Semester Test 2 (1) - Edited
Semester Test 2 (1) - Edited
SPECIAL REQUIREMENTS
NONE
NON-PROGRAMMABLE POCKET CALCULATOR
SCIENTIFIC CALCULATOR
COMPUTER ANSWER SHEET
GRAPH PAPER
DRAWING INSTRUMENTS
OPEN BOOK
OTHER:
TOTAL: 100
FULL MARKS: 100 Signature of Examiner Signature of Moderator Signature of Exam
Committee Chairperson
INITIALS: GROUP:__________
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DSA115D MAKEUP TEST 2023
Question 1 [30]
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DSA115D MAKEUP TEST 2023
1.10 The time interval between the 50% mark of the falling and rising edges of a pulse
amplitude is called the : (1)
(a) fall time
(b) period
(c) rise time
(d) pulse width
(e) frequency
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DSA115D MAKEUP TEST 2023
1.11 A certain pulse has Ton = 20ms and Toff = 10ms. The Duty cycle is ?
(1)
(a) 20%
(b) 33.33%
(c) 66.66%
(d) 66%
(e) None of the above
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DSA115D MAKEUP TEST 2023
1.15 Give the equation for F(A,B,C) of the following logic circuit. (1)
(a) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐹 = (𝐴𝐵 + 𝐶 + 𝐷)
̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(b) F = ̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅
AB(C ̅̅̅̅̅̅̅
+ D)
(c) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅ ̅̅̅̅̅̅̅
F = AB(C + D)
(d) ̅B
F = A ̅ + A
̅C ̅BC
̅ + AB
̅ ̅C + A B C
̅ + ABC
(e) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅ + 𝐴𝐶
𝐹 = (𝐴𝐵 ̅̅̅̅ )𝐶
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DSA115D MAKEUP TEST 2023
Marks
1.1 A B C D E 2
1.2 A B C D E 2
1.3 A B C D E 2
1.4 A B C D E 2
1.5 A B C D E 2
1.6 A B C D E 2
1.7 A B C D E 2
1.8 A B C D E 2
1.9 A B B D E 2
1.10 A B C D E 1
1.11 A B C D E 2
1.12 A B C D E 1
1.13 A B C D E 1
1.14 A B C D E 1
1.15 A B C D E 2
1.16 A B C D E 2
1.17 A B C D E 2
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DSA115D MAKEUP TEST 2023
Question 2 [18]
Write the answer (only equations) in the box next to the question.
2.4
̅̅̅̅̅̅̅
Simplify (A ̅̅̅̅̅̅̅
+ B)(B + C) (2)
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DSA115D MAKEUP TEST 2023
Question 3 [11]
Design a code converter according to the truth table given below:
INPUT OUTPUT
A B C X Y Z
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0
X= Y= Z=
3.3 Would it be possible to implement this converter using NOR gates only (1)
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DSA115D MAKEUP TEST 2023
Question 4 [14]
4.1 Illustrate how you will construct an 8:1 Multiplexer using only 2:1 multiplexers. (8)
4.2 Design a 4:1 multiplexer using only primary logic gates (6)
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DSA115D MAKEUP TEST 2023
Question 5 [10]
Design a system that will compare four 4-bit values and then display the largest value on 4
LED’s. Use a combination of multiplexers (2x4-bit channels) and magnitude comparators.
Question 6 [8]
Design a system that will ADD two 4-bit numbers. The SUM should be compared to the
value 10 and the largest of the two values (SUM or 10) should be displayed on 5 LEDs.
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DSA115D MAKEUP TEST 2023
Question 7 [9]
7.1 Show how you will display the value ‘59’ on 2 x 7 Segment common anode displays
using only one 7447 decoder. (6)
7.2 Cascade 2 x 1:2 line decoders in order to create a 2:4 line decoder (3)
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