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Semester Test 2 (1) - Edited

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Semester Test 2 (1) - Edited

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DSA115D MAKEUP TEST 2023

SUBJECT NAME: Digital Systems 1A


SUBJECT CODE: DSA115D
QUALIFICATION(S): DIPLOMA: Electrical Engineering
EXAMINER(S): Mr. TA MOKOENA
MODERATOR(S): Mr. O MORAPEDI
TOTAL MARKS: 100 TOTAL NUMBER OF PAGES INCLUDING COVER PAGE: 11
FULL MARKS: 100 TOTAL NUMBER OF ANNEXURES: 0
PAPER DESCRIPTION: A4 CLOSED BOOK DURATION: 2 hours

SPECIAL REQUIREMENTS
NONE
NON-PROGRAMMABLE POCKET CALCULATOR
SCIENTIFIC CALCULATOR
COMPUTER ANSWER SHEET
GRAPH PAPER
DRAWING INSTRUMENTS
OPEN BOOK
OTHER:

Question Type % Question Mark Question Mark


RECALL Q1 30 Q1
APPLICATION 100 Q2 18
INSIGHT Q3 11
TOTAL Q4 14
Q5 10
Q6 8
Q9 9

TOTAL: 100
FULL MARKS: 100 Signature of Examiner Signature of Moderator Signature of Exam
Committee Chairperson

SURNAME: STUDENT NUMBER:

INITIALS: GROUP:__________

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DSA115D MAKEUP TEST 2023

Question 1 [30]

Determine the value of X.

1.1 ((8010 + 11002)*410) / 102 = XOCTAL. (2)


(a) 108
(b) 2708
(c) 10BCD
(d) 82
(e) None of the above

1.2 (528 + 5210) / 5E16 = X16 (2)


(a) 138
(b) 2616
(c) 116
(d) 1316
(e) None of the above

1.3 (135910 / 316)* = X8 (2)


(a) None of the below
(b) 1BA516
(c) A9E8
(d) 52368
(e) 52638

1.4 Convert 101010011110BINARY to Gray and then to X16 (2)


(a) FDE16
(b) CBE16
(c) 635316
(d) 1C1216
(e) 110011012

1.5 Convert 1100110110111111GRAY to Binary (2)


(a) 10101010011001012
(b) 11011010101011002
(c) 00111101010011112
(d) 00101001100010102
(e) 10001001001010102

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DSA115D MAKEUP TEST 2023

1.6 Perform the following operation using 2’s compliment (2)


0*01112 – 1*10012
(a) 1*0111
(b) 1*0011
(c) 1*0010
(d) 0*0100
(e) 1*0110

1.7 1001,112 x 10,012 = X2 (5 decimal places) (2)


(a) 10001,000112
(b) 11010,110112
(c) 10011,010012
(d) 10101,111012
(e) None of the above

1.8 Convert 23,6562510 = X2 (2)


(a) 10111,101012
(b) 10111,110112
(c) 10111,111002
(d) 10111,010102
(e) 10111,110012

1.9 Calculate the period of a signal with a frequency of 2000Hz. (1)


(a) 1.5s
(b) 0,006125us
(c) 0,005s
(d) 0,5s
(e) 0.5ms

1.10 The time interval between the 50% mark of the falling and rising edges of a pulse
amplitude is called the : (1)
(a) fall time
(b) period
(c) rise time
(d) pulse width
(e) frequency

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DSA115D MAKEUP TEST 2023

1.11 A certain pulse has Ton = 20ms and Toff = 10ms. The Duty cycle is ?
(1)
(a) 20%
(b) 33.33%
(c) 66.66%
(d) 66%
(e) None of the above

1.12 A quantity having a continuous set of values is: (1)


(a) digital quantity
(b) natural quantity
(c) binary quantity
(d) analog quantity
(e) discreet quantity

1.13 𝑆𝑖𝑚𝑝𝑙𝑖𝑓𝑦 𝐹 = 𝑃̅ 𝑄̅ 𝑅 + 𝑃̅ 𝑄𝑅̅ + 𝑃𝑄̅ 𝑅 + 𝑃𝑄𝑅̅ (1)


(a) 𝑃̅. 𝑄̅ + 𝑃.
(b) ̅ + 𝑃. 𝑄
𝑃.
(c) 𝑄𝑅 + 𝑄̅ 𝑅̅
(d) 𝑄 + 𝑃𝑅+PQ
(e) 𝑄𝑅̅ + 𝑄̅ 𝑅

1.14 F(A,B,C) = π(0,1,5,7) is the same as: (1)


(a) F(A,B,C) = Σ(2,3,4,6)
(b) F(A,B,C) = Σ(1,2,5,7)
(c) F(A,B,C) = Σ(0,1,3,7)
(d) F(A,B,C) = π(1,2,4,5,6)
(e) none of the above

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DSA115D MAKEUP TEST 2023

1.15 Give the equation for F(A,B,C) of the following logic circuit. (1)

(a) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐹 = (𝐴𝐵 + 𝐶 + 𝐷)
̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(b) F = ̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅
AB(C ̅̅̅̅̅̅̅
+ D)
(c) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅ ̅̅̅̅̅̅̅
F = AB(C + D)
(d) ̅B
F = A ̅ + A
̅C ̅BC
̅ + AB
̅ ̅C + A B C
̅ + ABC

(e) ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅ + 𝐴𝐶
𝐹 = (𝐴𝐵 ̅̅̅̅ )𝐶

1.16 Determine the standard SOP for 𝐹(𝐴, 𝐵, 𝐶) = 𝐵 (2)


(a) 𝐹 = Σ(2,3,6,7)
(b) 𝐹 = Σ(2,6,7)
(c) 𝐹 = Σ(1,3,6,7)
(d) 𝐹 = Σ(1,2,3,6,7)
(e) None of the above

1.17 Determine the standard POS for 𝐹(𝐴, 𝐵, 𝐶) = 𝐶 (2)


(a) 𝐹 = Σ(1,3,5,7)
(b) 𝐹 = Π(0,3,4,6)
(c) 𝐹 = Π(0,2,5,6)
(d) 𝐹 = Π(0,2,4,6)
(e) 𝐹 = Σ(2,3,6,7)

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DSA115D MAKEUP TEST 2023

Answer sheet for Question 1

Please mark as follows: (a) X

Marks
1.1 A B C D E 2

1.2 A B C D E 2

1.3 A B C D E 2

1.4 A B C D E 2

1.5 A B C D E 2

1.6 A B C D E 2

1.7 A B C D E 2

1.8 A B C D E 2

1.9 A B B D E 2

1.10 A B C D E 1

1.11 A B C D E 2

1.12 A B C D E 1

1.13 A B C D E 1

1.14 A B C D E 1

1.15 A B C D E 2

1.16 A B C D E 2

1.17 A B C D E 2

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DSA115D MAKEUP TEST 2023

Question 2 [18]
Write the answer (only equations) in the box next to the question.

2.1 Determine from the Karnaugh map the


minimum SOP expression. (2)
AB \ CD
0 0 0 0
0 1 1 0
0 1 1 0
0 0 0 0
2.2 Determine from the truth table the minimum
POS. (2)
A B C F
0 0 0 0
0 1 0 0
1 0 0 0
1 1 0 0
2.3 Simplify F(A,B,C) = ∑(1,3,5,7) (2)

2.4
̅̅̅̅̅̅̅
Simplify (A ̅̅̅̅̅̅̅
+ B)(B + C) (2)

2.5 F = Π(0,1,2,3,4,5,6,8,9,10,12), determine the


output for F if A=1,B=1,C=0,D=1 (2)

2.6 Standard SOP of 𝐹(𝐴, 𝐵) = 𝐵 is: (2)

2.7 Determine the minimum POS expression: (2)


AB \ C
0 0
0 0
0 1
1 1
2.8 Realise 𝐹 = (𝐴)(𝐵̅ + 𝐶) with NOR-gates:
(2)
2.9 Realise 𝐹 = (𝐴̅𝐵 ) + (𝐴𝐵) with NAND-gates:
(2)

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DSA115D MAKEUP TEST 2023

Question 3 [11]
Design a code converter according to the truth table given below:
INPUT OUTPUT
A B C X Y Z
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0

3.1 Complete and simplify the K-MAPS (6)

X= Y= Z=

3.2 Draw the circuit diagram of the code converter (4)

3.3 Would it be possible to implement this converter using NOR gates only (1)

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DSA115D MAKEUP TEST 2023

Question 4 [14]
4.1 Illustrate how you will construct an 8:1 Multiplexer using only 2:1 multiplexers. (8)

4.2 Design a 4:1 multiplexer using only primary logic gates (6)

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DSA115D MAKEUP TEST 2023

Question 5 [10]
Design a system that will compare four 4-bit values and then display the largest value on 4
LED’s. Use a combination of multiplexers (2x4-bit channels) and magnitude comparators.

Question 6 [8]
Design a system that will ADD two 4-bit numbers. The SUM should be compared to the
value 10 and the largest of the two values (SUM or 10) should be displayed on 5 LEDs.

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DSA115D MAKEUP TEST 2023

Question 7 [9]
7.1 Show how you will display the value ‘59’ on 2 x 7 Segment common anode displays
using only one 7447 decoder. (6)

7.2 Cascade 2 x 1:2 line decoders in order to create a 2:4 line decoder (3)

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