BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI

WORK INTEGRATED LEARNING PROGRAMMES

COURSE HANDOUT

Part A: Content Design

Course Title DIGITAL DESIGN

Course No(s) CSF 214
Credit Units 4
Course Author Dr. Lucy J Gudino
Version No 1.0
Date Nov 9, 2018

Course Objective

No Course Objective

CO1 To cover the basics of digital logic circuits and design, beginning with the basic
understanding of Boolean Algebra and Number systems

CO2 To enable the understanding of the logical operation and design of basic combinational and
sequential building blocks, Programmable logic devices, and other circuits needed to build
complex digital systems.

Text Book(s)
T1 Mano, M. Morris, Michael D. Ciletti, Digital Design, Pearson Education, 5th Edition.
T2 R P Jain, Modern Digital Electronics, Mc GrawHill, 4Th Edition

Reference Book(s) & other resources

R1 Ronald J. Tocci, Digital Systems: Principles and Applications, 10th Ed, Pearson
Education
R2 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture
(Books24X7)
R3 A. Saha and N. Manna, Digital Principles and Logic Design (Books24X7)
Modular Content Structure
1. Digital Systems and Numbering systems
1.1 Introduction to Digital systems and number systems
1.2 Binary Numbers
1.3 Number base Conversion
1.3.1 Decimal, Binary, Octal, hexadecimal Number base conversion.
1.4 Complements of Numbers
1.5 Signed Binary Numbers
1.5.1 Sign Magnitude representation
1.5.2 1’s Complement representation
1.5.3 2’s Complement representation
1.6 Binary Codes
1.7 Binary logic
2. Boolean Algebra and Logic Gates
2.1 Basic Theorems and Properties of Boolean Algebra
2.2 Boolean Functions
2.3 Canonical and Standard Forms
2.4 Digital Logic Gates
3. Digital Logic Families
3.1 Characteristics of Digital ICs
3.2 Resistor Transistor Logic
3.3 Diode Transistor Logic
3.4 Transistor-Transistor Logic, 5400/7400 TTL series
3.5 Emitter Coupled Logic
3.6 MOS Logic
3.7 CMOS Logic
3.8 Tristate Logic
4. Gate Level Minimization
4.1 Introduction
4.2 The K- Map Method: Two, Three, Four, Five and Six Variable
4.3 Quine – McCluskey Minimization Technique
4.4 SOP/POS Simplification
4.5 Don’t Care Conditions
4.6 NAND and NOR Implementations
5. Combinational Logic
5.1 Introduction to Combinational Circuits
5.2 Analysis and Design procedure
5.3 Binary Adder – Subtractor
5.4 Decimal Adder
5.4.1 BCD Adder
5.5 Binary Multiplier
5.6 Magnitude Comparator
5.7 Decoders
5.8 Encoders
5.9 Multiplexers
5.10 De-Multiplexers
6. Synchronous Sequential Circuits
6.1 Introduction to sequential circuits
6.2 Storage Elements: Latches and Flip-flops
6.2.1 SR Flip Flop
6.2.2 JK Flip Flop
6.2.3 D Flip Flop
6.2.4 T Flip Flop
6.2.5 Master –Slave Flip Flop
6.2.6 Characteristic tables and equations of flip flops
 6.3 Analysis of Clocked Sequential Circuits
6.4 State Reduction
7. Registers and Counters
7.1 Registers
7.2 Shift Registers
7.3 Ripple Counters
7.4 Synchronous Counters
7.5 Design of Mod n counter
7.6 Other counters

8. Memory and Programmable Logic

8.1 Random Access Memory
8.2 Memory Decoding
8.3 Error Detection and Correction
8.4 Read Only Memory
8.5 Programmable Logic Array
8.6 Programmable Array Logic
8.7 Sequential Programmable Devices

9. A/D and D/A Converters

9.1 Digital to Analog Converters
9.2 An example of D/A Converter IC
9.3 Sample and Hold
9.4 Analog to Digital Converter
9.5 An example of A/D Converter IC

Learning Outcomes:

No Learning Outcomes

LO1 An ability to infer number systems, Boolean algebra and minimize logic function using K-
map method.

LO2 Ability to analyze and design combinational logic networks in a hierarchical, modular
approach, using standard and custom logic blocks.

LO3 Ability to analyze and design basic synchronous sequential machines using various memory
elements.

LO4 Ability to describe different types of programmable logic devices

LO5 Ability to identify basic requirements for a design application and propose a cost effective
solution
 Part B: Contact Session Plan

Academic Term
Course Title Digital Electronics
Course No
Lead Instructor

Course Contents

Contact List of Topic Title Topic # Text/Ref

Hour (from content structure in Part A) (from Book/external
content resource
structure in
Part A)

1-2 Digital Systems and Numbering Systems: 1.1- 1.4 T1 – Chapter 1

Digital systems, Binary Numbers, Number base [1.1 – 1.5]
Conversion: Decimal, Binary, Octal,
hexadecimal Number, Complements

3-4 Digital Systems and Numbering Systems: 1.5-1.7 T1 – Chapter

Signed Binary Numbers, Binary codes, Binary 1[1.6-1.9]
Storage and registers, and Binary Logic

5-6 Boolean Algebra and Logic Gates: Basic 2.1-2.4 T1- Chapter 2
Theorems and Properties of Boolean Algebra, [2.1-2.8]
Boolean Functions, Canonical and Standard
Forms, Digital Logic Gates

7-8 Digital Logic Families: Characteristics of 3.1-3.4 T2 – Chapter

Digital ICs, Resistor Transistor Logic, Diode 4[4.1-4.3, 4.8,
Transistor Logic, Transistor -Transistor Logic, 4.10]
5400/7400 TTL series,

9-10 Digital Logic Families: Emitter Coupled Logic, 3.5-3.8 T2 – Chapter 4

MOS Logic, CMOS Logic, Tristate Logic [4.11, 4.13,4.14,
4.20]
Gate Level Minimization: Introduction, The 4.1-4.2
Map Method-Two, Three and Four Variable T1 – Chapter 3
Map [3.1-3.3]

11-12 Gate Level Minimization: Five and Six 4.2-4.5 T1- Chapter
Variable, Quine – McCluskey Minimization 3[3.4-3.5]
Technique, Product of Sums Simplification, T2 – Chapter 5
Don’t Care Conditions,

13-14 Gate Level Minimization: NAND and NOR 4.6 T1 - - Chapter

Implementations. 5.1-5.3 3[3.6],
Combinational Circuits: Introduction, Analysis Chapter 4 [4.1-
and Design procedure, Binary Adder – 4.5]
Subtractor
 15 -16 Combinational Logic : Decimal Adder, Binary 5.4-5.6 T1 – Chapter 4
Multiplier, Magnitude Comparator [4.6-4.8]
Revision

17-18 Combinational Logic : Decoders, Encoders, 5.7-5.10 T1 – Chapter 4

Multiplexor, Demultiplexor [4.9 – 4.11]

19-20 Synchronous Sequential Circuits: Introduction to 6.1-6.2.3 T1 – Chapter 5

sequential circuits, Combinational Logic Vs Sequential [5.1-5.4]
Logic, Storage Elements: SR Latch, SR Flip Flop, J K
Flip Flop, D Flip Flop

21-22 Synchronous Sequential Circuits: Storage 6.2.4-6.4 T1 – Chapter 5

Elements-T Flip Flop, Master Slave Flip Flop, [5.4, 5.5, 5.7]
Characteristic tables and equations of flip flops,
Analysis of Clocked Sequential Circuits, State
Reduction

23-24 Registers and Counters: Registers, Shift 7.1-7.4 T1 – Chapter 6

Registers, Ripple Counter, Synchronous [6.1-6.4]
Counters

25-26 Registers and Counters: Up Down Counter, 7.5-7.6 T1 – Chapter 6

Design of Mod n counter, Other Counters [6.4]

27-28 Memory And Programmable Logic: Random 8.1-8.4 T1 – Chapter 7

Access Memory, Memory Decoding, Error [7.1-7.5]
Detection and Correction, Read Only Memory,

29-30 Memory And Programmable Logic : Programmable 8.5-8.7 T1 – Chapter 7

Logic Array, Programmable Array Logic, Sequential [7.6-7.9]
Programmable Devices
A/D and D/A Converters: Digital to Analog 9.1-9.3 T2 – Chapter 10
Converters, An example of D/A Converter IC [10.1-10.4]
Sample and Hold

31-32 A/D and D/A Converters: Analog to Digital 9.4-9.5 T2 – Chapter 10

Converters, An example of A/D Converter IC [10.5-10.6]
Revision

Detailed Plan for Lab work/Design work:

● Infrastructure Needed:

▪ Simulation software Multisim for Digital Electronics

● Lab Sessions required: 4 sessions.

Lab Lab Objective Lab Sheet Access URL Content

No Reference
 1 Realization of all Basic gates using Universal Gates Platify Virtual Lab Lab Sheets
(Both NAND and NOR) using multisim.

2 Simplification , Realization of Boolean Expressions by Platify Virtual Lab Lab Sheets

using Logic gates/Universal Gates using multisim.

3 Design of combinational circuit using Platify Virtual Lab Lab Sheets

multisim(Adder/Subtractor/comparator/MUX/DEMUX)

4 Design of MOD N counter (synchronos/Asynchronous) Platify Virtual Lab Lab Sheets

using IC 7476 using multisim.

Evaluation Scheme
Evaluation Name Type Weight Duration Day, Date,
Component Session, Time

EC - 1 Quiz/ Assignment 30% To be announced

EC - 2 Mid-Semester Test Closed Book 30% 2 hrs To be announced

EC - 3 Comprehensive Exam Open Book 40% 3 hrs To be announced

Note - Evaluation components can be tailored depending on the proposed model.

Important Information
Syllabus for Mid-Semester Test (Closed Book): Topics in Weeks 1-8
Syllabus for Comprehensive Exam (Open Book): All topics given in plan of study

Evaluation Guidelines:
1. EC-1 consists of either two Assignments or three Quizzes. Announcements regarding the
same will be made in a timely manner.
2. For Closed Book tests: No books or reference material of any kind will be permitted.
Laptops/Mobiles of any kind are not allowed. Exchange of any material is not allowed.
3. For Open Book exams: Use of prescribed and reference text books, in original (not
photocopies) is permitted. Class notes/slides as reference material in filed or bound form is
permitted. However, loose sheets of paper will not be allowed. Use of calculators is permitted
in all exams. Laptops/Mobiles of any kind are not allowed. Exchange of any material is not
allowed.
4. If a student is unable to appear for the Regular Test/Exam due to genuine exigencies, the
student should follow the procedure to apply for the Make-Up Test/Exam. The genuineness of
the reason for absence in the Regular Exam shall be assessed prior to giving permission to
appear for the Make-up Exam. Make-Up Test/Exam will be conducted only at selected exam
centre on the dates to be announced later.
It shall be the responsibility of the individual student to be regular in maintaining the self-study
schedule as given in the course handout, attend the lectures, and take all the prescribed evaluation
components such as Assignment/Quiz, Mid-Semester Test and Comprehensive Exam according to the
evaluation scheme provided in the handout.