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Be - Computer Engineering - Semester 3 - 2023 - May - Digital Electronics and Logic Design Deld Pattern 2019

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Komal Rathod
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0% found this document useful (0 votes)
21 views

Be - Computer Engineering - Semester 3 - 2023 - May - Digital Electronics and Logic Design Deld Pattern 2019

Uploaded by

Komal Rathod
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

Total No. of Questions : 8] SEAT No.

8
23
P-1530 [Total No. of Pages : 3

ic-
[6002]-159

tat
8s
S.E. (Computer Engineering)

7:3
02 91
DIGITAL ELECTRONICS AND LOGIC DESIGN

0:3
0
(2019 Pattern) (Semester - III) (210245)

31
Time : 2½ Hours] 0/0 13 [Max. Marks : 70
0

om
6/2
Instructions to the candidates:
.23 GP

1) Attempt Q1 or Q2, Q3 or Q4, Q5 or Q6, Q7 or Q8,


E

2) Neat diagram must be drawn wherever necessary.


82

rsic-238
.c
C

3) Assume suitable data jf necessary.


16

tat
8.2

es
Q1) a) Distinguish between combinational and sequential switching circuits also

:38
.24

write examples of both. :37p [6]


02P 91
49

0a
b) Convert Following Flip flops: [6]
0
31
0/0 n13

i) SR to T
P0
6/2

ii) JK to D
8 2 io
.23 tG

c) What is MOD counter ? Design MOD 7 counter using IC 7490. [6]


CE
s

38
OR
ue

Q2) a) Draw and explain 3-bit asynchronous up-counter using JK flip flop. Also
c-2
i
16

tat
draw the necessary timing diagram. [6]
Q
8.2

8s
.24

7:3

b) What do you mean by excitation table of flip flop? Write the excitation
PU

91
49

0:3

table of [6]
30
31

i) S-R flip flop


SP

01
02

ii) J-K flip flop


6/2
GP

c) With neat diagrams explain the working of the following types of shift
0/0

registers [6]
CE
82

i) Serial-in, serial-out
.23
16

ii) Parallel-in, serial-out


8.2
.24

P.T.O.
49
Q3) a) Draw the state diagram, state table, and ASM chart for a 2-bit binary

8
23
counter having one enable line E such that E = l counting enabled,and E = 0

ic-
counting disabled. [6]

tat
b) Implement following Boolean function using PAL [6]

8s
Fl = Σm (0,2,4,6,8,12)

7:3
02 91
0:3
F2 = Σm (2,3,8,9,12,13)

0
31
F3 = Σm (l,3,4,6,9,11,12,14,15)
0/0 13
0
c) Draw a block diagram of the PLA device and explain. [5]

om
6/2
.23 GP

OR
E
82

rsic-238
.c
Q4) a) What is an ASM Chart? Name the elements of an ASM chart and define
C

each of them. [6]


16

tat
b) Implement BCD to Excess-3 code converter using PAL. [6]
8.2

es
c) What is the difference between PAL and PLA. [5]

:38
.24

:37p
02P 91
49

0a
Q5) a) With the help of a neat diagram, explain the working of two-input TTL
0
31

NAND gate. [6]


0/0 n13
P0

b) Draw and explain the circuit diagram of CMOS inverter. [6]


6/2
8 2 io
.23 tG

c) Define the following terms and mention the standard values for TTL logic
CE
s

Family [6]

38
ue

c-2
i) Fan-out
i
16

tat
Q
8.2

ii) Power Dissipation


8s
.24

7:3
PU

iii) Propagation Delay.


91
49

0:3
30

OR
31
SP

01
02

Q6) a) What is the advantage of open collector output? Justify your answer with
6/2

suitable circuit. [6]


GP
0/0

b) Compare TTL and CMOS logic family. [6]


CE
82

c) What is logic family? Give the classification of logic family and also write
.23

important characteristics of .CMOS. [6]


16
8.2
.24

[6002]-159 2
49
Q7) a) Draw and explain the basic building of an ideal microprocessor based

8
23
system with the help of neat diagram. [6]

ic-
tat
b) What is system bus? Draw microprocessor bus structure and explain in

8s
brief. [6]

7:3
02 91
0:3
c) Write a short note on ALU IC 74181. [5]

0
31
0/0 13 OR
0

om
6/2
.23 GP

Q8) a) With the help of a block diagram explain the fundamental units of a
microprocessor. [6]
E
82

rsic-238
.c
C

b) Explain the Memory organization of the microprocessor. [6]


16

tat
c) What is microprocessor? List different applications of microprocessor.[5]
8.2

es
:38
.24

:37p
02P 91
49

0a

0
31
0/0 n13
P0
6/2
8 2 io
.23 tG
CE
s

38
ue

c-2
i
16

tat
Q
8.2

8s
.24

7:3
PU

91
49

0:3
30
31
SP

01
02
6/2
GP
0/0
CE
82
.23
16
8.2
.24

[6002]-159 3
49

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