8 Series Chipset PCH Datasheet
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coldspider7401098 Series Chipset PCH Datasheet
Uploaded by
coldspider740109Intel® 8 Series / C220 Series Chipset
Family Platform Controller Hub
(PCH)
Datasheet
June 2013
328904-001
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2 Datasheet
Contents
1 Introduction ............................................................................................................ 43
1.1 About This Manual ............................................................................................. 43
1.1.1 Chapter Descriptions ............................................................................. 44
1.2 Overview ......................................................................................................... 46
1.2.1 Capability Overview............................................................................... 47
1.3 Intel® 8 Series / C220 Series Chipset Family SKU Definition.................................... 54
1.4 Device and Revision ID Table .............................................................................. 60
2 Signal Description ................................................................................................... 63
2.1 Flexible I/O ...................................................................................................... 65
2.2 USB Interface ................................................................................................... 66
2.3 PCI Express* .................................................................................................... 70
2.4 Serial ATA Interface........................................................................................... 72
2.5 Clock Signals .................................................................................................... 75
2.6 Real Time Clock Interface ................................................................................... 77
2.7 External RTC Circuitry ........................................................................................ 77
2.8 Interrupt Interface ............................................................................................ 78
2.9 Processor Interface............................................................................................ 78
2.10 Direct Media Interface (DMI) to Host Controller ..................................................... 79
2.11 Intel® Flexible Display Interface (Intel® FDI) ........................................................ 79
2.12 Analog Display / VGA DAC Signals ....................................................................... 80
2.13 Digital Display Signals........................................................................................ 81
2.14 Embedded DisplayPort* (eDP*) Backlight Control Signals ....................................... 81
2.15 Intel® High Definition Audio (Intel® HD Audio) Link ............................................... 82
2.16 Low Pin Count (LPC) Interface............................................................................. 83
2.17 General Purpose I/O Signals ............................................................................... 83
2.18 Functional Straps .............................................................................................. 91
2.19 SMBus Interface................................................................................................ 95
2.20 System Management Interface............................................................................ 95
2.21 Controller Link .................................................................................................. 96
2.22 Serial Peripheral Interface (SPI) .......................................................................... 96
2.23 Manageability Signals ........................................................................................ 98
2.24 Power Management Interface.............................................................................. 99
2.25 Power and Ground Signals ................................................................................ 103
2.26 Thermal Signals .............................................................................................. 104
2.27 Miscellaneous Signals ...................................................................................... 105
2.28 Testability Signals ........................................................................................... 106
2.29 Reserved / Test Pins ........................................................................................ 107
3 PCH Pin States....................................................................................................... 109
3.1 Integrated Pull-Ups and Pull-Downs ................................................................... 109
3.2 Output Signals Planes and States ...................................................................... 112
3.3 Input and I/O Signals Planes and States............................................................. 118
4 PCH and System Clocks ......................................................................................... 125
4.1 Straps Related to Clock Configuration ................................................................ 125
4.2 Platform Clocking Requirements ........................................................................ 126
4.3 Functional Blocks ............................................................................................ 127
4.4 Clock Configuration Access Overview ................................................................. 130
4.5 Integrated Clock Controller (ICC) Registers......................................................... 130
4.5.1 ICC Registers under Intel® Management Engine (Intel® ME) Control.......... 130
4.5.1.1 SSCDIVINTPHASE_DMI100—100MHz DMI Clock SSC Divider
Integer Phase Control Register................................................ 131
4.5.1.2 SSCTRIPARAM_DMI100—100MHz DMI Clock SSC Triangle
Register............................................................................... 131
4.5.1.3 SSCCTL_DMI100—100MHz DMI Clock SSC Control Register ........ 131
4.5.1.4 SSCDIVINTPHASE_PCHPCIE100—100MHz PCH PCIE Clock SSC
Divider Integer Phase Register................................................ 132
4.5.1.5 SSCTRIPARAM_PCHPCIE100—100MHz PCH PCIE Clock SSC
Triangle Register................................................................... 132
4.5.1.6 SSCCTL_PCHPCIE100—100MHz PCH PCIE* Clock SSC Control
Register............................................................................... 132
Datasheet 3
4.5.1.7 DIV_PCI33—33MHz Single Ended Clock Divide and Spread
Enable Register ..................................................................... 132
4.5.1.8 DIV_FLEX4824—48MHz and 24MHz Single Ended FLEX Clock
Divide Enable Register ........................................................... 133
4.5.1.9 OCKEN—Output Clock Enable Register...................................... 134
4.5.1.10 SEFLXBP—Single Ended Flex Buffer Parameter Register .............. 136
4.5.1.11 SEPCICLKBP—Single Ended 33 MHz Clock Buffer
Parameter Register ................................................................ 137
4.5.1.12 DCOSS—Differential Clock Out Source Select Register ................ 138
4.5.1.13 SECOSS—Single Ended Clock Out Source Select Register ............ 139
4.5.1.14 MCSS—Miscellaneous Clock Source Select Register .................... 140
4.5.1.15 PLLRCS—PLL Reference Clock Select Register ............................ 140
4.5.1.16 ICCCTL—ICC Control Register ................................................. 140
4.5.1.17 PMPCI—33MHz Single Ended Clock Power Management Register .. 141
4.5.1.18 PM1PCIECLK—Power Management 1 PCIE Clock Register ............ 142
4.5.1.19 PM2PCIECLK—Power Management 2 PCIE Clock Register ............ 145
5 Functional Description ........................................................................................... 149
5.1 Flexible I/O..................................................................................................... 149
5.2 PCI-to-PCI Bridge ............................................................................................ 150
5.2.1 PCI Bus Interface ................................................................................ 150
5.2.2 PCI Legacy Mode ................................................................................. 150
5.3 PCI Express* Root Ports (D28:F0~F7) ................................................................ 151
5.3.1 Supported PCIe* Port Configurations...................................................... 151
5.3.2 Interrupt Generation ............................................................................ 151
5.3.3 Power Management ............................................................................. 152
5.3.3.1 S3/S4/S5 Support ................................................................. 152
5.3.3.2 Resuming from Suspended State ............................................. 152
5.3.3.3 Device Initiated PM_PME Message............................................ 152
5.3.3.4 SMI/SCI Generation............................................................... 153
5.3.3.5 Latency Tolerance Reporting (LTR) .......................................... 153
5.3.3.6 Opportunistic Buffer Flush/Fill (OBFF)....................................... 153
5.3.4 SERR# Generation............................................................................... 153
5.3.5 Hot-Plug............................................................................................. 154
5.3.5.1 Presence Detection ................................................................ 154
5.3.5.2 Message Generation .............................................................. 154
5.3.5.3 Attention Button Detection...................................................... 155
5.3.5.4 SMI/SCI Generation............................................................... 155
5.4 Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 156
5.4.1 GbE PCI Express* Bus Interface ............................................................ 159
5.4.1.1 Transaction Layer .................................................................. 159
5.4.1.2 Data Alignment ..................................................................... 159
5.4.1.3 Configuration Request Retry Status.......................................... 159
5.4.2 Error Events and Error Reporting ........................................................... 159
5.4.2.1 Data Parity Error ................................................................... 159
5.4.2.2 Completion with Unsuccessful Completion Status ....................... 160
5.4.3 Ethernet Interface ............................................................................... 160
5.4.3.1 Intel® Ethernet Network Connection I127LM/V Platform LAN
Connect Device Interface........................................................ 160
5.4.4 PCI Power Management........................................................................ 161
5.4.4.1 Wake Up .............................................................................. 161
5.4.5 Configurable LEDs ............................................................................... 163
5.4.6 Function Level Reset Support (FLR)........................................................ 164
5.4.6.1 FLR Steps............................................................................. 164
5.5 Low Pin Count (LPC) Bridge (with System and
Management Functions) (D31:F0) ...................................................................... 165
5.5.1 LPC Interface ...................................................................................... 165
5.5.1.1 LPC Cycle Types .................................................................... 165
5.5.1.2 Start Field Definition .............................................................. 166
5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR) ................................... 166
5.5.1.4 Size..................................................................................... 167
5.5.1.5 SYNC ................................................................................... 167
5.5.1.6 SYNC Time-Out ..................................................................... 167
5.5.1.7 SYNC Error Indication ............................................................ 168
5.5.1.8 LFRAME# Usage .................................................................... 168
5.5.1.9 I/O Cycles ............................................................................ 168
5.5.1.10 Bus Master Cycles ................................................................. 168
4 Datasheet
5.5.1.11 LPC Power Management......................................................... 168
5.5.1.12 Configuration and PCH Implications ......................................... 169
5.6 DMA Operation (D31:F0) .................................................................................. 170
5.6.1 Channel Priority .................................................................................. 170
5.6.1.1 Fixed Priority ........................................................................ 170
5.6.1.2 Rotating Priority.................................................................... 171
5.6.2 Address Compatibility Mode.................................................................. 171
5.6.3 Summary of DMA Transfer Sizes ........................................................... 171
5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count
by Words ............................................................................. 171
5.6.4 Autoinitialize ...................................................................................... 172
5.6.5 Software Commands ........................................................................... 172
5.7 Low Pin Count (LPC) DMA ................................................................................. 173
5.7.1 Asserting DMA Requests ...................................................................... 173
5.7.2 Abandoning DMA Requests ................................................................... 174
5.7.3 General Flow of DMA Transfers ............................................................. 174
5.7.4 Terminal Count ................................................................................... 174
5.7.5 Verify Mode........................................................................................ 175
5.7.6 DMA Request De-assertion ................................................................... 175
5.7.7 SYNC Field / LDRQ# Rules.................................................................... 176
5.8 8254 Timers (D31:F0) ..................................................................................... 176
5.8.1 Timer Programming............................................................................. 177
5.8.2 Reading from the Interval Timer ........................................................... 178
5.8.2.1 Simple Read......................................................................... 178
5.8.2.2 Counter Latch Command........................................................ 178
5.8.2.3 Read Back Command............................................................. 178
5.9 8259 Programmable Interrupt Controllers (PIC) (D31:F0) ..................................... 179
5.9.1 Interrupt Handling............................................................................... 180
5.9.1.1 Generating Interrupts ............................................................ 180
5.9.1.2 Acknowledging Interrupts....................................................... 181
5.9.1.3 Hardware/Software Interrupt Sequence ................................... 181
5.9.2 Initialization Command Words (ICWx).................................................... 182
5.9.2.1 ICW1 .................................................................................. 182
5.9.2.2 ICW2 .................................................................................. 182
5.9.2.3 ICW3 .................................................................................. 182
5.9.2.4 ICW4 .................................................................................. 182
5.9.3 Operation Command Words (OCW)........................................................ 183
5.9.4 Modes of Operation ............................................................................. 183
5.9.4.1 Fully Nested Mode................................................................. 183
5.9.4.2 Special Fully-Nested Mode...................................................... 183
5.9.4.3 Automatic Rotation Mode (Equal Priority Devices)...................... 183
5.9.4.4 Specific Rotation Mode (Specific Priority).................................. 184
5.9.4.5 Poll Mode ............................................................................. 184
5.9.4.6 Edge and Level Triggered Mode............................................... 184
5.9.4.7 End of Interrupt (EOI) Operations ........................................... 184
5.9.4.8 Normal End of Interrupt ......................................................... 184
5.9.4.9 Automatic End of Interrupt Mode............................................. 185
5.9.5 Masking Interrupts .............................................................................. 185
5.9.5.1 Masking on an Individual Interrupt Request .............................. 185
5.9.5.2 Special Mask Mode ................................................................ 185
5.9.6 Steering PCI Interrupts ........................................................................ 185
5.10 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 186
5.10.1 Interrupt Handling............................................................................... 186
5.10.2 Interrupt Mapping ............................................................................... 186
5.10.3 PCI / PCI Express* Message-Based Interrupts......................................... 187
5.10.4 IOxAPIC Address Remapping ................................................................ 187
5.10.5 External Interrupt Controller Support..................................................... 187
5.11 Serial Interrupt (D31:F0) ................................................................................. 188
5.11.1 Start Frame........................................................................................ 188
5.11.2 Data Frames ...................................................................................... 189
5.11.3 Stop Frame ........................................................................................ 189
5.11.4 Specific Interrupts Not Supported Using SERIRQ ..................................... 189
5.11.5 Data Frame Format ............................................................................. 190
5.12 Real Time Clock (D31:F0)................................................................................. 191
5.12.1 Update Cycles..................................................................................... 191
5.12.2 Interrupts .......................................................................................... 192
5.12.3 Lockable RAM Ranges .......................................................................... 192
Datasheet 5
5.12.4 Century Rollover ................................................................................. 192
5.12.5 Clearing Battery-Backed RTC RAM ......................................................... 192
5.13 Processor Interface (D31:F0) ............................................................................ 194
5.13.1 Processor Interface Signals and VLW Messages........................................ 194
5.13.1.1 INIT (Initialization) ................................................................ 194
5.13.1.2 FERR# (Numeric Coprocessor Error) ........................................ 195
5.13.1.3 NMI (Non-Maskable Interrupt)................................................. 195
5.13.1.4 Processor Power Good (PROCPWRGD) ...................................... 195
5.13.2 Dual-Processor Issues .......................................................................... 195
5.13.2.1 Usage Differences.................................................................. 195
5.13.3 Virtual Legacy Wire (VLW) Messages ...................................................... 196
5.14 Power Management.......................................................................................... 196
5.14.1 Features............................................................................................. 196
5.14.2 PCH and System Power States .............................................................. 197
5.14.3 System Power Planes ........................................................................... 199
5.14.4 SMI# / SCI Generation......................................................................... 199
5.14.4.1 PCI Express* SCI .................................................................. 203
5.14.4.2 PCI Express* Hot-Plug ........................................................... 203
5.14.5 C-States............................................................................................. 203
5.14.6 Dynamic 33 MHz Clock Control (Mobile Only) .......................................... 203
5.14.6.1 Conditions for Checking the 33 MHz Clock................................. 203
5.14.6.2 Conditions for Maintaining the 33MHz Clock .............................. 204
5.14.6.3 Conditions for Stopping the 33MHz Clock .................................. 204
5.14.6.4 Conditions for Re-Starting the 33MHz Clock .............................. 204
5.14.6.5 LPC Devices and CLKRUN# ..................................................... 204
5.14.7 Sleep States ....................................................................................... 204
5.14.7.1 Sleep State Overview............................................................. 204
5.14.7.2 Initiating Sleep State ............................................................. 205
5.14.7.3 Exiting Sleep States............................................................... 205
5.14.7.4 PCI Express* WAKE# Signal and PME Event Message ................. 207
5.14.7.5 Sx-G3-Sx, Handling Power Failures .......................................... 208
5.14.7.6 Deep Sx ............................................................................... 208
5.14.8 Event Input Signals and Their Usage ...................................................... 210
5.14.8.1 PWRBTN# (Power Button) ...................................................... 210
5.14.8.2 RI# (Ring Indicator) .............................................................. 212
5.14.8.3 PME# (PCI Power Management Event) ..................................... 212
5.14.8.4 SYS_RESET# Signal............................................................... 212
5.14.8.5 THRMTRIP# Signal ................................................................ 212
5.14.9 ALT Access Mode ................................................................................. 213
5.14.9.1 Write Only Registers with Read Paths in ALT Access Mode ........... 214
5.14.9.2 PIC Reserved Bits .................................................................. 216
5.14.9.3 Read Only Registers with Write Paths in ALT Access Mode ........... 216
5.14.10 System Power Supplies, Planes, and Signals ........................................... 217
5.14.10.1 Power Plane Control with SLP_S3#,
SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN#............................. 217
5.14.10.2 SLP_S4# and Suspend-To-RAM Sequencing .............................. 217
5.14.10.3 PWROK Signal....................................................................... 217
5.14.10.4 BATLOW# (Battery Low) (Mobile Only) ..................................... 218
5.14.10.5 SLP_LAN# Pin Behavior.......................................................... 218
5.14.10.6 SLP_WLAN# Pin Behavior ....................................................... 220
5.14.10.7 SUSPWRDNACK / SUSWARN# / GPIO30 Steady State Pin
Behavior .............................................................................. 220
5.14.10.8 RTCRST# and SRTCRST# ....................................................... 220
5.14.11 Legacy Power Management Theory of Operation ...................................... 221
5.14.11.1 APM Power Management (Desktop Only) .................................. 221
5.14.11.2 Mobile APM Power Management (Mobile Only) ........................... 221
5.14.12 Reset Behavior.................................................................................... 221
5.15 System Management (D31:F0) .......................................................................... 224
5.15.1 Theory of Operation ............................................................................. 224
5.15.1.1 Detecting a System Lockup..................................................... 224
5.15.1.2 Handling an Intruder.............................................................. 224
5.15.1.3 Detecting Improper Flash Programming.................................... 225
5.15.1.4 Heartbeat and Event Reporting using SMLink/SMBus .................. 225
5.15.2 TCO Modes ......................................................................................... 226
5.15.2.1 TCO Legacy / Compatible Mode ............................................... 226
5.15.2.2 Advanced TCO Mode .............................................................. 227
5.16 General Purpose I/O (D31:F0) ........................................................................... 228
6 Datasheet
5.16.1 Power Wells ....................................................................................... 228
5.16.2 SMI# SCI and NMI Routing .................................................................. 228
5.16.3 Triggering .......................................................................................... 228
5.16.4 GPIO Registers Lockdown..................................................................... 228
5.16.5 Serial POST Codes over GPIO ............................................................... 229
5.16.5.1 Theory of Operation .............................................................. 229
5.16.5.2 Serial Message Format........................................................... 230
5.17 SATA Host Controller (D31:F2, F5) .................................................................... 232
5.17.1 SATA 6 Gb/s Support........................................................................... 232
5.17.2 SATA Feature Support ......................................................................... 232
5.17.3 Theory of Operation ............................................................................ 233
5.17.3.1 Standard ATA Emulation ........................................................ 233
5.17.3.2 48-Bit LBA Operation............................................................. 233
5.17.4 SATA Swap Bay Support ...................................................................... 234
5.17.5 Hot-Plug Operation.............................................................................. 234
5.17.6 Function Level Reset Support (FLR) ....................................................... 234
5.17.6.1 FLR Steps ............................................................................ 234
5.17.7 Intel® Rapid Storage Technology (Intel RST®) Configuration .................... 235
5.17.7.1 Intel® Rapid Storage Technology (Intel® RST) RAID
Option ROM.......................................................................... 235
5.17.8 Intel® Smart Response Technology ....................................................... 236
5.17.9 Power Management Operation .............................................................. 236
5.17.9.1 Power State Mappings ........................................................... 236
5.17.9.2 Power State Transitions ......................................................... 237
5.17.9.3 SMI Trapping (APM) .............................................................. 237
5.17.10 SATA Device Presence ......................................................................... 238
5.17.11 SATA LED .......................................................................................... 238
5.17.12 AHCI Operation................................................................................... 238
5.17.13 SGPIO Signals .................................................................................... 239
5.17.13.1 Mechanism........................................................................... 239
5.17.13.2 Message Format ................................................................... 240
5.17.13.3 LED Message Type ................................................................ 241
5.17.13.4 SGPIO Waveform .................................................................. 242
5.17.14 External SATA .................................................................................... 243
5.18 High Precision Event Timers (HPET) ................................................................... 243
5.18.1 Timer Accuracy ................................................................................... 243
5.18.2 Interrupt Mapping ............................................................................... 244
5.18.3 Periodic versus Non-Periodic Modes ....................................................... 245
5.18.4 Enabling the Timers............................................................................. 245
5.18.5 Interrupt Levels .................................................................................. 245
5.18.6 Handling Interrupts ............................................................................. 246
5.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors............................. 246
5.19 USB EHCI Host Controllers (D29:F0 and D26:F0)................................................. 247
5.19.1 EHC Initialization ................................................................................ 247
5.19.1.1 BIOS Initialization ................................................................. 247
5.19.1.2 Driver Initialization................................................................ 247
5.19.1.3 EHC Resets .......................................................................... 247
5.19.2 Data Structures in Main Memory ........................................................... 247
5.19.3 USB 2.0 Enhanced Host Controller DMA ................................................. 248
5.19.4 Data Encoding and Bit Stuffing.............................................................. 248
5.19.5 Packet Formats ................................................................................... 248
5.19.6 USB 2.0 Interrupts and Error Conditions................................................. 248
5.19.6.1 Aborts on USB 2.0-Initiated Memory Reads .............................. 249
5.19.7 USB 2.0 Power Management................................................................. 249
5.19.7.1 Pause Feature ...................................................................... 249
5.19.7.2 Suspend Feature................................................................... 249
5.19.7.3 ACPI Device States................................................................ 249
5.19.7.4 ACPI System States .............................................................. 250
5.19.8 USB 2.0 Legacy Keyboard Operation...................................................... 250
5.19.9 USB 2.0 Based Debug Port ................................................................... 250
5.19.9.1 Theory of Operation ............................................................. 251
5.19.10 EHCI Caching ..................................................................................... 255
® USB Pre-Fetch Based Pause ........................................................ 255
5.19.11 Intel
5.19.12 Function Level Reset Support (FLR) ....................................................... 255
5.19.12.1 FLR Steps ............................................................................ 255
5.19.13 USB Overcurrent Protection .................................................................. 256
5.20 Integrated USB 2.0 Rate Matching Hub .............................................................. 256
Datasheet 7
5.20.1 Overview............................................................................................ 256
5.20.2 Architecture........................................................................................ 257
5.21 xHCI Controller (D20:F0) .................................................................................. 257
5.22 SMBus Controller (D31:F3) ............................................................................... 258
5.22.1 Host Controller.................................................................................... 258
5.22.1.1 Command Protocols ............................................................... 259
5.22.2 Bus Arbitration .................................................................................... 262
5.22.3 Bus Timing ......................................................................................... 263
5.22.3.1 Clock Stretching .................................................................... 263
5.22.3.2 Bus Time Out (The PCH as SMBus Master) ................................ 263
5.22.4 Interrupts / SMI# ................................................................................ 263
5.22.5 SMBALERT# ....................................................................................... 264
5.22.6 SMBus CRC Generation and Checking ..................................................... 264
5.22.7 SMBus Slave Interface ......................................................................... 265
5.22.7.1 Format of Slave Write Cycle .................................................... 265
5.22.7.2 Format of Read Command ...................................................... 267
5.22.7.3 Slave Read of RTC Time Bytes................................................. 269
5.22.7.4 Format of Host Notify Command.............................................. 269
5.23 Thermal Management....................................................................................... 271
5.23.1 Thermal Sensor................................................................................... 271
5.23.1.1 Internal Thermal Sensor Operation .......................................... 271
5.23.2 PCH Thermal Throttling ........................................................................ 272
5.23.3 Thermal Reporting Over System Management Link 1 Interface (SMLink1) ... 273
5.23.3.1 Block Read Address ............................................................... 274
5.23.3.2 Block Read Command ............................................................ 274
5.23.3.3 Read Data Format ................................................................. 274
5.23.3.4 Thermal Data Update Rate...................................................... 274
5.23.3.5 Temperature Comparator and Alert.......................................... 274
5.23.3.6 BIOS Set Up ......................................................................... 275
5.23.3.7 SMBus Rules ......................................................................... 275
5.23.3.8 Case for Considerations.......................................................... 276
5.24 Intel High Definition Audio (Intel® HD Audio) Overview (D27:F0)......................... 279
®
5.24.1 Intel® High Definition Audio (Intel® HD Audio) Docking (Mobile Only) ........ 279
5.24.1.1 Dock Sequence ..................................................................... 279
5.24.1.2 Exiting D3/CRST# When Docked ............................................. 280
5.24.1.3 Cold Boot/Resume from S3 When Docked ................................. 281
5.24.1.4 Undock Sequence .................................................................. 281
5.24.1.5 Normal Undock ..................................................................... 281
5.24.1.6 Surprise Undock .................................................................... 282
5.24.1.7 Interaction between Dock/Undock and Power Management States 282
5.24.1.8 Relationship between HDA_DOCK_RST# and HDA_RST# ............ 282
5.25 Intel® Management Engine (Intel® ME) and Intel®
Management Engine Firmware (Intel® ME FW) 9.0 ............................................... 283
5.25.1 Intel® Management Engine (Intel® ME) Requirements.............................. 284
5.26 Serial Peripheral Interface (SPI) ........................................................................ 285
5.26.1 SPI Supported Feature Overview ........................................................... 286
5.26.1.1 Non-Descriptor Mode ............................................................. 286
5.26.1.2 Descriptor Mode .................................................................... 286
5.26.2 Flash Descriptor .................................................................................. 287
5.26.2.1 Descriptor Master Region........................................................ 289
5.26.3 Flash Access ....................................................................................... 290
5.26.3.1 Direct Access Security ............................................................ 290
5.26.3.2 Register Access Security......................................................... 290
5.26.4 Serial Flash Device Compatibility Requirements ....................................... 291
5.26.4.1 PCH SPI Based BIOS Requirements.......................................... 291
5.26.4.2 Integrated LAN Firmware SPI Flash Requirements...................... 291
5.26.4.3 Intel® Management Engine Firmware (Intel® ME FW) SPI
Flash Requirements ............................................................... 292
5.26.4.4 Hardware Sequencing Requirements ........................................ 292
5.26.5 Multiple Page Write Usage Model ........................................................... 294
5.26.5.1 Soft Flash Protection .............................................................. 294
5.26.5.2 BIOS Range Write Protection................................................... 294
5.26.5.3 SMI# Based Global Write Protection ......................................... 295
5.26.6 Flash Device Configurations .................................................................. 295
5.26.7 SPI Flash Device Recommended Pinout................................................... 295
5.26.8 Serial Flash Device Package .................................................................. 296
5.26.8.1 Common Footprint Usage Model .............................................. 296
8 Datasheet
5.26.8.2 Serial Flash Device Package Recommendations ......................... 296
5.26.9 PWM Outputs (Server/Workstation Only) ................................................ 297
5.26.10 TACH Inputs (Server/Workstation Only) ................................................. 297
5.27 Feature Capability Mechanism ........................................................................... 297
5.28 PCH Display Interface and Intel® Flexible Display Interface (Intel® FDI)
Interconnect ................................................................................................... 298
5.28.1 Analog Display Interface Characteristics ................................................. 299
5.28.1.1 Integrated RAMDAC .............................................................. 299
5.28.1.2 DDC (Display Data Channel)................................................... 299
5.28.2 Digital Display Side Band Signals .......................................................... 300
5.28.2.1 DisplayPort AUX CH............................................................... 300
5.28.2.2 DDC (Display Data Channel)................................................... 300
5.28.2.3 Hot-Plug Detect .................................................................... 300
5.28.2.4 Map of Digital Display Side Band Signals Per Display
Configuration ....................................................................... 300
5.28.2.5 Panel Power Sequencing and Backlight Control.......................... 301
5.28.3 Intel® Flexible Display Interface (Intel® FDI) .......................................... 302
5.29 Intel® Virtualization Technology (Intel® VT) ....................................................... 302
5.29.1 Intel® Virtualization Technology (Intel® VT) for
Directed I/O (Intel® VT-d) Objectives .................................................... 302
5.29.2 Intel® VT-d Features Supported ............................................................ 303
5.29.3 Support for Function Level Reset (FLR) in PCH ........................................ 303
5.29.4 Virtualization Support for PCH IOxAPIC .................................................. 303
5.29.5 Virtualization Support for High Precision Event Timer (HPET)..................... 304
6 Ballout Definition................................................................................................... 305
6.1 Desktop/Server PCH Ballout.............................................................................. 305
6.2 Mobile PCH Ballout .......................................................................................... 314
7 Package Information ............................................................................................. 323
7.1 Desktop / Server PCH package.......................................................................... 323
7.1.1 Tape and Reel Pin 1 Placement ............................................................. 323
7.2 Mobile PCH Package......................................................................................... 325
7.2.1 Tape and Reel Pin 1 Placement ............................................................. 325
8 Electrical Characteristics ....................................................................................... 327
8.1 Thermal Specifications ..................................................................................... 327
8.1.1 Storage Specifications and Thermal Design Power (TDP) .......................... 327
8.2 Absolute Maximum Ratings............................................................................... 328
8.3 PCH Power Supply Range ................................................................................. 328
8.4 General DC Characteristics ............................................................................... 329
8.5 Display DC Characteristics ................................................................................ 342
8.6 AC Characteristics ........................................................................................... 343
8.7 Power Sequencing and Reset Signal Timings ....................................................... 358
8.8 Power Management Timing Diagrams................................................................. 361
8.9 AC Timing Diagrams ........................................................................................ 367
8.10 Sequencing Rails Within The Same Well ............................................................. 378
9 Register and Memory Mapping............................................................................... 379
9.1 PCI Devices and Functions................................................................................ 380
9.2 PCI Configuration Map ..................................................................................... 381
9.3 I/O Map ......................................................................................................... 381
9.3.1 Fixed I/O Address Ranges .................................................................... 381
9.3.2 Variable I/O Decode Ranges ................................................................. 384
9.4 Memory Map................................................................................................... 385
9.4.1 Boot-Block Update Scheme .................................................................. 387
10 Chipset Configuration Registers............................................................................. 389
10.1 Chipset Configuration Registers (Memory Space) ................................................. 389
10.1.1 RPC—Root Port Configuration Register ................................................... 391
10.1.2 RPFN—Root Port Function Number and Hide for PCI
Express* Root Ports Register ................................................................ 391
10.1.3 FLRSTAT—Function Level Reset Pending Status Register........................... 393
10.1.4 TRSR—Trap Status Register.................................................................. 393
10.1.5 TRCR—Trapped Cycle Register .............................................................. 394
10.1.6 TWDR—Trapped Write Data Register...................................................... 394
10.1.7 IOTRn—I/O Trap Register (0–3) ............................................................ 395
10.1.8 V0CTL—Virtual Channel 0 Resource Control Register ................................ 396
Datasheet 9
10.1.9 V0STS—Virtual Channel 0 Resource Status Register ................................. 396
10.1.10 V1CTL—Virtual Channel 1 Resource Control Register ................................ 397
10.1.11 V1STS—Virtual Channel 1 Resource Status Register ................................. 397
10.1.12 REC—Root Error Command Register....................................................... 397
10.1.13 LCAP—Link Capabilities Register ............................................................ 398
10.1.14 LCTL—Link Control Register .................................................................. 399
10.1.15 LSTS—Link Status Register ................................................................... 399
10.1.16 DLCTL2—DMI Link Control 2 Register ..................................................... 399
10.1.17 DMIC—DMI Control Register ................................................................. 400
10.1.18 DMC—DMI Miscellaneous Control Register............................................... 400
10.1.19 TCTL—TCO Configuration Register ........................................................ 400
10.1.20 D31IP—Device 31 Interrupt Pin Register ................................................. 401
10.1.21 D30IP—Device 30 Interrupt Pin Register ................................................. 402
10.1.22 D29IP—Device 29 Interrupt Pin Register ................................................. 402
10.1.23 D28IP—Device 28 Interrupt Pin Register ................................................. 402
10.1.24 D27IP—Device 27 Interrupt Pin Register ................................................. 404
10.1.25 D26IP—Device 26 Interrupt Pin Register ................................................. 404
10.1.26 D25IP—Device 25 Interrupt Pin Register ................................................. 404
10.1.27 D22IP—Device 22 Interrupt Pin Register ................................................. 405
10.1.28 D20IP—Device 20 Interrupt Pin Register ................................................. 405
10.1.29 D31IR—Device 31 Interrupt Route Register............................................. 406
10.1.30 D30IR—Device 30 Interrupt Route Register............................................. 407
10.1.31 D29IR—Device 29 Interrupt Route Register............................................. 407
10.1.32 D28IR—Device 28 Interrupt Route Register............................................. 408
10.1.33 D27IR—Device 27 Interrupt Route Register............................................. 409
10.1.34 D26IR—Device 26 Interrupt Route Register............................................. 410
10.1.35 D25IR—Device 25 Interrupt Route Register............................................. 411
10.1.36 D22IR—Device 22 Interrupt Route Register............................................. 412
10.1.37 D20IR—Device 20 Interrupt Route Register............................................. 413
10.1.38 OIC—Other Interrupt Control Register .................................................... 414
10.1.39 WADT_AC—Wake Alarm Device Timer – AC Register ................................ 414
10.1.40 WADT_DC—Wake Alarm Device Timer – DC Register ................................ 415
10.1.41 WADT_EXP_AC—Wake Alarm Device Expired Timer – AC
Register ............................................................................................. 415
10.1.42 WADT_EXP_DC—Wake Alarm Device Expired Timer – DC
Register ............................................................................................. 416
10.1.43 PRSTS—Power and Reset Status Register................................................ 417
10.1.44 PM_CFG—Power Management Configuration Register ............................... 418
10.1.45 DEEP_S3_POL—Deep Sx From S3 Power Policies Register ......................... 420
10.1.46 DEEP_S4_POL—Deep Sx From S4 Power Policies Register ......................... 420
10.1.47 DEEP_S5_POL—Deep Sx From S5 Power Policies Register ......................... 420
10.1.48 DSX_CFG—Deep Sx Configuration Register ............................................. 421
10.1.49 PMSYNC_CFG—PMSYNC Configuration Register........................................ 422
10.1.50 RC—RTC Configuration Register............................................................. 422
10.1.51 HPTC—High Precision Timer Configuration Register .................................. 423
10.1.52 GCS—General Control and Status Register .............................................. 423
10.1.53 BUC—Backed Up Control Register .......................................................... 425
10.1.54 FD—Function Disable Register ............................................................... 426
10.1.55 CG—Clock Gating Register .................................................................... 428
10.1.56 FDSW—Function Disable SUS Well Register ............................................. 428
10.1.57 DISPBDF—Display Bus, Device and Function
Initialization Register ........................................................................... 429
10.1.58 FD2—Function Disable 2 Register........................................................... 429
10.2 Thermal Configuration Registers ........................................................................ 430
10.2.1 TIRC0—Thermal Initialization Register C0 ............................................... 430
10.2.2 TIRC4—Thermal Initialization Register C4 ............................................... 430
10.2.3 TIRC8—Thermal Initialization Register C8 ............................................... 430
10.2.4 TIRCC—Thermal Initialization Register CC ............................................... 430
10.2.5 TIRD0—Thermal Initialization Register D0............................................... 431
10.2.6 TIRE0—Thermal Initialization Register E0................................................ 431
10.2.7 TIRF0—Thermal Initialization Register F0 ................................................ 431
11 Gigabit LAN Configuration Registers ...................................................................... 433
11.1 Gigabit LAN Configuration Registers
(Gigabit LAN—D25:F0) ..................................................................................... 433
11.1.1 VID—Vendor Identification Register
(Gigabit LAN—D25:F0) ......................................................................... 434
10 Datasheet
11.1.2 DID—Device Identification Register
(Gigabit LAN—D25:F0) ........................................................................ 434
11.1.3 PCICMD—PCI Command Register
(Gigabit LAN—D25:F0) ........................................................................ 435
11.1.4 PCISTS—PCI Status Register
(Gigabit LAN—D25:F0) ........................................................................ 436
11.1.5 RID—Revision Identification Register
(Gigabit LAN—D25:F0) ........................................................................ 437
11.1.6 CC—Class Code Register
(Gigabit LAN—D25:F0) ........................................................................ 437
11.1.7 CLS—Cache Line Size Register
(Gigabit LAN—D25:F0) ........................................................................ 437
11.1.8 PLT—Primary Latency Timer Register
(Gigabit LAN—D25:F0) ........................................................................ 437
11.1.9 HEADTYP—Header Type Register
(Gigabit LAN—D25:F0) ........................................................................ 438
11.1.10 MBARA—Memory Base Address Register A
(Gigabit LAN—D25:F0) ........................................................................ 438
11.1.11 MBARB—Memory Base Address Register B
(Gigabit LAN—D25:F0) ........................................................................ 438
11.1.12 MBARC—Memory Base Address Register C
(Gigabit LAN—D25:F0) ........................................................................ 439
11.1.13 SVID—Subsystem Vendor ID Register
(Gigabit LAN—D25:F0) ........................................................................ 439
11.1.14 SID—Subsystem ID Register
(Gigabit LAN—D25:F0) ........................................................................ 439
11.1.15 ERBA—Expansion ROM Base Address Register
(Gigabit LAN—D25:F0) ........................................................................ 440
11.1.16 CAPP—Capabilities List Pointer Register
(Gigabit LAN—D25:F0) ........................................................................ 440
11.1.17 INTR—Interrupt Information Register
(Gigabit LAN—D25:F0) ........................................................................ 440
11.1.18 MLMG—Maximum Latency / Minimum Grant Register
(Gigabit LAN—D25:F0) ........................................................................ 440
11.1.19 STCL—System Time Control Low Register
(Gigabit LAN—D25:F0) ........................................................................ 441
11.1.20 STCH—System Time Control High Register
(Gigabit LAN—D25:F0) ........................................................................ 441
11.1.21 LTRCAP—System Time Control High Register
(Gigabit LAN—D25:F0) ........................................................................ 441
11.1.22 CLIST1—Capabilities List Register 1
(Gigabit LAN—D25:F0) ........................................................................ 442
11.1.23 PMC—PCI Power Management Capabilities Register
(Gigabit LAN—D25:F0) ........................................................................ 443
11.1.24 PMCS—PCI Power Management Control and Status
Register (Gigabit LAN—D25:F0) ............................................................ 444
11.1.25 DR—Data Register
(Gigabit LAN—D25:F0) ........................................................................ 445
11.1.26 CLIST2—Capabilities List Register 2
(Gigabit LAN—D25:F0) ........................................................................ 445
11.1.27 MCTL—Message Control Register
(Gigabit LAN—D25:F0) ........................................................................ 445
11.1.28 MADDL—Message Address Low Register
(Gigabit LAN—D25:F0) ........................................................................ 446
11.1.29 MADDH—Message Address High Register
(Gigabit LAN—D25:F0) ........................................................................ 446
11.1.30 MDAT—Message Data Register
(Gigabit LAN—D25:F0) ........................................................................ 446
11.1.31 FLRCAP—Function Level Reset Capability
(Gigabit LAN—D25:F0) ........................................................................ 446
11.1.32 FLRCLV—Function Level Reset Capability Length and
Version Register (Gigabit LAN—D25:F0) ................................................. 447
11.1.33 DEVCTRL—Device Control Register (Gigabit LAN—D25:F0) ....................... 447
11.2 Gigabit LAN Capabilities and Status Registers (CSR)............................................. 448
11.2.1 GBECSR_00—Gigabit Ethernet Capabilities and Status Register 00............. 448
11.2.2 GBECSR_18—Gigabit Ethernet Capabilities and Status Register 18............. 449
11.2.3 GBECSR_20—Gigabit Ethernet Capabilities and Status Register 20............. 449
Datasheet 11
11.2.4 GBECSR_2C—Gigabit Ethernet Capabilities and Status Register 2C............. 450
11.2.5 GBECSR_F00—Gigabit Ethernet Capabilities and Status Register F00 .......... 450
11.2.6 GBECSR_F10—Gigabit Ethernet Capabilities and Status Register F10 .......... 451
11.2.7 GBECSR_5400—Gigabit Ethernet Capabilities and Status Register 5400 ...... 451
11.2.8 GBECSR_5404—Gigabit Ethernet Capabilities and Status Register 5404 ...... 451
11.2.9 GBECSR_5800—Gigabit Ethernet Capabilities and Status Register 5800 ...... 452
11.2.10 GBECSR_5B54—Gigabit Ethernet Capabilities and Status Register 5B54 ...... 452
12 LPC Interface Bridge Registers (D31:F0) ............................................................... 453
12.1 PCI Configuration Registers (LPC I/F—D31:F0) .................................................... 453
12.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0) ............................. 454
12.1.2 DID—Device Identification Register (LPC I/F—D31:F0) ............................. 454
12.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0) ............................... 455
12.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0) ...................................... 455
12.1.5 RID—Revision Identification Register (LPC I/F—D31:F0) ........................... 456
12.1.6 PI—Programming Interface Register (LPC I/F—D31:F0) ............................ 456
12.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0) .................................... 456
12.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0)................................... 457
12.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0) ........................... 457
12.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0)................................. 457
12.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0)............................ 458
12.1.12 CAPP—Capability List Pointer Register (LPC I/F—D31:F0) .......................... 458
12.1.13 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0).......................... 458
12.1.14 ACPI_CNTL—ACPI Control Register (LPC I/F—D31:F0) .............................. 459
12.1.15 GPIOBASE—GPIO Base Address Register (LPC I/F—D31:F0) ...................... 459
12.1.16 GC—GPIO Control Register (LPC I/F—D31:F0) ......................................... 460
12.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register
(LPC I/F—D31:F0) ............................................................................... 461
12.1.18 SIRQ_CNTL—Serial IRQ Control Register
(LPC I/F—D31:F0) ............................................................................... 462
12.1.19 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register
(LPC I/F—D31:F0) ............................................................................... 463
12.1.20 LPC_IBDF—IOxAPIC Bus:Device:Function
(LPC I/F—D31:F0) ............................................................................... 463
12.1.21 LPC_HnBDF—HPET n Bus:Device:Function
(LPC I/F—D31:F0) ............................................................................... 464
12.1.22 LPC_I/O_DEC—I/O Decode Ranges Register
(LPC I/F—D31:F0) ............................................................................... 465
12.1.23 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)............................... 466
12.1.24 GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0) ............................................................................... 467
12.1.25 GEN2_DEC—LPC I/F Generic Decode Range 2 Register
(LPC I/F—D31:F0) ............................................................................... 467
12.1.26 GEN3_DEC—LPC I/F Generic Decode Range 3 Register
(LPC I/F—D31:F0) ............................................................................... 468
12.1.27 GEN4_DEC—LPC I/F Generic Decode Range 4 Register
(LPC I/F—D31:F0) ............................................................................... 468
12.1.28 ULKMC—USB Legacy Keyboard / Mouse
Control Register(LPC I/F—D31:F0)......................................................... 469
12.1.29 LGMR—LPC I/F Generic Memory Range Register
(LPC I/F—D31:F0) ............................................................................... 470
12.1.30 BIOS_SEL1—BIOS Select 1 Register
(LPC I/F—D31:F0) ............................................................................... 471
12.1.31 BIOS_SEL2—BIOS Select 2 Register
(LPC I/F—D31:F0) ............................................................................... 472
12.1.32 BIOS_DEC_EN1—BIOS Decode Enable
Register (LPC I/F—D31:F0)................................................................... 473
12.1.33 BIOS_CNTL—BIOS Control Register
(LPC I/F—D31:F0) ............................................................................... 475
12.1.34 FDCAP—Feature Detection Capability ID Register
(LPC I/F—D31:F0) ............................................................................... 476
12.1.35 FDLEN—Feature Detection Capability Length Register
(LPC I/F—D31:F0) ............................................................................... 476
12.1.36 FDVER—Feature Detection Version Register
(LPC I/F—D31:F0) ............................................................................... 476
12.1.37 FVECIDX—Feature Vector Index Register
(LPC I/F—D31:F0) ............................................................................... 476
12 Datasheet
12.1.38 FVECD—Feature Vector Data Register
(LPC I/F—D31:F0)............................................................................... 477
12.1.39 Feature Vector Space .......................................................................... 477
12.1.39.1 FVEC0—Feature Vector Register 0 ........................................... 477
12.1.39.2 FVEC1—Feature Vector Register 1 ........................................... 478
12.1.39.3 FVEC2—Feature Vector Register 2 ........................................... 478
12.1.39.4 FVEC3—Feature Vector Register 3 ........................................... 479
12.1.40 RCBA—Root Complex Base Address Register
(LPC I/F—D31:F0)............................................................................... 479
12.2 DMA I/O Registers........................................................................................... 480
12.2.1 DMABASE_CA—DMA Base and Current Address Registers ......................... 481
12.2.2 DMABASE_CC—DMA Base and Current Count Registers ............................ 482
12.2.3 DMAMEM_LP—DMA Memory Low Page Registers...................................... 482
12.2.4 DMACMD—DMA Command Register ....................................................... 483
12.2.5 DMASTA—DMA Status Register ............................................................. 483
12.2.6 DMA_WRSMSK—DMA Write Single Mask Register .................................... 484
12.2.7 DMACH_MODE—DMA Channel Mode Register .......................................... 485
12.2.8 DMA Clear Byte Pointer Register............................................................ 486
12.2.9 DMA Master Clear Register ................................................................... 486
12.2.10 DMA_CLMSK—DMA Clear Mask Register ................................................. 486
12.2.11 DMA_WRMSK—DMA Write All Mask Register ........................................... 487
12.3 Timer I/O Registers ......................................................................................... 488
12.3.1 TCW—Timer Control Word Register........................................................ 489
12.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register ......................... 491
12.3.3 Counter Access Ports Register............................................................... 492
12.4 8259 Interrupt Controller (PIC) Registers ........................................................... 493
12.4.1 Interrupt Controller I/O MAP................................................................. 493
12.4.2 ICW1—Initialization Command Word 1 Register....................................... 494
12.4.3 ICW2—Initialization Command Word 2 Register....................................... 495
12.4.4 ICW3—Master Controller Initialization Command
Word 3 Register .................................................................................. 495
12.4.5 ICW3—Slave Controller Initialization Command
Word 3 Register .................................................................................. 496
12.4.6 ICW4—Initialization Command Word 4 Register....................................... 496
12.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)
Register............................................................................................. 497
12.4.8 OCW2—Operational Control Word 2 Register........................................... 497
12.4.9 OCW3—Operational Control Word 3 Register........................................... 498
12.4.10 ELCR1—Master Controller Edge/Level Triggered Register .......................... 499
12.4.11 ELCR2—Slave Controller Edge/Level Triggered Register............................ 500
12.5 Advanced Programmable Interrupt Controller (APIC)............................................ 501
12.5.1 APIC Register Map............................................................................... 501
12.5.2 IND—Index Register ............................................................................ 501
12.5.3 DAT—Data Register ............................................................................. 502
12.5.4 EOIR—EOI Register ............................................................................. 502
12.5.5 ID—Identification Register.................................................................... 503
12.5.6 VER—Version Register ......................................................................... 503
12.5.7 REDIR_TBL—Redirection Table Register ................................................. 504
12.6 Real Time Clock Registers................................................................................. 506
12.6.1 I/O Register Address Map..................................................................... 506
12.6.2 Indexed Registers ............................................................................... 507
12.6.2.1 RTC_REGA—Register A .......................................................... 508
12.6.2.2 RTC_REGB—Register B (General Configuration) ........................ 509
12.6.2.3 RTC_REGC—Register C (Flag Register)..................................... 510
12.6.2.4 RTC_REGD—Register D (Flag Register) .................................... 510
12.7 Processor Interface Registers ............................................................................ 511
12.7.1 NMI_SC—NMI Status and Control Register.............................................. 511
12.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)
Register............................................................................................. 512
12.7.3 PORT92—Init Register ......................................................................... 512
12.7.4 COPROC_ERR—Coprocessor Error Register ............................................. 512
12.7.5 RST_CNT—Reset Control Register ......................................................... 513
12.8 Power Management Registers ........................................................................... 514
12.8.1 Power Management PCI Configuration Registers
(PM—D31:F0)..................................................................................... 514
12.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0)....................................................................... 515
Datasheet 13
12.8.1.2
GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0) ....................................................................... 516
12.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register
(PM—D31:F0) ....................................................................... 518
12.8.1.4 GEN_PMCON_LOCK—General Power Management
Configuration Lock Register .................................................... 521
12.8.1.5 BM_BREAK_EN_2 Register #2 (PM—D31:F0)............................. 521
12.8.1.6 BM_BREAK_EN Register (PM—D31:F0) ..................................... 521
12.8.1.7 GPI_ROUT—GPI Routing Control Register
(PM—D31:F0) ....................................................................... 523
12.8.1.8 GPI_ROUT2—GPI Routing Control Register #2 (PM-D31:F0) ........ 524
12.8.2 APM I/O Decode Register...................................................................... 524
12.8.2.1 APM_CNT—Advanced Power Management Control Port Register ... 525
12.8.2.2 APM_STS—Advanced Power Management Status Port Register .... 525
12.8.3 Power Management I/O Registers .......................................................... 526
12.8.3.1 PM1_STS—Power Management 1 Status Register....................... 527
12.8.3.2 PM1_EN—Power Management 1 Enable Register ........................ 529
12.8.3.3 PM1_CNT—Power Management 1 Control Register ..................... 530
12.8.3.4 PM1_TMR—Power Management 1 Timer Register ....................... 531
12.8.3.5 GPE0_STS—General Purpose Event 0 Status Register ................. 531
12.8.3.6 GPE0_EN—General Purpose Event 0 Enables Register................. 536
12.8.3.7 SMI_EN—SMI Control and Enable Register ................................ 538
12.8.3.8 SMI_STS—SMI Status Register................................................ 540
12.8.3.9 ALT_GPI_SMI_EN—Alternate GPI SMI Enable Register ................ 542
12.8.3.10 ALT_GPI_SMI_STS—Alternate GPI SMI Status Register............... 543
12.8.3.11 GPE_CNTL—General Purpose Control Register ........................... 544
12.8.3.12 DEVACT_STS—Device Activity Status Register........................... 544
12.8.3.13 PM2_CNT—Power Management 2 Control Register ..................... 545
12.8.3.14 ALT_GPI_SMI_EN2 - Alternate GPI SMI Enable 2 Register ........... 545
12.8.3.15 ALT_GPI_SMI_STS2—Alternate GPI SMI Status 2 Register .......... 546
12.9 System Management TCO Registers ................................................................... 547
12.9.1 TCO_RLD—TCO Timer Reload and Current Value Register ......................... 547
12.9.2 TCO_DAT_IN—TCO Data In Register ...................................................... 548
12.9.3 TCO_DAT_OUT—TCO Data Out Register ................................................. 548
12.9.4 TCO1_STS—TCO1 Status Register ......................................................... 548
12.9.5 TCO2_STS—TCO2 Status Register ......................................................... 550
12.9.6 TCO1_CNT—TCO1 Control Register ........................................................ 551
12.9.7 TCO2_CNT—TCO2 Control Register ........................................................ 552
12.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers ...................................... 552
12.9.9 TCO_WDCNT—TCO Watchdog Control Register ........................................ 553
12.9.10 SW_IRQ_GEN—Software IRQ Generation Register.................................... 553
12.9.11 TCO_TMR—TCO Timer Initial Value Register ............................................ 553
12.10 General Purpose I/O Registers ........................................................................... 554
12.10.1 GPIO_USE_SEL—GPIO Use Select Register.............................................. 555
12.10.2 GP_IO_SEL—GPIO Input/Output Select Register ...................................... 555
12.10.3 GP_LVL—GPIO Level for Input or Output Register .................................... 556
12.10.4 GPO_BLINK—GPO Blink Enable Register ................................................. 556
12.10.5 GP_SER_BLINK—GP Serial Blink Register ................................................ 557
12.10.6 GP_SB_CMDSTS—GP Serial Blink Command
Status Register ................................................................................... 557
12.10.7 GP_SB_DATA—GP Serial Blink Data Register ........................................... 558
12.10.8 GPI_NMI_EN—GPI NMI Enable Register .................................................. 558
12.10.9 GPI_NMI_STS—GPI NMI Status Register ................................................. 558
12.10.10GPI_INV—GPIO Signal Invert Register.................................................... 559
12.10.11GPIO_USE_SEL2—GPIO Use Select 2 Register ......................................... 559
12.10.12GP_IO_SEL2—GPIO Input/Output Select 2 Register ................................. 560
12.10.13GP_LVL2—GPIO Level for Input or Output 2 Register................................ 560
12.10.14GPIO_USE_SEL3—GPIO Use Select 3 Register ......................................... 561
12.10.15GP_IO_SEL3—GPIO Input/Output Select 3 Register ................................. 561
12.10.16GP_LVL3—GPIO Level for Input or Output 3 Register................................ 562
12.10.17GP_RST_SEL1—GPIO Reset Select Register ............................................ 562
12.10.18GP_RST_SEL2—GPIO Reset Select Register ............................................ 563
12.10.19GP_RST_SEL3—GPIO Reset Select Register ............................................ 563
13 SATA Controller Registers (D31:F2) ....................................................................... 565
13.1 PCI Configuration Registers (SATA–D31:F2) ........................................................ 565
13.1.1 VID—Vendor Identification Register (SATA—D31:F2)................................ 567
14 Datasheet
13.1.2 DID—Device Identification Register (SATA—D31:F2)................................ 567
13.1.3 PCICMD—PCI Command Register (SATA–D31:F2).................................... 567
13.1.4 PCISTS—PCI Status Register (SATA–D31:F2).......................................... 568
13.1.5 RID—Revision Identification Register (SATA—D31:F2).............................. 568
13.1.6 PI—Programming Interface Register (SATA–D31:F2) ............................... 569
13.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h......... 569
13.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h......... 569
13.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h......... 569
13.1.7 SCC—Sub Class Code Register (SATA–D31:F2) ....................................... 570
13.1.8 BCC—Base Class Code Register
(SATA–D31:F2SATA–D31:F2) ............................................................... 570
13.1.9 PMLT—Primary Master Latency Timer Register
(SATA–D31:F2) .................................................................................. 570
13.1.10 HTYPE—Header Type Register
(SATA–D31:F2) .................................................................................. 571
13.1.11 PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F2) ...................................................................... 571
13.1.12 PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F2) .................................................................................. 571
13.1.13 SCMD_BAR—Secondary Command Block Base Address
Register (SATA D31:F2) ....................................................................... 572
13.1.14 SCNL_BAR—Secondary Control Block Base Address
Register (SATA D31:F2) ....................................................................... 572
13.1.15 BAR—Legacy Bus Master Base Address Register
(SATA–D31:F2) .................................................................................. 573
13.1.16 ABAR/SIDPBA1—AHCI Base Address Register / Serial ATA
Index Data Pair Base Address (SATA–D31:F2) ........................................ 573
13.1.16.1 When SCC is not 01h............................................................. 573
13.1.16.2 When SCC is 01h .................................................................. 574
13.1.17 SVID—Subsystem Vendor Identification Register
(SATA–D31:F2) .................................................................................. 574
13.1.18 SID—Subsystem Identification Register (SATA–D31:F2) ........................... 574
13.1.19 CAP—Capabilities Pointer Register (SATA–D31:F2) .................................. 574
13.1.20 INT_LN—Interrupt Line Register (SATA–D31:F2) ..................................... 575
13.1.21 INT_PN—Interrupt Pin Register (SATA–D31:F2) ...................................... 575
13.1.22 IDE_TIM—IDE Timing Register (SATA–D31:F2) ....................................... 575
13.1.23 SIDETIM—Slave IDE Timing Register (SATA–D31:F2) .............................. 576
13.1.24 SDMA_CNT—Synchronous DMA Control Register
(SATA–D31:F2) .................................................................................. 576
13.1.25 SDMA_TIM—Synchronous DMA Timing Register
(SATA–D31:F2) .................................................................................. 576
13.1.26 IDE_CONFIG—IDE I/O Configuration Register
(SATA–D31:F2) .................................................................................. 577
13.1.27 PID—PCI Power Management Capability Identification
Register (SATA–D31:F2) ...................................................................... 577
13.1.28 PC—PCI Power Management Capabilities Register
(SATA–D31:F2) .................................................................................. 578
13.1.29 PMCS—PCI Power Management Control and Status
Register (SATA–D31:F2) ...................................................................... 578
13.1.30 MSICI—Message Signaled Interrupt Capability
Identification Register (SATA–D31:F2) ................................................... 579
13.1.31 MSIMC—Message Signaled Interrupt Message
Control Register (SATA–D31:F2) ........................................................... 579
13.1.32 MSIMA—Message Signaled Interrupt Message
Address Register (SATA–D31:F2) .......................................................... 581
13.1.33 MSIMD—Message Signaled Interrupt Message
Data Register (SATA–D31:F2)............................................................... 581
13.1.34 MAP—Address Map Register (SATA–D31:F2) ........................................... 582
13.1.35 PCS—Port Control and Status Register (SATA–D31:F2) ............................ 583
13.1.36 SCLKCG—SATA Clock Gating Control Register ......................................... 585
13.1.37 SGC—SATA General Configuration Register............................................. 586
13.1.38 SATACR0—SATA Capability Register 0 (SATA–D31:F2) ............................. 587
13.1.39 SATACR1—SATA Capability Register 1 (SATA–D31:F2) ............................. 587
13.1.40 FLRCID—FLR Capability Identification Register (SATA–D31:F2) ................. 588
13.1.41 FLRCLV—FLR Capability Length and Version Register (SATA–D31:F2)......... 588
13.1.42 FLRC—FLR Control Register (SATA–D31:F2) ........................................... 589
13.1.43 ATC—APM Trapping Control Register (SATA–D31:F2) ............................... 589
Datasheet 15
13.1.44 ATS—APM Trapping Status Register (SATA–D31:F2)................................. 590
13.1.45 SP—Scratch Pad Register (SATA–D31:F2) ............................................... 590
13.1.46 BFCS—BIST FIS Control/Status Register (SATA–D31:F2) .......................... 591
13.1.47 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ....................... 593
13.1.48 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ....................... 593
13.2 Bus Master IDE I/O Registers (D31:F2)............................................................... 594
13.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) ......................... 595
13.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2) .............................. 596
13.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F2)................................................................................ 597
13.2.4 AIR—AHCI Index Register (D31:F2) ....................................................... 597
13.2.5 AIDR—AHCI Index Data Register (D31:F2) ............................................. 597
13.3 Serial ATA Index/Data Pair Superset Registers..................................................... 598
13.3.1 SINDX—Serial ATA Index Register (D31:F2)............................................ 598
13.3.2 SDATA—Serial ATA Data Register (D31:F2)............................................. 599
13.3.2.1 PxSSTS—Serial ATA Status Register (D31:F2) ........................... 599
13.3.2.2 PxSCTL—Serial ATA Control Register (D31:F2) .......................... 600
13.3.2.3 PxSERR—Serial ATA Error Register (D31:F2) ............................. 601
13.4 AHCI Registers (D31:F2) .................................................................................. 603
13.4.1 AHCI Generic Host Control Registers (D31:F2) ........................................ 604
13.4.1.1 CAP—Host Capabilities Register (D31:F2) ................................. 604
13.4.1.2 GHC—Global PCH Control Register (D31:F2) ............................. 606
13.4.1.3 IS—Interrupt Status Register (D31:F2) .................................... 607
13.4.1.4 PI—Ports Implemented Register (D31:F2)................................. 608
13.4.1.5 VS—AHCI Version Register (D31:F2)........................................ 609
13.4.1.6 EM_LOC—Enclosure Management Location Register (D31:F2)...... 609
13.4.1.7 EM_CTRL—Enclosure Management Control Register (D31:F2) ...... 610
13.4.1.8 CAP2—HBA Capabilities Extended Register ................................ 611
13.4.1.9 RSTF—Intel® RST Feature Capabilities Register ......................... 611
13.4.2 Port Registers (D31:F2)........................................................................ 613
13.4.2.1 PxCLB—Port [5:0] Command List Base Address Register
(D31:F2) .............................................................................. 616
13.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper
32-Bits Register (D31:F2)....................................................... 616
13.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2) ................ 616
13.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits
Register (D31:F2) ................................................................. 617
13.4.2.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2) .................. 617
13.4.2.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2) .................. 619
13.4.2.7 PxCMD—Port [5:0] Command Register (D31:F2) ....................... 620
13.4.2.8 PxTFD—Port [5:0] Task File Data Register (D31:F2) ................... 623
13.4.2.9 PxSIG—Port [5:0] Signature Register (D31:F2) ......................... 623
13.4.2.10 PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2) ............ 624
13.4.2.11 PxSCTL—Port [5:0] Serial ATA Control Register (D31:F2) ........... 625
13.4.2.12 PxSERR—Port [5:0] Serial ATA Error Register (D31:F2) .............. 626
13.4.2.13 PxSACT—Port [5:0] Serial ATA Active Register (D31:F2)............. 628
13.4.2.14 PxCI—Port [5:0] Command Issue Register (D31:F2) .................. 628
14 SATA Controller Registers (D31:F5) ....................................................................... 629
14.1 PCI Configuration Registers (SATA–D31:F5) ........................................................ 629
14.1.1 VID—Vendor Identification Register (SATA—D31:F5)................................ 630
14.1.2 DID—Device Identification Register (SATA—D31:F5) ................................ 630
14.1.3 PCICMD—PCI Command Register (SATA–D31:F5) .................................... 631
14.1.4 PCISTS—PCI Status Register (SATA–D31:F5) .......................................... 632
14.1.5 RID—Revision Identification Register (SATA—D31:F5) .............................. 632
14.1.6 PI—Programming Interface Register (SATA–D31:F5) ................................ 633
14.1.7 SCC—Sub Class Code Register (SATA–D31:F5)........................................ 633
14.1.8 BCC—Base Class Code Register
(SATA–D31:F5SATA–D31:F5)................................................................ 633
14.1.9 PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F5) ...................................................................... 634
14.1.10 PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F5)................................................................................... 634
14.1.11 SCMD_BAR—Secondary Command Block Base Address
Register (SATA D31:F5) ....................................................................... 635
14.1.12 SCNL_BAR—Secondary Control Block Base Address
Register (SATA D31:F5) ....................................................................... 635
16 Datasheet
14.1.13 BAR—Legacy Bus Master Base Address Register
(SATA–D31:F5) .................................................................................. 636
14.1.14 SIDPBA—SATA Index/Data Pair Base Address Register
(SATA–D31:F5) .................................................................................. 636
14.1.15 SVID—Subsystem Vendor Identification Register
(SATA–D31:F5) .................................................................................. 637
14.1.16 SID—Subsystem Identification Register (SATA–D31:F5) ........................... 637
14.1.17 CAP—Capabilities Pointer Register (SATA–D31:F5) .................................. 637
14.1.18 INT_LN—Interrupt Line Register (SATA–D31:F5) ..................................... 637
14.1.19 INT_PN—Interrupt Pin Register (SATA–D31:F5) ...................................... 637
14.1.20 IDE_TIM—IDE Timing Register (SATA–D31:F5) ....................................... 638
14.1.21 SDMA_CNT—Synchronous DMA Control Register
(SATA–D31:F5) .................................................................................. 638
14.1.22 SDMA_TIM—Synchronous DMA Timing Register
(SATA–D31:F5) .................................................................................. 639
14.1.23 IDE_CONFIG—IDE I/O Configuration Register
(SATA–D31:F5) .................................................................................. 639
14.1.24 PID—PCI Power Management Capability Identification
Register (SATA–D31:F5) ...................................................................... 640
14.1.25 PC—PCI Power Management Capabilities Register
(SATA–D31:F5) .................................................................................. 640
14.1.26 PMCS—PCI Power Management Control and Status
Register (SATA–D31:F5) ...................................................................... 641
14.1.27 MAP—Address Map Register (SATA–D31:F5) ........................................... 642
14.1.28 PCS—Port Control and Status Register (SATA–D31:F5) ............................ 642
14.1.29 SATACR0—SATA Capability Register 0 (SATA–D31:F5) ............................. 643
14.1.30 SATACR1—SATA Capability Register 1 (SATA–D31:F5) ............................. 643
14.1.31 FLRCID—FLR Capability ID Register (SATA–D31:F5) ................................ 644
14.1.32 FLRCLV—FLR Capability Length and
Value Register (SATA–D31:F5) ............................................................. 644
14.1.33 FLRCTRL—FLR Control Register (SATA–D31:F5) ...................................... 644
14.1.34 ATC—APM Trapping Control Register (SATA–D31:F5) ............................... 645
14.1.35 ATC—APM Trapping Control Register (SATA–D31:F5) ............................... 645
14.2 Bus Master IDE I/O Registers (D31:F5) .............................................................. 645
14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5) ......................... 646
14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5) .............................. 647
14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F5) ............................................................................... 647
14.3 Serial ATA Index/Data Pair Superset Registers .................................................... 648
14.3.1 SINDX—SATA Index Register (D31:F5) .................................................. 648
14.3.2 SDATA—SATA Index Data Register (D31:F5) .......................................... 648
14.3.2.1 PxSSTS—Serial ATA Status Register (D31:F5)........................... 649
14.3.2.2 PxSCTL—Serial ATA Control Register (D31:F5) .......................... 650
14.3.2.3 PxSERR—Serial ATA Error Register (D31:F5) ............................ 651
15 EHCI Controller Registers (D29:F0, D26:F0) .......................................................... 653
15.1 USB EHCI Configuration Registers
(USB EHCI—D29:F0, D26:F0) ........................................................................... 653
15.1.1 VID—Vendor Identification Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 654
15.1.2 DID—Device Identification Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 654
15.1.3 PCICMD—PCI Command Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 655
15.1.4 PCISTS—PCI Status Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 656
15.1.5 RID—Revision Identification Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 657
15.1.6 PI—Programming Interface Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 657
15.1.7 SCC—Sub Class Code Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 657
15.1.8 BCC—Base Class Code Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 657
15.1.9 PMLT—Primary Master Latency Timer Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 658
Datasheet 17
15.1.10 HEADTYP—Header Type Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 658
15.1.11 MEM_BASE—Memory Base Address Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 658
15.1.12 SVID—USB EHCI Subsystem Vendor ID Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 659
15.1.13 SID—USB EHCI Subsystem ID Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 659
15.1.14 CAP_PTR—Capabilities Pointer Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 659
15.1.15 INT_LN—Interrupt Line Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 660
15.1.16 INT_PN—Interrupt Pin Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 660
15.1.17 PWR_CAPID—PCI Power Management Capability
Identification Register (USB EHCI—D29:F0, D26:F0) ................................ 660
15.1.18 NXT_PTR1—Next Item Pointer #1 Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 661
15.1.19 PWR_CAP—Power Management Capabilities Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 661
15.1.20 PWR_CNTL_STS—Power Management Control /
Status Register (USB EHCI—D29:F0, D26:F0) ......................................... 662
15.1.21 DEBUG_CAPID—Debug Port Capability ID Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 663
15.1.22 NXT_PTR2—Next Item Pointer #2 Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 663
15.1.23 DEBUG_BASE—Debug Port Base Offset Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 663
15.1.24 USB_RELNUM—USB Release Number Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 663
15.1.25 FL_ADJ—Frame Length Adjustment Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 664
15.1.26 PWAKE_CAP—Port Wake Capability Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 665
15.1.27 PDO—Port Disable Override Register ...................................................... 665
15.1.28 RMHDEVR—RMH Device Removable Field Register ................................... 666
15.1.29 LEG_EXT_CAP—USB EHCI Legacy Support Extended
Capability Register (USB EHCI—D29:F0, D26:F0) .................................... 666
15.1.30 LEG_EXT_CS—USB EHCI Legacy Support Extended
Control / Status Register (USB EHCI—D29:F0, D26:F0) ............................ 667
15.1.31 SPECIAL_SMI—Intel® Specific USB 2.0 SMI Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 669
15.1.32 OCMAP—Over-Current Mapping Register................................................. 670
15.1.33 RMHWKCTL—RMH Wake Control Register................................................ 672
15.1.34 ACCESS_CNTL—Access Control Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 672
15.1.35 EHCIIR1—EHCI Initialization Register 1
(USB EHCI—D29:F0, D26:F0) ............................................................... 673
15.1.36 FLR_CID—Function Level Reset Capability ID Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 673
15.1.37 FLR_NEXT—Function Level Reset Next Capability
Pointer Register (USB EHCI—D29:F0, D26:F0) ........................................ 673
15.1.38 FLR_CLV—Function Level Reset Capability Length and
Version Register (USB EHCI—D29:F0, D26:F0)........................................ 674
15.1.39 FLR_CTRL—Function Level Reset Control Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 674
15.1.40 FLR_STS—Function Level Reset Status Register
(USB EHCI—D29:F0, D26:F0) ............................................................... 674
15.2 Memory-Mapped I/O Registers .......................................................................... 675
15.2.1 Host Controller Capability Registers ....................................................... 675
15.2.1.1 CAPLENGTH—Capability Registers Length Register ..................... 676
15.2.1.2 HCIVERSION—Host Controller Interface Version Number
Register ............................................................................... 676
15.2.1.3 HCSPARAMS—Host Controller Structural Parameters .................. 676
15.2.1.4 HCCPARAMS—Host Controller Capability Parameters
Register ............................................................................... 677
15.2.2 Host Controller Operational Registers ..................................................... 678
18 Datasheet
15.2.2.1
USB2.0_CMD—USB 2.0 Command Register .............................. 678
15.2.2.2
USB2.0_STS—USB 2.0 Status Register .................................... 683
15.2.2.3
USB2.0_INTR—USB 2.0 Interrupt Enable Register ..................... 685
15.2.2.4
FRINDEX—Frame Index Register ............................................. 686
15.2.2.5
CTRLDSSEGMENT—Control Data Structure Segment
Register............................................................................... 687
15.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address
Register............................................................................... 687
15.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address
Register............................................................................... 688
15.2.2.8 CONFIGFLAG—Configure Flag Register ..................................... 688
15.2.2.9 PORTSC—Port N Status and Control Register ............................ 689
15.2.3 USB 2.0-Based Debug Port Registers ..................................................... 692
15.2.3.1 CNTL_STS—Control / Status Register....................................... 693
15.2.3.2 USBPID—USB PIDs Register ................................................... 694
15.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register ....................... 695
15.2.3.4 CONFIG—Configuration Register ............................................. 695
16 xHCI Controller Registers (D20:F0) ....................................................................... 697
16.1 USB xHCI Configuration Registers
(USB xHCI—D20:F0) ....................................................................................... 697
16.1.1 VID—Vendor Identification Register
(USB xHCI—D20:F0) ........................................................................... 699
16.1.2 DID—Device Identification Register
(USB xHCI—D20:F0) ........................................................................... 699
16.1.3 PCICMD—PCI Command Register
(USB xHCI—D20:F0) ........................................................................... 700
16.1.4 PCISTS—PCI Status Register
(USB xHCI—D20:F0) ........................................................................... 701
16.1.5 RID—Revision Identification Register
(USB xHCI—D20:F0) ........................................................................... 702
16.1.6 PI—Programming Interface Register
(USB xHCI—D20:F0) ........................................................................... 702
16.1.7 SCC—Sub Class Code Register
(USB xHCI—D20:F0) ........................................................................... 702
16.1.8 BCC—Base Class Code Register
(USB xHCI—D20:F0) ........................................................................... 702
16.1.9 PMLT—Primary Master Latency Timer Register
(USB xHCI—D20:F0) ........................................................................... 703
16.1.10 HEADTYP—Header Type Register
(USB xHCI—D20:F0) ........................................................................... 703
16.1.11 MEM_BASE_L—Memory Base Address Low Register
(USB xHCI—D20:F0) ........................................................................... 703
16.1.12 MEM_BASE_H—Memory Base Address High Register
(USB xHCI—D20:F0) ........................................................................... 704
16.1.13 SVID—USB xHCI Subsystem Vendor ID Register
(USB xHCI—D20:F0) ........................................................................... 704
16.1.14 SID—USB xHCI Subsystem ID Register
(USB xHCI—D20:F0) ........................................................................... 704
16.1.15 CAP_PTR—Capabilities Pointer Register
(USB xHCI—D20:F0) ........................................................................... 704
16.1.16 INT_LN—Interrupt Line Register
(USB xHCI—D20:F0) ........................................................................... 705
16.1.17 INT_PN—Interrupt Pin Register
(USB xHCI—D20:F0) ........................................................................... 705
16.1.18 XHCC—xHC System Bus Configuration Register
(USB xHCI—D20:F0) ........................................................................... 705
16.1.19 XHCC2—xHC System Bus Configuration Register 2
(USB xHCI—D20:F0) ........................................................................... 706
16.1.20 SBRN—Serial Bus Release Number
Register (USB xHCI—D20:F0) ............................................................... 706
16.1.21 FL_ADJ—Frame Length Adjustment Register
(USB xHCI—D20:F0) ........................................................................... 707
16.1.22 PWR_CAPID—PCI Power Management Capability ID
Register (USB xHCI—D20:F0) ............................................................... 707
16.1.23 NXT_PTR1—Next Item Pointer #1 Register
(USB xHCI—D20:F0) ........................................................................... 708
Datasheet 19
16.1.24 PWR_CAP—Power Management Capabilities Register
(USB xHCI—D20:F0)............................................................................ 708
16.1.25 PWR_CNTL_STS—Power Management Control /
Status Register (USB xHCI—D20:F0) ..................................................... 709
16.1.26 MSI_CAPID—Message Signaled Interrupt Capability ID Register
(USB xHCI—D20:F0)............................................................................ 710
16.1.27 NEXT_PTR2—Next Item Pointer Register #2
(USB xHCI—D20:F0)............................................................................ 710
16.1.28 MSI_MCTL—MSI Message Control Register
(USB xHCI—D20:F0)............................................................................ 710
16.1.29 MSI_LMAD—MSI Lower Message Address Register
(USB xHCI—D20:F0)............................................................................ 711
16.1.30 MSI_UMAD—MSI Upper Message Address Register
(USB xHCI—D20:F0)............................................................................ 711
16.1.31 MSI_MD—MSI Message Data Register
(USB xHCI—D20:F0)............................................................................ 711
16.1.32 U2OCM1 - XHCI USB2 Overcurrent Mapping Register1
(USB xHCI—D20:F0)............................................................................ 712
16.1.33 U2OCM2 - XHCI USB2 Overcurrent Mapping Register 2
(USB xHCI—D20:F0)............................................................................ 713
16.1.34 U3OCM1 - XHCI USB3 Overcurrent Pin Mapping 1
(USB xHCI—D20:F0)............................................................................ 714
16.1.35 U3OCM2 - XHCI USB3 Overcurrent Pin Mapping 2
(USB xHCI—D20:F0)............................................................................ 715
16.1.36 XUSB2PR—xHC USB 2.0 Port Routing Register
(USB xHCI—D20:F0)............................................................................ 716
16.1.37 XUSB2PRM—xHC USB 2.0 Port Routing Mask Register
(USB xHCI—D20:F0)............................................................................ 716
16.1.38 USB3_PSSEN—USB 3.0 Port SuperSpeed Enable Register
(USB xHCI—D20:F0)............................................................................ 717
16.1.39 USB3PRM—USB 3.0 Port Routing Mask Register
(USB xHCI—D20:F0)............................................................................ 717
16.1.40 USB2PDO—xHCI USB Port Disable Override Register
(USB xHCI—D20:F0)............................................................................ 718
16.1.41 USB3PDO—USB3 Port Disable Override
(USB xHCI—D20:F0)............................................................................ 718
16.2 Memory-Mapped I/O Registers .......................................................................... 719
16.2.1 Host Controller Capability Registers ....................................................... 719
16.2.1.1 CAPLENGTH—Capability Registers Length Register ..................... 720
16.2.1.2 HCIVERSION—Host Controller Interface Version Number
Register ............................................................................... 720
16.2.1.3 HCSPARAMS1—Host Controller Structural Parameters
#1 Register .......................................................................... 720
16.2.1.4 HCSPARAMS2—Host Controller Structural Parameters
#2 Register .......................................................................... 721
16.2.1.5 HCSPARAMS3—Host Controller Structural Parameters
#3 Register .......................................................................... 722
16.2.1.6 HCCPARAMS—Host Controller Capability Parameters Register ...... 723
16.2.1.7 dBOFF—Doorbell Offset Register .............................................. 724
16.2.1.8 RTSOFF—Runtime Register Space Offset Register ...................... 724
16.2.2 Host Controller Operational Registers ..................................................... 725
16.2.2.1 USB_CMD—USB Command Register......................................... 726
16.2.2.2 USB_STS—USB Status Register ............................................... 728
16.2.2.3 PAGESIZE—Page Size Register ................................................ 729
16.2.2.4 DNCTRL—Device Notification Control Register ........................... 729
16.2.2.5 CRCRL—Command Ring Control Low Register............................ 730
16.2.2.6 CRCRH—Command Ring Control High Register .......................... 731
16.2.2.7 DCBAAPL—Device Context Base Address Array Pointer Low
Register ............................................................................... 731
16.2.2.8 DCBAAPH—Device Context Base Address Array Pointer High
Register ............................................................................... 732
16.2.2.9 CONFIG—Configure Register ................................................... 732
16.2.2.10 PORTSCNUSB2—Port N Status and Control USB2 Register........... 733
16.2.2.11 PORTPMSCNUSB2—xHCI Port N Power Management Status
and Control USB2 Register...................................................... 739
16.2.2.12 PORTSCNUSB3—xHCI USB 3.0 Port N Status and
Control Register .................................................................... 740
20 Datasheet
16.2.2.13 PORTPMSCN—Port N Power Management Status and Control
USB3 Register ...................................................................... 746
16.2.2.14 PORTLIX—USB 3.0 Port X Link Info Register ............................. 747
16.2.3 Host Controller Runtime Registers ......................................................... 747
16.2.3.1 MFINDEX—Microframe Index Register ...................................... 747
16.2.3.2 IMAN—Interrupter X Management Register............................... 748
16.2.3.3 IMOD—Interrupter X Moderation Register................................. 749
16.2.3.4 ERSTSZ—Event Ring Segment Table Size X Register .................. 749
16.2.3.5 ERSTBAL—Event Ring Segment Table Base Address Low X
Register............................................................................... 750
16.2.3.6 ERSTBAH—Event Ring Segment Table Base Address High X
Register............................................................................... 750
16.2.3.7 ERDPL—Event Ring Dequeue Pointer Low X Register .................. 751
16.2.3.8 ERDPH—Event Ring Dequeue Pointer High X Register................. 751
16.2.4 Doorbell Registers ............................................................................... 752
16.2.4.1 DOORBELL—Doorbell X Register.............................................. 752
17 Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers .... 753
17.1 Intel® High Definition Audio (Intel® HD Audio) Controller Registers (D27:F0) .......... 753
17.1.1 Intel® High Definition Audio PCI Configuration Space
(Intel® High Definition Audio—D27:F0) .................................................. 753
17.1.1.1 VID—Vendor Identification Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 755
17.1.1.2 DID—Device Identification Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 755
17.1.1.3 PCICMD—PCI Command Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 756
17.1.1.4 PCISTS—PCI Status Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 757
17.1.1.5 RID—Revision Identification Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 757
17.1.1.6 PI—Programming Interface Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 757
17.1.1.7 SCC—Sub Class Code Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 758
17.1.1.8 BCC—Base Class Code Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 758
17.1.1.9 CLS—Cache Line Size Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 758
17.1.1.10 LT—Latency Timer Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 758
17.1.1.11 HEADTYP—Header Type Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 758
17.1.1.12 HdBARL—Intel® High Definition Audio Lower Base Address
Register (Intel® High Definition Audio—D27:F0) ........................ 759
17.1.1.13 HdBARU—Intel® High Definition Audio Upper Base Address
Register (Intel® High Definition Audio Controller—D27:F0) ......... 759
17.1.1.14 SVID—Subsystem Vendor Identification Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 759
17.1.1.15 SID—Subsystem Identification Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 760
17.1.1.16 CAPPTR—Capabilities Pointer Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 760
17.1.1.17 INTLN—Interrupt Line Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 760
17.1.1.18 INTPN—Interrupt Pin Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 761
17.1.1.19 HDCTL—Intel® High Definition Audio Control Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 761
17.1.1.20 DCKCTL—Docking Control Register (Mobile Only)
(Intel® High Definition Audio Controller—D27:F0) ..................... 761
17.1.1.21 DCKSTS—Docking Status Register (Mobile Only)
(Intel® High Definition Audio Controller—D27:F0) ..................... 762
17.1.1.22 PID—PCI Power Management Capability ID Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 762
17.1.1.23 PC—Power Management Capabilities Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 763
Datasheet 21
17.1.1.24 PCS—Power Management Control and Status Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 763
17.1.1.25 MID—MSI Capability ID Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 764
17.1.1.26 MMC—MSI Message Control Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 764
17.1.1.27 MMLA—MSI Message Lower Address Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 765
17.1.1.28 MMUA—MSI Message Upper Address Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 765
17.1.1.29 MMD—MSI Message Data Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 765
17.1.1.30 PXID—PCI Express* Capability ID Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 765
17.1.1.31 PXC—PCI Express* Capabilities Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 766
17.1.1.32 DEVCAP—Device Capabilities Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 766
17.1.1.33 DEVC—Device Control Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 767
17.1.1.34 DEVS—Device Status Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 768
17.1.1.35 VCCAP—Virtual Channel Enhanced Capability Header
(Intel® High Definition Audio Controller—D27:F0) ...................... 768
17.1.1.36 PVCCAP1—Port VC Capability Register 1
(Intel® High Definition Audio Controller—D27:F0) ...................... 769
17.1.1.37 PVCCAP2—Port VC Capability Register 2
(Intel® High Definition Audio Controller—D27:F0) ...................... 769
17.1.1.38 PVCCTL—Port VC Control Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 769
17.1.1.39 PVCSTS—Port VC Status Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 770
17.1.1.40 VC0CAP—VC0 Resource Capability Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 770
17.1.1.41 VC0CTL—VC0 Resource Control Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 771
17.1.1.42 VC0STS—VC0 Resource Status Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 771
17.1.1.43 VCiCAP—VCi Resource Capability Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 772
17.1.1.44 VCiCTL—VCi Resource Control Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 772
17.1.1.45 VCiSTS—VCi Resource Status Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 773
17.1.1.46 RCCAP—Root Complex Link Declaration Enhanced
Capability Header Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 773
17.1.1.47 ESD—Element Self Description Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 773
17.1.1.48 L1DESC—Link 1 Description Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 774
17.1.1.49 L1ADDL—Link 1 Lower Address Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 774
17.1.1.50 L1ADDU—Link 1 Upper Address Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 774
17.1.2 Intel® High Definition Audio Memory Mapped Configuration Registers
(Intel® High Definition Audio D27:F0) .................................................... 775
17.1.2.1 GCAP—Global Capabilities Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 779
17.1.2.2 VMIN—Minor Version Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 779
17.1.2.3 VMAJ—Major Version Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 779
17.1.2.4 OUTPAY—Output Payload Capability Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 780
17.1.2.5 INPAY—Input Payload Capability Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 780
22 Datasheet
17.1.2.6 GCTL—Global Control Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 781
17.1.2.7 WAKEEN—Wake Enable Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 782
17.1.2.8 STATESTS—State Change Status Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 782
17.1.2.9 GSTS—Global Status Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 783
17.1.2.10 GCAP2 Global Capabilities 2 Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 783
17.1.2.11 OUTSTRMPAY—Output Stream Payload Capability
(Intel® High Definition Audio Controller—D27:F0) ..................... 783
17.1.2.12 INSTRMPAY—Input Stream Payload Capability
(Intel® High Definition Audio Controller—D27:F0) ..................... 784
17.1.2.13 INTCTL—Interrupt Control Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 784
17.1.2.14 INTSTS—Interrupt Status Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 785
17.1.2.15 WALCLK—Wall Clock Counter Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 786
17.1.2.16 SSYNC—Stream Synchronization Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 786
17.1.2.17 CORBLBASE—CORB Lower Base Address Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 787
17.1.2.18 CORBUBASE—CORB Upper Base Address Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 787
17.1.2.19 CORBWP—CORB Write Pointer Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 787
17.1.2.20 CORBRP—CORB Read Pointer Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 788
17.1.2.21 CORBCTL—CORB Control Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 788
17.1.2.22 CORBST—CORB Status Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 789
17.1.2.23 CORBSIZE—CORB Size Register
Intel® High Definition Audio Controller—D27:F0)....................... 789
17.1.2.24 RIRBLBASE—RIRB Lower Base Address Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 789
17.1.2.25 RIRBUBASE—RIRB Upper Base Address Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 790
17.1.2.26 RIRBWP—RIRB Write Pointer Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 790
17.1.2.27 RINTCNT—Response Interrupt Count Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 790
17.1.2.28 RIRBCTL—RIRB Control Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 791
17.1.2.29 RIRBSTS—RIRB Status Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 791
17.1.2.30 RIRBSIZE—RIRB Size Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 792
17.1.2.31 IC—Immediate Command Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 792
17.1.2.32 IR—Immediate Response Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 792
17.1.2.33 ICS—Immediate Command Status Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 793
17.1.2.34 DPLBASE—DMA Position Lower Base Address Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 793
17.1.2.35 DPUBASE—DMA Position Upper Base Address Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 794
17.1.2.36 SDCTL—Stream Descriptor Control Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 794
17.1.2.37 SDSTS—Stream Descriptor Status Register
(Intel® High Definition Audio Controller—D27:F0) ..................... 796
17.1.2.38 SDLPIB—Stream Descriptor Link Position in Buffer
Register (Intel® High Definition Audio Controller—D27:F0) ......... 797
Datasheet 23
17.1.2.39 SDCBL—Stream Descriptor Cyclic Buffer Length Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 797
17.1.2.40 SDLVI—Stream Descriptor Last Valid Index Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 798
17.1.2.41 SDFIFOW—Stream Descriptor FIFO Watermark Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 798
17.1.2.42 ISDFIFOS—Input Stream Descriptor FIFO Size Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 799
17.1.2.43 SDFMT—Stream Descriptor Format Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 800
17.1.2.44 SdBDPL—Stream Descriptor Buffer Descriptor List
Pointer Lower Base Address Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 801
17.1.2.45 SdBDPU—Stream Descriptor Buffer Descriptor List
Pointer Upper Base Address Register
(Intel® High Definition Audio Controller—D27:F0) ...................... 801
18 SMBus Controller Registers (D31:F3) ..................................................................... 803
18.1 PCI Configuration Registers (SMBus—D31:F3) ..................................................... 803
18.1.1 VID—Vendor Identification Register (SMBus—D31:F3) .............................. 803
18.1.2 DID—Device Identification Register (SMBus—D31:F3) .............................. 804
18.1.3 PCICMD—PCI Command Register (SMBus—D31:F3) ................................. 804
18.1.4 PCISTS—PCI Status Register (SMBus—D31:F3) ....................................... 805
18.1.5 RID—Revision Identification Register (SMBus—D31:F3) ............................ 805
18.1.6 PI—Programming Interface Register (SMBus—D31:F3) ............................. 806
18.1.7 SCC—Sub Class Code Register (SMBus—D31:F3)..................................... 806
18.1.8 BCC—Base Class Code Register (SMBus—D31:F3) ................................... 806
18.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0
Register (SMBus—D31:F3).................................................................... 806
18.1.10 SMBMBAR1—D31_F3_SMBus Memory Base Address 1
Register (SMBus—D31:F3).................................................................... 807
18.1.11 SMB_BASE—SMBus Base Address Register
(SMBus—D31:F3) ................................................................................ 807
18.1.12 SVID—Subsystem Vendor Identification Register
(SMBus—D31:F2/F4) ........................................................................... 807
18.1.13 SID—Subsystem Identification Register
(SMBus—D31:F2/F4) ........................................................................... 808
18.1.14 INT_LN—Interrupt Line Register (SMBus—D31:F3) .................................. 808
18.1.15 INT_PN—Interrupt Pin Register (SMBus—D31:F3) .................................... 808
18.1.16 HOSTC—Host Configuration Register (SMBus—D31:F3) ............................ 809
18.2 SMBus I/O and Memory Mapped I/O Registers ..................................................... 810
18.2.1 HST_STS—Host Status Register (SMBus—D31:F3) ................................... 811
18.2.2 HST_CNT—Host Control Register (SMBus—D31:F3).................................. 812
18.2.3 HST_CMD—Host Command Register (SMBus—D31:F3) ............................. 814
18.2.4 XMIT_SLVA—Transmit Slave Address Register
(SMBus—D31:F3) ................................................................................ 814
18.2.5 HST_D0—Host Data 0 Register (SMBus—D31:F3) .................................... 814
18.2.6 HST_D1—Host Data 1 Register (SMBus—D31:F3) .................................... 814
18.2.7 Host_BLOCK_dB—Host Block Data Byte Register
(SMBus—D31:F3) ................................................................................ 815
18.2.8 PEC—Packet Error Check (PEC) Register
(SMBus—D31:F3) ................................................................................ 815
18.2.9 RCV_SLVA—Receive Slave Address Register
(SMBus—D31:F3) ................................................................................ 816
18.2.10 SLV_DATA—Receive Slave Data Register (SMBus—D31:F3)....................... 816
18.2.11 AUX_STS—Auxiliary Status Register (SMBus—D31:F3) ............................. 816
18.2.12 AUX_CTL—Auxiliary Control Register (SMBus—D31:F3) ............................ 817
18.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register
(SMBus—D31:F3) ................................................................................ 817
18.2.14 SMBus_PIN_CTL—SMBus Pin Control Register
(SMBus—D31:F3) ................................................................................ 818
18.2.15 SLV_STS—Slave Status Register (SMBus—D31:F3) .................................. 818
18.2.16 SLV_CMD—Slave Command Register (SMBus—D31:F3) ............................ 819
18.2.17 NOTIFY_DADDR—Notify Device Address Register
(SMBus—D31:F3) ................................................................................ 819
18.2.18 NOTIFY_DLOW—Notify Data Low Byte Register
(SMBus—D31:F3) ................................................................................ 820
24 Datasheet
18.2.19 NOTIFY_DHIGH—Notify Data High Byte Register
(SMBus—D31:F3) ............................................................................... 820
19 PCI Express* Configuration Registers.................................................................... 821
19.1 PCI Express* Configuration Registers
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)................................................... 821
19.1.1 VID—Vendor Identification Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 823
19.1.2 DID—Device Identification Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 823
19.1.3 PCICMD—PCI Command Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 824
19.1.4 PCISTS—PCI Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 825
19.1.5 RID—Revision Identification Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 826
19.1.6 PI—Programming Interface Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 826
19.1.7 SCC—Sub Class Code Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 826
19.1.8 BCC—Base Class Code Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 826
19.1.9 CLS—Cache Line Size Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 827
19.1.10 PLT—Primary Latency Timer Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 827
19.1.11 HEADTYP—Header Type Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 827
19.1.12 BNUM—Bus Number Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 828
19.1.13 SLT—Secondary Latency Timer Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 828
19.1.14 IOBL—I/O Base and Limit Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 828
19.1.15 SSTS—Secondary Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 829
19.1.16 MBL—Memory Base and Limit Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 830
19.1.17 PMBL—Prefetchable Memory Base and Limit Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 830
19.1.18 PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................... 831
19.1.19 PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) .......................... 831
19.1.20 CAPP—Capabilities List Pointer Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 831
19.1.21 INTR—Interrupt Information Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 832
19.1.22 BCTRL—Bridge Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 833
19.1.23 CLIST—Capabilities List Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 834
19.1.24 XCAP—PCI Express* Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 834
19.1.25 DCAP—Device Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 835
19.1.26 DCTL—Device Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 836
19.1.27 DSTS—Device Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 837
19.1.28 LCAP—Link Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 838
19.1.29 LCTL—Link Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 840
19.1.30 LSTS—Link Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ...................................... 841
Datasheet 25
19.1.31 SLCAP—Slot Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 842
19.1.32 SLCTL—Slot Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 843
19.1.33 SLSTS—Slot Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 844
19.1.34 RCTL—Root Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 845
19.1.35 RSTS—Root Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 845
19.1.36 DCAP2—Device Capabilities 2 Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 846
19.1.37 DCTL2—Device Control 2 Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 846
19.1.38 LCTL2—Link Control 2 Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 848
19.1.39 LSTS2—Link Status 2 Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 849
19.1.40 MID—Message Signaled Interrupt Identifiers Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 849
19.1.41 MC—Message Signaled Interrupt Message Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 850
19.1.42 MA—Message Signaled Interrupt Message Address
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................... 850
19.1.43 MD—Message Signaled Interrupt Message Data Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 851
19.1.44 SVCAP—Subsystem Vendor Capability Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 851
19.1.45 SVID—Subsystem Vendor Identification Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 851
19.1.46 PMCAP—Power Management Capability Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 852
19.1.47 PMC—PCI Power Management Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 852
19.1.48 PMCS—PCI Power Management Control and Status
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)........................... 853
19.1.49 MPC2—Miscellaneous Port Configuration Register 2
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 854
19.1.50 MPC—Miscellaneous Port Configuration Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 855
19.1.51 SMSCS—SMI/SCI Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 857
19.1.52 RPDCGEN—Root Port Dynamic Clock Gating Enable
Register (PCI Express—D28:F0/F1/F2/F3/F4/F5/F6/F7) ............................ 857
19.1.53 PECR3—PCI Express* Configuration Register 3
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 858
19.1.54 UES—Uncorrectable Error Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 859
19.1.55 UEM—Uncorrectable Error Mask Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 860
19.1.56 UEV—Uncorrectable Error Severity Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 861
19.1.57 CES—Correctable Error Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 862
19.1.58 CEM—Correctable Error Mask Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 862
19.1.59 AECC—Advanced Error Capabilities and Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 863
19.1.60 RES—Root Error Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 863
19.1.61 PECR2—PCI Express* Configuration Register 2
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 864
19.1.62 PEETM—PCI Express* Extended Test Mode Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 864
19.1.63 PEC1—PCI Express* Configuration Register 1
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) ....................................... 864
26 Datasheet
20 High Precision Event Timer Registers .................................................................... 865
20.1 Memory Mapped Registers................................................................................ 865
20.1.1 GCAP_ID—General Capabilities and Identification Register ........................ 867
20.1.2 GEN_CONF—General Configuration Register ........................................... 867
20.1.3 GINTR_STA—General Interrupt Status Register ....................................... 868
20.1.4 MAIN_CNT—Main Counter Value Register ............................................... 868
20.1.5 TIMn_CONF—Timer n Configuration and Capabilities Register.................... 869
20.1.6 TIMn_COMP—Timer n Comparator Value Register.................................... 872
20.1.7 TIMERn_PROCMSG_ROUT—Timer n Processor Message
Interrupt Rout Register ........................................................................ 873
21 Serial Peripheral Interface (SPI) ........................................................................... 875
21.1 Serial Peripheral Interface Memory Mapped Configuration Registers ....................... 875
21.1.1 BFPR –BIOS Flash Primary Region Register
(SPI Memory Mapped Configuration Registers) ........................................ 877
21.1.2 HSFS—Hardware Sequencing Flash Status Register
(SPI Memory Mapped Configuration Registers) ........................................ 877
21.1.3 HSFC—Hardware Sequencing Flash Control Register
(SPI Memory Mapped Configuration Registers) ........................................ 879
21.1.4 FADDR—Flash Address Register
(SPI Memory Mapped Configuration Registers) ........................................ 879
21.1.5 FDATA0—Flash Data 0 Register
(SPI Memory Mapped Configuration Registers) ........................................ 880
21.1.6 FDATAN—Flash Data [N] Register
(SPI Memory Mapped Configuration Registers) ........................................ 880
21.1.7 FRAP—Flash Regions Access Permissions Register
(SPI Memory Mapped Configuration Registers) ........................................ 881
21.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register
(SPI Memory Mapped Configuration Registers) ........................................ 882
21.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register
(SPI Memory Mapped Configuration Registers) ........................................ 882
21.1.10 FREG2—Flash Region 2 (Intel® ME) Register
(SPI Memory Mapped Configuration Registers) ........................................ 883
21.1.11 FREG3—Flash Region 3 (GbE) Register
(SPI Memory Mapped Configuration Registers) ........................................ 883
21.1.12 FREG4—Flash Region 4 (Platform Data) Register
(SPI Memory Mapped Configuration Registers) ........................................ 884
21.1.13 PR0—Protected Range 0 Register
(SPI Memory Mapped Configuration Registers) ........................................ 884
21.1.14 PR1—Protected Range 1 Register
(SPI Memory Mapped Configuration Registers) ........................................ 885
21.1.15 PR2—Protected Range 2 Register
(SPI Memory Mapped Configuration Registers) ........................................ 885
21.1.16 PR3—Protected Range 3 Register
(SPI Memory Mapped Configuration Registers) ........................................ 886
21.1.17 PR4—Protected Range 4 Register
(SPI Memory Mapped Configuration Registers) ........................................ 886
21.1.18 SSFS—Software Sequencing Flash Status Register
(SPI Memory Mapped Configuration Registers) ........................................ 887
21.1.19 SSFC—Software Sequencing Flash Control Register
(SPI Memory Mapped Configuration Registers) ........................................ 888
21.1.20 PREOP—Prefix Opcode Configuration Register
(SPI Memory Mapped Configuration Registers) ........................................ 889
21.1.21 OPTYPE—Opcode Type Configuration Register
(SPI Memory Mapped Configuration Registers) ........................................ 889
21.1.22 OPMENU—Opcode Menu Configuration Register
(SPI Memory Mapped Configuration Registers) ........................................ 890
21.1.23 BBAR—BIOS Base Address Configuration Register
(SPI Memory Mapped Configuration Registers) ........................................ 890
21.1.24 FDOC—Flash Descriptor Observability Control Register
(SPI Memory Mapped Configuration Registers) ........................................ 891
21.1.25 FDOD—Flash Descriptor Observability Data Register
(SPI Memory Mapped Configuration Registers) ........................................ 891
21.1.26 AFC—Additional Flash Control Register
(SPI Memory Mapped Configuration Registers) ........................................ 892
21.1.27 LVSCC—Host Lower Vendor Specific Component Capabilities Register
(SPI Memory Mapped Configuration Registers) ........................................ 892
Datasheet 27
21.1.28 UVSCC—Host Upper Vendor Specific Component Capabilities Register
(SPI Memory Mapped Configuration Registers) ........................................ 894
21.1.29 FPB—Flash Partition Boundary Register
(SPI Memory Mapped Configuration Registers) ........................................ 895
21.1.30 SRDL—Soft Reset Data Lock Register
(SPI Memory Mapped Configuration Registers) ........................................ 895
21.1.31 SRDC—Soft Reset Data Control Register
(SPI Memory Mapped Configuration Registers) ........................................ 896
21.1.32 SRD—Soft Reset Data Register
(SPI Memory Mapped Configuration Registers) ........................................ 896
21.2 Flash Descriptor Records................................................................................... 896
21.3 OEM Section ................................................................................................... 896
21.4 GbE SPI Flash Program Registers ....................................................................... 897
21.4.1 GLFPR –Gigabit LAN Flash Primary Region Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 898
21.4.2 HSFS—Hardware Sequencing Flash Status Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 898
21.4.3 HSFC—Hardware Sequencing Flash Control Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 900
21.4.4 FADDR—Flash Address Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 900
21.4.5 FDATA0—Flash Data 0 Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 901
21.4.6 FRAP—Flash Regions Access Permissions Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 901
21.4.7 FREG0—Flash Region 0 (Flash Descriptor) Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 902
21.4.8 FREG1—Flash Region 1 (BIOS Descriptor) Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 902
21.4.9 FREG2—Flash Region 2 (Intel® ME) Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 902
21.4.10 FREG3—Flash Region 3 (GbE) Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 903
21.4.11 PR0—Protected Range 0 Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 903
21.4.12 PR1—Protected Range 1 Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 904
21.4.13 SSFS—Software Sequencing Flash Status Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 905
21.4.14 SSFC—Software Sequencing Flash Control Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 906
21.4.15 PREOP—Prefix Opcode Configuration Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 907
21.4.16 OPTYPE—Opcode Type Configuration Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 907
21.4.17 OPMENU—Opcode Menu Configuration Register
(GbE LAN Memory Mapped Configuration Registers) ................................. 908
22 Thermal Sensor Registers (D31:F6) ....................................................................... 909
22.1 PCI Bus Configuration Registers......................................................................... 909
22.1.1 VID—Vendor Identification Register ....................................................... 910
22.1.2 DID—Device Identification Register ........................................................ 910
22.1.3 CMD—Command Register ..................................................................... 910
22.1.4 STS—Status Register ........................................................................... 911
22.1.5 RID—Revision Identification Register...................................................... 911
22.1.6 PI—Programming Interface Register....................................................... 911
22.1.7 SCC—Sub Class Code Register .............................................................. 912
22.1.8 BCC—Base Class Code Register ............................................................. 912
22.1.9 CLS—Cache Line Size Register .............................................................. 912
22.1.10 LT—Latency Timer Register................................................................... 912
22.1.11 HTYPE—Header Type Register ............................................................... 912
22.1.12 TBAR—Thermal Base Register ............................................................... 913
22.1.13 TBARH—Thermal Base High DWord Register............................................ 913
22.1.14 SVID—Subsystem Vendor ID Register .................................................... 913
22.1.15 SID—Subsystem ID Register ................................................................. 914
22.1.16 CAP_PTR—Capabilities Pointer Register................................................... 914
22.1.17 INTLN—Interrupt Line Register .............................................................. 914
28 Datasheet
22.1.18 INTPN—Interrupt Pin Register ............................................................... 914
22.1.19 TBARB—BIOS Assigned Thermal Base Address Register............................ 915
22.1.20 TBARBH—BIOS Assigned Thermal Base High
DWord Register .................................................................................. 915
22.1.21 PID—PCI Power Management Capability ID Register ................................ 915
22.1.22 PC—Power Management Capabilities Register.......................................... 916
22.1.23 PCS—Power Management Control And Status Register ............................. 916
22.2 Thermal Memory Mapped Configuration Registers
(Thermal Sensor – D31:F26) ............................................................................ 917
22.2.1 TEMP—Temperature Register ................................................................ 917
22.2.2 TSC—Thermal Sensor Control Register................................................... 918
22.2.3 TSS—Thermal Sensor Status Register .................................................... 918
22.2.4 TSEL—Thermal Sensor Enable and Lock Register ..................................... 919
22.2.5 TSREL—Thermal Sensor Reporting Enable and Lock Register..................... 919
22.2.6 TSMIC—Thermal Sensor SMI Control Register ......................................... 919
22.2.7 CTT—Catastrophic Trip Point Register .................................................... 920
22.2.8 TAHV—Thermal Alert High Value Register ............................................... 920
22.2.9 TALV—Thermal Alert Low Value Register ................................................ 920
22.2.10 TL—Throttle Levels Register ................................................................. 921
22.2.11 PHL—PCH Hot Level Register ................................................................ 922
22.2.12 PHLC—PHL Control Register.................................................................. 922
22.2.13 TAS—Thermal Alert Status Register ....................................................... 922
22.2.14 TSPIEN—PCI Interrupt Event Enables Register ........................................ 923
22.2.15 TSGPEN—General Purpose Event Enables Register................................... 923
23 Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0]) .......... 925
23.1 First Intel® Management Engine Interface (Intel® MEI) Configuration
Registers (Intel® MEI 1—D22:F0)...................................................................... 925
23.1.1 PCI Configuration Registers (Intel® MEI 1—D22:F0) ................................ 925
23.1.1.1 VID—Vendor Identification Register
(Intel® MEI 1—D22:F0) ......................................................... 926
23.1.1.2 DID—Device Identification Register
(Intel® MEI 1—D22:F0) ......................................................... 926
23.1.1.3 PCICMD—PCI Command Register
(Intel® MEI 1—D22:F0) ......................................................... 927
23.1.1.4 PCISTS—PCI Status Register
(Intel® MEI 1—D22:F0) ......................................................... 927
23.1.1.5 RID—Revision Identification Register
(Intel® MEI 1—D22:F0) ......................................................... 928
23.1.1.6 CC—Class Code Register
(Intel® MEI 1—D22:F0) ......................................................... 928
23.1.1.7 HTYPE—Header Type Register
(Intel® MEI 1—D22:F0) ......................................................... 928
23.1.1.8 MEI0_MBAR—Intel® MEI 1 MMIO Base Address
(Intel® MEI 1—D22:F0) ......................................................... 928
23.1.1.9 SVID—Subsystem Vendor ID Register
(Intel® MEI 1—D22:F0) ......................................................... 929
23.1.1.10 SID—Subsystem ID Register
(Intel® MEI 1—D22:F0) ......................................................... 929
23.1.1.11 CAPP—Capabilities List Pointer Register
(Intel® MEI 1—D22:F0) ......................................................... 929
23.1.1.12 INTR—Interrupt Information Register
(Intel® MEI 1—D22:F0) ......................................................... 929
23.1.1.13 HFS—Host Firmware Status Register
(Intel® MEI 1—D22:F0) ......................................................... 930
23.1.1.14 ME_UMA—Intel® Management Engine UMA Register
(Intel® MEI 1—D22:F0) ......................................................... 930
23.1.1.15 GMES—General Intel® ME Status Register
(Intel® MEI 1—D22:F0) ......................................................... 930
23.1.1.16 H_GS—Host General Status Register
(Intel® MEI 1—D22:F0) ......................................................... 931
23.1.1.17 PID—PCI Power Management Capability ID Register
(Intel® MEI 1—D22:F0) ......................................................... 931
23.1.1.18 PC—PCI Power Management Capabilities Register
(Intel® MEI 1—D22:F0) ......................................................... 931
23.1.1.19 PMCS—PCI Power Management Control and Status
Register (Intel® MEI 1—D22:F0) ............................................. 932
Datasheet 29
23.1.1.20 GMES2—General Intel® ME Status Register 2
(Intel® MEI 1—D22:F0).......................................................... 932
23.1.1.21 GMES3—General Intel® ME Status Register 3
(Intel® MEI 1—D22:F0).......................................................... 932
23.1.1.22 GMES4—General Intel® ME Status Register 4
(Intel® MEI 1—D22:F0).......................................................... 933
23.1.1.23 GMES5—General Intel® ME Status Register 5
(Intel® MEI 1—D22:F0).......................................................... 933
23.1.1.24 H_GS2—Host General Status Register 2
(Intel® MEI 1—D22:F0).......................................................... 933
23.1.1.25 H_GS3—Host General Status Register 3
(Intel® MEI 1—D22:F0).......................................................... 933
23.1.1.26 MID—Message Signaled Interrupt Identifiers Register
(Intel® MEI 1—D22:F0).......................................................... 933
23.1.1.27 MC—Message Signaled Interrupt Message Control Register
(Intel® MEI 1—D22:F0).......................................................... 934
23.1.1.28 MA—Message Signaled Interrupt Message Address Register
(Intel® MEI 1—D22:F0).......................................................... 934
23.1.1.29 MUA—Message Signaled Interrupt Upper Address Register
(Intel® MEI 1—D22:F0).......................................................... 934
23.1.1.30 MD—Message Signaled Interrupt Message Data Register
(Intel® MEI 1—D22:F0).......................................................... 934
23.1.1.31 HIDM—MEI Interrupt Delivery Mode Register
(Intel® MEI 1—D22:F0).......................................................... 935
23.1.1.32 HERES—Intel® MEI Extend Register Status
(Intel® MEI 1—D22:F0).......................................................... 935
23.1.1.33 HERX—Intel® MEI Extend Register DWX
(Intel® MEI 1—D22:F0).......................................................... 936
23.1.2 MEI0_MBAR—Intel® MEI 1 MMIO Registers ............................................. 936
23.1.2.1 H_CB_WW—Host Circular Buffer Write Window Register
(Intel® MEI 1 MMIO Register) ................................................. 936
23.1.2.2 H_CSR—Host Control Status Register
(Intel® MEI 1 MMIO Register) ................................................. 937
23.1.2.3 ME_CB_RW—Intel® ME Circular Buffer Read Window Register
(Intel® MEI 1 MMIO Register) ................................................. 938
23.1.2.4 ME_CSR_HA—Intel® ME Control Status Host Access Register
(Intel® MEI 1 MMIO Register) ................................................. 938
23.2 Second Intel® Management Engine Interface
(Intel® MEI 2) Configuration Registers
(Intel® MEI 2—D22:F1) .................................................................................... 939
23.2.1 PCI Configuration Registers (Intel® MEI 2—D22:F2)................................. 939
23.2.1.1 VID—Vendor Identification Register
(Intel® MEI 2—D22:F1).......................................................... 940
23.2.1.2 DID—Device Identification Register
(Intel® MEI 2—D22:F1).......................................................... 940
23.2.1.3 PCICMD—PCI Command Register
(Intel® MEI 2—D22:F1).......................................................... 941
23.2.1.4 PCISTS—PCI Status Register
(Intel® MEI 2—D22:F1).......................................................... 941
23.2.1.5 RID—Revision Identification Register
(Intel® MEI 2—D22:F1).......................................................... 942
23.2.1.6 CC—Class Code Register
(Intel® MEI 2—D22:F1).......................................................... 942
23.2.1.7 HTYPE—Header Type Register
(Intel® MEI 2—D22:F1).......................................................... 942
23.2.1.8 MEI1_MBAR—Intel MEI 2 MMIO Base Address
(Intel® MEI 2—D22:F1).......................................................... 943
23.2.1.9 SVID—Subsystem Vendor ID Register
(Intel® MEI 2—D22:F1).......................................................... 943
23.2.1.10 SID—Subsystem ID Register
(Intel® MEI 2—D22:F1).......................................................... 943
23.2.1.11 CAPP—Capabilities List Pointer Register
(Intel® MEI 2—D22:F1).......................................................... 944
23.2.1.12 INTR—Interrupt Information Register
(Intel® MEI 2—D22:F1).......................................................... 944
23.2.1.13 HFS—Host Firmware Status Register
(Intel® MEI 2—D22:F1).......................................................... 944
30 Datasheet
23.2.1.14 GMES—General Intel® ME Status Register
(Intel® MEI 2—D22:F1) ......................................................... 944
23.2.1.15 H_GS—Host General Status Register
(Intel® MEI 2—D22:F1) ......................................................... 945
23.2.1.16 PID—PCI Power Management Capability ID Register
(Intel® MEI 2—D22:F1) ......................................................... 945
23.2.1.17 PC—PCI Power Management Capabilities Register
(Intel® MEI 2—D22:F1) ......................................................... 945
23.2.1.18 PMCS—PCI Power Management Control and Status
Register (Intel® MEI 2—D22:F1) ............................................. 946
23.2.1.19 GMES2—General Intel® ME Status Register 2
(Intel® MEI 2—D22:F1) ......................................................... 946
23.2.1.20 GMES3—General Intel® ME Status Register 3
(Intel® MEI 2—D22:F1) ......................................................... 946
23.2.1.21 GMES4—General Intel® ME Status Register 4
(Intel® MEI 2—D22:F1) ......................................................... 947
23.2.1.22 GMES5—General Intel® ME Status Register 5
(Intel® MEI 2—D22:F1) ......................................................... 947
23.2.1.23 H_GS2—Host General Status Register 2
(Intel® MEI 2—D22:F1) ......................................................... 947
23.2.1.24 H_GS3—Host General Status Register 3
(Intel® MEI 2—D22:F1) ......................................................... 947
23.2.1.25 MID—Message Signaled Interrupt Identifiers Register
(Intel® MEI 2—D22:F1) ......................................................... 947
23.2.1.26 MC—Message Signaled Interrupt Message Control Register
(Intel® MEI 2—D22:F1) ......................................................... 948
23.2.1.27 MA—Message Signaled Interrupt Message Address Register
(Intel® MEI 2—D22:F1) ......................................................... 948
23.2.1.28 MUA—Message Signaled Interrupt Upper Address Register
(Intel® MEI 2—D22:F1) ......................................................... 948
23.2.1.29 MD—Message Signaled Interrupt Message Data Register
(Intel® MEI 2—D22:F1) ......................................................... 949
23.2.1.30 HIDM—Intel® MEI Interrupt Delivery Mode Register
(Intel® MEI 2—D22:F1) ......................................................... 949
23.2.1.31 HERES—Intel® MEI Extend Register Status
(Intel® MEI 2—D22:F1) ......................................................... 949
23.2.1.32 HERX—Intel® MEI Extend Register DWX
(Intel® MEI 2—D22:F1) ......................................................... 950
23.2.2 MEI1_MBAR—Intel® MEI 2 MMIO Registers............................................. 950
23.2.2.1 H_CB_WW—Host Circular Buffer Write Window
(Intel® MEI 2 MMIO Register) ................................................. 950
23.2.2.2 H_CSR—Host Control Status Register
(Intel® MEI 2 MMIO Register) ................................................. 951
23.2.2.3 ME_CB_RW—Intel® ME Circular Buffer Read Window Register
(Intel® MEI 2 MMIO Register) ................................................. 952
23.2.2.4 ME_CSR_HA—Intel® ME Control Status Host Access Register
(Intel® MEI 2 MMIO Register) ................................................. 952
23.3 IDE Redirect IDER Registers (IDER—D22:F2) ...................................................... 953
23.3.1 PCI Configuration Registers (IDER—D22:F2) ........................................... 953
23.3.1.1 VID—Vendor Identification Register (IDER—D22:F2).................. 954
23.3.1.2 DID—Device Identification Register (IDER—D22:F2) .................. 954
23.3.1.3 PCICMD—PCI Command Register (IDER—D22:F2) ..................... 954
23.3.1.4 PCISTS—PCI Device Status Register (IDER—D22:F2)................. 955
23.3.1.5 RID—Revision Identification Register (IDER—D22:F2) ................ 955
23.3.1.6 CC—Class Codes Register (IDER—D22:F2) ............................... 955
23.3.1.7 CLS—Cache Line Size Register (IDER—D22:F2)......................... 955
23.3.1.8 PCMdBA—Primary Command Block IO Bar
Register (IDER—D22:F2) ....................................................... 956
23.3.1.9 PCTLBA—Primary Control Block Base Address
Register (IDER—D22:F2) ....................................................... 956
23.3.1.10 SCMdBA—Secondary Command Block Base Address
Register (IDER—D22:F2) ....................................................... 956
23.3.1.11 SCTLBA—Secondary Control Block base Address
Register (IDER—D22:F2) ....................................................... 957
23.3.1.12 LBAR—Legacy Bus Master Base Address Register
(IDER—D22:F2).................................................................... 957
23.3.1.13 SVID—Subsystem Vendor ID Register (IDER—D22:F2) .............. 957
Datasheet 31
23.3.1.14 SID—Subsystem ID Register (IDER—D22:F2)............................ 957
23.3.1.15 CAPP—Capabilities List Pointer Register
(IDER—D22:F2) .................................................................... 958
23.3.1.16 INTR—Interrupt Information Register
(IDER—D22:F2) .................................................................... 958
23.3.1.17 PID—PCI Power Management Capability ID Register
(IDER—D22:F2) .................................................................... 958
23.3.1.18 PC—PCI Power Management Capabilities Register
(IDER—D22:F2) .................................................................... 959
23.3.1.19 PMCS—PCI Power Management Control and Status
Register (IDER—D22:F2) ........................................................ 959
23.3.1.20 MID—Message Signaled Interrupt Capability ID
Register (IDER—D22:F2) ........................................................ 960
23.3.1.21 MC—Message Signaled Interrupt Message Control
Register (IDER—D22:F2) ........................................................ 960
23.3.1.22 MA—Message Signaled Interrupt Message Address
Register (IDER—D22:F2) ........................................................ 960
23.3.1.23 MAU—Message Signaled Interrupt Message Upper
Address Register (IDER—D22:F2) ............................................ 960
23.3.1.24 MD—Message Signaled Interrupt Message Data
Register (IDER—D22:F2) ........................................................ 961
23.3.2 IDER BAR0 Registers ........................................................................... 961
23.3.2.1 IDEDATA—IDE Data Register (IDER—D22:F2) ........................... 962
23.3.2.2 IDEERD1—IDE Error Register DEV1
(IDER—D22:F2) .................................................................... 962
23.3.2.3 IDEERD0—IDE Error Register DEV0
(IDER—D22:F2) .................................................................... 963
23.3.2.4 IDEFR—IDE Features Register
(IDER—D22:F2) .................................................................... 963
23.3.2.5 IDESCIR—IDE Sector Count In Register
(IDER—D22:F2) .................................................................... 963
23.3.2.6 IDESCOR1—IDE Sector Count Out Register Device 1
Register (IDER—D22:F2) ........................................................ 964
23.3.2.7 IDESCOR0—IDE Sector Count Out Register Device
0 Register (IDER—D22:F2) ..................................................... 964
23.3.2.8 IDESNOR0—IDE Sector Number Out Register
Device 0 Register (IDER—D22:F2) ........................................... 964
23.3.2.9 IDESNOR1—IDE Sector Number Out Register
Device 1 Register (IDER—D22:F2) ........................................... 965
23.3.2.10 IDESNIR—IDE Sector Number In Register (IDER—D22:F2) ......... 965
23.3.2.11 IDECLIR—IDE Cylinder Low In Register (IDER—D22:F2) ............. 965
23.3.2.12 IDCLOR1—IDE Cylinder Low Out Register Device 1
Register (IDER—D22:F2) ........................................................ 966
23.3.2.13 IDCLOR0—IDE Cylinder Low Out Register Device 0
Register (IDER—D22:F2) ........................................................ 966
23.3.2.14 IDCHOR0—IDE Cylinder High Out Register Device 0
Register (IDER—D22:F2) ........................................................ 966
23.3.2.15 IDCHOR1—IDE Cylinder High Out Register Device 1
Register (IDER—D22:F2) ........................................................ 967
23.3.2.16 IDECHIR—IDE Cylinder High In Register
(IDER—D22:F2) .................................................................... 967
23.3.2.17 IDEDHIR—IDE Drive/Head In Register
(IDER—D22:F2) .................................................................... 967
23.3.2.18 IDDHOR1—IDE Drive Head Out Register Device 1
Register (IDER—D22:F2) ........................................................ 968
23.3.2.19 IDDHOR0—IDE Drive Head Out Register Device 0
Register (IDER—D22:F2) ........................................................ 968
23.3.2.20 IDESD0R—IDE Status Device 0 Register
(IDER—D22:F2) .................................................................... 969
23.3.2.21 IDESD1R—IDE Status Device 1 Register
(IDER—D22:F2) .................................................................... 970
23.3.2.22 IDECR—IDE Command Register (IDER—D22:F2) ....................... 970
23.3.3 IDER BAR1 Registers ........................................................................... 971
23.3.3.1 IDDCR—IDE Device Control Register (IDER—D22:F2)................. 971
23.3.3.2 IDASR—IDE Alternate Status Register (IDER—D22:F2)............... 971
23.3.4 IDER BAR4 Registers ........................................................................... 972
32 Datasheet
23.3.4.1 IDEPBMCR—IDE Primary Bus Master Command
Register (IDER—D22:F2) ....................................................... 973
23.3.4.2 IDEPBMDS0R—IDE Primary Bus Master Device
Specific 0 Register (IDER—D22:F2) ......................................... 973
23.3.4.3 IDEPBMSR—IDE Primary Bus Master Status
Register (IDER—D22:F2) ....................................................... 974
23.3.4.4 IDEPBMDS1R—IDE Primary Bus Master Device
Specific 1 Register (IDER—D22:F2) ......................................... 974
23.3.4.5 IDEPBMDTPR0—IDE Primary Bus Master Descriptor
Table Pointer Byte 0 Register (IDER—D22:F2) .......................... 974
23.3.4.6 IDEPBMDTPR1—IDE Primary Bus Master Descriptor
Table Pointer Byte 1 Register (IDER—D22:F2) .......................... 975
23.3.4.7 IDEPBMDTPR2—IDE Primary Bus Master Descriptor
Table Pointer Byte 2 Register (IDER—D22:F2) .......................... 975
23.3.4.8 IDEPBMDTPR3—IDE Primary Bus Master Descriptor
Table Pointer Byte 3 Register (IDER—D22:F2) .......................... 975
23.3.4.9 IDESBMCR—IDE Secondary Bus Master Command
Register (IDER—D22:F2) ....................................................... 976
23.3.4.10 IDESBMDS0R—IDE Secondary Bus Master Device
Specific 0 Register (IDER—D22:F2) ......................................... 976
23.3.4.11 IDESBMSR—IDE Secondary Bus Master Status
Register (IDER—D22:F2) ....................................................... 977
23.3.4.12 IDESBMDS1R—IDE Secondary Bus Master Device
Specific 1 Register (IDER—D22:F2) ......................................... 977
23.3.4.13 IDESBMDTPR0—IDE Secondary Bus Master Descriptor
Table Pointer Byte 0 Register (IDER—D22:F2) .......................... 977
23.3.4.14 IDESBMDTPR1—IDE Secondary Bus Master Descriptor
Table Pointer Byte 1 Register (IDER—D22:F2) .......................... 978
23.3.4.15 IDESBMDTPR2—IDE Secondary Bus Master Descriptor
Table Pointer Byte 2 Register (IDER—D22:F2) .......................... 978
23.3.4.16 IDESBMDTPR3—IDE Secondary Bus Master Descriptor
Table Pointer Byte 3 Register (IDER—D22:F2) .......................... 978
23.4 Serial Port for Remote Keyboard and Text (KT)
Redirection (KT—D22:F3) ................................................................................. 979
23.4.1 PCI Configuration Registers (KT—D22:F3) .............................................. 979
23.4.1.1 VID—Vendor Identification Register (KT—D22:F3) ..................... 980
23.4.1.2 DID—Device Identification Register (KT—D22:F3) ..................... 980
23.4.1.3 CMD—Command Register (KT—D22:F3)................................... 980
23.4.1.4 STS—Device Status Register (KT—D22:F3)............................... 981
23.4.1.5 RID—Revision ID Register (KT—D22:F3) .................................. 981
23.4.1.6 CC—Class Codes Register (KT—D22:F3)................................... 981
23.4.1.7 CLS—Cache Line Size Register (KT—D22:F3) ............................ 982
23.4.1.8 KTIBA—KT IO Block Base Address Register
(KT—D22:F3) ....................................................................... 982
23.4.1.9 KTMBA—KT Memory Block Base Address Register
(KT—D22:F3) ....................................................................... 982
23.4.1.10 SVID—Subsystem Vendor ID Register (KT—D22:F3).................. 983
23.4.1.11 SID—Subsystem ID Register (KT—D22:F3) .............................. 983
23.4.1.12 CAP—Capabilities Pointer Register (KT—D22:F3) ....................... 983
23.4.1.13 INTR—Interrupt Information Register (KT—D22:F3) .................. 983
23.4.1.14 PID—PCI Power Management Capability ID Register
(KT—D22:F3) ....................................................................... 984
23.4.1.15 PC—PCI Power Management Capabilities ID Register
(KT—D22:F3) ....................................................................... 984
23.4.1.16 MID—Message Signaled Interrupt Capability ID
Register (KT—D22:F3)........................................................... 985
23.4.1.17 MC—Message Signaled Interrupt Message Control
Register (KT—D22:F3)........................................................... 985
23.4.1.18 MA—Message Signaled Interrupt Message Address
Register (KT—D22:F3)........................................................... 985
23.4.1.19 MAU—Message Signaled Interrupt Message Upper
Address Register (KT—D22:F3)............................................... 986
23.4.1.20 MD—Message Signaled Interrupt Message Data
Register (KT—D22:F3)........................................................... 986
23.4.2 KT IO/Memory Mapped Device Registers ................................................ 986
23.4.2.1 KTRxBR—KT Receive Buffer Register (KT—D22:F3).................... 987
23.4.2.2 KTTHR—KT Transmit Holding Register (KT—D22:F3).................. 987
Datasheet 33
23.4.2.3 KTDLLR—KT Divisor Latch LSB Register (KT—D22:F3) ................ 987
23.4.2.4 KTIER—KT Interrupt Enable Register (KT—D22:F3) .................... 988
23.4.2.5 KTDLMR—KT Divisor Latch MSB Register (KT—D22:F3) .............. 988
23.4.2.6 KTIIR—KT Interrupt Identification Register
(KT—D22:F3) ....................................................................... 989
23.4.2.7 KTFCR—KT FIFO Control Register (KT—D22:F3) ........................ 989
23.4.2.8 KTLCR—KT Line Control Register (KT—D22:F3) ......................... 990
23.4.2.9 KTMCR—KT Modem Control Register (KT—D22:F3) .................... 990
23.4.2.10 KTLSR—KT Line Status Register (KT—D22:F3) .......................... 991
23.4.2.11 KTMSR—KT Modem Status Register (KT—D22:F3) ..................... 992
Figures
2-1 PCH Interface Signals Block Diagram (not all signals are on all SKUs)..........................64
2-2 Example External RTC Circuit.................................................................................77
4-1 PCH Detailed Clock Diagram ................................................................................ 129
5-1 Flexible I/O – High Speed Signal Mapping with PCI Express*, USB 3.0*, and
SATA Ports ........................................................................................................ 149
5-2 Generation of SERR# to Platform ......................................................................... 154
5-3 Valid PCI Express* Ports for Platform LAN Connect Device (GbE) Support .................. 157
5-4 LPC Interface Diagram ........................................................................................ 165
5-5 PCH DMA Controller............................................................................................ 170
5-6 DMA Request Assertion through LDRQ# ................................................................ 173
5-7 Conceptual Diagram of SLP_LAN# ........................................................................ 219
5-8 TCO Legacy/Compatible Mode SMBus Configuration ................................................ 226
5-9 Advanced TCO Mode ........................................................................................... 227
5-10 Serial Post over GPIO Reference Circuit ................................................................. 229
5-11 Flow for Port Enable / Device Present Bits.............................................................. 238
5-12 Serial Data transmitted over the SGPIO Interface ................................................... 242
5-13 EHCI with USB 2.0 with Rate Matching Hub ........................................................... 257
5-14 PCH Intel® Management Engine (Intel® ME) High-Level Block Diagram ..................... 284
5-15 Flash Descriptor Sections .................................................................................... 288
5-16 PCH Display Architecture ..................................................................................... 298
5-17 Analog Port Characteristics .................................................................................. 299
5-18 Panel Power Sequencing ..................................................................................... 302
6-1 Desktop/Server PCH Ballout (Top View - Upper Left) ............................................... 306
6-2 Desktop/Server PCH Ballout (Top View - Lower Left) ............................................... 306
6-3 Desktop/Server PCH Ballout (Top View - Upper Right) ............................................. 307
6-4 Desktop/Server PCH Ballout (Top View - Lower Right) ............................................. 307
6-5 Mobile PCH Ballout (Top View - Upper Left)............................................................ 314
6-6 Mobile PCH Ballout (Top View - Lower Left)............................................................ 314
6-7 Mobile PCH Ballout (Top View - Upper Right).......................................................... 315
6-8 Mobile PCH Ballout (Top View - Lower Right).......................................................... 315
7-1 Tape and Reel Pin 1 Location ............................................................................... 323
7-2 Desktop / Server PCH Package Drawing ................................................................ 324
7-3 Tape and Reel Pin 1 Location ............................................................................... 325
7-4 Mobile PCH Package Drawing ............................................................................... 326
8-1 G3 w/RTC Loss to S4/S5 (With Deep Sx Support) Timing Diagram ............................ 361
8-2 G3 w/RTC Loss to S4/S5 (Without Deep Sx Support) Timing Diagram ....................... 361
8-3 S5 to S0 Timing Diagram .................................................................................... 362
8-4 S3/M3 to S0 Timing Diagram ............................................................................... 363
8-5 S5/Moff - S5/M3 Timing Diagram ......................................................................... 363
8-6 S0 to S5 Timing Diagram .................................................................................... 364
8-7 S3/S4/S5 to Deep Sx to G3 w/ RTC Loss Timing Diagram ........................................ 365
8-8 G3 to Deep Sx Timing Diagram ............................................................................ 365
8-9 DRAMPWROK Timing Diagram.............................................................................. 366
8-10 Clock Cycle Time................................................................................................ 367
8-11 Transmitting Position (Data to Strobe) .................................................................. 367
8-12 Clock Timing...................................................................................................... 367
8-13 Valid Delay from Rising Clock Edge ....................................................................... 368
8-14 Setup and Hold Times......................................................................................... 368
8-15 Float Delay........................................................................................................ 368
8-16 Pulse Width ....................................................................................................... 368
8-17 Output Enable Delay........................................................................................... 369
8-18 USB Rise and Fall Times ...................................................................................... 369
8-19 USB Jitter ......................................................................................................... 369
34 Datasheet
8-20 USB EOP Width ................................................................................................. 370
8-21 SMBus / SMLink Transaction................................................................................ 370
8-22 SMBus / SMLink Timeout .................................................................................... 370
8-23 SPI Timings ...................................................................................................... 371
8-24 Intel® High Definition Audio (Intel® HD Audio) Input and Output Timings.................. 371
8-25 Dual Channel Interface Timings ........................................................................... 372
8-26 Dual Channel Interface Timings ........................................................................... 372
8-27 LVDS Load and Transition Times .......................................................................... 372
8-28 Transmitting Position (Data to Strobe).................................................................. 373
8-29 PCI Express* Transmitter Eye.............................................................................. 373
8-30 PCI Express* Receiver Eye .................................................................................. 374
8-31 Measurement Points for Differential Waveforms ..................................................... 375
8-32 PCH Test Load ................................................................................................... 376
8-33 Controller Link Receive Timings ........................................................................... 376
8-34 Controller Link Receive Slew Rate ....................................................................... 376
8-35 PCH Suspend Well Ramp Up/Down Requirement .................................................... 376
8-36 Sequencing Requirements between PCH VCCSUS (1.05V) and External USB Vbus ...... 377
8-37 Sequencing Requirements between PCH VCC3_3 and VCC Core Rail ......................... 377
8-38 Sequencing Requirements between PCH VCC1_5 and VCC Core Rail ......................... 377
Tables
1-1 Industry Specifications ......................................................................................... 43
1-2 Desktop Intel® 8 Series Chipset Family SKUs .......................................................... 54
1-3 Desktop Intel® 8 Series Chipset Family SKUs Flexible I/O Map................................... 55
1-4 Mobile Intel® 8 Series Chipset Family SKUs............................................................. 56
1-5 Mobile Intel® 8 Series Chipset Family SKUs Flexible I/O Map ..................................... 57
1-6 Server / Workstation Intel® C220 Series Chipset Family SKUs ................................... 58
1-7 Server / Workstation Intel® C220 Series Chipset Family SKUs Flexible I/O Map............ 59
1-8 PCH Device and Revision ID Table.......................................................................... 60
2-1 I/O Flexibility Signal Mapping ................................................................................ 65
2-2 USB Interface Signals........................................................................................... 66
2-3 PCI Express* Signals............................................................................................ 70
2-4 Serial ATA Interface Signals .................................................................................. 72
2-5 Clock Interface Signals ......................................................................................... 75
2-6 Real Time Clock Interface ..................................................................................... 77
2-7 Interrupt Signals ................................................................................................. 78
2-8 Processor Interface Signals ................................................................................... 78
2-9 Direct Media Interface Signals ............................................................................... 79
2-10 Intel® Flexible Display Interface (Intel® FDI) Signals................................................ 79
2-11 Analog Display Interface Signals ............................................................................ 80
2-12 Digital Display Signals .......................................................................................... 81
2-13 Embedded DisplayPort* (eDP*) backlight control signals ........................................... 81
2-14 Intel® High Definition Audio (Intel® HD Audio) Link Signals....................................... 82
2-15 Low Pin Count (LPC) Interface Signals .................................................................... 83
2-16 General Purpose I/O Signals.................................................................................. 84
2-17 Functional Strap Definitions................................................................................... 91
2-18 SMBus Interface Signals ....................................................................................... 95
2-19 System Management Interface Signals ................................................................... 95
2-20 Controller Link Signals.......................................................................................... 96
2-21 Serial Peripheral Interface (SPI) Signals.................................................................. 96
2-22 MGPIO Conversion Table....................................................................................... 98
2-23 Client Manageability Signals .................................................................................. 98
2-24 Server Manageability Signals................................................................................. 99
2-25 Power Management Interface Signals ..................................................................... 99
2-26 Power and Ground Signals .................................................................................. 103
2-27 Thermal Signals................................................................................................. 104
2-28 Miscellaneous Signals ......................................................................................... 105
2-29 Testability Signals.............................................................................................. 106
2-30 Test Pins .......................................................................................................... 107
3-1 Integrated Pull-Up and Pull-Down Resistors ........................................................... 109
3-2 Output Signals - Power Plane and States in Desktop, Mobile and Server Configurations 113
3-3 Input Signals - Power Plane and States in Desktop and Mobile Configurations ............ 119
4-1 PCH Clock Inputs ............................................................................................... 126
4-2 Clock Outputs ................................................................................................... 126
4-3 PCH PLLs .......................................................................................................... 127
4-4 Modulator Blocks ............................................................................................... 128
Datasheet 35
4-1 ICC Registers under Intel® Management Engine (Intel® ME) Control ......................... 130
5-1 PCI Express* Ports 1 thru 4 - Supported Configurations .......................................... 151
5-2 PCI Express* Ports 5 thru 8 - Supported Configurations .......................................... 151
5-3 MSI versus PCI IRQ Actions ................................................................................. 152
5-4 LAN Mode Support.............................................................................................. 160
5-5 LPC Cycle Types Supported ................................................................................. 165
5-6 Start Field Bit Definitions..................................................................................... 166
5-7 Cycle Type Bit Definitions .................................................................................... 166
5-8 Transfer Size Bit Definition .................................................................................. 167
5-9 SYNC Bit Definition ............................................................................................. 167
5-10 DMA Transfer Size .............................................................................................. 171
5-11 Address Shifting in 16-Bit I/O DMA Transfers ......................................................... 172
5-12 Counter Operating Modes .................................................................................... 177
5-13 Interrupt Controller Connections .......................................................................... 179
5-14 Interrupt Status Registers ................................................................................... 180
5-15 Content of Interrupt Vector Byte .......................................................................... 181
5-16 APIC Interrupt Mapping1 ..................................................................................... 186
5-17 Stop Frame Explanation ...................................................................................... 189
5-18 Data Frame Format ............................................................................................ 190
5-19 Configuration Bits Reset by RTCRST# Assertion...................................................... 193
5-20 INIT# Going Active............................................................................................. 194
5-21 NMI Sources...................................................................................................... 195
5-22 General Power States for Systems Using the PCH ................................................... 197
5-23 State Transition Rules for the PCH ........................................................................ 198
5-24 System Power Plane ........................................................................................... 199
5-25 Causes of SMI and SCI ....................................................................................... 200
5-26 Sleep Types....................................................................................................... 205
5-27 Causes of Wake Events ....................................................................................... 206
5-28 GPI Wake Events ............................................................................................... 207
5-29 Transitions Due to Power Failure .......................................................................... 208
5-30 Supported Deep Sx Policy Configurations............................................................... 209
5-31 Deep Sx Wake Events ......................................................................................... 210
5-32 Transitions Due to Power Button .......................................................................... 211
5-33 Transitions Due to RI# Signal .............................................................................. 212
5-34 Write Only Registers with Read Paths in ALT Access Mode........................................ 214
5-35 PIC Reserved Bits Return Values .......................................................................... 216
5-36 Register Write Accesses in ALT Access Mode .......................................................... 216
5-37 SUSPWRDNACK / SUSWARN# / GPIO30 Pin Behavior.............................................. 220
5-38 SUSPWRDNACK during Reset ............................................................................... 220
5-39 Causes of Host and Global Resets ......................................................................... 222
5-40 Event Transitions that Cause Messages ................................................................. 226
5-41 SATA Feature Support ........................................................................................ 232
5-42 SATA Features ................................................................................................... 233
5-43 Message Format................................................................................................. 240
5-44 Multi-activity LED Message Type........................................................................... 241
5-45 Legacy Replacement Routing ............................................................................... 244
5-46 EHC Resets ....................................................................................................... 247
5-47 Debug Port Behavior........................................................................................... 251
5-48 I2C* Block Read................................................................................................. 261
5-49 Enable for SMBALERT# ....................................................................................... 263
5-50 Enables for SMBus Slave Write and SMBus Host Events ........................................... 264
5-51 Enables for the Host Notify Command ................................................................... 264
5-52 Slave Write Registers.......................................................................................... 266
5-53 Command Types ................................................................................................ 266
5-54 Slave Read Cycle Format..................................................................................... 267
5-55 Data Values for Slave Read Registers.................................................................... 268
5-56 Host Notify Format ............................................................................................. 270
5-57 PCH Thermal Throttle States (T-states) ................................................................. 273
5-58 PCH Thermal Throttling Configuration Registers...................................................... 273
5-59 Region Size versus Erase Granularity of Flash Components ...................................... 287
5-60 Region Access Control Table ................................................................................ 289
5-61 Hardware Sequencing Commands and Opcode Requirements ................................... 292
5-62 Flash Protection Mechanism Summary .................................................................. 294
5-63 Recommended Pinout for 8-Pin Serial Flash Device ................................................. 295
5-64 Recommended Pinout for 16-Pin Serial Flash Device ............................................... 296
6-1 Desktop/Server PCH Ballout By Signal Name.......................................................... 308
6-2 Mobile PCH Ballout by Signal Name....................................................................... 316
36 Datasheet
8-1 Storage Conditions and Thermal Junction Operating Temperature Limits ................... 327
8-2 Mobile Thermal Design Power .............................................................................. 328
8-3 PCH Absolute Maximum Ratings........................................................................... 328
8-4 PCH Power Supply Range.................................................................................... 328
8-5 Measured Silicon ICC Estimates (Desktop and Mobile) ............................................. 329
8-6 Single-Ended Signal DC Characteristics as Inputs or Outputs ................................... 331
8-7 Differential Signal DC Characteristics.................................................................... 337
8-8 Other DC Characteristics..................................................................................... 341
8-9 Signal Groups ................................................................................................... 342
8-10 CRT DAC Signal Group DC Characteristics: Functional Operating Range
(VccADAC = 3.3 V ±5%) .................................................................................... 342
8-11 Display Port Auxiliary Signal Group DC Characteristics ............................................ 342
8-12 PCI Express* Interface Timings ........................................................................... 343
8-13 HDMI* Interface Timings (DDP[D:B][3:0]) ............................................................ 344
8-14 Intel® SDVO Interface Timings ............................................................................ 344
8-15 DisplayPort* Interface Timings (DDP[D:B][3:0]) .................................................... 345
8-16 DisplayPort* Aux Interface.................................................................................. 346
8-17 DDC Characteristics
DDC Signals: VGA_DDC_CLK, VGA_DDC_DATA, DDP[D:C]_CTRLCLK,
DDP[D:C]_CTRLDATA......................................................................................... 346
8-18 CRT DAC AC Characteristics ................................................................................ 347
8-19 Clock Timings.................................................................................................... 347
8-20 Universal Serial Bus Timing ................................................................................. 351
8-21 SATA Interface Timings ...................................................................................... 352
8-22 SMBus and SMLink Timing .................................................................................. 353
8-23 Intel® High Definition Audio (Intel® HD Audio) Timing ............................................ 354
8-24 LPC Timing ....................................................................................................... 354
8-25 Miscellaneous Timings ........................................................................................ 354
8-26 SPI Timings (20 MHz)......................................................................................... 355
8-27 SPI Timings (33 MHz)......................................................................................... 355
8-28 SPI Timings (50 MHz)......................................................................................... 356
8-29 SST Timings (Server/Workstation Only) ................................................................ 356
8-30 Controller Link Receive Timings ........................................................................... 357
8-31 USB 3.0 Interface Transmit and Receiver Timings .................................................. 357
8-32 Power Sequencing and Reset Signal Timings.......................................................... 358
8-33 Suspend Well Voltage Ramp Up/Down Requirements .............................................. 378
8-34 Core Well Voltage Ramp Up/Down Requirements ................................................... 378
9-1 PCI Devices and Functions .................................................................................. 380
9-2 Fixed I/O Ranges Decoded by PCH ....................................................................... 382
9-3 Variable I/O Decode Ranges ................................................................................ 384
9-4 Memory Decode Ranges from Processor Perspective ............................................... 385
9-5 SPI Mode Address Swapping ............................................................................... 387
10-1 Chipset Configuration Register Memory Map (Memory Space) .................................. 389
10-1 Thermal Initialization Registers............................................................................ 430
11-1 Gigabit LAN Configuration Registers Address Map
(Gigabit LAN—D25:F0) ....................................................................................... 433
11-2 Gigabit LAN Capabilities and Status Registers Address Map
(Gigabit LAN—MBARA) ....................................................................................... 448
12-1 LPC Interface PCI Register Address Map (LPC I/F—D31:F0) ..................................... 453
12-2 DMA Registers................................................................................................... 480
12-3 PIC Registers .................................................................................................... 493
12-4 APIC Direct Registers ......................................................................................... 501
12-5 APIC Indirect Registers....................................................................................... 501
12-6 RTC I/O Registers .............................................................................................. 506
12-7 RTC (Standard) RAM Bank .................................................................................. 507
12-8 Processor Interface PCI Register Address Map ....................................................... 511
12-9 Power Management PCI Register Address Map (PM—D31:F0)................................... 514
12-10 APM Register Map .............................................................................................. 524
12-11 ACPI and Legacy I/O Register Map ....................................................................... 526
12-12 TCO I/O Register Address Map............................................................................. 547
12-13 Registers to Control GPIO Address Map................................................................. 554
13-1 SATA Controller PCI Register Address Map (SATA–D31:F2)...................................... 565
13-2 Bus Master IDE I/O Register Address Map ............................................................. 594
13-3 AHCI Register Address Map ................................................................................. 603
13-4 Generic Host Controller Register Address Map........................................................ 604
13-5 Port [5:0] DMA Register Address Map ................................................................... 613
14-1 SATA Controller PCI Register Address Map (SATA–D31:F5)...................................... 629
Datasheet 37
14-2 Bus Master IDE I/O Register Address Map ............................................................. 645
15-1 USB EHCI PCI Register Address Map (USB EHCI—D29:F0, D26:F0) ........................... 653
15-2 Enhanced Host Controller Capability Registers........................................................ 675
15-3 Enhanced Host Controller Operational Register Address Map .................................... 678
15-4 Debug Port Register Address Map ......................................................................... 692
16-1 USB xHCI PCI Register Address Map (USB xHCI—D20:F0) ....................................... 697
16-2 Enhanced Host Controller Capability Registers........................................................ 719
16-3 Enhanced Host Controller Operational Register Address Map .................................... 725
16-4 Enhanced Host Controller Operational Register Address Map .................................... 747
17-1 Intel® High Definition Audio (Intel® HD Audio) PCI Register Address Map
(Intel® High Definition Audio D27:F0) ....................................................................... 753
17-2 Intel® High Definition Audio Memory Mapped Configuration Registers
Address Map (Intel® High Definition Audio D27:F0) ................................................ 775
18-1 SMBus Controller PCI Register Address Map (SMBus—D31:F3) ................................. 803
18-2 SMBus I/O and Memory Mapped I/O Register Address Map ...................................... 810
19-1 PCI Express* Configuration Registers Address Map
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)...................................................... 821
20-1 Memory-Mapped Register Address Map ................................................................. 865
21-1 Serial Peripheral Interface (SPI) Register Address Map
(SPI Memory Mapped Configuration Registers) ....................................................... 875
21-2 Gigabit LAN SPI Flash Program Register Address Map
(GbE LAN Memory Mapped Configuration Registers)................................................ 897
22-1 Thermal Sensor Register Address Map................................................................... 909
22-2 Thermal Memory Mapped Configuration Register Address Map.................................. 917
23-1 Intel® MEI 1 Configuration Registers Address Map
(Intel® MEI 1—D22:F0) ...................................................................................... 925
23-2 Intel® MEI 1 MMIO Register Address Map .............................................................. 936
23-3 Intel® MEI 2 Configuration Registers Address Map
(Intel® MEI 2—D22:F1) ...................................................................................... 939
23-4 Intel® MEI 2 MMIO Register Address Map .............................................................. 950
23-5 IDE Redirect Function IDER Register Address Map .................................................. 953
23-6 IDER BAR0 Register Address Map ......................................................................... 961
23-7 IDER BAR1 Register Address Map ......................................................................... 971
23-8 IDER BAR4 Register Address Map ......................................................................... 972
23-9 Serial Port for Remote Keyboard and Text (KT) Redirection Register
Address Map...................................................................................................... 979
23-10 KT IO/Memory Mapped Device Register Address Map .............................................. 986
38 Datasheet
Revision History
Revision
Description Revision Date
Number
001 • Initial Release. June 2013
§§
Datasheet 39
Platform Controller Hub Features
Direct Media Interface USB
— Up to 20 Gb/s each direction, full duplex. — xHCI Host Controller, supports up to 6
— Transparent to software SuperSpeed USB 3.0 connections and 14
NEW: Flexible IO USB 2.0 connections
— A new architecture that allows some high — More flexibility in pairing USB 3.0 and USB
speed IO signals to be configured as SATA 2.0 signals to the same connector
or USB 3.0 or PCIe — Two EHCI Host Controllers, supporting up
PCI Express* to fourteen external USB 2.0 ports
— Up to eight PCI Express root ports — Support for dynamic power gating and
— Supports PCI Express Rev 2.0 running at up Intel® Power Management Framework
to 5.0 GT/s (PMF)
— Ports 1-4 and 5-8 can independently be — Per-Port-Disable Capability
configured to support multiple port — Includes up to two USB 2.0 High-speed
configurations Debug Ports
— Module based Hot-Plug supported (that is, — Supports wake-up from sleeping states S1-
ExpressCard*) S4
— NEW: Latency Tolerance Reporting Integrated Gigabit LAN Controller
— NEW: Optimized Buffer Flush/Fill — Connection utilizes PCI Express pins
Integrated Serial ATA Host Controller — Integrated ASF Management Controller
— Up to six SATA ports — Network security with System Defense
— Data transfer rates supported: 6.0 Gb/s, — Supports IEEE 802.3
3.0 Gb/s, and 1.5 Gb/s on all ports — 10/100/1000 Mbps Ethernet Support
— Integrated AHCI controller — Jumbo Frame Support
External SATA support on all ports Intel® Active Management Technology with
— 3.0 Gb/s and 1.5 Gb/s support System Defense
— Port Disable Capability — Network Outbreak Containment Heuristics
Intel® Rapid Storage Technology Intel® IO Virtualization (Intel® VT-d) Support
— Configures the PCH SATA controller as a Intel® Trusted Execution Technology (Intel®
RAID controller supporting RAID 0/1/5/10 TXT) Support
Intel® Smart Response Technology Intel® Anti-Theft Technology (Intel® AT)
Intel® High Definition Audio Interface Power Management Logic
— PCI Express endpoint — Supports ACPI 4.0a
— Independent Bus Master logic for eight — ACPI-defined power states (processor
general purpose streams: four input and driven C states)
four output — ACPI Power Management Timer
— Support four external Codecs — SMI# generation
— Supports variable length stream slots — All registers readable/restorable for proper
— Supports multichannel, 32-bit sample resume from 0 V core well suspend states
depth, 192 kHz sample rate output — Support for APM-based legacy power
— Provides mic array support management for non-ACPI
— Allows for non-48 kHz sampling output implementations
— Support for ACPI Device States Integrated Clock Controller
— Low Voltage — Full featured platform clocking without
need for a discrete clock chip
Eight TACH signals and Four PWM signals
(Server and Workstation Only) — 8 PCIe* 2.0 specification compliant clocks,
Platform Environmental Control Interface 4 PCIe 3.0 specification compliant clocks,
(PECI) and Simple Serial Transport (SST) 1.0 five 33 MHz PCI clocks, four Flex Clocks
Bus (Server and Workstation Only) that can be configured for various
frequencies, and two 135 MHz clocks for
DisplayPort*.
40 Datasheet
External Glue Integration Serial Peripheral Interface (SPI)
— Integrated Pull-down and Series resistors — Supports up to two SPI devices
on USB — Supports 20 MHz, 33 MHz, and 50 MHz SPI
Enhanced DMA Controller devices
— Two cascaded 8237 DMA controllers — NEW: Supports Quad IO Fast Read, Quad
— Supports LPC DMA Output Fast Read, Dual IO Fast Read
SMBus — NEW: Support for TPM over SPI with the
— Interface speeds of up to 100 kbps addition of SPI_CS2# chip select pin
— Supports SMBus 2.0 Specification — NEW: Supports Serial Flash Discoverable
— Host interface allows processor to Parameter (SFDP)
communicate using SMBus — Support up to two different erase
— Slave interface allows an internal or granularities
external microcontroller to access system Firmware Hub I/F supports BIOS Memory size
resources up to 8 MB
— Supports most two-wire components that Low Pin Count (LPC) I/F
are also I2C compatible — Supports two Master/DMA devices.
SMLink — Support for Security Device (Trusted
— Provides independent manageability bus Platform Module) connected to LPC
through SMLink0 and SMLink1 Interrupt Controller
— SMLink0 dedicated to LAN PHY and NFC, — Supports up to eight legacy interrupt pins
operating up to 1 MHz — Supports PCI 2.3 Message Signaled
— SMLink1 dedicated to EC or BMC, operating Interrupts
up to 100 kHz — Two cascaded 8259 with 15 interrupts
High Precision Event Timers — Integrated IO APIC capability with 24
— Advanced operating system interrupt interrupts
scheduling — Supports Processor System Bus interrupt
Timers Based on 8254 delivery
— System timer, Refresh request, Speaker 1.05 V operation with tolerance up to 3.3 V IO
tone output 1.05 V Core Voltage
Real-Time Clock Integrated Voltage Regulators for select power
— 256 byte battery-backed CMOS RAM rails
— Integrated oscillator components GPIO
— Open-Drain, Inversion
— Lower Power DC/DC Converter
— GPIO lock down
implementation
Intel® Flexible Display Interface
System TCO Reduction Circuits
— Timers to generate SMI# and Reset upon Display
— Analog Display (VGA) Interface
detection of system hang
— Side band signals AUX CH, DDC and HPD
— Timers to detect improper processor reset
— Backlight Control and Panel Power
— Supports ability to disable external devices
sequencing signals
JTAG
— Boundary Scan for testing during board Package
— 23 mm x 22 mm FCBGA (Desktop Only)
manufacturing
— 20 mm x 20 mm FCBGA (Mobile Only)
Note: Not all features are available on all PCH SKUs.
§§
Datasheet 41
42 Datasheet
Introduction
1 Introduction
1.1 About This Manual
This document is intended for Original Equipment Manufacturers and BIOS vendors
creating products based on the Intel® 8 Series / C220 Series Chipset Family Platform
Controller Hub (PCH) (See Section 1.3 for SKU definitions and supported features).
Note: Throughout this document, Platform Controller Hub (PCH) is used as a general term
and refers to all Intel® 8 Series / C220 Series Chipset Family Platform Controller Hub
(PCH) SKUs, unless specifically noted otherwise.
Note: Throughout this document, the terms “Desktop” and “Desktop Only” refer to
information that is applicable only to Desktop PCH, unless specifically noted otherwise.
Note: Throughout this document, the terms “Server/Workstation” and “Server/Workstation
Only” refers to information that is applicable only to Server/Workstation PCH, unless
specifically noted otherwise.
Note: Throughout this document, the terms “Mobile” and “Mobile Only” refers to information
that is applicable only to the Mobile PCH, unless specifically noted otherwise.
This manual assumes a working knowledge of the vocabulary and principles of PCI
Express*, USB, AHCI, SATA, Intel® High Definition Audio (Intel® HD Audio), SMBus,
ACPI and Low Pin Count (LPC). Although some details of these features are described
within this manual, refer to the individual industry specifications listed in Table 1-1 for
the complete details.
All PCI buses, devices and functions in this manual are abbreviated using the following
nomenclature; Bus:Device:Function. This manual abbreviates buses as Bn, devices as
Dn and functions as Fn. For example Device 31 Function 0 is abbreviated as D31:F0,
Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number will
not be used, and can be considered to be Bus 0.
Table 1-1. Industry Specifications (Sheet 1 of 2)
Specification Location
PCI Express* Base Specification, Revision 2.0 http://www.pcisig.com/specifications
http://developer.intel.com/design/chipsets/
Low Pin Count Interface Specification, Revision 1.1 (LPC)
industry/lpc.htm
System Management Bus Specification, Version 2.0 (SMBus) http://www.smbus.org/specs/
PCI Local Bus Specification, Revision 2.3 (PCI) http://www.pcisig.com/specifications
PCI Power Management Specification, Revision 1.2 http://www.pcisig.com/specifications
Universal Serial Bus Specification (USB), Revision 2.0 http://www.usb.org/developers/docs
Advanced Configuration and Power Interface, Version 4.0a
http://www.acpi.info/spec.htm
(ACPI)
Enhanced Host Controller Interface Specification for http://developer.intel.com/technology/usb/
Universal Serial Bus, Revision 1.0 (EHCI) ehcispec.htm
eXtensible Host Controller Interface for Universal Serial Bus http://www.intel.com/technology/usb/
(xHCI), Revision 1.0 xhcispec.htm
Serial ATA Specification, Revision 3.0 http://www.serialata.org/
Datasheet 43
Introduction
Table 1-1. Industry Specifications (Sheet 2 of 2)
Specification Location
Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0 http://www.serialata.org
Serial ATA II Cables and Connectors Volume 2 Gold http://www.serialata.org
Alert Standard Format Specification, Version 1.03 http://www.dmtf.org/standards/asf
IEEE 802.3 Fast Ethernet http://standards.ieee.org/getieee802/
AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) http://T13.org (T13 1410D)
IA-PC HPET (High Precision Event Timers) Specification, http://www.intel.com/hardwaredesign/
Revision 1,0a hpetspec_1.pdf
Trusted Platform Module (TPM) Specification 1.3 http://www.trustedcomputinggroup.org/specs/
Note: TPM over SPI supports 8 bytes transactions max. TPM
http://www.intel.com/technology/virtualization/
Intel® Virtualization Technology
index.htm
SFF-8485 Specification for Serial GPIO (SGPIO) Bus, http://www.intel.com/technology/virtualization/
Revision 0.7 index.htm
Advanced Host Controller Interface specification for Serial http://www.intel.com/technology/serialata/
ATA, Revision 1.3 ahci.htm
Intel® High Definition Audio Specification, Revision 1.0a http://www.intel.com/standards/hdaudio/
1.1.1 Chapter Descriptions
Chapter 1, “Introduction”
Chapter 1 introduces the PCH, provides information on the organization of the manual
and gives a general overview of the PCH.
Chapter 2, “Signal Description”
Chapter 2 provides a block diagram of the PCH and a detailed description of each
signal. Signals are arranged according to interface and details are provided as to the
drive characteristics (Input/Output, Open Drain, and so on) of all signals.
Chapter 3, “PCH Pin States”
Chapter 3 provides a complete list of signals, their associated power well, their logic
level in each suspend state, and their logic level before and after reset.
Chapter 4, “PCH and System Clocks”
Chapter 4 provides a list of each clock domain associated with the PCH.
Chapter 5, “Functional Description”
Chapter 5 provides a detailed description of the functions in the PCH.
Chapter 6, “Ballout Definition”
Chapter 6 provides the ball assignment table and the ball-map for the Desktop and
Mobile packages.
Chapter 7, “Package Information”
Chapter 7 provides drawings of the physical dimensions and characteristics of the
Desktop and Mobile packages.
Chapter 8, “Electrical Characteristics”
Chapter 8 provides all AC and DC characteristics including detailed timing diagrams.
44 Datasheet
Introduction
Chapter 9, “Register and Memory Mapping”
Chapter 9 provides an overview of the registers, fixed I/O ranges, variable I/O ranges
and memory ranges decoded by the PCH.
Chapter 10, “Chipset Configuration Registers”
Chapter 10 provides a detailed description of registers and base functionality that is
related to chipset configuration. It contains the root complex register block, which
describes the behavior of the upstream internal link.
Chapter 11, “Gigabit LAN Configuration Registers”
Chapter 11 provides a detailed description of registers that reside in the PCH’s
integrated LAN controller. The integrated LAN Controller resides at Device 25,
Function 0 (D25:F0).
Chapter 12, “LPC Interface Bridge Registers (D31:F0)”
Chapter 12 provides a detailed description of registers that reside in the LPC bridge.
This bridge resides at Device 31, Function 0 (D31:F0). This function contains registers
for many different units within the PCH including DMA, Timers, Interrupts, Processor
Interface, GPIO, Power Management, System Management and RTC.
Chapter 13, “SATA Controller Registers (D31:F2)”
Chapter 13 provides a detailed description of registers that reside in the SATA
controller #1. This controller resides at Device 31, Function 2 (D31:F2).
Chapter 14, “PCI Configuration Registers (SATA–D31:F5)”
Chapter 14.1 provides a detailed description of registers that reside in the SATA
controller #2. This controller resides at Device 31, Function 5 (D31:F5).
Chapter 15, “EHCI Controller Registers (D29:F0, D26:F0)”
Chapter 15 provides a detailed description of registers that reside in the two EHCI host
controllers. These controllers reside at Device 29, Function 0 (D29:F0) and Device 26,
Function 0 (D26:F0).
Chapter 16, “xHCI Controller Registers (D20:F0)”
Chapter 16 provides a detailed description of registers that reside in the xHCI. This
controller resides at Device 20, Function 0 (D20:F0).
Chapter 17, “Integrated Intel® High Definition Audio (Intel® HD Audio)
Controller Registers”
Chapter 17 provides a detailed description of registers that reside in the Intel High
Definition Audio controller. This controller resides at Device 27, Function 0 (D27:F0).
Chapter 18, “SMBus Controller Registers (D31:F3)”
Chapter 18 provides a detailed description of registers that reside in the SMBus
controller. This controller resides at Device 31, Function 3 (D31:F3).
Chapter 19, “PCI Express* Configuration Registers”
Chapter 19 provides a detailed description of registers that reside in the PCI Express
controller. This controller resides at Device 28, Functions 0 to 7 (D28:F0-F7).
Chapter 20, “High Precision Event Timer Registers”
Chapter 20 provides a detailed description of registers that reside in the multimedia
timer memory mapped register space.
Chapter 21, “Serial Peripheral Interface (SPI)”
Chapter 21 provides a detailed description of registers that reside in the SPI memory
mapped register space.
Datasheet 45
Introduction
Chapter 22, “Thermal Sensor Registers (D31:F6)”
Chapter 22 provides a detailed description of registers that reside in the thermal
sensors PCI configuration space. The registers reside at Device 31, Function 6
(D31:F6).
Chapter 23, “Intel® Management Engine (Intel® ME) Subsystem Registers
(D22:F[3:0])”
Chapter 23 provides a detailed description of registers that reside in the Intel ME
controller. The registers reside at Device 22, Function 0 (D22:F0).
1.2 Overview
The PCH provides extensive I/O support. Functions and capabilities include:
• PCI Express* Base Specification, Revision 2.0 support for up to eight ports with
transfers up to 5 GT/s
• ACPI Power Management Logic Support, Revision 4.0a
• Enhanced DMA controller, interrupt controller, and timer functions
• Integrated Serial ATA host controllers with independent DMA operation on up to six
ports
• xHCI USB controller provides support for up to 14 USB ports, of which six can be
configured as SuperSpeed USB 3.0 ports.
• Two legacy EHCI USB controllers each provides a USB debug port.
• Flexible I/O, A new architecture to allow some high speed I/O signals to be
configured as PCIe, SATA or USB 3.0.
• Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense
• System Management Bus (SMBus) Specification, Version 2.0 with additional
support for I2C devices
• Supports Intel® High Definition Audio (Intel® HD Audio)
• Supports Intel® Rapid Storage Technology (Intel® RST)
• Supports Intel® Active Management Technology (Intel® AMT)
• Supports Intel® Virtualization Technology for Directed I/O (Intel® VT-d)
• Supports Intel® Trusted Execution Technology (Intel® TXT)
• Integrated Clock Controller
• Intel® Flexible Display Interface (Intel® FDI)
• Analog VGA Display Interface
• Low Pin Count (LPC) interface
• Firmware Hub (FWH) interface support
• Serial Peripheral Interface (SPI) support
• Intel® Anti-Theft Technology (Intel® AT)
• JTAG Boundary Scan support
Note: Not all functions and capabilities may be available on all SKUs. See Section 1.3 for
details on SKU feature availability.
46 Datasheet
Introduction
1.2.1 Capability Overview
The following sub-sections provide an overview of the PCH capabilities.
Direct Media Interface (DMI)
Direct Media Interface (DMI) is the chip-to-chip connection between the processor and
PCH. This high-speed interface integrates advanced priority-based servicing allowing
for concurrent traffic and true isochronous transfer capabilities. Base functionality is
completely software-transparent, permitting current and legacy software to operate
normally.
Intel® Flexible Display Interface (Intel® FDI)
Intel FDI connects the display engine in the processor with the Analog display interface
on the PCH. The display data for Analog VGA panels from the frame buffer is processed
by the display engine and sent to the PCH through Intel FDI. Intel FDI has two lanes for
display data transfer to the PCH from the processor. Each Intel FDI lane consists of two
differential signal receive pairs supporting a data rate of 2.7 Gb/s.
PCH Display Interface
The Analog VGA display interface is the only display interface supported on the PCH.
This interface is used to drive legacy CRT panels and advanced LCD VGA panels. The
analog VGA display interface has an integrated RAMDAC 180 MHz, driving a standard
progressive scan analog monitor to a resolution of up to 1920x2000 pixels and 24-bit
color at a 60 Hz refresh rate with reduced blanking.
Analog VGA display interface is in the PCH, although the main display engine is in the
processor. Thus, the Intel FDI is used to send the display data to the PCH. Intel FDI is a
bus that connects the processor and PCH display components. The PCH, upon receiving
the display data, transcodes the data as per the display technology protocol and sends
the data through the DAC to display panel.
The PCH integrates digital display side band signals, even though digital display
interfaces are in the processor. There are three pairs of AUX CH, DDC Clock/Data, and
Hot-Plug Detect Signals on the PCH that correspond to digital display interface/ports B,
C, and D.
The PCH also integrates panel backlight control signals, which are used only when
Embedded DisplayPort* (eDP) is configured on the platform.
PCI Express* Interface
The PCH provides up to 8 PCI Express Root Ports, supporting the PCI Express Base
Specification, Revision 2.0. Each Root Port x1 lane supports up to 5 Gb/s bandwidth in
each direction (10 Gb/s concurrent). PCI Express Root Ports 1–4 or Ports 5–8 can
independently be configured to support multiple port width configurations. See
Section 1.3 for details on feature availability.
Datasheet 47
Introduction
Serial ATA (SATA) Controller
The PCH has two integrated SATA host controllers that support independent DMA
operation on up to six ports and support data transfer rates of up to 6.0 Gb/s on all
ports. The SATA controller contains two modes of operation – a legacy mode using I/O
space, and an AHCI mode using memory space. Software that uses legacy mode will
not have AHCI capabilities.
The PCH supports the Serial ATA Specification, Revision 3.0. The PCH also supports
several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification,
Revision 1.0 (AHCI support is required for some elements).
See Section 1.3 for details on feature availability.
AHCI
The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a
standardized programming interface for SATA host controllers. Platforms supporting
AHCI may take advantage of performance features such as no master/slave
designation for SATA devices – each device is treated as a master – and hardware-
assisted native command queuing. AHCI also provides usability enhancements, such as
Hot-Plug. AHCI requires appropriate software support (such as, an AHCI driver) and for
some features, hardware support in the SATA device or additional platform hardware.
See Section 1.3 for details on SKU feature availability.
Intel® Rapid Storage Technology (Intel® RST)
The PCH provides support for Intel Rapid Storage Technology (Intel RST), providing
both AHCI (see above for details on AHCI) and integrated RAID functionality. The RAID
capability provides high-performance RAID 0, 1, 5, and 10 functionality on up to 6
SATA ports of the PCH. Matrix RAID support is provided to allow multiple RAID levels to
be combined on a single set of hard drives, such as RAID 0 and RAID 1 on two disks.
Other RAID features include hot spare support, SMART alerting, and RAID 0 auto
replace. Software components include an Option ROM for pre-boot configuration and
boot functionality, a Microsoft* Windows* compatible driver, and a user interface for
configuration and management of the RAID capability of PCH. See Section 1.3 for
details on SKU feature availability.
Intel® Smart Response Technology
Intel Smart Response Technology is a disk caching solution that can provide improved
computer system performance with improved power savings. It allows configuration of
a computer system with the advantage of having HDDs for maximum storage capacity
with system performance at or near SSD performance levels. See Section 1.3 for
details on SKU feature availability.
Low Pin Count (LPC) Interface
The PCH implements an LPC Interface as described in the LPC 1.1 Specification. The
Low Pin Count (LPC) bridge function of the PCH is mapped as PCI D31:F0 and supports
a memory size up to 8 MB, two master/DMA devices, interrupt controllers, timers,
power management, system management, Super I/O, and RTC.
48 Datasheet
Introduction
Serial Peripheral Interface (SPI)
In addition to the standard Dual Output Fast Read mode, the SPI interface in the PCH
supports new Dual I/O Fast Read, Quad I/O Fast Read and Quad Output Fast Read. To
enable the new Quad I/O operation modes, all data transfer signals in the interface are
bidirectional and two new signals (SPI_IO2 and SPI_IO3) have been added to the basic
four-wire interface: Clock, Master Out Slave In (MOSI), Master In Slave Out (MISO)
and active-low chip selects (CS#). The PCH supports three chip selects: SPI_CS0# and
SPI_CS1# are used to access two separate SPI Flash components in Descriptor Mode.
SPI_CS2# is dedicated only to support Trusted Platform Module (TPM) on SPI (TPM can
be configured through PCH soft straps to operate over LPC or SPI, but no more than
1 TPM is allowed in the system). SPI_CS2# may not be used for any purpose other
than TPM.
The SPI Flash Controller supports running instructions at 20 MHz, 33 MHz, and 50 MHz,
and can be used by the PCH for BIOS code, to provide chipset configuration settings,
internal micro-processor code, integrated Gigabit Ethernet MAC/PHY configuration, and
Intel Active Management Technology (Intel AMT) settings. The SPI Flash Controller
supports the Serial Flash Discoverable Parameter (SFDP) JEDEC standard that provides
a consistent way of describing the functional and feature capabilities of serial flash
devices in a standard set of internal parameter tables. The SPI Flash Controller queries
these parameter tables to discover the attributes to enable divergent features from
multiple SPI part vendors, such as Quad I/O Fast Read capabilities or device storage
capacity, among others.
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)
The DMA controller incorporates the logic of two 8237 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-
byte transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any
two of the seven DMA channels can be programmed to support fast Type-F transfers.
Channel 4 is reserved as a generic bus master request.
The PCH supports LPC DMA, which is similar to ISA DMA, through the PCH DMA
controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals
and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and
Increment modes are supported on the LPC interface.
The timer/counter block contains three counters that are equivalent in function to those
found in one 8254 programmable interval timer. These three counters are combined to
provide the system timer function, and speaker tone. The 14.318 MHz oscillator input
provides the clock source for these three counters.
The PCH provides an ISA-compatible Programmable Interrupt Controller (PIC) that
incorporates the functionality of two 8259 interrupt controllers. The two interrupt
controllers are cascaded so that 14 external and two internal interrupts are possible. In
addition, the PCH supports a serial interrupt scheme.
All of the registers in these modules can be read and restored. This is required to save
and restore system state after power has been removed and restored to the platform.
Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA-compatible Programmable Interrupt controller (PIC)
described in the previous section, the PCH incorporates the Advanced Programmable
Interrupt Controller (APIC).
Datasheet 49
Introduction
Universal Serial Bus (USB) Controllers
The PCH contains one eXtensible Host Controller Interface (xHCI) controller and two
Enhanced Host Controller Interface (EHCI) controllers. The xHCI controller is mapped
as PCI D20:F0 and it supports up to 14 USB 2.0 ports of which 6 can be configured as
SuperSpeed (USB 3.0) ports.
EHCI controller 1 (EHCI1) is located at D29:F0 and it supports up to 8 USB 2.0 ports.
EHCI controller 2 (EHCI2) is located at D26:F0 and it supports up to 6 USB 2.0 ports.
One of the USB 2.0 ports in either EHCI controller can be used for a Debug Port (not
available through xHCI).
Note: USB 2.0 differential pairs are numbered starting with 0. USB 3.0 differential pairs are
numbered starting with 1.
See Section 1.3 for details on feature availability.
Flexible I/O
The PCH implements Flexible I/O, an architecture to allow some high speed signals to
be configured as SATA, USB 3.0, or PCIe signals. Through soft straps, the functionality
on these multiplexed signals are selected to meet the I/O needs on the platform. See
Section 5.22 for details on Flexible I/O.
Gigabit Ethernet Controller
The Gigabit Ethernet Controller provides a system interface using a PCI function. The
controller provides a full memory-mapped or I/O mapped interface along with a 64-bit
address master support for systems using more than 4 GB of physical memory and
DMA (Direct Memory Addressing) mechanisms for high performance data transfers. Its
bus master capabilities enable the component to process high-level commands and
perform multiple operations. This lowers processor utilization by off-loading
communication tasks from the processor. Two large configurable transmit and receive
FIFOs (up to 20 KB each) help prevent data underruns and overruns while waiting for
bus accesses. This enables the integrated LAN controller to transmit data with
minimum interframe spacing (IFS).
The LAN controller can operate at multiple speeds (10/100/1000 MB/s) and in either
full duplex or half duplex mode. In full duplex mode the LAN controller adheres with the
IEEE 802.3x Flow Control Specification. Half duplex performance is enhanced by a
proprietary collision reduction mechanism. See Section 5.4 for details.
RTC
The PCH contains a Motorola MC146818B-compatible real-time clock with 256 bytes of
battery-backed RAM. The real-time clock performs two key functions – keeping track of
the time of day and storing system data, even when the system is powered down. The
RTC operates on a 32.768-kHz crystal and a 3-V battery.
The RTC also supports two lockable memory ranges. By setting bits in the configuration
space, two 8-byte ranges can be locked to read and write accesses. This prevents
unauthorized reading of passwords or other system security information.
The RTC also supports a date alarm that allows for scheduling a wake up event up to
30 days in advance, rather than just 24 hours in advance.
GPIO
Various general purpose inputs and outputs are provided for custom system design.
The number of inputs and outputs varies depending on PCH configuration.
50 Datasheet
Introduction
Enhanced Power Management
The PCH’s power management functions fully support the Advanced Configuration and
Power Interface (ACPI) Specification, Revision 4.0a, and include enhanced clock control
and various low-power (suspend) states (such as Suspend-to-RAM and Suspend-to-
Disk). A hardware-based thermal management circuit permits software-independent
entrance to low-power states.
Intel® Active Management Technology (Intel® AMT)
Intel AMT is a fundamental component of Intel® vPro™ technology. Intel AMT is a set of
advanced manageability features developed as a direct result of IT customer feedBack
gained through Intel market research. With the advent of powerful tools like the Intel
System Defense Utility, the extensive feature set of Intel AMT easily integrates into any
network environment. See Section 1.3 for details on SKU feature availability.
Manageability
In addition to Intel AMT, the PCH integrates several functions designed to manage the
system and lower the total cost of ownership (TCO) of the system. These system
management functions are designed to report errors, diagnose the system, and recover
from system lockups without the aid of an external microcontroller.
• TCO Timer. The PCH’s integrated programmable TCO timer is used to detect
system locks. The first expiration of the timer generates an SMI# that the system
can use to recover from a software lock. The second expiration of the timer causes
a system reset to recover from a hardware lock.
• Processor Present Indicator. The PCH looks for the processor to fetch the first
instruction after reset. If the processor does not fetch the first instruction, the PCH
will reboot the system.
• ECC Error Reporting. When detecting an ECC error, the host controller has the
ability to send one of several messages to the PCH. The host controller can instruct
the PCH to generate either an SMI#, NMI, SERR#, or TCO interrupt.
• Function Disable. The PCH provides the ability to disable the following integrated
functions: LAN, USB, LPC, Intel HD Audio, SATA, PCI Express* or SMBus. Once
disabled, these functions no longer decode I/O, memory, or PCI configuration
space. Also, no interrupts or power management events are generated from the
disabled functions.
• Intruder Detect. The PCH provides an input signal (INTRUDER#) that can be used
to inform the system in the event of the case being opened. The PCH can be
programmed to generate an SMI# or TCO interrupt due to an active INTRUDER#
signal.
Datasheet 51
Introduction
System Management Bus (SMBus 2.0)
The PCH contains an SMBus Host interface that allows the processor to communicate
with SMBus slaves. This interface is compatible with most I2C devices. Special I2C
commands are implemented.
The PCH SMBus host controller provides a mechanism for the processor to initiate
communications with SMBus peripherals (slaves). Also, the PCH supports slave
functionality, including the Host Notify protocol. Hence, the host controller supports
eight command protocols of the SMBus interface (see System Management Bus
(SMBus) Specification, version 2.0): Quick Command, Send Byte, Receive Byte, Write
Byte/Word, Read Byte/Word, Process Call, Block Read/Write, and Host Notify.
The PCH SMBus also implements hardware-based Packet Error Checking for data
robustness and the Address Resolution Protocol (ARP) to dynamically provide
addresses to all SMBus devices.
Intel® High Definition Audio (Intel® HD Audio) Controller
The Intel HD Audio controller is a PCI Express* device, configured as D27:F0. The PCH
Intel HD Audio controller supports up to 4 codecs, such as audio and modem codecs.
The link can operate at either 3.3 V or 1.5 V.
With the support of multi-channel audio stream, 32-bit sample depth, and sample rate
up to 192 kHz, the Intel HD Audio controller provides audio quality that can deliver CE
levels of audio experience. On the input side, the PCH adds support for an array of
microphones.
Intel® Virtualization Technology for Directed I/O (Intel® VT-d)
The PCH provides hardware support for implementation of Intel Virtualization
Technology with Directed I/O (Intel VT-d). Intel VT-d Technology consists of technology
components that support the virtualization of platforms based on Intel Architecture
processors. Intel VT-d Technology enables multiple operating systems and applications
to run in independent partitions. A partition behaves like a virtual machine (VM) and
provides isolation and protection across partitions. Each partition is allocated its own
subset of host physical memory.
JTAG Boundary-Scan
The PCH implements the industry standard JTAG interface and enables Boundary-Scan.
Boundary-Scan can be used to ensure device connectivity during the board
manufacturing process. The JTAG interface allows system manufacturers to improve
efficiency by using industry available tools to test the PCH on an assembled board.
Since JTAG is a serial interface, it eliminates the need to create probe points for every
pin in an XOR chain. This eases pin breakout and trace routing and simplifies the
interface between the system and a bed-of-nails tester.
Note: The TRST# JTAG signal is an optional signal in the IEEE* 1149 JTAG Specification and is
not implemented in the PCH.
52 Datasheet
Introduction
Integrated Clock Controller
The PCH contains an Integrated Clock Controller (ICC) that generates various platform
clocks from a 25 MHz crystal source. The ICC contains PLLs, Modulators, and Dividers
for generating various clocks suited to the platform needs. The ICC supplies up to eight
100 MHz PCI Express 2.0 Specification compliant clocks, one 100 MHz PCI Express* 3.0
Specification compliant clock for BCLK/DMI, two 100 MHz PCI Express 3.0 Specification
compliant clocks for PEG slots, one 100 MHz PCI Express 3.0 Specification compliant
clock for ITP or a third PEG slot, two 135 MHz differential output clocks for DisplayPort
on the processor, five 33 MHz PCI 2.3 Local Bus Specification compliant single-ended
clocks for LPC/TPM devices and four Flex Clocks that can be configured to various
frequencies that include 14.318 MHz, 33 MHz, and 24/48 MHz for use with SIO, TPM,
EC, LPC, and any other legacy functions.
Serial Over LAN (SOL) Function
This function supports redirection of keyboard and text screens to a terminal window
on a remote console. The keyboard and text redirection enables the control of the client
machine through the network without the need to be physically near that machine. Text
and keyboard redirection allows the remote machine to control and configure a client
system. The SOL function emulates a standard PCI device and redirects the data from
the serial port to the management console using the integrated LAN.
Intel® KVM Technology
Intel KVM technology provides enhanced capabilities to its predecessor – SOL. In
addition to the features set provided by SOL, Intel KVM technology provides mouse and
graphic redirection across the integrated LAN. Unlike SOL, Intel KVM technology does
not appear as a host accessible PCI device, but is instead almost completely performed
by Intel AMT Firmware with minimal BIOS interaction. The Intel KVM technology
feature is only available with internal graphics.
IDE-R Function
The IDE-R function is an IDE Redirection interface that provides client connection to
management console ATA/ATAPI devices, such as hard disk drives and optical disk
drives. A remote machine can setup a diagnostic software or operating system
installation image and direct the client to boot an IDE-R session. The IDE-R interface is
the same as the IDE interface; although, the device is not physically connected to the
system and supports the ATA/ATAPI-6 specification. IDE-R does not conflict with any
other type of boot and can, instead, be implemented as a boot device option. The Intel
AMT solution will use IDE-R when remote boot is required. The device attached through
IDE-R is only visible to software during a management boot session. During normal
boot session, the IDE-R controller does not appear as a PCI present device.
Datasheet 53
Introduction
1.3 Intel® 8 Series / C220 Series Chipset Family SKU
Definition
Table 1-2. Desktop Intel® 8 Series Chipset Family SKUs
SKU Name
Intel® Intel® Intel® Intel® Intel®
Feature Set Q87 Q85 B85 Z87 H87
Express Express Express Express Express
Chipset Chipset Chipset Chipset Chipset
Flexible I/O Yes No No Yes Yes
PCI Express* 2.0 Ports 84 8 8 84 84
5
Total number of USB ports 14 14 12 14 14
• USB 3.0 Capable Ports (SuperSpeed and all USB 2.0 7 7
4(6) 4 4 4(6) 4(6)7
speeds)
• USB 2.0 Only Ports 10(8)9 10 8 10(8)9 10(8)9
10 10
Total number of SATA ports 4(6) 6 6 4(6) 4(6)10
• SATA Ports (6 Gb/s, 3 Gb/s, and 1.5 Gb/s) 6 412 412 6 6
• SATA Ports (3 Gb/s and 1.5 Gb/s only) 0 2 2 0 0
VGA Yes Yes Yes Yes Yes
Intel® Wireless Display (WiDi) Yes Yes Yes Yes Yes
AHCI Yes Yes Yes Yes Yes
®
Intel Rapid Storage RAID 0/1/5/10 Support Yes No No Yes Yes
Technology
Intel® Smart Response
Yes No No Yes Yes
Technology14
Intel® Anti-Theft Technology15 Yes Yes Yes Yes Yes
Intel® Active Management Technology 9.0 Yes No No No No
Intel® Small Business Advantage16 Yes Yes Yes No Yes17
Intel Rapid Start Technology18 Yes Yes Yes Yes Yes
Intel® Identity Protection Technology (Intel® IPT)19 Yes Yes Yes Yes Yes
20
Near Field Communication Yes Yes Yes Yes Yes
ACPI S1 State Support Yes Yes Yes Yes Yes
NOTES:
1. Contact your local Intel Field Sales Representative for currently available PCH SKUs.
2. Table above shows feature differences between the PCH SKUs. If a feature is not listed in
the table it is considered a Base feature that is included in all SKUs.
3. PCI Legacy Mode may optionally be used allowing external PCI bus support through a
PCIe-to-PCI bridge. See Section 5.2.2 for more details.
4. The number of PCI Express ports available depends on the Flexible I/O configuration. See
Section 2.7 and Table 1-3.
5. When using EHCI, USB 2.0 ports 6 and 7 are disabled on 12 port SKUs. When using xHCI,
USB 2.0 ports 12 and 13 are disabled on 12 port SKUs.
6. USB 2.0 ports 6,7,12 and 13 are disabled on 10 port SKUs.
7. 6 USB 3.0 ports requires High Speed I/O ports 5 and 6 to be configured as USB 3.0. See
Section 2.7 and Table 1-3.
8. Only USB 3.0 ports 1 and 2 are enabled.
9. When Flexible I/O ports are configured as USB 3.0, the total number of USB 2.0 only ports
reduces in direct proportion.
54 Datasheet
Introduction
10. 6 SATA ports requires High Speed I/O ports 13 and 14 to be configured as SATA. See
Section 2.7 and Table 1-3.
11. SATA ports 2 and 3 are disabled on 4 port SKUs.
12. SATA 6 Gb/s support on ports 0,1,2 and 3. SATA ports 0,1,2 and 3 also support 3 Gb/s and
1.5 Gb/s.
13. SATA 6 Gb/s support on ports 0 and 1 only. SATA ports 0 and 1 also support 3 Gb/s and 1.5
Gb/s.
14. Intel® Smart Response Technology requires an Intel® Core™ processor.
15. Intel® Anti-Theft Technology requires an Intel® Core™ processor.
16. Intel® Small Business Advantage requires an Intel® Core™ processor.
17. Intel® Small Business Advantage with the Intel® H87 Express Chipset requires 5Mb
firmware.
18. Intel® Rapid Start Technology requires an Intel® Core™ processor.
19. Intel® Identity Protection Technology requires an Intel® Core™ processor.
20. Near Field Communication is only supported in All-in-One system designs.
Table 1-3. Desktop Intel® 8 Series Chipset Family SKUs Flexible I/O Map
High Speed I/O Ports
SKU
Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
USB USB SATA SATA
USB USB USB USB 3.0 3.0 6Gb/s 6Gb/s SATA SATA SATA SATA
Port 3 Port 4 PCIe* PCIe* PCIe* PCIe* PCIe* PCIe* Port 4 Port 5
Q87 3.0 3.0 3.0 3.0
Port 3 Port 4 Port 5 Port 6 Port 7 Port 8
6Gb/s 6Gb/s 6Gb/s 6Gb/s
Port 1 Port 2 Port 5 Port 6 PCIe* PCIe* PCIe* PCIe* Port 0 Port 1 Port 2 Port 3
Port 1 Port 2 Port 1 Port 2
USB USB USB USB SATA SATA SATA SATA SATA SATA
PCIe* PCIe* PCIe* PCIe* PCIe* PCIe* PCIe* PCIe*
Q85 3.0 3.0 3.0 3.0
Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8
3Gb/s 3Gb/s 6Gb/s 6Gb/s 6Gb/s 6Gb/s
Port 1 Port 2 Port 5 Port 6 Port 4 Port 5 Port 0 Port 1 Port 2 Port 3
USB USB USB USB SATA SATA SATA SATA SATA SATA
PCIe* PCIe* PCIe* PCIe* PCIe* PCIe* PCIe* PCIe*
B85 3.0 3.0 3.0 3.0
Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8
3Gb/s 3Gb/s 6Gb/s 6Gb/s 6Gb/s 6Gb/s
Port 1 Port 2 Port 5 Port 6 Port 4 Port 5 Port 0 Port 1 Port 2 Port 3
USB USB SATA SATA
USB USB USB USB 3.0 3.0 6Gb/s 6Gb/s SATA SATA SATA SATA
Port 3 Port 4 PCIe* PCIe* PCIe* PCIe* PCIe* PCIe* Port 4 Port 5
Z87 3.0 3.0 3.0 3.0
Port 3 Port 4 Port 5 Port 6 Port 7 Port 8
6Gb/s 6Gb/s 6Gb/s 6Gb/s
Port 1 Port 2 Port 5 Port 6 PCIe* PCIe* PCIe* PCIe* Port 0 Port 1 Port 2 Port 3
Port 1 Port 2 Port 1 Port 2
USB USB SATA SATA
USB USB USB USB 3.0 3.0 6Gb/s 6Gb/s SATA SATA SATA SATA
Port 3 Port 4 PCIe* PCIe* PCIe* PCIe* PCIe* PCIe* Port 4 Port 5
H87 3.0 3.0 3.0 3.0
Port 3 Port 4 Port 5 Port 6 Port 7 Port 8
6Gb/s 6Gb/s 6Gb/s 6Gb/s
Port 1 Port 2 Port 5 Port 6 PCIe* PCIe* PCIe* PCIe* Port 0 Port 1 Port 2 Port 3
Port 1 Port 2 Port 1 Port 2
NOTES:
1. Ports listed with NA are not available and are disabled.
Datasheet 55
Introduction
Table 1-4. Mobile Intel® 8 Series Chipset Family SKUs
SKU Name
Mobile Mobile Mobile
Feature Set Intel® Intel® Intel®
QM87 HM87 HM86
Express Express Express
Chipset Chipset Chipset
Flexible I/O Yes Yes Yes4
PCI Express* 2.0 Ports 85 85 85
Total number of USB ports 14 14 14
• USB 3.0 Capable Ports (SuperSpeed and all USB 2.0 speeds) 4(6)6 4(6) 2(4)7
• USB 2.0 Only Ports 10(8)8 10(8)8 12(10)8
Total number of SATA ports 4(6)9 4(6)9 410
11 11
• SATA Ports (6 Gb/s, 3 Gb/s, and 1.5 Gb/s) 2(4) 2(4) 212
• SATA Ports (3 Gb/s and 1.5 Gb/s only) 2 2 2
VGA Yes Yes Yes
Intel® Wireless Display (WiDi) Yes Yes Yes
AHCI Yes Yes Yes
Intel® Rapid Storage Technology RAID 0/1/5/10 Support Yes Yes No
Intel® Smart Response Technology13 Yes Yes No
Intel® Anti-Theft Technology14 Yes Yes Yes
Intel® Active Management Technology 9.0 Yes No No
Intel® Small Business Advantage 15
Yes Yes16 No
Intel Rapid Start Technology17 Yes Yes Yes
Intel® Identity Protection Technology (Intel® IPT)18 Yes Yes Yes
Near Field Communication Yes Yes Yes
ACPI S1 State Support No No No
NOTES:
1. Contact your local Intel Field Sales Representative for currently available PCH SKUs.
2. Table above shows feature difference between the PCH SKUs. If a feature is not listed in
the table, it is considered a Base feature that is included in all SKUs.
3. PCI Legacy Mode may optionally be used allowing external PCI bus support through a
PCIe-to-PCI bridge. See Section 5.2.2 for more details.
4. Flexible I/O is only available on High Speed I/O ports 5 and 6 which are shared between
USB 3.0 and PCI Express. High Speed I/O ports 13 and 14 are fixed as SATA Gen 2 ports.
See Section 2.7 and Table 1-5.
5. The number of PCI Express ports available depends on the Flexible I/O configuration. See
Section 2.7 and Table 1-5.
6. 6 USB 3.0 ports requires High Speed I/O ports 5 and 6 to be configured as USB 3.0. See
Section 2.7 and Table 1-5.
7. USB 3.0 ports 5 and 6 are disabled on the Intel® HM86 Express Chipset.
8. When Flexible I/O ports are configured as USB 3.0, the total number of USB 2.0 only ports
reduces in direct proportion.
9. 6 SATA ports requires High Speed I/O ports 13 and 14 to be configured as SATA. See
Section 2.7 and Table 1-5.
10. SATA ports 1 and 3 are disabled on 4 port SKUs.
11. SATA 6 Gb/s support on ports 0,1,4 and 5. SATA ports 0,1,4 and 5 also support 3 Gb/s and
1.5 Gb/s. In order to support 4 SATA 6 Gb/s ports, High Speed I/O ports 13 and 14 must
be configured as SATA. See Section 2.7 and Table 1-5.
12. SATA 6 Gb/s support on port 4 and port 5. SATA ports 4 and 5 also support 3 Gb/s and
1.5 Gb/s.
13. Intel® Smart Response Technology requires an Intel® Core™ processor.
56 Datasheet
Introduction
14. Intel® Anti-Theft Technology requires an Intel® Core™ processor.
15. Intel® Small Business Advantage requires an Intel® Core™ processor.
16. Intel® Small Business Advantage with the Intel® HM87 Express Chipset requires 5Mb
firmware.
17. Intel® Rapid Start Technology requires an Intel® Core™ processor.
18. Intel® Identity Protection Technology requires an Intel® Core™ processor.
Table 1-5. Mobile Intel® 8 Series Chipset Family SKUs Flexible I/O Map
High Speed I/O Ports
SKU
Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
USB USB SATA SATA
USB USB USB USB 3.0 3.0 6Gb/s 6Gb/s SATA SATA SATA SATA
Port 3 Port 4 PCIe* PCIe* PCIe* PCIe* PCIe* PCIe* Port 4 Port 5
QM87 3.0 3.0 3.0 3.0
Port 3 Port 4 Port 5 Port 6 Port 7 Port 8
6Gb/s 6Gb/s 3Gb/s 3Gb/s
Port 1 Port 2 Port 5 Port 6 PCIe* PCIe* PCIe* PCIe* Port 0 Port 1 Port 2 Port 3
Port 1 Port 2 Port 1 Port 2
USB USB SATA SATA
USB USB USB USB 3.0 3.0 6Gb/s 6Gb/s SATA SATA SATA SATA
Port 3 Port 4 PCIe* PCIe* PCIe* PCIe* PCIe* PCIe* Port 4 Port 5
HM87 3.0 3.0 3.0 3.0
Port 3 Port 4 Port 5 Port 6 Port 7 Port 8
6Gb/s 6Gb/s 3Gb/s 3Gb/s
Port 1 Port 2 Port 5 Port 6 PCIe* PCIe* PCIe* PCIe* Port 0 Port 1 Port 2 Port 3
Port 1 Port 2 Port 1 Port 2
USB USB
USB USB 3.0 3.0 SATA SATA SATA SATA
Port 3 Port 4 PCIe* PCIe* PCIe* PCIe* PCIe* PCIe*
HM86 3.0 3.0 NA NA
Port 3 Port 4 Port 5 Port 6 Port 7 Port 8
6Gb/s 6Gb/s 3Gb/s NA 3Gb/s NA
Port 1 Port 2 PCIe* PCIe* Port 4 Port 5 Port 0 Port 2
Port 1 Port 2
NOTES:
1. Ports listed with NA are not available and are disabled.
Datasheet 57
Introduction
Table 1-6. Server / Workstation Intel® C220 Series Chipset Family SKUs
SKU Name
Feature Set Intel® Intel® Intel®
C222 C224 C226
Chipset Chipset Chipset
Flexible I/O No No Yes
PCI Express* 2.0 Ports 8 8 84
Total number of USB ports 105 126 14
7 8
• USB 3.0 Capable Ports (SuperSpeed and all USB 2.0 speeds) 2 4 4(6)9
• USB 2.0 Only Ports 8 8 10(8)10
Total number of SATA ports 6 6 4(6)11
13
• SATA Ports (6 Gb/s, 3 Gb/s, and 1.5 Gb/s) 2 12 4 4(6)11
• SATA Ports (3 Gb/s and 1.5 Gb/s only) 4 2 0
VGA No No Yes
Intel® Wireless Display (WiDi) No No Yes
AHCI Yes Yes Yes
Intel® Rapid Storage Technology RAID 0/1/5/10 Support Yes Yes Yes
Intel® Smart Response Technology14 No No Yes
Intel® Anti-Theft Technology15 No No No
Intel® Active Management Technology 9.0 No No Yes
Intel® Small Business Advantage No No No
Intel Rapid Start Technology No No No
Intel® Identity Protection Technology (Intel® IPT)16 No No Yes
Near Field Communication No No No
ACPI S1 State Support No No No
NOTES:
1. Contact your local Intel Field Sales Representative for currently available PCH SKUs.
2. Table above shows feature differences between the PCH SKUs. If a feature is not listed in
the table, it is considered a Base feature that is included in all SKUs
3. PCI Legacy Mode may optionally be used allowing external PCI bus support through a
PCIe-to-PCI bridge. See Section 5.2.2 for more details.
4. The number of PCI Express ports available depends on the Flexible I/O configuration. See
Section 2.7 and Table 1-7.
5. USB 2.0 ports 6,7,12 and 13 are disabled on 10 port SKUs.
6. USB 2.0 ports 6 and 7 are disabled on 12 port SKUs.
7. Only USB 3.0 ports 1 and 2 are enabled.
8. Only USB 3.0 ports 1,2,5 and 6 are enabled.
9. 6 USB 3.0 ports require High Speed I/O ports 5 and 6 to be configured as USB 3.0. See
Section 2.7 and Table 1-7.
10. When Flexible I/O ports are configured as USB 3.0, the total number of USB 2.0 only ports
reduces in direct proportion.
11. 6 SATA ports require High Speed I/O ports 13 and 14 to be configured as SATA. See
Section 2.7 and Table 1-7.
12. SATA 6 Gb/s support on ports 0 and 1 only. SATA ports 0 and 1 also support 3 Gb/s and
1.5 Gb/s.
13. SATA 6 Gb/s support on ports 0,1,2 and 3. SATA ports 0,1,2 and 3 also support 3 Gb/s and
1.5 Gb/s.
14. Intel® Smart Response Technology requires an Intel® Core™ processor.
58 Datasheet
Introduction
15. Intel® Anti-Theft Technology requires an Intel® Core™ processor.
16. Intel® Identity Protection Technology requires an Intel® Xeon® processor.
Table 1-7. Server / Workstation Intel® C220 Series Chipset Family SKUs Flexible I/O
Map
High Speed I/O Ports
SKU
Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
USB USB SATA SATA SATA SATA SATA SATA
PCIe* PCIe* PCIe* PCIe* PCIe* PCIe* PCIe* PCIe*
C222 3.0 3.0 NA NA
Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8
3Gb/s 3Gb/s 6Gb/s 6Gb/s 3Gb/s 3Gb/s
Port 1 Port 2 Port 4 Port 5 Port 0 Port 1 Port 2 Port 3
USB USB USB USB SATA SATA SATA SATA SATA SATA
PCIe* PCIe* PCIe* PCIe* PCIe* PCIe* PCIe* PCIe*
C224 3.0 3.0 3.0 3.0
Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8
3Gb/s 3Gb/s 6Gb/s 6Gb/s 6Gb/s 6Gb/s
Port 1 Port 2 Port 5 Port 6 Port 4 Port 5 Port 0 Port 1 Port 2 Port 3
USB USB SATA SATA
USB USB USB USB 3.0 3.0 6Gb/s 6Gb/s SATA SATA SATA SATA
Port 3 Port 4 PCIe* PCIe* PCIe* PCIe* PCIe* PCIe* Port 4 Port 5
C226 3.0 3.0 3.0 3.0
Port 3 Port 4 Port 5 Port 6 Port 7 Port 8
6Gb/s 6Gb/s 6Gb/s 6Gb/s
Port 1 Port 2 Port 5 Port 6 PCIe* PCIe* PCIe* PCIe* Port 0 Port 1 Port 2 Port 3
Port 1 Port 2 Port 1 Port 2
NOTES:
1. Ports listed with NA are not available and are disabled.
Datasheet 59
Introduction
1.4 Device and Revision ID Table
NOTES:
1. PCH contains two SATA controllers. The SATA Device ID is dependent upon which SATA mode is selected
by BIOS and what RAID capabilities exist in the SKU.
2. The SATA RAID Controller Device ID is dependent upon the AIE bit setting (bit 7 of D31:F2:Offset 9Ch).
3. SATA Controller 2 (D31:F5) is only visible when D31:F2 CC.SCC =01h
4. LAN Device ID is loaded from EEPROM. If EEPROM contains either 0000h or FFFFh in the Device ID
location, then 1E33h is used. Refer to the appropriate Intel GbE physical layer Transceiver (PHY)
datasheet for LAN Device IDs.
5. For a given stepping, not all SKUs may be available.
6. This table shows the default PCI Express Function Number-to-Root Port mapping. Function numbers for
a given root port are assignable through the “Root Port Function Number and Hide for PCI Express Root
Ports” register (RCBA+0404h).
The Revision ID (RID) register is an 8-bit register located at offset 08h in the PCI
header of every PCI/PCIe function. The RID register is used by software to identify a
particular component stepping when a driver change or patch unique to that stepping is
needed.
Table 1-8. PCH Device and Revision ID Table (Sheet 1 of 3)
Device Descrip- C1
Function tion
Dev ID
SRID
Comments
8C00h 04h Desktop: Non-AHCI and Non-RAID Mode.
8C01h 04h Mobile: Non-AHCI and Non-RAID Mode.
8C02h 04h Desktop: AHCI Mode.
8C03h 04h Mobile: AHCI Mode.
8C04h 04h Desktop: RAID Capable3 if AIE (D31:F2 Offset 9Ch bit 7) = 1.
Desktop: RAID Capable3 with or without Intel® Smart Response
2822h 04h Technology, if AIE (D31:F2 Offset 9Ch bit 7) = 0 AND AIES
(D31:F2 Offset 9Ch bit 6) = 0.
8C05h 04h Mobile: RAID Capable3 if AIE (D31:F2 Offset 9Ch bit 7) = 1.
D31:F2 SATA1 Mobile: RAID Capable3 with or without Intel® Smart Response
282Ah 04h Technology, if AIE (D31:F2 Offset 9Ch bit 7) = 0.
Desktop: RAID Capable3 and Intel® Smart Response Technology,
8C06h 04h if AIE (D31:F2 Offset 9Ch bit 7) = 1.
Server/Workstation: RAID Capable3 and Intel® Smart Response
2826h 04h Technology, if AIE (D31:F2 Offset 9Ch bit 7) = 0 AND AIES
(D31:F2 Offset 9Ch bit 6) = 1.
Mobile: RAID Capable3 and Intel® Smart Response Technology, if
8C07h 04h AIE (D31:F2 Offset 9Ch bit 7) = 1.
8C0Eh 04h Desktop: RAID 1 Only.
8C0Fh 04h Mobile: RAID 1 Only.
Desktop: Non-AHCI and Non-RAID Mode
8C08h 04h (Ports 4 and 5)
D31:F5 SATA
Mobile: Non-AHCI and Non-RAID Mode
8C09h 04h (Ports 4 and 5)
8C10h 04h Desktop and Mobile (When D28:F0:ECh:bit 1= 0)
PCI
D28:F0 Express* 244Eh 04h Desktop (When D28:F0:ECh:bit 1 = 1)
Port 1
2448h 04h Mobile (When D28:F0:ECh:bit 1 = 1)
60 Datasheet
Introduction
Table 1-8. PCH Device and Revision ID Table (Sheet 2 of 3)
Device Descrip- C1
Function tion
Dev ID
SRID
Comments
8C12h 04h Desktop and Mobile (When D28:F1:ECh:bit 1 = 0)
PCI
D28:F1 Express 244Eh 04h Desktop (When D28:F1:ECh:bit 1 = 1)
Port 2
2448h 04h Mobile (When D28:F1:ECh:bit 1 = 1)
8C14h 04h Desktop and Mobile (When D28:F2:ECh:bit 1 = 0)
PCI
D28:F2 Express 244Eh 04h Desktop (When D28:F2:ECh:bit 1 = 1)
Port 3
2448h 04h Mobile (When D28:F2:ECh:bit 1 = 1)
8C16h 04h Desktop and Mobile (When D28:F3:ECh:bit 1 = 0)
PCI
D28:F3 Express 244Eh 04h Desktop (When D28:F3:ECh:bit 1 = 1)
Port 4
2448h 04h Mobile (When D28:F3:ECh:bit 1 = 1)
8C18h 04h Desktop and Mobile (When D28:F4:ECh:bit 1 = 0)
PCI
D28:F4 Express 244Eh 04h Desktop (When D28:F4:ECh:bit 1 = 1)
Port 5
2448h 04h Mobile (When D28:F4:ECh:bit 1 = 1)
8C1Ah 04h Desktop and Mobile (When D28:F5:ECh:bit 1 = 0)
PCI
D28:F5 Express 244Eh 04h Desktop (When D28:F5:ECh:bit 1 = 1)
Port 6
2448h 04h Mobile (When D28:F5:ECh:bit 1 = 1)
8C1Ch 04h Desktop and Mobile (When D28:F6:ECh:bit 1 = 0)
PCI
D28:F6 Express 244Eh 04h Desktop (When D28:F6:ECh:bit 1 = 1)
Port 7
2448h 04h Mobile (When D28:F6:ECh:bit 1 = 1)
8C1Eh 04h Desktop and Mobile (When D28:F7:ECh:bit 1 = 0)
PCI
D28:F7 Express 244Eh 04h Desktop (When D28:F7:ECh:bit 1 = 1)
Port 8
2448h 04h Mobile (When D28:F7:ECh:bit 1 = 1)
Intel®
High
D27:F0 8C20h 04h Desktop and Mobile - All SKUs.
Definition
Audio
D31:F3 SMBus 8C22h 04h Desktop and Mobile - All SKUs.
D31:F6 Thermal 8C24h 04h Desktop and Mobile - All SKUs.
USB EHCI
D29:F0 8C26h 04h Desktop and Mobile - All SKUs.
#1
USB EHCI
D26:F0 8C2Dh 04h Desktop and Mobile - All SKUs.
#2
D20:F0 USB xHCI 8C31h 04h Desktop and Mobile - All SKUs.
D25:F0 LAN 8C33h 04h Desktop and Mobile - All SKUs.
® ME
Intel
D22:F0 Interface 8C3Ah 04h Desktop and Mobile - All SKUs.
#1
Intel ME
D22:F1 Interface 8C3Bh 04h Desktop and Mobile - All SKUs.
#2
D22:F2 IDE-R 8C3Ch 04h Desktop and Mobile - All SKUs.
D22:F3 KT 8C3Dh 04h Desktop and Mobile - All SKUs.
Datasheet 61
Introduction
Table 1-8. PCH Device and Revision ID Table (Sheet 3 of 3)
Device Descrip- C1
Function tion
Dev ID
SRID
Comments
8C41h 04h LPC Controller (Mobile Full Featured Engineering Sample).
8C42h 04h LPC Controller (Desktop Full Featured Engineering Sample).
8C44h 04h LPC Controller (Z87 SKU).
8C46h 04h LPC Controller (Z85 SKU).
8C49h 04h LPC Controller (HM86 SKU).
8C4Ah 04h LPC Controller (H87 SKU).
8C4Bh 04h LPC Controller (HM87 SKU).
D31:F0 LPC 8C4Ch 04h LPC Controller (Q85 SKU).
8C4Eh 04h LPC Controller (Q87 SKU).
8C4Fh 04h LPC Controller (QM87 SKU).
8C50h 04h LPC Controller (B85 SKU).
8C52h 04h LPC Controller (C222 SKU).
8C54h 04h LPC Controller (C224 SKU).
8C56h 04h LPC Controller (C226 SKU).
8C5Ch 04h LPC Controller (H81 SKU).
NOTES:
1. PCH contains two SATA controllers. The SATA Device ID is dependent upon which SATA
mode is selected by BIOS and what RAID capabilities exist in the SKU.
2. The SATA RAID Controller Device ID is dependent upon the AIE bit setting (bit 7 of
D31:F2:Offset 9Ch).
3. SATA Controller 2 (D31:F5) is only visible when D31:F2 CC.SCC =01h.
4. LAN Device ID is loaded from EEPROM. If EEPROM contains either 0000h or FFFFh in the
Device ID location, then 8C33h is used. Refer to the appropriate Intel® GbE physical layer
Transceiver (PHY) datasheet for LAN Device IDs.
5. For a given stepping, not all SKUs may be available.
6. This table shows the default PCI Express Function Number-to-Root Port mapping. Function
numbers for a given root port are assignable through the “Root Port Function Number and
Hide for PCI Express Root Ports” register (RCBA+0404h).
§§
62 Datasheet
Signal Description
2 Signal Description
This chapter provides a detailed description of each signal. The signals are arranged in
functional groups according to their associated interface.
The “#” symbol at the end of the signal name indicates that the active, or asserted
state occurs when the signal is at a low voltage level. When “#” is not present, the
signal is asserted when voltage level is high.
The following notations are used to describe the signal type:
I Input Pin.
O Output Pin.
OD O Open Drain Output Pin.
I/OD Bi-directional Input/Open Drain Output Pin.
I/O Bi-directional Input/Output Pin.
CMOS CMOS buffers. 1.5 V tolerant.
COD CMOS Open Drain buffers. 3.3 V tolerant.
HVCMOS High Voltage CMOS buffers. 3.3 V tolerant.
A Analog reference or output.
The “Type” for each signal is indicative of the functional operating mode of the signal.
Unless otherwise noted in Section 3.2 or Section 3.3, a signal is considered to be in the
functional operating mode after RTCRST# de-asserts for signals in the RTC well, after
RSMRST# de-asserts for signals in the suspend well, after PWROK asserts for signals in
the core well, after DPWROK asserts for signals in the DeepSx well, after APWROK
asserts for signals in the Active Sleep well.
Note: Core well includes 1.05 V, 1.5 V and 3.3 V rails powering PCH logic and these rails may
be shut off in S3, S4, S5, and G3 states.
Datasheet 63
Signal Description
Figure 2-1. PCH Interface Signals Block Diagram (not all signals are on all SKUs)
FDI_RXP[1:0]
Intel® Flexible FDI_RXN[1:0]
GPIO50
Display FDI_CSYNC
GPIO52 FDI_INT
Interface
GPIO54
GPIO51
MISC. FDI_RCOMP
FDI_IREF
GPIO53 Signals
GPIO55 Controller CL_CLK ; CL_DATA
CLKIN_33MHZLOOPBACK Link CL_RST#
PET[p,n][8:1]
PCI Express* PER[p,n][8:1]
PMSYNCH Interface PCIE_RCOMP
RCIN# Processor PCIE_IREF
THRMPTRIP#
PROCPWRGD Interface
SATA_TX[P,N][5:0]
SATA_RX[P,N][5:0]
SPI_IO1 SATA_RCOMP
SPI_IO2 SATA_IREF
SPI_MISO SATALED#
SPI_MOSI
SPI_CS0#; SPI_CS1#;SPI_CS2# SPI Serial ATA SATA0GP/GPIO21
SATA1GP/GPIO19
SPI_CLK Interface SATA2GP/GPIO36
SATA3GP/GPIO37
SATA4GP/GPIO16
SATA5GP/GPIO49
LAD[3:0]
LPC / SCLOCK/GPIO22, SLOAD/GPIO38
LFRAME# FWH SDATAOUT0/GPIO39, SDATAOUT1/GPIO48
LDRQ0#; LDRQ1#/GPIO23 SUSWARN#/SUSPWRDNACK/GPIO30
Interface DPWROK
SYS_RESET#
RSMRST#
CLKOUT_DP_[P,N] SLP_S3#
CLKOUT_DMI_[P,N] SLP_S4#
XTAL25_OUT SLP_S5#/GPIO63
CLKOUT_PEG_A_[P,N];CLKOUT_PEG_B_[P,N]
CLKOUT_PCIE[7:0]_[P,N]
Clock SLP_A#
CLKRUN#/GPIO32
CLKOUT_ITPXDP_[P,N] Outputs PWROK
CLKOUT_33MHz[4:0] AWROK
CLKOUTFLEX0/GPIO64;CLKOUTFLEX1/GPIO65 PWRBTN#
RI#
CLKOUTFLEX2/GPIO66;CLKOUTFLEX3/GPIO67
Power WAKE#
CLKIN_DMI_[P,N]
Mgnt. SUS_STAT#/GPIO61
SUSCLK/GPIO62
CLKIN_SATA_[P,N] BATLOW#/GPIO72
CLKIN_DOT96[P,N] PLTRST#
XTAL25_IN;REF14CLKIN BMBUSY#/GPIO0
PCIECLKRQ0#/GPIO73;PCIECLKRQ1#/GPIO18 Clock GPIO34
PCIECLKRQ2#/GPIO20/SMI#;PCIECLKRQ3#/GPIO25 ACPRESENT/GPIO31
PCIECLKRQ4#/GPIO26;PCIECLKRQ5#/GPIO44 Inputs DRAMPWROK
PCIECLKRQ6#/GPIO45;PCIECLKRQ7#/GPIO46 LAN_PHY_PWR_CTRL/GPIO12
PEG_A_CLKRQ#/GPIO47;PEG_B_CLKRQ#/GPIO56 SLP_WLAN#/GPIO29
SUSACK#
SLP_SUS#
PLTRST#
SERIRQ Interrupt
PIRQ[D:A]# Intel® HDA_RST#
PIRQ[H:E]#/GPIO[5:2] Interface HDA_SYNC
High HDA_BCLK
Definition HDA_SDO
HDA_SDIN[3:0]
USB[13:0][P,N] Audio HDA_DOCK_EN#/HDA_DOCK_RST#
OC0#/GPIO59; OC1#/GPIO40
OC2#/GPIO41; OC3#/GPIO42
OC4#/GPIO43; OC5#/GPIO9 USB
OC6#/GPIO10; OC7#/GPIO14 Direct DMI_TX[P,N][3:0]
USBRBIAS, USBRBIAS#
Media DMI_RX[P,N][3:0]
USB3[T,R][p,n][6:1] DMI_RCOMP
Interface DMI_IREF
RTCX1
RTCX2 RTC SMBus SMBDATA; SMBCLK
Interface SMBALERT#/GPIO11
INTVRMEN, DSWVRMEN
SPKR
INTRUDER#;
SRTCRST#; RTCRST#
GPIO35/NMI#
Misc. System SML[1:0]DATA;SML[1:0]CLK
GPIO24 Signals Mgnt. SML0ALERT#/GPIO60
PME# SML1ALERT#/TEMP_ALERT#/GPIO74
General VGA_RED;VGA_GREEN;VGA_BLUE
DAC_IREF
GPIO[72,57,32,28,27,15,8] Purpose Analog VGA_HSYNC;VGA_VSYNC
I/O Display VGA_DDC_CLK;VGA_DDC_DATA
VGA_IRTN
PWM[3:0]
TACH7/GPIO71;TACH6/GPIO70; TACH5/GPIO69;TACH4/GPIO68 Fan
TACH3/GPIO7; TACH2/GPIO6; TACH1/GPIO1;TACH0/GPIO17 Speed
SST DDP[B:D]_AUX[P,N]
PECI Control Digital DDP[B:D]_HPD
Display DDP[B:D]_CTRLCLK
DDP[B:D]_CTRLDATA
JTAGTCK Sideband eDP_BKLTEN
JTAGTMS JTAG
JTAGTDI Signals eDP_BKLTCTL
eDP_VDDEN
JTAGTDO
64 Datasheet
Signal Description
2.1 Flexible I/O
The Intel® 8 Series / C220 Series Chipset Family Platform Controller Hub (PCH)
implements Flexible I/O, a technology to allow some high speed signals to be
configured as PCIe*, USB 3.0, or SATA signals. There are a total of 18 High Speed I/O
Ports in the PCH and, through soft straps, four of these ports can have their
functionality selected to meet the I/O needs of the platform. Table 2-1 illustrates high
speed I/O ports mapping to PCIe, USB 3.0 and SATA signals.
Table 2-1. I/O Flexibility Signal Mapping
High Speed
GbE Map PCIe Signals USB 3.0 Signals SATA Signals
I/O Ports
USB3Tp/n1
1 — — —
USB3Rp/n1
USB3Tp/n2
2 — — —
USB3Rp/n2
USB3Tp/n5
3 — — —
USB3Rp/n5
USB3Tp/n6
4 — — —
USB3Rp/n6
000 PETp/n1 USB3Tp/n3
5 —
(soft strap) PERp/n1 USB3Rp/n3
001 PETp/n2 USB3Tp/n4
6 —
(soft strap) PERp/n2 USB3Rp/n4
010 PETp/n3
7 — —
(soft strap) PERp/n3
011 PETp/n4
8 — —
(soft strap) PERp/n4
100 PETp/n5
9 — —
(soft strap) PERp/n5
101 PETp/n6
10 — —
(soft strap) PERp/n6
110 PETp/n7
11 — —
(soft strap) PERp/n7
111 PETp/n8
12 — —
(soft strap) PERp/n8
PETp/n1 SATA_TXp/n4
13 — —
PERp/n1 SATA_RXp/n4
PETp/n2 SATA_TXp/n5
14 — —
PERp/n2 SATA_RXp/n5
SATA_TXp/n0
15 — — —
SATA_RXp/n0
SATA_TXp/n1
16 — — —
SATA_RXp/n1
SATA_TXp/n2
17 — — —
SATA_RXp/n2
SATA_TXp/n3
18 — — —
SATA_RXp/n3
Datasheet 65
Signal Description
NOTES:
1. High speed I/O ports 5 and 6 can be configured as either PCIe port 1 and 2 or USB 3.0 port
3 and 4.
2. High speed I/O ports 13 and 14 can be configured as either PCIe port 1 and 2 or SATA port
4 and 5.
3. Maximum of 8 PCIe* ports, 6 USB 3.0 Ports or 6 SATA ports possible. GbE uses the
physical interface of PCIe ports so having 8 PCIe ports + 1 GbE simultaneously does not
mean a total of 9 PCIe ports. 8 PCIe ports + 1 GbE simultaneously is supported (depending
on SKU configuration).
4. Refer to Chapter 5.22 for more details.
2.2 USB Interface
Note: The USB2.0 signals in the PCH integrate pull-down resistors and provide an output
driver impedance of 45 that requires no external series resistor. No external pull-up/
pull-down resistors should be added to the USB2.0 signals. USB ports not needed can
be left floating as No Connect.
Note: The voltage divider formed by the device pull-up and the host pull-down will ensure the
data wire park at a safe voltage level, which is below the VBUS value. This ensures that
the host/hub will not see 5 V at the wire when inter-operating with devices that have
VBUS at 5 V.
Note: All USB 2.0 register addresses throughout the datasheet correspond to the external pin
names. Refer to Table 2-2 to know exactly how the USB pins are mapped to the
different internal ports within the xHCI and EHCI controllers.
Table 2-2. USB Interface Signals (Sheet 1 of 4)
xHCI EHCI
Name Type Description
Port Port
USB 2.0 Port 0 Transmit/Receive Differential Pair 0:
USB2p0 This USB 2.0 signal pair can be routed to xHCI or EHCI
0 0 I/O
USB2n0 Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
USB 2.0 Port 1 Transmit/Receive Differential Pair 1:
USB2p1 This USB 2.0 signal pair can be routed to xHCI or EHCI
1 1 I/O
USB2n1 Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
USB 2.0 Port 2 Transmit/Receive Differential Pair 2:
USB2p2 This USB 2.0 signal pair can be routed to xHCI or EHCI
2 2 I/O
USB2n2 Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
USB 2.0 Port 3 Transmit/Receive Differential Pair 3:
USB2p3 This USB 2.0 signal pair can be routed to xHCI or EHCI
3 3 I/O
USB2n3 Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
USB 2.0 Port 4 Transmit/Receive Differential Pair 4:
USB2p4 This USB 2.0 signal pair can be routed to xHCI or EHCI
8 4 I/O
USB2n4 Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
66 Datasheet
Signal Description
Table 2-2. USB Interface Signals (Sheet 2 of 4)
xHCI EHCI
Name Type Description
Port Port
USB 2.0 Port 5 Transmit/Receive Differential Pair 5:
USB2p5 This USB 2.0 signal pair can be routed to xHCI or EHCI
9 5 I/O
USB2n5 Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
USB 2.0 Port 6 Transmit/Receive Differential Pair 6:
USB2p6 This USB 2.0 signal pair can be mapped to xHCI or EHCI
12 6 I/O
USB2n6 Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
USB 2.0 Port 7 Transmit/Receive Differential Pair 7:
USB2p7 This USB 2.0 signal pair can be mapped to xHCI or EHCI
13 7 I/O
USB2n7 Controller 1 through software and should map to a USB
connector with one of the overcurrent OC Pins 0-3.
USB 2.0 Port 8 Transmit/Receive Differential Pair 8:
USB2p8 This USB 2.0 signal pair can be mapped to xHCI or EHCI
4 8 I/O
USB2n8 Controller 2 through software and should map to a USB
connector with one of the overcurrent OC Pins 4–7.
USB 2.0 Port 9 Transmit/Receive Differential Pair 9:
USB2p9 This USB 2.0 signal pair can be mapped to xHCI or EHCI
5 9 I/O
USB2n9 Controller 2 through software and should map to a USB
connector with one of the overcurrent OC Pins 4–7.
USB 2.0 Port 10 Transmit/Receive Differential Pair
USB2p10 10:This USB 2.0 signal pair can be mapped to xHCI or
6 10 I/O
USB2n10 EHCI Controller 2 through software and should map to a
USB connector with one of the overcurrent OC Pins 4–7.
USB 2.0 Port 11 Transmit/Receive Differential Pair
USB2p11 11: This USB 2.0 signal pair can be mapped to xHCI or
7 11 I/O
USB2n11 EHCI Controller 2 through software and should map to a
USB connector with one of the overcurrent OC Pins 4–7.
USB 2.0 Port 12 Transmit/Receive Differential Pair
USB2p12 12: This USB 2.0 signal pair can be mapped to xHCI or
10 12 I/O
USB2n12 EHCI Controller 2 through software and should map to a
USB connector with one of the overcurrent OC Pins 4–7.
USB 2.0 Port 13 Transmit/Receive Differential Pair
USB2p13 13: This USB 2.0 signal pair can be mapped to xHCI or
11 13 I/O
USB2n13 EHCI Controller 2 through software and should map to a
USB connector with one of the overcurrent OC Pins 4–7.
USB 3.0 Differential Transmit Pair 1: These are USB
3.0-based outbound high-speed differential signals,
USB3Tp1
1 - O mapped to High Speed I/O (HSIO) Port #1 and the xHCI
USB3Tn1
Controller. It should map to a USB connector with one of
the OC (overcurrent) pins 0–7.
USB 3.0 Differential Receive Pair 1: These are USB
3.0-based inbound high-speed differential signals, mapped
USB3Rp1
1 - I to High Speed I/O (HSIO) Port #1 and the xHCI Controller.
USB3Rn1
It should map to a USB connector with one of the OC
(overcurrent) pins 0–7.
Datasheet 67
Signal Description
Table 2-2. USB Interface Signals (Sheet 3 of 4)
xHCI EHCI
Name Type Description
Port Port
USB 3.0 Differential Transmit Pair 2: These are USB
3.0-based outbound high-speed differential signals,
USB3Tp2
2 - O mapped to High Speed I/O (HSIO) Port #2 and the xHCI
USB3Tn2
Controller. It should map to a USB connector with one of
the OC (overcurrent) pins 0–7.
USB 3.0 Differential Receive Pair 2: These are USB
3.0-based inbound high-speed differential signals, mapped
USB3Rp2
2 - I to High Speed I/O (HSIO) Port #2 and the xHCI Controller.
USB3Rn2
It should map to a USB connector with one of the OC
(overcurrent) pins 0–7.
USB 3.0 Differential Transmit Pair 3: These are USB
3.0-based outbound high-speed differential signals,
mapped to High Speed I/O (HSIO) Port 5 and the xHCI
Controller. It should map to a USB connector with one of
USB3Tp3
3 - O the OC (overcurrent) pins 0–7.
USB3Tn3
NOTE: Use FITC to set the soft straps that select this port
as USB 3.0 Port 3. Default configuration is PCIe
Port 1.
USB 3.0 Differential Receive Pair 3: These are USB
3.0-based inbound high-speed differential signals, mapped
to High Speed I/O (HSIO) Port 5 and the xHCI Controller.
It should map to a USB connector with one of the OC
USB3Rp3
3 - I (overcurrent) pins 0–7.
USB3Rn3
NOTE: Use FITC to set the soft straps that select this port
as USB 3.0 Port 3. Default configuration is PCIe
Port 1.
USB 3.0 Differential Transmit Pair 4: These are USB
3.0-based outbound high-speed differential signals,
mapped to High Speed I/O (HSIO) Port #6 and the xHCI
Controller. It should map to a USB connector with one of
USB3Tp4 the OC (overcurrent) pins 0–7.
4 - O
USB3Tn4
NOTE: Use FITC to set the soft straps that select this port
as USB 3.0 Port 4. Default configuration is PCIe
Port 2.
USB 3.0 Differential Receive Pair 4: These are USB
3.0-based inbound high-speed differential signals, mapped
to High Speed I/O (HSIO) Port #6 and the xHCI Controller.
It should map to a USB connector with one of the OC
USB3Rp4
4 - I (overcurrent) pins 0–7.
USB3Rn4
NOTE: Use FITC to set the soft straps that select this port
as USB 3.0 Port 4. Default configuration is PCIe
Port 2.
USB 3.0 Differential Transmit Pair 5: These are USB
3.0-based outbound high-speed differential signals,
USB3Tp5
5 - O mapped to High Speed I/O (HSIO) Port #3 and the xHCI
USB3Tn5
Controller. It should map to a USB connector with one of
the OC (overcurrent) pins 0–7.
68 Datasheet
Signal Description
Table 2-2. USB Interface Signals (Sheet 4 of 4)
xHCI EHCI
Name Type Description
Port Port
USB 3.0 Differential Receive Pair 5: These are USB
3.0-based inbound high-speed differential signals, mapped
USB3Rp5
5 - I to High Speed I/O (HSIO) Port #3 and the xHCI Controller.
USB3Rn5
It should map to a USB connector with one of the OC
(overcurrent) pins 0–7.
USB 3.0 Differential Transmit Pair 6: These are USB
3.0-based outbound high-speed differential signals,
USB3Tp6
6 - O mapped to High Speed I/O (HSIO) Port #4 and the xHCI
USB3Tn6
Controller. It should map to a USB connector with one of
the OC (overcurrent) pins 0–7.
USB 3.0 Differential Receive Pair 6: These are USB
3.0-based inbound high-speed differential signals, mapped
USB3Rp6
6 - I to High Speed I/O (HSIO) Port #4 and the xHCI Controller.
USB3Rn6
It should map to a USB connector with one of the OC
(overcurrent) pins 0–7.
Overcurrent Indicators: These signals set
corresponding bits in the USB controllers to indicate that
an overcurrent condition has occurred.
OC[7:0]# is the default (Native) function for these pins
OC0#/GPIO59
but they may be configured as GPIOs instead.
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42 NOTES:
- - I 1. OC pins are 3.3 V tolerant.
OC4#/GPIO43
OC5#/GPIO9 2. Sharing of OC pins is required to cover all 14 USB
OC6#/GPIO10 connectors but no more than 1 OC line may be
OC7#/GPIO14 connected to a USB connector.
3. OC[3:0]# should be connected with USB 2.0 ports 0–
7 and any 4 of USB 3.0 ports 1–6.
4. OC[7:4]# should be connected with USB 2.0 ports 8–
13 and any 4 of USB 3.0 ports 1–6.
USB Resistor Bias: Analog connection point for an
external resistor that is used to set transmit currents and
USBRBIAS - - O
internal load resistors. It is recommended that a 22.6 Ω
±1% resistor to ground be connected to this pin.
USB Resistor Bias Complement: Analog connection
point for an external resistor that is used to set transmit
USBRBIAS# - - I
currents and internal load resistors. This signal should be
connected directly to USBRBIAS.
Datasheet 69
Signal Description
2.3 PCI Express*
Table 2-3. PCI Express* Signals (Sheet 1 of 2)
Name Type Description
PCI Express* Differential Transmit Pair 1: These are PCI
Express 2.0-based outbound high-speed differential signals,
and can be mapped to either High Speed I/O (HSIO) Port 5 or
HSIO Port 13.
NOTE: GbE can be mapped to PCIe Port 1 if PCIe Port 1 is
PETp1 selected at HSIO Port 5. GbE cannot be mapped to
O PCIe Port 1 if PCIe Port 1 is selected at HSIO Port 13.
PETn1
See Section 5.4 for details on GbE configuration and
support.
NOTE: Use FITC to set the soft straps that select this port as
muxed with USB 3.0 Port 3 or muxed with SATA Port 4.
FITC does not allow multiplexing PCIe Port 1 with USB
3.0 Port 3 and SATA Port 4 simultaneously, and it is not
a supported configuration.
PCI Express* Differential Receive Pair 1: These are PCI
Express 2.0-based inbound high-speed differential signals, and
can be mapped to HSIO Port 5 or HSIO Port 13.
NOTE: GbE can be mapped to PCIe Port 1 if PCIe Port 1 is
selected at HSIO Port 5. GbE cannot be mapped to
PERp1 PCIe Port 1 if PCIe Port 1 is selected at HSIO Port 13.
I
PERn1 See Section 5.4 for details on GbE configuration and
support.
NOTE: Use FITC to set the soft straps that select this port as
muxed with USB 3.0 Port 3 or muxed with SATA Port 4.
FITC does not allow multiplexing PCIe Port 1 with USB
3.0 Port 3 and SATA Port 4 simultaneously, and it is not
a supported configuration.
PCI Express Differential Transmit Pair 2: These are PCI
Express 2.0-based outbound high-speed differential signals,
and can be mapped to HSIO Port 6 or HSIO Port 14.
NOTE: GbE can be mapped to PCIe Port 2 if PCIe Port 2 is
selected at HSIO Port 6. GbE cannot be mapped to
PETp2 PCIe Port 2 if PCIe Port 2 is selected at HSIO Port 14.
O
PETn2 Please see Section 5.4 for details on GbE configuration
and support.
NOTE: Use FITC to set the soft straps that select this port as
muxed with USB 3.0 Port 4 or muxed with SATA Port 5.
FITC does not allow multiplexing PCIe Port 2 with USB
3.0 Port 4 and SATA Port 5 simultaneously, and it is not
a supported configuration.
70 Datasheet
Signal Description
Table 2-3. PCI Express* Signals (Sheet 2 of 2)
Name Type Description
PCI Express Differential Receive Pair 2: These are PCI
Express 2.0-based inbound high-speed differential signals, and
can be mapped to HSIO Port 6 or HSIO Port 14.
NOTE: GbE can be mapped to PCIe Port 2 if PCIe Port 2 is
selected at HSIO Port 6. GbE cannot be mapped to
PERp2 PCIe Port 2 if PCIe Port 2 is selected at HSIO Port 14.
I
PERn2 See Section 5.4 for details on GbE configuration and
support.
NOTE: Use FITC to set the soft straps that select this port as
muxed with USB 3.0 Port 4 or muxed with SATA Port 5.
FITC does not allow multiplexing PCIe Port 2 with USB
3.0 Port 4 and SATA Port 5 simultaneously, and it is not
a supported configuration.
PETp3 PCI Express Differential Transmit Pair 3: These are PCI
O Express 2.0-based outbound high-speed differential signals,
PETn3
mapped to HSIO Port 7.
PCI Express Differential Receive Pair 3: These are PCI
PERp3
I Express 2.0-based inbound high-speed differential signals,
PERn3 mapped to HSIO Port 7.
PETp4 PCI Express Differential Transmit Pair 4: These are PCI
O Express 2.0-based outbound high-speed differential signals,
PETn4
mapped to HSIO Port 8.
PCI Express* Differential Receive Pair 4: These are PCI
PERp4
I Express 2.0-based outbound high-speed differential signals,
PERn4 mapped to HSIO Port 8.
PCI Express Differential Transmit Pair 5: These are PCI
PETp5
O Express 2.0-based outbound high-speed differential signals,
PETn5
mapped to HSIO Port 9.
PERp5 PCI Express Differential Receive Pair 5: These are PCI
I Express 2.0-based outbound high-speed differential signals,
PERn5
mapped to HSIO Port 9.
PCI Express Differential Transmit Pair 6: These are PCI
PETp6
O Express 2.0-based outbound high-speed differential signals,
PETn6 mapped to HSIO Port 10.
PCI Express Differential Receive Pair 6: These are PCI
PERp6
I Express 2.0-based outbound high-speed differential signals,
PERn6
mapped to HSIO Port 10.
PETp7 PCI Express Differential Transmit Pair 7: These are PCI
O Express 2.0-based outbound high-speed differential signals,
PETn7
mapped to HSIO Port 11.
PCI Express Differential Receive Pair 7: These are PCI
PERp7
I Express 2.0-based outbound high-speed differential signals,
PERn7 mapped to HSIO Port 11.
PCI Express Differential Transmit Pair 8: These are PCI
PETp8
O Express 2.0-based outbound high-speed differential signals,
PETn8
mapped to HSIO Port 12.
PERp8 PCI Express Differential Receive Pair 8: These are PCI
I Express 2.0-based outbound high-speed differential signals,
PERn8
mapped to HSIO Port 12.
Impedance Compensation Input: Connected to a 7.5 K
PCIE_RCOMP I
(1%) precision external pull-up resistor to 1.5 V.
PCIE_IREF I Internal Reference Voltage: Connect directly to 1.5 V.
Datasheet 71
Signal Description
2.4 Serial ATA Interface
Table 2-4. Serial ATA Interface Signals (Sheet 1 of 3)
Name Type Description
Serial ATA Differential Transmit Pair 0: These outbound SATA
SATA_TXp0 Port 0 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and
O
SATA_TXn0 6 Gb/s, and are mapped to HSIO Port 15. In compatible mode,
SATA Port 0 is the primary master of SATA Controller 1.
Serial ATA Differential Receive Pair 0: These inbound SATA Port
SATA_RXp0 0 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and
I
SATA_RXn0 6 Gb/s, and are mapped to HSIO Port 15. In compatible mode,
SATA Port 0 is the primary master of SATA Controller 1.
Serial ATA Differential Transmit Pair 1: These outbound SATA
SATA_TXp1 Port 1 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and
O
SATA_TXn1 6 Gb/s, and are mapped to HSIO Port 16. In compatible mode,
SATA Port 1 is the secondary master of SATA Controller 1.
Serial ATA Differential Receive Pair 1: These inbound SATA Port
SATA_RXp1 1 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and
I
SATA_RXn1 6 Gb/s, and are mapped to HSIO Port 16. In compatible mode,
SATA Port 1 is the secondary master of SATA Controller 1.
Serial ATA Differential Transmit Pair 2: These outbound SATA
SATA_TXp2 Port 2 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and
O
SATA_TXn2 6 Gb/s, and are mapped to HSIO Port 17. In compatible mode,
SATA Port 2 is the primary slave of SATA Controller 1.
Serial ATA Differential Receive Pair 2: These inbound SATA Port
SATA_RXp2 2 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and
I
SATA_RXn2 6 Gb/s, and are mapped to HSIO Port 17. In compatible mode,
SATA Port 2 is the primary slave of SATA Controller 1.
Serial ATA Differential Transmit Pair 3: These outbound SATA
SATA_TXp3 Port 3 high-speed differential signals support 1.5Gb/s, 3Gb/s and
O
SATA_TXn3 6Gb/s, and are mapped to HSIO Port 18. In compatible mode, SATA
Port 3 is the secondary slave of SATA Controller 1.
Serial ATA Differential Receive Pair 3: These inbound SATA Port
SATA_RXp3 3 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and
I
SATA_RXn3 6 Gb/s, and are mapped to HSIO Port 18. In compatible mode,
SATA Port 3 is the secondary slave of SATA Controller 1.
Serial ATA Differential Transmit Pair 4: These outbound SATA
Port 4 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and
6 Gb/s, and are mapped to HSIO Port 13. In compatible mode,
SATA_TXp4
O SATA Port 4 is the primary master of SATA Controller 2.
SATA_TXn4
NOTE: Use FITC to set the soft straps that select this port as PCIe
Port 1. Default configuration is SATA Port 4.
Serial ATA Differential Receive Pair 4: These inbound SATA Port
4 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and
6 Gb/s, and are mapped to HSIO Port 13. In compatible mode,
SATA_RXp4
I SATA Port 4 is the primary master of SATA Controller 2.
SATA_RXn4
NOTE: Use FITC to set the soft straps that select this port as PCIe
Port 1. Default configuration is SATA Port 4.
72 Datasheet
Signal Description
Table 2-4. Serial ATA Interface Signals (Sheet 2 of 3)
Name Type Description
Serial ATA Differential Transmit Pair 5: These outbound SATA
Port 5 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and
6 Gb/s, and are mapped to HSIO Port 14. In compatible mode,
SATA_TXp5
O SATA Port 5 is the secondary master of SATA Controller 2.
SATA_TXn5
NOTE: Use FITC to set the soft straps that select this port as PCIe
Port 2. Default configuration is SATA Port 5.
Serial ATA Differential Receive Pair 5: These inbound SATA Port
5 high-speed differential signals support 1.5 Gb/s, 3 Gb/s and
6 Gb/s, and are mapped to HSIO Port 14. In compatible mode,
SATA_RXp5
I SATA Port 5 is the secondary master of SATA Controller 2.
SATA_RXn5
NOTE: Use FITC to set the soft straps that select this port as PCIe
Port 2. Default configuration is SATA Port 5.
Serial ATA 0 General Purpose: When configured as SATA0GP,
this is an input pin that is used as an interlock switch status
SATA0GP / indicator for SATA Port 0. Drive the pin to ‘0’ to indicate that the
I
GPIO21
switch is closed and to ‘1’ to indicate that the switch is open.
The default use of this pin is GPIO21.
Serial ATA 1 General Purpose: When configured as SATA1GP,
this is an input pin that is used as an interlock switch status
SATA1GP /
I indicator for SATA Port 1. Drive the pin to ‘0’ to indicate that the
GPIO19
switch is closed and to ‘1’ to indicate that the switch is open.
The default use of this pin is GPIO19.
Serial ATA 2 General Purpose: When configured as SATA2GP,
this is an input pin that is used as an interlock switch status
SATA2GP / indicator for SATA Port 2. Drive the pin to ‘0’ to indicate that the
I
GPIO36
switch is closed and to ‘1’ to indicate that the switch is open.
The default use of this pin is GPIO36.
Serial ATA 3 General Purpose: When configured as SATA3GP,
this is an input pin that is used as an interlock switch status
SATA3GP /
I indicator for SATA Port 3. Drive the pin to ‘0’ to indicate that the
GPIO37 switch is closed and to ‘1’ to indicate that the switch is open.
The default use of this pin is GPIO37.
Serial ATA 4 General Purpose: When configured as SATA4GP,
this is an input pin that is used as an interlock switch status
SATA4GP /
I indicator for SATA Port 4. Drive the pin to ‘0’ to indicate that the
GPIO16
switch is closed and to ‘1’ to indicate that the switch is open.
The default use of this pin is GPIO16.
Serial ATA 5 General Purpose: When configured as SATA5GP,
this is an input pin that is used as an interlock switch status
SATA5GP /
I indicator for SATA Port 5. Drive the pin to ‘0’ to indicate that the
GPIO49 switch is closed and to ‘1’ to indicate that the switch is open.
The default use of this pin is GPIO49.
Serial ATA LED: This signal is an open-drain output pin driven
during SATA command activity. It is to be connected to external
SATALED# OD O circuitry that can provide the current to drive a platform LED. When
active, the LED is on. When tri-stated, the LED is off. An external
pull-up resistor to Vcc3_3 is required.
Datasheet 73
Signal Description
Table 2-4. Serial ATA Interface Signals (Sheet 3 of 3)
Name Type Description
SGPIO Reference Clock: The SATA controller uses rising edges of
this clock to transmit serial data, and the target uses the falling
SCLOCK /
OD O edge of this clock to latch data. The SClock frequency supported is
GPIO22
32 kHz.
If SGPIO interface is not used, this signal can be used as GPIO22.
SGPIO Load: The controller drives a ‘1’ at the rising edge of
SCLOCK to indicate either the start or end of a bit stream. A 4-bit
SLOAD /
OD O vendor specific pattern will be transmitted right after the signal
GPIO38 assertion.
If SGPIO interface is not used, this signal can be used as GPIO38.
SDATAOUT0 /
SGPIO Dataout: Driven by the controller to indicate the drive
GPIO39
OD O status in the following sequence: drive 0, 1, 2, 3, 4, 5, 0, 1, 2...
SDATAOUT1 /
If SGPIO interface is not used, the signals can be used as GPIO.
GPIO48
Impedance Compensation Input: Connected to a 7.5 K (1%)
SATA_RCOMP I
precision external pull-up resistor to 1.5 V.
SATA_IREF I Internal Reference Voltage: Connect directly to 1.5 V.
74 Datasheet
Signal Description
2.5 Clock Signals
Table 2-5. Clock Interface Signals (Sheet 1 of 2)
Name Type Description
100 MHz PCIe* 3.0 specification compliant differential
output to processor XDP/ITP connector on platform
CLKOUT_ITPXDP_P
O This Clock can be used for the 3rd PEG slot. Platform Over-
CLKOUT_ITPXDP_N
clocking will not be supported when this clock is used for 3rd
PEG slot.
CLKOUT_DP_P
O 135 MHz differential output for DisplayPort reference
CLKOUT_DP_N
CLKOUT_DPNS_P 135 MHz non-spread differential output for DisplayPort
O
CLKOUT_DPNS_N reference
CLKIN_DMI_P
I Unused. Tie each signal to GND through a 10 K resistor.
CLKIN_DMI_N
CLKOUT_DMI_P 100 MHz PCIe 3.0 specification compliant differential output
O
CLKOUT_DMI_N to processor
CLKIN_SATA_P
I Unused. Tie each signal to GND through a 10 Kresistor.
CLKIN_SATA_N
CLKIN_DOT96_P
I Unused. Tie each signal to GND through a 10 Kresistor.
CLKIN_DOT96_N
XTAL25_IN I Connection for 25 MHz crystal to PCH oscillator circuit
XTAL25_OUT O Connection for 25 MHz crystal to PCH oscillator circuit
REFCLK14IN I Unused. Tie signal to GND through a 10 Kresistor.
CLKOUT_PEG_A_P 100 MHz PCIe 3.0 specification compliant differential output
O
CLKOUT_PEG_A_N to PCI Express* Graphics device
CLKOUT_PEG_B_P 100 MHz PCIe 3.0 specification compliant differential output
O
CLKOUT_PEG_B_N to a second PCI Express* Graphics device
Clock Request Signals for PCIe Graphics slots.
PEG_A_CLKRQ# / Can instead be used as GPIOs
GPIO47,
I NOTE: External pull-up resistor required if used for
PEG_B_CLKRQ# /
CLKREQ# functionality.
GPIO56
NOTE: These pins are not available in desktop packages.
CLKOUT_PCIE_P[7:0] 100 MHz PCIe 2.0 specification compliant differential output
O
CLKOUT_PCIE_N[7:0] to PCI Express devices
CLKIN_GND_P
I Unused. Tie each signal to GND through a 10 Kresistor.
CLKIN_GND_N
PCIECLKRQ0# /
GPIO73,
PCIECLKRQ1# / Clock Request Signals for PCI Express 100 MHz Clocks
GPIO18, Can instead by used as GPIOs
I/O
PCIECLKRQ3# / NOTE: External pull-up resistor required if used for
GPIO25, CLKREQ# functionality.
PCIECLKRQ4# /
GPIO26
Datasheet 75
Signal Description
Table 2-5. Clock Interface Signals (Sheet 2 of 2)
Name Type Description
PCIECLKRQ2# /
GPIO20 / SMI#, Clock Request Signals for PCI Express 100 MHz Clocks
PCIECLKRQ5# / Can instead by used as GPIOs
GPIO44,
I/O
PCIECLKRQ6# / NOTE: External pull-up resistor required if used for
GPIO45, CLKREQ# functionality
PCIECLKRQ7# / NOTE: SMI# is for server/workstation only
GPIO46
Single-Ended, 33 MHz outputs to various connectors/
devices. One of these signals must be connected to
CLKOUT_33MHZ[4:0] O CLKIN_33MHZLOOPBACK to function as a 33MHz clock
loopback. This allows skew control for variable lengths of
CLKOUT_33MHZ[4:0].
33 MHz clock feedBack input, to reduce skew between PCH
CLKIN_33MHZLOOPB
I on-die 33 MHz clock and 33 MHz clock observed by
ACK
connected devices.
Configurable as a GPIO or as a programmable output clock
which can be configured as one of the following:
CLKOUTFLEX01 / • 33 MHz
I/O
GPIO64 • 14.31818 MHz
• 48/24 MHz
• DC Output logic ‘0’
Configurable as a GPIO or as a programmable output clock
which can be configured as one of the following:
CLKOUTFLEX11 / • 33 MHz
I/O
GPIO65 • 14.31818 MHz
• 48/24 MHz
• DC Output logic ‘0’
Configurable as a GPIO or as a programmable output clock
that can be configured as one of the following:
CLKOUTFLEX21 / • 33 MHz
I/O
GPIO66 • 14.31818 MHz
• 48/24 MHz
• DC Output logic ‘0’
Configurable as a GPIO or as a programmable output clock
that can be configured as one of the following:
CLKOUTFLEX31 / • 33 MHz
I/O
GPIO67 • 14.31818 MHz
• 48/24 MHz
• DC Output logic ‘0’
Differential Clock Bias Reference: Connected to an
DIFFCLK_BIASREF I/O
external precision resistor (7.5 KW ±1%) to 1.5 V
Internal Clock Bias Reference: Connect directly to a quiet
ICLK_IREF I/O
1.5 V supply.
NOTE:
1. It is highly recommended to prioritize 14.31818/24/48 MHz clocks on CLKOUTFLEX1 and
CLKOUTFLEX3 outputs. Intel does not recommend configuring the 14.31818/24/48 MHz
clocks on CLKOUTFLEX0 and CLKOUTFLEX2 if more than two 33 MHz clocks in addition to the
feedback clock are used on the CLKOUT_33MHz outputs.
76 Datasheet
Signal Description
2.6 Real Time Clock Interface
Table 2-6. Real Time Clock Interface
Name Type Description
Crystal Input 1: This signal is connected to the 32.768 kHz crystal. If
RTCX1 Special no external crystal is used, then RTCX1 can be driven with the desired
clock rate. Maximum voltage allowed on this pin is 1.2 V.
Crystal Input 2: This signal is connected to the 32.768 kHz crystal. If
RTCX2 Special
no external crystal is used, then RTCX2 must be left floating.
2.7 External RTC Circuitry
The PCH implements an internal oscillator circuit that is sensitive to step voltage
changes in VccRTC. The following figure shows an example schematic recommended to
ensure correct operation of the PCH RTC.
Figure 2-2. Example External RTC Circuit
VccDSW3_3
(see note 3) VCCRTC
Schottky Diodes 1uF 0.1uF
RTCX2
1 K
R1
32.768 KHz 10M
Vbatt 20 K 20 K
Xtal
RTCX1
1.0 uF 1.0 uF C1 C2
RTCRST#
SRTCRST#
NOTES:
1. The Reference Designators used in this example are arbitrarily assigned.
2. The exact capacitor values and tolerances for C1 and C2 must be based on the crystal maker
recommendations.
3. For platforms not supporting DeepSx, the VccDSW3_3 pins must be connected to the
VccSUS3_3 pins.
4. Vbatt is voltage provided by the RTC battery (such as coin cell).
5. VccRTC, RTCX1, RTCX2, RTCRST#, and SRTCRST# are PCH pins.
6. VccRTC powers PCH RTC well.
7. RTCX1 is the input to the internal oscillator.
8. RTCX2 is the amplified feedBack (output) for the external crystal. Important: If a single-
ended clock source, such as an oscillator, is used instead of the crystal to generate the RTC
frequency, you must leave pin RTCX2 floating (no connect).
Datasheet 77
Signal Description
2.8 Interrupt Interface
Table 2-7. Interrupt Signals
Name Type Description
Serial Interrupt Request: This pin implements the serial interrupt
SERIRQ I/OD
protocol.
PCI Interrupt Requests: In non-APIC mode, the PIRQx# signals can
be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or 15 as
described in Section 5.9.6. Each PIRQx# line has a separate Route
Control register.
PIRQ[D:A]# I/OD
In APIC mode, these signals are connected to the internal I/O APIC in
the following fashion: PIRQA# is connected to IRQ16, PIRQB# to
IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the
legacy interrupts.
PCI Interrupt Requests: In non-APIC mode the PIRQx# signals can
be routed to interrupts 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, or 15 as
described in Section 5.9.6. Each PIRQx# line has a separate Route
Control register.
PIRQ[H:E]# /
I/OD In APIC mode, these signals are connected to the internal I/O APIC in
GPIO[5:2]
the following fashion: PIRQE# is connected to IRQ20, PIRQF# to
IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the
legacy interrupts. If not needed for interrupts, these signals can be
used as GPIO.
NOTE: PIRQ Interrupts can only be shared if it is configured as level sensitive. They cannot be
shared if configured as edge triggered.
2.9 Processor Interface
Table 2-8. Processor Interface Signals
Name Type Description
Keyboard Controller Reset Processor: The keyboard controller
can generate INIT# to the processor. This saves the external OR gate
with the PCH’s other sources of INIT#. When the PCH detects the
RCIN# I assertion of this signal, INIT# is generated using a VLW message to
the processor.
NOTE: The PCH will ignore RCIN# assertion during transitions to the
S3, S4, and S5 states.
Processor Power Good: This signal should be connected to the
PROCPWRGD O processor UNCOREPWRGOOD input to indicate when the processor
power is valid.
Power Management Sync: Provides state information from the PCH
PMSYNCH O
to the processor.
PECI I/O Platform Environment Control Interface: Single-wire, serial bus.
Thermal Trip: When low, this signal indicates that a thermal trip
from the processor occurred, and the PCH will immediately transition
THRMTRIP# I
to a S5 state. The PCH will not wait for the processor stop grant cycle
since the processor has overheated.
78 Datasheet
Signal Description
2.10 Direct Media Interface (DMI) to Host Controller
Table 2-9. Direct Media Interface Signals
Name Type Description
DMI_TXP0 Direct Media Interface Differential Transmit Pair 0: This signal is
O
DMI_TXN0 an output from the PCH to the processor.
DMI_RXP0 Direct Media Interface Differential Receive Pair 0: This signal is
I
DMI_RXN0 an input to the PCH from the processor.
DMI_TXP1 Direct Media Interface Differential Transmit Pair 1: This signal is
O
DMI_TXN1 an output from the PCH to the processor.
DMI_RXP1 Direct Media Interface Differential Receive Pair 1: This signal is
I
DMI_RXN1 an input to the PCH from the processor.
DMI_TXP2 Direct Media Interface Differential Transmit Pair 2: This signal is
O
DMI_TXN2 an output from the PCH to the processor.
DMI_RXP2 Direct Media Interface Differential Receive Pair 2: This signal is
I
DMI_RXN2 an input to the PCH from the processor.
DMI_TXP3 Direct Media Interface Differential Transmit Pair 3: This signal is
O
DMI_TXN3 an output from the PCH to the processor.
DMI_RXP3 Direct Media Interface Differential Receive Pair 3: This signal is
I
DMI_RXN3 an input to the PCH from the processor.
Impedance Compensation Input: Connected to a 7.5 K (1%)
DMI_RCOMP I
precision external pull-up resistor to 1.5 V.
DMI_IREF I Internal Reference Voltage: Connect directly to 1.5 V.
2.11 Intel® Flexible Display Interface (Intel® FDI)
Table 2-10. Intel® Flexible Display Interface (Intel® FDI) Signals
Signal Name Type Description
FDI_RXP0
I FDI Display Link Receive Pair 0
FDI_RXN0
FDI_RXP1
I FDI Display Link Receive Pair 1
FDI_RXN1
FDI_CSYNC O FDI Composite synchronization signal
FDI_INT O Used for Display interrupts from PCH to processor.
Impedance Compensation Input: Connected to an external
FDI_RCOMP I
precision resistor (7.5 K ±1%) to 1.5 V
FDI_IREF I Internal Reference Voltage: Connected to 1.5 V
Datasheet 79
Signal Description
2.12 Analog Display / VGA DAC Signals
Table 2-11. Analog Display Interface Signals
Name Type Description
O RED Analog Video Output: This signal is a VGA Analog video
VGA_RED
A output from the internal color palette DAC.
O GREEN Analog Video Output: This signal is a VGA Analog
VGA_GREEN
A video output from the internal color palette DAC.
O BLUE Analog Video Output: This signal is a VGA Analog video
VGA_BLUE
A output from the internal color palette DAC.
I/O Resistor Set: Set point resistor for the internal color palette
DAC_IREF DAC. A 649 resistor is required between DAC_IREF and
A
motherboard ground.
VGA Horizontal Synchronization: This signal is used as the
O
VGA_HSYNC horizontal sync (polarity is programmable) or “sync interval”.
HVCMOS 2.5 V output
O VGA Vertical Synchronization: This signal is used as the
VGA_VSYNC
HVCMOS vertical sync (polarity is programmable). 2.5 V output.
I/O
VGA_DDC_CLK Monitor Control Clock
COD
I/O
VGA_DDC_DATA Monitor Control Data
COD
I/O
VGA_IRTN Monitor Current Return
COD
80 Datasheet
Signal Description
2.13 Digital Display Signals
Table 2-12. Digital Display Signals
Name Type Description
DDPB_AUXP I/O Port B: DisplayPort* Aux
DDPB_AUXN I/O Port B: DisplayPort Aux Complement
DDPB_HPD I Port B: HPD Hot-Plug Detect
DDPB_CTRLCLK I/O Port B: HDMI* Port B Control Clock.
DDPB_CTRLDATA I/O Port B: HDMI Port B Control Data.
DDPC_AUXP I/O Port C: DisplayPort Aux
DDPC_AUXN I/O Port C: DisplayPort Aux Complement
DDPC_HPD I Port C: HPD Hot-Plug Detect
DDPC_CTRLCLK I/O Port C:HDMI Port C Control Clock
DDPC_CTRLDATA I/O Port C:HDMI Port C Control Data
DDPD_AUXP I/O Port D: DisplayPort Aux
DDPD_AUXN I/O Port D: DisplayPort Aux Complement
DDPD_HPD I Port D: Hot-Plug Detect
DDPD_CTRLCLK I/O Port D:HDMI Port D Control Clock
DDPD_CTRLDATA I/O Port D:HDMI Port D Control Data
2.14 Embedded DisplayPort* (eDP*) Backlight Control
Signals
Note: These signals can be left as No Connect (float) if eDP is not used.
Table 2-13. Embedded DisplayPort* (eDP*) backlight control signals
Name Type Description
eDP* Panel power Enable: Panel power control enable.
eDP_VDDEN I/O This signal is also called VDD_dBL in the CPIS specification and
is used to control the VDC source of the panel logic.
eDP Backlight Enable: Panel backlight enable control for eDP.
eDP_BKLTEN I/O This signal is also called ENA_BL in the CPIS specification and is
used to gate power into the backlight circuitry.
eDP Panel Backlight Brightness control: Panel brightness
control for eDP.
eDP_BKLTCTL I/O
This signal also called VARY_BL in the CPIS specification and is
used as the PWM Clock input signal
Datasheet 81
Signal Description
2.15 Intel® High Definition Audio (Intel® HD Audio)
Link
Table 2-14. Intel® High Definition Audio (Intel® HD Audio) Link Signals
Name Type Description
Intel® High Definition Audio Reset: Master hardware reset to
HDA_RST# O
external codec(s).
Intel High Definition Audio Sync: 48 kHz fixed rate sample
HDA_SYNC O sync to the codec(s). This signal is also used to encode the
stream number.
Intel High Definition Audio Bit Clock Output: 24.000 MHz
HDA_BCLK O serial data clock generated by the Intel High Definition Audio
controller (the PCH).
Intel High Definition Audio Serial Data Out: Serial TDM data
output to the codec(s). This serial output is double-pumped for a
bit rate of 48 Mb/s for Intel High Definition Audio.
HDA_SDO O
NOTE: This signal is sampled as a functional strap. See
Section 2.18 for more details. There is a weak integrated
pull-down resistor on this pin.
Intel High Definition Audio Serial Data In [3:0]: Serial TDM
data inputs from the codecs. The serial input is single-pumped
for a bit rate of 24 Mb/s for Intel High Definition Audio. These
signals have integrated pull-down resistors, which are always
HDA_SDI[3:0] I
enabled.
NOTE: During enumeration, the PCH will drive this signal. During
normal operation, the CODEC will drive it.
Intel High Definition Audio Dock Enable: This signal controls
the external Intel HD Audio docking isolation logic. This is an
active low signal. When de-asserted, the external docking switch
is in isolate mode. When asserted, the external docking switch
HDA_DOCK_EN#
O electrically connects the Intel HD Audio dock signals to the
/GPIO33
corresponding PCH signals.
This signal can instead be used as GPIO33. This signal defaults to
GPIO33 mode after PLTRST#. BIOS is responsible for configuring
GPIO33 to HDA_DOCK_EN# mode.
Intel High Definition Audio Dock Reset: This signal is a
dedicated HDA_RST# signal for the codec(s) in the docking
station. Aside from operating independently from the normal
HDA_DOCK_RST# HDA_RST# signal, it otherwise works similarly to the HDA_RST#
O
/ GPIO13 signal.
This signal is shared with GPIO13. This signal defaults to GPIO13
mode after PLTRST#. BIOS is responsible for configuring GPIO13
to HDA_DOCK_RST# mode.
82 Datasheet
Signal Description
2.16 Low Pin Count (LPC) Interface
Table 2-15. Low Pin Count (LPC) Interface Signals
Name Type Description
LPC Multiplexed Command, Address, Data: For LAD[3:0], internal pull-
LAD[3:0] I/O
ups are provided.
LFRAME# O LPC Frame: LFRAME# indicates the start of an LPC cycle, or an abort.
LPC Serial DMA/Master Request Inputs: LDRQ[1:0]# are used to
LDRQ0#, request DMA or bus master access. These signals are typically connected
LDRQ1# / I to an external Super I/O device. An internal pull-up resistor is provided on
GPIO23 these signals.
LDRQ1# may optionally be used as GPIO23.
2.17 General Purpose I/O Signals
The following table summarizes the GPIOs in the PCH. The control for the GPIO signals
is handled through an independent 128-byte I/O space. The base offset for this space is
selected by the GPIO_BAR register in D31:F0 configuration space. See Section 12.10
for details.
Highlights of GPIO Features
a. GPIO pins powered from DSW: If pin is configured as GPIO then it follows the
SUS well (does not follow DSW) and its content is wiped out when SUS is
removed.
b. Only GPIO[31:0] are blink-capable.
c. When the default of a multiplexed GPIO is Native but the desired functionality is
GPIO, care should be taken to ensure the signal is stable until it is initialized to
GPIO functionality.
d. Glitch-less Output means the signal is ensured to be stable (no glitch) during
power on and when switching mode of operation from Native to GPIO or GPIO
to Native. Glitch-less Input means the signal has built-in de-glitch protection
that gates the input signal until power has become stable (the input is ignored
during this time).
e. The following GPIOs are capable of generating SMI#, SCI, or NMI: GPIO[60, 57,
56, 43, 27, 22, 21, 19, 17, 15:0].
f. GPIO_USE_SEL[31:0], GPIO_USE_SEL2[63:32] and GPIO_USE_SEL3[75:64]
select whether the pin is selected to function as GPIO (GPIO_USE_SEL[x] = 1)
or Native (GPIO_USE_SEL[x] = 0). However, the PCH Soft Straps (SPI Flash)
take precedence if there is a mismatch with GPIO_USE_SEL.
g. GP_IO_SEL[31:0], GP_IO_SEL[63:32] and GP_IO_SEL[75:64] select whether
the pin is an output (GP_IO_SEL[x] = 0) or an input (GP_IO_SEL[x] = 1). The
value written to or reported in this register is invalid when the pin is programmed
to Native function.
h. If the corresponding GPIO has been set as an input, and GPI_ROUT has been
programmed for NMI functionality, the GPI_NMI_EN[15:0] is used to allow
active-high or active-low NMI events (depending on the polarity selected by
GPI_INV[31:0]).
i. All the GP_RST_SEL registers are only resetable by RSMRST#. GPIO
Configuration registers within the Core Well are reset whenever PWROK is de-
asserted.
Datasheet 83
Signal Description
j. GPIO Configuration registers within the Suspend Well are reset when RSMRST#
is asserted, CF9h reset (06h or 0Eh), or SYS_RESET# is asserted. However,
CF9h reset and SYS_RESET# events can be masked from resetting the Suspend
well GPIO by programming appropriate GPIO Reset Select (GPIO_RST_SEL)
registers. See Section 12.10 for details.
k. GPIO24 is an exception to the other GPIO Signals in the Suspend Well and is not
reset by CF9h reset (06h or 0Eh)
Table 2-16. General Purpose I/O Signals (Sheet 1 of 6)
Glitch-less
Power Default
Name GPI Event Description
Well (Note 2)
Input Output
GPIO0 Core GPI Yes No No Multiplexed with BMBUSY#.
Desktop and Mobile: Available as GPIO1 only
GPIO1 Core GPI Yes Yes No (Note 4).
Server: Multiplexed with TACH1.
GPIO2
Core GPI Yes No No Multiplexed PIRQE#.
(Note 8)
GPIO3
Core GPI Yes No No Multiplexed PIRQF#.
(Note 8)
GPIO4
Core GPI Yes No No Multiplexed PIRQG#.
(Note 8)
GPIO5
Core GPI Yes No No Multiplexed PIRQH#.
(Note 8)
Desktop and Mobile: Available as GPIO6 only
GPIO6 Core GPI Yes Yes No (Note 4).
Server: Multiplexed with TACH2.
Desktop and Mobile: Available as GPIO7 only
GPIO7 Core GPI Yes Yes No (Note 4).
Server: Multiplexed with TACH3.
GPIO8 Sus GPO Yes No No Unmultiplexed.
Multiplexed with OC5#. When configured as
GPIO9 Sus Native Yes No No
GPIO, default direction is Input (GPI).
Multiplexed with OC6#. When configured as
GPIO10 Sus Native Yes No No
GPIO, default direction is Input (GPI).
Multiplexed with SMBALERT#. When
GPIO11 Sus Native Yes Yes No configured as GPIO, default direction is Input
(GPI).
Multiplexed with LAN_PHY_PWR_CTRL. GPIO /
Native functionality is controlled using soft
DSW
GPIO12 Native Yes No No strap. When configured as GPIO, default
(Note 9)
direction is Output (GPO).
(Note 11)
Sus
Mobile: Multiplexed with HDA_DOCK_RST#.
GPIO13 (Note GPI Yes No No
12)
Desktop: Available as GPIO13 only (Note 4).
Multiplexed with OC7#. When configured as
GPIO14 Sus Native Yes No No
GPIO, default direction is Input (GPI).
GPIO15 Sus GPO Yes No Yes Unmultiplexed.
84 Datasheet
Signal Description
Table 2-16. General Purpose I/O Signals (Sheet 2 of 6)
Glitch-less
Power Default
Name GPI Event Description
Well (Note 2)
Input Output
Multiplexed with SATA4GP.
GPIO16 Core GPI No No No
(Note 11)
Desktop and Mobile: Available as GPIO17 only
GPIO17 Core GPI Yes Yes No (Note 4).
Server: Multiplexed with TACH0.
Multiplexed with PCIECLKRQ1#. External pull
up resistor required for Native function.
GPIO18 Core Native No No No
When configured as GPIO, default direction is
Output (GPO).
GPIO19
Core GPI Yes No No Multiplexed with SATA1GP.
(Note 5)
Multiplexed with PCIECLKRQ2#. External pull
up resistor required for Native function.
GPIO20 Core Native No No No When configured as GPIO, default direction is
Output (GPO).
Server: Also available as SMI# (Note 18).
GPIO21 Core GPI Yes No No Multiplexed with SATA0GP.
GPIO22 Core GPI Yes No No Multiplexed with SCLOCK.
GPIO23 Core Native No No No Multiplexed with LDRQ1#.
GPIO24
Sus GPO No No Yes Unmultiplexed.
(Note 1)
Multiplexed with PCIECLKRQ3#. External pull
up resistor required for Native function.
GPIO25 Sus Native No No No
When configured as GPIO, default direction is
Output (GPO).
Multiplexed with PCIECLKRQ4#. External pull
up resistor required for Native function.
GPIO26 Sus Native No No No
When configured as GPIO, default direction is
Output (GPO).
Datasheet 85
Signal Description
Table 2-16. General Purpose I/O Signals (Sheet 3 of 6)
Glitch-less
Power Default
Name GPI Event Description
Well (Note 2)
Input Output
Unmultiplexed. Can be configured as wake
input to allow wakes from Deep Sx but, since
the pin is shared, the PCH counts on this pin
remaining asserted until PLTRST# de-asserts
or the PCH may latch the pin assertion as a
LAN wake request.
• Intel LAN Present: This pin is connected to
the LANWAKE# pin on the LAN PHY, is
used to signal a ME or host wake to the
DSW
PCH. The pin may also be driven by the
GPIO27 (Note GPI No No No
platform to cause a host wake, but it must
9)
be de-asserted whenever PLTRST# is de-
asserted and may only be used to wake
the host (GPIO27 wake enable must
always be set).
• No Intel LAN Present: This pin does not
have a specific usage model for
connection on the board, but allows the
OEM/ODM customers a custom method to
wake from Deep Sx.
GPIO28 Sus GPO No No Yes Unmultiplexed.
Multiplexed with SLP_WLAN#.
GPIO / Native functionality is controlled using
DSW
GPIO29 Native No No Yes soft strap. When configured as GPIO, default
(Note 9)
direction is Output (GPO).
(Note 11, 15)
Multiplexed with SUSPWRDNACK,
SUSWARN#. SUSPWRDNACK mode is the
default mode of operation. If the system
GPIO30
Sus Native No No Yes supports Deep Sx, then subsequent boots will
(Note 9)
default to SUSWARN# mode. (Note 23)
When configured as GPIO, default direction is
Input (GPI).
NOTES:
1. Toggling this pin at a frequency higher
than 10Hz is not supported.
2. Desktop: GPIO_USE_SEL[31] is
GPIO31 DSW internally hardwired to a 1b, which
GPI No No Yes
(Note 3) (Note 9) means GPIO mode is permanently
selected and cannot be changed.
3. Mobile: This GPIO pin is permanently
appropriated by the ME as MGPIO2 for
ACPRESENT function (not available as
a true GPIO).
Desktop: Available as GPIO32 only (Note 4).
Mobile: GPIO_USE_SEL2[0] is internally
hardwired to a 0b, which means Native mode
GPIO32 Core GPO No No No
is permanently selected and cannot be
changed (not available as GPIO). External pull
up to Core well is required for CLKRUN#.
86 Datasheet
Signal Description
Table 2-16. General Purpose I/O Signals (Sheet 4 of 6)
Glitch-less
Power Default
Name GPI Event Description
Well (Note 2)
Input Output
GPIO33 Desktop: Available as GPIO33 only (Note 4).
Core GPO No No No
(Note 5) Mobile: Also available as HDA_DOCK_EN#.
GPIO34 Core GPI No No No Unmultiplexed.
Desktop & Mobile: Available as GPIO33 only
(Note 4).
GPIO35 Core GPO No No Yes
Server: Also available as NMI#.
(Note 25)
GPIO36
Core GPI No No No Multiplexed with SATA2GP.
(Note 5)
GPIO37
Core GPI No No No Multiplexed with SATA3GP.
(Note 5)
GPIO38 Core GPI No No No Multiplexed with SLOAD.
GPIO39 Core GPI No No No Multiplexed with SDATAOUT0.
Multiplexed with OC1#.
GPIO40 Sus Native No No No When configured as GPIO, default direction is
Input (GPI).
Multiplexed with OC2#.
GPIO41 Sus Native No No No When configured as GPIO, default direction is
Input (GPI).
Multiplexed with OC3#.
GPIO42 Sus Native No No No When configured as GPIO, default direction is
Input (GPI).
Multiplexed with OC4#.
GPIO43 Sus Native Yes No No When configured as GPIO, default direction is
Input (GPI).
Multiplexed with PCIECLKRQ5#. External pull
up resistor required for Native function.
GPIO44 Sus Native No No No
When configured as GPIO, default direction is
Input (GPI).
Multiplexed with PCIECLKRQ6#. External pull
up resistor required for Native function.
GPIO45 Sus Native No No No
When configured as GPIO, default direction is
Input (GPI).
Multiplexed with PCIECLKRQ7#. External pull
up resistor required for Native function.
GPIO46 Sus Native No No No
When configured as GPIO, default direction is
Input (GPI).
Desktop and Server: This pin is not available
GPIO47 Sus Native No No No in the package as GPIO or Native.
Mobile: Multiplexed with PEG_A_CLKRQ#.
GPIO48 Core GPI No No No Multiplexed with SDATAOUT1.
Multiplexed with SATA5GP.
GPIO49 Core GPI No Yes No
(Note 11)
GPIO50 Core GPI No No No Unmultiplexed.
Datasheet 87
Signal Description
Table 2-16. General Purpose I/O Signals (Sheet 5 of 6)
Glitch-less
Power Default
Name GPI Event Description
Well (Note 2)
Input Output
GPIO51
Core GPO No No No Unmultiplexed.
(Note 5)
GPIO52 Core GPI No No No Unmultiplexed.
GPIO53
Core GPO No No No Unmultiplexed.
(Note 5)
GPIO54 Core GPI No No No Unmultiplexed.
GPIO55
Core GPO No No No Unmultiplexed.
(Note 5)
Desktop and Server: This pin is not available
GPIO56 Sus Native Yes No No in the package as GPIO or Native.
Mobile: Multiplexed with PEG_B_CLKRQ#.
Unmultiplexed. Can be re-purposed for NFC
GPIO57 Sus GPI Yes No Yes interface input.
(Note 10)
Multiplexed with SML1CLK.
GPIO58 Sus Native No Yes No When configured as GPIO, default direction is
Input (GPI).
Multiplexed with OC0#.
GPIO59 Sus Native No No No When configured as GPIO, default direction is
Input (GPI).
Multiplexed with SML0ALERT#.
GPIO60 Sus Native Yes Yes No When configured as GPIO, default direction is
Input (GPI).
Multiplexed with SUS_STAT#.
GPIO61 Sus Native No No Yes When configured as GPIO, default direction is
Output (GPO).
Multiplexed with SUSCLK (Note 13).
GPIO62
Sus Native No No No When configured as GPIO, default direction is
(Note 5)
Output (GPO).
Multiplexed with SLP_S5#.
GPIO63 Sus Native No No Yes When configured as GPIO, default direction is
Output (GPO).
Multiplexed with CLKOUTFLEX0.
GPIO64 Core Native No No No When configured as GPIO, default direction is
Output (GPO).
Multiplexed with CLKOUTFLEX1.
GPIO65 Core Native No No No When configured as GPIO, default direction is
Output (GPO).
Multiplexed with CLKOUTFLEX2.
GPIO66 Core Native No No No When configured as GPIO, default direction is
Output (GPO).
Multiplexed with CLKOUTFLEX3.
GPIO67 Core Native No No No When configured as GPIO, default direction is
Output (GPO).
88 Datasheet
Signal Description
Table 2-16. General Purpose I/O Signals (Sheet 6 of 6)
Glitch-less
Power Default
Name GPI Event Description
Well (Note 2)
Input Output
Desktop and Mobile: Available as GPIO68 only
GPIO68 Core GPI No Yes No (Note 4).
Server: Multiplexed with TACH4.
Desktop and Mobile: Available as GPIO69 only
GPIO69 Core GPI No Yes No (Note 4).
Server: Multiplexed with TACH5.
Desktop and Mobile: Available as GPIO70 only
(Note 4).
GPIO70 Core Native No Yes No
Server: Multiplexed with TACH6.
(Note 11)
Desktop and Mobile: Available as GPIO71 only
(Note 4).
GPIO71 Core Native No Yes No
Server: Multiplexed with TACH7.
(Note 11)
Desktop: Available as GPIO72 only (Note 4).
DSW Mobile: Also available as BATLOW#.
GPIO72 Native No No No
(Note 9) Requires external pull-up resistor to DSW
well.
Multiplexed with PCIECLKRQ0#.
External pull up resistor required for Native
GPIO73 Sus Native No No No function.
When configured as GPIO, default direction is
Input (GPI).
Multiplexed with SML1ALERT#/
TEMP_ALERT#.
When configured as GPIO, default direction is
GPIO74 Sus Native No Yes No
Input (GPI). Can be re-purposed for NFC
interface input.
(Note 10, 11, 21)
Multiplexed with SML1DATA.
GPIO75 Sus Native No Yes No When configured as GPIO, default direction is
Input (GPI).
NOTES:
1. GPIO[24] register bits are not cleared by CF9h reset by default, it is programmable through
GP_RST_SEL[24]
2. Internal pull up or pull down may be present when Native functionality is selected. Refer to
Table 3-1 for more details.
3. Internal pull down resistor may be enabled in Deep Sx mode based on DSX_CFG configuration
bit, as follows: ‘1’ (pin will be driven by platform in Deep Sx) -> Z; - ‘0’ (pin will NOT be
driven by platform in Deep Sx) -> Internal pull-down. Refer to DSX_CFG register
(RCBA+3334h) for more details.
4. For pins that are available as GPIO-only: if the power-on default is Native, BIOS is still
required to configure the pin as GPIO by writing to the pin’s GPIO_USE_SEL register, even
though the pin is only available as GPIO.
5. A functional strap also exists on this pin.
6. Glitch-less Inputs are ensured, by circuit design, to de-glitch the input. Glitch-less Outputs
are ensured, by circuit design, to not generate any glitches on the output during power-on.
Datasheet 89
Signal Description
7. The GPIO pins which are capable of generating NMI message when it is configured as input,
its GPI_ROUT register is configured NMI functionality and its corresponding GPI NMI Enable
(GNE) bit is set. NMI event is positive edge trigger based on the signal and after GPI
Inversion logic.
8. When GPIO[5:2] are configured as output GPIOs, they behave in an open drain manner.
9. This SUS well pin will be controlled by DSW logic. GPIO functionality is only available when
the SUS well is powered.
10. GPIO 74 or GPIO 57 can be used for NFC on a platform. The NFC option can be set through
FITC in ME configuration settings.
11. For GPIOs where GPIO vs Native Mode is configured using SPI Soft Strap, the corresponding
GPIO_USE_SEL bits for these GPIOs have no effect. The GPIO_USE_SEL bits for these GPIOs
may change to reflect the Soft-Strap configuration even though GPIO Lockdown Enable (GLE)
bit is set.
12. GPIO13 is located in the HDA Suspend well. It can only be used if VccsusHDA is powered.
13. GPIO62 defaults as Native SUSCLK. If this pin is to be configured as GPIO, it is required that
the board ensure that the 32.768 kHz toggle rate does not affect the receiving logic of the pin
until it is set as GPIO.
14. When switching from GPIO at logic 1 to the native functionality, the pin must not glitch low.
15. A soft strap (PMC_SOFT_STRAP_2 register[7] GP23MGPIO3_SLPWLAN_SEL) to enable
switching between SLP_WLAN# (default) or GP29/MPGIO3. By default the strap is 0b, which
enables the SLP_WLAN# pin function when sus well is up. When soft strap is loaded and
value is 1b, the pin returns to its regular GPIO or MGPIO mode while SLP_WLAN# function no
longer exists. Also take into account of note 11.
16. GPIO72 will default to mobile (native) until determining if this is mobile or desktop/server
SKU.
17. GPIO may toggle until after
18. When strapped as SMI#, the pin is automatically configured as open drain. The SMI#
function is only available in server/workstation SKU. The SMI# function is not the same as
the SMI# events that the GPIOs can be configured to generate, as described in GPI_ROUT
and ALT_GPI_SMI_EN.
19. N/A
20. N/A
21. The choice of which native mode, SML1ALERT# or TEMP_ALERT#, is determined by a soft
strap.
22. N/A
23. SUSPWRDNACK Mode is the default mode of operation. If the system supports DeepSx, then
subsequent boots will default to SUSWARN# mode.
90 Datasheet
Signal Description
2.18 Functional Straps
The PCH implements hardware functional straps that are used to configure specific
functions within the PCH and processor very early in the boot process, before BIOS or
software intervention. Some are sampled at the rising edge of PWROK, while others at
the rising edge of RSMRST# to select configurations (except as noted), and then revert
later to their normal usage. When Descriptor Mode is enabled, the PCH will read Soft
Strap data out of the SPI device prior to the de-assertion of reset to both the Intel
Management Engine and the Host system. In some cases, the soft strap data may
override the hardware functional straps. See Section 5.26.2 for information on
Descriptor Mode.
Table 2-17. Functional Strap Definitions (Sheet 1 of 5)
When
Signal Usage Comment
Sampled
This signal has a weak internal pull-up.
This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS
Destination bit (Chipset Config Registers: Offset
3410h:Bit 10). This strap is used in conjunction with
Boot BIOS Destination Selection 1 strap.
Boot BIOS
Bit11 Bit 10
Destination
0 1 Reserved
1 0 Reserved
1 1 SPI (default)
Boot BIOS Strap 0 0 LPC
SATA1GP / Rising edge of
bit 0
GPIO19 PWROK
(BBS0) NOTES:
1. The internal pull-up is disabled after PLTRST#
de-asserts.
2. If option 00 (LPC) is selected, BIOS may still be
placed on LPC, but the platform is required to
have SPI flash connected directly to the PCH SPI
bus with a valid descriptor in order to boot.
3. Boot BIOS Destination Select to LPC/PCI by
functional strap or using Boot BIOS Destination
Bit will not affect SPI accesses initiated by Intel
ME or Integrated GbE LAN.
4. See Section 10.1.52 for additional information.
5. This signal is in the Core well.
Datasheet 91
Signal Description
Table 2-17. Functional Strap Definitions (Sheet 2 of 5)
When
Signal Usage Comment
Sampled
This signal has a weak internal pull-up.
This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS
Destination bit (Chipset Config Registers: Offset
3410h:Bit 11). This strap is used in conjunction with
Boot BIOS Destination Selection 0 strap.
Boot BIOS
Bit11 Bit 10
Destination
0 1 Reserved
1 0 Reserved
1 1 SPI (default)
Boot BIOS Strap 0 0 LPC
Rising edge of
GPIO51 bit 1
PWROK NOTES:
(BBS1)
1. The internal pull-up is disabled after PLTRST#
de-asserts.
2. If option 00 (LPC) is selected, BIOS may still be
placed on LPC, but the platform is required to
have SPI flash connected directly to the PCH's
SPI bus with a valid descriptor in order to boot.
3. Boot BIOS Destination Select to LPC/PCI by
functional strap or using Boot BIOS Destination
Bit will not affect SPI accesses initiated by Intel
ME or Integrated GbE LAN.
4. See Section 10.1.52 for additional information.
5. This signal is in the Core well.
This signal has a weak internal pull-down.
This signal only takes effect if DMI is configured in AC-
coupled mode (server/workstation only).
0 = DMI RX is terminated to VSS.
1 = DMI RX is terminated to VCC/2.
SATA2GP / DMI RX Rising edge of NOTES:
GPIO36 Termination PWROK 1. The internal pull-down is disabled after PLTRST#
de-asserts.
2. If DMI is operating in DC-coupled mode (such as
Client applications), then DMI RX is terminated
to VSS and the value of this strap is ignored by
the PCH and does not take effect.
3. This signal is in the Core well.
This signal has a weak internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality).
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be
SATA3GP / TLS Rising edge of pulled up to support Intel AMT with TLS and Intel
GPIO37 Confidentiality PWROK SBA (Small Business Advantage) with TLS.
NOTES:
1. The internal pull-down is disabled after PLTRST#
de-asserts.
2. This signal is in the Core well.
92 Datasheet
Signal Description
Table 2-17. Functional Strap Definitions (Sheet 3 of 5)
When
Signal Usage Comment
Sampled
Flash Descriptor This signal has a weak internal pull-down.
Rising edge of
HDA_SDO Security
PWROK
Override
This signal has a weak internal pull-down.
This signal only takes effect if DMI is configured in DC-
coupled mode.
0 = DMI TX is terminated to VSS.
1 = DMI TX is terminated to VCC/2.
HDA_DOCK_EN# / DMI TX Rising edge of
Termination PWROK NOTES:
GPIO33
1. The internal pull-down is disabled after PLTRST#
de-asserts.
2. If DMI is operating in AC-coupled mode, then
DMI TX is terminated to VCC/2 and the value of
this strap does not take effect.
3. This signal is in the Core well.
This signal does not have an internal resistor; an
external resistor is required.
0 = DCPSUS1, DCPSUS2 and DCPSUS3 are powered
from an external power source (should be
connected to an external VRM). External VR
powering option is for Mobile Only; Desktop/Server/
Integrated VRM
INTVRMEN Always Workstation should not pull the strap low.
Enable
1 = Integrated VRMs enabled. DCPSUS1, DCPSUS2 and
DCPSUS3 can be left as No Connect.
NOTES:
1. This signal is always sampled.
2. This signal is in the RTC well.
This signal has a weak internal pull-up.
0 = Disable PLL On-Die voltage regulator.
1 = Enable PLL On-Die voltage regulator.
PLL On-Die
Rising edge of
GPIO62 / SUSCLK Voltage
RSMRST# NOTES:
Regulator Enable
1. The internal pull-up is disabled after RSMRST#
de-asserts.
2. This signal is in the Suspend well.
This signal does not have an internal resistor; an
external resistor is required.
0 = Disable Integrated DeepSx Well (DSW) On-Die
Voltage Regulator. This mode is only supported for
testing environments.
DeepSx Well On- 1 = Enable DSW 3.3 V-to-1.05 V Integrated DeepSx
DSWVRMEN Die Voltage Always
Well (DSW) On-Die Voltage Regulator. This must
Regulator Enable
always be pulled high on production boards.
NOTES:
1. This signal is always sampled.
2. This signal is in the RTC well.
Datasheet 93
Signal Description
Table 2-17. Functional Strap Definitions (Sheet 4 of 5)
When
Signal Usage Comment
Sampled
The signal has a weak internal pull-down.
0 = Disable “No Reboot” mode.
1 = Enable “No Reboot” mode (PCH will disable the TCO
Timer system reboot feature). This function is
useful when running ITP/XDP.
Rising edge of NOTES:
SPKR No Reboot
PWROK 1. The internal pull-down is disabled after PLTRST#
de-asserts.
2. The status of this strap is readable using the NO
REBOOT bit (Chipset Config Registers: RCBA +
Offset 3410h:Bit 5).
3. See Section 10.1.52 for additional information.
4. This signal is in the Core well.
This signal has a weak internal pull-up.
0 = DMI is in AC-coupling mode (server/workstation
only, not meant for desktop/mobile).
1 = DMI is in DC-coupling mode (desktop, mobile or
DMI AC-Coupling
Rising edge of server/workstation).
GPIO53 or DC-Coupling
PWROK
Mode
NOTES:
1. The internal pull-up is disabled after PLTRST#
de-asserts.
2. This signal is in the Core well.
The signal has a weak internal pull-up.
0 = Enable “Top Swap” mode. This inverts an address
on access to SPI and firmware hub, so the processor
believes its fetches the alternate boot block instead
of the original boot-block. PCH will invert A16
(default) for cycles going to the upper two 64 KB
blocks in the FWH or the appropriate address lines
(A16, A17, A18, A19, or A20) as selected in Top-
Swap Block size soft strap (handled through FITc.
Top Swap Rising edge of 1 = Disable “Top Swap” mode.
GPIO55
Override PWROK
NOTES:
1. The internal pull-up is disabled after PLTRST#
de-asserts.
2. Software will not be able to clear the Top Swap
mode bit until the system is rebooted.
3. The status of this strap is readable using the Top
Swap bit (Chipset Config Registers: RCBA +
Offset 3414h:Bit 0).
4. This signal is in the Core well.
This signal has a weak internal pull-down.
0 = Port B is not detected.
1 = Port B is detected.
Rising edge of
DDPB_CTRLDATA Port B Detected
PWROK NOTES:
1. The internal pull-down is disabled after PLTRST#
de-asserts.
2. This signal is in the Core well.
94 Datasheet
Signal Description
Table 2-17. Functional Strap Definitions (Sheet 5 of 5)
When
Signal Usage Comment
Sampled
This signal has a weak internal pull-down.
0 = Port C is not detected.
1 = Port C is detected.
Rising edge of
DDPC_CTRLDATA Port C Detected
PWROK NOTES:
1. The internal pull-down is disabled after PLTRST#
de-asserts.
2. This signal is in the Core well.
This signal has a weak internal pull-down.
0 = Port D is not detected.
1 = Port D is detected.
Rising edge of
DDPD_CTRLDATA Port D Detected
PWROK NOTES:
1. The internal pull-down is disabled after PLTRST#
de-asserts.
2. This signal is in the Core well.
NOTE: See Section 3.1 for full details on pull-up/pull-down resistors.
2.19 SMBus Interface
Table 2-18. SMBus Interface Signals
Name Type Description
SMBDATA I/OD SMBus Data: External pull-up resistor is required.
SMBCLK I/OD SMBus Clock: External pull-up resistor is required.
SMBus Alert: This signal is used to wake the system or generate
SMBALERT# /
I SMI#.
GPIO11
This signal may be used as GPIO11.
2.20 System Management Interface
Table 2-19. System Management Interface Signals (Sheet 1 of 2)
Name Type Description
Intruder Detect: This signal can be set to disable the system if box
INTRUDER# I detected open. This signal status is readable, so it can be used like a
GPI if the Intruder Detection is not needed.
System Management Link 0 Data: SMBus link to external PHY.
SML0DATA I/OD
External pull-up is required.
System Management Link 0 Clock: SMBus link to external PHY.
SML0CLK I/OD
External pull-up is required.
SMLink Alert 0: Output of the integrated LAN controller to external
SML0ALERT# / PHY. External pull-up resistor is required.
O OD
GPIO60
This signal can instead be used as GPIO60.
Datasheet 95
Signal Description
Table 2-19. System Management Interface Signals (Sheet 2 of 2)
Name Type Description
SMLink Alert 1: Alert for the ME SMBus controller to optional
Embedded Controller or BMC. A soft-strap determines the native
SML1ALERT# / function SML1ALERT# or TEMP_ALERT# usage. When soft-strap is 0,
TEMP_ALERT# / O OD
function is SML1ALERT#, when soft-strap is 1, function is
GPIO74
TEMP_ALERT#. This pin can also be set to function as GPIO74.
External pull-up resistor is required on this pin.
System Management Link 1 Clock: SMBus link to optional
SML1CLK / Embedded Controller or BMC. External pull-up resistor is required.
I/OD
GPIO58
This signal can instead be used as GPIO58.
System Management Link 1 Data: SMBus link to optional
SML1DATA /
I/OD Embedded Controller or BMC. External pull-up resistor is required.
GPIO75
This signal can instead be used as GPIO75.
2.21 Controller Link
Table 2-20. Controller Link Signals
Signal Name Type Description
Controller Link Reset: Controller Link reset that connects to a
CL_RST# O Wireless LAN Device supporting Intel Active Management
Technology. This signal is in the Suspend power well.
Controller Link Clock: Bi-directional clock that connects to a
CL_CLK I/O Wireless LAN Device supporting Intel Active Management
Technology. This signal is in the Suspend power well.
Controller Link Data: Bi-directional data that connects to a
CL_DATA I/O Wireless LAN Device supporting Intel Active Management
Technology. This signal is in the Suspend power well.
2.22 Serial Peripheral Interface (SPI)
Table 2-21. Serial Peripheral Interface (SPI) Signals (Sheet 1 of 2)
Name Type Description
SPI Clock: SPI clock signal, during idle the bus owner will drive the
SPI_CLK O clock signal low. Supported frequencies are 20 MHz, 33 MHz and
50 MHz.
SPI Chip Select 0: Used to select the primary SPI Flash device.
SPI_CS0# O NOTE: This signal cannot be used for any other type of device than
SPI Flash.
SPI Chip Select 1: Used to select an optional secondary SPI Flash
device.
SPI_CS1# O
NOTE: SPI_CS0# cannot be used for any other type of device than
SPI Flash.
SPI Chip Select 2: Used to select the TPM device if it is connected to
the SPI interface, it cannot be used for any other type of device than
SPI_CS2# O TPM.
NOTE: TPM can be configured through soft straps to operate over
LPC or SPI, but no more than 1 TPM is allowed in the system.
96 Datasheet
Signal Description
Table 2-21. Serial Peripheral Interface (SPI) Signals (Sheet 2 of 2)
Name Type Description
SPI Master OUT Slave IN: Defaults as a data output pin for PCH in
Dual Output Fast Read mode. Can be configured with a soft strap as a
SPI_MOSI I/O
bidirectional signal (SPI_IO0) to support the new Dual I/O Fast Read,
Quad I/O Fast Read and Quad Output Fast Read modes.
SPI Master IN Slave OUT: Defaults as a data input pin for PCH in
Dual Output Fast Read mode. Can be configured with a soft strap as a
SPI_MISO I/O
bidirectional signal (SPI_IO1) to support the new Dual I/O Fast Read,
Quad I/O Fast Read and Quad Output Fast Read modes.
SPI Data I/O: A bidirectional signal used to support the new Dual
SPI_IO2 I/O I/O Fast Read, Quad I/O Fast Read and Quad Output Fast Read
modes. This signal is not used in Dual Output Fast Read mode.
SPI Data I/O: A bidirectional signal used to support the new Dual
SPI_IO3 I/O I/O Fast Read, Quad I/O Fast Read and Quad Output Fast Read
modes. This signal is not used in Dual Output Fast Read mode.
Datasheet 97
Signal Description
2.23 Manageability Signals
The following signals can be optionally used by the Intel ME supported applications and
appropriately configured by Intel Management Engine Firmware. When configured and
used as a manageability function, the associated host GPIO functionality is no longer
available. If the manageability function is not used in a platform, the signal can be used
as a host General Purpose I/O or a native function.
The manageability signals are referred to as Management Engine GPIO pins (MGPIO
pins), which are GPIO pins that can be controlled through Intel ME FW.
Table 2-22. MGPIO Conversion Table
MGPIO GPIO Well Default Usage
0 24 SUS –
1 30 SUS SUSWARN# or SUSPWRDNACK
2 31 SUS ACPRESENT
3 29 SUS SLP_WLAN#
4 60 SUS SML0ALERT#
Required for NFC (assumes GPIO74 is not
5 57 SUS
setup for NFC)
6 27 DSW Intel ME Wake Input
7 28 SUS –
SML1ALERT#/TEMP_ALERT# or
8 74 SUS Required for NFC (assumes GPIO 57 is not
setup for NFC)
9 16 MAIN SATA4GP#
10 49 MAIN SATA5GP#
11 58 SUS SML1CLK
12 75 SUS SML1DATA
Note: The information in the Default Usage column is not for server platforms. For
information on server manageability signals, see Table 2-24.
Table 2-23. Client Manageability Signals
Power
Name Type Description
Well
Can be configured as a wake input for the Intel ME.
This pin is implemented in the DSW in order to allow
wakes from the DeepSx state. This pin does not
MGPIO6 I/O DSW
have a specific usage model for connection on the
board, but allows the OEM/ODM customers a
custom method to wake from DeepSx.
98 Datasheet
Signal Description
Table 2-24. Server Manageability Signals
Power
Name Type Description
Well
SMBALERT# signal from PSU to PCH. This signal
indicates the PSU may cause a system shutdown due
MGPIO2 I/O SUS
to a momentary loss of AC input voltage or an over-
temperature condition.
MGPIO0,
MGPIO1,
MGPIO2,
MGPIO3, Intel ME Firmware Recovery Mode Strap. These
See
MGPIO4, I/O signals are inputs to the PCH to force Intel ME to stay
Table 2-22
MGPIO5, in recovery boot loader.
MGPIO6,
MGPIO7,
MGPIO8
Note: See Table 2-22 for the MGPIO conversion table.
2.24 Power Management Interface
Table 2-25. Power Management Interface Signals (Sheet 1 of 4)
Name Type Description
ACPRESENT: This input pin indicates when the platform is plugged into AC
power or not. In addition to the previous Intel ME to EC communication, the
PCH uses this information to implement the DeepSx policies. For example,
the platform may be configured to enter DeepSx when in S4 or S5 and only
when running on battery. This is powered by DeepSx Well.
ACPRESENT
I
/ GPIO31 NOTE: This signal is muxed with GPIO31 but GPIO_USE_SEL[31] is
internally hardwired to a 1b, which means GPIO mode is
permanently selected and cannot be changed.
Mobile: This GPIO pin is permanently appropriated by the Intel ME as
MGPIO2 for ACPRESENT function.
Desktop: This pin is only GPIO31, ACPRESENT is not supported.
Active Sleep Well (ASW) Power OK: When asserted, this signal indicates
APWROK I
that power to the ASW sub-system is stable.
Battery Low: This signal is available in Mobile package only. An input from
the battery to indicate that there is insufficient power to boot the system.
Assertion will prevent wake from S3–S5 state. This signal can also be
BATLOW# / enabled to cause an SMI# when asserted. For the Mobile package, this
I
GPIO72 signal is multiplexed with GPIO72. In the Desktop package, this signal is
only available as GPIO72. This signal must be tied high to the VCCDSW3_3,
which will be tied to VccSUS3_3 on DeepSx disabled platforms.
NOTE: See Table 2-16 for Desktop implementation pin requirements.
Bus Master Busy: Generic bus master activity indication driven into the
BMBUSY# PCH. This signal can be configured to set the PM1_STS.BM_STS bit. The
I
/ GPIO0 signal can also be configured to assert indications transmitted from the PCH
to the processor using the PMSYNCH pin.
Datasheet 99
Signal Description
Table 2-25. Power Management Interface Signals (Sheet 2 of 4)
Name Type Description
CLKRUN#
LPC Clock Run: This signal is used to support LPC CLKRUN protocol. It
(Mobile Only) /
I/O connects to peripherals that need to request clock restart or prevention of
GPIO32 (Desktop
clock stopping. Not available in Desktop.
Only)
DPWROK: Power OK Indication for the VccDSW3_3 voltage rail. This input
DPWROK I is tied together with RSMRST# on platforms that do not support DeepSx.
This signal is in the RTC well.
DRAM Power OK: This signal should connect to the processor’s
SM_DRAMPWROK pin. The PCH asserts this pin to indicate when DRAM
DRAMPWROK OD O
power is stable.
This pin requires an external pull-up.
LAN PHY Power Control: LAN_PHY_PWR_CTRL should be connected to
LAN_DISABLE_N on the PHY. PCH will drive LAN_PHY_PWR_CTRL low to put
the PHY into a low power state when functionality is not needed.
LAN_PHY_PWR
O
_CTRL / GPIO12 NOTES:
1. LAN_PHY_PWR_CTRL can only be driven low if SLP_LAN# is de-
asserted.
2. Signal can instead be used as GPIO12.
Platform Reset: The PCH asserts PLTRST# to reset devices on the platform
(such as SIO, FWH, LAN, processor, and so on). The PCH asserts PLTRST#
during power-up and when S/W initiates a hard reset sequence through the
Reset Control register (I/O port CF9h). The PCH drives PLTRST# active a
PLTRST# O
minimum of 1 ms when initiated through the Reset Control register (I/O
port CF9h).
NOTE: PLTRST# is in the VccSUS3_3 well.
Platform Reset Processor: A 1.0 V copy of PLTRST# pin. This signal is the
main host platform reset and should directly connect to the processor pin
PLTRST_PROC# O
PLTRSTIN#. No on-board logic is required to level shift the voltage of this
signal.
Power Button: The Power Button will cause SMI# or SCI to indicate a
system request to go to a sleep state. If the system is already in a sleep
state, this signal will cause a wake event. If PWRBTN# is pressed for more
PWRBTN# I than 4 seconds, this will cause an unconditional transition (power button
override) to the S5 state. Override will occur even if the system is in the
S1–S4 states. This signal has an internal pull-up resistor and has an internal
16 ms de-bounce on the input. This signal is in the DSW well.
Power OK: When asserted, PWROK is an indication to the PCH that all of its
core power rails have been stable for at least 5 ms. PWROK can be driven
asynchronously. When PWROK is negated, the PCH asserts PLTRST#.
NOTES:
PWROK I
1. It is required that the power rails associated with PCI/PCIe (typically
the 3.3 V, 5 V, and 12 V core well rails) have been valid for 99 ms prior
to PWROK assertion in order to comply with the 100 ms PCI 2.3/PCIe*
2.0 specification on PLTRST# de-assertion.
2. PWROK must not glitch, even if RSMRST# is low.
Ring Indicate: This signal is an input from a modem. It can be enabled as
RI# I
a wake event, and this is preserved across power failures.
100 Datasheet
Signal Description
Table 2-25. Power Management Interface Signals (Sheet 3 of 4)
Name Type Description
Resume Well Reset: This signal is used for resetting the resume power
plane logic. This signal must be asserted for at least t201 after the suspend
RSMRST# I
power wells are valid. When de-asserted, this signal is an indication that the
suspend power wells are stable.
SLP_A#: This signal is used to control power to the active sleep well (ASW)
SLP_A# O
of the PCH.
LAN Sub-System Sleep Control: When SLP_LAN# is de-asserted, it
indicates that the PHY device must be powered. When SLP_LAN# is
SLP_LAN# O
asserted, power can be shut off to the PHY device. SLP_LAN# will always be
de-asserted in S0 and anytime SLP_A# is de-asserted.
WLAN Sub-System Sleep Control: When SLP_WLAN# is asserted, power
can be shut off to the external wireless LAN device. SLP_WLAN# will always
will be de-asserted in S0.
SLP_WLAN#/
O NOTE: The selection between native and GPIO mode is based on a soft
GPIO29
strap. The soft strap default is '0', SLP_WLAN# mode. Even though
the pin is in the deep sleep well (DSW), the native and GPIO
functionality is only available when the SUS well is powered. Set soft
strap to ‘1’ to use the GPIO mode.
S3 Sleep Control: SLP_S3# is for power plane control. This signal shuts off
SLP_S3# O power to all non-critical systems when in S3 (Suspend To RAM), S4
(Suspend to Disk), or S5 (Soft Off) states.
S4 Sleep Control: SLP_S4# is for power plane control. This signal shuts
power to all non-critical systems when in the S4 (Suspend to Disk) or S5
(Soft Off) state.
SLP_S4# O
NOTE: This pin must be used to control the DRAM power in order to use the
PCH’s DRAM power-cycling feature.
S5 Sleep Control: SLP_S5# is for power plane control. This signal is used
SLP_S5# / to shut power off to all non-critical systems when in the S5 (Soft Off)
O
GPIO63 states.
This pin may also be used as GPIO63.
DeepSx Indication: When asserted (driven low), this signal indicates the
PCH is in DeepSx state where internal Sus power is shut off for enhanced
power saving. When de-asserted (driven high), this signal indicates exit
SLP_SUS# O
from DeepSx state and Sus power can be applied to PCH. If DeepSx is not
supported, this pin can be left unconnected.
This pin is in the DSW power well.
SUSACK#: If DeepSx is supported, the EC/motherboard controlling logic
must change SUSACK# to match SUSWARN# once the EC/motherboard
controlling logic has completed the preparations discussed in the description
for the SUSWARN# pin.
SUSACK# I
NOTE: SUSACK# is only required to change in response to SUSWARN# if
DeepSx is supported by the platform.
This pin is in the Sus power well.
Datasheet 101
Signal Description
Table 2-25. Power Management Interface Signals (Sheet 4 of 4)
Name Type Description
Suspend Status: This signal is asserted by the PCH to indicate that the
system will be entering a low power state soon. This can be monitored by
SUS_STAT# / devices with memory that need to switch from normal refresh to suspend
O
GPIO61 refresh mode. It can also be used by other peripherals as an indication that
they should isolate their outputs that may be going to powered-off planes.
This pin may also be used as GPIO61.
Suspend Clock: This clock is an output of the RTC generator circuit to use
SUSCLK /GPIO62 O by other chips for refresh clock.
This pin may also be used as GPIO62.
SUSWARN#: This pin asserts low when the PCH is planning to enter the
DeepSx power state and remove Suspend power (using SLP_SUS#). The
EC/motherboard controlling logic must observe edges on this pin, preparing
for SUS well power loss on a falling edge and preparing for SUS well related
activity (host/Intel ME wakes and runtime events) on a rising edge.
SUSACK# must be driven to match SUSWARN# once the above preparation
is complete. SUSACK# should be asserted within a minimal amount of time
SUSWARN# / from SUSWARN# assertion as no wake events are supported if SUSWARN#
SUSPWRDNACK / O is asserted but SUSACK# is not asserted. Platforms supporting DeepSx, but
GPIO30 not wishing to participate in the handshake during wake and DeepSx entry
may tie SUSACK# to SUSWARN#.
This pin may be multiplexed with a GPIO for use in systems that do not
support DeepSx. This pin is multiplexed with SUSPWRDNACK since it is not
needed in DeepSx supported platforms.
Reset type: RSMRST#
This signal is multiplexed with GPIO30 and SUSPWRDNACK.
SUSPWRDNACK: Active high. Asserted by the PCH on behalf of the Intel
SUSPWRDNACK ME when it does not require the PCH Suspend well to be powered.
/ SUSWARN# / O Platforms are not expected to use this signal when the PCH’s DeepSx
GPIO30 feature is used.
This signal is multiplexed with GPIO30 and SUSWARN#.
System Power OK: This generic power good input to the PCH is driven and
utilized in a platform-specific manner. While PWROK always indicates that
SYS_PWROK I the core wells of the PCH are stable, SYS_PWROK is used to inform the PCH
that power is stable to some other system component(s) and the system is
ready to start the exit from reset.
System Reset: This signal forces an internal reset after being debounced.
SYS_RESET# I The PCH will reset immediately if the SMBus is idle; otherwise, it will wait up
to 25 ms ±2 ms for the SMBus to idle before forcing a reset on the system.
PCI Express* Wake Event in Sx: This signal is in DSW and behaves as an
input pin in Sx states. Sideband wake signal on PCI Express asserted by
WAKE# I/OD components requesting wake up.
PCIe OBFF on this pin has been de-featured and is not supported.
102 Datasheet
Signal Description
2.25 Power and Ground Signals
Table 2-26. Power and Ground Signals (Sheet 1 of 2)
Name Description
Decoupling: This signal is for RTC decoupling only. The signal requires
DCPRTC
decoupling.
Decoupling: Internally generated 1.5 V powered from Suspend Well. This
DCPSST signal requires decoupling. Decoupling is required even if this feature is not
used.
1.05 V Suspend well power.
If INTVRMEN is strapped high, power to this well is supplied internally and
this pin should be left as no connect.
DCPSUS1 If INTVRMEN is strapped low, power to this well must be supplied by an
external 1.05 V suspend rail.
NOTE: External VR mode applies to Mobile Only.
1.05 V Suspend well power for USB 2.0.
If INTVRMEN is strapped high, power to this well is supplied internally and
this pin should be left as no connect.
DCPSUS2 If INTVRMEN is strapped low, power to this well must be supplied by an
external 1.05 V suspend rail.
NOTE: External VR mode applies to Mobile Only.
1.05 V Suspend well power for USB 3.0.
If INTVRMEN is strapped high, power to this well is supplied internally and
these pins should be left as no connect.
DCPSUS3 If INTVRMEN is strapped low, power to this well must be supplied by an
external 1.05 V suspend rail.
NOTE: External VR mode applies to Mobile Only.
Decoupling: This signal is for decoupling internally generated 1.05 V
DCPSUSBYP
DeepSx only.
1.05 V supply for core well logic. This power may be shut off in S3, S4, S5,
VCC
or G3 states.
VCC3_3 3.3 V supply for core well I/O buffers.
1.05 V supply for the Active Sleep Well. Provides power to the Intel ME and
VCCASW integrated LAN. This plane must be on in S0 and other times the Intel ME or
integrated LAN is used.
3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well. This
power is not expected to be shut off unless the RTC battery is removed or
completely drained.
VCCRTC
NOTE: Implementations should not attempt to clear CMOS by using a
jumper to pull VccRTC low. Clearing CMOS can be done by using a
jumper on RTCRST# or GPI.
1.05 V supply for I/O buffers. This power may be shut off in S3, S4, S5,
VCCIO
Deep Sx or G3 states.
3.3 V supply for suspend well I/O buffers. This power may be shut off in
VccSUS3_3
DeepSx or G3 state.
VCCSUSHDA Suspend supply for Intel HD Audio. This pin can be either 1.5 or 3.3 V.
Datasheet 103
Signal Description
Table 2-26. Power and Ground Signals (Sheet 2 of 2)
Name Description
1.5 V supply for internal VRMs. This power may be shut off in S3, S4, S5,
VCCVRM
Deep Sx, or G3 states.
1.5 V supply for Display DAC Analog Power. This power may be shut off in
VCCADAC1_5
S3, S4, S5, Deep Sx, or G3 states.
3.3 V supply for Display DAC Band Gap. This power may be shut off in S3,
VCCADACBG3_3
S4, S5, Deep Sx, or G3 states.
VSS Ground.
1.05V Analog power supply for internal clock PLL. This power may be shut
VCCCLK
off in S3, S4, S5, Deep Sx, or G3 states.
3.3 V Analog power supply for internal clock PLL. This power may be shut off
VCCCLK3_3
in S3, S4, S5, Deep Sx, or G3 states.
1.05V supply for processor interface signals. This power may be shut off in
V_PROC_IO S3, S4, S5, Deep Sx, or G3 states. Connect to the same supply as the PCH
VCCIO; do not tie this signal to the processor.
3.3 V supply for DeepSx wells. If the platform does not support Deep Sx,
VCCDSW3_3
then tie to VccSUS3_3.
3.3 V supply for SPI Controller Logic. This rail must be powered when
VccASW is powered.
VCCSPI
NOTE: This rail can be optionally powered on 3.3 V Suspend power
(VccSUS3_3) based on platform needs.
1.05V Analog power supply for USB PLL. This power may be shut off in S3,
VCCUSBPLL
S4, S5, Deep Sx, or G3 states.
2.26 Thermal Signals
Table 2-27. Thermal Signals (Sheet 1 of 2)
Signal Name Type Description
Fan Pulse Width Modulation Outputs: These signals are Pulse
Width Modulated duty cycle output signals used for fan control.
These signals are 3.3 V tolerant.
PWM[3:0] OD O
NOTE: TACH signals used on Server/Workstation Only; not
supported on Mobile and Desktop.
TACH0 / GPIO17
TACH1 / GPIO1 Fan Tachometer Inputs: Tachometer pulse input signal that is
used to measure fan speed. This signal is connected to the “Sense”
TACH2 / GPIO6 signal on the fan.
TACH3 / GPIO7
I The signals can instead be used as a GPIO.
TACH4 / GPIO68
TACH5 / GPIO69 NOTE: TACH signals used on Server/Workstation Only; not
TACH6 / GPIO70 supported on Mobile and Desktop.
TACH7 / GPIO71
104 Datasheet
Signal Description
Table 2-27. Thermal Signals (Sheet 2 of 2)
Signal Name Type Description
Simple Serial Transport: Single-wire, serial bus. Connect this
signal to SST compliant devices such as SST thermal sensors or
voltage sensors.
SST I/O
NOTE: TACH signals used on Server/Workstation Only; not
supported on Mobile & Desktop.
Platform Environment Control Interface: Single-wire, serial
PECI I/O
bus.
Internal Reference Voltage: Thermal sensor low-cap analog
TD_IREF I reference bias current. This should be connected to Vss (ground)
using an external resistor of 8.2 K.
2.27 Miscellaneous Signals
Table 2-28. Miscellaneous Signals (Sheet 1 of 2)
Name Type Description
Internal Voltage Regulator Enable: When pulled high, this signal
enables the internal 1.05 V regulators for the Suspend well in the
PCH. This signal must remain asserted for the VRMs to behave
INTVRMEN I properly (no glitches allowed).
This signal must be pulled-up to VCCRTC on desktop platforms and
may optionally be pulled low on mobile platforms if using an external
VR for the VCCSUS rail.
DeepSx Well Internal Voltage Regulator Enable: This signal
DSWVRMEN I enables the internal DSW 1.05 V regulators and must be always
pulled-up to VCCRTC.
Speaker: The SPKR signal is the output of counter 2 and is internally
“ANDed” with Port 61h Bit 1 to provide Speaker Data Enable. This
signal drives an external speaker driver device, which in turn drives
SPKR O the system speaker. Upon PLTRST#, its output state is 0.
NOTE: SPKR is sampled as a functional strap. There is a weak
integrated pull-down resistor on SPKR pin.
RTC Reset: When asserted, this signal resets register bits in the RTC
well.
NOTES:
RTCRST# I 1. Unless CMOS is being cleared (only to be done in the G3 power
state), the RTCRST# input must always be high when all other
RTC power planes are on.
2. In the case where the RTC battery is dead or missing on the
platform, the RTCRST# pin must rise before the DPWROK pin.
Secondary RTC Reset: This signal resets the manageability register
bits in the RTC well when the RTC battery is removed.
NOTES:
SRTCRST# I
1. The SRTCRST# input must always be high when all other RTC
power planes are on.
2. In the case where the RTC battery is dead or missing on the
platform, the SRTCRST# pin must rise before the RSMRST# pin.
Datasheet 105
Signal Description
Table 2-28. Miscellaneous Signals (Sheet 2 of 2)
Name Type Description
TEMP_ALERT#: This signal is used to indicate a PCH temperature
out of bounds condition to an external EC, when PCH temperature is
greater than value programmed by BIOS. An external pull-up resistor
SML1ALERT#/
is required on this signal.
TEMP_ALERT# OD
/GPIO74
NOTE: A soft-strap determines the native function SML1ALERT# or
TEMP_ALERT# usage. When soft-strap is 0, function is
SML1ALERT#, when soft-strap is 1, function is TEMP_ALERT#.
NMI#: This is an NMI event indication to an external controller (such
GPIO35 / NMI#
as a BMC) on server/workstation platforms.
(Server /
OD O When operating as NMI event indication pin function (enabled when
Workstation
“NMI SMI Event Native GPIO Enable” soft strap [PCHSTRP9:bit 16] is
Only)
set to 1), the pin is OD (open drain).
PCIECLKRQ2# / SMI#: This is an SMI event indication to an external controller (such
GPIO20 / SMI# as a BMC) on server/workstation platforms.
(Server / OD O When operating as SMI event indication pin function (enabled when
Workstation “NMI SMI Event Native GPIO Enable” soft strap [PCHSTRP9:bit 16] is
Only) set to 1), the pin is OD (open drain).
PCI Power Management Event: PCI peripherals drive PME# to
wake the system from low-power states S1–S5. PME# assertion can
also be enabled to generate an SCI from the S0 state. In some cases
the PCH may drive PME# active due to an internal wake event. The
PME# I/OD PCH will not drive PME# high, but it will be pulled up to VccSUS3_3
by an internal pull-up resistor.
PME# is still functional and can be used with PCI legacy mode on
platforms using a PCIe-to-PCI bridge. Downstream PCI devices would
need to have PME# routed from the connector to the PCH PME# pin.
2.28 Testability Signals
Table 2-29. Testability Signals
Name Type Description
Test Clock Input (TCK): The test clock input provides the clock
JTAG_TCK I
for the JTAG test logic.
JTAG_TMS I Test Mode Select (TMS): The signal is decoded by the Test
Access Port (TAP) controller to control test operations.
Test Data Input (TDI): Serial test instructions and data are
JTAG_TDI I
received by the test logic at TDI.
JTAG_TDO OD Test Data Output (TDO): TDO is the serial output for test
instructions and data from the test logic defined in this standard.
NOTE: JTAG Pin definitions are from IEEE Standard Test Access Port and Boundary-Scan
Architecture (IEEE Std. 1149.1-2001)
106 Datasheet
Signal Description
2.29 Reserved / Test Pins
Table 2-30. Test Pins
Name Description
TP1 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP2 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP3 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP4 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP5 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP6 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP7 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP8 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP9 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP10 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP11 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP12 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP13 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
Intel Reserved Pin: Must have a pull-up resistor to VCC3_3. Standard
TP14
resistor value in the range of 4.7 K to 15 K
TP15 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP16 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP17 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP18 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP19 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP20 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP21 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP22 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP23 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP24 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
TP25 Intel Reserved Pin: Leave as No Connect (float, no breakout necessary).
NOTE: The Test Point descriptions provided in this table apply to both Desktop and Mobile
packages.
§§
Datasheet 107
Signal Description
108 Datasheet
PCH Pin States
3 PCH Pin States
3.1 Integrated Pull-Ups and Pull-Downs
Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 1 of 2)
Signal Resistor Type Nominal Notes
USB2p/n[13:0] Pull-down 15K 4
SATA1GP/GPIO19,
SUSCLK/GPIO62, Pull-up 20K 3, 7, 24
GPIO55, GPIO53, GPIO51,
SATA2GP/GPIO36,
SATA3GP/GPIO37,
Pull-down 20K 3, 7
SPKR,
DDP[B:D]_CTRLDATA
HDA_DOCK_EN#,
Pull-down 15K 2, 7, 12, 24
HDA_SDO
SATA4GP/GPIO16,
Pull-up 20K 3, 5
SATA5GP/GPIO49
PCIECLKRQ5#/GPIO44,
PCIECLKRQ7#/GPIO46, Pull-up 20K 3, 11
GPIO8
NMI# Pull-up 20K 3, 6, 24
USB3[T/R] [p/n] [6:1] Pull-down 15K 4
HDA_SDI[3:0],
Pull-down 15K 2, 12
HDA_SYNC
SPI_CLK,
Pull-up 20K 3, 23
SPI_CS[2:0]#
Pull-up or
SPI_MOSI 20K 3, 22
Pull-down
SPI_MISO,
SPI_IO3, Pull-up 20K 3, 8
SPI_IO2
PECI Pull-down 350 17
LAD[3:0],
LDRQ0#, Pull-up 20K 3
LDRQ1#
TACH[7:0] Pull-up 20K 3, 19, 24
SST Pull-down 10K 3, 16, 24
PWRBTN# Pull-up 20K 3
WAKE# Pull-down 20K 3, 9, 19
GPIO31 (ACPRESENT) Pull-down 20K 3, 9
SUSACK# Pull-up 20K 2
Datasheet 109
PCH Pin States
Table 3-1. Integrated Pull-Up and Pull-Down Resistors (Sheet 2 of 2)
Signal Resistor Type Nominal Notes
GPIO27 Pull-down 20K 3, 9, 20
PME# Pull-up 20K 3
Pull-up/Pull-
CL_CLK, CL_DATA 31.25/100 13
down
CLKOUT_33MHZ[4:0],
Pull-down 20K 1, 10
CLKOUTFLEX[3:0]/GPIO[67:64]
SMI# Pull-up 20K 3, 9, 24
JTAG_TDI,
Pull-up 20K 3
JTAG_TMS
JTAG_TCK Pull-down 20K 3
PET/R p/n[8:1],
Pull-up or
USB3T/R p/n[6:1], 50 14
Pull-down
SATA_TX/RX p/n [6:1]
FDI_RX p/n[1:0], Pull-up or
50 14
DMI_TX/RX p/n[3:0] Pull-down
NOTES:
1. Simulation data shows that these resistor values can range from 10 k to 45 k.
2. Simulation data shows that these resistor values can range from 9 k to 50 k.
3. Simulation data shows that these resistor values can range from 15 k to 40 k.
4. Simulation data shows that these resistor values can range from 14.25 k to 24.8 k.
5. GPIO16 has two native functions – the 1st native function (SATAP4_PCIEP1_SELECT) is
selected if the Flex I/O soft strap SATAP4_PCIEP1_MODE = 11b and takes precedence over
any other assignments to this pin (that is, if this is selected, writes to GPIO_USE_SEL are
ignored). If SATAP4_PCIEP1_MODE is not set to 11b, the GPIO_USE_SEL register can be
used to select the 2nd native function (SATA4GP) or GPIO functionality. Setting
SATAP4_PCIEP1_MODE = 11b also enables an internal pull up resistor in this pin to allow
Flexible I/O selection of SATA Port 4 or PCIe Port 1 to be done based on the type of card
installed (If sampled value = 1, select SATA; if sampled value = 0, select PCIe). The same
behavior is true of pin SATA5GP/GPIO49 when the soft strap SATAP5_PCIEP2_MODE =
11b. Soft straps are handled through FITc.
6. When operating as NMI# event indication pin function, the pin is open drain but the PCH
provides an internal pull up to ensure the pin does not float.
7. This signal is a PCH functional strap; the pull-up or pull-down on this signal is disabled
after it is sampled as a PCH functional strap.
8. This signal has a weak internal pull-up that always on.
9. 9When operating as SMI# event indication pin function, the pin is open drain but the PCH
provides an internal pull up to ensure the pin does not float.
10. The pull down is disabled after the pins are driven strongly to logic 0 when PWROK is
asserted.
11. The pull-up or pull-down on this signal is disabled after RSMRST# de-asserts. This pin is
not a functional strap.
12. The internal pull-down on HDA_SYNC and HDA_SDO is enabled during reset.
13. The Controller Link Clock and Data buffers use internal pull-up or pull-down resistors to
drive a logical 1 or 0.
14. Termination resistors may be present if signal is enabled (that is, related Port is not
disabled). These resistors appear to be strong pull downs or pull ups on the signals.
15. Internal pull down resistor may be enabled in Deep Sx mode based on DSX_CFG
configuration bit, as follows: ‘1’ (pin will be driven by platform in Deep Sx) -> Z; - ‘0’ (pin
will NOT be driven by platform in Deep Sx) -> Internal pull-down. Refer to DSX_CFG
register (RCBA+3334h) for more details.
110 Datasheet
PCH Pin States
16. When the interface is in BUS IDLE, the internal pull-down of 10 k is enabled. In normal
transmission, a 400 pull-down takes effect, the signal will be overridden to logic 1 with
pull-up resistor (37 ) to VCC 1.5 V.
17. This is a 350- normal pull-down, signal will be overridden to logic 1 with pull-up resistor
(31 ) to VCC 1.05 V.
18. N/A
19. Regardless of internal pull up or pull down, an external pull up resistor is still required.
20. External pull-up if Intel wired LAN is present (pull up to SUS/DSW based on deepest wake
on LAN support desired).
21. N/A
22. Weak internal pull-up resistor is enabled when APWROK is de-asserted and is switched to a
weak internal pull-down resistor when APWROK and PLTRST# are both asserted.
23. Signals are tri-stated with weak pull-up resistors when APWROK is de-asserted. SPI_CS1#
remains tri-stated with a weak pull-up resistor when APWROK and PLTRST# are both
asserted.
24. Some signals may not be available in all SKUs. Check signal and SKU descriptions.
Datasheet 111
PCH Pin States
3.2 Output Signals Planes and States
Table 3-2 shows the power plane associated with the output and I/O signals, as well as
the state at various times. Within the table, the following terms are used:
“DL” PCH drives low.
“DH” PCH drives high.
“IPU” Internal pull-up.
“IPD” Internal pull-down.
“T” Toggling or signal is transitioning because function not stopping.
“High-Z” Tri-state. PCH not driving the signal high or low.
“Defined” Driven to a level that is defined by the function or external pull-
up/pull-down resistor (will be high or low).
“Off” The power plane is off; PCH is not driving when configured as an
output or sampling when configured as an input.
Note: Pin state within table assumes interfaces are idle and default pin configuration for
different power states.
Signal levels are the same in S3, S4 and S5, except as noted.
In general, PCH suspend well signal states are indeterminate and undefined and may
glitch prior to RSMRST# de-assertion.
PCH core well signal states are indeterminate and undefined and may glitch prior to
PWROK assertion. However, this does not apply to THRMTRIP# as this signal is
determinate and defined prior to PWROK assertion.
DSW indicates PCH Deep Sx Well. This state provides a few wake events and critical
context to allow system to draw minimal power in S3, S4 or S5 states. In general, PCH
DSW signal states are indeterminate, undefined and may glitch prior to DPWROK
assertion. The signals that are determinate and defined prior to DPWROK assertion will
have a note added as a reference.
ASW indicates PCH Active Sleep Well. This power well contains functionality associated
with active usage models while the host system is in Sx.
112 Datasheet
PCH Pin States
Table 3-2. Output Signals - Power Plane and States in Desktop, Mobile and Server
Configurations (Sheet 1 of 4)
Power During Immediately
Signal Name S3/S4/S5 Deep Sx
Plane Reset23 after Reset23
USB Interface
USB2p/n[13:0] Suspend IPD IPD IPD Off
USB3Tp/n[4:3]24, S3 High-Z
Suspend IPD1 IPD1 Off
USB3Tp/n[6:5, 2:1] S4 and S5 Off
PCI Express*
24 Suspend or
PETp/n[2:1] IPD1 IPD1 Off Off
Core5
PETp/n[8:3] Core IPD1 IPD1 Off Off
SATA Interface
SATA_TXp/n[3:0] Core IPU1 IPU1 Off Off
SATA_TXp/n[5:4]24 Core IPU1 IPU1 Off Off
SATALED# Core High-Z High-Z Off Off
SCLOCK Core High-Z High-Z Off Off
SLOAD Core High-Z High-Z Off Off
SDATAOUT[1:0] Core High-Z High-Z Off Off
Clocking Signals
T (platform T (platform
CLKOUT_ITPXDP_P/N Core Off Off
dependent) dependent)
CLKOUT_DP_P/N Core T T Off Off
CLKOUT_DPNS_P/N Core T T Off Off
CLKOUT_DMI_P/N Core T T Off Off
XTAL25_OUT Core High-Z High-Z Off Off
CLKOUT_PEG_A_P/N Core T T Off Off
CLKOUT_PEG_B_P/N Core T T Off Off
CLKOUT_PCIE_P/N[7:0] Core T T Off Off
CLKOUT_33MHZ[4:0] Core T T Off Off
T (platform T (platform
CLKOUTFLEX[3:0] Core Off Off
dependent) dependent)
DIFFCLK_BIASREF Core High-Z High-Z Off Off
ICLK_IREF Core High-Z High-Z Off Off
Interrupt Interface
SERIRQ Core High-Z High-Z Off Off
PIRQ[D:A]# Core High-Z High-Z Off Off
PIRQ[H:E]# Core High-Z High-Z Off Off
NMI#9 Core IPU IPU Off Off
Datasheet 113
PCH Pin States
Table 3-2. Output Signals - Power Plane and States in Desktop, Mobile and Server
Configurations (Sheet 2 of 4)
Power During Immediately
Signal Name S3/S4/S5 Deep Sx
Plane Reset23 after Reset23
Processor Interface
PROCPWRGD Core DL DH Off Off
PMSYNCH Core DL DL Off Off
DMI
DMI_TXp/n[3:0] Core IPU or IPD1, 21 IPU or IPD1, 21 Off Off
Intel® Flexible Display Interface (Intel® FDI)
FDI_CSYNC Core High-Z2 High-Z2 Off Off
2 High-Z2
FDI_INT Core High-Z Off Off
Analog Display / VGA DAC Signals
VGA_RED, VGA_GREEN,
Core High-Z High-Z Off Off
VGA_BLUE
DAC_IREF Core High-Z DL Off Off
VGA_HSYNC Core DL DL Off Off
VGA_VSYNC Core DL DL Off Off
VGA_DDC_CLK Core High-Z High-Z Off Off
VGA_DDC_DATA Core High-Z High-Z Off Off
VGA_IRTN Core High-Z High-Z Off Off
Digital Display Interface
DDP[D:B]_AUXP/N Core IPD IPD Off Off
DDPB_CTRLCLK,
DDPC_CTRLCLK, Core High-Z High-Z Off Off
DDPD_CTRLCLK
DDPB_CTRLDATA,
DDPC_CTRLDATA, Core IPD3 High-Z Off Off
DDPD_CTRLDATA
eDP_VDD_EN Core DL DL Off Off
eDP_BKLTEN Core DL DL Off Off
eDP_BKLTCTL Core DL DL Off Off
Intel® High Definition Audio Interface (Intel® HD Audio)
HDA_RST#4,
Suspend DL DL DL Off
HDA_BCLK4
HDA_SYNC26,
Suspend IPD IPD IPD Off
HDA_SDO26
HDA_DOCK_EN#10 Core IPD IPD Off Off
HDA_DOCK_RST#10 Suspend25 High-Z High-Z8 High-Z8 Off
114 Datasheet
PCH Pin States
Table 3-2. Output Signals - Power Plane and States in Desktop, Mobile and Server
Configurations (Sheet 3 of 4)
Power During Immediately
Signal Name S3/S4/S5 Deep Sx
Plane Reset23 after Reset23
LPC Interface
LAD[3:0] Core IPU IPU Off Off
LFRAME# Core DH DH Off Off
Non-Multiplexed GPIO Signals
GPIO85 Suspend IPU DH DH Off
5, 9
GPIO15 Suspend DL DL DL Off
9
GPIO24 Suspend DL DL DL Off
9
GPIO28 Suspend DL DL DL Off
DL (Mobile); DL (Mobile);
CLKRUN# Core Off Off
DH (Desktop) DH (Desktop)
GPIO[53, 51] Core IPU DH Off Off
GPIO55 Core IPU DL DL Off
SMBus Interface
SMBCLK, SMBDATA Suspend High-Z High-Z High-Z Off
System Management Interface
SML0DATA Suspend High-Z High-Z High-Z Off
SML0CLK Suspend High-Z High-Z High-Z Off
SML0ALERT# Suspend High-Z High-Z7 High-Z Off
SML1ALERT# Suspend High-Z High-Z High-Z Off
SML1CLK Suspend High-Z High-Z High-Z Off
SML1DATA Suspend High-Z High-Z High-Z Off
Controller Link
CL_RST#11 Suspend DL DH DH Off
11 Terminated12 Terminated12
CL_CLK Suspend IPD Off
11 12 12
CL_DATA Suspend Terminated Terminated IPD Off
SPI Interface
SPI_CLK ASW DL DL DL Off
SPI_CS0# ASW DH DH DH Off
SPI_CS1# ASW IPU DH DH Off
SPI_CS2# ASW DH DH DH Off
SPI_MOSI ASW IPD DL DL Off
SPI_MISO ASW IPU IPU IPU Off
SPI_IO2 ASW IPU IPU IPU Off
SPI_IO3 ASW IPU IPU IPU Off
Datasheet 115
PCH Pin States
Table 3-2. Output Signals - Power Plane and States in Desktop, Mobile and Server
Configurations (Sheet 4 of 4)
Power During Immediately
Signal Name S3/S4/S5 Deep Sx
Plane Reset23 after Reset23
Power Management
S3 High-Z,
DRAMPWROK9 Suspend DL High-Z Off
S4 and S5 DL
LAN_PHY_PWR_CTRL DSW DL DL DL DL
PLTRST# Suspend DL DH DL Off
PLTRST_PROC# Core DL DH DL Off
SLP_A#9, 11 DSW DL DH DH DL
SLP_LAN#9 DSW DL DL DL/DH16 DL/DH16
SLP_WLAN#9 DSW DL DL DL/DH16 DL/DH16
SLP_S3#9 DSW DL DH DL DL
S3 DH,
SLP_S4#9 DSW DL DH DL/DH17
S4 and S5 DL
S3 and S4 DH,
SLP_S5#9 Suspend DL DH DL
S5 DL
SLP_SUS#9 DSW DL DH DH DL
SUS_STAT# Suspend DL DH18 DL Off
SUSCLK Suspend IPU T Off
SUSWARN#/
Suspend DL DL DL OFF22
SUSPWRDNACK9, 19
Thermal Signals
PWM[3:0] Core DL DL Off Off
20 20 20
SST Suspend DL DL DL Off
PECI Core DL DL Off Off
Miscellaneous Signals
SPKR5 Core IPD DL Off Off
TEMP_ALERT# Suspend High-Z High-Z High-Z Off
JTAG_TDO Suspend High-Z High-Z High-Z Off
NOTES:
1. This is a strong pull down (or pull up, as applicable).
2. If the port is disabled, signal is tri-stated.
3. External 2.2 K Pull-Up when used.
4. The internal pull-down on HDA_BCLK and HDA_RST# are enabled when PWROK is de-
asserted. When GCTL.CRST# bit is set, the HDA_BCLK pin will start to toggle.
5. The power well depends on whether the PCIe port is being multiplexed with USB3
(suspend) or with SATA (core).
6. N/A.
7. N/A.
8. This pin will be driven High when Dock Attach bit is set (Docking Control Register D27:F0
Offset 4Ch).
9. The pin output shall not glitch during power up sequence.
10. Native functionality multiplexed with these GPIOs are not used in Desktop configurations.
116 Datasheet
PCH Pin States
11. The state of signals in S3-S5 will be defined by Intel ME Policies.
12. The terminated state is when the I/O buffer pull down is enabled.
13. N/A.
14. N/A.
15. N/A.
16. Pin may toggle between RSMRST# de-assertion to PLTRST# de-assertion, based on ME
firmware configuration. Sx and DSx behavior is based on wake events and ME state/policy.
17. When the platform enters DeepSx, the pin will retain the value it held prior to DeepSx
entry.
18. Driven High after PWROK rises.
19. Based on wake events and ME state. SUSPWRDNACK is always ‘0’ while in M0 or M3, but
can be driven to 0 or 1 during the Moff state. SUSPWRDNACK is the default mode of
operation. If the system supports DeepSx, then subsequent boots will default to
SUSWARN# mode.
20. When Interface is in BUS IDLE, internal pull-down of 10k ohms is enabled. In normal
transmission, a 400 ohm pull-down takes effect, the signal will be overridden to logic 1
with pull-up resistor (37 ohms) to 1.5 V.
21. Depending on the platform usage, if termination is set to VSS then the signal is low. If it is
terminated to VCC, the default value will be high. For AC coupling mode, DMI_TX* pins are
terminated to VCC/2 and DMI_RX* pins are terminated to VSS. DMI AC coupling mode is
only supported in Server/Workstation SKUs.
22. OFF if DeepSx supported else not available (SUSPWRDNACK: Non-DeepSx OR DeepSx
after RTC power failure) / Off (SUSWARN: DeepSx).
23. The states of signals on Core and processor power planes are evaluated at the times
during PLTRST# and immediately after PLTRST#. The states of the Controller Link signals
are taken at the times during CL_RST# and Immediately after CL_RST#. The states of the
Suspend signals are evaluated at the times during RSMRST# and Immediately after
RSMRST#, with an exception to GPIO signals; refer to Section 2.17 for more details on
GPIO state after reset. The states of the HDA signals are evaluated at the times During
HDA_RST# and Immediately after HDA_RST#.
24. Flexible I/O ports follow the properties of the selected technology.
25. GPIO13 is located in the HDA Suspend well. It can only be used if VccsusHDA is powered.
26. The internal pull-down on HDA_SYNC and HDA_SDO is enabled after reset.
Datasheet 117
PCH Pin States
3.3 Input and I/O Signals Planes and States
Table 3-3 shows the power plane associated with the input and I/O signals, as well as
the state at various times. Within the table, the following terms are used:
“IPU” Internal pull-up.
“IPD” Internal pull-down.
“T” Toggling or signal is transitioning because function not stopping.
“High-Z” Tri-state. PCH not driving the signal high or low.
“Defined” Driven to a level that is defined by the function or external pull-
up/pull-down resistor (will be high or low).
“Off” The power plane is off; PCH is not driving when configured as an
output or sampling when configured as an input.
Note: Pin state within table assumes interfaces are idle and default pin configuration for
different power states.
Signal levels are the same in S3, S4, and S5, except as noted.
In general, PCH suspend well signal states are indeterminate and undefined and may
glitch prior to RSMRST# de-assertion.
PCH core well signal states are indeterminate and undefined and may glitch prior to
PWROK assertion. However, this does not apply to THRMTRIP# as this signal is
determinate and defined prior to PWROK assertion.
DSW indicates PCH Deep Sx Well. This state provides a few wake events and critical
context to allow system to draw minimal power in S3, S4, or S5 states. In general, PCH
DSW signal states are indeterminate, undefined and may glitch prior to DPWROK
assertion. The signals that are determinate and defined prior to DPWROK assertion will
have a note added as a reference.
ASW indicates PCH Active Sleep Well. This power well contains functionality associated
with active usage models while the host system is in Sx.
118 Datasheet
PCH Pin States
Table 3-3. Input Signals - Power Plane and States in Desktop and Mobile Configurations
(Sheet 1 of 4)
Power Immediately
Signal Name During Reset S3/S4/S5 Deep Sx
Plane after Reset
USB Interface
USB2p/n[13:0] Suspend IPD IPD IPD Off
USB3Rp/n[4:3]17, S3 IPD1, 2
Suspend IPD1, 2 IPD1, 2 Off
USB3Rp/n[6:5, 2:1] S4 and S5 Off
OC0#3, OC1#3, OC2#3,
OC3#3, OC4#3, OC5#3, Suspend High-Z High-Z High-Z Off
OC6#3, OC7#3
PCI Express*
Suspend or
PERp/n[2:1]17 IPD4 IPD4 Off Off
Core6
PERp/n[8:3] Core IPD4 IPD4 Off Off
SATA Interface
SATA_RXp/n[3:0] Core IPD2 IPD2 Off Off
17
SATA_RXp/n[5:4] Core IPD2 IPD2 Off Off
SATA0GP, SATA4GP,
Core High-Z High-Z Off Off
SATA5G
SATA1GP Core IPU High-Z Off Off
SATA2GP, SATA3GP Core IPD High-Z Off Off
Clocking Signals
XTAL25_IN Core High-Z High-Z Off Off
PEG_A_CLKRQ#,
PEG_B_CLKRQ#,
PCIECLKRQ0#,
PCIECLKRQ3#,
Suspend High-Z High-Z High-Z Off
PCIECLKRQ4#,
PCIECLKRQ5#,
PCIECLKRQ6#,
PCIECLKRQ7#
PCIECLKRQ1#,
Core High-Z High-Z Off Off
PCIECLKRQ2#
CLKIN_33MHZLOOPBACK Core High-Z High-Z Off Off
DIFFCLK_BIASREF Core High-Z High-Z Off Off
ICLK_IREF Core High-Z High-Z Off Off
Processor Interface
RCIN# Core High-Z High-Z Off Off
THRMTRIP# Core High-Z High-Z Off Off
Interrupt Interface
SERIRQ Core High-Z High-Z Off Off
Datasheet 119
PCH Pin States
Table 3-3. Input Signals - Power Plane and States in Desktop and Mobile Configurations
(Sheet 2 of 4)
Power Immediately
Signal Name During Reset S3/S4/S5 Deep Sx
Plane after Reset
PIRQ[D:A]# Core High-Z High-Z Off Off
PIRQ[H:E]# Core High-Z High-Z Off Off
DMI
DMI_RXp/n[3:0] Core IPD2, 18 IPD2, 18 Off Off
Intel® Flexible Display Interface (Intel® FDI)
2
FDI_RXP/N[1:0] Core High-Z IPD Off Off
Analog Display / VGA DAC Signals
DAC_IREF Core High-Z DL Off Off
VGA_DDC_CLK Core High-Z High-Z Off Off
VGA_DDC_DATA Core High-Z High-Z Off Off
VGA_IRTN Core High-Z High-Z Off Off
Digital Display Interface
DDPB_AUXP/N,
DDPC_AUXP/N, Core IPD IPD Off Off
DDPD_AUXP/N
DDPB_CTRLCLK,
DDPC_CTRLCLK, Core High-Z High-Z Off Off
DDPD_CTRLCLK
DDPB_CTRLDATA,
DDPC_CTRLDATA, Core IPD5 High-Z Off Off
DDPD_CTRLDATA
DDPB_HPD,
DDPC_HPD, Core High-Z High-Z Off Off
DDPD_HPD
eDP_VDD_EN Core DL DL Off Off
eDP_BKLTEN Core DL DL Off Off
eDP_BKLTCTL Core DL DL Off Off
® ®
Intel High Definition Audio Interface (Intel HD Audio)
HDA_SDI[3:0] Suspend IPD IPD IPD Off
LPC Interface
LAD[3:0] Core IPU IPU Off Off
LDRQ0#
Core IPU IPU Off Off
LDRQ1#
Non-Multiplexed GPIO Signals
GPIO8 Suspend IPU DH DH Off
GPIO15 Suspend DL DL DL Off
GPIO24 Suspend DL DL DL Off
120 Datasheet
PCH Pin States
Table 3-3. Input Signals - Power Plane and States in Desktop and Mobile Configurations
(Sheet 3 of 4)
Power Immediately
Signal Name During Reset S3/S4/S5 Deep Sx
Plane after Reset
High-Z /
GPIO27 DSW High-Z High-Z High-Z
IPD8
GPIO28 Suspend DL DL DL Off
GPIO34 Core High-Z High-Z Off Off
GPIO50 Core High-Z High-Z Off Off
GPIO51 Core IPU DH Off Off
GPIO52 Core High-Z High-Z Off Off
GPIO53 Core IPU DH Off Off
GPIO54 Core High-Z High-Z Off Off
GPIO55 Core IPU DL DL Off
GPIO57 Suspend DL High-Z High-Z Off
SMBus Interface
SMBCLK, SMBDATA Suspend High-Z High-Z High-Z Off
SMBALERT# Suspend High-Z High-Z High-Z Off
System Management Interface
INTRUDER# RTC High-Z High-Z High-Z High-Z
SML0DATA Suspend High-Z High-Z High-Z Off
SML0CLK Suspend High-Z High-Z High-Z Off
SML1CLK Suspend High-Z High-Z High-Z Off
SML1DATA Suspend High-Z High-Z High-Z Off
Controller Link
CL_CLK9 Suspend Terminated10 Terminated10 IPD Off
9 Terminated10 Terminated10
CL_DATA Suspend IPD Off
SPI Interface
SPI_MOSI ASW IPD DL DL Off
SPI_MISO ASW IPU IPU IPU Off
SPI_IO2 ASW IPU IPU IPU Off
SPI_IO3 ASW IPU IPU IPU Off
Datasheet 121
PCH Pin States
Table 3-3. Input Signals - Power Plane and States in Desktop and Mobile Configurations
(Sheet 4 of 4)
Power Immediately
Signal Name During Reset S3/S4/S5 Deep Sx
Plane after Reset
Power Management
DL (Non-DSx
13 mode) IPD / High-
ACPRESENT DSW High-Z High-Z
High-Z (DSx Z8
mode)
APWROK Suspend High-Z High-Z High-Z Off
BATLOW# DSW IPU IPU IPU IPU/IP8
BMBUSY# Core High-Z High-Z Off Off
DPWROK RTC High-Z High-Z High-Z High-Z
PWRBTN# DSW IPU IPU IPU IPU
PWROK RTC High-Z High-Z High-Z High-Z
RI# Suspend High-Z High-Z High-Z Off
RSMRST# RTC High-Z High-Z High-Z High-Z
SUSACK# Suspend IPU IPU IPU Off
SYS_PWROK Suspend High-Z High-Z High-Z Off
SYS_RESET# Core High-Z High-Z Off Off
High-Z /
WAKE# DSW High-Z High-Z High-Z
IPD8
Thermal Signals
TACH0, TACH1, TACH2,
TACH3, TACH4, TACH5, Core IPU (TACH) IPU(TACH) Off Off
TACH6, TACH7
SST Suspend DL15 DL15 DL15 Off
16
PECI Core DL DL16 Off Off
TD_IREF Core Analog Analog Off Off
Miscellaneous Signals
INTVRMEN RTC High-Z High-Z High-Z High-Z
DSWVRMEN RTC High-Z High-Z High-Z High-Z
RTCRST# RTC High-Z High-Z High-Z High-Z
SRTCRST# RTC High-Z High-Z High-Z High-Z
PME# Suspend IPU IPU IPU Off
JTAG_TCK Suspend IPD IPD IPD Off
JTAG_TMS Suspend IPU IPU IPU Off
JTAG_TDI Suspend IPU IPU IPU Off
NOTE:
1. USB3 Rx pins transition from High-Z to IPD after Reset.
2. This is a strong pull down (or pull up, as applicable).
3. Signals must be shared between ports. There are only 8 OC# signals and 14 USB ports.
4. PCIe Rx pins transition from High-Z to IPD after Reset.
122 Datasheet
PCH Pin States
5. External 2.2 K Pull-Up when used - strap sampled during reset only.
6. The power well depends on whether the PCIe port is being multiplexed with USB3
(suspend) or with SATA (core).
7. This pin will be driven High when Dock Attach bit is set (Docking Control Register D27:F0
Offset 4Ch).
8. Pull-down is configurable; refer to DSX_CFG register (RCBA+3334h) for more details.
9. The state of signals in S3-S5 will be defined by Intel ME Policies.
10. The terminated state is when the I/O buffer pull down is enabled.
11. N/A.
12. N/A.
13. The pin output shall not glitch during power up sequence.
14. Pin defaults to Native function upon power up. A USB3Px_PCIEPx_ MODE soft strap
determines if the native mode is USB3P* select or TACH native function. If the
USB3Px_PCIEPx_ MODE soft strap is "11b" then the pin native function is USB3P*, else it
is TACH. The USB3P*# pins shall not glitch or drive (that is, momentarily change to
output) during any of the GPIO and/or native function mode transition. If the
USB3Px_PCIEPx_ MODE soft strap is not set to "11b", then it is the requirement of the
USB3 controller, to ignore the USB3P*# pin.
15. When interface is in BUS IDLE status, internal pull-down of 10k ohms is enabled. In normal
transmission, a 400 ohms pull-down takes effect, the signal will be overridden to logic 1
with pull-up resistor (37 ohms) to 1.5 V.
16. This is a 350 ohm normal pull-down, the signal will be overridden to logic 1 with pull-up
resistor (31 ohms) to 1.05 V.
17. The Flexible I/O ports follow the properties of the selected technology.
18. Depending on the platform usage, if termination is set to VSS then the signal is low. If it is
terminated to VCC, the default value will be high. For AC coupling mode, DMI_TX* pins are
terminated to VCC/2 and DMI_RX* pins are terminated to VSS. DMI AC coupling mode is
only supported in Server/Workstation SKUs. Desktop and Mobile SKUs only support DC
coupled mode, where the RX signals are terminated to VSS.
§§
Datasheet 123
PCH Pin States
124 Datasheet
PCH and System Clocks
4 PCH and System Clocks
The PCH provides a complete system clocking solution through Integrated Clocking.
PCH-based platforms require several single-ended and differential clocks to synchronize
signal operation and data propagation between system-wide interfaces, and across
clock domains. In Integrated Clock mode, all the system clocks will be provided by PCH
from a 25 MHz crystal-generated clock input.
The output signals from PCH are:
• One 100 MHz differential source for BCLK and DMI (PCI Express* 3.0 jitter tolerant)
• Two 135 MHz differential sources for DisplayPort* on Integrated Graphics
processors
• Eight 100 MHz differential sources for PCI Express 2.0 devices
• Two 100 MHz differential source for PCI Express Graphics devices (PCI Express 3.0
jitter tolerant)
• One 100 MHz differential clock for XDP/ITP which can be used as a clock to a 3rd
PEG slot (PCI Express 3.0 jitter tolerant)
• Five 33 MHz single-ended source for other devices (One of these is reserved as
loopback clock)
• Four flexible single-ended outputs that can be used for 14.31818/24/33/48 MHz for
legacy platform functions, discrete graphics devices, external USB controllers, and
so on.
4.1 Straps Related to Clock Configuration
Hardware functional straps (that is, pins): None required for clock configuration.
Soft straps implemented in the SPI flash device for PCH clock configuration: Integrated
Clocking Profile Select (3 Profile select bits allow up to 8 different clock profiles to be
specified). In addition, 3 RTC well backed host register bits are also defined for
Integrated Clocking Profile Selection through BIOS.
Datasheet 125
PCH and System Clocks
4.2 Platform Clocking Requirements
Providing a platform-level clocking solution uses multiple system components
including:
• The PCH
• 25 MHz crystal source
More detail on the clock interface signals is provided in Section 2.5 but a summary is
given in the following tables; Table 4-1 shows the system clock input to PCH. Table 4-2
shows system clock outputs generated by PCH.
Table 4-1. PCH Clock Inputs
Clock Domain Frequency Usage description
CLKIN_DMI_P/N 100 MHz Unused. Tie each signal to GND through a 10 Kresistor.
CLKIN_DOT96_P/N 96 MHz Unused. Tie each signal to GND through a 10 Kresistor.
CLKIN_SATA_P/N 100 MHz Unused. Tie each signal to GND through a 10 Kresistor.
CLKIN_GND_P/N 100 MHz Unused. Tie each signal to GND through a 10 Kresistor.
33 MHz clock feedBack input to reduce skew between
CLKIN_33MHZLOO PCH 33MHz clocks and buses such as LPC. This signal
33 MHz
PBACK must be connected to one of the pins in the group
CLKOUT_33MHz[4:0]
REFCLK14IN 14.31818 MHz Unused. Tie signal to GND through a 10 Kresistor.
XTAL25_IN 25 MHz Crystal input source used by PCH.
Table 4-2. Clock Outputs (Sheet 1 of 2)
Spread
Clock Domain Frequency Usage
Spectrum
Single Ended 33 MHz outputs. One of
these signals must be connected to
CLKIN_33MHZLOOPBACK to
CLKOUT_33MHz[4:0] 33 MHz Yes
function as a clock loopback. This
allows skew control for variable
lengths of CLKOUT_33MHz[4:0].
100 MHz PCIe* 3.0 specification
CLKOUT_DMI_P/N 100 MHz Yes compliant differential output to the
processor for DMI/BCLK.
100 MHz PCIe 2.0 specification
CLKOUT_PCIE[7:0]_P/N 100 MHz Yes compliant differential output to PCI
Express devices.
CLKOUT_PEG_A_P/N 100 MHz PCIe 3.0 specification
100 MHz Yes compliant differential outputs to PCI
CLKOUT_PEG_B_P/N Express Graphics devices.
Primarily used as 100 MHz Clock to
processor XDP/ITP on the platform or
CLKOUT_ITPXDP_P/N 100 MHz Yes
can be configured as
CLKOUT_PEG_C_P/N.
135 MHz Differential SSC capable
CLKOUT_DP_P/N 135 MHz Yes
outputs to processor for DisplayPort.
126 Datasheet
PCH and System Clocks
Table 4-2. Clock Outputs (Sheet 2 of 2)
Spread
Clock Domain Frequency Usage
Spectrum
135 MHz Differential non-SSC capable
outputs to processor for DisplayPort.
CLKOUT_DPNS_P/N 135 MHz No NOTE: CLKOUT_DPNS_P/N must
always be connected,
regardless of internal graphics
application support.
Programmable 33 MHz, 48/24 MHz or
14.31818 MHz outputs for various
platform devices.
NOTE: It is highly recommended to
prioritize 14.31818/24/48 MHz
CLKOUTFLEX0/ GPIO64 clocks on CLKOUTFLEX1 and
33 MHz /
CLKOUTFLEX1/ GPIO65 14.31818 MHz / CLKOUTFLEX3 outputs. Intel
Yes does not recommend
CLKOUTFLEX2/ GPIO66 48 MHz /
configuring the 14.31818/24/
CLKOUTFLEX3/ GPIO67 24 MHz
48 MHz clocks on
CLKOUTFLEX0 and
CLKOUTFLEX2 if more than
two 33 MHz clocks in addition
to the feedback clock are used
on the CLKOUT_33 MHz
outputs.
17.86 MHz /
Drive SPI devices connected to the
SPI_CLK 31.25 MHz / No
PCH. Generated by the PCH.
50 MHz
4.3 Functional Blocks
The PCH has 1 main PLL in which its output is divided down through Modulators and
Dividers to provide great flexibility in clock source selection, configuration, and better
power management. Table 4-3 describes the PLLs on the PCH and the clock domains
that are driven from the PLLs.
Table 4-3. PCH PLLs
PLL Outputs1 Description/Usage
Four 2.7 GHz outputs 90° apart. Outputs
are routed to each of the Spread Main Reference PLL. Always
Modulator blocks before hitting the various enabled in Integrated Clocking
dividers and the other PLLs to provide mode. Resides in core power well
XCK_PLL
clocks to all of the I/O interface logic. This and is not powered in S3 and below
PLL also provides 5.4 GHz and 2.7 GHz states. Powered in sub-S0 states
CMOS outputs for use by various dividers by a Suspend well Ring oscillator.
to create non-spread output clocks.
NOTES:
1. Indicates the source clock frequencies driven to other internal logic for delivering
functionality needed. Does not indicate external outputs.
Datasheet 127
PCH and System Clocks
Spread Spectrum adjustment can be made without platform reboot. Table 4-4 provides
a basic description of spread modulators that operate on the XCK PLL’s 2.7 GHz
outputs.
Table 4-4. Modulator Blocks
Modulator Description
Used for spread modulation, or bending, on 135 MHz clock to integrated
graphics display. Typical display usage model is 0.5% down-spread. In certain
MOD1
usage case, this modulator can be shut off for 0% spread with or without clock
bending. Used by the display driver only.
Used for spread modulation and fine grain frequency synthesis on nominal
100 MHz overclockable clock to CPU BCLK (CLKOUT_DMI), DMI, PEG. This
MOD2
modulator also subject to adaptive clocking adjustment (for EMC) when left on
at nominal 100 MHz frequency.
Used for spread modulation (and adaptive clocking) on 100 M Hz clock to
MOD3 processor BCLK (CLKOUT_DMI), DMI, PEG, PCIe*, USB 3.0, SATA, Single
Ended 33 MHz, and Thermal Sensor.
Used for fine grain frequency synthesis on nominal 135 MHz, non-spread clock
MOD4
to integrated graphics display. Used by the display driver only.
Used for fine grain frequency synthesis of a wide variety of integrated graphics
MOD5
display VGA clocking needs. Used by the display driver only.
Used for fine grain frequency synthesis of 96 MHz non-spread clock to USB PLL
MOD6 and PCH logic. 48/24 MHz to Flex Clocks are further derived from 96 MHz
output.
Used for fine grain frequency synthesis of 14.31818 MHz non-spread clock to
MOD7
Flex Clocks and PCH logic.
128 Datasheet
PCH and System Clocks
Figure 4-1. PCH Detailed Clock Diagram
PLLRCS[14:13]
CLKOUT_DPNS_P/N
Control through 00 – MODIV3 (POR)
DMI (To Processor)
display register set 01 – MODIV2
FDI_PLL PORT
DMI_PLL
(OC Use)
MCSS [2]
MODIV1 00 –
(135MHz) USB3PCIe_PLL
USB3PCIe_PLL
(Non OC Use)
(POR)
01 – DMI_PLL
MODIV4 CLKOUT_DP_P/N
(135MHz) (To Processor)
VGA_Display PMSync
MODIV5
PLLs MCSS [1]
(Various Freq)
0 – USB3PCIe_PLL
(POR)
1 – DMI_PLL
x2 CLKOUT_PEG_[B:A]_P/N
DCOSS [7:6] PEGB
DCOSS [5:4] PEGA
00 – MODIV3 (POR)
01 – MODIV2
10 – DMI_PLL
CLKOUT_DMI_P/N
MODIV2
DCOSS [9:8] (To Processor)
(100MHz)
00 – MODIV3 (POR)
01 – MODIV2 CLKOUT_ITPXDP_P/N
XCK_PLL / VCO
CLKOUT_PCIE_[7:0]_P/N
PCH Legacy. This must be
MODIV3 SATA_PLL Free Running CLKIN_33MHZ
(100MHz) LOOPBACK
* requires one
Divide by 81 clock copy only
(Non-Spread)
Divide by 3 CLKOUT_33MHz [4:0]
(Spread) DIV_PCI33[22:21]
00 – Spread (POR)
11 – Non-Spread
MODIV6 USB2_PLL
(96Mhz)
DIV4824 (48/
MODIV7 24 MHz)
(14.31818MHz) DIV_FLEX4824[10:8]
001 – 48MHz (POR) x4
101 – 24MHz CLKOUT_FLEX[3:0]
SECOSS [14:12] – CLKOUTFLEX3
SECOSS [10:8] – CLKOUTFLEX2
SECOSS [6:4] – CLKOUTFLEX1
SECOSS [2:0] – CLKOUTFLEX0
FFDIVME 000 – 33.33MHz Clock Source
ME Core
(385.71MHz) 001 – 14.31818MHz Clock Source (default for Flex 1)
010 – 48/24MHz Clock Source (default for Flex 3)
101 – Reserved (default for Flex 0 and Flex 2)
IMPORTANT:
1. Non-POR configurations have not been fully validated by Intel and may be shown only as an example .
2. Overclocking / Center Spread mode places the platform in an unsupported configuration and /or operational state and can result in platform
25MHz instability, physical damage, and data loss. These margins are not guaranteed or supported.
XTAL 3. MODIV2 Clock source is not electrically validated (EV). Example; compliance to PCIe clock jitter, Transmitter jitter performance, etc.
4. MODIV1, MODIV4 and MODIV5 programming is done through the Integrated Graphic Display MMIO register set .
5. CLKOUT_FLEX[3:2] must be programmed to the same clock source for proper operation. For example if both CLKOUT_FLEX[3:2] are to
be enabled and 33MHz is desired on one clock, BOTH clocks have to be programmed for that same frequency and cannot be programmed to
one having a different frequency than the other.
Datasheet 129
PCH and System Clocks
4.4 Clock Configuration Access Overview
The PCH provides increased flexibility of host equivalent configurability of clocks, using
Intel ME FW.
In the Intel ME FW assisted configuration mode, control settings for PLLs, Spread
Modulators, and other clock configuration registers will be handled by the Intel ME. The
parameters to be loaded will reside in the Intel ME data region of the SPI Flash device.
BIOS would only have access to the register set through a set of Intel MEI commands
to the Intel ME.
4.5 Integrated Clock Controller (ICC) Registers
This section describes all registers and base functionality that is related to the
Integrated Clock Controller. The ICC registers are not visible using PCI Configuration
access and it is not mapped to I/O memory as other devices within the PCH. The
control settings for the ICC clock structure is located in registers directly under the
control of the Intel Management Engine (Intel ME).
ICC register access is only accessible using Intel ME FW and must be programmed
using available FW access tools. The ICC registers disclosed in this chapter cover user
adjustable features within the ICC subsystem programmable through available FW
access tools.
4.5.1 ICC Registers under Intel® Management Engine (Intel®
ME) Control
Table 4-1. ICC Registers under Intel® Management Engine (Intel® ME) Control (Sheet 1
of 2)
Mnemonic Register Name Default
100 MHz SSC Divider Integer Phase Control
SSCDIVINPHASE_DMI100 0000_0032h
for DMI Clock
100 MHz SSC Triangle Parameter for DMI
SSCTRIPARAM_DMI100 1240_4038h
Clock
SSCCTL_DMI100 100 MHz SSC Control for DMI Clock 0000_0001h
100 MHz SSC Divider Integer Phase Control
SSCDIVINPHASE_PCHPCIE100 0000_0032h
for PCH PCIE Clocks
100 MHz SSC Triangle Parameter for PCH
SSCTRIPARAM_PCHPCIE100 1240_4038h
PCIE Clocks
SSCCTL_PCHPCIE100 100 MHz SSC Control for PCH PCIE Clocks 0000_0000h
33 MHz Single Ended Clock Divide and
DIV_PCI33 0003_0203h
Spread Enable
48/24 MHz Single Ended Flex Clock Divide
DIV_FLEX4824 0003_0103h
Enable
OCKEN Output Clock Enables 7DFF_0F8Fh
SEFLXBP Single Ended Flex Buffer Parameters 0000_9999h
Single Ended 33 MHz Clock Buffer
SEPCICLKBP 0009_9999h
Parameters
DCOSS Differential Clock Out Source Select 0000_0400h
130 Datasheet
PCH and System Clocks
Table 4-1. ICC Registers under Intel® Management Engine (Intel® ME) Control (Sheet 2
of 2)
Mnemonic Register Name Default
SECOSS Single Ended Clock Out Source Select 0000_2516h
MCSS Miscellaneous Clock Source Select 0000_0001h
PLLRCS PLL Reference Clock Select 0001_1114h
ICCCTL ICC Control 0000_0008h
PMPCI Power Management 33 MHz Clock 0000_0000h
PM1PCIECLK Power Management 1 PCIe Clock 7654_3210h
PM2PCIECLK Power Management 2 PCIe Clock 0000_0098h
4.5.1.1 SSCDIVINTPHASE_DMI100—100MHz DMI Clock SSC Divider
Integer Phase Control Register
Attribute: R/W
Default Value: 00000032h Size: 32-bit
Bit Description
100MHz Clock SSC Phase Control—R/W. This register is used to control the over-
31:0 clockable clock source (such as 100 MHz BCLK, MODIV2). Firmware may program
this field with various values when over-clocking is used.
4.5.1.2 SSCTRIPARAM_DMI100—100MHz DMI Clock SSC Triangle
Register
Attribute: R/W
Default Value: 12404038h Size: 32-bit
Bit Description
100MHz Clock SSC Triangle Control—R/W. This register is used to control the
31:0 over-clockable clock source (such as 100 MHz BCLK, MODIV2). Firmware may
program this field with various values when SSC is enabled.
4.5.1.3 SSCCTL_DMI100—100MHz DMI Clock SSC Control Register
Attribute: R/W
Default Value: 00000001h Size: 32-bit
Bit Description
100MHz Clock SSC Control—R/W. This register is used to turn on the overclockable
31:0 clock source. Firmware may program this field with various values when SSC is
enabled.
Datasheet 131
PCH and System Clocks
4.5.1.4 SSCDIVINTPHASE_PCHPCIE100—100MHz PCH PCIE Clock SSC
Divider Integer Phase Register
Attribute: R/W
Default Value: 00000032h Size: 32-bit
Bit Description
100MHz PCIe* Clock SSC Phase Control—R/W. This register is used for tuning
31:0 PCIe Adaptive Clocking frequency. Firmware may program this field with various
values when adjusting PCIe adaptive clocking values.
4.5.1.5 SSCTRIPARAM_PCHPCIE100—100MHz PCH PCIE Clock SSC
Triangle Register
Attribute: R/W
Default Value: 12404038h Size: 32-bit
Bit Description
100MHz PCIe Clock SSC Triangle Control—R/W. This register is used for PCH
31:0 PCIE clock SSC control. Firmware may program this field with various values when
SSC is enabled.
4.5.1.6 SSCCTL_PCHPCIE100—100MHz PCH PCIE* Clock SSC Control
Register
Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
100MHz PCIe Clock SSC Control—R/W. This register is used for PCH PCIE clock
31:0
SSC control. Should only use the default value.
4.5.1.7 DIV_PCI33—33MHz Single Ended Clock Divide and Spread
Enable Register
Attribute: R/W
Default Value: 00030203h Size: 32-bit
Bit Description
31:23 Reserved
DIV_PCI33 Clock Mux Control 1—R/W. Internal multiplex control for 33.33 MHz
clock direction.
22:21 00 = 33.33 MHz SSC (Default)
10 = 33.33 MHz non-SSC
All other values are not supported.
20:17 Reserved
132 Datasheet
PCH and System Clocks
Bit Description
DIV_PCI33 Clock Mux Control 2—R/W. Internal multiplex control for 33.33 MHz
clock direction.
16
0 = 33.33 MHz SSC (Default)
1 = 33.33 MHz non-SSC
DIV_PCI33 Enable/Disable—R/W.
15 0 = Enables divider for SSC. (Default)
1 = Enables divider with no SSC.
14:13 Reserved
DIV_PCI33 Clock Internal Gating Enable—R/W.
12 0 = 33.33 MHz SSC (Default)
1 = 33.33 MHz non-SSC
11 Reserved
DIV_PCI33 Divider Selection—R/W.
010 =Divide by 3 from an internal 100 MHz clock source for 33 MHz single ended
10:8
clocks.
All other values are not supported.
7 Reserved
DIV_PCI33 Divider Value Counter—R/W. Bit value only valid when use in non-
SSC configurations.
6:0
001_1001 = 33.33 MHz frequency
All other values are not supported.
4.5.1.8 DIV_FLEX4824—48MHz and 24MHz Single Ended FLEX Clock
Divide Enable Register
Attribute: R/W
Default Value: 00030103h Size: 32-bit
Bit Description
31:16 Reserved
DIV_FLEX4824 Enable/Disable—R/W. This register controls the 48 MHz and
24 MHz single ended FLEX clock divider from a 96 MHz internal clock source.
15
0 = Enables divider
1 = Disables divider
14:11 Reserved
DIV_FLEX4824 Divider Selection—R/W.
001 = Enables a divide by 2 from an internal 96 MHz clock source for 48 MHz single
ended clock FLEX clock output frequency. (Default)
10:8
100 = Enables a divide by 4 from an internal 96 MHz clock source for a 24 MHz
single ended clock FLEX clock output frequency.
All other values are not supported.
7:0 Reserved
Datasheet 133
PCH and System Clocks
4.5.1.9 OCKEN—Output Clock Enable Register
Attribute: R/W
Default Value: 7DFF0F8Fh Size: 32-bit
Bit Description
31 Reserved
DPNS Clock Output Clock Enable—R/W.
0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default)
30
NOTE: This clock must be connected to the processor (and functional) regardless of
internal graphics configuration support.
DP Clock Output Clock Enable—R/W.
29 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default)
DMI Clock Output Clock Enable—R/W.
28 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default)
PEG_B Clock Output Clock Enable—R/W.
27 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default)
PEG_A Clock Output Clock Enable—R/W.
26 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default)
25 Reserved
ITPXDP Clock Output Clock Enable—R/W.
24 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default)
PCIe* Clock 7 Output Clock Enable—R/W.
23 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
PCIe Clock 6 Output Clock Enable—R/W.
22 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
PCIe Clock 5 Output Clock Enable—R/W.
21 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
PCIe Clock 4 Output Clock Enable—R/W.
20 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
PCIe Clock 3 Output Clock Enable—R/W.
19 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
PCIe Clock 2 Output Clock Enable—R/W.
18 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
134 Datasheet
PCH and System Clocks
Bit Description
PCIe Clock 1 Output Clock Enable—R/W.
17 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
PCIe* Clock 0 Output Clock Enable—R/W.
16 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
15:12 Reserved
33MHz Clock 4 Output Clock Enable—R/W.
11 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
33MHz Clock 3 Output Clock Enable—R/W.
10 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
33MHz Clock 2 Output Clock Enable—R/W.
9 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
33MHz Clock 1 Output Clock Enable—R/W.
8 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
33MHz Clock 0 Output Clock Enable—R/W.
7 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
6:4 Reserved
FLEX Clock 3 Output Clock Enable—R/W.
3 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
FLEX Clock 2 Output Clock Enable—R/W.
2 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
FLEX Clock 1 Output Clock Enable—R/W.
1 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
FLEX Clock 0 Output Clock Enable—R/W.
0 0 = Output is gated to a low state.
1 = Output is enabled to toggle (Default).
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PCH and System Clocks
4.5.1.10 SEFLXBP—Single Ended Flex Buffer Parameter Register
Attribute: R/W
Default Value: 00009999h Size: 32-bit
Bit Description
31:16 Reserved
FLEX3 Clock Buffer Slew Rate Selection—R/W. This parameter controls slew rate
of FLEX clock 3. Each bit step change corresponds to ~0.2 V/ns.
15:13 000 = 0.6 V/ns minimum
100 = 1.4 V/ns (Default)
111 = 2.0 V/ns maximum
FLEX3 Clock Buffer Resistance Selection—R/W. This parameter controls Single/
Double load series resistance.
12
0 = 25 single load usage
1 = 17 double load usage (Default).
FLEX2 Clock Buffer Slew Rate Selection—R/W. This parameter controls slew rate
of FLEX clock 3. Each bit step change corresponds to ~0.2 V/ns.
11:9 000 = 0.6 V/ns minimum
100 = 1.4 V/ns (Default)
111 = 2.0 V/ns maximum
FLEX2 Clock Buffer Resistance Selection—R/W. This parameter controls Single/
Double load series resistance.
8
0 = 25 single load usage
1 = 17 double load usage (Default).
FLEX1 Clock Buffer Slew Rate Selection—R/W. This parameter controls slew rate
of FLEX clock 3. Each bit step change corresponds to ~0.2 V/ns.
7:5 000 = 0.6 V/ns minimum
100 = 1.4 V/ns (Default)
111 = 2.0 V/ns maximum
FLEX1 Clock Buffer Resistance Selection—R/W. This parameter controls Single/
Double load series resistance.
4
0 = 25 single load usage
1 = 17 double load usage (Default).
FLEX0 Clock Buffer Slew Rate Selection—R/W. This parameter controls slew rate
of FLEX clock 3. Each bit step change corresponds to ~0.2 V/ns.
3:1 000 = 0.6 V/ns minimum
100 = 1.4 V/ns (Default)
111 = 2.0 V/ns maximum
FLEX0 Clock Buffer Resistance Selection—R/W. This parameter controls Single/
Double load series resistance.
0
0 = 25 single load usage
1 = 17 double load usage (Default).
136 Datasheet
PCH and System Clocks
4.5.1.11 SEPCICLKBP—Single Ended 33 MHz Clock Buffer
Parameter Register
Attribute: R/W
Default Value: 00099999h Size: 32-bit
Bit Description
31:20 Reserved
CLKOUT_33MHz_4 Clock Buffer Slew Rate Selection—R/W. This parameter
controls slew rate of 33 MHz clock 4. Each bit step change corresponds to ~0.2 V/ns.
19:17 000 = 0.6 V/ns minimum
100 = 1.4 V/ns (Default)
111 = 2.0 V/ns maximum
CLKOUT_33MHz_4 Clock Buffer Resistance Selection—R/W. This parameter
controls Single/Double load series resistance.
16
0 = 25 single load usage
1 = 17 double load usage (Default).
CLKOUT_33MHz_3 Clock Buffer Slew Rate Selection—R/W. This parameter
controls slew rate of 33 MHz clock 3. Each bit step change corresponds to ~0.2 V/ns.
15:13 000 = 0.6 V/ns minimum
100 = 1.4 V/ns (Default)
111 = 2.0 V/ns maximum
CLKOUT_33MHz_3 Clock Buffer Resistance Selection—R/W. This parameter
controls Single/Double load series resistance.
12
0 = 25 single load usage
1 = 17 double load usage (Default).
CLKOUT_33MHz_2 Clock Buffer Slew Rate Selection—R/W. This parameter
controls slew rate of 33 MHz clock 2. Each bit step change corresponds to ~0.2 V/ns.
11:9 000 = 0.6 V/ns minimum
100 = 1.4 V/ns (Default)
111 = 2.0 V/ns maximum
CLKOUT_33MHz_2 Clock Buffer Resistance Selection—R/W. This parameter
controls Single/Double load series resistance.
8
0 = 25 single load usage
1 = 17 double load usage (Default).
CLKOUT_33MHz_1 Clock Buffer Slew Rate Selection—R/W. This parameter
controls slew rate of 33 MHz clock 1. Each bit step change corresponds to ~0.2 V/ns.
7:5 000 = 0.6 V/ns minimum
100 = 1.4 V/ns (Default)
111 = 2.0 V/ns maximum
CLKOUT_33MHz_1 Clock Buffer Resistance Selection—R/W. This parameter
controls Single/Double load series resistance.
4
0 = 25 single load usage
1 = 17 double load usage (Default).
CLKOUT_33MHz_0 Clock Buffer Slew Rate Selection—R/W. This parameter
controls slew rate of 33 MHz clock 0. Each bit step change corresponds to ~0.2 V/ns.
3:1 000 = 0.6 V/ns minimum
100 = 1.4 V/ns (Default)
111 = 2.0 V/ns maximum
Datasheet 137
PCH and System Clocks
Bit Description
CLKOUT_33MHz_0 Clock Buffer Resistance Selection—R/W. This parameter
controls Single/Double load series resistance.
0
0 = 25 single load usage
1 = 17 double load usage (Default)
4.5.1.12 DCOSS—Differential Clock Out Source Select Register
Attribute: R/W
Default Value: 00000400h Size: 32-bit
Bit Description
31:10 Reserved
CLKOUT_DMI Source Select—R/W. This parameter selects the source of clock to
be driven out on CLKOUT_DMI. When not over-clocking this output should be sourced
by the PCIe clock source MODIV3.
9:8 00 = Non-Overclockable source MODIV3 (Default)
01 = Overclockable source MODIV2
10 = Reserved
11 = Reserved
CLKOUT_PEGB Source Select—R/W. This parameter selects the source of clock to
be driven out on CLKOUT_PEGB. When not over-clocking this output should be
sourced by the PCIe clock source MODIV3. When over-clocking this output should be
sourced from DMI_PLL derived off of MODIV2.
7:6 00 = Non-Overclockable source MODIV3 (Default)
01 = Over-clockable source from MODIV2
10 = Over-clockable source from DMI_PLL derived from MODIV2
11 = Reserved
CLKOUT_PEGA Source Select—R/W. This parameter selects the source of clock to
be driven out on CLKOUT_PEGA. When not over-clocking this output should be
sourced by the PCIe clock source MODIV3. When over-clocking this output should be
sourced from DMI_PLL derived off of MODIV2.
5:4 00 = Non-Overclockable source MODIV3 (Default)
01 = Overclockable source from MODIV2
10 = Overclockable source from DMI_PLL derived from MODIV2
11 = Reserved
3:0 Reserved
138 Datasheet
PCH and System Clocks
4.5.1.13 SECOSS—Single Ended Clock Out Source Select Register
Attribute: R/W
Default Value: 00002516h Size: 32-bit
Note: CLKOUTFLEX2 and CLKOUTFLEX3 can be configured to any of the supported clock
frequencies: 14.31818 MHz, 48 MHz, 24 MHz, 33.33 MHz. However, both CLKOUTFLEX2
and CLKOUTFLEX3 must be configured to the same frequency, and never to different
frequency values on the two clock outputs. Alternatively, either CLKOUTFLEX2 or
CLKOUTFLEX3 is configured to any of the above listed supported frequencies while the
other one is gated disabled or re-configured as a GPIO. This restriction is to mitigate
noise coupling.
Bit Description
31:15 Reserved
CLKOUTFLEX3 Source Select—R/W. This field selects the source of clock to be
driven out on CLKOUTFLEX3.
000 = 33.33 MHz Clock Source
14:12
001 = 14.31818 MHz Clock Source
010 = 48/24 MHz Clock Source (Default)
All other values are not supported.
11 Reserved
CLKOUTFLEX2 Source Select—R/W. This field selects the source of clock to be
driven out on CLKOUTFLEX2.
000 = 33.33 MHz Clock Source
001 = 14.31818 MHz Clock Source
10:8 010 = 48/24 MHz Clock Source
All other values are not supported.
NOTE: Default setting is ‘101b’, which is a non-supported setting. This is expected to
be programmed to a supported frequency.
7 Reserved
CLKOUTFLEX1 Source Select—R/W. This field selects the source of clock to be
driven out on CLKOUTFLEX1.
000 = 33.33 MHz Clock Source
6:4
001 = 14.31818 MHz Clock Source (Default)
010 = 48/24 MHz Clock Source
All other values are not supported.
3 Reserved
CLKOUTFLEX0 Source Select—R/W. This field selects the source of clock to be
driven out on CLKOUTFLEX0.
000 = 33.33 MHz Clock Source
001 = 14.31818 MHz Clock Source
2:0 010 = 48/24 MHz Clock Source
All other values are not supported.
NOTE: Default setting is ‘101b’ for a non-supported frequency. This needs to be
programmed to a supported frequency.
Datasheet 139
PCH and System Clocks
4.5.1.14 MCSS—Miscellaneous Clock Source Select Register
Attribute: R/W
Default Value: 00000001h Size: 32-bit
Bit Description
31:3 Reserved
DMI Port Clock Select—R/W. This field supports the source of the clocks used by
the DMI port.
2
0 = USB3PCIe PLL Clock Source during Non-Overclocking use. (Default)
1 = DMI PLL Clock Source when Overclocking is used
PMSync Clock Source Select—R/W. This field supports the source of the clock for
the PCH internal PMSync logic.
1 0 = Non-overclocking Clock Source MODIV3 (Default)
1 = Overclocking Clock Source MODIV2
0 Reserved
4.5.1.15 PLLRCS—PLL Reference Clock Select Register
Attribute: R/W
Default Value: 00011114h Size: 32-bit
Bit Description
31:15 Reserved
DMI PLL Reference Select—R/W. This field supports the source of the clock for the
DMI PLL.
14:13 01 = DMI PLL is driven by Overclocking Cl.ock Source MODIV2
All other values are not supported.
Reprogramming from hardware default is required for overclocking usage
12:0 Reserved
4.5.1.16 ICCCTL—ICC Control Register
Attribute: R/W
Default Value: 00000008h Size: 32-bit
Bit Description
31:5 Reserved
Dynamic Power Management for 96MHz Clock Source MODIV6—R/W. This
field enables power management for all clocks that use this source to be brought
4 down to the lowest power state when hardware detects an idle condition.
0 = Power Management is Disabled (Default)
1 = Power Management is Enabled
3 Reserved
140 Datasheet
PCH and System Clocks
Bit Description
Warm Reset Gating of CLKOUT_DPNS—R/W. This field enabled whether
CLKOUT_DPNS is gated during Warm Reset.
2
0 = CLKOUT_DPNS is not gated (Default)
1 = CLKOUT_DPNS is gated
Warm Reset Gating of CLKOUT_PEGA/PEGB—R/W. This field enabled whether
CLKOUT_PEGA/PEGB are gated during Warm Reset.
1
0 = CLKOUT_PEGA/PEGB are not gated (Default)
1 = CLKOUT_PEGA/PEGB are gated
0 Reserved
4.5.1.17 PMPCI—33MHz Single Ended Clock Power Management Register
Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:9 Reserved
CLKRUN Control Enable for 33MHz Single Ended Clocks on CLKOUTFLEX3—R/W.
Controls the enabling of support for CLKRUN protocol for 33 MHz clocks multiplexed out
8 on CLKOUTFLEX3 pin.
0 = CLKRUN Control is disabled and clock is free running (Default)
1 = CLKRUN Control is enabled and clock output can be turned off
CLKRUN Control Enable for 33MHz Single Ended Clocks on CLKOUTFLEX2—R/W.
Controls the enabling of support for CLKRUN protocol for 33 MHz clocks multiplexed out
7 on CLKOUTFLEX2 pin.
0 = CLKRUN Control is disabled and clock is free running (Default)
1 = CLKRUN Control is enabled and clock output can be turned off
CLKRUN Control Enable for 33MHz Single Ended Clocks on CLKOUTFLEX1—R/W.
Controls the enabling of support for CLKRUN protocol for 33 MHz clocks multiplexed out
6 on CLKOUTFLEX1 pin.
0 = CLKRUN Control is disabled and clock is free running (Default)
1 = CLKRUN Control is enabled and clock output can be turned off
CLKRUN Control Enable for 33MHz Single Ended Clocks on CLKOUTFLEX0—R/W.
Controls the enabling of support for CLKRUN protocol for 33 MHz clocks multiplexed out
5 on CLKOUTFLEX0 pin.
0 = CLKRUN Control is disabled and clock is free running (Default)
1 = CLKRUN Control is enabled and clock output can be turned off
CLKRUN Control Enable for fixed 33MHz Single Ended Clock Output 4—R/W.
Controls the enabling of support for CLKRUN protocol for fixed 33 MHz clock outputs.
4
0 = CLKRUN Control is disabled and clock is free running (Default)
1 = CLKRUN Control is enabled and clock output can be turned off
CLKRUN Control Enable for fixed 33MHz Single Ended Clock Output 3—R/W.
Controls the enabling of support for CLKRUN protocol for fixed 33 MHz clock outputs.
3
0 = CLKRUN Control is disabled and clock is free running (Default)
1 = CLKRUN Control is enabled and clock output can be turned off
Datasheet 141
PCH and System Clocks
Bit Description
CLKRUN Control Enable for fixed 33MHz Single Ended Clock Output 2—R/W.
Controls the enabling of support for CLKRUN protocol for fixed 33 MHz clock outputs.
2
0 = CLKRUN Control is disabled and clock is free running (Default)
1 = CLKRUN Control is enabled and clock output can be turned off
CLKRUN Control Enable for fixed 33MHz Single Ended Clock Output 1—R/W.
Controls the enabling of support for CLKRUN protocol for fixed 33 MHz clock outputs.
1
0 = CLKRUN Control is disabled and clock is free running (Default)
1 = CLKRUN Control is enabled and clock output can be turned off
CLKRUN Control Enable for fixed 33MHz Single Ended Clock Output 0—R/W.
Controls the enabling of support for CLKRUN protocol for fixed 33 MHz clock outputs.
0
0 = CLKRUN Control is disabled and clock is free running (Default)
1 = CLKRUN Control is enabled and clock output can be turned off
4.5.1.18 PM1PCIECLK—Power Management 1 PCIE Clock Register
Attribute: R/W
Default Value: 76543210h Size: 32-bit
Bit Description
CLKRQ# Select for CLKOUT_PCIE7_P/N—R/W. Select version of external input
CLKRQ# for dynamic control of the output CLKOUT_PCIE7_P/N.
0000 = PCIECLKRQ0# (GPIO 73) controls CLKOUT_PCIE7_P/N
0001 = PCIECLKRQ1# (GPIO 18) controls CLKOUT_PCIE7_P/N
0010 = PCIECLKRQ2# (GPIO 20) controls CLKOUT_PCIE7_P/N
0011 = PCIECLKRQ3# (GPIO 25) controls CLKOUT_PCIE7_P/N
31:28 0100 = PCIECLKRQ4# (GPIO 26) controls CLKOUT_PCIE7_P/N
0101 = PCIECLKRQ5# (GPIO 44) controls CLKOUT_PCIE7_P/N
0110 = PCIECLKRQ6# (GPIO 45) controls CLKOUT_PCIE7_P/N
0111 = PCIECLKRQ7# (GPIO 46) controls CLKOUT_PCIE7_P/N (Default)
1000 = PEG_A_CLKRQ# (GPIO47) controls CLKOUT_PCIE7_P/N
1001 = PEG_B_CLKRQ# (GPIO56)controls CLKOUT_PCIE7_P/N
1010 – 1111 = RSVD
CLKRQ# Select for CLKOUT_PCIE6_P/N—R/W. Select version of external input
CLKRQ# for dynamic control of the output CLKOUT_PCIE6_P/N.
0000 = PCIECLKRQ0# (GPIO 73) controls CLKOUT_PCIE6_P/N
0001 = PCIECLKRQ1# (GPIO 18) controls CLKOUT_PCIE6_P/N
0010 = PCIECLKRQ2# (GPIO 20) controls CLKOUT_PCIE6_P/N
0011 = PCIECLKRQ3# (GPIO 25) controls CLKOUT_PCIE6_P/N
27:24
0100 = PCIECLKRQ4# (GPIO 26) controls CLKOUT_PCIE6_P/N
0101 = PCIECLKRQ5# (GPIO 44) controls CLKOUT_PCIE6_P/N
0110 = PCIECLKRQ6# (GPIO 45) controls CLKOUT_PCIE6_P/N (Default)
0111 = PCIECLKRQ7# (GPIO 46) controls CLKOUT_PCIE6_P/N
1000 = PEG_A_CLKRQ# (GPIO47) controls CLKOUT_PCIE6_P/N
1001 = PEG_B_CLKRQ# (GPIO56)controls CLKOUT_PCIE6_P/N
1010 – 1111 = RSVD
142 Datasheet
PCH and System Clocks
Bit Description
CLKRQ# Select for CLKOUT_PCIE5_P/N—R/W. Select version of external input
CLKRQ# for dynamic control of the output CLKOUT_PCIE5_P/N.
0000 = PCIECLKRQ0# (GPIO 73) controls CLKOUT_PCIE5_P/N
0001 = PCIECLKRQ1# (GPIO 18) controls CLKOUT_PCIE5_P/N
0010 = PCIECLKRQ2# (GPIO 20) controls CLKOUT_PCIE5_P/N
0011 = PCIECLKRQ3# (GPIO 25) controls CLKOUT_PCIE5_P/N
23:20
0100 = PCIECLKRQ4# (GPIO 26) controls CLKOUT_PCIE5_P/N
0101 = PCIECLKRQ5# (GPIO 44) controls CLKOUT_PCIE5_P/N (Default)
0110 = PCIECLKRQ6# (GPIO 45) controls CLKOUT_PCIE5_P/N
0111 = PCIECLKRQ7# (GPIO 46) controls CLKOUT_PCIE5_P/N
1000 = PEG_A_CLKRQ# (GPIO47) controls CLKOUT_PCIE5_P/N
1001 = PEG_B_CLKRQ# (GPIO56)controls CLKOUT_PCIE5_P/N
1010 – 1111 = RSVD
CLKRQ# Select for CLKOUT_PCIE4_P/N—R/W. Select version of external input
CLKRQ# for dynamic control of the output CLKOUT_PCIE4_P/N.
0000 = PCIECLKRQ0# (GPIO 73) controls CLKOUT_PCIE4_P/N
0001 = PCIECLKRQ1# (GPIO 18) controls CLKOUT_PCIE4_P/N
0010 = PCIECLKRQ2# (GPIO 20) controls CLKOUT_PCIE4_P/N
0011 = PCIECLKRQ3# (GPIO 25) controls CLKOUT_PCIE4_P/N
19:16 0100 = PCIECLKRQ4# (GPIO 26) controls CLKOUT_PCIE4_P/N (Default)
0101 = PCIECLKRQ5# (GPIO 44) controls CLKOUT_PCIE4_P/N
0110 = PCIECLKRQ6# (GPIO 45) controls CLKOUT_PCIE4_P/N
0111 = PCIECLKRQ7# (GPIO 46) controls CLKOUT_PCIE4_P/N
1000 = PEG_A_CLKRQ# (GPIO47) controls CLKOUT_PCIE4_P/N
1001 = PEG_B_CLKRQ# (GPIO56)controls CLKOUT_PCIE4_P/N
1010 – 1111 = RSVD
CLKRQ# Select for CLKOUT_PCIE3_P/N—R/W. Select version of external input
CLKRQ# for dynamic control of the output CLKOUT_PCIE3_P/N.
0000 = PCIECLKRQ0# (GPIO 73) controls CLKOUT_PCIE3_P/N
0001 = PCIECLKRQ1# (GPIO 18) controls CLKOUT_PCIE3_P/N
0010 = PCIECLKRQ2# (GPIO 20) controls CLKOUT_PCIE3_P/N
0011 = PCIECLKRQ3# (GPIO 25) controls CLKOUT_PCIE3_P/N (Default)
15:12
0100 = PCIECLKRQ4# (GPIO 26) controls CLKOUT_PCIE3_P/N
0101 = PCIECLKRQ5# (GPIO 44) controls CLKOUT_PCIE3_P/N
0110 = PCIECLKRQ6# (GPIO 45) controls CLKOUT_PCIE3_P/N
0111 = PCIECLKRQ7# (GPIO 46) controls CLKOUT_PCIE3_P/N
1000 = PEG_A_CLKRQ# (GPIO47) controls CLKOUT_PCIE3_P/N
1001 = PEG_B_CLKRQ# (GPIO56)controls CLKOUT_PCIE3_P/N
1010 – 1111 = RSVD
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PCH and System Clocks
Bit Description
CLKRQ# Select for CLKOUT_PCIE2_P/N—R/W. Select version of external input
CLKRQ# for dynamic control of the output CLKOUT_PCIE2_P/N.
0000 = PCIECLKRQ0# (GPIO 73) controls CLKOUT_PCIE2_P/N
0001 = PCIECLKRQ1# (GPIO 18) controls CLKOUT_PCIE2_P/N
0010 = PCIECLKRQ2# (GPIO 20) controls CLKOUT_PCIE2_P/N (Default)
0011 = PCIECLKRQ3# (GPIO 25) controls CLKOUT_PCIE2_P/N
11:8 0100 = PCIECLKRQ4# (GPIO 26) controls CLKOUT_PCIE2_P/N
0101 = PCIECLKRQ5# (GPIO 44) controls CLKOUT_PCIE2_P/N
0110 = PCIECLKRQ6# (GPIO 45) controls CLKOUT_PCIE2_P/N
0111 = PCIECLKRQ7# (GPIO 46) controls CLKOUT_PCIE2_P/N
1000 = PEG_A_CLKRQ# (GPIO47) controls CLKOUT_PCIE2_P/N
1001 = PEG_B_CLKRQ# (GPIO56)controls CLKOUT_PCIE2_P/N
1010 – 1111 = RSVD
CLKRQ# Select for CLKOUT_PCIE1_P/N—R/W. Select version of external input
CLKRQ# for dynamic control of the output CLKOUT_PCIE1_P/N.
0000 = PCIECLKRQ0# (GPIO 73) controls CLKOUT_PCIE1_P/N
0001 = PCIECLKRQ1# (GPIO 18) controls CLKOUT_PCIE1_P/N (Default)
0010 = PCIECLKRQ2# (GPIO 20) controls CLKOUT_PCIE1_P/N
0011 = PCIECLKRQ3# (GPIO 25) controls CLKOUT_PCIE1_P/N
7:4 0100 = PCIECLKRQ4# (GPIO 26) controls CLKOUT_PCIE1_P/N
0101 = PCIECLKRQ5# (GPIO 44) controls CLKOUT_PCIE1_P/N
0110 = PCIECLKRQ6# (GPIO 45) controls CLKOUT_PCIE1_P/N
0111 = PCIECLKRQ7# (GPIO 46) controls CLKOUT_PCIE1_P/N
1000 = PEG_A_CLKRQ# (GPIO47) controls CLKOUT_PCIE1_P/N
1001 = PEG_B_CLKRQ# (GPIO56)controls CLKOUT_PCIE1_P/N
1010 – 1111 = RSVD
CLKRQ# Select for CLKOUT_PCIE0_P/N—R/W. Select version of external input
CLKRQ# for dynamic control of the output CLKOUT_PCIE0_P/N.
0000 = PCIECLKRQ0# (GPIO 73) controls CLKOUT_PCIE0_P/N (Default)
0001 = PCIECLKRQ1# (GPIO 18) controls CLKOUT_PCIE0_P/N
0010 = PCIECLKRQ2# (GPIO 20) controls CLKOUT_PCIE0_P/N
0011 = PCIECLKRQ3# (GPIO 25) controls CLKOUT_PCIE0_P/N
3:0 0100 = PCIECLKRQ4# (GPIO 26) controls CLKOUT_PCIE0_P/N
0101 = PCIECLKRQ5# (GPIO 44) controls CLKOUT_PCIE0_P/N
0110 = PCIECLKRQ6# (GPIO 45) controls CLKOUT_PCIE0_P/N
0111 = PCIECLKRQ7# (GPIO 46) controls CLKOUT_PCIE0_P/N
1000 = PEG_A_CLKRQ# (GPIO47) controls CLKOUT_PCIE0_P/N
1001 = PEG_B_CLKRQ# (GPIO56)controls CLKOUT_PCIE0_P/N
1010 – 1111 = RSVD
144 Datasheet
PCH and System Clocks
4.5.1.19 PM2PCIECLK—Power Management 2 PCIE Clock Register
Attribute: R/W
Default Value: 00000098h Size: 32-bit
Bit Description
31:27 Reserved
Enable CLKREQ# for CLKOUT_ ITPXDP_P/N—R/W. Enable dynamic control of
CLKOUT_ ITPXDP_P/N by the mapped CLKREQ#. This register bit may be updated
26 dynamically.
0 = Disable dynamic control of CLKOUT_ ITPXDP_P/N (Default)
1 = Enable dynamic control of CLKOUT_ ITPXDP_P/N
Enable CLKREQ# for CLKOUT_ PEG_B_P/N—R/W. Enable dynamic control of
CLKOUT_PEG_B_P/N by the mapped CLKREQ#. This register bit may be updated
25 dynamically.
0 = Disable dynamic control of CLKOUT_PEG_B_P/N (Default)
1 = Enable dynamic control of CLKOUT_PEG_B_P/N
Enable CLKREQ# for CLKOUT_ PEG_A_P/N—R/W. Enable dynamic control of
CLKOUT_ PEG_A_P/N by the mapped CLKREQ#. This register bit may be updated
24 dynamically.
0 = Disable dynamic control of CLKOUT_ PEG_A_P/N (Default)
1 = Enable dynamic control of CLKOUT_ PEG_A_P/N
Enable CLKREQ# for CLKOUT_ PCIE7_P/N—R/W. Enable dynamic control of
CLKOUT_ PCIE7_P/N by the mapped CLKREQ#. This register bit may be updated
23 dynamically.
0 = Disable dynamic control of CLKOUT_ PCIE7_P/N (Default)
1 = Enable dynamic control of CLKOUT_ PCIE7_P/N
Enable CLKREQ# for CLKOUT_ PCIE6_P/N—R/W. Enable dynamic control of
CLKOUT_ PCIE6_P/N by the mapped CLKREQ#. This register bit may be updated
22 dynamically.
0 = Disable dynamic control of CLKOUT_ PCIE6_P/N (Default)
1 = Enable dynamic control of CLKOUT_ PCIE6_P/N
Enable CLKREQ# for CLKOUT_ PCIE5_P/N—R/W. Enable dynamic control of
CLKOUT_ PCIE5_P/N by the mapped CLKREQ#. This register bit may be updated
21 dynamically.
0 = Disable dynamic control of CLKOUT_ PCIE5_P/N (Default)
1 = Enable dynamic control of CLKOUT_ PCIE5_P/N
Enable CLKREQ# for CLKOUT_ PCIE4_P/N—R/W. Enable dynamic control of
CLKOUT_ PCIE4_P/N by the mapped CLKREQ#. This register bit may be updated
20 dynamically.
0 = Disable dynamic control of CLKOUT_ PCIE4_P/N (Default)
1 = Enable dynamic control of CLKOUT_ PCIE4_P/N
Enable CLKREQ# for CLKOUT_ PCIE3_P/N—R/W. Enable dynamic control of
CLKOUT_ PCIE3_P/N by the mapped CLKREQ#. This register bit may be updated
19 dynamically.
0 = Disable dynamic control of CLKOUT_ PCIE3_P/N (Default)
1 = Enable dynamic control of CLKOUT_ PCIE3_P/N
Datasheet 145
PCH and System Clocks
Bit Description
Enable CLKREQ# for CLKOUT_ PCIE2_P/N—R/W. Enable dynamic control of
CLKOUT_ PCIE2_P/N by the mapped CLKREQ#. This register bit may be updated
18 dynamically.
0 = Disable dynamic control of CLKOUT_ PCIE2_P/N (Default)
1 = Enable dynamic control of CLKOUT_ PCIE2_P/N
Enable CLKREQ# for CLKOUT_ PCIE1_P/N—R/W. Enable dynamic control of
CLKOUT_ PCIE1_P/N by the mapped CLKREQ#. This register bit may be updated
17 dynamically.
0 = Disable dynamic control of CLKOUT_ PCIE1_P/N (Default)
1 = Enable dynamic control of CLKOUT_ PCIE1_P/N
Enable CLKREQ# for CLKOUT_ PCIE0_P/N—R/W. Enable dynamic control of
CLKOUT_ PCIE0_P/N by the mapped CLKREQ#. This register bit may be updated
16 dynamically.
0 = Disable dynamic control of CLKOUT_ PCIE0_P/N (Default)
1 = Enable dynamic control of CLKOUT_ PCIE0_P/N
15:12 Reserved
CLKRQ# Select for CLKOUT_ITPXDP_P/N—R/W. Select version of external input
CLKRQ# for dynamic control of the output CLKOUT_ITPXDP_P/N.
0000 = PCIECLKRQ0# (GPIO 73) controls CLKOUT_ITPXDP_P/N (Default)
0001 = PCIECLKRQ1# (GPIO 18) controls CLKOUT_ITPXDP_P/N
0010 = PCIECLKRQ2# (GPIO 20) controls CLKOUT_ITPXDP_P/N
0011 = PCIECLKRQ3# (GPIO 25) controls CLKOUT_ITPXDP_P/N
11:8
0100 = PCIECLKRQ4# (GPIO 26) controls CLKOUT_ITPXDP_P/N
0101 = PCIECLKRQ5# (GPIO 44) controls CLKOUT_ITPXDP_P/N
0110 = PCIECLKRQ6# (GPIO 45) controls CLKOUT_ITPXDP_P/N
0111 = PCIECLKRQ7# (GPIO 46) controls CLKOUT_ITPXDP_P/N
1000 = PEG_A_CLKRQ# (GPIO47) controls CLKOUT_ITPXDP_P/N
1001 = PEG_B_CLKRQ# (GPIO56)controls CLKOUT_ITPXDP_P/N
1010 – 1111 = RSVD
CLKRQ# Select for CLKOUT_PEG_B_P/N—R/W. Select version of external input
CLKRQ# for dynamic control of the output CLKOUT_PEG_B_P/N.
0000 = PCIECLKRQ0# (GPIO 73) controls CLKOUT_PEG_B_P/N
0001 = PCIECLKRQ1# (GPIO 18) controls CLKOUT_PEG_B_P/N
0010 = PCIECLKRQ2# (GPIO 20) controls CLKOUT_PEG_B_P/N
0011 = PCIECLKRQ3# (GPIO 25) controls CLKOUT_PEG_B_P/N
7:4 0100 = PCIECLKRQ4# (GPIO 26) controls CLKOUT_PEG_B_P/N
0101 = PCIECLKRQ5# (GPIO 44) controls CLKOUT_PEG_B_P/N
0110 = PCIECLKRQ6# (GPIO 45) controls CLKOUT_PEG_B_P/N
0111 = PCIECLKRQ7# (GPIO 46) controls CLKOUT_PEG_B_P/N
1000 = PEG_A_CLKRQ# (GPIO47) controls CLKOUT_PEG_B_P/N
1001 = PEG_B_CLKRQ# (GPIO56)controls CLKOUT_PEG_B_P/N (Default)
1010 – 1111 = RSVD
146 Datasheet
PCH and System Clocks
Bit Description
CLKRQ# Select for CLKOUT_PEG_A_P/N—R/W. Select version of external input
CLKRQ# for dynamic control of the output CLKOUT_PEG_A_P/N.
0000 = PCIECLKRQ0# (GPIO 73) controls CLKOUT_PEG_A_P/N
0001 = PCIECLKRQ1# (GPIO 18) controls CLKOUT_PEG_A_P/N
0010 = PCIECLKRQ2# (GPIO 20) controls CLKOUT_PEG_A_P/N
0011 = PCIECLKRQ3# (GPIO 25) controls CLKOUT_PEG_A_P/N
3:0
0100 = PCIECLKRQ4# (GPIO 26) controls CLKOUT_PEG_A_P/N
0101 = PCIECLKRQ5# (GPIO 44) controls CLKOUT_PEG_A_P/N
0110 = PCIECLKRQ6# (GPIO 45) controls CLKOUT_PEG_A_P/N
0111 = PCIECLKRQ7# (GPIO 46) controls CLKOUT_PEG_A_P/N
1000 = PEG_A_CLKRQ# (GPIO47) controls CLKOUT_PEG_A_P/N (Default)
1001 = PEG_B_CLKRQ# (GPIO56)controls CLKOUT_PEG_A_P/N
1010 – 1111 = RSVD
§§
Datasheet 147
PCH and System Clocks
148 Datasheet
Functional Description
5 Functional Description
This chapter describes the functions and interfaces of the PCH.
5.1 Flexible I/O
The PCH implements Flexible I/O, an architecture to allow some high speed signals to
be configured as PCIe*, USB 3.0 or SATA signals in accordance with I/O needs on a
platform. There are 18 differential pairs that are split between the three interfaces.
Among them, 4 differential pairs are multiplexed: 2 multiplexed differential pairs can
be configured to be used as PCIe port 1, 2 or USB3 port 3, 4, and the other 2
differential pairs can be configured to be used as PCIe port 1, 2 or SATA port 4, 5.
Figure 5-1 below illustrates how the signals are utilized for Flexible I/O.
The Flexible I/O is configured through soft straps. Refer to the latest PCH SPI
Programming Guide Application Note for more detail on the soft strap. These Flexible
I/O ports can be configured in any way as allowed by the soft strap, provided that the
max number of PCIe ports does not exceed 8.
Note: Specifically for the multiplexed differential signal pairs between SATA and PCIe, the
corresponding soft straps provide an option to select desired ports using GPIO16 and
GPIO49. If a GPIO is chosen to select the desired port, the GPIO value needs to be valid
at PLTRST# de-assertion and must be maintained without change while PCH_PLTRST#
remains de-asserted.
Figure 5-1. Flexible I/O – High Speed Signal Mapping with PCI Express*, USB 3.0*, and
SATA Ports
NOTES:
1. USB3Tp3/USB3Tn3 and USB3Rp3/USB3Rn3 signals are multiplexed with PETp1/PETn1 and
PERp1/PERn1 signals respectively.
2. USB3Tp4/USB3Tn4 and USB3Rp4/USB3Rn4 signals are multiplexed with PETp2/PETn2 and
PERp2/PERn2 signals respectively.
3. SATA_TXP4/SATA_TXN4 and SATA_RXP4/SATA_RXN4 signals are multiplexed with PETp1/
PETn1 and PERp1/PERn1 signals respectively.
4. SATA_TXP5/SATA_TXN5 and SATA_RXP5/SATA_RXN5 signals are multiplexed with PETp2/
PETn2 and PERp2/PERn2 signals respectively.
5. The total number of PCIe ports on the platform must not exceed 8. The system designer
needs to take this into account when configuring the flexible I/O on the platform.
Datasheet 149
Functional Description
5.2 PCI-to-PCI Bridge
The PCI-to-PCI bridge resides in PCI. This portion of the PCH implements the buffering
and control logic between PCI and Direct Media Interface (DMI). The arbitration for the
PCI bus is handled by this PCI device. The PCI decoder in this device must decode the
ranges for the DMI. All register contents are lost when core well power is removed.
Direct Media Interface (DMI) is the chip-to-chip connection between the processor and
the PCH. This high-speed interface integrates advanced priority-based servicing
allowing for concurrent traffic and true isochronous transfer capabilities. Base
functionality is completely software transparent permitting current and legacy software
to operate normally.
To provide for true isochronous transfers and configurable Quality of Service (QoS)
transactions, the PCH supports two virtual channels on DMI—VC0 and VC1. These two
channels provide a fixed arbitration scheme where VC1 is always the highest priority.
VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be
specifically enabled and configured at both ends of the DMI link (that is, the PCH and
processor).
Configuration registers for DMI, virtual channel support, and DMI active state power
management (ASPM) are in the RCRB space in the Chipset Config Registers
(Chapter 10).
DMI is also capable of operating in an Enterprise Southbridge Interface (ESI)
compatible mode. ESI is a chip-to-chip connection for server/workstation chipsets. In
this ESI-compatible mode, the DMI signals require AC coupling. A hardware strap is
used to configure DMI in ESI-compatible mode see Section 2.26 for details.
5.2.1 PCI Bus Interface
The PCI Bus Interface is not available on any PCH SKU.
5.2.2 PCI Legacy Mode
PCI functionality is not supported on new generation of PCH requiring methods such as
using PCIe*-to-PCI bridges to enable external PCI I/O devices. To be able to use PCIe-
to-PCI bridges and attached legacy PCI devices, the PCH provides PCI Legacy Mode.
PCI Legacy Mode allows both the PCI Express* root port and PCIe-to-PCI bridge look
like subtractive PCI-to-PCI bridges. This allows the PCI Express root port to
subtractively decode and forward legacy cycles to the bridge, and the PCIe-to-PCI
bridge continues forwarding legacy cycles to downstream PCI devices.
Note: Software must ensure that only one PCH device is enabled for Subtractive decode at a
time.
150 Datasheet
Functional Description
5.3 PCI Express* Root Ports (D28:F0~F7)
There are eight root ports available in the PCH. The root ports are compliant to the PCI
Express 2.0 specification running at 5.0 GT/s. The ports all reside in Device 28, and
take Function 0 – 7. Port 1 is Function 0, Port 2 is Function 1, Port 3 is Function 2,
Port 4 is Function 3, Port 5 is Function 4, Port 6 is Function 5, Port 7 is Function 6, and
Port 8 is Function 7.
Note: This section assumes the default PCI Express Function Number-to-Root Port mapping is
used. Function numbers for a given root port are assignable through the Root Port
Function Number and Hide for PCI Express Root Ports register (RCBA+404h). In
accordance with the PCI Local Bus Specification, all multi-function devices must have a
Function 0 assigned.
5.3.1 Supported PCIe* Port Configurations
PCI Express Root Ports 1–4 or Ports 5–8 can independently be configured as four x1s,
two x2s, one x2 and two x1s, or one x4 port widths, as shown in Table 5-1 and
Table 5-2.
Function disable is covered in Section 10.1.54.
Table 5-1. PCI Express* Ports 1 thru 4 - Supported Configurations
Port 1 Port 2 Port 3 Port 4
x4
x2 x2
x2 x1 x1
x1 x1 x1 x1
Table 5-2. PCI Express* Ports 5 thru 8 - Supported Configurations
Port 5 Port 6 Port 7 Port 8
x4
x2 x2
x2 x1 x1
x1 x1 x1 x1
5.3.2 Interrupt Generation
The root port generates interrupts on behalf of Hot-Plug and power management
events, when enabled. These interrupts can either be pin based, or can be MSIs, when
enabled.
When an interrupt is generated using the legacy pin, the pin is internally routed to the
PCH interrupt controllers. The pin that is driven is based upon the setting of the chipset
configuration registers. Specifically, the chipset configuration registers used are the
D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) registers.
Table 5-3 summarizes interrupt behavior for MSI and wire-modes. In the table “bits”
refers to the Hot-Plug and PME interrupt bits.
Datasheet 151
Functional Description
Table 5-3. MSI versus PCI IRQ Actions
Interrupt Register Wire-Mode Action MSI Action
All bits 0 Wire inactive No action
One or more bits set to 1 Wire active Send message
One or more bits set to 1, new bit gets set to 1 Wire active Send message
One or more bits set to 1, software clears some (but not
Wire active Send message
all) bits
One or more bits set to 1, software clears all bits Wire inactive No action
Software clears one or more bits, and one or more bits
Wire active Send message
are set on the same clock
5.3.3 Power Management
5.3.3.1 S3/S4/S5 Support
Software initiates the transition to S3/S4/S5 by performing an I/O write to the Power
Management Control register in the PCH. After the I/O write completion has been
returned to the processor, each root port will send a PME_Turn_Off TLP (Transaction
Layer Packet) message on its downstream link. The device attached to the link will
eventually respond with a PME_TO_Ack TLP message followed by sending a
PM_Enter_L23 DLLP (Data Link Layer Packet) request to enter the L2/L3 Ready state.
When all of the PCH root ports links are in the L2/L3 Ready state, the PCH power
management control logic will proceed with the entry into S3/S4/S5.
Prior to entering S3, software is required to put each device into D3HOT. When a device
is put into D3HOT, it will initiate entry into a L1 link state by sending a PM_Enter_L1
DLLP. Thus, under normal operating conditions when the root ports sends the
PME_Turn_Off message, the link will be in state L1. However, when the root port is
instructed to send the PME_Turn_Off message, it will send it whether or not the link
was in L1. Endpoints attached to PCH can make no assumptions about the state of the
link prior to receiving a PME_Turn_Off message.
5.3.3.2 Resuming from Suspended State
The root port contains enough circuitry in the suspend well to detect a wake event
through the WAKE# signal and to wake the system. When WAKE# is detected asserted,
an internal signal is sent to the power management controller of the PCH to cause the
system to wake up. This internal message is not logged in any register, nor is an
interrupt/GPE generated due to it.
5.3.3.3 Device Initiated PM_PME Message
When the system has returned to a working state from a previous low power state, a
device requesting service will send a PM_PME message continuously, until
acknowledged by the root port. The root port will take different actions depending upon
whether this is the first PM_PME that has been received, or whether a previous
message has been received but not yet serviced by the operating system.
If this is the first message received (RSTS.PS - D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset
60h:bit 16 is cleared), the root port will set RSTS.PS, and log the PME Requester ID
into RSTS.RID (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 60h:bits 15:0). If an interrupt is
enabled using RCTL.PIE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 5Ch:bit 3), an interrupt
152 Datasheet
Functional Description
will be generated. This interrupt can be either a pin or an MSI if MSI is enabled using
MC.MSIE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 82h:Bit 0). See Section 5.3.3.4 for
SMI/SCI generation.
If this is a subsequent message received (RSTS.PS is already set), the root port will set
RSTS.PP (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 60h:Bit 17) and log the PME Requester
ID from the message in a hidden register. No other action will be taken.
When the first PME event is cleared by software clearing RSTS.PS, the root port will set
RSTS.PS, clear RSTS.PP, and move the requester ID from the hidden register into
RSTS.RID.
If RCTL.PIE is set, an interrupt will be generated. If RCTL.PIE is not set, a message will
be sent to the power management controller so that a GPE can be set. If messages
have been logged (RSTS.PS is set), and RCTL.PIE is later written from a 0 to a 1, an
interrupt will be generated. This last condition handles the case where the message
was received prior to the operating system re-enabling interrupts after resuming from
a low power state.
5.3.3.4 SMI/SCI Generation
Interrupts for power management events are not supported on legacy operating
systems. To support power management on non-PCI Express aware operating systems,
PM events can be routed to generate SCI. To generate SCI, MPC.PMCE must be set.
When set, a power management event will cause SMSCS.PMCS (D28:F0/F1/F2/F3/F4/
F5/F6/F7:Offset DCh:Bit 31) to be set.
Additionally, BIOS workarounds for power management can be supported by setting
MPC.PMME (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset D8h:Bit 0). When this bit is set,
power management events will set SMSCS.PMMS (D28:F0/F1/F2/F3/F4/F5/F6/
F7:Offset DCh:Bit 0), and SMI # will be generated. This bit will be set regardless of
whether interrupts or SCI is enabled. The SMI# may occur concurrently with an
interrupt or SCI.
5.3.3.5 Latency Tolerance Reporting (LTR)
The root port supports the extended Latency Tolerance Reporting (LTR) capability. LTR
provides a means for device endpoints to dynamically report their service latency
requirements for memory access to the root port. Endpoint devices should transmit a
new LTR message to the root port each time its latency tolerance changes (and initially
during boot). The PCH uses the information to make better power management
decision. The processor uses the worst case tolerance value communicated by the PCH
to optimize c-state transitions. This results in better platform power management
without impacting endpoint functionality.
Note: Endpoint devices the support LTR must implement the reporting and enable mechanism
detailed in the PCIe* Latency Tolerance Reporting Engineering Change Notice.
5.3.3.6 Opportunistic Buffer Flush/Fill (OBFF)
The Opportunistic Buffer Flush/Fill (OBFF) capability (also known as Optimized Buffer
Flush/Fill) feature has been dropped from POR in the Series 8 PCH Family and is no
longer supported.
5.3.4 SERR# Generation
SERR# may be generated using two paths – through PCI mechanisms involving bits in
the PCI header, or through PCI Express* mechanisms involving bits in the PCI Express
capability structure.
Datasheet 153
Functional Description
Figure 5-2. Generation of SERR# to Platform
5.3.5 Hot-Plug
Each root port implements a Hot-Plug controller that performs the following:
• Messages to turn on/off/blink LEDs
• Presence and attention button detection
• Interrupt generation
The root port only allows Hot-Plug with modules (such as, ExpressCard*). Edge-
connector based Hot-Plug is not supported.
5.3.5.1 Presence Detection
When a module is plugged in and power is supplied, the physical layer will detect the
presence of the device, and the root port sets SLSTS.PDS (D28:F0/F1/F2/F3/F4/
F5:Offset 5Ah:Bit 6) and SLSTS.PDC (D28:F0/F1/F2/F3:Offset 6h:Bit 3). If SLCTL.PDE
(D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bit 3) and SLCTL.HPE (D28:F0/F1/F2/F3/
F4/F5/F6/F7:Offset 58h:Bit 5) are both set, the root port will also generate an
interrupt.
When a module is removed (using the physical layer detection), the root port clears
SLSTS.PDS and sets SLSTS.PDC. If SLCTL.PDE and SLCTL.HPE are both set, the root
port will also generate an interrupt.
5.3.5.2 Message Generation
When system software writes to SLCTL.AIC (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset
58h:Bits 7:6) or SLCTL.PIC (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bits 9:8), the
root port will send a message down the link to change the state of LEDs on the module.
Writes to these fields are non-postable cycles, and the resulting message is a postable
cycle. When receiving one of these writes, the root port performs the following:
• Changes the state in the register.
• Generates a completion into the upstream queue
• Formulates a message for the downstream port if the field is written to regardless
of if the field changed.
• Generates the message on the downstream port
154 Datasheet
Functional Description
• When the last message of a command is transmitted, sets SLSTS.CCE (D28:F0/F1/
F2/F3/F4/F5/F6/F7:Offset 58h:Bit 4) to indicate the command has completed. If
SLCTL.CCE and SLCTL.HPE (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 58h:Bit 5) are
set, the root port generates an interrupt.
The command completed register (SLSTS.CC) applies only to commands issued by
software to control the Attention Indicator (SLCTL.AIC), Power Indicator (SLCTL.PIC),
or Power Controller (SLCTL.PCC). However, writes to other parts of the Slot Control
Register would invariably end up writing to the indicators and power controller fields.
Hence, any write to the Slot Control Register is considered a command and if enabled,
will result in a command complete interrupt. The only exception to this rule is a write to
disable the command complete interrupt which will not result in a command complete
interrupt.
A single write to the Slot Control register is considered to be a single command, and,
hence, receives a single command complete, even if the write affects more than one
field in the Slot Control Register.
5.3.5.3 Attention Button Detection
When an attached device is ejected, an attention button could be pressed by the user.
This attention button press will result in a the PCI Express* message
“Attention_Button_Pressed” from the device. Upon receiving this message, the root
port will set SLSTS.ABP (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset 5Ah:Bit 0).
If SLCTL.ABE (D28:F0/F1/F2/F3/F4/F5:Offset 58h:bit 0) and SLCTL.HPE (D28:F0/F1/
F2/F3/F4/F5/F6/F7:Offset 58h:Bit 5) are set, the Hot-Plug controller will also generate
an interrupt. The interrupt is generated on an edge-event. For example, if SLSTS.ABP is
already set, a new interrupt will not be generated.
5.3.5.4 SMI/SCI Generation
Interrupts for Hot-Plug events are not supported on legacy operating systems. To
support Hot-Plug on n on-PCI Express aware operating systems, Hot-Plug events can
be routed to generate SCI. To generate SCI, MPC.HPCE (D28:F0/F1/F2/F3/F4/F5/F6/
F7:Offset D8h:Bit 30) must be set. When set, enabled Hot-Plug events will cause
SMSCS.HPCS (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset DCh:Bit 30) to be set.
Datasheet 155
Functional Description
Additionally, BIOS workarounds for Hot-Plug can be supported by setting MPC.HPME
(D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset D8h:Bit 1). When this bit is set, Hot-Plug events
can cause SMI status bits in SMSCS to be set. Supported Hot-Plug events and their
corresponding SMSCS bit are:
• Command Completed – SCSCS.HPCCM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset
DCh:Bit 3)
• Presence Detect Changed – SMSCS.HPPDM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset
DCh:Bit 1)
• Attention Button Pressed – SMSCS.HPABM (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset
DCh:Bit 2)
• Link Active State Changed – SMSCS.HPLAS (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset
DCh:Bit 4)
When any of these bits are set, SMI# will be generated. These bits are set regardless of
whether interrupts or SCI is enabled for Hot-Plug events. The SMI# may occur
concurrently with an interrupt or SCI.
5.4 Gigabit Ethernet Controller (B0:D25:F0)
The PCH integrates a Gigabit Ethernet (GbE) controller. The integrated GbE controller is
compatible with the Intel® Ethernet Network Connection I127LM/V Platform LAN
Connect device. The integrated GbE controller provides two interfaces for 10/100/
1000 Mb/s and manageability operation:
• Based on PCI Express* – A high-speed SerDes interface using PCI Express
electrical signaling at half speed while keeping the custom logical protocol for active
state operation mode.
• System Management Bus (SMBus) SMLink0 – A low speed connection for low power
state mode for manageability communication only. The frequency of this
connection can be configured to one of three different speeds (100KHz, 400KHz or
1MHz). At this low power state mode the Ethernet link speed is reduced to 10 Mb/s.
Note: The SMBus Specification Version 2.0 defines a maximum bus frequency of 100 kHz.
Speeds faster than this are not SMBus compliant and are used by Intel to support
higher bandwidth manageability communication in the Sx states.
The Intel Ethernet Network Connection I127LM/V Platform LAN Connect Device can be
connected to any non-multiplexed (fixed) PCI Express port or the Flexible I/O PCI
Express ports multiplexed with USB 3.0 on the PCH.The Intel Ethernet Network
Connection I127LM/V Platform LAN Connect Device can’t be connected to the PCI
Express Flexible I/O ports multiplexed with SATA.
156 Datasheet
Functional Description
Figure 5-3. Valid PCI Express* Ports for Platform LAN Connect Device (GbE) Support
The Intel Ethernet Network Connection I127LM/V only runs at a speed of 1250 Mb/s,
which is 1/2 of the 2.5 Gb/s PCI Express* frequency. Each of the fixed signal PCI
Express root ports and the Flex I/O PCI Express ports multiplexed with USB 3.0 in the
PCH have the ability to run at the 1250 Mb/s rate. There is no need to implement a
mechanism to detect that the Platform LAN Device is connected. The port configuration
(if any), attached to the Platform LAN Device, is pre-loaded from the NVM. The selected
port adjusts the transmitter to run at the 1250 Mb/s rate and does not need to be PCI
Express compliant.
Note: PCIe validation tools cannot be used for electrical validation of this interface; however,
PCIe layout rules apply for on-board routing.
The integrated GbE controller operates at full-duplex at all supported speeds or half-
duplex at 10/100 Mb/s. It also adheres to the IEEE 802.3x Flow Control Specification.
Note: GbE operation (1000 Mb/s) is only supported in S0 mode. In Sx modes, SMBus is the
only active bus and is used to support manageability/remote wake-up functionality.
The integrated GbE controller provides a system interface using a PCI Express function.
A full memory-mapped or I/O-mapped interface is provided to the software, along with
DMA mechanisms for high performance data transfer.
The integrated GbE controller features are:
• Network Features
— Compliant with the 1 Gb/s Ethernet 802.3, 802.3u, 802.3z, 802.3ab
specifications
— Multi-speed operation: 10/100/1000 Mb/s
— Full-duplex operation at 10/100/1000 Mb/s: Half-duplex at 10/100 Mb/s
— Flow control support compliant with the 802.3X specification as well as the
specific operation of asymmetrical flow control defined by 802.3z
— VLAN support compliant with the 802.3q specification
— MAC address filters: perfect match unicast filters; multicast hash filtering,
broadcast filter and promiscuous mode
— PCI Express/SMBus interface to GbE PHYs
• Host Interface Features
— 64-bit address master support for systems using more than 4 GB of physical
memory
— Programmable host memory receive buffers (256 Bytes to 16 KB)
— Intelligent interrupt generation features to enhance driver performance
Datasheet 157
Functional Description
— Descriptor ring management hardware for transmit and receive
— Software controlled reset (resets everything except the configuration space)
— Message Signaled Interrupts
• Performance Features
— Configurable receive and transmit data FIFO, programmable in 1 KB increments
— TCP segmentation capability compatible with Windows NT* 5.x off loading
features
— Fragmented UDP checksum offload for packet reassembly
— IPv4 and IPv6 checksum offload support (receive, transmit, and TCP
segmentation offload)
— Split header support to eliminate payload copy from user space to host space
— Receive Side Scaling (RSS) with two hardware receive queues
— Supports 9018 bytes of jumbo packets
— Packet buffer size
— LinkSec offload compliant with 802.3ae specification
— TimeSync offload compliant with 802.1as specification
• Virtualization Technology Features
— Warm function reset – function level reset (FLR)
— VMDq1
• Power Management Features
— Magic Packet* wake-up enable with unique MAC address
— ACPI register set and power down functionality supporting D0 and D3 states
— Full wake up support (APM, ACPI)
— MAC power down at Sx, DMoff with and without WoL
— Auto connect battery saver at S0 no link and Sx no link
— Energy Efficient Ethernet (EEE) support
— Latency Tolerance Reporting (LTR)
— ARP and ND proxy support through LAN Connected Device proxy
— Wake on LAN (WoL) from Deep Sx
158 Datasheet
Functional Description
5.4.1 GbE PCI Express* Bus Interface
The GbE controller has a PCI Express interface to the host processor and host memory.
The following sections detail the bus transactions.
5.4.1.1 Transaction Layer
The upper layer of the host architecture is the transaction layer. The transaction layer
connects to the device GbE controller using an implementation specific protocol.
Through this GbE controller-to-transaction-layer protocol, the application-specific parts
of the device interact with the subsystem and transmit and receive requests to or from
the remote agent, respectively.
5.4.1.2 Data Alignment
5.4.1.2.1 4-KB Boundary
PCI requests must never specify an address/length combination that causes a memory
space access to cross a 4 KB boundary. It is hardware’s responsibility to break requests
into 4 KB-aligned requests (if needed). This does not pose any requirement on
software. However, if software allocates a buffer across a 4-KB boundary, hardware
issues multiple requests for the buffer. Software should consider aligning buffers to a
4-KB boundary in cases where it improves performance.
The alignment to the 4-KB boundaries is done by the GbE controller. The transaction
layer does not do any alignment according to these boundaries.
5.4.1.2.2 64 Bytes
PCI requests are 128 bytes or less and are aligned to make better use of memory
controller resources. Writes, however, can be on any boundary and can cross a 64-byte
alignment boundary.
5.4.1.3 Configuration Request Retry Status
The integrated GbE controller might have a delay in initialization due to an NVM read. If
the NVM configuration read operation is not completed and the device receives a
configuration request, the device responds with a configuration request retry
completion status to terminate the request, and thus effectively stalls the configuration
request until such time that the sub-system has completed local initialization and is
ready to communicate with the host.
5.4.2 Error Events and Error Reporting
5.4.2.1 Data Parity Error
The PCI host bus does not provide parity protection, but it does forward parity errors
from bridges. The integrated GbE controller recognizes parity errors through the
internal bus interface and sets the Parity Error bit in PCI configuration space. If parity
errors are enabled in configuration space, a system error is indicated on the PCI host
bus. The offending cycle with a parity error is dropped and not processed by the
integrated GbE controller.
Datasheet 159
Functional Description
5.4.2.2 Completion with Unsuccessful Completion Status
A completion with unsuccessful completion status (any status other than 000) is
dropped and not processed by the integrated GbE controller. Furthermore, the request
that corresponds to the unsuccessful completion is not retried. When this unsuccessful
completion status is received, the System Error bit in the PCI configuration space is set.
If the system errors are enabled in configuration space, a system error is indicated on
the PCI host bus.
5.4.3 Ethernet Interface
The integrated GbE controller provides a complete CSMA/CD function supporting IEEE
802.3 (10 Mb/s), 802.3u (100 Mb/s) implementations. It also supports the IEEE 802.3z
and 802.3ab (1000 Mb/s) implementations. The device performs all of the functions
required for transmission, reception, and collision handling called out in the standards.
The mode used to communicate between the PCH and the Intel® Ethernet Network
Connection I127LM/V Platform LAN Connect Device supports 10/100/1000 Mb/s
operation, with both half- and full-duplex operation at 10/100 Mb/s, and full-duplex
operation at 1000 Mb/s.
5.4.3.1 Intel® Ethernet Network Connection I127LM/V Platform LAN
Connect Device Interface
The integrated GbE controller and the Intel® Ethernet Network Connection I127LM/V
Platform LAN Connect Device communicate through the PCIe and SMLink0 interfaces.
All integrated GbE controller configuration is performed using device control registers
mapped into system memory or I/O space. The Platform LAN Connect Device is
configured using the PCI Express* or SMBus interface.
The integrated GbE controller supports various modes as listed in Table 5-4.
Table 5-4. LAN Mode Support
Mode System State Interface Active Connections
Intel® Ethernet
PCI Express or Network
Normal 10/100/1000 Mb/s S0
SMLink01 Connection
I127LM/V
Intel® Ethernet
Network
Manageability and Remote Wake-up Sx SMLink0
Connection
I127LM/V
NOTES:
1. GbE operation is not supported in Sx states.
160 Datasheet
Functional Description
5.4.4 PCI Power Management
The integrated GbE controller supports the Advanced Configuration and Power Interface
(ACPI) specification as well as Advanced Power Management (APM). This enables the
network-related activity (using an internal host wake signal) to wake up the host. For
example, from Sx (S3–S5) and Deep Sx to S0.
Note: The Intel Ethernet Network Connection I127LM/V Platform LAN Connect Device must
be powered during the Deep Sx state in order to support host wake up from Deep Sx.
GPIO27 on the PCH must be configured to support wake from Deep Sx and must be
connected to LANWAKE_N on the Platform LAN Connect Device. The SLP_LAN# signal
must be driven high (de-asserted) in the Deep Sx state to maintain power to the
Platform LAN Connect Device.
The integrated GbE controller contains power management registers for PCI and
supports D0 and D3 states. PCIe* transactions are only allowed in the D0 state, except
for host accesses to the integrated GbE controller’s PCI configuration registers.
5.4.4.1 Wake Up
The integrated GbE controller supports two types of wake-up mechanisms:
1. Advanced Power Management (APM) Wake Up
2. ACPI Power Management Wake Up
Both mechanisms use an internal logic signal to wake the system up. The wake-up
steps are as follows:
1. Host wake event occurs (packet is not delivered to host).
2. The Platform LAN Connect Device receives a WoL packet/link status change.
3. The Platform LAN Connect Device sends a wake indication to the PCH (this requires
the LANWAKE_N pin from the Intel® Ethernet Network Connection I127LM/V
Platform LAN Connect Device to be connected to the PCH GPIO27 pin. GPIO27 must
also be configured to support wake from Deep Sx.
4. If the system is in Deep Sx the wake will cause the system to wake from the Deep
Sx state to the Sx state.
5. The Platform LAN Connect Device wakes up the integrated GbE controller using an
SMBus message on SMLink0.
6. The integrated GbE controller sets the PME_STATUS bit.
7. System wakes from Sx state to S0 state.
8. The host LAN function is transitioned to D0.
9. The host clears the PME_STATUS bit.
5.4.4.1.1 Advanced Power Management Wake Up
Advanced Power Management Wake Up or APM Wake Up was previously known as
Wake on LAN (WoL). It is a feature that has existed in the 10/100 Mb/s NICs for several
generations. The basic premise is to receive a broadcast or unicast packet with an
explicit data pattern and then to assert a signal to wake up the system. In earlier
generations, this was accomplished by using a special signal that ran across a cable to
a defined connector on the motherboard. The NIC would assert the signal for
approximately 50 ms to signal a wake up. The integrated GbE controller uses (if
configured to) an in-band PM_PME message for this.
Datasheet 161
Functional Description
At power up, the integrated GbE controller reads the APM Enable bits from the NVM PCI
Init Control Word into the APM Enable (APME) bits of the Wake Up Control (WUC)
register. These bits control enabling of APM wake up.
When APM wake up is enabled, the integrated GbE controller checks all incoming
packets for Magic Packets.
Once the integrated GbE controller receives a matching Magic Packet, it:
• Sets the Magic Packet Received bit in the Wake Up Status (WUS) register.
• Sets the PME_Status bit in the Power Management Control/Status Register
(PMCSR).
APM wake up is supported in all power states and only disabled if a subsequent NVM
read results in the APM Wake Up bit being cleared or the software explicitly writes a 0b
to the APM Wake Up (APM) bit of the WUC register.
Note: APM wake up settings will be restored to NVM default by the PCH when LAN connected
Device (PHY) power is turned off and subsequently restored. Some example host WoL
flows are:
• When system transitions to G3 after WoL is disabled from the BIOS, APM host WoL
would get enabled.
• Anytime power to the LAN Connected Device (PHY) is cycled while in S4/S5 after
WoL is disabled from the BIOS, APM host WoL would get enabled. Anytime power to
the LAN Connected Device (PHY) is cycled while in S3, APM host WoL configuration
is lost.
5.4.4.1.2 ACPI Power Management Wake Up
The integrated GbE controller supports ACPI Power Management based Wake ups. It
can generate system wake-up events from three sources:
• Receiving a Magic Packet*.
• Receiving a Network Wake Up Packet.
• Detecting a link change of state.
Activating ACPI Power Management Wakeup requires the following steps:
• The software device driver programs the Wake Up Filter Control (WUFC) register to
indicate the packets it needs to wake up from and supplies the necessary data to
the IPv4 Address Table (IP4AT) and the Flexible Filter Mask Table (FFMT), Flexible
Filter Length Table (FFLT), and the Flexible Filter Value Table (FFVT). It can also set
the Link Status Change Wake Up Enable (LNKC) bit in the Wake Up Filter Control
(WUFC) register to cause wake up when the link changes state.
• The operating system (at configuration time) writes a 1b to the PME_EN bit of the
Power Management Control/Status Register (PMCSR.8).
Normally, after enabling wake up, the operating system writes a 11b to the lower two
bits of the PMCSR to put the integrated GbE controller into low-power mode.
Once wake up is enabled, the integrated GbE controller monitors incoming packets,
first filtering them according to its standard address filtering method, then filtering
them with all of the enabled wake-up filters. If a packet passes both the standard
address filtering and at least one of the enabled wake-up filters, the integrated GbE
controller:
• Sets the PME_Status bit in the PMCSR
• Sets one or more of the Received bits in the Wake Up Status (WUS) register. (More
than one bit is set if a packet matches more than one filter.)
162 Datasheet
Functional Description
If enabled, a link state change wake up causes similar results, setting the Link Status
Changed (LNKC) bit in the Wake Up Status (WUS) register when the link goes up or
down.
After receiving a wake-up packet, the integrated GbE controller ignores any subsequent
wake-up packets until the software device driver clears all of the Received bits in the
Wake Up Status (WUS) register. It also ignores link change events until the software
device driver clears the Link Status Changed (LNKC) bit in the Wake Up Status (WUS)
register.
Note: ACPI wake up settings are not preserved when the LAN Connected Device (PHY) power
is turned off and subsequently restored. Some example host WoL flows are:
• Anytime power to the LAN Connected Device (PHY) is cycled while in S3 or S4,
ACPI host WoL configuration is lost.
5.4.5 Configurable LEDs
The integrated GbE controller supports three controllable and configurable LEDs that
are driven from the Intel® Ethernet Network Connection I127LM/V Platform LAN
Connect Device. Each of the three LED outputs can be individually configured to select
the particular event, state, or activity that is indicated on that output. In addition, each
LED can be individually configured for output polarity as well as for blinking versus non-
blinking (steady-state) indication.
The configuration for LED outputs is specified using the LEDCTL register. Furthermore,
the hardware-default configuration for all the LED outputs, can be specified using NVM
fields; thereby, supporting LED displays configurable to a particular OEM preference.
Each of the three LEDs might be configured to use one of a variety of sources for output
indication. The MODE bits control the LED source:
• LINK_100/1000 is asserted when link is established at either 100 or 1000 Mb/s.
• LINK_10/1000 is asserted when link is established at either 10 or 1000 Mb/s.
• LINK_UP is asserted when any speed link is established and maintained.
• ACTIVITY is asserted when link is established and packets are being transmitted or
received.
• LINK/ACTIVITY is asserted when link is established AND there is NO transmit or
receive activity.
• LINK_10 is asserted when a 10 Mb/s link is established and maintained.
• LINK_100 is asserted when a 100 Mb/s link is established and maintained.
• LINK_1000 is asserted when a 1000 Mb/s link is established and maintained.
• FULL_DUPLEX is asserted when the link is configured for full duplex operation.
• COLLISION is asserted when a collision is observed.
• PAUSED is asserted when the device's transmitter is flow controlled.
• LED_ON is always asserted; LED_OFF is always de-asserted.
The IVRT bits enable the LED source to be inverted before being output or observed by
the blink-control logic. LED outputs are assumed to normally be connected to the
negative side (cathode) of an external LED.
Datasheet 163
Functional Description
The BLINK bits control whether the LED should be blinked while the LED source is
asserted, and the blinking frequency (either 200 ms on and 200 ms off or 83 ms on and
83 ms off). The blink control can be especially useful for ensuring that certain events,
such as ACTIVITY indication, cause LED transitions, which are sufficiently visible to a
human eye. The same blinking rate is shared by all LEDs.
5.4.6 Function Level Reset Support (FLR)
The integrated GbE controller supports FLR capability. FLR capability can be used in
conjunction with Intel® Virtualization Technology. FLR allows an operating system in a
Virtual Machine to have complete control over a device, including its initialization,
without interfering with the rest of the platform. The device provides a software
interface that enables the operating system to reset the entire device as if a PCI reset
was asserted.
5.4.6.1 FLR Steps
5.4.6.1.1 FLR Initialization
1. FLR is initiated by software by writing a 1b to the Initiate FLR bit.
2. All subsequent requests targeting the function are not claimed and will be master
aborted immediately on the bus. This includes any configuration, I/O or memory
cycles. However, the function will continue to accept completions targeting the
function.
5.4.6.1.2 FLR Operation
Function resets all configuration, I/O, and memory registers of the function except
those indicated otherwise and resets all internal states of the function to the default or
initial condition.
5.4.6.1.3 FLR Completion
The Initiate FLR bit is reset (cleared) when the FLR reset completes. This bit can be
used to indicate to the software that the FLR reset completed.
Note: From the time the Initiate FLR bit is written to 1b, software must wait at least 100 ms
before accessing the function.
164 Datasheet
Functional Description
5.5 Low Pin Count (LPC) Bridge (with System and
Management Functions) (D31:F0)
The LPC bridge function of the PCH resides in PCI D31:F0. In addition to the LPC bridge
function, D31:F0 contains other functional units including DMA, Interrupt controllers,
Timers, Power Management, System Management, GPIO, and RTC. In this chapter,
registers and functions associated with other functional units (power management,
GPIO, USB, and so on) are described in their respective sections.
Note: The LPC bridge cannot be configured as a subtractive decode agent.
5.5.1 LPC Interface
The PCH implements an LPC interface as described in the Low Pin Count Interface
Specification, Revision 1.1. The LPC interface to the PCH is shown in Figure 5-4. The
PCH implements all of the signals that are shown as optional, but peripherals are not
required to do so.
Figure 5-4. LPC Interface Diagram
5.5.1.1 LPC Cycle Types
The PCH implements all of the cycle types described in the Low Pin Count Interface
Specification, Revision 1.1. Table 5-5 shows the cycle types supported by the PCH.
Table 5-5. LPC Cycle Types Supported
Cycle Type Comment
Memory Read 1 byte only. (See Note 1 below)
Memory Write 1 byte only. (See Note 1 below)
1 byte only. The PCH breaks up 16-bit and 32-bit processor cycles into
I/O Read
multiple 8-bit transfers.
1 byte only. The PCH breaks up 16-bit and 32-bit processor cycles into
I/O Write
multiple 8-bit transfers.
DMA Read Can be 1 or 2 bytes
Datasheet 165
Functional Description
Table 5-5. LPC Cycle Types Supported
Cycle Type Comment
DMA Write Can be 1 or 2 bytes
Bus Master Read Can be 1, 2 or 4 bytes. (See Note 2 below)
Bus Master Write Can be 1, 2 or 4 bytes. (See Note 2 below)
NOTES:
1. The PCH provides a single generic memory range (LGMR) for decoding memory cycles and
forwarding them as LPC Memory cycles on the LPC bus. The LGMR memory decode range is
64 KB in size and can be defined as being anywhere in the 4 GB memory space. This range
needs to be configured by BIOS during POST to provide the necessary memory resources.
BIOS should advertise the LPC Generic Memory Range as Reserved to the OS in order to
avoid resource conflict. For larger transfers, the PCH performs multiple 8-bit transfers. If the
cycle is not claimed by any peripheral, it is subsequently aborted, and the PCH returns a
value of all 1s to the processor. This is done to maintain compatibility with ISA memory
cycles where pull-up resistors would keep the bus high if no device responds.
2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer
can be to any address. However, the 2-byte transfer must be word-aligned (that is, with an
address where A0=0). A DWord transfer must be DWord-aligned (that is, with an address
where A1 and A0 are both 0).
5.5.1.2 Start Field Definition
Table 5-6. Start Field Bit Definitions
Bits 3:0
Definition
Encoding
0000 Start of cycle for a generic target
0010 Grant for bus master 0
0011 Grant for bus master 1
1111 Stop/Abort: End of a cycle for a target.
NOTE: All other encodings are RESERVED.
5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR)
The PCH always drives Bit 0 of this field to 0. Peripherals running bus master cycles
must also drive Bit 0 to 0. Table 5-7 shows the valid bit encodings.
Table 5-7. Cycle Type Bit Definitions
Bits 3:2 Bit 1 Definition
00 0 I/O Read
00 1 I/O Write
01 0 Memory Read
01 1 Memory Read
10 0 DMA Read
10 1 DMA Write
Reserved. If a peripheral performing a bus master cycle generates this
11 x
value, the PCH aborts the cycle.
166 Datasheet
Functional Description
5.5.1.4 Size
Bits[3:2] are reserved. The PCH always drives them to 00. Peripherals running bus
master cycles are also supposed to drive 00 for Bits 3:2; however, the PCH ignores
those bits. Bits[1:0] are encoded as listed in Table 5-8.
Table 5-8. Transfer Size Bit Definition
Bits 1:0 Size
00 8-bit transfer (1 byte)
01 16-bit transfer (2 bytes)
Reserved. The PCH never drives this combination. If a peripheral running a bus
10
master cycle drives this combination, the PCH may abort the transfer.
11 32-bit transfer (4 bytes)
5.5.1.5 SYNC
Valid values for the SYNC field are shown in Table 5-9.
Table 5-9. SYNC Bit Definition
Bits 3:0 Indication
Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA
0000
request de-assertion and no more transfers desired for that channel.
Short Wait: Part indicating wait-states. For bus master cycles, the PCH does not
0101 use this encoding. Instead, the PCH uses the Long Wait encoding (see next encoding
below).
Long Wait: Part indicating wait-states, and many wait-states will be added. This
0110 encoding driven by the PCH for bus master cycles, rather than the Short Wait
(0101).
Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no
1001 error and more DMA transfers desired to continue after this transfer. This value is
valid only on DMA transfers and is not allowed for any other type of cycle.
Error: Sync achieved with error. This is generally used to replace the SERR# or
IOCHK# signal on the PCI/ISA bus. It indicates that the data is to be transferred,
1010 but there is a serious error in this transfer. For DMA transfers, this not only indicates
an error, but also indicates DMA request de-assertion and no more transfers desired
for that channel.
NOTES:
1. All other combinations are RESERVED.
2. If the LPC controller receives any SYNC returned from the device other than short (0101),
long wait (0110), or ready (0000) when running a FWH cycle, indeterminate results may
occur. A FWH device is not allowed to assert an Error SYNC.
5.5.1.6 SYNC Time-Out
There are several error cases that can occur on the LPC interface. The PCH responds as
defined in Section 4.2.1.9 of the Low Pin Count Interface Specification, Revision 1.1 to
the stimuli described therein. There may be other peripheral failure conditions;
however, these are not handled by the PCH.
Datasheet 167
Functional Description
5.5.1.7 SYNC Error Indication
The PCH responds as defined in Section 4.2.1.10 of the Low Pin Count Interface
Specification, Revision 1.1.
Upon recognizing the SYNC field indicating an error, the PCH treats this as a SERR by
reporting this into the Device 31 Error Reporting Logic.
5.5.1.8 LFRAME# Usage
The PCH follows the usage of LFRAME# as defined in the Low Pin Count Interface
Specification, Revision 1.1.
The PCH performs an abort for the following cases (possible failure cases):
• The PCH starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC
after four consecutive clocks.
• The PCH starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid
SYNC pattern.
• A peripheral drives an illegal address when performing bus master cycles.
• A peripheral drives an invalid value.
5.5.1.9 I/O Cycles
For I/O cycles targeting registers specified in the PCH’s decode ranges, the PCH
performs I/O cycles as defined in the Low Pin Count Interface Specification, Revision
1.1. These are 8-bit transfers. If the processor attempts a 16-bit or 32-bit transfer, the
PCH breaks the cycle up into multiple 8-bit transfers to consecutive I/O addresses.
Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the PCH
returns a value of all 1s (FFh) to the processor. This is to maintain compatibility with
ISA I/O cycles where pull-up resistors would keep the bus high if no device responds.
5.5.1.10 Bus Master Cycles
The PCH supports Bus Master cycles and requests (using LDRQ#) as defined in the Low
Pin Count Interface Specification, Revision 1.1. The PCH has two LDRQ# inputs, and
thus supports two separate bus master devices. It uses the associated START fields for
Bus Master 0 (0010b) or Bus Master 1 (0011b).
Note: The PCH does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters
should only perform memory read or memory write cycles.
5.5.1.11 LPC Power Management
LPCPD# Protocol
Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals drive
LDRQ# low or tri-state it. The PCH shuts off the LDRQ# input buffers. After driving
SUS_STAT# active, the PCH drives LFRAME# low, and tri-states (or drives low)
LAD[3:0].
Note: The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol
where there is at least 30 µs from LPCPD# assertion to LRST# assertion. This
specification explicitly states that this protocol only applies to entry/exit of low power
states which does not include asynchronous reset events. The PCH asserts both
SUS_STAT# (connects to LPCPD#) and PLTRST# (connects to LRST#) at the same time
during a global reset. This is not inconsistent with the LPC LPCPD# protocol.
168 Datasheet
Functional Description
5.5.1.12 Configuration and PCH Implications
LPC I/F Decoders
To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the PCH
includes several decoders. During configuration, the PCH must be programmed with the
same decode ranges as the peripheral. The decoders are programmed using the D
31:F0 configuration space.
Note: The PCH cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar
characteristics (specifically those with a “Retry Read” feature which is enabled) to an
LPC device if there is an outstanding LPC read cycle towards the same PCI device or
bridge. These cycles are not part of normal system operation, but may be encountered
as part of platform validation testing using custom test fixtures.
Bus Master Device Mapping and START Fields
Bus Masters must have a unique START field. In the case of the PCH that supports two
LPC bus masters, it drives 0010 for the START field for grants to Bus Master 0
(requested using LDRQ0#) and 0011 for grants to Bus Master 1 (requested using
LDRQ1#.). Thus, no registers are needed to configure the START fields for a particular
bus master.
Datasheet 169
Functional Description
5.6 DMA Operation (D31:F0)
The PCH supports LPC DMA using the PCH’s DMA controller. The DMA controller has
registers that are fixed in the lower 64 KB of I/O space. The DMA controller is
configured using registers in the PCI configuration space. These registers allow
configuration of the channels for use by LPC DMA.
The DMA circuitry incorporates the functionality of two 8237 DMA controllers with
seven independently programmable channels (Figure 5-5). DMA Controller 1 (DMA-1)
corresponds to DMA Channels 0–3 and DMA Controller 2 (DMA-2) corresponds to
Channels 5–7. DMA Channel 4 is used to cascade the two controllers and defaults to
cascade mode in the DMA Channel Mode (DCM) Register. Channel 4 is not available for
any other purpose. In addition to accepting requests from DMA slaves, the DMA
controller also responds to requests that software initiates. Software may initiate a
DMA service request by setting any bit in the DMA Channel Request Register to a 1.
Floppy disk is not supported (or validated) in this PCH.
Figure 5-5. PCH DMA Controller
Channel 4
Channel 0
Channel 1 Channel 5
DMA-1 DMA-2
Channel 2 Channel 6
Channel 3 Channel 7
Each DMA channel is hardwired to the compatible settings for DMA device size:
Channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and Channels [7:5]
are hardwired to 16-bit, count-by-words (address shifted) transfers.
The PCH provides 24-bit addressing in compliance with the ISA-Compatible
specification. Each channel includes a 16-bit ISA-Compatible Current Register which
holds the sixteen least-significant bits of the 24-bit address, an ISA-Compatible Page
Register which contains the eight next most significant bits of address.
The DMA controller also features refresh address generation, and auto-initialization
following a DMA termination.
5.6.1 Channel Priority
For priority resolution, the DMA consists of two logical channel groups: Channels 0–3
and Channels 4–7. Each group may be in either fixed or rotate mode, as determined by
the DMA Command Register.
DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However,
a software request for DMA service can be presented through each channel's DMA
Request Register. A software request is subject to the same prioritization as any
hardware request. See the detailed register description for Request Register
programming information in Section 12.2.
5.6.1.1 Fixed Priority
The initial fixed priority structure is as follows:
High priority Low priority
0, 1, 2, 3 5, 6, 7
170 Datasheet
Functional Description
The fixed priority ordering is 0, 1, 2, 3, 5, 6, and 7. In this scheme, channel 0 has the
highest priority, and channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume
the priority position of channel 4 in DMA-2, thus taking priority over Channels 5, 6,
and 7.
5.6.1.2 Rotating Priority
Rotation allows for “fairness” in priority resolution. The priority chain rotates so that the
last channel serviced is assigned the lowest priority in the channel group (0–3, 5–7).
Channels 0–3 rotate as a group of 4. They are always placed between Channel 5 and
Channel 7 in the priority list.
Channel 5–7 rotate as part of a group of 4. That is, Channels (5–7) form the first three
positions in the rotation, while Channel Group (0–3) comprises the fourth position in
the arbitration.
5.6.2 Address Compatibility Mode
When the DMA is operating, the addresses do not increment or decrement through the
High and Low Page Registers. Therefore, if a 24-bit address is 01FFFFh and increments,
the next address is 010000h, not 020000h. Similarly, if a 24-bit address is 020000h
and decrements, the next address is 02FFFFh, not 01FFFFh. However, when the DMA is
operating in 16-bit mode, the addresses still do not increment or decrement through
the High and Low Page Registers but the page boundary is now 128 K. Therefore, if a
24-bit address is 01FFFEh and increments, the next address is 000000h, not
0100000h. Similarly, if a 24-bit address is 020000h and decrements, the next address
is 03FFFEh, not 02FFFEh. This is compatible with the 8237 and Page Register
implementation used in the PC-AT. This mode is set after CPURST is valid.
5.6.3 Summary of DMA Transfer Sizes
Table 5-10 lists each of the DMA device transfer sizes. The column labeled “Current
Byte/Word Count Register” indicates that the register contents represents either the
number of bytes to transfer or the number of 16-bit words to transfer. The column
labeled “Current Address Increment/Decrement” indicates the number added to or
taken from the Current Address register after each DMA transfer cycle. The DMA
Channel Mode Register determines if the Current Address Register will be incremented
or decremented.
5.6.3.1 Address Shifting When Programmed for 16-Bit I/O Count
by Words
Table 5-10. DMA Transfer Size
Current Address
Current Byte/Word
DMA Device Date Size And Word Count Increment /
Count Register
Decrement
8-Bit I/O, Count By Bytes Bytes 1
16-Bit I/O, Count By Words (Address
Words 1
Shifted)
The PCH maintains compatibility with the implementation of the DMA in the PC AT that
used the 8237. The DMA shifts the addresses for transfers to/from a 16-bit device
count-by-words.
Datasheet 171
Functional Description
Note: The least significant bit of the Low Page Register is dropped in 16-bit shifted mode.
When programming the Current Address Register (when the DMA channel is in this
mode), the Current Address must be programmed to an even address with the address
value shifted right by one bit.
The address shifting is shown in Table 5-11.
Table 5-11. Address Shifting in 16-Bit I/O DMA Transfers
16-Bit I/O Programmed
Output 8-Bit I/O Programmed
Address (Ch 5–7)
Address Address (Ch 0–3)
(Shifted)
A0 A0 0
A[16:1] A[16:1] A[15:0]
A[23:17] A[23:17] A[23:17]
NOTE: The least significant bit of the Page Register is dropped in 16-bit shifted mode.
5.6.4 Autoinitialize
By programming a bit in the DMA Channel Mode Register, a channel may be set up as
an autoinitialize channel. When a channel undergoes autoinitialization, the original
values of the Current Page, Current Address and Current Byte/Word Count Registers
are automatically restored from the Base Page, Address, and Byte/Word Count
Registers of that channel following Terminal Count (TC). The Base Registers are loaded
simultaneously with the Current Registers by the microprocessor when the DMA
channel is programmed and remain unchanged throughout the DMA service. The mask
bit is not set when the channel is in autoinitialize. Following autoinitialize, the channel
is ready to perform another DMA service, without processor intervention, as soon as a
valid DREQ is detected.
5.6.5 Software Commands
There are three additional special software commands that the DMA controller can
execute. The three software commands are:
• Clear Byte Pointer Flip-Flop
• Master Clear
• Clear Mask Register
They do not depend on any specific bit pattern on the data bus.
172 Datasheet
Functional Description
5.7 Low Pin Count (LPC) DMA
DMA on LPC is handled through the use of the LDRQ# lines from peripherals and
special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment
modes are supported on the LPC interface. Channels 0–3 are 8-bit channels. Channels
5–7 are 16-bit channels. Channel 4 is reserved as a generic bus master request.
5.7.1 Asserting DMA Requests
Peripherals that need DMA service encode their requested channel number on the
LDRQ# signal. To simplify the protocol, each peripheral on the LPC I/F has its own
dedicated LDRQ# signal (they may not be shared between two separate peripherals).
The PCH has two LDRQ# inputs, allowing at least two devices to support DMA or bus
mastering.
LDRQ# is synchronous with LCLK (PCI clock). As shown in Figure 5-6, the peripheral
uses the following serial encoding sequence:
• Peripheral starts the sequence by asserting LDRQ# low (start bit). LDRQ# is high
during idle conditions.
• The next three bits contain the encoded DMA channel number (MSB first).
• The next bit (ACT) indicates whether the request for the indicated DMA channel is
active or inactive. The ACT bit is 1 (high) to indicate if it is active and 0 (low) if it is
inactive. The case where ACT is low is rare, and is only used to indicate that a
previous request for that channel is being abandoned.
• After the active/inactive indication, the LDRQ# signal must go high for at least one
clock. After that one clock, LDRQ# signal can be brought low to the next encoding
sequence.
If another DMA channel also needs to request a transfer, another sequence can be sent
on LDRQ#. For example, if an encoded request is sent for Channel 2, and then Channel
3 needs a transfer before the cycle for Channel 2 is run on the interface, the peripheral
can send the encoded request for Channel 3. This allows multiple DMA agents behind
an I/O device to request use of the LPC interface, and the I/O device does not need to
self-arbitrate before sending the message.
Figure 5-6. DMA Request Assertion through LDRQ#
LCLK
LDRQ#
Start MSB LSB ACT Start
Datasheet 173
Functional Description
5.7.2 Abandoning DMA Requests
DMA Requests can be de-asserted in two fashions: on error conditions by sending an
LDRQ# message with the ‘ACT’ bit set to 0, or normally through a SYNC field during the
DMA transfer. This section describes boundary conditions where the DMA request needs
to be removed prior to a data transfer.
There may be some special cases where the peripheral desires to abandon a DMA
transfer. The most likely case of this occurring is due to a floppy disk controller which
has overrun or underrun its FIFO, or software stopping a device prematurely.
In these cases, the peripheral wishes to stop further DMA activity. It may do so by
sending an LDRQ# message with the ACT bit as 0. However, since the DMA request was
seen by the PCH, there is no assurance that the cycle has not been granted and will
shortly run on LPC. Therefore, peripherals must take into account that a DMA cycle may
still occur. The peripheral can choose not to respond to this cycle, in which case the
host will abort it, or it can choose to complete the cycle normally with any random data.
This method of DMA de-assertion should be prevented whenever possible, to limit
boundary conditions both on the PCH and the peripheral.
5.7.3 General Flow of DMA Transfers
Arbitration for DMA channels is performed through the 8237 within the host. Once the
host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts
LFRAME# on the LPC I/F and begins the DMA transfer. The general flow for a basic DMA
transfer is as follows:
1. The PCH starts transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted.
2. The PCH asserts ‘cycle type’ of DMA, direction based on DMA transfer direction.
3. The PCH asserts channel number and, if applicable, terminal count.
4. The PCH indicates the size of the transfer: 8 or 16 bits.
5. If a DMA read…
— The PCH drives the first 8 bits of data and turns the bus around.
— The peripheral acknowledges the data with a valid SYNC.
— If a 16-bit transfer, the process is repeated for the next 8 bits.
6. If a DMA write…
— The PCH turns the bus around and waits for data.
— The peripheral indicates data ready through SYNC and transfers the first byte.
— If a 16-bit transfer, the peripheral indicates data ready and transfers the next
byte.
7. The peripheral turns around the bus.
5.7.4 Terminal Count
Terminal count is communicated through LAD[3] on the same clock that DMA channel is
communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates
the last byte of transfer, based upon the size of the transfer.
For example, on an 8-bit transfer size (SIZE field is 00b), if the TC bit is set, then this is
the last byte. On a 16-bit transfer (SIZE field is 01b), if the TC bit is set, then the
second byte is the last byte. The peripheral, therefore, must internalize the TC bit when
the CHANNEL field is communicated, and only signal TC when the last byte of that
transfer size has been transferred.
174 Datasheet
Functional Description
5.7.5 Verify Mode
Verify mode is supported on the LPC interface. A verify transfer to the peripheral is
similar to a DMA write, where the peripheral is transferring data to main memory. The
indication from the host is the same as a DMA write, so the peripheral will be driving
data onto the LPC interface. However, the host will not transfer this data into main
memory.
5.7.6 DMA Request De-assertion
An end of transfer is communicated to the PCH through a special SYNC field
transmitted by the peripheral. An LPC device must not attempt to signal the end of a
transfer by de-asserting LDREQ#. If a DMA transfer is several bytes (such as, a transfer
from a demand mode device) the PCH needs to know when to de-assert the DMA
request based on the data currently being transferred.
The DMA agent uses a SYNC encoding on each byte of data being transferred, which
indicates to the PCH whether this is the last byte of transfer or if more bytes are
requested. To indicate the last byte of transfer, the peripheral uses a SYNC value of
0000b (ready with no error), or 1010b (ready with error). These encodings tell the PCH
that this is the last piece of data transferred on a DMA read (PCH to peripheral), or the
byte that follows is the last piece of data transferred on a DMA write (peripheral to the
PCH).
When the PCH sees one of these two encodings, it ends the DMA transfer after this byte
and de-asserts the DMA request to the 8237. Therefore, if the PCH indicated a 16-bit
transfer, the peripheral can end the transfer after one byte by indicating a SYNC value
of 0000b or 1010b. The PCH does not attempt to transfer the second byte, and de-
asserts the DMA request internally.
If the peripheral indicates a 0000b or 1010b SYNC pattern on the last byte of the
indicated size, then the PCH only de-asserts the DMA request to the 8237 since it does
not need to end the transfer.
If the peripheral wishes to keep the DMA request active, then it uses a SYNC value of
1001b (ready plus more data). This tells the 8237 that more data bytes are requested
after the current byte has been transferred, so the PCH keeps the DMA request active
to the 8237. Therefore, on an 8-bit transfer size, if the peripheral indicates a SYNC
value of 1001b to the PCH, the data will be transferred and the DMA request will remain
active to the 8237. At a later time, the PCH will then come back with another START–
CYCTYPE–CHANNEL–SIZE and so on combination to initiate another transfer to the
peripheral.
The peripheral must not assume that the next START indication from the PCH is
another grant to the peripheral if it had indicated a SYNC value of 1001b. On a single
mode DMA device, the 8237 will re-arbitrate after every transfer. Only demand mode
DMA devices can be assured that they will receive the next START indication from the
PCH.
Note: Indicating a 0000b or 1010b encoding on the SYNC field of an odd byte of a 16-bit
channel (first byte of a 16-bit transfer) is an error condition.
Note: The host stops the transfer on the LPC bus as indicated, fills the upper byte with
random data on DMA writes (peripheral to memory), and indicates to the 8237 that the
DMA transfer occurred, incrementing the 8237’s address and decrementing its byte
count.
Datasheet 175
Functional Description
5.7.7 SYNC Field / LDRQ# Rules
Since DMA transfers on LPC are requested through an LDRQ# assertion message, and
are ended through a SYNC field during the DMA transfer, the peripheral must obey the
following rule when initiating back-to-back transfers from a DMA channel.
The peripheral must not assert another message for eight LCLKs after a de-assertion is
indicated through the SYNC field. This is needed to allow the 8237, that typically runs
off a much slower internal clock, to see a message de-asserted before it is re-asserted
so that it can arbitrate to the next agent.
Under default operation, the host only performs 8-bit transfers on 8-bit channels and
16-bit transfers on 16-bit channels.
The method by which this communication between host and peripheral through system
BIOS is performed is beyond the scope of this specification. Since the LPC host and LPC
peripheral are motherboard devices, no “plug-n-play” registry is required.
The peripheral must not assume that the host is able to perform transfer sizes that are
larger than the size allowed for the DMA channel, and be willing to accept a SIZE field
that is smaller than what it may currently have buffered.
To that end, it is recommended that future devices that may appear on the LPC bus,
that require higher bandwidth than 8-bit or 16-bit DMA allow, do so with a bus
mastering interface and not rely on the 8237.
5.8 8254 Timers (D31:F0)
The PCH contains three counters that have fixed uses. All registers and functions
associated with the 8254 timers are in the core well. The 8254 unit is clocked by a
14.318 MHz clock.
Counter 0, System Timer
This counter functions as the system timer by controlling the state of IRQ0 and is
typically programmed for Mode 3 operation. The counter produces a square wave with
a period equal to the product of the counter period (838 ns) and the initial count value.
The counter loads the initial count value 1 counter period after software writes the
count value to the counter I/O address. The counter initially asserts IRQ0 and
decrements the count value by two each counter period. The counter negates IRQ0
when the count value reaches 0. It then reloads the initial count value and again
decrements the initial count value by two each counter period. The counter then
asserts IRQ0 when the count value reaches 0, reloads the initial count value, and
repeats the cycle, alternately asserting and negating IRQ0.
Counter 1, Refresh Request Signal
This counter provides the refresh request signal and is typically programmed for Mode
2 operation and only impacts the period of the REF_TOGGLE bit in Port 61. The initial
count value is loaded one counter period after being written to the counter I/O address.
The REF_TOGGLE bit will have a square wave behavior (alternate between 0 and 1) and
will toggle at a rate based on the value in the counter. Programming the counter to
anything other than Mode 2 will result in undefined behavior for the REF_TOGGLE bit.
Counter 2, Speaker Tone
This counter provides the speaker tone and is typically programmed for Mode 3
operation. The counter provides a speaker frequency equal to the counter clock
frequency (1.193 MHz) divided by the initial count value. The speaker must be enabled
by a write to port 061h (see NMI Status and Control ports).
176 Datasheet
Functional Description
5.8.1 Timer Programming
The counter/timers are programmed in the following fashion:
1. Write a control word to select a counter.
2. Write an initial count for that counter.
3. Load the least and/or most significant bytes (as required by Control Word Bits 5, 4)
of the 16-bit counter.
4. Repeat with other counters.
Only two conventions need to be observed when programming the counters. First, for
each counter, the control word must be written before the initial count is written.
Second, the initial count must follow the count format specified in the control word
(least significant byte only, most significant byte only, or least significant byte and then
most significant byte).
A new initial count may be written to a counter at any time without affecting the
counter's programmed mode. Counting is affected as described in the mode definitions.
The new count must follow the programmed count format.
If a counter is programmed to read/write two-byte counts, the following precaution
applies: A program must not transfer control between writing the first and second byte
to another routine which also writes into that same counter. Otherwise, the counter will
be loaded with an incorrect count.
The Control Word Register at port 43h controls the operation of all three counters.
Several commands are available:
• Control Word Command. Specifies which counter to read or write, the operating
mode, and the count format (binary or BCD).
• Counter Latch Command. Latches the current count so that it can be read by the
system. The countdown process continues.
• Read Back Command. Reads the count value, programmed mode, the current
state of the OUT pins, and the state of the Null Count Flag of the selected counter.
Table 5-12 lists the six operating modes for the interval counters.
Table 5-12. Counter Operating Modes
Mode Function Description
Output is 0. When count goes to 0, output goes to
0 Out signal on end of count (=0)
1 and stays at 1 until counter is reprogrammed.
Output is 0. When count goes to 0, output goes to
1 Hardware retriggerable one-shot
1 for one clock time.
Rate generator (divide by n Output is 1. Output goes to 0 for one clock time,
2
counter) then back to 1 and counter is reloaded.
Output is 1. Output goes to 0 when counter rolls
over, and counter is reloaded. Output goes to 1
3 Square wave output
when counter rolls over, and counter is reloaded,
and so on.
Output is 1. Output goes to 0 when count expires
4 Software triggered strobe
for one clock time.
Output is 1. Output goes to 0 when count expires
5 Hardware triggered strobe
for one clock time.
Datasheet 177
Functional Description
5.8.2 Reading from the Interval Timer
It is often desirable to read the value of a counter without disturbing the count in
progress. There are three methods for reading the counters: a simple read operation,
counter Latch command, and the Read-Back command. Each is explained below.
With the simple read and counter latch command methods, the count must be read
according to the programmed format; specifically, if the counter is programmed for two
byte counts, two bytes must be read. The two bytes do not have to be read one right
after the other. Read, write, or programming operations for other counters may be
inserted between them.
5.8.2.1 Simple Read
The first method is to perform a simple read operation. The counter is selected through
Port 40h (Counter 0), 41h (Counter 1), or 42h (Counter 2).
Note: Performing a direct read from the counter does not return a determinate value,
because the counting process is asynchronous to read operations. However, in the case
of Counter 2, the count can be stopped by writing to the GATE bit in Port 61h.
5.8.2.2 Counter Latch Command
The Counter Latch command, written to Port 43h, latches the count of a specific
counter at the time the command is received. This command is used to ensure that the
count read from the counter is accurate, particularly when reading a two-byte count.
The count value is then read from each counter’s Count register as was programmed by
the Control register.
The count is held in the latch until it is read or the counter is reprogrammed. The count
is then unlatched. This allows reading the contents of the counters on the fly without
affecting counting in progress. Multiple Counter Latch Commands may be used to latch
more than one counter. Counter Latch commands do not affect the programmed mode
of the counter in any way.
If a Counter is latched and then, some time later, latched again before the count is
read, the second Counter Latch command is ignored. The count read is the count at the
time the first Counter Latch command was issued.
5.8.2.3 Read Back Command
The Read Back command, written to Port 43h, latches the count value, programmed
mode, and current states of the OUT pin and Null Count flag of the selected counter or
counters. The value of the counter and its status may then be read by I/O access to the
counter address.
The Read Back command may be used to latch multiple counter outputs at one time.
This single command is functionally equivalent to several counter latch commands, one
for each counter latched. Each counter's latched count is held until it is read or
reprogrammed. Once read, a counter is unlatched. The other counters remain latched
until they are read. If multiple count Read Back commands are issued to the same
counter without reading the count, all but the first are ignored.
The Read Back command may additionally be used to latch status information of
selected counters. The status of a counter is accessed by a read from that counter's
I/O port address. If multiple counter status latch operations are performed without
reading the status, all but the first are ignored.
178 Datasheet
Functional Description
Both count and status of the selected counters may be latched simultaneously. This is
functionally the same as issuing two consecutive, separate Read Back commands. If
multiple count and/or status Read Back commands are issued to the same counters
without any intervening reads, all but the first are ignored.
If both count and status of a counter are latched, the first read operation from that
counter returns the latched status, regardless of which was latched first. The next one
or two reads, depending on whether the counter is programmed for one or two type
counts, returns the latched count. Subsequent reads return unlatched count.
5.9 8259 Programmable Interrupt Controllers (PIC)
(D31:F0)
The PCH incorporates the functionality of two 8259 interrupt controllers that provide
system interrupts for the ISA compatible interrupts. These interrupts can include:
system timer, keyboard controller, serial ports, parallel ports, floppy disk, mouse, and
DMA channels. In addition, this interrupt controller can support the PCI based
interrupts, by mapping the PCI interrupt onto the compatible ISA interrupt line. Each
8259 controller supports eight interrupts, numbered 0–7. Table 5-13 shows how the
controllers are connected.
Table 5-13. Interrupt Controller Connections
8259 Typical Interrupt
8259 Connected Pin / Function
Input Source
0 Internal Internal Timer / Counter 0 output / HPET #0
1 Keyboard IRQ1 using SERIRQ
2 Internal Slave controller INTR output
3 Serial Port A IRQ3 using SERIRQ,
Master
4 Serial Port B IRQ4 using SERIRQ, PIRQ#
5 Parallel Port / Generic IRQ5 using SERIRQ, PIRQ#
6 Floppy Disk IRQ6 using SERIRQ, PIRQ#
7 Parallel Port / Generic IRQ7 using SERIRQ, PIRQ#
Internal Real Time
0 Internal RTC / HPET #1
Clock
1 Generic IRQ9 using SERIRQ, SCI, TCO, or PIRQ#
2 Generic IRQ10 using SERIRQ, SCI, TCO, or PIRQ#
IRQ11 using SERIRQ, SCI, TCO, or PIRQ#, or HPET
3 Generic
#2
IRQ12 using SERIRQ, SCI, TCO, or PIRQ#, or HPET
Slave 4 PS/2 Mouse
#3
State Machine output based on processor FERR#
5 Internal assertion. May optionally be used for SCI or TCO
interrupt if FERR# not needed.
SATA Primary (legacy mode), or using SERIRQ or
6 SATA
PIRQ#
SATA Secondary (legacy mode) or using SERIRQ or
7 SATA
PIRQ#
Datasheet 179
Functional Description
The PCH cascades the slave controller onto the master controller through master
controller interrupt input 2. This means there are only 15 possible interrupts for the
PCH PIC.
Interrupts can individually be programmed to be edge or level, except for IRQ0, IRQ2,
IRQ8#, and IRQ13.
Note: Active-low interrupt sources (such as, the PIRQ#s) are inverted inside the PCH. In the
following descriptions of the 8259s, the interrupt levels are in reference to the signals
at the internal interface of the 8259s, after the required inversions have occurred.
Therefore, the term “high” indicates “active,” which means “low” on an originating
PIRQ#.
5.9.1 Interrupt Handling
5.9.1.1 Generating Interrupts
The PIC interrupt sequence involves three bits, from the IRR, ISR, and IMR, for each
interrupt level. These bits are used to determine the interrupt vector returned, and
status of any other pending interrupts. Table 5-14 defines the IRR, ISR, and IMR.
Table 5-14. Interrupt Status Registers
Bit Description
Interrupt Request Register. This bit is set on a low to high transition of the interrupt
IRR line in edge mode, and by an active high level in level mode. This bit is set whether or
not the interrupt is masked. However, a masked interrupt will not generate INTR.
Interrupt Service Register. This bit is set, and the corresponding IRR bit cleared,
ISR when an interrupt acknowledge cycle is seen, and the vector returned is for that
interrupt.
Interrupt Mask Register. This bit determines whether an interrupt is masked.
IMR
Masked interrupts will not generate INTR.
180 Datasheet
Functional Description
5.9.1.2 Acknowledging Interrupts
The processor generates an interrupt acknowledge cycle that is translated by the host
bridge into a PCI Interrupt Acknowledge Cycle to the PCH. The PIC translates this
command into two internal INTA# pulses expected by the 8259 cores. The PIC uses the
first internal INTA# pulse to freeze the state of the interrupts for priority resolution. On
the second INTA# pulse, the master or slave sends the interrupt vector to the
processor with the acknowledged interrupt code. This code is based upon Bits 7:3 of
the corresponding ICW2 register, combined with three bits representing the interrupt
within that controller.
Table 5-15. Content of Interrupt Vector Byte
Master, Slave Interrupt Bits [7:3] Bits [2:0]
IRQ7,15 111
IRQ6,14 110
IRQ5,13 101
IRQ4,12 100
ICW2[7:3]
IRQ3,11 011
IRQ2,10 010
IRQ1,9 001
IRQ0,8 000
5.9.1.3 Hardware/Software Interrupt Sequence
1. One or more of the Interrupt Request lines (IRQ) are raised high in edge mode, or
seen high in level mode, setting the corresponding IRR bit.
2. The PIC sends INTR active to the processor if an asserted interrupt is not masked.
3. The processor acknowledges the INTR and responds with an interrupt acknowledge
cycle. The cycle is translated into a PCI interrupt acknowledge cycle by the host
bridge. This command is broadcast over PCI by the PCH.
4. Upon observing its own interrupt acknowledge cycle on PCI, the PCH converts it
into the two cycles that the internal 8259 pair can respond to. Each cycle appears
as an interrupt acknowledge pulse on the internal INTA# pin of the cascaded
interrupt controllers.
5. Upon receiving the first internally generated INTA# pulse, the highest priority ISR
bit is set and the corresponding IRR bit is reset. On the trailing edge of the first
pulse, a slave identification code is broadcast by the master to the slave on a
private, internal three bit wide bus. The slave controller uses these bits to
determine if it must respond with an interrupt vector during the second INTA#
pulse.
6. Upon receiving the second internally generated INTA# pulse, the PIC returns the
interrupt vector. If no interrupt request is present because the request was too
short in duration, the PIC returns vector 7 from the master controller.
7. This completes the interrupt cycle. In AEOI mode the ISR bit is reset at the end of
the second INTA# pulse. Otherwise, the ISR bit remains set until an appropriate
EOI command is issued at the end of the interrupt subroutine.
Datasheet 181
Functional Description
5.9.2 Initialization Command Words (ICWx)
Before operation can begin, each 8259 must be initialized. In the PCH, this is a four
byte sequence. The four initialization command words are referred to by their
acronyms: ICW1, ICW2, ICW3, and ICW4.
The base address for each 8259 initialization command word is a fixed location in the
I/O memory space: 20h for the master controller, and A0h for the slave controller.
5.9.2.1 ICW1
An I/O write to the master or slave controller base address with data bit 4 equal to 1 is
interpreted as a write to ICW1. Upon sensing this write, the PCH’s PIC expects three
more byte writes to 21h for the master controller, or A1h for the slave controller, to
complete the ICW sequence.
A write to ICW1 starts the initialization sequence during which the following
automatically occur:
1. Following initialization, an interrupt request (IRQ) input must make a low-to-high
transition to generate an interrupt.
2. The Interrupt Mask Register is cleared.
3. IRQ7 input is assigned priority 7.
4. The slave mode address is set to 7.
5. Special mask mode is cleared and Status Read is set to IRR.
5.9.2.2 ICW2
The second write in the sequence (ICW2) is programmed to provide bits [7:3] of the
interrupt vector that will be released during an interrupt acknowledge. A different base
is selected for each interrupt controller.
5.9.2.3 ICW3
The third write in the sequence (ICW3) has a different meaning for each controller.
• For the master controller, ICW3 is used to indicate which IRQ input line is used to
cascade the slave controller. Within the PCH, IRQ2 is used. Therefore, Bit 2 of ICW3
on the master controller is set to a 1, and the other bits are set to 0s.
• For the slave controller, ICW3 is the slave identification code used during an
interrupt acknowledge cycle. On interrupt acknowledge cycles, the master
controller broadcasts a code to the slave controller if the cascaded interrupt won
arbitration on the master controller. The slave controller compares this
identification code to the value stored in its ICW3, and if it matches, the slave
controller assumes responsibility for broadcasting the interrupt vector.
5.9.2.4 ICW4
The final write in the sequence (ICW4) must be programmed for both controllers. At
the very least, Bit 0 must be set to a 1 to indicate that the controllers are operating in
an Intel Architecture-based system.
182 Datasheet
Functional Description
5.9.3 Operation Command Words (OCW)
These command words reprogram the Interrupt controller to operate in various
interrupt modes.
• OCW1 masks and unmasks interrupt lines.
• OCW2 controls the rotation of interrupt priorities when in rotating priority mode,
and controls the EOI function.
• OCW3 sets up ISR/IRR reads, enables/disables the special mask mode (SMM), and
enables/disables polled interrupt mode.
5.9.4 Modes of Operation
5.9.4.1 Fully Nested Mode
In this mode, interrupt requests are ordered in priority from 0 through 7, with 0 being
the highest. When an interrupt is acknowledged, the highest priority request is
determined and its vector placed on the bus. Additionally, the ISR for the interrupt is
set. This ISR bit remains set until: the processor issues an EOI command immediately
before returning from the service routine; or if in AEOI mode, on the trailing edge of
the second INTA#. While the ISR bit is set, all further interrupts of the same or lower
priority are inhibited, while higher levels generate another interrupt. Interrupt priorities
can be changed in the rotating priority mode.
5.9.4.2 Special Fully-Nested Mode
This mode is used in the case of a system where cascading is used, and the priority has
to be conserved within each slave. In this case, the special fully-nested mode is
programmed to the master controller. This mode is similar to the fully-nested mode
with the following exceptions:
• When an interrupt request from a certain slave is in service, this slave is not locked
out from the master's priority logic and further interrupt requests from higher
priority interrupts within the slave are recognized by the master and initiate
interrupts to the processor. In the normal-nested mode, a slave is masked out
when its request is in service.
• When exiting the Interrupt Service routine, software has to check whether the
interrupt serviced was the only one from that slave. This is done by sending a Non-
Specific EOI command to the slave and then reading its ISR. If it is 0, a non-
specific EOI can also be sent to the master.
5.9.4.3 Automatic Rotation Mode (Equal Priority Devices)
In some applications, there are a number of interrupting devices of equal priority.
Automatic rotation mode provides for a sequential 8-way rotation. In this mode, a
device receives the lowest priority after being serviced. In the worst case, a device
requesting an interrupt has to wait until each of seven other devices are serviced at
most once.
There are two ways to accomplish automatic rotation using OCW2; the Rotation on
Non-Specific EOI Command (R=1, SL=0, EOI=1) and the rotate in automatic EOI mode
which is set by (R=1, SL=0, EOI=0).
Datasheet 183
Functional Description
5.9.4.4 Specific Rotation Mode (Specific Priority)
Software can change interrupt priorities by programming the bottom priority. For
example, if IRQ5 is programmed as the bottom priority device, then IRQ6 is the highest
priority device. The Set Priority Command is issued in OCW2 to accomplish this, where:
R=1, SL=1, and LO–L2 is the binary priority level code of the bottom priority device.
In this mode, internal status is updated by software control during OCW2. However, it
is independent of the EOI command. Priority changes can be executed during an EOI
command by using the Rotate on Specific EOI Command in OCW2 (R=1, SL=1, EOI=1
and LO–L2=IRQ level to receive bottom priority.
5.9.4.5 Poll Mode
Poll mode can be used to conserve space in the interrupt vector table. Multiple
interrupts that can be serviced by one interrupt service routine do not need separate
vectors if the service routine uses the poll command. Poll mode can also be used to
expand the number of interrupts. The polling interrupt service routine can call the
appropriate service routine, instead of providing the interrupt vectors in the vector
table. In this mode, the INTR output is not used and the microprocessor internal
Interrupt Enable flip-flop is reset, disabling its interrupt input. Service to devices is
achieved by software using a Poll command.
The Poll command is issued by setting P=1 in OCW3. The PIC treats its next I/O read as
an interrupt acknowledge, sets the appropriate ISR bit if there is a request, and reads
the priority level. Interrupts are frozen from the OCW3 write to the I/O read. The byte
returned during the I/O read contains a 1 in Bit 7 if there is an interrupt, and the binary
code of the highest priority level in Bits 2:0.
5.9.4.6 Edge and Level Triggered Mode
In ISA systems this mode is programmed using Bit 3 in ICW1, which sets level or edge
for the entire controller. In the PCH, this bit is disabled and a register for edge and level
triggered mode selection, per interrupt input, is included. This is the Edge/Level control
Registers ELCR1 and ELCR2.
If an ELCR bit is 0, an interrupt request will be recognized by a low-to-high transition
on the corresponding IRQ input. The IRQ input can remain high without generating
another interrupt. If an ELCR bit is 1, an interrupt request will be recognized by a high
level on the corresponding IRQ input and there is no need for an edge detection. The
interrupt request must be removed before the EOI command is issued to prevent a
second interrupt from occurring.
In both the edge and level triggered modes, the IRQ inputs must remain active until
after the falling edge of the first internal INTA#. If the IRQ input goes inactive before
this time, a default IRQ7 vector is returned.
5.9.4.7 End of Interrupt (EOI) Operations
An EOI can occur in one of two fashions: by a command word write issued to the PIC
before returning from a service routine, the EOI command; or automatically when AEOI
bit in ICW4 is set to 1.
5.9.4.8 Normal End of Interrupt
In normal EOI, software writes an EOI command before leaving the interrupt service
routine to mark the interrupt as completed. There are two forms of EOI commands:
Specific and Non-Specific. When a Non-Specific EOI command is issued, the PIC clears
the highest ISR bit of those that are set to 1. Non-Specific EOI is the normal mode of
operation of the PIC within the PCH, as the interrupt being serviced currently is the
184 Datasheet
Functional Description
interrupt entered with the interrupt acknowledge. When the PIC is operated in modes
that preserve the fully nested structure, software can determine which ISR bit to clear
by issuing a Specific EOI. An ISR bit that is masked is not cleared by a Non-Specific EOI
if the PIC is in the special mask mode. An EOI command must be issued for both the
master and slave controller.
5.9.4.9 Automatic End of Interrupt Mode
In this mode, the PIC automatically performs a Non-Specific EOI operation at the
trailing edge of the last interrupt acknowledge pulse. From a system standpoint, this
mode should be used only when a nested multi-level interrupt structure is not required
within a single PIC. The AEOI mode can only be used in the master controller and not
the slave controller.
5.9.5 Masking Interrupts
5.9.5.1 Masking on an Individual Interrupt Request
Each interrupt request can be masked individually by the Interrupt Mask Register
(IMR). This register is programmed through OCW1. Each bit in the IMR masks one
interrupt channel. Masking IRQ2 on the master controller masks all requests for service
from the slave controller.
5.9.5.2 Special Mask Mode
Some applications may require an interrupt service routine to dynamically alter the
system priority structure during its execution under software control. For example, the
routine may wish to inhibit lower priority requests for a portion of its execution but
enable some of them for another portion.
The special mask mode enables all interrupts not masked by a bit set in the Mask
register. Normally, when an interrupt service routine acknowledges an interrupt without
issuing an EOI to clear the ISR bit, the interrupt controller inhibits all lower priority
requests. In the special mask mode, any interrupts may be selectively enabled by
loading the Mask Register with the appropriate pattern. The special mask mode is set
by OCW3 where: SSMM=1, SMM=1, and cleared where SSMM=1, SMM=0.
5.9.6 Steering PCI Interrupts
The PCH can be programmed to allow PIRQA#-PIRQH# to be routed internally to
interrupts 3–7, 9–12, 14 or 15. The assignment is programmable through the PIRQx
Route Control registers, located at 60–63h and 68–6Bh in D31:F0. One or more
PIRQx# lines can be routed to the same IRQx input. If interrupt steering is not
required, the Route registers can be programmed to disable steering.
The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts
on a PCI board to share a single line across the connector. When a PIRQx# is routed to
specified IRQ line, software must change the IRQ's corresponding ELCR bit to level
sensitive mode. The PCH internally inverts the PIRQx# line to send an active high level
to the PIC. When a PCI interrupt is routed onto the PIC, the selected IRQ can no longer
be used by an active high device (through SERIRQ). However, active low interrupts can
share their interrupt with PCI interrupts.
Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external
PIRQ to be asserted. The PCH receives the PIRQ input, like all of the other external
sources, and routes it accordingly.
Datasheet 185
Functional Description
5.10 Advanced Programmable Interrupt Controller
(APIC) (D31:F0)
In addition to the standard ISA-compatible PIC described in the previous section, the
PCH incorporates the APIC. While the standard interrupt controller is intended for use
in a uni-processor system, APIC can be used in either a uni-processor or multi-
processor system.
5.10.1 Interrupt Handling
The I/O APIC handles interrupts very differently than the 8259. Briefly, these
differences are:
• Method of Interrupt Transmission. The I/O APIC transmits interrupts through
memory writes on the normal data path to the processor, and interrupts are
handled without the need for the processor to run an interrupt acknowledge cycle.
• Interrupt Priority. The priority of interrupts in the I/O APIC is independent of the
interrupt number. For example, interrupt 10 can be given a higher priority than
interrupt 3.
• More Interrupts. The I/O APIC in the PCH supports a total of 24 interrupts.
• Multiple Interrupt Controllers. The I/O APIC architecture allows for multiple I/O
APIC devices in the system with their own interrupt vectors.
5.10.2 Interrupt Mapping
The I/O APIC within the PCH supports 24 APIC interrupts. Each interrupt has its own
unique vector assigned by software. The interrupt vectors are mapped as shown in the
following table.
Table 5-16. APIC Interrupt Mapping1 (Sheet 1 of 2)
Using Direct Using PCI
IRQ # Internal Modules
SERIRQ from Pin Message
0 No No No Cascade from 8259 #1
1 Yes No Yes
2 No No No 8254 Counter 0, HPET #0 (legacy mode)
3 Yes No Yes
4 Yes No Yes
5 Yes No Yes
6 Yes No Yes
7 Yes No Yes
8 No No No RTC, HPET #1 (legacy mode)
9 Yes No Yes Option for SCI, TCO
10 Yes No Yes Option for SCI, TCO
11 Yes No Yes HPET #2, Option for SCI, TCO (Note 2)
12 Yes No Yes HPET #3 (Note 3)
13 No No No FERR# logic
14 Yes No Yes SATA Primary (legacy mode)
15 Yes No Yes SATA Secondary (legacy mode)
186 Datasheet
Functional Description
Table 5-16. APIC Interrupt Mapping1 (Sheet 2 of 2)
Using Direct Using PCI
IRQ # Internal Modules
SERIRQ from Pin Message
16 PIRQA# PIRQA#
17 PIRQB# PIRQB# Internal devices are routable; see
Yes
18 PIRQC# PIRQC# Section 10.1.20 though Section 10.1.36.
19 PIRQD# PIRQD#
20 N/A PIRQE#4
21 N/A PIRQF#4 Option for SCI, TCO, HPET #0,1,2, 3. Other
Yes internal devices are routable; see
22 N/A PIRQG#4 Section 10.1.20 though Section 10.1.36.
23 N/A PIRQH#4
NOTES:
1. When programming the polarity of internal interrupt sources on the APIC, interrupts 0
through 15 receive active-high internal interrupt sources, while interrupts 16 through 23
receive active-low internal interrupt sources.
2. If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other
devices to ensure the proper operation of HPET #2. The PCH hardware does not prevent
sharing of IRQ 11.
3. If IRQ 12 is used for HPET #3, software should ensure IRQ 12 is not shared with any other
devices to ensure the proper operation of HPET #3. The PCH hardware does not prevent
sharing of IRQ 12.
4. PIRQ[E:H] are Multiplexed with GPIO pins. Interrupts PIRQ[E:H] will not be exposed if they
are configured as GPIOs.
5.10.3 PCI / PCI Express* Message-Based Interrupts
When external devices through PCI/PCI Express wish to generate an interrupt, they will
send the message defined in the PCI Express* Base Specification, Revision 2.0 for
generating INTA# – INTD#. These will be translated internal assertions/de-assertions
of INTA# – INTD#.
5.10.4 IOxAPIC Address Remapping
To support Intel Virtualization Technology, interrupt messages are required to go
through similar address remapping as any other memory request. Address remapping
allows for domain isolation for interrupts, so a device assigned in one domain is not
allowed to generate an interrupt to another domain.
The address remapping is based on the Bus: Device: Function field associated with the
requests. The internal APIC is required to initiate the interrupt message using a unique
Bus: Device: Function.
The PCH allows BIOS to program the unique Bus: Device: Function address for the
internal APIC. This address field does not change the APIC functionality and the APIC is
not promoted as a stand-alone PCI device. See Device 31: Function 0 Offset 6Ch for
additional information.
5.10.5 External Interrupt Controller Support
The PCH supports external APICs off of PCI Express ports but does not support APICs
on the PCI bus. The EOI special cycle is only forwarded to PCI Express ports.
Datasheet 187
Functional Description
5.11 Serial Interrupt (D31:F0)
The PCH supports a serial IRQ scheme. This allows a single signal to be used to report
interrupt requests. The signal used to transmit this information is shared between the
PCH and all participating peripherals. The signal line, SERIRQ, is synchronous to PCI
clock, and follows the sustained tri-state protocol that is used by all PCI signals. This
means that if a device has driven SERIRQ low, it will first drive it high synchronous to
PCI clock and release it the following PCI clock. The serial IRQ protocol defines this
sustained tri-state signaling in the following fashion:
• S – Sample Phase. Signal driven low
• R – Recovery Phase. Signal driven high
• T – Turn-around Phase. Signal released
The PCH supports a message for 21 serial interrupts. These represent the 15 ISA
interrupts (IRQ0–1, 3–15), the four PCI interrupts, and the control signals SMI# and
IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts
(20–23).
Note: When the SATA controller is configured for legacy IDE mode, IRQ14 and IRQ15 are
expected to behave as ISA legacy interrupts that cannot be shared (that is, through the
Serial Interrupt pin). If IRQ14 and IRQ15 are shared with Serial Interrupt pin then
abnormal system behavior may occur. For example, IRQ14/15 may not be detected by
the PCH's interrupt controller. When the SATA controller is not running in Native IDE
mode, IRQ14 and IRQ15 are used as special interrupts. If the SATA controller is in
native mode, these interrupts can be mapped to other devices accordingly.
5.11.1 Start Frame
The serial IRQ protocol has two modes of operation which affect the start frame. These
two modes are: Continuous, where the PCH is solely responsible for generating the
start frame; and Quiet, where a serial IRQ peripheral is responsible for beginning the
start frame.
The mode that must first be entered when enabling the serial IRQ protocol is
continuous mode. In this mode, the PCH asserts the start frame. This start frame is 4,
6, or 8 PCI clocks wide based upon the Serial IRQ Control Register, bits 1:0 at 64h in
D31:F0 configuration space. This is a polling mode.
When the serial IRQ stream enters quiet mode (signaled in the Stop Frame), the
SERIRQ line remains inactive and pulled up between the Stop and Start Frame until a
peripheral drives the SERIRQ signal low. The PCH senses the line low and continues to
drive it low for the remainder of the Start Frame. Since the first PCI clock of the start
frame was driven by the peripheral in this mode, the PCH drives the SERIRQ line low for
1 PCI clock less than in continuous mode. This mode of operation allows for a quiet,
and therefore lower power, operation.
188 Datasheet
Functional Description
5.11.2 Data Frames
Once the Start frame has been initiated, all of the SERIRQ peripherals must start
counting frames based on the rising edge of SERIRQ. Each of the IRQ/DATA frames has
exactly 3 phases of 1 clock each:
• Sample Phase. During this phase, the SERIRQ device drives SERIRQ low if the
corresponding interrupt signal is low. If the corresponding interrupt is high, then
the SERIRQ devices tri-state the SERIRQ signal. The SERIRQ line remains high due
to pull-up resistors (there is no internal pull-up resistor on this signal, an external
pull-up resistor is required). A low level during the IRQ0–1 and IRQ2–15 frames
indicates that an active-high ISA interrupt is not being requested, but a low level
during the PCI INT[A:D], SMI#, and IOCHK# frame indicates that an active-low
interrupt is being requested.
• Recovery Phase. During this phase, the device drives the SERIRQ line high if in
the Sample Phase it was driven low. If it was not driven in the sample phase, it is
tri-stated in this phase.
• Turn-around Phase. The device tri-states the SERIRQ line
5.11.3 Stop Frame
After all data frames, a Stop Frame is driven by the PCH. The SERIRQ signal is driven
low by the PCH for 2 or 3 PCI clocks. The number of clocks is determined by the
SERIRQ configuration register. The number of clocks determines the next mode.
Table 5-17. Stop Frame Explanation
Stop Frame Width Next Mode
2 PCI clocks Quiet Mode. Any SERIRQ device may initiate a Start Frame
3 PCI clocks Continuous Mode. Only the host (the PCH) may initiate a Start Frame
5.11.4 Specific Interrupts Not Supported Using SERIRQ
There are three interrupts seen through the serial stream that are not supported by the
PCH. These interrupts are generated internally, and are not sharable with other devices
within the system. These interrupts are:
• IRQ0. Heartbeat interrupt generated off of the internal 8254 counter 0.
• IRQ8#. RTC interrupt can only be generated internally.
• IRQ13. Floating point error interrupt generated off of the processor assertion of
FERR#.
The PCH ignores the state of these interrupts in the serial stream, and does not adjust
their level based on the level seen in the serial stream.
Datasheet 189
Functional Description
5.11.5 Data Frame Format
Table 5-18 shows the format of the data frames. For the PCI interrupts (A–D), the
output from the PCH is AND’d with the PCI input signal. This way, the interrupt can be
signaled using both the PCI interrupt input signal and using the SERIRQ signal (they
are shared).
Table 5-18. Data Frame Format
Data Clocks Past
Frame Interrupt Start Comment
# Frame
Ignored. IRQ0 can only be generated using the internal
1 IRQ0 2
8524
2 IRQ1 5
3 SMI# 8 Causes SMI# if low. Will set the SERIRQ_SMI_STS bit.
4 IRQ3 11
5 IRQ4 14
6 IRQ5 17
7 IRQ6 20
8 IRQ7 23
9 IRQ8 26 Ignored. IRQ8# can only be generated internally.
10 IRQ9 29
11 IRQ10 32
12 IRQ11 35
13 IRQ12 38
14 IRQ13 41 Ignored. IRQ13 can only be generated from FERR#
15 IRQ14 44 Not attached to SATA logic
16 IRQ15 47 Not attached to SATA logic
17 IOCHCK# 50 Same as ISA IOCHCK# going active.
18 PCI INTA# 53 Drive PIRQA#
19 PCI INTB# 56 Drive PIRQB#
20 PCI INTC# 59 Drive PIRQC#
21 PCI INTD# 62 Drive PIRQD#
190 Datasheet
Functional Description
5.12 Real Time Clock (D31:F0)
The Real Time Clock (RTC) module provides a battery backed-up date and time keeping
device with two banks of static RAM with 128 bytes each, although the first bank has
114 bytes for general purpose usage. Three interrupt features are available: time of
day alarm with once a second to once a month range, periodic rates of 122 µs to
500 ms, and end of update cycle notification. Seconds, minutes, hours, days, day of
week, month, and year are counted. Daylight savings compensation is no longer
supported. The hour is represented in twelve or twenty-four hour format, and data can
be represented in BCD or binary format. The design is functionally compatible with the
Motorola MS146818B. The time keeping comes from a 32.768 kHz oscillating source,
which is divided to achieve an update every second. The lower 14 bytes on the lower
RAM block has very specific functions. The first ten are for time and date information.
The next four (0Ah to 0Dh) are registers, which configure and report RTC functions.
The time and calendar data should match the data mode (BCD or binary) and hour
mode (12 or 24 hour) as selected in register B. It is up to the programmer to make
sure that data stored in these locations is within the reasonable values ranges and
represents a possible date and time. The exception to these ranges is to store a value
of C0–FFh in the Alarm bytes to indicate a don’t care situation. All Alarm conditions
must match to trigger an Alarm Flag, which could trigger an Alarm Interrupt if enabled.
The SET bit must be 1 while programming these locations to avoid clashes with an
update cycle. Access to time and date information is done through the RAM locations. If
a RAM read from the ten time and date bytes is attempted during an update cycle, the
value read do not necessarily represent the true contents of those locations. Any RAM
writes under the same conditions are ignored.
Note: The leap year determination for adding a 29th day to February does not take into
account the end-of-the-century exceptions. The logic simply assumes that all years
divisible by 4 are leap years. According to the Royal Observatory Greenwich, years that
are divisible by 100 are typically not leap years. In every fourth century (years divisible
by 400, like 2000), the 100-year-exception is over-ridden and a leap-year occurs. The
year 2100 will be the first time in which the current RTC implementation would
incorrectly calculate the leap-year.
The PCH does not implement month/year alarms.
5.12.1 Update Cycles
An update cycle occurs once a second, if the SET bit of register B is not asserted and
the divide chain is properly configured. During this procedure, the stored time and date
are incremented, overflow is checked, a matching alarm condition is checked, and the
time and date are rewritten to the RAM locations. The update cycle will start at least
488 µs after the UIP bit of register A is asserted, and the entire cycle does not take
more than 1984 µs to complete. The time and date RAM locations (0–9) are
disconnected from the external bus during this time.
To avoid update and data corruption conditions, external RAM access to these locations
can safely occur at two times. When a updated-ended interrupt is detected, almost
999 ms is available to read and write the valid time and date data. If the UIP bit of
Register A is detected to be low, there is at least 488 µs before the update cycle begins.
Warning: The overflow conditions for leap years adjustments are based on more than one date or
time item. To ensure proper operation when adjusting the time, the new time and data
values should be set at least two seconds before leap year occurs.
Datasheet 191
Functional Description
5.12.2 Interrupts
The real-time clock interrupt is internally routed within the PCH both to the I/O APIC
and the 8259. It is mapped to interrupt vector 8. This interrupt does not leave the PCH,
nor is it shared with any other interrupt. IRQ8# from the SERIRQ stream is ignored.
However, the High Performance Event Timers can also be mapped to IRQ8#; in this
case, the RTC interrupt is blocked.
5.12.3 Lockable RAM Ranges
The RTC battery-backed RAM supports two 8-byte ranges that can be locked using the
configuration space. If the locking bits are set, the corresponding range in the RAM will
not be readable or writable. A write cycle to those locations will have no effect. A read
cycle to those locations will not return the location’s actual value (resultant value is
undefined).
Once a range is locked, the range can be unlocked only by a hard reset, which will
invoke the BIOS and allow it to relock the RAM range.
5.12.4 Century Rollover
The PCH detects a rollover when the Year byte (RTC I/O space, index Offset 09h)
transitions form 99 to 00. Upon detecting the rollover, the PCH sets the
NEWCENTURY_STS bit (TCOBASE + 04h, Bit 7). If the system is in an S0 state, this
causes an SMI#. The SMI# handler can update registers in the RTC RAM that are
associated with century value. If the system is in a sleep state (S1–S5) when the
century rollover occurs, the PCH also sets the NEWCENTURY_STS bit, but no SMI# is
generated. When the system resumes from the sleep state, BIOS should check the
NEWCENTURY_STS bit and update the century value in the RTC RAM.
5.12.5 Clearing Battery-Backed RTC RAM
Clearing CMOS RAM in a PCH-based platform can be done by using a jumper on
RTCRST# or GPI. Implementations should not attempt to clear CMOS by using a
jumper to pull VccRTC low.
Using RTCRST# to Clear CMOS
A jumper on RTCRST# can be used to clear CMOS values, as well as reset to default,
the state of those configuration bits that reside in the RTC power well. When the
RTCRST# is strapped to ground, the RTC_PWR_STS bit (D31:F0:A4h Bit 2) will be set
and those configuration bits in the RTC power well will be set to their default state.
BIOS can monitor the state of this Bit, and manually clear the RTC CMOS array once
the system is booted. The normal position would cause RTCRST# to be pulled up
through a weak pull-up resistor. Table 5-19 shows which bits are set to their default
state when RTCRST# is asserted. This RTCRST# jumper technique allows the jumper to
be moved and then replaced—all while the system is powered off. Then, once booted,
the RTC_PWR_STS can be detected in the set state.
192 Datasheet
Functional Description
Table 5-19. Configuration Bits Reset by RTCRST# Assertion
Default
Bit Name Register Location Bit(s)
State
Alarm Interrupt Register B (General I/O space (RTC Index
5 X
Enable (AIE) Configuration) (RTC_REGB) + 0Bh)
Register C (Flag Register) I/O space (RTC Index
Alarm Flag (AF) 5 X
(RTC_REGC) + 0Ch)
General PM Configuration 3
SWSMI_RATE_SEL D31:F0:A4h 7:6 0
Register GEN_PMCON_3
SLP_S4# Minimum General PM Configuration 3
D31:F0:A4h 5:4 0
Assertion Width Register GEN_PMCON_3
SLP_S4# Assertion General PM Configuration 3
D31:F0:A4h 3 0
Stretch Enable Register GEN_PMCON_3
RTC Power Status General PM Configuration 3
D31:F0:A4h 2 0
(RTC_PWR_STS) Register GEN_PMCON_3
Power Failure General PM Configuration 3
D31:F0:A4h 1 0
(PWR_FLR) Register (GEN_PMCON_3)
General PM Configuration 3
AFTERG3_EN D31:F0:A4h 0 0
Register GEN_PMCON_3
Power Button
Power Management 1 Status
Override Status PMBase + 00h 11 0
Register (PM1_STS)
(PRBTNOR_STS)
RTC Event Enable Power Management 1 Enable
PMBase + 02h 10 0
(RTC_EN) Register (PM1_EN)
Sleep Type Power Management 1 Control
PMBase + 04h 12:10 0
(SLP_TYP) (PM1_CNT)
General Purpose Event 0
PME_EN PMBase + 2Ch 11 0
Enables Register (GPE0_EN)
General Purpose Event 0
BATLOW_EN PMBase + 2Ch 10 0
Enables Register (GPE0_EN)
General Purpose Event 0
RI_EN PMBase + 2Ch 8 0
Enables Register (GPE0_EN)
NEWCENTURY_ST TCO1 Status Register
TCOBase + 04h 7 0
S (TCO1_STS)
Intruder Detect TCO2 Status Register
TCOBase + 06h 0 0
(INTRD_DET) (TCO2_STS)
Backed Up Control Register Chipset Config
Top Swap (TS) 0 X
(BUC) Registers:Offset 3414h
Using a GPI to Clear CMOS
A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the
setting of this GPI on system boot-up, and manually clear the CMOS array.
Note: The GPI strap technique to clear CMOS requires multiple steps to implement. The
system is booted with the jumper in new position, then powered back down. The
jumper is replaced back to the normal position, then the system is rebooted again.
Warning: Do not implement a jumper on VccRTC to clear CMOS.
Datasheet 193
Functional Description
5.13 Processor Interface (D31:F0)
The PCH interfaces to the processor with following pin-based signals other than DMI:
• Standard Outputs to processor: PROCPWRGD, PMSYNCH, PECI
• Standard Input from processor: THRMTRIP#
Most PCH outputs to the processor use standard buffers. The PCH has separate
V_PROC_IO signals that are pulled up at the system level to the processor voltage, and
thus determines VOH for the outputs to the processor.
The following processor interface legacy pins were removed from the PCH:
• IGNNE#, STPCLK#, DPSLP#, are DPRSLPVR are no longer required on PCH based
systems.
• A20M#, SMI#, NMI, INIT#, INTR, FERR#: Functionality has been replaced by in-
band Virtual Legacy Wire (VLW) messages. See Section 5.13.3.
5.13.1 Processor Interface Signals and VLW Messages
This section describes each of the signals that interface between the PCH and the
processor(s). The behavior of some signals may vary during processor reset, as the
signals are used for frequency strapping.
5.13.1.1 INIT (Initialization)
The INIT# VLW Message is asserted based on any one of several events described in
Table 5-20. When any of these events occur, INIT# is asserted for 16 PCI clocks, then
driven high.
Table 5-20. INIT# Going Active
Cause of INIT# Going Active Comment
Shutdown special cycle from processor observed INIT assertion based on value of Shutdown
on PCH-processor interconnect. Policy Select register (SPS)
PORT92 write, where INIT_NOW (Bit 0) transitions
from a 0 to a 1.
PORTCF9 write, where SYS_RST (Bit 1) was a 0
and RST_CPU (Bit 2) transitions from 0 to 1.
0 to 1 transition on RCIN# must occur
before the PCH will arm INIT# to be
generated again.
NOTE: RCIN# signal is expected to be low
RCIN# input signal goes low. RCIN# is expected
during S3, S4, and S5 states.
to be driven by the external microcontroller
Transition on the RCIN# signal in
(KBC).
those states (or the transition to
those states) may not necessarily
cause the INIT# signal to be
generated to the processor.
To enter BIST, software sets CPU_BIST_EN
Processor BIST bit and then does a full processor reset
using the CF9 register.
194 Datasheet
Functional Description
5.13.1.2 FERR# (Numeric Coprocessor Error)
The PCH supports the coprocessor error function with the FERR# message. The
function is enabled using the CEN bit. If FERR# is driven active by the processor, IRQ13
goes active (internally). When it detects a write to the COPROC_ERR register (I/O
Register F0h), the PCH negates the internal IRQ13 and IGNNE# will be active. IGNNE#
remains active until FERR# is driven inactive. IGNNE# is never driven active unless
FERR# is active.
Note: IGNNE# (Ignore Numeric Error is now internally generated by the processor.
5.13.1.3 NMI (Non-Maskable Interrupt)
Non-Maskable Interrupts (NMIs) can be generated by several sources, as described in
Table 5-21.
Table 5-21. NMI Sources
Cause of NMI Comment
SERR# goes active (either internally,
Can instead be routed to generate an SCI, through the
externally using SERR# signal, or using
NMI2SCI_EN bit (D31:F0, TCO Base + 08h, Bit 11).
message from processor)
IOCHK# goes active using SERIRQ# Can instead be routed to generate an SCI, through the
stream (ISA system Error) NMI2SCI_EN bit (D31:F0, TCO Base + 08h, Bit 11).
SECSTS Register D31:F0 Offset 1Eh, bit
This is enabled by the Parity Error Response Bit (PER).
8.
DEV_STS Register D31:F0 Offset 06h,
This is enabled by the Parity Error Response Bit (PER).
bit 8
GPIO[15:0] when configured as a
General Purpose input and routed as This is enabled by GPI NMI Enable (GPI_NMI_EN) bits
NMI (by GPIO_ROUT at D31:F0 Offset at D31:F0 Offset: GPIOBASE + 28h bits 15:0
B8)
5.13.1.4 Processor Power Good (PROCPWRGD)
This signal is connected to the processor UNCOREPWRGOOD input to indicate when the
processor power is valid.
5.13.2 Dual-Processor Issues
5.13.2.1 Usage Differences
In dual-processor designs, some of the processor signals are unused or used differently
than for uniprocessor designs.
• FERR# are generally not used, but still supported.
• I/O APIC and SMI# are assumed to be used.
Datasheet 195
Functional Description
5.13.3 Virtual Legacy Wire (VLW) Messages
The PCH supports VLW messages as alternative method of conveying the status of the
following legacy sideband interface signals to the processor:
• A20M#, INTR, SMI#, INIT#, NMI
Note: IGNNE# VLW message is not required to be generated by the PCH as it is internally
emulated by the processor.
VLW are inbound messages to the processor. They are communicated using Vendor
Defined Message over the DMI link.
Legacy processor signals can only be delivered using VLW in the PCH. Delivery of
legacy processor signals (A20M#, INTR, SMI#, INIT# or NMI) using I/O APIC controller
is not supported.
5.14 Power Management
5.14.1 Features
• Support for Advanced Configuration and Power Interface, Version 4.0a (ACPI)
providing power and thermal management
— ACPI 24-Bit Timer SCI and SMI# Generation
• PCI PME# signal for Wake Up from Low-Power states
• System Sleep State Control
— ACPI S3 state – Suspend to RAM (STR)
— ACPI S4 state – Suspend-to-Disk (STD)
— ACPI G2/S5 state – Soft Off (SOFF)
— Power Failure Detection and Recovery
— Deep Sx
• Intel Management Engine (Intel ME) Power Management Support
— Wake events from the Intel Management Engine (enabled from all S-States
including Catastrophic S5 conditions)
196 Datasheet
Functional Description
5.14.2 PCH and System Power States
Table 5-22 shows the power states defined for PCH-based platforms. The state names
generally match the corresponding ACPI states.
Table 5-22. General Power States for Systems Using the PCH
State/
Legacy Name / Description
Substates
Full On: Processor operating. Individual devices may be shut down or be placed
G0/S0/C0
into lower power states to save power.
Cx State: Cx states are processor power states within the S0 system state that
provide for various levels of power savings. The processor initiates C-state entry
G0/S0/Cx
and exit while interacting with the PCH. The PCH will base its behavior on the
processor state.
S1: The PCH provides the S1 messages and the S0 messages on a wake event.
G1/S1
It is preferred for systems to use C-states than S1.
Suspend-To-RAM (STR): The system context is maintained in system DRAM,
G1/S3 but power is shut off to non-critical circuits. Memory is retained and refreshes
continue. All external clocks stop except RTC.
Suspend-To-Disk (STD): The context of the system is maintained on the disk.
G1/S4
All power is then shut off to the system except for the logic required to resume.
Soft Off (SOFF): System context is not maintained. All power is shut off except
G2/S5
for the logic required to restart. A full boot is required when waking.
Deep Sx: An optional low power state where system context may or may not be
maintained depending upon entry condition. All power is shut off except for
minimal logic that allows exiting Deep Sx. If Deep Sx state was entered from S3
Deep Sx state, then the resume path will place system back into S3. If Deep Sx state was
entered from S4 state, then the resume path will place system back into S4. If
Deep Sx state was entered from S5 state, then the resume path will place
system back into S5.
Mechanical OFF (MOFF): System context not maintained. All power is shut off
except for the RTC. No “Wake” events are possible. This state occurs if the user
removes the main system batteries in a mobile system, turns off a mechanical
G3 switch, or if the system power supply is at a level that is insufficient to power the
“waking” logic. When system power returns, transition will depend on the state
just prior to the entry to G3 and the AFTERG3_EN bit in the GEN_PMCON_3
register (D31:F0, offset A4). Refer to Table 5-29 for more details.
Table 5-23 shows the transitions rules among the various states. Transitions among the
various states may appear to temporarily transition through intermediate states. For
example, in going from S0 to S3, it may appear to pass through the G1/S1 states.
These intermediate transitions and states are not listed in the table.
Datasheet 197
Functional Description
Table 5-23. State Transition Rules for the PCH
Present
Transition Trigger Next State
State
• DMI Msg • G0/S0/Cx
• SLP_EN bit set • G1/Sx or G2/S5 state
G0/S0/C0
• Power Button Override3 • G2/S5
• Mechanical Off/Power Failure • G3
• DMI Msg • G0/S0/C0
G0/S0/Cx • Power Button Override3 • S5
• Mechanical Off/Power Failure • G3
• Any Enabled Wake Event
• Power Button Override3 • G0/S0/C02
G1/S1 or • Conditions met as described in • G2/S5
G1/S3 Section 5.14.7.6.1 and • Deep Sx
Section 5.14.7.6.2 • G3
• Mechanical Off/Power Failure
• Any Enabled Wake Event • G0/S0/C02
• Power Button Override3 • G2/S5
G1/S4 • Conditions met as described in
Section 5.14.7.6.1 and • Deep Sx
Section 5.14.7.6.2
• Mechanical Off/Power Failure • G3
• Any Enabled Wake Event • G0/S0/C02
• Conditions met as described in
G2/S5 Section 5.14.7.6.1 and • Deep Sx
Section 5.14.7.6.2
• Mechanical Off/Power Failure • G3
• G0/S0/C02
• Any Enabled Wake Event
G2/Deep • G1/S3, G1/S4 or G2/S5 (see
• ACPRESENT Assertion
Sx Section 5.14.7.6.2)
• Mechanical Off/Power Failure
• G3
• S0/C0 (reboot) or G2/S54 (stay off until
G3 • Power Returns power button pressed or other wake
event)1,2
NOTES:
1. Some wake events can be preserved through power failure.
2. Transitions from the S1–S5 or G3 states to the S0 state are deferred until BATLOW# is
inactive in mobile configurations.
3. Includes all other applicable types of events that force the host into and stay in G2/S5.
4. If the system was in G1/S4 before G3 entry, then the system will go to S0/C0 or G1/S4.
198 Datasheet
Functional Description
5.14.3 System Power Planes
The system has several independent power planes, as described in Table 5-24. When a
particular power plane is shut off, it should go to a 0 V level.
Table 5-24. System Power Plane
Plane Controlled By Description
The SLP_S3# signal can be used to cut the power to the
Processor SLP_S3# signal
processor completely.
When SLP_S3# goes active, power can be shut off to any circuit
not required to wake the system from the S3 state. Since the S3
state requires that the memory context be preserved, power
Main SLP_S3# signal must be retained to the main memory.
The processor, devices on the PCI bus, LPC I/F, and graphics will
typically be shut off when the Main power plane is off, although
there may be small subsections powered.
When SLP_S4# goes active, power can be shut off to any circuit
not required to wake the system from the S4. Since the memory
context does not need to be preserved in the S4 state, the power
SLP_S4# signal to the memory can also be shut down.
Memory
SLP_S5# signal When SLP_S5# goes active, power can be shut off to any circuit
not required to wake the system from the S5 state. Since the
memory context does not need to be preserved in the S5 state,
the power to the memory can also be shut.
This signal is asserted when the manageability platform goes to
MOff. Depending on the platform, this pin may be used to control
Intel® ME SLP_A#
the Intel Management Engine power planes, LAN subsystem
power, and the SPI flash power.
This signal is asserted in Sx/Moff when both host and Intel ME
LAN SLP_LAN# WoL are not supported. This signal can be use to control power
to the Intel GbE PHY.
Suspend This signal is asserted when the Sus rails can be externally shut
SLP_SUS#
Well off for enhanced power saving.
Individual subsystems may have their own power plane. For
Implementation
DEVICE[n] example, GPIO signals may be used to control the power to disk
Specific
drives, audio amplifiers, or the display screen.
5.14.4 SMI# / SCI Generation
Upon any enabled SMI event taking place while the End of SMI (EOS) bit is set, the PCH
will clear the EOS bit and assert SMI to the processor, which will cause it to enter SMM
space. SMI assertion is performed using a Virtual Legacy Wire (VLW) message. Prior
system generations (those based upon legacy processors) used an actual SMI# pin.
Once the SMI VLW has been delivered, the PCH takes no action on behalf of active SMI
events until Host software sets the End of SMI (EOS) bit. At that point, if any SMI
events are still active, the PCH will send another SMI VLW message.
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating
system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the
8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed
to level mode for that interrupt.
Datasheet 199
Functional Description
In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or
23. The interrupt polarity changes depending on whether it is on an interrupt shareable
with a PIRQ or not (see Section 12.1.14). The interrupt remains asserted until all SCI
sources are removed.
Table 5-25 shows which events can cause an SMI and SCI. Some events can be
programmed to cause either an SMI or SCI. The usage of the event for SCI (instead of
SMI) is typically associated with an ACPI-based system. Each SMI or SCI source has a
corresponding enable and status bit.
Table 5-25. Causes of SMI and SCI (Sheet 1 of 3)
Cause SCI SMI Additional Enables Where Reported
PME# Yes Yes PME_EN=1 PME_STS
PME_B0 (Internal, Bus 0, PME-
Yes Yes PME_B0_EN=1 PME_B0_STS
Capable Agents)
PCI_EXP_EN=1
PCI Express* PME Messages Yes Yes PCI_EXP_STS
(Not enabled for SMI)
HOT_PLUG_EN=1
PCI Express Hot-Plug Message Yes Yes HOT_PLUG_STS
(Not enabled for SMI)
Power Button Press Yes Yes PWRBTN_EN=1 PWRBTN_STS
Power Button Override (Note 7) Yes No None PRBTNOR_STS
RTC Alarm Yes Yes RTC_EN=1 RTC_STS
Ring Indicate Yes Yes RI_EN=1 RI_STS
ACPI Timer overflow (2.34 sec.) Yes Yes TMROF_EN=1 TMROF_STS
GPI[x]_Route=10;
GPI[x]_EN=1
(SCI) GPI[x]_STS
Any GPI[15:0] Yes Yes
GPI[x]_Route=01; ALT_GPI[x]_SMI_STS
ALT_GPI[x]_SMI_EN=1
(SMI)
GPIO[27] Yes Yes GP27_EN=1 GP27_STS
TCO SCI Logic Yes No TCOSCI_EN=1 TCOSCI_STS
GPI[17] Route = 10
GP17_EN=1
(SCI); GP17_STS
GPIO[17] Yes Yes
GPI[17]_Route=01 ALT_GPI17_SMI_STS
ALT_GP17_SMI_EN=1
(SMI)
GPI[19] Route = 10
GP19_EN=1
(SCI); GP19_STS
GPIO[19] Yes Yes
GPI[19]_Route=01 ALT_GPI19_SMI_STS
ALT_GP19_SMI_EN=1
(SMI)
200 Datasheet
Functional Description
Table 5-25. Causes of SMI and SCI (Sheet 2 of 3)
Cause SCI SMI Additional Enables Where Reported
GPI[21] Route=10
GP21_EN=1
(SCI); GP21_STS
GPIO[21] Yes Yes
GPI[21]_Route=01 ALT_GPI21_SMI_STS
ALT_GP21_SMI_EN=1
(SMI)
GPI[22] Route = 10
GP22_EN=1
(SCI); GP22_STS
GPIO[22] Yes Yes
GPI[22]_Route=01 ALT_GPI22_SMI_STS
ALT_GP22_SMI_EN=1
(SMI)
GPI[43] Route = 10
GP43_EN=1
(SCI); GP43_STS
GPIO[43] Yes Yes
GPI[43]_Route=01 ALT_GPI43_SMI_STS
ALT_GP43_SMI_EN=1
(SMI)
GPI[56] Route = 10
GP56_EN=1
(SCI); GP56_STS
GPIO[56] Yes Yes
GPI[56]_Route=01 ALT_GPI56_SMI_STS
ALT_GP56_SMI_EN=1
(SMI)
GPI[57] Route = 10
GP57_EN=1
(SCI); GP57_STS
GPIO[57] Yes Yes
GPI[57]_Route=01 ALT_GPI57_SMI_STS
ALT_GP57_SMI_EN=1
(SMI)
GPI[60] Route = 10
GP60_EN=1
(SCI); GP60_STS
GPIO[60] Yes Yes
GPI[60]_Route=01 ALT_GPI60_SMI_STS
ALT_GP60_SMI_EN=1
(SMI)
TCO SCI message from processor Yes No None DMISCI_STS
TCO SMI Logic No Yes TCO_EN=1 TCO_STS
TCO SMI – No Yes None NEWCENTURY_STS
TCO SMI – TCO TIMEROUT No Yes None TIMEOUT
TCO SMI – OS writes to TCO_DAT_IN
No Yes None SW_TCO_SMI
register
TCO SMI – Message from processor No Yes None DMISMI_STS
TCO SMI – NMI occurred (and NMIs
No Yes NMI2SMI_EN=1 NMI2SMI_STS
mapped to SMI)
Datasheet 201
Functional Description
Table 5-25. Causes of SMI and SCI (Sheet 3 of 3)
Cause SCI SMI Additional Enables Where Reported
TCO SMI – INTRUDER# signal goes
No Yes INTRD_SEL=10 INTRD_DET
active
TCO SMI – Change of the BIOSWE
No Yes BLE=1 BIOSWR_STS
(D31:F0:DCh, Bit 0) bit from 0 to 1
TCO SMI – Write attempted to BIOS No Yes BIOSWE=1 BIOSWR_STS
BIOS_RLS written to Yes No GBL_EN=1 GBL_STS
GBL_RLS written to No Yes BIOS_EN=1 BIOS_STS
Write to B2h register No Yes APMC_EN = 1 APM_STS
Periodic timer expires No Yes PERIODIC_EN=1 PERIODIC_STS
64 ms timer expires No Yes SWSMI_TMR_EN=1 SWSMI_TMR_STS
Enhanced USB Legacy Support Event No Yes LEGACY_USB2_EN = 1 LEGACY_USB2_STS
Enhanced USB Intel Specific Event No Yes INTEL_USB2_EN = 1 INTEL_USB2_STS
Serial IRQ SMI reported No Yes None SERIRQ_SMI_STS
Device monitors match address in its
No Yes None DEVTRAP_STS
range
SMB_SMI_EN
SMBus Host Controller No Yes SMBus host status reg.
Host Controller Enabled
SMBus Slave SMI message No Yes None SMBUS_SMI_STS
SMBus SMBALERT# signal active No Yes None SMBUS_SMI_STS
SMBUS_SMI_STS
SMBus Host Notify message received No Yes HOST_NOTIFY_INTREN
HOST_NOTIFY_STS
(Mobile Only) BATLOW# assertion Yes Yes BATLOW_EN=1 BATLOW_STS
Access microcontroller 62h/66h No Yes MCSMI_EN MCSMI_STS
SLP_EN bit written to 1 No Yes SLP_SMI_EN=1 SLP_SMI_STS
SPI Command Completed No Yes None SPI_STS
Software Generated GPE Yes Yes SWGPE_EN=1 SWGPE_STS
USB Per-Port Registers Write Enable INTEL_USB2_EN=1, INTEL_USB2_STS, Write
No Yes
bit changes to 1 Write_Enable_SMI_Enable=1 Enable Status
GPIO Lockdown Enable bit changes
No Yes GPIO_UNLOCK_SMI_EN=1 GPIO_UNLOCK_SMI_STS
from ‘1’ to ‘0’
Wake Alarm Device Timer Yes Yes WADT_EN WADT_STS
NOTES:
1. SCI_EN must be 1 to enable SCI, except for BIOS_RLS. SCI_EN must be 0 to enable SMI.
2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).
3. GBL_SMI_EN must be 1 to enable SMI.
4. EOS must be written to 1 to re-enable SMI for the next 1.
5. The PCH must have SMI fully enabled when the PCH is also enabled to trap cycles. If SMI is not enabled in
conjunction with the trap enabling, then hardware behavior is undefined.
6. Only GPI[15:0] may generate an SMI or SCI.
7. When a power button override first occurs, the system will transition immediately to S5. The SCI will only
occur after the next wake to S0 if the residual status bit (PRBTNOR_STS) is not cleared prior to setting
SCI_EN.
8. GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set. Software must take great care not to
set the BIOS_RLS bit (which causes GBL_STS to be set) if the SCI handler is not in place.
202 Datasheet
Functional Description
5.14.4.1 PCI Express* SCI
PCI Express ports and the processor (using DMI) have the ability to cause PME using
messages. When a PME message is received, the PCH will set the PCI_EXP_STS bit. If
the PCI_EXP_EN bit is also set, the PCH can cause an SCI using the GPE1_STS register.
5.14.4.2 PCI Express* Hot-Plug
PCI Express has a Hot-Plug mechanism and is capable of generating a SCI using the
GPE1 register. It is also capable of generating an SMI. However, it is not capable of
generating a wake event.
5.14.5 C-States
PCH-based systems implement C-states by having the processor control the states. The
chipset exchanges messages with the processor as part of the C-state flow, but the
chipset does not directly control any of the processor impacts of C-states, such as
voltage levels or processor clocking. In addition to the messages, the PCH also provides
additional information to the processor using a sideband pin (PMSYNCH). All of the
legacy C-state related pins (STPCLK#, STP_CPU#, DPRSLP#, DPRSLPVR#, and so on)
do not exist on the PCH.
5.14.6 Dynamic 33 MHz Clock Control (Mobile Only)
The 33 MHz clock can be dynamically controlled independent of any other low-power
state. This control is accomplished using the CLKRUN# protocol and is transparent to
software.
The Dynamic 33MHz Clock control is handled using the following signal:
• CLKRUN#: Used by LPC peripherals or other legacy devices to request the system
33 MHz clock to run
5.14.6.1 Conditions for Checking the 33 MHz Clock
When there is a lack of activity, the PCH has the capability to stop the 33 MHz clocks to
conserve power. “Clock activity” is defined as any activity that would require the 33
MHz clock to be running.
Any of the following conditions will indicate that it is not okay to stop the 33 MHz
clock:
• Cycles on LPC
• SERIRQ activity
Behavioral Description
When there is a lack of activity (as defined above) for ninety 33 MHz clock cycles, the
PCH de-asserts (drive high) CLKRUN# for 1 clock and then tri-states the signal.
Datasheet 203
Functional Description
5.14.6.2 Conditions for Maintaining the 33MHz Clock
LPC or any other devices that wish to maintain the 33 MHz clock running will observe
the CLKRUN# signal de-asserted, and then must re-assert if (drive it low) within 92
clocks.
• When the PCH has tri-stated the CLKRUN# signal after de-asserting it, the PCH
then checks to see if the signal has been re-asserted (externally).
• After observing the CLKRUN# signal asserted for 1 clock, the PCH again starts
asserting the signal.
• If an internal device needs the PCI bus, the PCH asserts the CLKRUN# signal.
5.14.6.3 Conditions for Stopping the 33MHz Clock
• If no device drives CLKRUN# low within 93 clock cycles after it has been de-
asserted, the PCH will stop the 33 MHz clocks.
5.14.6.4 Conditions for Re-Starting the 33MHz Clock
• A peripheral asserts CLKRUN# to indicate that it needs the 33MHz clock re-started.
• Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the
PCH again starts driving CLKRUN# asserted.
If an internal source requests the clock to be re-started, the PCH re-asserts CLKRUN#,
then the PCH will start the 33 MHz clocks.
5.14.6.5 LPC Devices and CLKRUN#
If an LPC device (of any type) needs the 33 MHz clock, such as for LPC DMA or LPC
serial interrupt, then it can assert CLKRUN#. LPC devices running DMA or bus master
cycles will not need to assert CLKRUN#, since the PCH asserts it on their behalf.
The LDRQ# inputs are ignored by the PCH when the 33MHz clock is stopped to the LPC
devices in order to avoid misinterpreting the request.
5.14.7 Sleep States
5.14.7.1 Sleep State Overview
The PCH directly supports different sleep states (S1–S5), which are entered by
methods such as setting the SLP_EN bit or due to a Power Button press. The entry to
the Sleep states is based on several assumptions:
• The G3 state cannot be entered using any software mechanism. The G3 state
indicates a complete loss of power.
204 Datasheet
Functional Description
5.14.7.2 Initiating Sleep State
Sleep states (S1–S5) are initiated by:
• Masking interrupts, turning off all bus master enable bits, setting the desired type
in the SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts
to gracefully put the system into the corresponding Sleep state.
• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button
Override event. In this case the transition to the S5 state is less graceful, since
there are no dependencies on DMI messages from the processor or on clocks other
than the RTC clock.
• Assertion of the THRMTRIP# signal will cause a transition to the S5 state. This can
occur when system is in S0 or S1 state.
• Shutdown by integrated manageability functions (ASF / Intel AMT)
• Internal watchdog timer time-out events
Table 5-26. Sleep Types
Sleep Type Comment
System lowers the processor’s power consumption. No snooping is possible in this
S1
state.
The PCH asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical
S3 circuits. Power is only retained to devices needed to wake from this sleeping
state, as well as to the memory.
The PCH asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power
S4 to the memory subsystem. Only devices needed to wake from this state should be
powered.
S5 The PCH asserts SLP_S3#, SLP_S4# and SLP_S5#.
5.14.7.3 Exiting Sleep States
Sleep states (S1–S5) are exited based on Wake events. The Wake events forces the
system to a full on state (S0), although some non-critical subsystems might still be
shut off and have to be brought back manually. For example, the hard disk may be shut
off during a sleep state and have to be enabled using a GPIO pin before it can be used.
Upon exit from the PCH-controlled Sleep states, the WAK_STS bit is set. The possible
causes of Wake Events (and their restrictions) are shown in Table 5-27.
Note: ((Mobile Only) If the BATLOW# signal is asserted, the PCH does not attempt to wake
from an S1–S5 state, nor will it exit from Deep Sx state, even if the power button is
pressed. This prevents the system from waking when the battery power is insufficient
to wake the system. Wake events that occur while BATLOW# is asserted are latched by
the PCH, and the system wakes after BATLOW# is de-asserted.
Datasheet 205
Functional Description
Table 5-27. Causes of Wake Events (Sheet 1 of 2)
Wake from Wake from
Wake from Wake from S1, Sx After “Reset”
Cause How Enabled
S1, Sx Deep Sx Power Loss Types
(Note 1) (Note 2)
Set RTC_EN bit in PM1_EN
RTC Alarm Yes Yes Yes No
register.
Always enabled as Wake
Power Button Yes Yes Yes Yes
event.
GPE0_EN register
GPI[15:0] NOTE: GPIs that are in the
GPIO17, GPIO19, core well are not
GPIO21, GPIO22, capable of waking the Yes No No No
GPIO43, GPIO56, system from sleep
GPIO57, GPIO60 states when the core
well is not powered.
GPIO27
(Intel LAN Set GP27_EN in GPE0_EN
solution uses Yes Yes Yes Yes
Register.
GPIO27 for PHY
Wake)
Will use PME#. Wake enable
LAN Yes No Yes No
set with LAN logic.
Set RI_EN bit in GPE0_EN
RI# Yes No Yes No
register.
Event sets PME_B0_STS bit;
PM_B0_EN must be enabled.
Intel® High Can not wake from S5 state if
Yes No Yes No
Definition Audio it was entered due to power
failure or power button
override.
PME_B0_EN bit in GPE0_EN
Primary PME# Yes No Yes No
register.
Set PME_EN bit in GPE0_EN
Secondary PME# Yes No Yes No
register.
PCI_EXP_WAKE# PCI_EXP_WAKE bit. (Note 3) Yes Yes Yes No
Set PME_EN bit in GPE0_EN Yes (S1
SATA No Yes (S1 only) No
register. (Note 4) only)
Must use the PCI Express*
PCI_EXP PME WAKE# pin rather than Yes (S1
No Yes (S1 only) No
Message messages for wake from S3, only)
S4, or S5.
Always enabled as Wake
SMBALERT# Yes No Yes Yes
event.
Wake/SMI# command always
enabled as a Wake event.
SMBus Slave NOTE: SMBus Slave Message
Wake Message can wake the system Yes No Yes Yes
(01h) from S1–S5, as well as
from S5 due to Power
Button Override.
206 Datasheet
Functional Description
Table 5-27. Causes of Wake Events (Sheet 2 of 2)
Wake from Wake from
Wake from Wake from S1, Sx After “Reset”
Cause How Enabled
S1, Sx Deep Sx Power Loss Types
(Note 1) (Note 2)
HOST_NOTIFY_WKEN bit
SMBus Host SMBus Slave Command
Notify message register. Reported in the Yes No Yes Yes
received SMB_WAK_STS bit in the
GPEO_STS register.
Intel® ME Non- Always enabled as a wake
Yes No Yes Yes
Maskable Wake event.
Integrated WoL WoL Enable Override bit (in
Yes No Yes Yes
Enable Override Configuration Space).
Wake Alarm
WADT_EN in GPE0_EN Yes Yes No No
Device
NOTES:
1. This column represents what the PCH would honor as wake events but there may be
enabling dependencies on the device side which are not enabled after a power loss.
2. Reset Types include: Power Button override, Intel ME initiated power button override, Intel
ME initiated host partition reset with power down, Intel ME Watchdog Timer, SMBus
unconditional power down, processor thermal trip, PCH catastrophic temperature event.
3. When the WAKE# pin is active and the PCI Express device is enabled to wake the system,
the PCH will wake the platform.
4. SATA can only trigger a wake event in S1, but if PME is asserted prior to S3/S4/S5 entry and
software does not clear the PME_B0_STS, a wake event would still result.
It is important to understand that the various GPIs have different levels of functionality
when used as wake events. The GPIs that reside in the core power well can only
generate wake events from sleep states where the core well is powered. Also, only
certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits reside in
ACPI I/O space. Table 5-28 summarizes the use of GPIs as wake events.
Table 5-28. GPI Wake Events
GPI Power Well Wake From Notes
GPI[7:0] Core S1 ACPI Compliant
GPI[15:8] Suspend S1–S5 ACPI Compliant
The latency to exit the various Sleep states varies greatly and is heavily dependent on
power supply design, so much so that the exit latencies due to the PCH are
insignificant.
5.14.7.4 PCI Express* WAKE# Signal and PME Event Message
PCI Express ports can wake the platform from any sleep state (S1, S3, S4, or S5 or
Deep Sx) using the WAKE# pin. WAKE# is treated as a wake event, but does not cause
any bits to go active in the GPE_STS register.
PCI Express ports and the processor (using DMI) have the ability to cause PME using
messages. When a PME message is received, the PCH will set the PCI_EXP_STS bit.
Datasheet 207
Functional Description
5.14.7.5 Sx-G3-Sx, Handling Power Failures
Depending on when the power failure occurs and how the system is designed, different
transitions could occur due to a power failure.
The AFTERG3_EN bit provides the ability to program whether or not the system should
boot once power returns after a power loss event. If the policy is to not boot, the
system remains in an S5 state (unless previously in S4). There are only three possible
events that will wake the system after a power failure.
1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low
(G3 state), the PWRBTN_STS bit is reset. When the PCH exits G3 after power
returns (RSMRST# goes high), the PWRBTN# signal is already high (because VCC-
standBy goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0.
2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a
wake event, it is important to keep this signal powered during the power loss
event. If this signal goes low (active), when power returns the RI_STS bit is set and
the system interprets that as a wake event.
3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss.
Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.
The PCH monitors both PCH PWROK and RSMRST# to detect for power failures. If PCH
PWROK goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.
Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power
loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.
Table 5-29. Transitions Due to Power Failure
State at Power Failure AFTERG3_EN bit Transition When Power Returns
1 S5
S0, S1, S3
0 S0
1 S4
S4
0 S0
1 S5
S5
0 S0
1 Deep Sx1
Deep Sx
0 S0
NOTE:
1. Entry state to Deep Sx is preserved through G3 allowing resume from Deep Sx to take
appropriate path (that is, return to S3, S4 or S5).
5.14.7.6 Deep Sx
To minimize power consumption while in S3/S4/S5, the PCH supports a lower power,
lower featured version of these power states known as Deep Sx. In the Deep Sx state,
the Suspend wells are powered off, while the Deep Sx Well (DSW) remains powered. A
limited set of wake events are supported by the logic located in the DSW.
The Deep Sx capability and the SUSPWRDNACK pin functionality are mutually
exclusive.
208 Datasheet
Functional Description
5.14.7.6.1 Entry Into Deep Sx
A combination of conditions is required for entry into Deep Sx.
All of the following must be met:
1. Intel ME in Moff
2. AND either a or b as defined below:
a. ((DPS4_EN_AC AND S4) OR (DPS5_EN_AC AND S5)) (desktop only)
b. ((ACPRESENT = 0) AND ((DPS3_EN_DC AND S3) OR (DPS4_EN_DC AND S4) OR
(DPS5_EN_DC AND S5)))
Table 5-30. Supported Deep Sx Policy Configurations
DPS3_EN DPS3_EN DPS4_EN DPS4_EN DPS5_EN DPS5_EN
Configuration
_DC _AC _DC _AC _DC _AC
1: Enabled in S5 when on Battery
0 0 0 0 1 0
(ACPRESENT = 0)
2: Enabled in S5 (ACPRESENT
0 0 0 0 1 1
not considered) (desktop only)
3: Enabled in S4 and S5 when on
0 0 1 0 1 0
Battery (ACPRESENT = 0)
4: Enabled in S4 and S5
(ACPRESENT not considered) 0 0 1 1 1 1
(desktop only
5: Enabled in S3, S4 and S5
when on Battery 1 0 1 0 1 0
(ACPRESENT = 0)
6: Deep S3/S4/ S5 disabled 0 0 0 0 0 0
The PCH also performs a SUSWARN#/SUSACK# handshake to ensure the platform is
ready to enter Deep Sx. The PCH asserts SUSWARN# as notification that it is about to
enter Deep Sx. Before the PCH proceeds and asserts SLP_SUS#, the PCH waits for
SUSACK# to assert.
Datasheet 209
Functional Description
5.14.7.6.2 Exit from Deep Sx
While in Deep Sx, the PCH monitors and responds to a limited set of wake events (RTC
Alarm, Power Button, WAKE#, and GPIO27). Upon sensing an enabled Deep Sx wake
event, the PCH brings up the Suspend well by de-asserting SLP_SUS#.
Table 5-31. Deep Sx Wake Events
Event Enable
RTC Alarm RTC_DS_WAKE_DIS (RCBA+3318h:Bit 21)
Power Button Always enabled
GPIO27 GPIO27_EN (PMBASE+28h:Bit 35)
PCIe WAKE# pin PCIEXP_WAK_DIS
Wake Alarm Device WADT_EN
ACPRESENT has some behaviors that are different from the other Deep Sx wake
events. If the Intel ME has enabled ACPRESENT as a wake event, then it behaves just
like any other Intel ME Deep Sx wake event. However, even if ACPRESENT wakes are
not enabled, if the Host policies indicate that Deep Sx is only supported when on
battery, then ACPRESENT going high will cause the PCH to exit Deep Sx. In this case,
the Suspend wells gets powered up and the platform remains in S3/MOFF, S4/MOFF or
S5/MOFF. If ACPRESENT subsequently drops (before any Host or Intel ME wake events
are detected), the PCH will re-enter Deep Sx.
5.14.8 Event Input Signals and Their Usage
The PCH has various input signals that trigger specific events. This section describes
those signals and how they should be used.
5.14.8.1 PWRBTN# (Power Button)
The PCH PWRBTN# signal operates as a “Fixed Power Button” as described in the
Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a
16 ms de-bounce on the input. The state transition descriptions are included in
Table 5-32. The transitions start as soon as the PWRBTN# is pressed (but after the
debounce logic), and does not depend on when the Power Button is released.
Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled), the Power Button is not a wake event. Refer to the following Power Button
Override Function section for further details.
210 Datasheet
Functional Description
Table 5-32. Transitions Due to Power Button
Present
Event Transition/Action Comment
State
SMI or SCI generated
(depending on SCI_EN, Software typically initiates a
S0/Cx PWRBTN# goes low
PWRBTN_EN and Sleep state
GLB_SMI_EN)
Wake Event. Transitions to
S1–S5 PWRBTN# goes low Standard wakeup
S0 state
No effect since no power
G3 PWRBTN# pressed None
Not latched nor detected
PWRBTN# held low No dependence on processor
Unconditional transition to
S0–S4 for at least 4 (DMI Messages) or any other
S5 state
consecutive seconds subsystem
Power Button Override Function
If PWRBTN# is observed active for at least four consecutive seconds, the state machine
should unconditionally transition to the G2/S5 state, regardless of present state (S0–
S4), even if the PCH PWROK is not active. In this case, the transition to the G2/S5 state
should not depend on any particular response from the processor (such as, DMI
Messages), nor any similar dependency from any other subsystem.
The PWRBTN# status is readable to check if the button is currently being pressed or
has been released. The status is taken after the de-bounce, and is readable using the
PWRBTN_LVL bit.
Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has
occurred. The 4-second timer starts counting when the PCH is in a S0 state. If the
PWRBTN# signal is asserted and held active when the system is in a suspend state
(S1–S5), the assertion causes a wake event. Once the system has resumed to the S0
state, the 4-second timer starts.
Note: During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled by D31:F0:A4h Bit 3), the Power Button is not a wake event. As a result, it
is conceivable that the user will press and continue to hold the Power Button waiting for
the system to awake. Since a 4-second press of the Power Button is already defined as
an Unconditional Power down, the power button timer will be forced to inactive while
the power-cycle timer is in progress. Once the power-cycle timer has expired, the
Power Button awakes the system. Once the minimum SLP_S4# power cycle expires,
the Power Button must be pressed for another 4 to 5 seconds to create the Override
condition to S5.
Sleep Button
The Advanced Configuration and Power Interface, Version 2.0b defines an optional
Sleep button. It differs from the power button in that it only is a request to go from S0
to S1–S4 (not S5). Also, in an S5 state, the Power Button can wake the system, but the
Sleep Button cannot.
Although the PCH does not include a specific signal designated as a Sleep Button, one
of the GPIO signals can be used to create a “Control Method” Sleep Button. See the
Advanced Configuration and Power Interface, Version 2.0b for implementation details.
Datasheet 211
Functional Description
5.14.8.2 RI# (Ring Indicator)
The Ring Indicator can cause a wake event (if enabled) from the S1–S5 states.
Table 5-33 shows when the wake event is generated or ignored in different states. If in
the G0/S0/Cx states, the PCH generates an interrupt based on RI# active, and the
interrupt will be set up as a Break event.
Table 5-33. Transitions Due to RI# Signal
Present State Event RI_EN Event
S0 RI# Active X Ignored
0 Ignored
S1–S5 RI# Active
1 Wake Event
Note: Filtering/Debounce on RI# will not be done in PCH. Can be in modem or external.
5.14.8.3 PME# (PCI Power Management Event)
The PME# signal comes from a PCI Express* device to request that the system be
restarted. The PME# signal can generate an SMI#, SCI, or optionally a Wake event.
The event occurs when the PME# signal goes from high to low. No event is caused
when it goes from low to high.
There is also an internal PME_B0 bit. This is separate from the external PME# signal
and can cause the same effect.
5.14.8.4 SYS_RESET# Signal
When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the
PCH attempts to perform a “graceful” reset, by waiting up to 25 ms for the SMBus to go
idle. If the SMBus is idle when the pin is detected active, the reset occurs immediately;
otherwise, the counter starts. If at any point during the count the SMBus goes idle the
reset occurs. If, however, the counter expires and the SMBus is still active, a reset is
forced upon the system even though activity is still occurring.
Once the reset is asserted, it remains asserted for 5 to 6 ms regardless of whether the
SYS_RESET# input remains asserted or not. It cannot occur again until SYS_RESET#
has been detected inactive after the debounce logic, and the system is back to a full S0
state with PLTRST# inactive. If bit 3 of the CF9h I/O register is set, then SYS_RESET#
will result in a full power cycle reset.
5.14.8.5 THRMTRIP# Signal
If THRMTRIP# goes active, the processor is indicating an overheat condition, and the
PCH immediately transitions to an S5 state, driving SLP_S3#, SLP_S4#, SLP_S5# low,
and setting the CTS bit. The transition looks like a power button override.
When a THRMTRIP# event occurs, the PCH will power down immediately without
following the normal S0 -> S5 path. The PCH will immediately drive SLP_S3#,
SLP_S4#, and SLP_S5# low after sampling THRMTRIP# active.
If the processor is running extremely hot and is heating up, it is possible (although very
unlikely) that components around it, such as the PCH, are no longer executing cycles
properly. Therefore, if THRMTRIP# goes active, and the PCH is relying on state machine
logic to perform the power down, the state machine may not be working, and the
system will not power down.
212 Datasheet
Functional Description
The PCH provides filtering for short low glitches on the THRMTRIP# signal in order to
prevent erroneous system shut downs from noise. Glitches shorter than 25nsec are
ignored.
During boot, THRMTRIP# is ignored until SLP_S3#, PWROK, and PLTRST# are all ‘1’.
During entry into a powered-down state (due to S3, S4, S5 entry, power cycle reset,
and so on) THRMTRIP# is ignored until either SLP_S3# = 0, or PCH PWROK = 0, or
SYS_PWROK = 0.
Note: A thermal trip event will:
• Clear the PWRBTN_STS bit
• Clear all the GPE0_EN register bits
• Clear the SMB_WAK_STS bit only if SMB_SAK_STS was set due to SMBus slave
receiving message and not set due to SMBAlert
5.14.9 ALT Access Mode
Before entering a low power state, several registers from powered down parts may
need to be saved. In the majority of cases, this is not an issue, as registers have read
and write paths. However, several of the ISA compatible registers are either read only
or write only. To get data out of write-only registers, and to restore data into read-only
registers, the PCH implements an ALT access mode.
If the ALT access mode is entered and exited after reading the registers of the PCH
timer (8254), the timer starts counting faster (13.5 ms). The following steps listed
below can cause problems:
1. BIOS enters ALT access mode for reading the PCH timer related registers.
2. BIOS exits ALT access mode.
3. BIOS continues through the execution of other needed steps and passes control to
the operating system.
After getting control in step #3, if the operating system does not reprogram the system
timer again, the timer ticks may be happening faster than expected. For example
Microsoft* MS-DOS* and its associated software assume that the system timer is
running at 54.6 ms and as a result the time-outs in the software may be happening
faster than expected.
Operating systems (such as Microsoft Windows* 98 and Windows* 2000) reprogram
the system timer and therefore do not encounter this problem.
For other operating systems (such as Microsoft MS-DOS*), the BIOS should restore the
timer back to 54.6 ms before passing control to the operating system. If the BIOS is
entering ALT access mode before entering the suspend state it is not necessary to
restore the timer contents after the exit from ALT access mode.
Datasheet 213
Functional Description
5.14.9.1 Write Only Registers with Read Paths in ALT Access Mode
The registers described in Table 5-34 have read paths in ALT access mode. The access
number field in the table indicates which register will be returned per access to that
port.
Table 5-34. Write Only Registers with Read Paths in ALT Access Mode (Sheet 1 of 2)
Restore Data Restore Data
I/O # of I/O # of
Access Data Access Data
Addr Rds Addr Rds
DMA Chan 0 base address Timer Counter 0 status, bits
1 1
low byte [5:0]
00h 2
DMA Chan 0 base address Timer Counter 0 base count
2 2
high byte low byte
DMA Chan 0 base count low Timer Counter 0 base count
1 3
byte high byte
01h 2
DMA Chan 0 base count high Timer Counter 1 base count
2 40h 7 4
byte low byte
DMA Chan 1 base address Timer Counter 1 base count
1 5
low byte high byte
02h 2
DMA Chan 1 base address Timer Counter 2 base count
2 6
high byte low byte
DMA Chan 1 base count low Timer Counter 2 base count
1 7
byte high byte
03h 2
DMA Chan 1 base count high Timer Counter 1 status, bits
2 41h 1
byte [5:0]
DMA Chan 2 base address Timer Counter 2 status, bits
1 42h 1
low byte [5:0]
04h 2
DMA Chan 2 base address Bit 7 = NMI Enable,
2 70h 1
high byte Bits [6:0] = RTC Address
DMA Chan 2 base count low DMA Chan 5 base address
1 1
byte low byte
05h 2 C4h 2
DMA Chan 2 base count high DMA Chan 5 base address
2 2
byte high byte
DMA Chan 3 base address DMA Chan 5 base count low
1 1
low byte byte
06h 2 C6h 2
DMA Chan 3 base address DMA Chan 5 base count
2 2
high byte high byte
DMA Chan 3 base count low DMA Chan 6 base address
1 1
byte low byte
07h 2 C8h 2
DMA Chan 3 base count high DMA Chan 6 base address
2 2
byte high byte
214 Datasheet
Functional Description
Table 5-34. Write Only Registers with Read Paths in ALT Access Mode (Sheet 2 of 2)
Restore Data Restore Data
I/O # of I/O # of
Access Data Access Data
Addr Rds Addr Rds
DMA Chan 6 base count low
1 DMA Chan 0–3 Command2 1
byte
CAh 2
DMA Chan 6 base count
2 DMA Chan 0–3 Request 2
high byte
DMA Chan 0 Mode: DMA Chan 7 base address
3 1
Bits(1:0) = 00 low byte
08h 6 CCh 2
DMA Chan 1 Mode: DMA Chan 7 base address
4 2
Bits(1:0) = 01 high byte
DMA Chan 2 Mode: DMA Chan 7 base count low
5 1
Bits(1:0) = 10 byte
CEh 2
DMA Chan 3 Mode: Bits(1:0) DMA Chan 7 base count
6 2
= 11. high byte
1 PIC ICW2 of Master controller 1 DMA Chan 4–7 Command2
2 PIC ICW3 of Master controller 2 DMA Chan 4–7 Request
DMA Chan 4 Mode:
3 PIC ICW4 of Master controller 3
Bits(1:0) = 00
PIC OCW1 of Master D0h 6 DMA Chan 5 Mode:
4 4
controller1 Bits(1:0) = 01
PIC OCW2 of Master DMA Chan 6 Mode:
5 5
controller Bits(1:0) = 10
20h 12 PIC OCW3 of Master DMA Chan 7 Mode:
6 6
controller Bits(1:0) = 11.
7 PIC ICW2 of Slave controller
8 PIC ICW3 of Slave controller
9 PIC ICW4 of Slave controller
PIC OCW1 of Slave
10
controller1
11 PIC OCW2 of Slave controller
12 PIC OCW3 of Slave controller
NOTES:
1. The OCW1 register must be read before entering ALT access mode.
2. Bits 5, 3, 1, and 0 return 0.
Datasheet 215
Functional Description
5.14.9.2 PIC Reserved Bits
Many bits within the PIC are reserved, and must have certain values written in order for
the PIC to operate properly. Therefore, there is no need to return these values in ALT
access mode. When reading PIC registers from 20h and A0h, the reserved bits shall
return the values listed in Table 5-35.
Table 5-35. PIC Reserved Bits Return Values
PIC Reserved Bits Value Returned
ICW2(2:0) 000
ICW4(7:5) 000
ICW4(3:2) 00
ICW4(0) 0
OCW2(4:3) 00
OCW3(7) 0
OCW3(5) Reflects bit 6
OCW3(4:3) 01
5.14.9.3 Read Only Registers with Write Paths in ALT Access Mode
The registers described in Table 5-36 have write paths to them in ALT access mode.
Software restores these values after returning from a powered down state. These
registers must be handled special by software. When in normal mode, writing to the
base address/count register also writes to the current address/count register.
Therefore, the base address/count must be written first, then the part is put into ALT
access mode and the current address/count register is written.
Table 5-36. Register Write Accesses in ALT Access Mode
I/O Address Register Write Value
08h DMA Status Register for Channels 0–3
D0h DMA Status Register for Channels 4–7
216 Datasheet
Functional Description
5.14.10 System Power Supplies, Planes, and Signals
5.14.10.1 Power Plane Control with SLP_S3#,
SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN#
The SLP_S3# output signal can be used to cut power to the system core supply, since it
only goes active for the Suspend-to-RAM state (typically mapped to ACPI S3). Power
must be maintained to the PCH suspend well, and to any other circuits that need to
generate Wake signals from the Suspend-to-RAM state. During S3 (Suspend-to-RAM)
all signals attached to powered down plans will be tri-stated or driven low, unless they
are pulled using a pull-up resistor.
Cutting power to the core may be done using the power supply, or by external FETs on
the motherboard.
The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core
supply, as well as power to the system memory, since the context of the system is
saved on the disk. Cutting power to the memory may be done using the power supply,
or by external FETs on the motherboard.
The SLP_S4# output signal is used to remove power to additional subsystems that are
powered during SLP_S3#.
SLP_S5# output signal can be used to cut power to the system core supply, as well as
power to the system memory, since the context of the system is saved on the disk.
Cutting power to the memory may be done using the power supply, or by external FETs
on the motherboard.
SLP_A# output signal can be used to cut power to the Intel Management Engine and
SPI flash on a platform that supports the M3 state (for example, certain power policies
in Intel AMT).
SLP_LAN# output signal can be used to cut power to the external Intel® GbE PHY LAN
device.
5.14.10.2 SLP_S4# and Suspend-To-RAM Sequencing
The system memory suspend voltage regulator is controlled by the Glue logic. The
SLP_S4# signal should be used to remove power to system memory rather than the
SLP_S5# signal. The SLP_S4# logic in the PCH provides a mechanism to fully cycle the
power to the DRAM and/or detect if the power is not cycled for a minimum time.
Note: To use the minimum DRAM power-down feature that is enabled by the SLP_S4#
Assertion Stretch Enable bit (D31:F0:A4h Bit 3), the DRAM power must be controlled
by the SLP_S4# signal.
5.14.10.3 PWROK Signal
When asserted, PWROK is an indication to the PCH that its core well power rails are
powered and stable. PWROK can be driven asynchronously. When PCH PWROK is low,
the PCH asynchronously asserts PLTRST#. PWROK must not glitch, even if RSMRST# is
low.
It is required that the power associated with PCIe* have been valid for 99 ms prior to
PWROK assertion in order to comply with the 100 ms PCIe 2.0 specification on
PLTRST# de-assertion.
Note: SYS_RESET# is recommended for implementing the system reset button. This saves
external logic that is needed if the PWROK input is used. Additionally, it allows for
Datasheet 217
Functional Description
better handling of the SMBus and processor resets and avoids improperly reporting
power failures.
5.14.10.4 BATLOW# (Battery Low) (Mobile Only)
The BATLOW# input can inhibit waking from S3, S4, S5, and Deep Sx states if there is
not sufficient power. It also causes an SMI if the system is already in an S0 state.
5.14.10.5 SLP_LAN# Pin Behavior
The PCH controls the voltage rails into the external LAN PHY using the SLP_LAN# pin.
• The LAN PHY is always powered when the Host & ME systems are running.
— SLP_LAN#=’1’ whenever SLP_S3#=’1’ or SLP_A#=’1’.
• If the LAN PHY is required by ME in Sx/Moff or Deep Sx, ME must configure
SLP_LAN#=’1’ irrespective of the power source and the destination power state.
ME must be powered at least once after G3 to configure this.
• If the LAN PHY is required after a G3 transition, the host BIOS must set AG3_PP_EN
(B0:D31:F0:A2h bit 12).
• If the LAN PHY is required in Sx/Moff, the host BIOS must set SX_PP_EN
(B0:D31:F0:A2h bit 11).
• If the LAN PHY is required in Deep Sx, the host BIOS must keep DSX_PP_DIS
(B0:D31:F0:A2h bit 13) cleared.
• If the LAN PHY is not required if the source of power is battery, the host BIOS must
set DC_PP_DIS (B0:D31:F0:A2h bit 14).
Note: ME configuration of SLP_LAN# in Sx/Moff and Deep Sx is dependant on ME power
policy configuration.
The flow chart below shows how a decision is made to drive SLP_LAN# every time its
policy needs to be evaluated.
218 Datasheet
Functional Description
Figure 5-7. Conceptual Diagram of SLP_LAN#
State Transition Change
(Sx or Mx) or
ACPRESENT change
S0 or Sx/M3 or YES
ME configure WOL SLP_LAN#=1
Enabled
NO
NO
After G3
YES
NO NO
AG3_PP_EN=1 Sx_PP_EN=1 SLP_LAN#=0
YES
NO ACPRESENT or YES
not(DC_PP_DIS)
YES
YES Going to DeepSx
SLP_LAN#=0
and DSX_PP_DIS
AG3_PP_EN = After G3 PHY Power Enable
SX_PP_EN = SX PHY Power Enable (Regular SX entry)
NO DC_PP_DIS = On DC PHY Power Disable
DSX_PP_DIS = In Deep_SX PHY Power Disable
SLP_LAN#=1
Datasheet 219
Functional Description
5.14.10.6 SLP_WLAN# Pin Behavior
The PCH controls the voltage rails into the external wireless LAN PHY using the
SLP_WLAN# pin.
• The wireless LAN PHY is always powered when the Host is running.
— SLP_WLAN#=’1’ whenever SLP_S3#=’1’.
• If Wake on Wireless LAN (WoWLAN) is required from S3/S4/S5 states, the host
BIOS must set HOST_WLAN_PP_EN (RCBA+3318h bit 4).
• If ME has access to the Wireless LAN device
— The Wireless LAN device must always be powered as long as Intel ME is
powered. SLP_WLAN#=’1’ whenever SLP_A#=’1’.
— If Wake on Wireless LAN (WoWLAN) is required from Moff state, Intel ME will
configure SLP_WLAN#=’1’ in Sx/Moff.
Intel ME configuration of SLP_WLAN# in Sx/Moff is dependant on Intel ME power policy
configuration.
5.14.10.7 SUSPWRDNACK / SUSWARN# / GPIO30 Steady State Pin Behavior
The following tables summarize SUSPWRDNACK/SUSWARN#/GPIO30 pin behavior.
Table 5-37. SUSPWRDNACK / SUSWARN# / GPIO30 Pin Behavior
Deep Sx GPIO30 Pin Value in Pin Value in Pin Value in Pin Value
Support Setting S0 Sx/Moff Sx/M3 in Deep Sx
Depends on ME
power package
SUSPWRDNACK Not Support Native 0 0 OFF
and source
(note 1)
SUSWARN# Support Native 1 1 (note 2) 1 OFF
Don’t Care IN High-Z High-Z High-Z OFF
Depends on
GPIO30 Depends on Depends on
GPIO30
Don’t Care OUT GPIO30 output GPIO30 output OFF
output data
data value data value
value
NOTES:
1. PCH will drive SPDA pin based on ME power policy configuration.
2. If entering Deep Sx, pin will assert and become undriven ("Off") when suspend well drops
upon Deep Sx entry.
Table 5-38. SUSPWRDNACK during Reset
PIC Reserved Bits Value Returned
PCH initially drive to ‘0’ and then drive per ME power
Straight to S5
policy configuration.
5.14.10.8 RTCRST# and SRTCRST#
RTCRST# is used to reset PCH registers in the RTC Well to their default value. If a
jumper is used on this pin, it should only be pulled low when system is in the G3 state
and then replaced to the default jumper position. Upon booting, BIOS should recognize
that RTCRST# was asserted and clear internal PCH registers accordingly. It is
imperative that this signal not be pulled low in the S0 to S5 states.
220 Datasheet
Functional Description
SRTCRST# is used to reset portions of the Intel Management Engine and should not be
connected to a jumper or button on the platform. The only time this signal gets
asserted (driven low in combination with RTCRST#) should be when the coin cell
battery is removed or not installed and the platform is in the G3 state. Pulling this
signal low independently (without RTCRST# also being driven low) may cause the
platform to enter an indeterminate state. Similar to RTCRST#, it is imperative that
SRTCRST# not be pulled low in the S0 to S5 states.
See Figure 2-2 which demonstrates the proper circuit connection of these pins.
5.14.11 Legacy Power Management Theory of Operation
Instead of relying on ACPI software, legacy power management uses BIOS and various
hardware mechanisms. The scheme relies on the concept of detecting when individual
subsystems are idle, detecting when the whole system is idle, and detecting when
accesses are attempted to idle subsystems.
However, the operating system is assumed to be at least APM enabled. Without APM
calls, there is no quick way to know when the system is idle between keystrokes. The
PCH does not support burst modes.
5.14.11.1 APM Power Management (Desktop Only)
The PCH has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and
Enable register, generates an SMI once per minute. The SMI handler can check for
system activity by reading the DEVTRAP_STS register. If none of the system bits are
set, the SMI handler can increment a software counter. When the counter reaches a
sufficient number of consecutive minutes with no activity, the SMI handler can then put
the system into a lower power state.
If there is activity, various bits in the DEVTRAP_STS register will be set. Software clears
the bits by writing a 1 to the bit position.
The DEVTRAP_STS register allows for monitoring various internal devices, or Super I/O
devices (SP, PP, FDC) on LPC, keyboard controller accesses, or audio functions on LPC.
5.14.11.2 Mobile APM Power Management (Mobile Only)
In mobile systems, there are additional requirements associated with device power
management. To handle this, the PCH has specific SMI traps available. The following
algorithm is used:
1. The periodic SMI timer checks if a device is idle for the require time. If so, it puts
the device into a low-power state and sets the associated SMI trap.
2. When software (not the SMI handler) attempts to access the device, a trap occurs
(the cycle doesn’t really go to the device and an SMI is generated).
3. The SMI handler turns on the device and turns off the trap.
4. The SMI handler exits with an I/O restart. This allows the original software to
continue.
5.14.12 Reset Behavior
When a reset is triggered, the PCH will send a warning message to the processor to
allow the processor to attempt to complete any outstanding memory cycles and put
memory into a safe state before the platform is reset. When the processor is ready, it
will send an acknowledge message to the PCH. Once the message is received, the PCH
asserts PLTRST#.
Datasheet 221
Functional Description
The PCH does not require an acknowledge message from the processor to trigger
PLTRST#. A global reset will occur after 4 seconds if an acknowledge from the
processor is not received.
When the PCH causes a reset by asserting PLTRST#, its output signals will go to their
reset states as defined in Chapter 3.
A reset in which the host platform is reset and PLTRST# is asserted is called a Host
Reset or Host Partition Reset. Depending on the trigger, a host reset may also result in
power cycling (see Table 5-39 for details). If a host reset is triggered and the PCH times
out before receiving an acknowledge message from the processor, a Global Reset with
power cycle will occur.
A reset in which the host and Intel ME partitions of the platform are reset is called a
Global Reset. During a Global Reset, all PCH functionality is reset except RTC Power
Well backed information and Suspend well status, configuration, and functional logic for
controlling and reporting the reset. Intel ME and Host power back up after the power
cycle period.
Straight to S5 is another reset type where all power wells that are controlled by the
SLP_S3#, SLP_S4#, and SLP_A# pins, as well as SLP_S5# and SLP_LAN# (if pins are
not configured as GPIOs), are turned off. All PCH functionality is reset, except RTC
Power Well backed information and Suspend well status, configuration, and functional
logic for controlling and reporting the reset. The host stays there until a valid wake
event occurs.
Table 5-39 shows the various reset triggers.
Table 5-39. Causes of Host and Global Resets (Sheet 1 of 2)
Host Reset
Host Reset Global Reset Straight to S5
without
Trigger with Power with Power (Host Stays
Power
Cycle2 Cycle3 there)
Cycle1
Write of 0Eh to CF9h (RST_CNT Register) No Yes No (Note 4)
Write of 06h to CF9h (RST_CNT Register) Yes No No (Note 4)
SYS_RESET# Asserted and CF9h (RST_CNT Register) Bit
Yes No No (Note 4)
3=0
SYS_RESET# Asserted and CF9h (RST_CNT Register) Bit
No Yes No (Note 4)
3=1
SMBus Slave Message received for Reset with Power Cycle No Yes No (Note 4)
SMBus Slave Message received for Reset without Power
Yes No No (Note 4)
Cycle
SMBus Slave Message received for unconditional Power
No No No Yes
Down
TCO Watchdog Timer reaches zero two times Yes No No (Note 4)
Power Failure: PWROK signal goes inactive in S0/S1 or
No No Yes
DPWROK drops
SYS_PWROK Failure: SYS_PWROK signal goes inactive in
No No Yes
S0/S1
Processor Thermal Trip (THRMTRIP#) causes transition to
No No No Yes
S5 and reset asserts
PCH internal thermal sensors signals a catastrophic
No No No Yes
temperature condition
Power Button 4 second override causes transition to S5
No No No Yes
and reset asserts
Special shutdown cycle from processor causes CF9h-like
No Yes No (Note 4)
PLTRST# and CF9h (RST_CNT Register) Bit 3 = 1
222 Datasheet
Functional Description
Table 5-39. Causes of Host and Global Resets (Sheet 2 of 2)
Host Reset
Host Reset Global Reset Straight to S5
without
Trigger with Power with Power (Host Stays
Power
Cycle2 Cycle3 there)
Cycle1
Special shutdown cycle from processor causes CF9h-like
Yes No No (Note 4)
PLTRST# and CF9h (RST_CNT Register) Bit 3 = 0
Intel® Management Engine Triggered Host Reset without
Yes No No (Note 4)
power cycle
Intel Management Engine Triggered Host Reset with
No Yes No (Note 4)
power cycle
Intel Management Engine Triggered Power Button
No No No Yes
Override
Intel Management Engine Watchdog Timer Timeout No No No Yes
Intel Management Engine Triggered Global Reset No No Yes
Intel Management Engine Triggered Host Reset with
No Yes (Note 5) No (Note 4)
power down (host stays there)
PLTRST# Entry Time-out No No Yes
S3/4/5 Entry Timeout No No No Yes
PROCPWRGD Stuck Low No No Yes
Power Management Watchdog Timer No No No Yes
Intel Management Engine Hardware Uncorrectable Error No No No Yes
NOTES:
1. The PCH drops this type of reset request if received while the system is in S3/S4/S5.
2. PCH does not drop this type of reset request if received while system is in a software-
entered S3/S4/S5 state. However, the PCH will perform the reset without executing the
RESET_WARN protocol in these states.
3. The PCH does not send warning message to processor, reset occurs without delay.
4. Trigger will result in Global Reset with power cycle if the acknowledge message is not
received by the PCH.
5. The PCH waits for enabled wake event to complete reset.
Datasheet 223
Functional Description
5.15 System Management (D31:F0)
The PCH provides various functions to make a system easier to manage and to lower
the Total Cost of Ownership (TCO) of the system. Features and functions can be
augmented using external A/D converters and GPIO, as well as an external
microcontroller.
The following features and functions are supported by the PCH:
• Processor present detection
— Detects if processor fails to fetch the first instruction after reset
• Various Error detection (such as ECC Errors) indicated by host controller
— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt
• Intruder Detect input
— Can generate TCO interrupt or SMI# when the system cover is removed
— INTRUDER# allowed to go active in any power state, including G3
• Detection of bad BIOS Flash (FWH or Flash on SPI) programming
— Detects if data on first read is FFh (indicates that BIOS flash is not
programmed)
Note: Voltage ID from the processor can be read using GPI signals.
5.15.1 Theory of Operation
The System Management functions are designed to allow the system to diagnose failing
subsystems. The intent of this logic is that some of the system management
functionality can be provided without the aid of an external microcontroller.
5.15.1.1 Detecting a System Lockup
When the processor is reset, it is expected to fetch its first instruction. If the processor
fails to fetch the first instruction after reset, the TCO timer times out twice and the PCH
asserts PLTRST#.
5.15.1.2 Handling an Intruder
The PCH has an input signal, INTRUDER#, that can be attached to a switch that is
activated by the system’s case being open. This input has a two RTC clock debounce. If
INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the
TCO2_STS register. The INTRD_SEL bits in the TCO_CNT register can enable the PCH to
cause an SMI# or interrupt. The BIOS or interrupt handler can then cause a transition
to the S5 state by writing to the SLP_EN bit.
The software can also directly read the status of the INTRUDER# signal (high or low) by
clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPI
if the intruder function is not required.
If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written
as a 1, then the INTRD_DET bit will go to a 0 when INTRUDER# input signal goes
inactive. This is slightly different than a classic sticky bit, since most sticky bits would
remain active indefinitely when the signal goes active and would immediately go
inactive when a 1 is written to the bit.
Note: The INTRD_DET bit resides in the PCH’s RTC well, and is set and cleared synchronously
with the RTC clock. Thus, when software attempts to clear INTRD_DET (by writing a 1
224 Datasheet
Functional Description
to the bit location) there may be as much as two RTC clocks (about 65 µs) delay before
the bit is actually cleared. Also, the INTRUDER# signal should be asserted for a
minimum of 1 ms to ensure that the INTRD_DET bit will be set.
Note: If the INTRUDER# signal is still active when software attempts to clear the INTRD_DET
bit, the bit remains set and the SMI is generated again immediately. The SMI handler
can clear the INTRD_SEL bits to avoid further SMIs. However, if the INTRUDER# signal
goes inactive and then active again, there will not be further SMIs, since the
INTRD_SEL bits would select that no SMI# be generated.
5.15.1.3 Detecting Improper Flash Programming
The PCH can detect the case where the BIOS flash is not programmed. This results in
the first instruction fetched to have a value of FFh. If this occurs, the PCH sets the
BAD_BIOS bit. The BIOS flash may reside in FWH or flash on the SPI bus.
5.15.1.4 Heartbeat and Event Reporting using SMLink/SMBus
Heartbeat and event reporting using SMLink/SMBus is no longer supported. The Intel
AMT logic in the PCH can be programmed to generate an interrupt to the Intel
Management Engine (Intel ME) when an event occurs. The Intel ME will poll the TCO
registers to gather appropriate bits to send the event message to the Gigabit Ethernet
controller, if the Intel ME is programmed to do so.
Datasheet 225
Functional Description
5.15.2 TCO Modes
5.15.2.1 TCO Legacy / Compatible Mode
In TCO Legacy/Compatible mode, only the host SMBus is used. The TCO Slave is
connected to the host SMBus internally by default. In this mode, the Intel ME SMBus
controllers are not used and should be disabled by soft strap.
Figure 5-8. TCO Legacy/Compatible Mode SMBus Configuration
PCH
TCO Legacy/Compatible Mode
Intel ME SMBus
Controller 3 X
Intel ME SMBus X
Controller 2
Intel ME SMBus X
Controller 1
SPD PCI/PCIe*
uCtrl
(Slave) Device
SMBus
Host SMBus
Legacy Sensors
3rd Party
(Master or Slave
TCO Slave NIC
with ALERT)
In TCO Legacy/Compatible mode the PCH can function directly with an external LAN
controller or equivalent external LAN controller to report messages to a network
management console without the aid of the system processor. This is crucial in cases
where the processor is malfunctioning or cannot function due to being in a low-power
state. Table 5-40 includes a list of events that will report messages to the network
management console.
Table 5-40. Event Transitions that Cause Messages
Event Assertion? De-assertion? Comments
INTRUDER# pin Yes No Must be in “S1 or hung S0” state
Must be in “S1 or hung S0” state. The
THRM# pin Yes Yes THRM# pin is isolated when the core power
is off, thus preventing this event in S3–S5.
Watchdog Timer
Yes No (NA) “S1 or hung S0” state entered
Expired
GPIO[11]/
Yes Yes Must be in “S1 or hung S0” state
SMBALERT# pin
BATLOW# Yes Yes Must be in “S1 or hung S0” state
CPU_PWR_FLR Yes No “S1 or hung S0” state entered
NOTE: The GPIO11/SMBALERT# pin will trigger an event message (when enabled by the
GPIO11_ALERT_DISABLE bit) regardless of whether it is configured as a GPI or not.
226 Datasheet
Functional Description
5.15.2.2 Advanced TCO Mode
The PCH supports the Advanced TCO mode in which SMLink0 and SMLink1 are used in
addition to the host SMBus. See Figure 5-9 for more details. In this mode, the Intel ME
SMBus controllers must be enabled by soft strap in the flash descriptor.
SMLink0 is dedicated to integrated LAN use and when an Intel® GbE PHY LAN is
connected to SMLink0, a soft strap must be set to indicate that the PHY is connected to
SMLink0. The interface will be running at the frequency of up to 1 MHz depending on
different factors such as board routing or bus loading when the Fast Mode is enabled
using a soft strap.
SMLink1 is dedicated to Embedded Controller (EC) or Baseboard Management
Controller (BMC) use. In the case where a BMC is connected to SMLink1, the BMC
communicates with the Intel ME through the Intel ME SMBus connected to SMLink1.
The host and TCO slave communicate with BMC through SMBus.
Figure 5-9. Advanced TCO Mode
PCH
Advanced TCO Mode
Intel ME SMBus SMLink1 EC or
Controller 3 BMC
Intel ME SMBus
Controller 2 SMLink0 Intel®
I127LM/V
Intel ME SMBus
Controller 1
SPD PCIe* Device
(Slave)
Host SMBus
SMBus
Legacy Sensors
TCO Slave (Master or Slave
with ALERT)
Datasheet 227
Functional Description
5.16 General Purpose I/O (D31:F0)
The PCH contains up to 70 General Purpose Input/Output (GPIO) signals for Desktop
PCH and 75 General Purpose Input/Output (GPIO) for Mobile PCH. Each GPIO can be
configured as an input or output signal. The number of inputs and outputs varies
depending on the configuration. Following is a brief summary of GPIO features.
• Capability to mask Suspend well GPIOs from CF9h events (configured using
GP_RST_SEL registers)
• Added capability to program GPIO prior to switching to output
5.16.1 Power Wells
Some GPIOs exist in the suspend power plane. Care must be taken to make sure GPIO
signals are not driven high into powered-down planes. Some PCH GPIOs may be
connected to pins on devices that exist in the core well. If these GPIOs are outputs,
there is a danger that a loss of core power (PWROK low) or a Power Button Override
event results in the PCH driving a pin to a logic 1 to another device that is powered
down.
5.16.2 SMI# SCI and NMI Routing
The routing bits for GPIO[15:0] allow an input to be routed to SMI#, SCI, NMI or
neither. A bit can be routed to either an SMI# or an SCI, but not both.
5.16.3 Triggering
GPIO[15:0] have “sticky” bits on the input. Refer to the GPE0_STS register and the
ALT_GPI_SMI_STS register. As long as the signal goes active for at least 2 clock cycles,
the PCH keeps the sticky status bit active. The active level can be selected in the
GP_INV register. This does not apply to GPI_NMI_STS residing in GPIO I/O space.
If the system is in an S0 or an S1 state, the GPI inputs are sampled at 33 MHz, so the
signal only needs to be active for about 60 ns to be latched. In the S3–S5 states, the
GPI inputs are sampled at 32.768 kHz, and thus must be active for at least
61 microseconds to be latched.
Note: GPIs that are in the core well are not capable of waking the system from sleep states
where the core well is not powered.
If the input signal is still active when the latch is cleared, it will again be set. Another
edge trigger is not required. This makes these signals “level” triggered inputs.
5.16.4 GPIO Registers Lockdown
The following GPIO registers are locked down when the GPIO Lockdown Enable (GLE)
bit is set. The GLE bit resides in D31:F0:GPIO Control (GC) register.
• Offset 00h: GPIO_USE_SEL[31:0]
• Offset 04h: GP_IO_SEL[31:0]
• Offset 0Ch: GP_LVL[31:0]
• Offset 28h: GPI_NMI_EN[15:0]
• Offset 2Ch: GPI_INV[31:0]
• Offset 30h: GPIO_USE_SEL2[63:32]
• Offset 34h: GPI_IO_SEL2[63:32]
• Offset 38h: GP_LVL2[63:32]
• Offset 40h: GPIO_USE_SEL3[95:64]
• Offset 44h: GPI_IO_SEL3[95:64]
• Offset 48h: GP_LVL3[95:64]
• Offset 60h: GP_RST_SEL[31:0]
• Offset 64h: GP_RST_SEL2[63:32]
• Offset 68h: GP_RST_SEL3[95:64]
228 Datasheet
Functional Description
Note: All other GPIO registers not listed here are not to be locked by GLE.
Once these registers are locked down, they become Read-Only registers and any
software writes to these registers will have no effect. To unlock the registers, the GPIO
Lockdown Enable (GLE) bit is required to be cleared to ‘0’. When the GLE bit changes
from a ‘1’ to a ‘0’ a System Management Interrupt (SMI#) is generated if enabled.
Once the GPIO_UNLOCK_SMI bit is set, it can not be changed until a PLTRST# occurs.
This ensures that only BIOS can change the GPIO configuration. If the GLE bit is
cleared by unauthorized software, BIOS will set the GLE bit again when the SMI# is
triggered and these registers will continue to be locked down.
5.16.5 Serial POST Codes over GPIO
The PCH adds the extended capability allowing system software to serialize POST or
other messages on GPIO. This capability negates the requirement for dedicated
diagnostic LEDs on the platform.
5.16.5.1 Theory of Operation
For the PCH generation POST code serialization logic will be shared with GPIO. These
GPIOs will likely be shared with LED control offered by the Super I/O (SIO) component.
Figure 5-10 shows a likely configuration.
Figure 5-10. Serial Post over GPIO Reference Circuit
V_3P3_STBY
R
PCH SIO
LED
Note: The pull-up value is based on the brightness required.
The anticipated usage model is that either the PCH or the SIO can drive a pin low to
turn off an LED. In the case of the power LED, the SIO would normally leave its
corresponding pin in a high-Z state to allow the LED to turn on. In this state, the PCH
can blink the LED by driving its corresponding pin low and subsequently tri-stating the
buffer. The I/O buffer should not drive a ‘1’ when configured for this functionality and
should be capable of sinking 24 mA of current.
An external optical sensing device can detect the on/off state of the LED. By externally
post-processing the information from the optical device, the serial bit stream can be
recovered. The hardware will supply a ‘sync’ byte before the actual data transmission
to allow external detection of the transmit frequency. The frequency of transmission
should be limited to 1 transition every 1 s to ensure the detector can reliably sample
Datasheet 229
Functional Description
the on/off state of the LED. To allow flexibility in pull-up resistor values for power
optimization, the frequency of the transmission is programmable using the DRS field in
the GP_GB_CMDSTS register.
The serial bit stream is Manchester encoded. This choice of transmission ensures that a
transition will be seen on every clock. The 1 or 0 data is based on the transmission
happening during the high or low phase of the clock.
As the clock will be encoded within the data stream, hardware must ensure that the Z-
0 and 0-Z transitions are glitch-free. Driving the pin directly from a flop or through
glitch-free logic are possible methods to meet the glitch-free requirement.
A simplified hardware/software register interface provides control and status
information to track the activity of this block. Software enabling the serial blink
capability should implement an algorithm referenced below to send the serialized
message on the enabled GPIO.
1. Read the Go/Busy status bit in the GP_GB_CMDSTS register and verify it is cleared.
This will ensure that the GPIO is idled and a previously requested message is still
not in progress.
2. Write the data to serialize into the GP_GB_DATA register.
3. Write the DLS and DRS values into the GP_GB_CMDSTS register and set the Go bit.
This may be accomplished using a single write.
The reference diagram shows the LEDs being powered from the suspend supply. By
providing a generic capability that can be used both in the main and the suspend power
planes maximum flexibility can be achieved. A key point to make is that the PCH will
not unintentionally drive the LED control pin low unless a serialization is in progress.
System board connections utilizing this serialization capability are required to use the
same power plane controlling the LED as the PCH GPIO pin. Otherwise, the PCH GPIO
may float low during the message and prevent the LED from being controlled from the
SIO. The hardware will only be serializing messages when the core power well is
powered and the processor is operational.
Care should be taken to prevent the PCH from driving an active ‘1’ on a pin sharing the
serial LED capability. Since the SIO could be driving the line to 0, having the PCH drive
a 1 would create a high current path. A recommendation to avoid this condition
involves choosing a GPIO defaulting to an input. The GP_SER_BLINK register should be
set first before changing the direction of the pin to an output. This sequence ensures
the open-drain capability of the buffer is properly configured before enabling the pin as
an output.
5.16.5.2 Serial Message Format
In order to serialize the data onto the GPIO, an initial state of high-Z is assumed. The
SIO is required to have its LED control pin in a high-Z state as well to allow the PCH to
blink the LED (refer to the reference diagram).
The three components of the serial message include the sync, data, and idle fields. The
sync field is 7 bits of ‘1’ data followed by 1 bit of ‘0’ data. Starting from the high-Z state
(LED on) provides external hardware a known initial condition and a known pattern. In
case one or more of the leading 1 sync bits are lost, the 1s followed by 0 provide a
clear indication of ‘end of sync’. This pattern will be used to ‘lock’ external sampling
logic to the encoded clock.
The data field is shifted out with the highest byte first (MSB). Within each byte, the
most significant bit is shifted first (MSb).
230 Datasheet
Functional Description
The idle field is enforced by the hardware and is at least 2 bit times long. The hardware
will not clear the Busy and Go bits until this idle time is met. Supporting the idle time in
hardware prevents time-based counting in BIOS as the hardware is immediately ready
for the next serial code when the Go bit is cleared. The idle state is represented as a
high-Z condition on the pin. If the last transmitted bit is a 1, returning to the idle state
will result in a final 0-1 transition on the output Manchester data. Two full bit times of
idle correspond to a count of 4 time intervals (the width of the time interval is
controlled by the DRS field).
The following waveform shows a 1-byte serial write with a data byte of 5Ah. The
internal clock and bit position are for reference purposes only. The Manchester D is the
resultant data generated and serialized onto the GPIO. Since the buffer is operating in
open-drain mode the transitions are from high-Z to 0 and back.
Bit 7 6 5 4 3 2 1 0
Internal Clock
Manchester D
8-bit sync field 2 clk
(1111_1110) 5A data byte idle
Datasheet 231
Functional Description
5.17 SATA Host Controller (D31:F2, F5)
The SATA function in the PCH has three modes of operation to support different
operating system conditions. In the case of Native IDE enabled operating systems, the
PCH uses two controllers to enable all six ports of the bus. The first controller
(Device 31: Function 2) supports ports 0 – 3 and the second controller (Device 31:
Function 5) supports ports 4 and 5. When using a legacy operating system, only one
controller (Device 31: Function 2) is available that supports ports 0 – 3. In AHCI or
RAID mode, only one controller (Device 31: Function 2) is utilized enabling all six ports
and the second controller (Device 31: Function 5) shall be disabled.
The MAP register, Section 14.1.27, provides the ability to share PCI functions. When
sharing is enabled, all decode of I/O is done through the SATA registers. Device 31,
Function 1 (IDE controller) is hidden by software writing to the Function Disable
Register (D31, F0, Offset F2h, bit 1), and its configuration registers are not used.
The PCH SATA controllers feature six sets of interface signals (ports) that can be
independently enabled or disabled (they cannot be tri-stated or driven low). Each
interface is supported by an independent DMA controller.
The PCH SATA controllers interact with an attached mass storage device through a
register interface that is equivalent to that presented by a traditional IDE host adapter.
The host software follows existing standards and conventions when accessing the
register interface and follows standard command protocol conventions.
Note: SATA interface transfer rates are independent of UDMA mode settings. SATA interface
transfer rates will operate at the bus’s maximum speed, regardless of the UDMA mode
reported by the SATA device or the system BIOS.
5.17.1 SATA 6 Gb/s Support
The PCH supports SATA 6 Gb/s transfers with all capable SATA devices.
5.17.2 SATA Feature Support
Table 5-41. SATA Feature Support
PCH PCH
Feature (AHCI/RAID (AHCI/RAID
Disabled) Enabled)
Native Command Queuing (NCQ) N/A Supported
Auto Activate for DMA N/A Supported
Hot-Plug Support N/A Supported
Asynchronous Signal Recovery N/A Supported
6 Gb/s Transfer Rate Supported Supported
ATAPI Asynchronous Notification N/A Supported
Host & Link Initiated Power Management N/A Supported
Staggered Spin-Up Supported Supported
Command Completion Coalescing N/A N/A
External SATA N/A Supported
232 Datasheet
Functional Description
Table 5-42. SATA Features
Feature Description
Native Command Queuing Allows the device to reorder commands for more efficient data
(NCQ) transfers
Collapses a DMA Setup then DMA Activate sequence into a DMA
Auto Activate for DMA
Setup only
Allows for device detection without power being applied and
Hot-Plug Support ability to connect and disconnect devices without prior
notification to the system
Asynchronous Signal Provides a recovery from a loss of signal or establishing
Recovery communication after Hot-Plug
6 Gb/s Transfer Rate Capable of data transfers up to 6 Gb/s
ATAPI Asynchronous A mechanism for a device to send a notification to the host that
Notification the device requires attention
Host & Link Initiated Power Capability for the host controller or device to request Partial and
Management Slumber interface power states
Enables the host the ability to spin up hard drives sequentially
Staggered Spin-Up
to prevent power load problems on boot
Reduces interrupt and completion overhead by allowing a
Command Completion
specified number of commands to complete and then generating
Coalescing
an interrupt to process the commands
Technology that allows for an outside the box connection of up
External SATA
to 2 meters (when using the cable defined in SATA-IO)
5.17.3 Theory of Operation
5.17.3.1 Standard ATA Emulation
The PCH contains a set of registers that shadow the contents of the legacy IDE
registers. The behavior of the Command and Control Block registers, PIO, and DMA
data transfers, resets, and interrupts are all emulated.
Note: The PCH will assert INTR when the master device completes the EDD command
regardless of the command completion status of the slave device. If the master
completes EDD first, an INTR is generated and BSY will remain '1' until the slave
completes the command. If the slave completes EDD first, BSY will be '0' when the
master completes the EDD command and asserts INTR. Software must wait for busy to
clear (0) before completing an EDD command, as required by the ATA5 through ATA7
(T13) industry standards.
5.17.3.2 48-Bit LBA Operation
The SATA host controller supports 48-bit LBA through the host-to-device register FIS
when accesses are performed using writes to the task file. The SATA host controller will
ensure that the correct data is put into the correct byte of the host-to-device FIS.
There are special considerations when reading from the task file to support 48-bit LBA
operation. Software may need to read all 16-bits. Since the registers are only 8-bits
wide and act as a FIFO, a bit must be set in the device/control register, which is at
offset 3F6h for primary and 376h for secondary (or their native counterparts).
Datasheet 233
Functional Description
If software clears Bit 7 of the control register before performing a read, the last item
written will be returned from the FIFO. If software sets Bit 7 of the control register
before performing a read, the first item written will be returned from the FIFO.
5.17.4 SATA Swap Bay Support
The PCH provides for basic SATA swap bay support using the PSC register configuration
bits and power management flows. A device can be powered down by software and the
port can then be disabled, allowing removal and insertion of a new device.
Note: This SATA swap bay operation requires board hardware (implementation specific),
BIOS, and operating system support.
5.17.5 Hot-Plug Operation
The PCH supports Hot-Plug Surprise removal and Insertion Notification. An internal
SATA port with a Mechanical Presence Switch can support PARTIAL and SLUMBER with
Hot-Plug Enabled. Software can take advantage of power savings in the low power
states while enabling Hot-Plug operation. Refer to chapter 7 of the AHCI specification
for details.
5.17.6 Function Level Reset Support (FLR)
The SATA Host Controller supports the Function Level Reset (FLR) capability. The FLR
capability can be used in conjunction with Intel Virtualization Technology. FLR allows an
operating system in a Virtual Machine to have complete control over a device, including
its initialization, without interfering with the rest of the platform. The device provides a
software interface that enables the Operating System to reset the whole device as if a
platform reset was asserted.
5.17.6.1 FLR Steps
5.17.6.1.1 FLR Initialization
1. A FLR is initiated by software writing a ‘1’ to the Initiate FLR bit.
2. All subsequent requests targeting the Function will not be claimed and will be
Master Abort Immediate on the bus. This includes any configuration, I/O or
Memory cycles, however, the Function shall continue to accept completions
targeting the Function.
5.17.6.1.2 FLR Operation
The Function will Reset all configuration, I/O and memory registers of the Function
except those indicated otherwise and reset all internal states of the Function to the
default or initial condition.
5.17.6.1.3 FLR Completion
The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be
used to indicate to the software that the FLR reset is completed.
Note: From the time Initiate FLR bit is written to 1 software must wait at least 100 ms before
accessing the function.
234 Datasheet
Functional Description
5.17.7 Intel® Rapid Storage Technology (Intel RST®)
Configuration
The Intel Rapid Storage Technology (Intel RST) offers several diverse options for RAID
(redundant array of independent disks) to meet the needs of the end user. AHCI
support provides higher performance and alleviates disk bottlenecks by taking
advantage of the independent DMA engines that each SATA port offers in the PCH.
• RAID Level 0 performance scaling up to 6 drives, enabling higher throughput for
data intensive applications such as video editing.
• Data security is offered through RAID Level 1, which performs mirroring.
• RAID Level 10 provides high levels of storage performance with data protection,
combining the fault-tolerance of RAID Level 1 with the performance of RAID Level
0. By striping RAID Level 1 segments, high I/O rates can be achieved on systems
that require both performance and fault-tolerance. RAID Level 10 requires 4 hard
drives, and provides the capacity of two drives.
• RAID Level 5 provides highly efficient storage while maintaining fault-tolerance on
3 or more drives. By striping parity, and rotating it across all disks, fault tolerance
of any single drive is achieved while only consuming 1 drive worth of capacity. That
is, a 3 drive RAID 5 has the capacity of 2 drives, or a 4 drive RAID 5 has the
capacity of 3 drives. RAID 5 has high read transaction rates, with a medium write
rate. RAID 5 is well suited for applications that require high amounts of storage
while maintaining fault tolerance.
By using the PCH’s built-in Intel Rapid Storage Technology, there is no loss of PCI
resources (request/grant pair) or add-in card slot.
Intel Rapid Storage Technology (Intel RST) functionality requires the following items:
1. PCH SKU enabled for Intel Rapid Storage Technology (see Section 1.3)
2. Intel Rapid Storage Technology RAID Option ROM must be on the platform
3. Intel Rapid Storage Technology drivers, most recent revision.
4. At least two SATA hard disk drives (minimum depends on RAID configuration).
Intel Rapid Storage Technology is not available in the following configurations:
1. The SATA controller is in compatible mode.
2. The SATA controller is programmed in RAID mode, but the AIE bit (D31:F2:Offset
9Ch bit 7) is set to 1.
5.17.7.1 Intel® Rapid Storage Technology (Intel® RST) RAID Option ROM
The Intel Rapid Storage Technology RAID Option ROM is a standard PnP Option ROM
that is easily integrated into any System BIOS. When in place, it provides the following
three primary functions:
• Provides a text mode user interface that allows the user to manage the RAID
configuration on the system in a pre-operating system environment. Its feature set
is kept simple to keep size to a minimum, but allows the user to create & delete
RAID volumes and select recovery options when problems occur.
• Provides boot support when using a RAID volume as a boot disk. It does this by
providing Int13 services when a RAID volume needs to be accessed by MS-DOS
applications (such as NTLDR) and by exporting the RAID volumes to the System
BIOS for selection in the boot order.
• At each boot up, provides the user with a status of the RAID volumes and the
option to enter the user interface by pressing CTRL-I.
Datasheet 235
Functional Description
5.17.8 Intel® Smart Response Technology
Part of the Intel RST storage class driver feature set, Intel Smart Response Technology
implements storage I/O caching to provide users with faster response times for things
like system boot and application startup. On a traditional system, performance of these
operations is limited by the hard drive, particularly when there may be other I/O
intensive background activities running simultaneously, like system updates or virus
scans. Intel Smart Response Technology accelerates the system response experience
by putting frequently-used blocks of disk data on an SSD, providing dramatically faster
access to user data than the hard disk alone can provide. The user sees the full
capacity of the hard drive with the traditional single drive letter with overall system
responsiveness similar to what an SSD-only system provides.
See Section 1.3 for SKUs enabled for Intel Smart Response Technology.
5.17.9 Power Management Operation
Power management of the PCH SATA controller and ports will cover operations of the
host controller and the SATA wire.
5.17.9.1 Power State Mappings
The D0 PCI power management state for device is supported by the PCH SATA
controller.
SATA devices may also have multiple power states. From parallel ATA, three device
states are supported through ACPI. They are:
• D0 – Device is working and instantly available.
• D1 – Device enters when it receives a STANdBY IMMEDIATE command. Exit latency
from this state is in seconds
• D3 – From the SATA device’s perspective, no different than a D1 state, in that it is
entered using the STANdBY IMMEDIATE command. However, an ACPI method is
also called which will reset the device and then cut its power.
Each of these device states are subsets of the host controller’s D0 state.
Finally, SATA defines three PHY layer power states, which have no equivalent mappings
to parallel ATA. They are:
• PHY READY – PHY logic and PLL are both on and active
• Partial – PHY logic is powered, but in a reduced state. Exit latency is no longer
than 10 ns
• Slumber – PHY logic is powered, but in a reduced state. Exit latency can be up to
10 ms.
Since these states have much lower exit latency than the ACPI D1 and D3 states, the
SATA controller defines these states as sub-states of the device D0 state.
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Functional Description
5.17.9.2 Power State Transitions
5.17.9.2.1 Partial and Slumber State Entry/Exit
The partial and slumber states save interface power when the interface is idle. It would
be most analogous to CLKRUN# (in power savings, not in mechanism), where the
interface can have power saved while no commands are pending. The SATA controller
defines PHY layer power management (as performed using primitives) as a driver
operation from the host side, and a device proprietary mechanism on the device side.
The SATA controller accepts device transition types, but does not issue any transitions
as a host. All received requests from a SATA device will be ACKed.
When an operation is performed to the SATA controller such that it needs to use the
SATA cable, the controller must check whether the link is in the Partial or Slumber
states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the
SATA device must perform the same action.
5.17.9.2.2 Device D1, D3 States
These states are entered after some period of time when software has determined that
no commands will be sent to this device for some time. The mechanism for putting a
device in these states does not involve any work on the host controller, other then
sending commands over the interface to the device. The command most likely to be
used in ATA/ATAPI is the “STANdBY IMMEDIATE” command.
5.17.9.2.3 Host Controller D3HOT State
After the interface and device have been put into a low power state, the SATA host
controller may be put into a low power state. This is performed using the PCI power
management registers in configuration space. There are two very important aspects to
note when using PCI power management.
1. When the power state is D3, only accesses to configuration space are allowed. Any
attempt to access the memory or I/O spaces will result in master abort.
2. When the power state is D3, no interrupts may be generated, even if they are
enabled. If an interrupt status bit is pending when the controller transitions to D0,
an interrupt may be generated.
When the controller is put into D3, it is assumed that software has properly shut down
the device and disabled the ports. Therefore, there is no need to sustain any values on
the port wires. The interface will be treated as if no device is present on the cable, and
power will be minimized.
When returning from a D3 state, an internal reset will not be performed.
5.17.9.2.4 Non-AHCI Mode PME# Generation
When in non-AHCI mode (legacy mode) of operation, the SATA controller does not
generate PME#. This includes attach events (since the port must be disabled), or
interlock switch events (using the SATAGP pins).
5.17.9.3 SMI Trapping (APM)
D31:F2:Offset C0h (see Section 13.1.43) contain control for generating SMI# on
accesses to the IDE I/O spaces. These bits map to the legacy ranges (1F0–1F7h, 3F6h,
170–177h, and 376h) and native IDE ranges defined by PCMdBA, PCTLBA, SCMdBA an
SCTLBA. If the SATA controller is in legacy mode and is using these addresses,
accesses to one of these ranges with the appropriate bit set causes the cycle to not be
forwarded to the SATA controller, and for an SMI# to be generated. If an access to the
Bus-Master IDE registers occurs while trapping is enabled for the device being
Datasheet 237
Functional Description
accessed, then the register is updated, an SMI# is generated, and the device activity
status bits (Section 13.1.44) are updated indicating that a trap occurred.
5.17.10 SATA Device Presence
In legacy mode, the SATA controller does not generate interrupts based on Hot-Plug/
unplug events. However, the SATA PHY does know when a device is connected (if not in
a partial or slumber state), and it s beneficial to communicate this information to host
software as this will greatly reduce boot times and resume times.
The flow used to indicate SATA device presence is shown in Figure 5-11. The ‘PxE’ bit
refers to PCS.P[3:0]E bits, depending on the port being checked and the ‘PxP’ bits refer
to the PCS.P[3:0]P bits, depending on the port being checked. If the PCS/PxP bit is set
a device is present, if the bit is cleared a device is not present. If a port is disabled,
software can check to see if a new device is connected by periodically re-enabling the
port and observing if a device is present, if a device is not present it can disable the
port and check again later. If a port remains enabled, software can periodically poll
PCS.PxP to see if a new device is connected.
Figure 5-11. Flow for Port Enable / Device Present Bits
5.17.11 SATA LED
The SATALED# output is driven whenever the BSY bit is set in any SATA port. The
SATALED# is an active-low open-drain output. When SATALED# is low, the LED should
be active. When SATALED# is high, the LED should be inactive.
5.17.12 AHCI Operation
The PCH provides hardware support for Advanced Host Controller Interface (AHCI), a
programming interface for SATA host controllers developed through a joint industry
effort. AHCI defines transactions between the SATA controller and software and enables
advanced performance and usability with SATA. Platforms supporting AHCI may take
advantage of performance features such as no master/slave designation for SATA
devices—each device is treated as a master—and hardware assisted native command
238 Datasheet
Functional Description
queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires
appropriate software support (such as, an AHCI driver) and for some features,
hardware support in the SATA device or additional platform hardware.
The PCH supports all of the mandatory features of the Serial ATA Advanced Host
Controller Interface Specification, Revision 1.3 and many optional features, such as
hardware assisted native command queuing, aggressive power management, LED
indicator support, and Hot-Plug through the use of interlock switch support (additional
platform hardware and software may be required depending upon the implementation).
Note: For reliable device removal notification while in AHCI operation without the use of
interlock switches (surprise removal), interface power management should be disabled
for the associated port. See Section 7.3.1 of the AHCI Specification for more
information.
5.17.13 SGPIO Signals
The SGPIO signals, in accordance to the SFF-8485 specification, support per-port LED
signaling. These signals are not related to SATALED#, which allows for simplified
indication of SATA command activity. The SGPIO group interfaces with an external
controller chip that fetches and serializes the data for driving across the SGPIO bus.
The output signals then control the LEDs. This feature is only valid in AHCI/RAID mode.
Note: Intel does not validate all possible usage cases of this feature. Customers should
validate their specific design implementation on their own platforms.
5.17.13.1 Mechanism
The enclosure management for SATA Controller 1 (Device 31: Function 2) involves
sending messages that control LEDs in the enclosure. The messages for this function
are stored after the normal registers in the AHCI BAR, at Offset 580h bytes for the PCH
from the beginning of the AHCI BAR as specified by the EM_LOC global register
(Section 13.4.1.6).
Software creates messages for transmission in the enclosure management message
buffer. The data in the message buffer should not be changed if CTL.TM bit is set by
software to transmit an update message. Software should only update the message
buffer when CTL.TM bit is cleared by hardware otherwise the message transmitted will
be indeterminate. Software then writes a register to cause hardware to transmit the
message or take appropriate action based on the message content. The software
should only create message types supported by the controller, which is LED messages
for the PCH. If the software creates other non LED message types (such as, SAF-TE,
SES-2), the SGPIO interface may hang and the result is indeterminate.
During reset all SGPIO pins will be in tri-state state. The interface will continue staying
in tri-state state after reset until the first transmission occurs, when software programs
the message buffer and sets the transmit bit CTL.TM. The SATA host controller will
initiate the transmission by driving SCLOCK and at the same time driving the SLOAD to
“0‟ prior to the actual bit stream transmission. The Host will drive SLOAD low for at
least 5 SCLOCK then only start the bit stream by driving the SLOAD to high. SLOAD will
be driven high for 1 SCLOCK, followed by vendor-specific pattern that is default to
“0000” if software is yet to program the value. A total of 18-bit streams from 6 ports
(Port0, Port1, Port2, Port3, Port4 and Port5) of 3-bit per port LED message will be
transmitted on SDATAOUT0 pin after the SLOAD is driven high for 1 SCLOCK. Only 2
ports (port4, and port 5) of 6-bit total LED message follow by 12 bits of tri-state value
will be transmitted out on SDATAOUT1 pin.
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Functional Description
All the default LED message values will be high prior to software setting them, except
the Activity LED message that is configured to be hardware driven that will be
generated based on the activity from the respective port. All the LED message values
will be driven to ‘1’ for the port that is unimplemented as indicated in the Port
Implemented register regardless of the software programmed value through the
message buffer.
There are 2 different ways of resetting the PCH’s SGPIO interface, asynchronous reset
and synchronous reset. Asynchronous reset is caused by platform reset to cause the
SGPIO interface to be tri-state asynchronously. Synchronous reset is caused by setting
the CTL.RESET bit, clearing the GHC.AE bit or HBA reset, where Host Controller will
complete the existing full bit stream transmission then only tri-state all the SGPIO pins.
After the reset, both synchronous and asynchronous, the SGPIO pins will stay tri-
stated.
Note: The PCH Host Controller does not ensure that it will cause the target SGPIO device or
controller to be reset. Software is responsible to keep the PCH SGPIO interface in tri-
state for 2 second to cause a reset on the target of the SGPIO interface.
5.17.13.2 Message Format
Messages shall be constructed with a one DWord header that describes the message to
be sent followed by the actual message contents. The first DWord shall be constructed
as shown in the following table.
Table 5-43. Message Format
Bit Description
31:28 Reserved
Message Type (MTYPE): Specifies the type of the message.
The message types are:
0h = LED
27:24 1h = SAF-TE
2h = SES-2
3h = SGPIO (register based interface)
All other values reserved
Data Size (DSIZE): Specifies the data size in bytes. If the message (enclosure
services command) has a data buffer that is associated with it that is transferred, the
23:16 size of that data buffer is specified in this field. If there is no separate data buffer, this
field shall have a value of ‘0’. The data directly follows the message in the message
buffer. For the PCH, this value should always be ‘0’.
Message Size (MSIZE): Specifies the size of the message in bytes. The message size
15:8 does not include the one DWord header. A value of ‘0’ is invalid. For the PCH, the
message size is always 4 bytes.
7:0 Reserved
The SAF-TE, SES-2, and SGPIO message formats are defined in the corresponding
specifications, respectively. The LED message type is defined in Section 5.17.13.3. It is
the responsibility of software to ensure the content of the message format is correct. If
the message type is not programmed as 'LED' for this controller, the controller shall not
take any action to update its LEDs. For LED message type, the message size always
consists of 4 bytes.
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Functional Description
5.17.13.3 LED Message Type
The LED message type specifies the status of up to three LEDs. Typically, the usage for
these LEDs is activity, fault, and locate. Not all implementations necessarily contain all
LEDs (for example, some implementations may not have a locate LED). The message
identifies the HBA port number and the Port Multiplier port number that the slot status
applies to. If a Port Multiplier is not in use with a particular device, the Port Multiplier
port number shall be ‘0’. The format of the LED message type is defined in Table 5-44.
The LEDs shall retain their values until there is a following update for that particular
slot.
Table 5-44. Multi-activity LED Message Type
Byte Description
Value (VAL): This field describes the state of each LED for a particular location. There
are three LEDs that may be supported by the HBA. Each LED has 3 bits of control.
LED values are:
000b – LED shall be off
001b – LED shall be solid on as perceived by human eye
All other values reserved
The LED bit locations are:
Bits 2:0 – Activity LED (may be driven by hardware)
Bits 5:3 – Vendor Specific LED (such as locate)
Bits 8:6 - Vendor Specific LED (such as fault)
3-2
Bits 15:9 – Reserved
Vendor specific message is:
Bit 3:0 – Vendor Specific Pattern
Bit 15:4 – Reserved
NOTE: If Activity LED Hardware Driven (ATTR.ALHD) bit is set, host will output the
hardware LED value sampled internally and will ignore software written activity
value on bit [2:0]. Since the PCH Enclosure Management does not support port
multiplier based LED message, the LED message will be generated
independently based on respective port’s operation activity. Vendor specific LED
values Locate (Bits 5:3) and Fault (Bits 8:6) always are driven by software.
Port Multiplier Information: Specifies slot specific information related to Port
Multiplier.
Bits 3:0 specify the Port Multiplier port number for the slot that requires the status
1
update. If a Port Multiplier is not attached to the device in the affected slot, the Port
Multiplier port number shall be '0'. Bits 7:4 are reserved. The PCH does not support LED
messages for devices behind a Port MUltiplier. This byte should be 0.
HBA Information: Specifies slot specific information related to the HBA.
Bits 4:0 – HBA port number for the slot that requires the status update.
0 Bit 5 – If set to '1', value is a vendor specific message that applies to the entire
enclosure. If cleared to '0', value applies to the port specified in bits 4:0.
Bits 7:6 – Reserved
Datasheet 241
Functional Description
5.17.13.4 SGPIO Waveform
Figure 5-12. Serial Data transmitted over the SGPIO Interface
242 Datasheet
Functional Description
5.17.14 External SATA
The PCH supports external SATA. External SATA uses the SATA interface outside of the
system box. The usage model for this feature must comply with the Serial ATA II
Cables and Connectors Volume 2 Gold specification at www.sata-io.org. Intel validates
two configurations:
1. The cable-up solution involves an internal SATA cable that connects to the SATA
motherboard connector and spans to a back panel PCI bracket with an eSATA
connector. A separate eSATA cable is required to connect an eSATA device.
2. The back-panel solution involves running a trace to the I/O back panel and
connecting a device using an external SATA connector on the board.
5.18 High Precision Event Timers (HPET)
This function provides a set of timers that can be used by the operating system. The
timers are defined such that the operating system may be able to assign specific timers
to be used directly by specific applications. Each timer can be configured to cause a
separate interrupt.
The PCH provides eight timers. The timers are implemented as a single counter, and
each timer has its own comparator and value register. The counter increases
monotonically. Each individual timer can generate an interrupt when the value in its
value register matches the value in the main counter.
The registers associated with these timers are mapped to a memory space (much like
the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS
reports to the operating system the location of the register space. The hardware can
support an assignable decode space; however, the BIOS sets this space prior to
handing it over to the operating system. It is not expected that the operating system
will move the location of these timers once it is set by the BIOS.
5.18.1 Timer Accuracy
The timers are accurate over any 1 ms period to within 0.05% of the time specified in
the timer resolution fields.
Within any 100 microsecond period, the timer reports a time that is up to two ticks too
early or too late. Each tick is less than or equal to 100 ns, so this represents an error of
less than 0.2%.
The timer is monotonic. It does not return the same value on two consecutive reads
(unless the counter has rolled over and reached the same value).
The main counter is clocked by the 14.31818 MHz clock. The accuracy of the main
counter is as accurate as the 14.31818 MHz clock.
Datasheet 243
Functional Description
5.18.2 Interrupt Mapping
Mapping Option #1 (Legacy Replacement Option)
In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is set. This forces the
mapping found in Table 5-45.
Table 5-45. Legacy Replacement Routing
Timer 8259 Mapping APIC Mapping Comment
In this case, the 8254 timer will
0 IRQ0 IRQ2
not cause any interrupts
In this case, the RTC will not cause
1 IRQ8 IRQ8
any interrupts.
Per IRQ Routing
2&3 Per IRQ Routing Field
Field.
4, 5, 6, 7 not available not available
NOTE: The Legacy Option does not preclude delivery of IRQ0/IRQ8 using processor interrupts
messages.
Mapping Option #2 (Standard Option)
In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is 0. Each timer has its
own routing control. The interrupts can be routed to various interrupts in the 8259 or
I/O APIC. A capabilities field indicates which interrupts are valid options for routing. If a
timer is set for edge-triggered mode, the timers should not be shared with any legacy
interrupts.
For the PCH, the only supported interrupt values are as follows:
Timer 0 and 1: IRQ20, 21, 22 & 23 (I/O APIC only).
Timer 2: IRQ11 (8259 or I/O APIC) and IRQ20, 21, 22 & 23 (I/O APIC only).
Timer 3: IRQ12 (8259 or I/O APIC) and IRQ 20, 21, 22 & 23 (I/O APIC only).
Interrupts from Timer 4, 5, 6, 7 can only be delivered using processor message
interrupts.
Mapping Option #3 (Processor Message Option)
In this case, the interrupts are mapped directly to processor messages without going to
the 8259 or I/O (x) APIC. To use this mode, the interrupt must be configured to edge-
triggered mode. The Tn_PROCMSG_EN_CNF bit must be set to enable this mode.
When the interrupt is delivered to the processor, the message is delivered to the
address indicated in the Tn_PROCMSG_INT_ADDR field. The data value for the write
cycle is specified in the Tn_PROCMSG_INT_VAL field.
Notes:
1. The processor message interrupt delivery option has HIGHER priority and is
mutually exclusive to the standard interrupt delivery option. Thus, if the
Tn_PROCMSG_EN_CNF bit is set, the interrupts will be delivered directly to the
processor, rather than using the APIC or 8259.
The processor message interrupt delivery can be used even when the legacy mapping
is used.
244 Datasheet
Functional Description
5.18.3 Periodic versus Non-Periodic Modes
Non-Periodic Mode
Timer 0 is configurable to 32 (default) or 64-bit mode, whereas whereas Timers 1:7
only support 32-bit mode (See Section 20.1.5).
All of the timers support non-periodic mode.
Refer to Section 2.3.9.2.1 of the IA-PC HPET Specification for a description of this
mode.
Periodic Mode
Timer 0 is the only timer that supports periodic mode. Refer to Section 2.3.9.2.2 of the
IA-PC HPET Specification for a description of this mode.
The following usage model is expected:
1. Software clears the ENABLE_CNF bit to prevent any interrupts.
2. Software Clears the main counter by writing a value of 00h to it.
3. Software sets the TIMER0_VAL_SET_CNF bit.
4. Software writes the new value in the TIMER0_COMPARATOR_VAL register.
5. Software sets the ENABLE_CNF bit to enable interrupts.
The Timer 0 Comparator Value register cannot be programmed reliably by a single
64-bit write in a 32-bit environment except if only the periodic rate is being changed
during run-time. If the actual Timer 0 Comparator Value needs to be reinitialized, then
the following software solution will always work regardless of the environment:
1. Set TIMER0_VAL_SET_CNF bit.
2. Set the lower 32 bits of the Timer0 Comparator Value register.
3. Set TIMER0_VAL_SET_CNF bit.
4. Set the upper 32 bits of the Timer0 Comparator Value register.
5.18.4 Enabling the Timers
The BIOS or operating system PnP code should route the interrupts. This includes the
Legacy Rout bit, Interrupt Rout bit (for each timer), interrupt type (to select the edge
or level type for each timer)
The Device Driver code should do the following for an available timer:
1. Set the Overall Enable bit (Offset 10h, bit 0).
2. Set the timer type field (selects one-shot or periodic).
3. Set the interrupt enable.
4. Set the comparator value.
5.18.5 Interrupt Levels
Interrupts directed to the internal 8259s are active high. See Section 5.10 for
information regarding the polarity programming of the I/O APIC for detecting internal
interrupts.
Datasheet 245
Functional Description
If the interrupts are mapped to the 8259 or I/O APIC and set for level-triggered mode,
they can be shared with legacy interrupts. They may be shared although it is unlikely
for the operating system to attempt to do this.
If more than one timer is configured to share the same IRQ (using the
TIMERn_INT_ROUT_CNF fields), then the software must configure the timers to level-
triggered mode. Edge-triggered interrupts cannot be shared.
5.18.6 Handling Interrupts
If each timer has a unique interrupt and the timer has been configured for edge-
triggered mode, then there are no specific steps required. No read is required to
process the interrupt.
If a timer has been configured to level-triggered mode, then its interrupt must be
cleared by the software. This is done by reading the interrupt status register and
writing a 1 back to the bit position for the interrupt to be cleared.
Independent of the mode, software can read the value in the main counter to see how
much time has passed between when the interrupt was generated and when it was first
serviced.
If Timer 0 is set up to generate a periodic interrupt, the software can check to see how
much time remains until the next interrupt by checking the timer value register.
5.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors
A 32-bit timer can be read directly using processors that are capable of 32-bit or 64-bit
instructions. However, a 32-bit processor may not be able to directly read 64-bit timer.
A race condition comes up if a 32-bit processor reads the 64-bit register using two
separate 32-bit reads. The danger is that just after reading one half, the other half rolls
over and changes the first half.
If a 32-bit processor needs to access a 64-bit timer, it must first halt the timer before
reading both the upper and lower 32-bits of the timer. If a 32-bit processor does not
want to halt the timer, it can use the 64-bit timer as a 32-bit timer by setting the
TIMERn_32MODE_CNF bit. This causes the timer to behave as a 32-bit timer. The upper
32-bits are always 0.
Alternatively, software may do a multiple read of the counter while it is running.
Software can read the high 32 bits, then the low 32 bits, the high 32 bits again. If the
high 32 bits have not changed between the two reads, then a rollover has not
happened and the low 32 bits are valid. If the high 32 bits have changed between
reads, then the multiple reads are repeated until a valid read is performed.
Note: On a 64-bit platform, if software attempts a 64 bit read of the 64-bit counter, software
must be aware that some platforms may split the 64 bit read into two 32 bit reads. The
read maybe inaccurate if the low 32 bits roll over between the high and low reads.
246 Datasheet
Functional Description
5.19 USB EHCI Host Controllers (D29:F0 and D26:F0)
The PCH contains two Enhanced Host Controller Interface (EHCI) host controllers which
support up to fourteen USB 2.0 high-speed root ports. USB 2.0 allows data transfers up
to 480 Mb/s. USB 2.0 based Debug Port is also implemented in the PCH.
5.19.1 EHC Initialization
The following descriptions step through the expected PCH Enhanced Host Controller
(EHC) initialization sequence in chronological order, beginning with a complete power
cycle in which the suspend well and core well have been off.
5.19.1.1 BIOS Initialization
BIOS performs a number of platform customization steps after the core well has
powered up. Contact your Intel Field Representative for additional PCH BIOS
information.
5.19.1.2 Driver Initialization
See Chapter 4 of the Enhanced Host Controller Interface Specification for Universal
Serial Bus, Revision 1.0.
5.19.1.3 EHC Resets
In addition to the standard PCH hardware resets, portions of the EHC are reset by the
HCRESET bit and the transition from the D3HOT device power management state to the
D0 state. The effects of each of these resets are shown in the following table.
Table 5-46. EHC Resets
Reset Does Reset Does Not Reset Comments
Memory space
The HCRESET must only affect
registers except
registers that the EHCI driver
Structural Configuration
HCRESET bit set. controls. PCI Configuration space
Parameters (which registers.
and BIOS-programmed
is written by
parameters cannot be reset.
BIOS).
The D3-to-D0 transition must not
Software writes Core well registers Suspend well cause wake information (suspend
the Device Power (except BIOS- registers; BIOS- well) to be lost. It also must not
State from D3HOT programmed programmed core clear BIOS-programmed registers
(11b) to D0 (00b). registers). well registers. because BIOS may not be invoked
following the D3-to-D0 transition.
If the detailed register descriptions give exceptions to these rules, those exceptions
override these rules. This summary is provided to help explain the reasons for the reset
policies.
5.19.2 Data Structures in Main Memory
See Section 3 and Appendix B of the Enhanced Host Controller Interface Specification
for Universal Serial Bus, Revision 1.0 for details.
Datasheet 247
Functional Description
5.19.3 USB 2.0 Enhanced Host Controller DMA
The PCH USB 2.0 EHC implements three sources of USB packets. They are, in order of
priority on USB during each microframe:
1. The USB 2.0 Debug Port,
2. The Periodic DMA engine, and
3. The Asynchronous DMA engine.
The PCH always performs any currently-pending debug port transaction at the
beginning of a microframe, followed by any pending periodic traffic for the current
microframe. If there is time left in the microframe, then the EHC performs any pending
asynchronous traffic until the end of the microframe (EOF1). The debug port traffic is
only presented on Port 1 and Port 9, while the other ports are idle during this time.
5.19.4 Data Encoding and Bit Stuffing
See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.
5.19.5 Packet Formats
See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.
The PCH EHCI allows entrance to USB test modes, as defined in the USB 2.0
specification, including Test J, Test Packet, and so on. However, the PCH Test Packet
test mode interpacket gap timing may not meet the USB 2.0 specification.
5.19.6 USB 2.0 Interrupts and Error Conditions
Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial
Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that
cause them. All error conditions that the EHC detects can be reported through the EHCI
Interrupt status bits. Only PCH-specific interrupt and error-reporting behavior is
documented in this section. The EHCI Interrupts section must be read first, followed by
this section of the datasheet to fully comprehend the EHC interrupt and error-reporting
functionality.
• Based on the EHC Buffer sizes and buffer management policies, the Data Buffer
Error can never occur on the PCH.
• Master Abort and Target Abort responses from hub interface on EHC-initiated read
packets will be treated as Fatal Host Errors. The EHC halts when these conditions
are encountered.
• The PCH may assert the interrupts which are based on the interrupt threshold as
soon as the status for the last complete transaction in the interrupt interval has
been posted in the internal write buffers. The requirement in the Enhanced Host
Controller Interface Specification for Universal Serial Bus, Revision 1.0 (that the
status is written to memory) is met internally, even though the write may not be
seen on DMI before the interrupt is asserted.
• Since the PCH supports the 1024-element Frame List size, the Frame List Rollover
interrupt occurs every 1024 milliseconds.
• The PCH delivers interrupts using PIRQH#.
• The PCH does not modify the CERR count on an Interrupt IN when the “Do
Complete-Split” execution criteria are not met.
• For complete-split transactions in the Periodic list, the “Missed Microframe” bit does
not get set on a control-structure-fetch that fails the late-start test. If subsequent
accesses to that control structure do not fail the late-start test, then the “Missed
Microframe” bit will get set and written back.
248 Datasheet
Functional Description
5.19.6.1 Aborts on USB 2.0-Initiated Memory Reads
If a read initiated by the EHC is aborted, the EHC treats it as a fatal host error. The
following actions are taken when this occurs:
• The Host System Error status bit is set.
• The DMA engines are halted after completing up to one more transaction on the
USB interface.
• If enabled (by the Host System Error Enable), then an interrupt is generated.
• If the status is Master Abort, then the Received Master Abort bit in configuration
space is set.
• If the status is Target Abort, then the Received Target Abort bit in configuration
space is set.
• If enabled (by the SERR Enable bit in the function’s configuration space), then the
Signaled System Error bit in configuration bit is set.
5.19.7 USB 2.0 Power Management
5.19.7.1 Pause Feature
This feature allows platforms to dynamically enter low-power states during brief
periods when the system is idle (that is, between keystrokes). This is useful for
enabling power management features in the PCH. The policies for entering these states
typically are based on the recent history of system bus activity to incrementally enter
deeper power management states. Normally, when the EHC is enabled, it regularly
accesses main memory while traversing the DMA schedules looking for work to do; this
activity is viewed by the power management software as a non-idle system, thus
preventing the power managed states to be entered. Suspending all of the enabled
ports can prevent the memory accesses from occurring, but there is an inherent
latency overhead with entering and exiting the suspended state on the USB ports that
makes this unacceptable for the purpose of dynamic power management. As a result,
the EHCI software drivers are allowed to pause the EHC DMA engines when it knows
that the traffic patterns of the attached devices can afford the delay. The pause only
prevents the EHC from generating memory accesses; the SOF packets continue to be
generated on the USB ports (unlike the suspended state).
5.19.7.2 Suspend Feature
The Enhanced Host Controller Interface (EHCI) For Universal Serial Bus Specification,
Section 4.3 describes the details of Port Suspend and Resume.
5.19.7.3 ACPI Device States
The USB 2.0 function only supports the D0 and D3 PCI Power Management states.
Notes regarding the PCH implementation of the Device States:
1. The EHC hardware does not inherently consume any more power when it is in the
D0 state than it does in the D3 state. However, software is required to suspend or
disable all ports prior to entering the D3 state such that the maximum power
consumption is reduced.
2. In the D0 state, all implemented EHC features are enabled.
3. In the D3 state, accesses to the EHC memory-mapped I/O range will master abort.
Since the Debug Port uses the same memory range, the Debug Port is only
operational when the EHC is in the D0 state.
4. In the D3 state, the EHC interrupt must never assert for any reason. The internal
PME# signal is used to signal wake events, and so on.
5. When the Device Power State field is written to D0 from D3, an internal reset is
generated. See Section 5.19.1.3, “EHC Resets” for general rules on the effects of
this reset.
Datasheet 249
Functional Description
6. Attempts to write any other value into the Device Power State field other than 00b
(D0 state) and 11b (D3 state) will complete normally without changing the current
value in this field.
5.19.7.4 ACPI System States
The EHC behavior as it relates to other power management states in the system is
summarized in the following list:
• The System is always in the S0 state when the EHC is in the D0 state. However,
when the EHC is in the D3 state, the system may be in any power management
state (including S0).
• When in D0, the Pause feature (See Section 5.19.7.1) enables dynamic processor
low-power states to be entered.
• The PLL in the EHC is disabled when entering the S3/S4/S5 states (core power
turns off).
• All core well logic is reset in the S3/S4/S5 states.
5.19.8 USB 2.0 Legacy Keyboard Operation
The PCH must support the possibility of a keyboard downstream from either a full-
speed/low-speed or a high-speed port. The description of the legacy keyboard support
is unchanged from USB 1.1.
The EHC provides the basic ability to generate SMIs on an interrupt event, along with
more sophisticated control of the generation of SMIs.
5.19.9 USB 2.0 Based Debug Port
The PCH supports the elimination of the legacy COM ports by providing the ability for
debugger software to interact with devices on a USB 2.0 port.
High-level restrictions and features are:
• Operational before USB 2.0 drivers are loaded.
• Functions even when the port is disabled.
• Allows normal system USB 2.0 traffic in a system that may only have one USB port.
• Debug Port device (DPD) must be high-speed capable and connect directly to Port 1
and Port 9 on PCH-based systems (such as, the DPD cannot be connected to
Port 1/Port 9 through a hub. When a DPD is detected the PCH EHCI will bypass the
integrated Rate Matching Hub and connect directly to the port and the DPD.).
• Debug Port FIFO always makes forward progress (a bad status on USB is simply
presented back to software).
• The Debug Port FIFO is only given one USB access per microframe.
The Debug port facilitates operating system and device driver debug. It allows the
software to communicate with an external console using a USB 2.0 connection.
Because the interface to this link does not go through the normal USB 2.0 stack, it
allows communication with the external console during cases where the operating
system is not loaded, the USB 2.0 software is broken, or where the USB 2.0 software is
being debugged. Specific features of this implementation of a debug port are:
• Only works with an external USB 2.0 debug device (console)
• Implemented for a specific port on the host controller
• Operational anytime the port is not suspended AND the host controller is in D0
power state.
• Capability is interrupted when port is driving USB RESET
250 Datasheet
Functional Description
5.19.9.1 Theory of Operation
There are two operational modes for the USB debug port:
1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard
host controller driver. In Mode 1, the Debug Port controller is required to generate a
“keepalive” packets less than 2 ms apart to keep the attached debug device from
suspending. The keepalive packet should be a standalone 32-bit SYNC field.
2. Mode 2 is when the host controller is running (that is, host controller’s Run/Stop#
bit is 1). In Mode 2, the normal transmission of SOF packets will keep the debug
device from suspending.
Behavioral Rules
1. In both modes 1 and 2, the Debug Port controller must check for software
requested debug transactions at least every 125 microseconds.
2. If the debug port is enabled by the debug driver, and the standard host controller
driver resets the USB port, USB debug transactions are held off for the duration of
the reset and until after the first SOF is sent.
3. If the standard host controller driver suspends the USB port, then USB debug
transactions are held off for the duration of the suspend/resume sequence and until
after the first SOF is sent.
4. The ENABLED_CNT bit in the debug register space is independent of the similar
port control bit in the associated Port Status and Control register.
Table 5-47 shows the debug port behavior related to the state of bits in the debug
registers as well as bits in the associated Port Status and Control register.
Table 5-47. Debug Port Behavior
Port Run /
OWNER_CNT ENABLED_CT Suspend Debug Port Behavior
Enable Stop
Debug port is not being used. Normal
0 X X X X
operation.
Debug port is not being used. Normal
1 0 X X X
operation.
Debug port in Mode 1. SYNC keepalives sent
1 1 0 0 X
plus debug traffic
Debug port in Mode 2. SOF (and only SOF) is
sent as keepalive. Debug traffic is also sent.
1 1 0 1 X
No other normal traffic is sent out this port,
because the port is not enabled.
Invalid. Host controller driver should never
1 1 1 0 0 put controller into this state (enabled, not
running and not suspended).
1 1 1 0 1 Port is suspended. No debug traffic sent.
Debug port in Mode 2. Debug traffic is
1 1 1 1 0
interspersed with normal traffic.
1 1 1 1 1 Port is suspended. No debug traffic sent.
Datasheet 251
Functional Description
5.19.9.1.1 OUT Transactions
An Out transaction sends data to the debug device. It can occur only when the
following are true:
• The debug port is enabled
• The debug software sets the GO_CNT bit
• The WRITE_READ#_CNT bit is set
The sequence of the transaction is:
1. Software sets the appropriate values in the following bits:
— USB_ADDRESS_CNF
— USB_ENDPOINT_CNF
— DATA_BUFFER[63:0]
— TOKEN_PID_CNT[7:0]
— SEND_PID_CNT[15:8]
— DATA_LEN_CNT
— WRITE_READ#_CNT: (note: this will always be 1 for OUT transactions)
— GO_CNT: (note: this will always be 1 to initiate the transaction)
2. The debug port controller sends a token packet consisting of:
— SYNC
— TOKEN_PID_CNT field
— USB_ADDRESS_CNT field
— USB_ENDPOINT_CNT field
— 5-bit CRC field
3. After sending the token packet, the debug port controller sends a data packet
consisting of:
— SYNC
— SEND_PID_CNT field
— The number of data bytes indicated in DATA_LEN_CNT from the DATA_BUFFER
— 16-bit CRC
NOTE: A DATA_LEN_CNT value of 0 is valid in which case no data bytes would be
included in the packet.
4. After sending the data packet, the controller waits for a handshake response from
the debug device.
— If a handshake is received, the debug port controller:
a. Places the received PID in the RECEIVED_PID_STS field
b. Resets the ERROR_GOOD#_STS bit
c. Sets the DONE_STS bit
— If no handshake PID is received, the debug port controller:
a. Sets the EXCEPTION_STS field to 001b
b. Sets the ERROR_GOOD#_STS bit
c. Sets the DONE_STS bit
252 Datasheet
Functional Description
5.19.9.1.2 IN Transactions
An IN transaction receives data from the debug device. It can occur only when the
following are true:
• The debug port is enabled
• The debug software sets the GO_CNT bit
• The WRITE_READ#_CNT bit is reset
The sequence of the transaction is:
1. Software sets the appropriate values in the following bits:
— USB_ADDRESS_CNF
— USB_ENDPOINT_CNF
— TOKEN_PID_CNT[7:0]
— DATA_LEN_CNT
— WRITE_READ#_CNT: (note: this will always be 0 for IN transactions)
— GO_CNT: (note: this will always be 1 to initiate the transaction)
2. The debug port controller sends a token packet consisting of:
— SYNC
— TOKEN_PID_CNT field
— USB_ADDRESS_CNT field
— USB_ENDPOINT_CNT field
— 5-bit CRC field.
3. After sending the token packet, the debug port controller waits for a response from
the debug device.
If a response is received:
— The received PID is placed into the RECEIVED_PID_STS field
— Any subsequent bytes are placed into the DATA_BUFFER
— The DATA_LEN_CNT field is updated to show the number of bytes that were
received after the PID.
4. If a valid packet was received from the device that was one byte in length
(indicating it was a handshake packet), then the debug port controller:
— Resets the ERROR_GOOD#_STS bit
— Sets the DONE_STS bit
5. If a valid packet was received from the device that was more than one byte in
length (indicating it was a data packet), then the debug port controller:
— Transmits an ACK handshake packet
— Resets the ERROR_GOOD#_STS bit
— Sets the DONE_STS bit
6. If no valid packet is received, then the debug port controller:
— Sets the EXCEPTION_STS field to 001b
— Sets the ERROR_GOOD#_STS bit
— Sets the DONE_STS bit.
Datasheet 253
Functional Description
5.19.9.1.3 Debug Software
Enabling the Debug Port
There are two mutually exclusive conditions that debug software must address as part
of its startup processing:
• The EHCI has been initialized by system software
• The EHCI has not been initialized by system software
Debug software can determine the current ‘initialized’ state of the EHCI by examining
the Configure Flag in the EHCI USB 2.0 Command Register. If this flag is set, then
system software has initialized the EHCI. Otherwise, the EHCI should not be considered
initialized. Debug software will initialize the debug port registers depending on the
state of the EHCI. However, before this can be accomplished, debug software must
determine which root USB port is designated as the debug port.
Determining the Debug Port
Debug software can easily determine which USB root port has been designated as the
debug port by examining bits 20:23 of the EHCI Host Controller Structural Parameters
register. This 4-bit field represents the numeric value assigned to the debug port (that
is, 0001=port 1).
Debug Software Startup with Non-Initialized EHCI
Debug software can attempt to use the debug port if after setting the OWNER_CNT bit,
the Current Connect Status bit in the appropriate (See Determining the Debug Port
Presence) PORTSC register is set. If the Current Connect Status bit is not set, then
debug software may choose to terminate or it may choose to wait until a device is
connected.
If a device is connected to the port, then debug software must reset/enable the port.
Debug software does this by setting and then clearing the Port Reset bit the PORTSC
register. To ensure a successful reset, debug software should wait at least 50 ms before
clearing the Port Reset bit. Due to possible delays, this bit may not change to 0
immediately; reset is complete when this bit reads as 0. Software must not continue
until this bit reads 0.
If a high-speed device is attached, the EHCI will automatically set the Port Enabled/
Disabled bit in the PORTSC register and the debug software can proceed. Debug
software should set the ENABLED_CNT bit in the Debug Port Control/Status register,
and then reset (clear) the Port Enabled/Disabled bit in the PORTSC register (so that the
system host controller driver does not see an enabled port when it is first loaded).
Debug Software Startup with Initialized EHCI
Debug software can attempt to use the debug port if the Current Connect Status bit in
the appropriate (See Determining the Debug Port) PORTSC register is set. If the
Current Connect Status bit is not set, then debug software may choose to terminate or
it may choose to wait until a device is connected.
If a device is connected, then debug software must set the OWNER_CNT bit and then
the ENABLED_CNT bit in the Debug Port Control/Status register.
254 Datasheet
Functional Description
Determining Debug Peripheral Presence
After enabling the debug port functionality, debug software can determine if a debug
peripheral is attached by attempting to send data to the debug peripheral. If all
attempts result in an error (Exception bits in the Debug Port Control/Status register
indicates a Transaction Error), then the attached device is not a debug peripheral. If the
debug port peripheral is not present, then debug software may choose to terminate or
it may choose to wait until a debug peripheral is connected.
5.19.10 EHCI Caching
EHCI Caching is a power management feature in the USB (EHCI) host controllers which
enables the controller to execute the schedules entirely in cache and eliminates the
need for the DMA engine to access memory when the schedule is idle. EHCI caching
allows the processor to maintain longer C-state residency times and provides
substantial system power savings.
5.19.11 Intel® USB Pre-Fetch Based Pause
The Intel USB Pre-Fetch Based Pause is a power management feature in USB (EHCI)
host controllers to ensure maximum C3/C4 processor power state time with C2 popup.
This feature applies to the period schedule, and works by allowing the DMA engine to
identify periods of idleness and preventing the DMA engine from accessing memory
when the periodic schedule is idle. Typically in the presence of periodic devices with
multiple millisecond poll periods, the periodic schedule will be idle for several frames
between polls.
The Intel USB Pre-Fetch Based Pause feature is disabled by setting bit 4 of EHCI
Configuration Register Section 15.2.1.
5.19.12 Function Level Reset Support (FLR)
The USB EHCI Controllers support the Function Level Reset (FLR) capability. The FLR
capability can be used in conjunction with Intel Virtualization Technology. FLR allows an
Operating System in a Virtual Machine to have complete control over a device,
including its initialization, without interfering with the rest of the platform. The device
provides a software interface that enables the Operating System to reset the whole
device as if a platform reset was asserted.
5.19.12.1 FLR Steps
5.19.12.1.1 FLR Initialization
1. A FLR is initiated by software writing a ‘1’ to the Initiate FLR bit.
2. All subsequent requests targeting the Function will not be claimed and will be
Master Abort Immediate on the bus. This includes any configuration, I/O or
Memory cycles, however, the Function shall continue to accept completions
targeting the Function.
5.19.12.1.2 FLR Operation
The Function will Reset all configuration, I/O and memory registers of the Function
except those indicated otherwise and reset all internal states of the Function to the
default or initial condition.
Datasheet 255
Functional Description
5.19.12.1.3 FLR Completion
The Initiate FLR bit is reset (cleared) when the FLR reset is completed. This bit can be
used to indicate to the software that the FLR reset is completed.
Note: From the time Initiate FLR bit is written to 1, software must wait at least 100 ms before
accessing the function.
5.19.13 USB Overcurrent Protection
The PCH has implemented programmable USB Overcurrent signals. The PCH provides a
total of 8 overcurrent pins to be shared across the 14 USB 2.0 and 6 USB 3.0 ports.
Each pin is mapped to one or more ports by setting bits in the Over-Current Map
registers, depending on whether the port is mapped to EHCI or XHCI. Please refer to
the following sections for more details:
1. EHCI (USB 2.0 Ports): Section 5.19.13, “USB Overcurrent Protection” .
2. XHCI (USB 2.0 Ports): Section 16.1.32, “U2OCM1 - XHCI USB2 Overcurrent
Mapping Register1 (USB xHCI—D20:F0)” .
3. XHCI (USB 2.0 Ports): Section 16.1.33, “U2OCM2 - XHCI USB2 Overcurrent
Mapping Register 2 (USB xHCI—D20:F0)” .
4. XHCI (USB 3.0 Ports): Section 16.1.34, “U3OCM1 - XHCI USB3 Overcurrent Pin
Mapping 1 (USB xHCI—D20:F0)” .
5. XHCI (USB 3.0 Ports): Section 16.1.35, “U3OCM2 - XHCI USB3 Overcurrent Pin
Mapping 2 (USB xHCI—D20:F0)” .
It is system BIOS’ responsibility to ensure that each port is mapped to only one over
current pin. Operation with more than one overcurrent pin mapped to a port is
undefined. It is expected that multiple ports are mapped to a single overcurrent pin,
however they should be connected at the port and not at the PCH pin. Shorting these
pins together may lead to reduced test capabilities. By default, two ports are routed to
each of the OC[6:0]# pins. OC7# is not used by default.
NOTES:
1. All USB ports routed out of the package must have Overcurrent protection. It is
system BIOS responsibility to ensure all used ports have OC protection.
2. USB Ports that are either unused or only routed within the system (such as, that do
not connect to a walk-up port) should not have OC pins assigned to them.
5.20 Integrated USB 2.0 Rate Matching Hub
5.20.1 Overview
The PCH has integrated two USB 2.0 Rate Matching Hubs (RMH). One hub is connected
to each of the EHCI controllers as shown in Figure 5-13. The Hubs convert low and full-
speed traffic into high-speed traffic. When the RMHs are enabled, they will appear to
software like an external hub is connected to Port 0 of each EHCI controller. In addition,
port 1 of each of the RMHs is multiplexed with Port 1 of the EHCI controllers and is able
to bypass the RMH for use as the Debug Port.
The hub operates like any USB 2.0 Discrete Hub and will consume one tier of hubs
allowed by the USB 2.0 Specification. Section 4.1.1. A maximum of four additional non-
root hubs can be supported on any of the PCH USB Ports. The RMH will report the
following Vendor ID = 8087h and Product ID = 0024h.
256 Datasheet
Functional Description
Figure 5-13. EHCI with USB 2.0 with Rate Matching Hub
5.20.2 Architecture
A hub consists of three components: the Hub Repeater, the Hub Controller, and the
Transaction Translator.
1. The Hub Repeater is responsible for connectivity setup and tear-down. It also
supports exception handling, such as bus fault detection and recovery and connect/
disconnect detect.
2. The Hub Controller provides the mechanism for host-to-hub communication. Hub-
specific status and control commands permit the host to configure a hub and to
monitor and control its individual downstream facing ports.
3. The Transaction Translator (TT) responds to high-speed split transactions and
translates them to full-/low-speed transactions with full-/low-speed devices
attached on downstream facing ports. There is 1 TT per RMH in the PCH.
See chapter 11 of the USB 2.0 Specification for more details on the architecture of the
hubs.
5.21 xHCI Controller (D20:F0)
The PCH contains an eXtensible Host Controller Interface (xHCI) host controller which
supports up to 14 USB 2.0 ports of which up to 6 can be used as USB 3.0 ports with
board routing, ACPI table and BIOS considerations. This controller allows data transfers
of up to 5 Gb/s. The controller supports SuperSpeed (SS), high-speed (HS), full-speed
(FS) and low speed (LS) traffic on the bus.
The xHCI controller does not have a USB Debug port. If USB debug port functionality is
desired then the system SW must use the EHCI-based debug port discussed in
Section 5.19.9.
Note: Some USB 3.0 motherboard down devices do not require support for USB 2.0 speed
and it is possible to route only the SuperSpeed signals, as allowed by the USB 3.0
specification. In this special case, USB 2.0 and USB 3.0 signals will not need to be
paired together, thereby allowing support for more than 14 USB connections.
Datasheet 257
Functional Description
5.22 SMBus Controller (D31:F3)
The PCH provides an System Management Bus (SMBus) 2.0 host controller as well as
an SMBus Slave Interface. The host controller provides a mechanism for the processor
to initiate communications with SMBus peripherals (slaves). The PCH is also capable of
operating in a mode in which it can communicate with I2C compatible devices. The host
SMBus controller supports up to 100 KHz clock speed.
The PCH can perform SMBus messages with either packet error checking (PEC) enabled
or disabled. The actual PEC calculation and checking is performed in hardware by the
PCH.
The Slave Interface allows an external master to read from or write to the PCH. Write
cycles can be used to cause certain events or pass messages, and the read cycles can
be used to determine the state of various status bits. The PCH’s internal host controller
cannot access the PCH’s internal Slave Interface.
The PCH SMBus logic exists in D31:F3 configuration space, and consists of a transmit
data path, and host controller. The transmit data path provides the data flow logic
needed to implement the seven different SMBus command protocols and is controlled
by the host controller. The PCH’s SMBus controller logic is clocked by RTC clock.
The SMBus Address Resolution Protocol (ARP) is supported by using the existing host
controller commands through software, except for the Host Notify command (which is
actually a received message).
The programming model of the host controller is combined into two portions: a PCI
configuration portion, and a system I/O mapped portion. All static configuration, such
as the I/O base address, is done using the PCI configuration space. Real-time
programming of the Host interface is done in system I/O space.
The PCH SMBus host controller checks for parity errors as a target. If an error is
detected, the detected parity error bit in the PCI Status Register (D31:F3:Offset
06h:Bit 15) is set. If Bit 6 and Bit 8 of the PCI Command Register (D31:F3:Offset 04h)
are set, an SERR# is generated and the signaled SERR# bit in the PCI Status Register
(bit 14) is set.
5.22.1 Host Controller
The SMBus host controller is used to send commands to other SMBus slave devices.
Software sets up the host controller with an address, command, and, for writes, data
and optional PEC; and then tells the controller to start. When the controller has finished
transmitting data on writes, or receiving data on reads, it generates an SMI# or
interrupt, if enabled.
The host controller supports 8 command protocols of the SMBus interface (see System
Management Bus (SMBus) Specification, Version 2.0): Quick Command, Send Byte,
Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write, Block
Write–Block Read Process Call, and Host Notify.
The SMBus host controller requires that the various data and command fields be setup
for the type of command to be sent. When software sets the START bit, the SMBus Host
controller performs the requested transaction, and interrupts the processor (or
generates an SMI#) when the transaction is completed. Once a START command has
been issued, the values of the “active registers” (Host Control, Host Command,
Transmit Slave Address, Data 0, Data 1) should not be changed or read until the
interrupt status message (INTR) has been set (indicating the completion of the
command). Any register values needed for computation purposes should be saved prior
to issuing of a new command, as the SMBus host controller updates all registers while
completing the new command.
258 Datasheet
Functional Description
The PCH supports the System Management Bus (SMBus) Specification, Version 2.0.
Slave functionality, including the Host Notify protocol, is available on the SMBus pins.
The SMLink and SMBus signals can be tied together externally depending on TCO mode
used. Refer to Section 5.15.2 for more details.
Using the SMB host controller to send commands to the PCH SMB slave port is not
supported.
5.22.1.1 Command Protocols
In all of the following commands, the Host Status Register (offset 00h) is used to
determine the progress of the command. While the command is in operation, the
HOST_BUSY bit is set. If the command completes successfully, the INTR bit will be set
in the Host Status Register. If the device does not respond with an acknowledge, and
the transaction times out, the DEV_ERR bit is set. If software sets the KILL bit in the
Host Control Register while the command is running, the transaction will stop and the
FAILED bit will be set.
Quick Command
When programmed for a Quick Command, the Transmit Slave Address Register is sent.
The PEC byte is never appended to the Quick Protocol. Software should force the
PEC_EN bit to 0 when performing the Quick Command. Software must force the
I2C_EN bit to 0 when running this command. See Section 5.5.1 of the System
Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.
Send Byte / Receive Byte
For the Send Byte command, the Transmit Slave Address and Device Command
Registers are sent. For the Receive Byte command, the Transmit Slave Address Register
is sent. The data received is stored in the DATA0 register. Software must force the
I2C_EN bit to 0 when running this command.
The Receive Byte is similar to a Send Byte, the only difference is the direction of data
transfer. See Sections 5.5.2 and 5.5.3 of the System Management Bus (SMBus)
Specification, Version 2.0 for the format of the protocol.
Write Byte/Word
The first byte of a Write Byte/Word access is the command code. The next 1 or 2 bytes
are the data to be written. When programmed for a Write Byte/Word command, the
Transmit Slave Address, Device Command, and Data0 Registers are sent. In addition,
the Data1 Register is sent on a Write Word command. Software must force the I2C_EN
bit to 0 when running this command. See Section 5.5.4 of the System Management Bus
(SMBus) Specification, Version 2.0 for the format of the protocol.
Read Byte/Word
Reading data is slightly more complicated than writing data. First the PCH must write a
command to the slave device. Then it must follow that command with a repeated start
condition to denote a read from that device's address. The slave then returns 1 or 2
bytes of data. Software must force the I2C_EN bit to 0 when running this command.
When programmed for the read byte/word command, the Transmit Slave Address and
Device Command Registers are sent. Data is received into the DATA0 on the read byte,
and the DAT0 and DATA1 registers on the read word. See Section 5.5.5 of the System
Management Bus (SMBus) Specification, Version 2.0 for the format of the protocol.
Datasheet 259
Functional Description
Process Call
The process call is so named because a command sends data and waits for the slave to
return a value dependent on that data. The protocol is simply a Write Word followed by
a Read Word, but without a second command or stop condition.
When programmed for the Process Call command, the PCH transmits the Transmit
Slave Address, Host Command, DATA0 and DATA1 registers. Data received from the
device is stored in the DATA0 and DATA1 registers. The Process Call command with
I2C_EN set and the PEC_EN bit set produces undefined results. Software must force
either I2C_EN or PEC_EN to 0 when running this command. See Section 5.5.6 of the
System Management Bus (SMBus) Specification, Version 2.0 for the format of the
protocol.
Note: For process call command, the value written into bit 0 of the Transmit Slave Address
Register (SMB I/O register, Offset 04h) needs to be 0.
Note: If the I2C_EN bit is set, the protocol sequence changes slightly: the Command Code
(Bits 18:11 in the bit sequence) are not sent - as a result, the slave will not
acknowledge (Bit 19 in the sequence).
Block Read/Write
The PCH contains a 32-byte buffer for read and write data which can be enabled by
setting bit 1 of the Auxiliary Control register at offset 0Dh in I/O space, as opposed to a
single byte of buffering. This 32-byte buffer is filled with write data before
transmission, and filled with read data on reception. In the PCH, the interrupt is
generated only after a transmission or reception of 32 bytes, or when the entire byte
count has been transmitted/received.
Note: When operating in I2C* mode (I2C_EN bit is set), the PCH will never use the 32-byte
buffer for any block commands.
The byte count field is transmitted but ignored by the PCH as software will end the
transfer after all bytes it cares about have been sent or received.
For a Block Write, software must either force the I2C_EN bit or both the PEC_EN and
AAC bits to 0 when running this command.
The block write begins with a slave address and a write condition. After the command
code the PCH issues a byte count describing how many more bytes will follow in the
message. If a slave had 20 bytes to send, the first byte would be the number 20 (14h),
followed by 20 bytes of data. The byte count may not be 0. A Block Read or Write is
allowed to transfer a maximum of 32 data bytes.
When programmed for a block write command, the Transmit Slave Address, Device
Command, and Data0 (count) registers are sent. Data is then sent from the Block Data
Byte register; the total data sent being the value stored in the Data0 Register. On block
read commands, the first byte received is stored in the Data0 register, and the
remaining bytes are stored in the Block Data Byte register. See Section 5.5.7 of the
System Management Bus (SMBus) Specification, Version 2.0 for the format of the
protocol.
Note: For Block Write, if the I2C_EN bit is set, the format of the command changes slightly.
The PCH will still send the number of bytes (on writes) or receive the number of bytes
(on reads) indicated in the DATA0 register. However, it will not send the contents of the
DATA0 register as part of the message. Also, the Block Write protocol sequence
changes slightly: the Byte Count (bits 27:20 in the bit sequence) are not sent - as a
result, the slave will not acknowledge (bit 28 in the sequence).
260 Datasheet
Functional Description
I2C Read
This command allows the PCH to perform block reads to certain I2C* devices, such as
serial E2PROMs. The SMBus Block Read supports the 7-bit addressing mode only.
However, this does not allow access to devices using the I2C “Combined Format” that
has data bytes after the address. Typically these data bytes correspond to an offset
(address) within the serial memory chips.
Note: This command is supported independent of the setting of the I2C_EN bit. The I2C Read
command with the PEC_EN bit set produces undefined results. Software must force
both the PEC_EN and AAC bit to 0 when running this command.
For I2C Read command, the value written into bit 0 of the Transmit Slave Address
Register (SMB I/O register, offset 04h) needs to be 0.
The format that is used for the command is shown in Table 5-48.
Table 5-48. I2C* Block Read
Bit Description
1 Start
8:2 Slave Address – 7 bits
9 Write
10 Acknowledge from slave
18:11 Send DATA1 register
19 Acknowledge from slave
20 Repeated Start
27:21 Slave Address – 7 bits
28 Read
29 Acknowledge from slave
37:30 Data byte 1 from slave – 8 bits
38 Acknowledge
46:39 Data byte 2 from slave – 8 bits
47 Acknowledge
– Data bytes from slave / Acknowledge
– Data byte N from slave – 8 bits
– NOT Acknowledge
– Stop
The PCH will continue reading data from the peripheral until the NAK is received.
Datasheet 261
Functional Description
Block Write–Block Read Process Call
The block write-block read process call is a two-part message. The call begins with a
slave address and a write condition. After the command code the host issues a write
byte count (M) that describes how many more bytes will be written in the first part of
the message. If a master has 6 bytes to send, the byte count field will have the value 6
(0000 0110b), followed by the 6 bytes of data. The write byte count (M) cannot be 0.
The second part of the message is a block of read data beginning with a repeated start
condition followed by the slave address and a Read bit. The next byte is the read byte
count (N), which may differ from the write byte count (M). The read byte count (N)
cannot be 0.
The combined data payload must not exceed 32 bytes. The byte length restrictions of
this process call are summarized as follows:
• M 1 byte
• N 1 byte
• M + N 32 bytes
The read byte count does not include the PEC byte. The PEC is computed on the total
message beginning with the first slave address and using the normal PEC
computational rules. It is highly recommended that a PEC byte be used with the Block
Write-Block Read Process Call. Software must do a read to the command register
(offset 2h) to reset the 32 byte buffer pointer prior to reading the block data register.
There is no STOP condition before the repeated START condition, and that a NACK
signifies the end of the read transfer.
Note: E32B bit in the Auxiliary Control register must be set when using this protocol.
See Section 5.5.8 of the System Management Bus (SMBus) Specification, Version 2.0
for the format of the protocol.
5.22.2 Bus Arbitration
Several masters may attempt to get on the bus at the same time by driving the
SMBDATA line low to signal a start condition. The PCH continuously monitors the
SMBDATA line. When the PCH is attempting to drive the bus to a 1 by letting go of the
SMBDATA line, and it samples SMBDATA low, then some other master is driving the bus
and the PCH will stop transferring data.
If the PCH sees that it has lost arbitration, the condition is called a collision. The PCH
will set the BUS_ERR bit in the Host Status Register, and if enabled, generate an
interrupt or SMI#. The processor is responsible for restarting the transaction.
When the PCH is a SMBus master, it drives the clock. When the PCH is sending address
or command as an SMBus master, or data bytes as a master on writes, it drives data
relative to the clock it is also driving. It will not start toggling the clock until the start or
stop condition meets proper setup and hold time. The PCH will also ensure minimum
time between SMBus transactions as a master.
Note: The PCH supports the same arbitration protocol for both the SMBus and the System
Management (SMLink) interfaces.
262 Datasheet
Functional Description
5.22.3 Bus Timing
5.22.3.1 Clock Stretching
Some devices may not be able to handle their clock toggling at the rate that the PCH as
an SMBus master would like. They have the capability of stretching the low time of the
clock. When the PCH attempts to release the clock (allowing the clock to go high), the
clock will remain low for an extended period of time.
The PCH monitors the SMBus clock line after it releases the bus to determine whether
to enable the counter for the high time of the clock. While the bus is still low, the high
time counter must not be enabled. Similarly, the low period of the clock can be
stretched by an SMBus master if it is not ready to send or receive data.
5.22.3.2 Bus Time Out (The PCH as SMBus Master)
If there is an error in the transaction, such that an SMBus device does not signal an
acknowledge, or holds the clock lower than the allowed time-out time, the transaction
will time out. The PCH will discard the cycle and set the DEV_ERR bit. The time out
minimum is 25 ms (800 RTC clocks). The time-out counter inside the PCH will start
after the last bit of data is transferred by the PCH and it is waiting for a response.
The 25-ms time-out counter will not count under the following conditions:
1. BYTE_DONE_STATUS bit (SMBus I/O Offset 00h, Bit 7) is set
2. The SECOND_TO_STS bit (TCO I/O Offset 06h, Bit 1) is not set (this indicates that
the system has not locked up).
5.22.4 Interrupts / SMI#
The PCH SMBus controller uses PIRQB# as its interrupt pin. However, the system can
alternatively be set up to generate SMI# instead of an interrupt, by setting the
SMBUS_SMI_EN bit (D31:F0:Offset 40h:Bit 1).
Table 5-50 and Table 5-51 specify how the various enable bits in the SMBus function
control the generation of the interrupt, Host and Slave SMI, and Wake internal signals.
The rows in the tables are additive, which means that if more than one row is true for a
particular scenario then the Results for all of the activated rows will occur.
Table 5-49. Enable for SMBALERT#
SMB_SMI_EN
INTREN (Host (Host SMBALERT_DIS
Control I/O Configuration (Slave Command I/
Event Result
Register, Offset Register, O Register, Offset
02h, Bit 0) D31:F3:Offset 40h, 11h, Bit 2)
Bit 1)
SMBALERT# X X X Wake generated
asserted low
Slave SMI# generated
(always reported in X 1 0
(SMBUS_SMI_STS)
Host Status
Register, Bit 5) 1 0 0 Interrupt generated
Datasheet 263
Functional Description
Table 5-50. Enables for SMBus Slave Write and SMBus Host Events
SMB_SMI_EN (Host
INTREN (Host
Configuration Register,
Event Control I/O Register, Event
D31:F3:Offset 40h,
Offset 02h, Bit 0)
Bit 1)
Wake generated when asleep.
Slave Write to Wake/
X X Slave SMI# generated when
SMI# Command
awake (SMBUS_SMI_STS).
Slave Write to
Slave SMI# generated when in
SMLINK_SLAVE_SMI X X
the S0 state (SMBUS_SMI_STS)
Command
0 X None
Any combination of Host
Status Register [4:1] 1 0 Interrupt generated
asserted
1 1 Host SMI# generated
Table 5-51. Enables for the Host Notify Command
HOST_NOTIFY_INTRE SMB_SMI_EN (Host HOST_NOTIFY_WKEN
N (Slave Control I/O Config Register, (Slave Control I/O
Result
Register, Offset 11h, D31:F3:Off40h, Register, Offset 11h,
Bit 0) Bit 1) Bit 1)
0 X 0 None
X X 1 Wake generated
1 0 X Interrupt generated
Slave SMI# generated
1 1 X
(SMBUS_SMI_STS)
5.22.5 SMBALERT#
SMBALERT# is multiplexed with GPIO[11]. When enable and the signal is asserted, the
PCH can generate an interrupt, an SMI#, or a wake event from S1–S5.
5.22.6 SMBus CRC Generation and Checking
If the AAC bit is set in the Auxiliary Control register, the PCH automatically calculates
and drives CRC at the end of the transmitted packet for write cycles, and will check the
CRC for read cycles. It will not transmit the contents of the PEC register for CRC. The
PEC bit must not be set in the Host Control register if this bit is set, or unspecified
behavior will result.
If the read cycle results in a CRC error, the DEV_ERR bit and the CRCE bit in the
Auxiliary Status register at Offset 0Ch will be set.
264 Datasheet
Functional Description
5.22.7 SMBus Slave Interface
The PCH SMBus Slave interface is accessed using the SMBus. The SMBus slave logic will
not generate or handle receiving the PEC byte and will only act as a Legacy Alerting
Protocol device. The slave interface allows the PCH to decode cycles, and allows an
external microcontroller to perform specific actions. Key features and capabilities
include:
• Supports decode of three types of messages: Byte Write, Byte Read, and Host
Notify.
• Receive Slave Address register: This is the address that the PCH decodes. A default
value is provided so that the slave interface can be used without the processor
having to program this register.
• Receive Slave Data register in the SMBus I/O space that includes the data written
by the external microcontroller.
• Registers that the external microcontroller can read to get the state of the PCH.
• Status bits to indicate that the SMBus slave logic caused an interrupt or SMI# due
to the reception of a message that matched the slave address.
— Bit 0 of the Slave Status Register for the Host Notify command
— Bit 16 of the SMI Status Register (Section 12.8.3.8) for all others
Note: The external microcontroller should not attempt to access the PCH SMBus slave logic
until either:
— 800 milliseconds after both: RTCRST# is high and RSMRST# is high, OR
— The PLTRST# de-asserts
If a master leaves the clock and data bits of the SMBus interface at 1 for 50 µs or more
in the middle of a cycle, the PCH slave logic's behavior is undefined. This is interpreted
as an unexpected idle and should be avoided when performing management activities
to the slave logic.
Note: When an external microcontroller accesses the SMBus Slave Interface over the SMBus
a translation in the address is needed to accommodate the least significant bit used for
read/write control. For example, if the PCH slave address (RCV_SLVA) is left at 44h
(default), the external micro controller would use an address of 88h/89h (write/read).
5.22.7.1 Format of Slave Write Cycle
The external master performs Byte Write commands to the PCH SMBus Slave I/F. The
“Command” field (bits 11:18) indicate which register is being accessed. The Data field
(bits 20:27) indicate the value that should be written to that register.
Datasheet 265
Functional Description
Table 5-52 has the values associated with the registers.
Table 5-52. Slave Write Registers
Register Function
0 Command Register. See Table 5-53 for legal values written to this register.
1–3 Reserved
4 Data Message Byte 0
5 Data Message Byte 1
6–7 Reserved
8 Reserved
9–FFh Reserved
NOTE: The external microcontroller is responsible to make sure that it does not update the
contents of the data byte registers until they have been read by the system processor. The
PCH overwrites the old value with any new value received. A race condition is possible
where the new value is being written to the register just at the time it is being read. The
PCH will not attempt to cover this race condition (that is, unpredictable results in this
case).
Table 5-53. Command Types (Sheet 1 of 2)
Command Description
Type
0 Reserved
WAKE/SMI#. This command wakes the system if it is not already awake. If
system is already awake, an SMI# is generated.
1
NOTE: The SMB_WAK_STS bit will be set by this command, even if the system
is already awake. The SMI handler should then clear this bit.
Unconditional Powerdown. This command sets the PWRBTNOR_STS bit,
2
and has the same effect as the Powerbutton Override occurring.
HARD RESET WITHOUT CYCLING: This command causes a hard reset of the
3 system (does not include cycling of the power supply). This is equivalent to a
write to the CF9h register with Bits 2:1 set to 1, but Bit 3 set to 0.
HARD RESET SYSTEM. This command causes a hard reset of the system
4 (including cycling of the power supply). This is equivalent to a write to the
CF9h register with Bits 3:1 set to 1.
Disable the TCO Messages. This command will disable the PCH from sending
Heartbeat and Event messages (as described in Section 5.15). Once this
5
command has been executed, Heartbeat and Event message reporting can
only be re-enabled by assertion and de-assertion of the RSMRST# signal.
6 WD RELOAD: Reload watchdog timer.
7 Reserved
266 Datasheet
Functional Description
Table 5-53. Command Types (Sheet 2 of 2)
Command Description
Type
SMLINK_SLV_SMI. When the PCH detects this command type while in the S0
state, it sets the SMLINK_SLV_SMI_STS bit (see Section 12.9.5). This
command should only be used if the system is in an S0 state. If the message is
received during S1–S5 states, the PCH acknowledges it, but the
SMLINK_SLV_SMI_STS bit does not get set.
8 NOTE: It is possible that the system transitions out of the S0 state at the
same time that the SMLINK_SLV_SMI command is received. In this
case, the SMLINK_SLV_SMI_STS bit may get set but not serviced
before the system goes to sleep. Once the system returns to S0, the
SMI associated with this bit would then be generated. Software must
be able to handle this scenario.
9–FFh Reserved.
5.22.7.2 Format of Read Command
The external master performs Byte Read commands to the PCH SMBus Slave interface.
The “Command” field (bits 18:11) indicate which register is being accessed. The Data
field (bits 30:37) contain the value that should be read from that register.
Table 5-54. Slave Read Cycle Format
Bit Description Driven by Comment
1 Start External Microcontroller
Must match value in Receive Slave
2–8 Slave Address - 7 bits External Microcontroller
Address register
9 Write External Microcontroller Always 0
10 ACK PCH
Indicates which register is being
11–18 Command code – 8 bits External Microcontroller accessed. See Table 5-55 for a list
of implemented registers.
19 ACK PCH
20 Repeated Start External Microcontroller
Must match value in Receive Slave
21–27 Slave Address - 7 bits External Microcontroller
Address register
28 Read External Microcontroller Always 1
29 ACK PCH
Value depends on register being
30–37 Data Byte PCH accessed. See Table 5-55 for a list
of implemented registers.
38 NOT ACK External Microcontroller
39 Stop External Microcontroller
Datasheet 267
Functional Description
Table 5-55. Data Values for Slave Read Registers (Sheet 1 of 2)
Register Bits Description
Reserved for capabilities indication. Should always return 00h. Future
0 7:0
chips may return another value to indicate different capabilities.
System Power State
2:0 000 = S0 001 = S1 010 = Reserved 011 = S3
1
100 = S4 101 = S5 110 = Reserved 111 = Reserved
7:3 Reserved
3:0 Reserved
2
7:4 Reserved
Watchdog Timer current value. The Watchdog Timer has 10 bits, but
5:0 this field is only 6 bits. If the current value is greater than 3Fh, the PCH
3 will always report 3Fh in this field.
7:6 Reserved
1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that the
0
system cover has probably been opened.
1 = BTI Temperature Event occurred. This bit will be set if the PCH
1
THRM# input signal is active. Else this bit will read “0.”
DOA Processor Status. This bit will be 1 to indicate that the processor is
2
dead
1 = SECOND_TO_STS bit set. This bit will be set after the second time-
3
4 out (SECOND_TO_STS bit) of the Watchdog Timer occurs.
6:4 Reserved. Will always be 0, but software should ignore.
Reflects the value of the GPIO[11]/SMBALERT# pin (and is dependent
upon the value of the GPI_INV[11] bit. If the GPI_INV[11] bit is 1, then
the value in this bit equals the level of the GPI[11]/SMBALERT# pin
7 (high = 1, low = 0).
If the GPI_INV[11] bit is 0, then the value of this bit will equal the inverse
of the level of the GPIO[11]/SMBALERT# pin (high = 0, low = 1).
FWH bad bit. This bit will be 1 to indicate that the FWH read returned
0
FFh, which indicates that it is probably blank.
1 Reserved
SYS_PWROK Failure Status: This bit will be 1 if the SYSPWR_FLR bit in
2
the GEN_PMCON_2 register is set.
3 Reserved
4 Reserved
5 POWER_OK_BAD: Indicates the failure core power well ramp during
5 boot/resume. This bit will be active if the SLP_S3# pin is de-asserted and
PWROK pin is not asserted.
Thermal Trip: This bit will shadow the state of processor Thermal Trip
6 status bit (CTS) (16.2.1.2, GEN_PMCON_2, bit 3). Events on signal will
not create a event message
Reserved: Default value is “X”
7 NOTE: Software should not expect a consistent value when this bit is read
through SMBUS/SMLink
Contents of the Message 1 register. Refer to Section 12.9.8 for the
6 7:0
description of this register.
Contents of the Message 2 register. Refer to Section 12.9.8 for the
7 7:0
description of this register.
Contents of the TCO_WDCNT register. Refer to Section 12.9.9 for the
8 7:0
description of this register.
268 Datasheet
Functional Description
Table 5-55. Data Values for Slave Read Registers (Sheet 2 of 2)
Register Bits Description
9 7:0 Seconds of the RTC
A 7:0 Minutes of the RTC
B 7:0 Hours of the RTC
C 7:0 “Day of Week” of the RTC
D 7:0 “Day of Month” of the RTC
E 7:0 Month of the RTC
F 7:0 Year of the RTC
10h–FFh 7:0 Reserved
5.22.7.2.1 Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a Start bit –
Address– Write bit sequence. When the PCH detects that the address matches the
value in the Receive Slave Address register, it will assume that the protocol is always
followed and ignore the Write bit (Bit 9) and signal an Acknowledge during bit 10. In
other words, if a Start –Address–Read occurs (which is illegal for SMBus Read or Write
protocol), and the address matches the PCH’s Slave Address, the PCH will still grab the
cycle.
Also according to SMBus protocol, a Read cycle contains a Repeated Start–Address–
Read sequence beginning at Bit 20. Once again, if the Address matches the PCH’s
Receive Slave Address, it will assume that the protocol is followed, ignore bit 28, and
proceed with the Slave Read cycle.
Note: An external microcontroller must not attempt to access the PCH’s SMBus Slave logic
until at least 1 second after both RTCRST# and RSMRST# are de-asserted (high).
5.22.7.3 Slave Read of RTC Time Bytes
The PCH SMBus slave interface allows external SMBus master to read the internal RTC’s
time byte registers.
The RTC time bytes are internally latched by the PCH’s hardware whenever RTC time is
not changing and SMBus is idle. This ensures that the time byte delivered to the slave
read is always valid and it does not change when the read is still in progress on the bus.
The RTC time will change whenever hardware update is in progress, or there is a
software write to the RTC time bytes.
The PCH SMBus slave interface only supports Byte Read operation. The external SMBus
master will read the RTC time bytes one after another. It is software’s responsibility to
check and manage the possible time rollover when subsequent time bytes are read.
For example, assuming the RTC time is 11 hours: 59 minutes: 59 seconds. When the
external SMBus master reads the hour as 11, then proceeds to read the minute, it is
possible that the rollover happens between the reads and the minute is read as 0. This
results in 11 hours: 0 minute instead of the correct time of 12 hours: 0 minutes. Unless
it is certain that rollover will not occur, software is required to detect the possible time
rollover by reading multiple times such that the read time bytes can be adjusted
accordingly if needed.
5.22.7.4 Format of Host Notify Command
The PCH tracks and responds to the standard Host Notify command as specified in the
System Management Bus (SMBus) Specification, Version 2.0. The host address for this
command is fixed to 0001000b. If the PCH already has data for a previously-received
Datasheet 269
Functional Description
host notify command which has not been serviced yet by the host software (as
indicated by the HOST_NOTIFY_STS bit), then it will NACK following the host address
byte of the protocol. This allows the host to communicate non-acceptance to the
master and retain the host notify address and data values for the previous cycle until
host software completely services the interrupt.
Note: Host software must always clear the HOST_NOTIFY_STS bit after completing any
necessary reads of the address and data registers.
Table 5-56 shows the Host Notify format.
Table 5-56. Host Notify Format
Bit Description Driven By Comment
1 Start External Master
8:2 SMB Host Address – 7 bits External Master Always 0001_000
9 Write External Master Always 0
10 ACK (or NACK) PCH PCH NACKs if HOST_NOTIFY_STS is 1
Indicates the address of the master;
17:11 Device Address – 7 bits External Master loaded into the Notify Device Address
Register
7-bit-only address; this bit is inserted
18 Unused – Always 0 External Master
to complete the byte
19 ACK PCH
Loaded into the Notify Data Low Byte
27:20 Data Byte Low – 8 bits External Master
Register
28 ACK PCH
Loaded into the Notify Data High Byte
36:29 Data Byte High – 8 bits External Master
Register
37 ACK PCH
38 Stop External Master
270 Datasheet
Functional Description
5.23 Thermal Management
5.23.1 Thermal Sensor
The PCH incorporates one on-die Digital thermal sensor (DTS) for thermal
management. The thermal sensor can provide PCH temperature information to an EC
or SIO device that can be used to determine how to control the fans.
This thermal sensor is located near the DMI interface. The on-die thermal sensor is
placed as close as possible to the hottest on-die location to reduce thermal gradients
and to reduce the error on the sensor trip thresholds. The thermal sensor trip points
may be programmed to generate various interrupts including SCI, SMI and other
General Purpose events.
5.23.1.1 Internal Thermal Sensor Operation
The internal thermal sensor reports four trip points: Aux2, Aux, Hot and Catastrophic
trip points in the order of increasing temperature.
Aux, Aux2 Temperature Trip Points
These trip points may be set dynamically if desired and provides an interrupt to ACPI
(or other software) when it is crossed in either direction. These auxiliary temperature
trip points do not automatically cause any hardware throttling but may be used by
software to trigger interrupts. This trip point is set below the Hot temperature trip point
and responses are separately programmable from the hot temperature settings, in
order to provide incrementally more aggressive actions. Aux and Aux2 trip points are
fully Software programmable during system run-time. Aux2 trip point is set below the
Aux temperature trip point.
Hot Temperature Trip Point
This trip point may be set dynamically if desired and provides an interrupt to ACPI (or
other software) when it is crossed in either direction. Software could optionally set this
as an Interrupt when the temperature exceeds this level setting. Hot trip does not
provide any default hardware based thermal throttling, and is available only as a
customer configurable interrupt when Tj,max has been reached.
Catastrophic Trip Point
This trip point is set at the temperature at which the PCH must be shut down
immediately without any software support. The catastrophic trip point must correspond
to a temperature ensured to be functional in order for the interrupt generation and
Hardware response. Hardware response using THRMTRIP# would be an unconditional
transition to S5. The catastrophic transition to the S5 state does not enforce a
minimum time in the S5 state. It is assumed that the S5 residence and the reboot
sequence cools down the system. If the catastrophic condition remains when the
catastrophic power down enable bit is set by BIOS, then the system will re-enter S5.
Thermometer Mode
The thermometer is implemented using a counter that starts at 0 and increments
during each sample point until the comparator indicates the temperature is above the
current value. The value of the counter is loaded into a read-only register (Thermal
Sensor Thermometer Read) when the comparator first trips.
Datasheet 271
Functional Description
5.23.1.1.1 Recommended Programming for Available Trip Points
There may be a ±2 °C offset due to thermal gradient between the hot-spot and the
location of the thermal sensor. Trip points should be programmed to account for this
temperature offset between the hot-spot Tj,max and the thermal sensor.
Aux Trip Points should be programmed for software and firmware control using
interrupts.
Hot Trip Point should be set to throttle at 108 °C (Tj,max) due to DTS trim accuracy
adjustments. Hot trip points should also be programmed for a software response.
Catastrophic Trip Point should be set to halt operation to avoid maximum Tj of about
120 C.
Note: Crossing a trip point in either direction may generate several types of interrupts. Each
trip point has a register that can be programmed to select the type of interrupt to be
generated. Crossing a trip point is implemented as edge detection on each trip point to
generate the interrupts.
5.23.1.1.2 Thermal Sensor Accuracy (Taccuracy)
Taccuracy for the PCH is ±5 °C in the temperature range 90 °C to 120 °C. Taccuracy is
±10 °C for temperatures from 45 °C – 90 °C. The PCH may not operate above
+108 °C. This value is based on product characterization and is not ensured by
manufacturing test.
Software has the ability to program the Tcat, Thot, and Taux trip points, but these trip
points should be selected with consideration for the thermal sensor accuracy and the
quality of the platform thermal solution. Overly conservative (unnecessarily low)
temperature settings may unnecessarily degrade performance due to frequent
throttling, while overly aggressive (dangerously high) temperature settings may fail to
protect the part against permanent thermal damage.
5.23.2 PCH Thermal Throttling
Occasionally the PCH may operate in conditions that exceed its maximum operating
temperature. In order to protect itself and the system from thermal failure, the PCH is
capable of reducing its overall power consumption and as a result, lower its
temperature. This is achieved by:
• Forcing the SATA device and interface in to a lower power state
• Reducing the number of active lanes on the DMI interface
• Reducing the Intel Management Engine (Intel ME) clock frequency
The severity of the throttling response is defined by four global PCH throttling states
referred to as T-states. In each T-state, the throttling response will differ per interface,
but will operate concurrently when a global T-state is activated. A T-state corresponds
to a temperature range. The T-states are defined in Table 5-57.
272 Datasheet
Functional Description
Table 5-57. PCH Thermal Throttle States (T-states)
State Description
T0 Normal operation, temperature is less than the T1 trip point temperature
Temperature is greater than or equal to the T1 trip point temperature, but less
T1
than the T2 trip point temperature. The default temperature is Tj,max at 108 °C
Temperature is greater than or equal to the T2 trip point temperature, but less
T2
than the T3 trip point temperature. The default temperature is 112 °C
Temperature is greater than or equal to the T3 trip point temperature. The
T3
default temperature is 116 °C
Enabling of this feature requires appropriate Intel Management Engine firmware and
configuration of the following registers shown in Table 5-58.
Table 5-58. PCH Thermal Throttling Configuration Registers
Register
Register Name
Location
TL – Throttle Levels TBARB+40h Section 22.2.10
5.23.3 Thermal Reporting Over System Management Link 1
Interface (SMLink1)
SMLink1 interface in the PCH is the SMBus link to an optional external controller. A
SMBus protocol is defined on the PCH to allow compatible devices such as Embedded
Controller (EC) or SIO to obtain system thermal data from PCH sensors using the
SMLink1 interface. This solution allows an external device or controller to use the
system thermal data for system thermal management.
Note: To enable Thermal Reporting: Set Section 22.2.4, “TSEL—Thermal Sensor Enable and
Lock Register” bit 0 = 1 (Enable TS) and Section 22.2.5, “TSREL—Thermal Sensor
Reporting Enable and Lock Register” bit 0 = 1 (Enable SMBus Temperature Reporting).
There are two uses for the PCH's thermal reporting capability:
1. To provide system thermal data to an external controller. The controller can
manage the fans and other cooling elements based on this data. In addition, the
PCH can be programmed by setting appropriate bits in the Section 22.2.7, “CTT—
Catastrophic Trip Point Register” , Section 22.2.8, “TAHV—Thermal Alert High Value
Register” and Section 22.2.9, “TALV—Thermal Alert Low Value Register” to alert
the controller when a device has gone outside of its temperature limits. The alert
causes the assertion of the PCH TEMP_ALERT# (SML1ALERT#/TEMP_ALERT#/
GPIO74) signal. See Section 5.23.3.5 for more details.
2. To provide an interface between the external controller and host software. This
software interface has no direct affect on the PCH's thermal collection. It is strictly
a software interface to pass information or data.
The PCH responds to thermal requests only when the system is in S0 or S1. Once the
PCH has been programmed, it will start responding to a request while the system is in
S0 or S1.
To implement this thermal reporting capability, the platform is required to have
appropriate BIOS support and compatible devices that support the SMBus protocol.
Datasheet 273
Functional Description
5.23.3.1 Block Read Address
The PCH supports the Block Read Address for reads. This address is used for reads from
the PCH.
• The address is set by soft straps or BIOS. It can be set to any value the platform
requires.
• This address only supports SMBus Block Read command and not Byte or Word
Read.
• The Block Read command is supported as defined in the SMBus 2.0 specification,
with the command being 40h, and the byte count being provided by the PCH
following the block read format in the SMBus specification.
• Writes are not allowed to this address, and result in indeterminate behavior.
• Packet Error Code (PEC) may be enabled or not, which is set up by BIOS.
5.23.3.2 Block Read Command
The external controller may read thermal information from the PCH using the SMBus
Block Read Command. Byte-read and Word-read SMBus commands are not supported.
The reads use a different address than the writes.
The command format follows the Block Read format of the SMBus specification.
The PCH returns a single byte of data, indicating the temperature between 0 °C (0x00)
and 254 °C (0xFE). A read of 0xFF indicates that the sensor is not yet enabled. For
more information, see Section 5.23.3.3.1.
5.23.3.3 Read Data Format
For each of the data fields an ERROR Code is listed below. This code indicates that the
PCH failed in its access to the device. This would be for the case where the read
returned no data, or some illegal value. In general that would mean the device is
broken. The EC can treat the device that failed the read as broken or with some fail-
safe mechanism.
5.23.3.3.1 PCH Temperature
The temperature readings for the PCH are 8-bit unsigned values from 0–255. The
minimum granularity supported by the internal thermal sensor is 1 °C. Thus, there are
no fractional values for the PCH temperatures. The device returns a temperature
between 0 °C (0x00) and 254 °C (0xFE). Devices that are not yet enabled return the
value 0xFF.
Note: Sensors used within the components do not support values below 0°C, so this field is
treated as 8 bits (0-255) absolute.
5.23.3.4 Thermal Data Update Rate
The temperature values are updated every 1 ms in the PCH, so reading more often
than that simply returns the same data multiple times. Also, the data may be up to 1
ms old if the external controller reads the data right before the next update window.
5.23.3.5 Temperature Comparator and Alert
The PCH has the ability to alert the external controller when temperatures are out of
range. This is done using the PCH TEMP_ALERT# signal. The alert is a simple
comparator. If any device's temperature is outside the limit range for that device, then
the signal is asserted (electrical low). This alert does not use the SML1ALERT#.
274 Datasheet
Functional Description
The PCH supports 2 ranges: an upper and lower limit (8 bits each, in degrees C) for the
PCH temperature.
The comparator checks if the device is within the specified range, including the limits.
For example, a device that is at 100 degrees when the upper limit is 100 will not trigger
the alert. Likewise, a device that is at 70 degrees when the lower limit is 70 will not
trigger the alert.
The compares are done only on devices that have been enabled by BIOS for checking.
The compares are done in firmware, so all the compares are executed in one software
loop and at the end, if there is any out of bound temperature, the PCH’s TEMP_ALERT#
signal is asserted.
When the external controller sees the TEMP_ALERT# signal low, it knows the device is
out of range. It can read the temperature and then change the limit for the device. It
may take up to 250 ms before the actual writes cause the signal to change state. For
instance, if the PCH is at 105 degrees and the limit is 100, the alert is triggered. If the
controller changes the limits to 110, the TEMP_ALERT# signal may remain low until the
next thermal sampling window (every 1 ms) occurs and only then go high, assuming
the PCH was still within its limits.
At boot, the controller can monitor the TEMP_ALERT# signal state. When BIOS has
finished all the initialization and enabled the temperature comparators, the
TEMP_ALERT# signal will be asserted since the default state of the limit registers is 0h;
hence, when the PCH first reads temperatures, they will be out of range. This is the
positive indication that the external controller may now read thermal information and
get valid data. If the TEMP_ALERT# signal is enabled and not asserted within 30
seconds after PLTRST#, the external controller should assume there is a fatal error and
handle accordingly. In general the TEMP_ALERT# signal will assert within a 1–4
seconds, depending on the actual BIOS implementation and flow.
Note: The TEMP_ALERT# assertion is only valid when PLTRST# is de-asserted. The controller
should mask the state of this signal when PLTRST# is asserted. Since the controller
may be powered even when the PCH and the rest of the platform are not, the signal
may glitch as power is being asserted; thus, the controller should wait until PLTRST#
has de-asserted before monitoring the signal.
5.23.3.5.1 Special Conditions
The external controller should have a graceful means of handling when TEMP_ALERT#
asserts, and the controller reads PCH, but all temperature values are within limits. In
this case, the controller should assume that by the time the controller could read the
data, it had changed and moved back within the limits.
5.23.3.6 BIOS Set Up
In order for the PCH to properly report temperature and enable alerts, the BIOS must
configure the PCH at boot or from suspend/resume state by writing the following
information to the PCH MMIO space. This information is NOT configurable using the
external controller.
• Enables for PCH thermal alerts.
• Enables for reading PCH temperatures.
• Setting up the temperature calculation equations.
5.23.3.7 SMBus Rules
The PCH may NACK an incoming SMBus transaction. In certain cases the PCH will NACK
the address, and in other cases it will NACK the command depending on internal
conditions (such as errors, busy conditions). Given that most of the cases are due to
internal conditions, the external controller must alias a NACK of the command and a
Datasheet 275
Functional Description
NACK of the address to the same behavior. The controller must not try to make any
determination of the reason for the NACK, based on the type of NACK (command
versus address).
The PCH will NACK when it is enabled but busy. The external controller is required to
retry up to 3 times when they are NACK'ed. In reality if there is a NACK because of the
PCH being busy, in almost all cases the next read will succeed since the update
internally takes very little time. In the case of a long delay, the external controller must
assume that the PCH will never return good data.
5.23.3.7.1 During Block Read
On the Block Read, the PCH will respect the NACK and Stop indications from the
external controller, but will consider this an error case. It will recover from this case
and correctly handle the next SMBus request.
The PCH will honor STOP during the block read command and cease providing data. On
the next Block Read, the data will start with byte 0 again. However, this is not a
recommended usage except for 'emergency cases'. In general the external controller
should read the entire length of data that was originally programmed.
5.23.3.7.2 Power On
On the Block Read, the PCH will respect the NACK and Stop indications from the
external controller, but will consider this an error case. It will recover from this case
and correctly handle the next SMBus request.
The PCH will honor STOP during the block read command and cease providing data. On
the next Block Read, the data will start with byte 0 again. However, this is not a
recommended usage except for 'emergency cases'. In general the external controller
should read the entire length of data that was originally programmed.
5.23.3.8 Case for Considerations
Below are some corner cases and some possible actions that the external controller
could take.
A 1-byte sequence number is available to the data read by the external controller. Each
time the PCH updates the thermal information it will increment the sequence number.
The external controller can use this value as an indication that the thermal FW is
actually operating. The sequence number will roll over to 00h when it reaches FFh.
1. Power on:
The PCH will not respond to any SMBus activity (on SMLink1 interface) until it
has loaded the thermal Firmware (FW), which in general would take 1–4 ms.
During this period, the PCH will NACK any SMBus transaction from the external
controller.
The load should take 1-4 ms, but the external controller should design for 30
seconds based on long delays for S4 resume which takes longer than normal
power up. This would be an extreme case, but for larger memory footprints and
non-optimized recovery times, 30 seconds is a safe number to use for the time-
out.
Recover/Failsafe: if the PCH has not responded within 30 seconds, the external
controller can assume that the system has had a major error and the external
controller should ramp the fans to some reasonably high value.
The only recover from this is an internal reset on the PCH, which is not visible
to the external controller. Therefore the external controller might choose to poll
every 10-60 seconds (some fairly long period) hereafter to see if the PCH's
thermal reporting has come alive.
276 Datasheet
Functional Description
2. The PCH Thermal FW hangs and requires an internal reset which is not visible to
the external controller.
The PCH will NACK any SMBus transaction from the external controller. The PCH
may not be able to respond for up to 30 seconds while the FW is being reset and
reconfigured.
The external controller could choose to poll every 1-10 seconds to see if the
thermal FW has been successfully reset and is now providing data.
General recovery for this case is about 1 second, but 30 seconds should be used
by the external controller at the time-out.
Recovery/Failsafe: same as in case #1.
3. Fatal PCH error, causes a global reset of all components.
When there is a fatal PCH error, a global reset may occur, and then case #1
applies.
The external controller can observe, if desired, PLTRST# assertion as an
indication of this event.
4. The PCH thermal FW fails or is hung, but no reset occurs
The sequence number will not be updated, so the external controller knows to
go to failsafe after some number of reads (8 or so) return the same sequence
number.
The external controller could choose to poll every 1-10 seconds to see if the
thermal FW has been successfully reset and working again.
In the absence of other errors, the updates for the sequence number should
never be longer than 400 ms, so the number of reads needed to indicate that
there is a hang should be at around 2 seconds. But when there is an error, the
sequence number may not get updated for seconds. In the case that the
external controller sees a NACK from the PCH, then it should restart its sequence
counter, or otherwise be aware that the NACK condition needs to be factored into
the sequence number usage.
The use of sequence numbers is not required, but is provided as a means to
ensure correct PCH FW operation.
5. When the PCH updates the Block Read data structure, the external controller gets a
NACK during this period.
To ensure atomicity of the SMBus data read with respect to the data itself, when
the data buffer is being updated, the PCH will NACK the Block Read transaction.
The update is only a few micro-seconds, so very short in terms of SMBus polling
time; therefore, the next read should be successful. The external controller
should attempt 3 reads to handle this condition before moving on.
If the Block read has started (that is, the address is ACK'ed) then the entire read
will complete successfully, and the PCH will update the data only after the SMBus
read has completed.
6. System is going from S0 to S3/S4/S5. The thermal monitoring FW is fully
operational if the system is in S0/S1, so the following only applies to S3/S4/S5.
When the PCH detects the OS request to go to S3/S4/S5, it will take the SMLink1
controller offline as part of the system preparation. The external controller will
see a period where its transactions are getting NACK'ed, and then see SLP_S3#
assert.
This period is relatively short (a couple of seconds depending on how long all the
devices take to place themselves into the D3 state), and would be far less than
the 30 second limit mentioned above.
7. TEMP_ALERT# – Since there can be an internal reset, the TEMP_ALERT# may get
asserted after the reset. The external controller must accept this assertion and
handle it.
Datasheet 277
Functional Description
5.23.3.8.1 Example Algorithm for Handling Transaction
One algorithm for the transaction handling could be summarized as follows. This is just
an example to illustrate the above rules. There could be other algorithms that can
achieve the same results.
1. Perform SMBus transaction.
2. If ACK, then continue
3. If NACK
a. Try again for 2 more times, in case the PCH is busy updating data.
b. If 3 successive transactions receive NACK, then
- Ramp fans, assuming some general long reset or failure
- Try every 1-10 seconds to see if SMBus transactions are now working
- If they start then return to step 1
- If they continue to fail, then stay in this step and poll, but keep the fans
ramped up or implement some other failure recovery mechanism.
278 Datasheet
Functional Description
5.24 Intel® High Definition Audio (Intel® HD Audio)
Overview (D27:F0)
The PCH High Definition Audio (HDA) controller communicates with the external
codec(s) over the Intel High Definition Audio serial link. The controller consists of a set
of DMA engines that are used to move samples of digitally encoded data between
system memory and an external codec(s). The PCH implements four output DMA
engines and 4 input DMA engines. The output DMA engines move digital data from
system memory to a D-A converter in a codec. The PCH implements a single Serial
Data Output signal (HDA_SDO) that is connected to all external codecs. The input DMA
engines move digital data from the A-D converter in the codec to system memory. The
PCH implements four Serial Digital Input signals (HDA_SDI[3:0]) supporting up to four
codecs.
Audio software renders outbound and processes inbound data to/from buffers in
system memory. The location of individual buffers is described by a Buffer Descriptor
List (BDL) that is fetched and processed by the controller. The data in the buffers is
arranged in a predefined format. The output DMA engines fetch the digital data from
memory and reformat it based on the programmed sample rate, bit/sample and
number of channels. The data from the output DMA engines is then combined and
serially sent to the external codecs over the Intel High Definition Audio link. The input
DMA engines receive data from the codecs over the Intel High Definition Audio link and
format the data based on the programmable attributes for that stream. The data is
then written to memory in the predefined format for software to process. Each DMA
engine moves one stream of data. A single codec can accept or generate multiple
streams of data, one for each A-D or D-A converter in the codec. Multiple codecs can
accept the same output stream processed by a single DMA engine.
Codec commands and responses are also transported to and from the codecs using
DMA engines.
The PCH HD Audio controller supports the Function Level Reset (FLR).
5.24.1 Intel® High Definition Audio (Intel® HD Audio) Docking
(Mobile Only)
5.24.1.1 Dock Sequence
This sequence is followed when the system is running and a docking event occurs.
1. Since the PCH supports docking, the Docking Supported (DCKSTS. DS) bit defaults
to a 1. POST BIOS and ACPI BIOS software uses this bit to determine if the HD
Audio controller supports docking. BIOS may write a 0 to this R/WO bit during
POST to effectively turn off the docking feature.
2. After reset in the undocked quiescent state, the Dock Attach (DCKCTL.DA) bit and
the Dock Mate (DCKSTS.DM) bit are both de-asserted. The HDA_DOCK_EN# signal
is de-asserted and HDA_DOCK_RST# is asserted. Bit Clock, SYNC and SDO signals
may or may no be running at the point in time that the docking event occurs.
3. The physical docking event is signaled to ACPI BIOS software using ACPI control
methods. This is normally done through a GPIO signal on the PCH and is outside
the scope of this section of the specification.
4. ACPI BIOS software first checks that the docking is supported using DCKSTS.DS=1
and that the DCKSTS.DM=0 and then initiates the docking sequence by writing a 1
to the DCKCTL.DA bit.
Datasheet 279
Functional Description
5. The HD Audio controller then asserts the HDA_DOCK_EN# signal so that the Bit
Clock signal begins toggling to the dock codec. HDA_DOCK_EN# shall be asserted
synchronously to Bit Clock and timed such that Bit Clock is low, SYNC is low, and
SDO is low. Pull-down resistors on these signals in the docking station discharge
the signals low so that when the state of the signal on both sides of the switch is
the same when the switch is turned on. This reduces the potential for charge
coupling glitches on these signals. In the PCH the first 8 bits of the Command field
are “reserved” and always driven to 0s. This creates a predictable point in time to
always assert HDA_DOCK_EN#. The HD Audio link reset exit specification that
requires that SYNC and SDO be driven low during Bit Clock startup is not ensured.
Note also that the SDO and Bit Clock signals may not be low while
HDA_DOCK_RST# is asserted which also violates the specification.
6. After the controller asserts HDA_DOCK_EN# it waits for a minimum of 2400 Bit
Clocks (100 µs) and then de-asserts HDA_DOCK_RST#. This is done in such a way
to meet the HD Audio link reset exit specification. HDA_DOCK_RST# de-assertion
should be synchronous to Bit Clock and timed such that there are least 4 full Bit
ClockS from the de-assertion of HDA_DOCK_RST# to the first frame SYNC
assertion.
7. The Connect/Turnaround/Address Frame hardware initialization sequence will now
occur on the dock codecs' SDI signals. A dock codec is detected when SDI is high
on the last Bit Clock cycle of the Frame Sync of a Connect Frame. The appropriate
bit(s) in the State Change Status (STATESTS) register will be set. The Turnaround
and Address Frame initialization sequence then occurs on the dock codecs' SDI(s).
8. After this hardware initialization sequence is complete (approximately 32 frames),
the controller hardware sets the DCKSTS.DM bit to 1 indicating that the dock is now
mated. ACPI BIOS polls the DCKSTS.DM bit and when it detects it is set to 1,
conveys this to the OS through a plug-N-play IRP. This eventually invokes the HD
Audio Bus Driver, which then begins it's codec discovery, enumeration, and
configuration process.
9. Alternatively to step #8, the HD Audio Bus Driver may choose to enable an
interrupt by setting the WAKEEN bits for SDINs that didn't originally have codecs
attached to them. When a corresponding STATESTS bit gets set an interrupt will be
generated. In this case the HD Audio Bus Driver is called directly by this interrupt
instead of being notified by the plug-N-play IRP.
10. Intel HD Audio Bus Driver software “discovers” the dock codecs by comparing the
bits now set in the STATESTS register with the bits that were set prior to the
docking event.
5.24.1.2 Exiting D3/CRST# When Docked
1. In D3/CRST#, CRST# is asserted by the HD Audio Bus Driver. CRST# asserted
resets the dock state machines, but does not reset the DCKCTL.DA bit. Because the
dock state machines are reset, the dock is electrically isolated (HDA_DOCK_EN#
de-asserted) and DOCK_RST# is asserted.
2. The Bus Driver clears the STATESTS bits, then de-asserts CRST#, waits
approximately 7 ms, then checks the STATESTS bits to see which codecs are
present.
3. When CRST# is de-asserted, the dock state machine detects that DCKCTL.DA is
still set and the controller hardware sequences through steps to electrically connect
the dock by asserting HDA_DOCK_EN# and then eventually de-asserts
DOCK_RST#. This completes within the 7 ms mentioned in step 2).
4. The Bus Driver enumerates the codecs present as indicated using the STATESTS
bits.
5. This process did not require BIOS or ACPI BIOS to set the DCKCTL.DA bit.
280 Datasheet
Functional Description
5.24.1.3 Cold Boot/Resume from S3 When Docked
1. When booting and resuming from S3, PLTRST# switches from asserted to de-
asserted. This clears the DCKCTL.DA bit and the dock state machines. Because the
dock state machines are reset, the dock is electrically isolated (HDA_DOCK_EN#
de-asserted) and DOCK_RST# is asserted.
2. POST BIOS detects that the dock is attached and sets the DCKCTL.DA bit to 1. At
this point CRST# is still asserted so the dock state machine will remain in its reset
state.
3. The Bus Driver clears the STATESTS bits, then de-asserts CRST#, waits
approximately 7 ms, then checks the STATESTS bits to see which codecs are
present.
4. When CRST# is de-asserted, the dock state machine detects that DCKCTL.DA is
still set and the controller hardware sequences through steps to electrically connect
the dock by asserting HDA_DOCK_EN# and then eventually de-asserts
DOCK_RST#. This completes within the 7 ms mentioned in step 3).
5. The Bus Driver enumerates the codecs present as indicated using the STATESTS
bits.
5.24.1.4 Undock Sequence
There are two possible undocking scenarios. The first is the one that is initiated by the
user that invokes software and gracefully shuts down the dock codecs before they are
undocked. The second is referred to as the “surprise undock” where the user undocks
while the dock codec is running. Both of these situations appear the same to the
controller as it is not cognizant of the “surprise removal”. But both sequences will be
discussed here.
5.24.1.5 Normal Undock
1. In the docked quiescent state, the Dock Attach (DCKCTL.DA) bit and the Dock Mate
(DCKSTS.DM) bit are both asserted. The HDA_DOCK_EN# signal is asserted and
HDA_DOCK_RST# is de-asserted.
2. The user initiates an undock event through the GUI interface or by pushing a
button. This mechanism is outside the scope of this section of the document. Either
way ACPI BIOS software will be invoked to manage the undock process.
3. ACPI BIOS will call the HD Audio Bus Driver software in order to halt the stream to
the dock codec(s) prior to electrical undocking. If the HD Audio Bus Driver is not
capable of halting the stream to the docked codec, ACPI BIOS will initiate the
hardware undocking sequence as described in the next step while the dock stream
is still running. From this standpoint, the result is similar to the “surprise undock”
scenario where an audio glitch may occur to the docked codec(s) during the undock
process.
4. The ACPI BIOS initiates the hardware undocking sequence by writing a 0 to the
DCKCTL.DA bit.
5. The HD Audio controller asserts HDA_DOCK_RST#. HDA_DOCK_RST# assertion
shall be synchronous to Bit Clock. There are no other timing requirements for
HDA_DOCK_RST# assertion. The HD Audio link reset specification requirement that
the last Frame sync be skipped will not be met.
6. A minimum of 4 Bit Clocks after HDA_DOCK_RST# the controller will de-assert
HDA_DOCK_EN# to isolate the dock codec signals from the PCH HD Audio link
signals. HDA_DOCK_EN# is de-asserted synchronously to Bit Clock and timed such
that Bit Clock, SYNC, and SDO are low.
7. After this hardware undocking sequence is complete the controller hardware clears
the DCKSTS.DM bit to 0 indicating that the dock is now un-mated. ACPI BIOS
software polls DCKSTS.DM and when it sees DM set, conveys to the end user that
physical undocking can proceed. The controller is now ready for a subsequent
docking event.
Datasheet 281
Functional Description
5.24.1.6 Surprise Undock
1. In the surprise undock case the user undocks before software has had the
opportunity to gracefully halt the stream to the dock codec and initiate the
hardware undock sequence.
2. A signal on the docking connector is connected to the switch that isolates the dock
codec signals from the PCH HD Audio link signals (DOCK_DET# in the conceptual
diagram). When the undock event begins to occur the switch will be put into isolate
mode.
3. The undock event is communicated to the ACPI BIOS using ACPI control methods
that are outside the scope of this section of the document.
4. ACPI BIOS software writes a 0 to the DCKCTL.DA bit. ACPI BIOS then calls the HD
Audio Bus Driver using plug-N-play IRP. The Bus Driver then posthumously cleans
up the dock codec stream.
5. The HD Audio controller hardware is oblivious to the fact that a surprise undock
occurred. The flow from this point on is identical to the normal undocking sequence
described in Section 5.24.1.5 starting at step 3). It finishes with the hardware
clearing the DCKSTS.DM bit set to 0 indicating that the dock is now un-mated. The
controller is now ready for a subsequent docking event.
5.24.1.7 Interaction between Dock/Undock and Power Management States
When exiting from S3, PLTRST# will be asserted. The POST BIOS is responsible for
initiating the docking sequence if the dock is already attached when PLTRST# is de-
asserted. POST BIOS writes a 1 to the DCKCTL.DA bit prior to the HD Audio driver de-
asserting CRTS# and detecting and enumerating the codecs attached to the
HDA_DOCK_RST# signal. The HD Audio controller does not directly monitor a hardware
signal indicating that a dock is attached. Therefore a method outside the scope of this
document must be used to cause the POST BIOS to initiate the docking sequence.
When exiting from D3, CRST# will be asserted. When CRST# bit is “0” (asserted), the
DCKCTL.DA bit is not cleared. The dock state machine will be reset such that
HDA_DOCK_EN# will be de-asserted, HDA_DOCK_RST# will be asserted and the
DCKSTS.DM bit will be cleared to reflect this state. When the CRST# bit is de-asserted,
the dock state machine will detect that DCKCTL.DA is set to “1” and will begin
sequencing through the dock process. This does not require any software intervention.
5.24.1.8 Relationship between HDA_DOCK_RST# and HDA_RST#
HDA_RST# will be asserted when a PLTRST# occurs or when the CRST# bit is 0. As
long as HDA_RST# is asserted, the DOCK_RST# signal will also be asserted.
When PLTRST# is asserted, the DCKCTL.DA and DCKSTS.DM bits will be get cleared to
their default state (0's), and the dock state machine will be reset such that
HDA_DOCK_EN# will be de-asserted, and HDA_DOCK_RST# will be asserted. After any
PLTRST#, POST BIOS software is responsible for detecting that a dock is attached and
then writing a “1” to the DCKCTL.DA bit prior to the HD Audio Bus Driver de-asserting
CRST#.
When CRST# bit is “0” (asserted), the DCKCTL.DA bit is not cleared. The dock state
machine will be reset such that HDA_DOCK_EN# will be de-asserted,
HDA_DOCK_RST# will be asserted and the DCKSTS.DM bit will be cleared to reflect this
state. When the CRST# bit is de-asserted, the dock state machine will detect that
DCKCTL.DA is set to “1” and will begin sequencing through the dock process. This does
not require any software intervention
282 Datasheet
Functional Description
5.25 Intel® Management Engine (Intel® ME) and Intel®
Management Engine Firmware (Intel® ME FW) 9.0
Key properties of Intel Management Engine (Intel ME):
• Connectivity
— Integration into I/O subsystem of PCH
— Delivery of advanced I/O functions
• Security
— More secure (Intel root of trust) & isolated execution
— Increased security of flash file system
• Modularity & Partitioning
— OSV, VMM & SW Independence
— Rapid response to competitive changes
• Power
— Always On Always Connected
— Advanced functions in low power S3-S4-S5 operation
— OS independent PM & thermal heuristics
Intel ME FW provides a variety of services that range from low-level hardware
initialization and provisioning to high-level end-user software based IT manageability
services. One of Intel ME FW’s most established and recognizable features is Intel
Active Management Technology (Intel AMT).
Intel Active Management Technology is a set of advanced manageability features
developed to meet the evolving demands placed on IT to manage a network
infrastructure. Intel AMT reduces the Total Cost of Ownership (TCO) for IT management
through features such as asset tracking, remote manageability, and robust policy-
based security, resulting in fewer desk-side visits and reduced incident support
durations. Intel AMT extends the manageability capability for IT through Out Of Band
(OOB), allowing asset information, remote diagnostics, recovery, and contain
capabilities to be available on client systems even when they are in a low power, or
“off” state, or in situations when the operating system is hung.
Datasheet 283
Functional Description
Figure 5-14. PCH Intel® Management Engine (Intel® ME) High-Level Block Diagram
5.25.1 Intel® Management Engine (Intel® ME) Requirements
The following list of components compose the Intel ME hardware infrastructure:
• The Intel ME is the general purpose controller that resides in the PCH. It operates in
parallel to, and is resource-isolated from, the host processor.
• The SPI flash device stores Intel ME Firmware code that is executed by the Intel ME
for its operations. The PCH controls the flash device through the SPI interface and
internal logic.
• In the M0 power state, the Intel ME FW code is loaded from SPI flash into DRAM
and cached in secure and isolated SRAM. In order to interface with DRAM, the Intel
ME utilizes the integrated memory controller (IMC) present in the processor. DMI
serves as the interface for communication between the IMC and Intel ME. This
interfacing occurs in only M0 power state. In the lower Intel ME power state, M3,
code is executed exclusively from secure and isolated Intel ME local RAM.
• The LAN controller embedded in the PCH as well as the Intel Gigabit Platform LAN
Connect device are required for Intel ME and Intel AMT network connectivity.
• BIOS provides asset detection and POST diagnostics (BIOS and Intel AMT can
optionally share same flash memory device)
• An ISV software package, such as LANDesk*, Altiris*, or Microsoft* SMS, can be
used to take advantage of the platform manageability capabilities of Intel AMT.
284 Datasheet
Functional Description
5.26 Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a lower-cost
alternative for system flash versus the Firmware Hub on the LPC bus.
The 4-pin SPI interface consists of clock (CLK), master data out (Master Out Slave In
(MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select
(SPI_CS[1:0]#). SPI also adds 2 extra pins SPI_IO2 and SPI_IO3 for Quad I/O
operation.
The PCH supports up to two SPI flash devices using two separate Chip Select pins. Each
SPI flash device can be up to 16 MB. The PCH SPI interface supports 20 MHz, 33 MHz,
and 50 MHz SPI devices. A SPI Flash device on with Chip Select 0 with a valid
descriptor MUST be attached directly to the PCH.
Note: When operating at 50 MHz, because of the 40% duty cycle PCH must use by dividing
down from a 125 MHz clock, the PCH SPI Flash Controller cannot meet the minimum
high timing requirements of a 50 MHz SPI Flash component and a 66 MHz rated or
faster SPI Flash component must be used.
The PCH supports fast read which consist of:
1. Dual Output Fast Read (Single Input Dual Output)
2. Dual I/O Fast Read (Dual Input Dual Output)
3. Quad Output Fast Read (Single Input Quad Output)
4. Quad I/O Fast Read (Quad Input Quad Output)
Fast Read function will be enabled if the particular SPI part supports one of the function
mentioned above along with support for SFDP (Serial Flash Discoverable Parameter).
PCH adds support for SFDP. SFDP is a JEDEC* standard that provides consistent
method for describing functional and feature capabilities of serial flash devices in a
standard set of internal parameter table. PCH SPI controller reads the internal
parameter table and enables divergent features of multiple SPI vendor parts.
PCH adds third chip select SPI_CS2# for TPM support over SPI. TPM Bus will use
SPI_CLK, SPI_MISO, SPI_MOSI and SPI_CS2# SPI signals.
Note: Communication on the SPI bus is done with a Master – Slave protocol. The Slave is
connected to the PCH and is implemented as a tri-state bus.If Boot BIOS Strap =’00’
then LPC is selected as the location for BIOS. BIOS may still be placed on LPC, but all
platforms with the PCH require a SPI flash connected directly to the PCH's SPI bus with
a valid descriptor connected to Chip Select 0 in order to boot.
Note: When SPI is selected by the Boot BIOS Destination Strap and a SPI device is detected
by the PCH, LPC based BIOS flash is disabled.
Datasheet 285
Functional Description
5.26.1 SPI Supported Feature Overview
SPI Flash on the PCH has two operational modes, descriptor and non-descriptor.
5.26.1.1 Non-Descriptor Mode
Non-Descriptor Mode is not supported as a valid flash descriptor is required for all PCH
Platforms.
5.26.1.2 Descriptor Mode
Descriptor Mode is required for all SKUs of the PCH. It enables many features of the
chipset:
• Integrated Gigabit Ethernet and Host processor for Gigabit Ethernet Software
• Intel Active Management Technology
• Intel Management Engine Firmware
• PCI Express* root port configuration
• Supports up to two SPI components using two separate chip select pins
• Hardware enforced security restricting master accesses to different regions
• Chipset Soft Strap regions provides the ability to use Flash NVM as an alternative to
hardware pull-up/pull-down resistors for the PCH and processor
• Supports the SPI Fast Read instruction and frequencies of up to 50 MHz
• Support Single Input, Dual Output Fast read
• Uses standardized Flash Instruction Set
5.26.1.2.1 SPI Flash Regions
In Descriptor Mode the Flash is divided into five separate regions:
Region Content
0 Flash Descriptor
1 BIOS
Intel Management
2
Engine
3 Gigabit Ethernet
4 Platform Data
Only three masters can access the four regions: Host processor running BIOS code,
Integrated Gigabit Ethernet and Host processor running Gigabit Ethernet Software, and
Intel Management Engine. The Flash Descriptor is in Region 0 and it must be located in
the first sector of Device 0 (Offset 0).
286 Datasheet
Functional Description
Flash Region Sizes
SPI flash space requirements differ by platform and configuration. The Flash Descriptor
requires one 4 KB or larger block. GbE requires two 4 KB or larger blocks. The amount
of flash space consumed is dependent on the erase granularity of the flash part and the
platform requirements for the Intel ME and BIOS regions. The Intel ME region contains
firmware to support Intel Active Management Technology and other Intel ME
capabilities.
Table 5-59. Region Size versus Erase Granularity of Flash Components
Size with 4 KB Size with 8 KB Size with 64 KB
Region
Blocks Blocks Blocks
Descriptor 4 KB 8 KB 64 KB
GbE 8 KB 16 KB 128 KB
BIOS Varies by Platform Varies by Platform Varies by Platform
Intel ME Varies by Platform Varies by Platform Varies by Platform
5.26.2 Flash Descriptor
The maximum size of the Flash Descriptor is 4 KB. If the block/sector size of the SPI
flash device is greater than 4 KB, the flash descriptor will only use the first 4 KB of the
first block. The flash descriptor requires its own block at the bottom of memory (00h).
The information stored in the Flash Descriptor can only be written during the
manufacturing process as its read/write permissions must be set to Read only when the
computer leaves the manufacturing floor.
The Flash Descriptor is made up of eleven sections (see Figure 5-15).
Datasheet 287
Functional Description
Figure 5-15. Flash Descriptor Sections
4KB
OEM Section
Descriptor
Upper MAP
Management
Engine VSCC
Table
Reserved
PCH Soft
Straps
Master
Region
Component
Descriptor
MAP
10 h Signature
288 Datasheet
Functional Description
1. The Flash signature selects Descriptor Mode as well as verifies if the flash is
programmed and functioning. The data at the bottom of the flash (offset 10h) must
be 0FF0A55Ah in order to be in Descriptor mode.
2. The Descriptor map has pointers to the other five descriptor sections as well as the
size of each.
3. The component section has information about the SPI flash in the system including:
the number of components, density of each, illegal instructions (such as chip
erase), and frequencies for read, fast read and write/erase instructions.
4. The Region section points to the three other regions as well as the size of each
region.
5. The master region contains the security settings for the flash, granting read/write
permissions for each region and identifying each master by a requestor ID. See
Section 5.26.2.1 for more information.
6 & 7. The processor and PCH soft strap sections contain processor and PCH
configurable parameters.
8. The Reserved region between the top of the processor strap section and the bottom
of the OEM Section is reserved for future chipset usages.
9. The Descriptor Upper MAP determines the length and base address of the
Management Engine VSCC Table.
10. The Management Engine VSCC Table holds the JEDEC ID and the VSCC information
of the entire SPI Flash supported by the NVM image.
11. OEM Section is 256 Bytes reserved at the top of the Flash Descriptor for use by
OEM.
5.26.2.1 Descriptor Master Region
The master region defines read and write access setting for each region of the SPI
device. The master region recognizes three masters: BIOS, Gigabit Ethernet, and
Management Engine. Each master is only allowed to do direct reads of its primary
regions.
Table 5-60. Region Access Control Table
Master Read/Write Access
Region Processor and BIOS Intel® ME GbE Controller
Descriptor N/A N/A N/A
Processor and BIOS
can always read from
BIOS Read / Write Read / Write
and write to BIOS
Region
Intel® ME can always
Management
Read / Write read from and write to Read / Write
Engine
Intel ME Region
GbE software can
Gigabit Ethernet Read / Write Read / Write always read from and
write to GbE region
Platform Data
N/A N/A N/A
Region
Datasheet 289
Functional Description
5.26.3 Flash Access
There are two types of flash accesses:
Direct Access:
• Masters are allowed to do direct read only of their primary region
— Gigabit Ethernet region can only be directly accessed by the Gigabit Ethernet
controller. Gigabit Ethernet software must use Program Registers to access the
Gigabit Ethernet region.
• Master's Host or Management Engine virtual read address is converted into the SPI
Flash Linear Address (FLA) using the Flash Descriptor Region Base/Limit registers
Program Register Access:
• Program Register Accesses are not allowed to cross a 4 KB boundary and can not
issue a command that might extend across two components
• Software programs the FLA corresponding to the region desired
— Software must read the devices Primary Region Base/Limit address to create a
FLA.
5.26.3.1 Direct Access Security
• Requester ID of the device must match that of the primary Requester ID in the
Master Section
• Calculated Flash Linear Address must fall between primary region base/limit
• Direct Write not allowed
• Direct Read Cache contents are reset to 0's on a read from a different master
— Supports the same cache flush mechanism in ICH7 which includes Program
Register Writes
5.26.3.2 Register Access Security
• Only primary region masters can access the registers
Note: Processor running Gigabit Ethernet software can access Gigabit Ethernet registers
• Masters are only allowed to read or write those regions they have read/write
permission
• Using the Flash Region Access Permissions, one master can give another master
read/write permissions to their area
• Using the five Protected Range registers, each master can add separate read/write
protection above that granted in the Flash Descriptor for their own accesses
— Example: BIOS may want to protect different regions of BIOS from being
erased
— Ranges can extend across region boundaries
290 Datasheet
Functional Description
5.26.4 Serial Flash Device Compatibility Requirements
A variety of serial flash devices exist in the market. For a serial flash device to be
compatible with the PCH SPI bus, it must meet the minimum requirements detailed in
the following sections.
Note: All PCH platforms have require Intel Management Engine Firmware.
5.26.4.1 PCH SPI Based BIOS Requirements
A serial flash device must meet the following minimum requirements when used
explicitly for system BIOS storage.
• Erase size capability of at least one of the following: 64 Kbytes, 8 Kbytes, 4 Kbytes,
or 256 bytes.
• Device must support multiple writes to a page without requiring a preceding erase
cycle (Refer to Section 5.26.5)
• Serial flash device must ignore the upper address bits such that an address of
FFFFFFh aliases to the top of the flash memory.
• SPI Compatible Mode 0 support (clock phase is 0 and data is latched on the rising
edge of the clock).
• If the device receives a command that is not supported or incomplete (less than 8
bits), the device must complete the cycle gracefully without any impact on the flash
content.
• An erase command (page, sector, block, chip, and so on) must set all bits inside the
designated area (page, sector, block, chip, and so on) to 1 (Fh).
• Status Register bit 0 must be set to 1 when a write, erase or write to status register
is in progress and cleared to 0 when a write or erase is NOT in progress.
• Devices requiring the Write Enable command must automatically clear the Write
Enable Latch at the end of Data Program instructions.
• Byte write must be supported. The flexibility to perform a write between 1 byte to
64 bytes is recommended.
• Hardware Sequencing requirements are optional in BIOS only platforms.
• SPI flash parts that do not meet Hardware sequencing command set requirements
may work in BIOS only platforms using software sequencing.
5.26.4.2 Integrated LAN Firmware SPI Flash Requirements
A serial flash device that will be used for system BIOS and Integrated LAN or
Integrated LAN only must meet all the SPI Based BIOS Requirements plus:
• Hardware sequencing
• 4, 8, or 64 KB erase capability must be supported.
5.26.4.2.1 SPI Flash Unlocking Requirements for Integrated LAN
BIOS must ensure there is no SPI flash based read/write/erase protection on the GbE
region. GbE firmware and drivers for the integrated LAN need to be able to read, write
and erase the GbE region at all times.
Datasheet 291
Functional Description
5.26.4.3 Intel® Management Engine Firmware (Intel® ME FW) SPI Flash
Requirements
Intel Management Engine Firmware must meet the SPI flash based BIOS Requirements
plus:
• Hardware Sequencing.
• Flash part must be uniform 4-KB erasable block throughout the entire device or
have 64 KB blocks with the first block (lowest address) divided into 4-KB or 8-KB
blocks.
• Write protection scheme must meet SPI flash unlocking requirements for Intel ME.
5.26.4.3.1 SPI Flash Unlocking Requirements for Intel® Management Engine (Intel® ME)
Flash devices must be globally unlocked (read, write and erase access on the ME
region) from power on by writing 00h to the flash’s status register to disable write
protection.
If the status register must be unprotected, it must use the enable write status register
command 50h or write enable 06h.
Opcode 01h (write to status register) must then be used to write a single byte of 00h
into the status register. This must unlock the entire part. If the SPI flash’s status
register has non-volatile bits that must be written to, bits [5:2] of the flash’s status
register must be all 0h to indicate that the flash is unlocked.
If bits [5:2] return a non zero values, the Intel ME firmware will send a write of 00h to
the status register. This must keep the flash part unlocked.
If there is no need to execute a write enable on the status register, then opcodes 06h
and 50h must be ignored.
After global unlock, BIOS has the ability to lock down small sections of the flash as long
as they do not involve the Intel ME or GbE region.
5.26.4.4 Hardware Sequencing Requirements
Table 5-61 contains a list of commands and the associated opcodes that a SPI-based
serial flash device must support in order to be compatible with hardware sequencing.
Table 5-61. Hardware Sequencing Commands and Opcode Requirements (Sheet 1 of 2)
Commands Opcode Notes
Writes a byte to SPI flash’s status register. Enable Write
Write to Status Register 01h to Status Register command must be run prior to this
command.
Single byte or 64 byte write as determined by flash part
Program Data 02h
capabilities and software.
Read Data 03h
Write Disable 04h
Read Status 05h Outputs contents of SPI flash’s status register
Write Enable 06h
Fast Read 0Bh
Enable Write to Status 50h or Enables a bit in the status register to allow an update to
Register 60h the status register
292 Datasheet
Functional Description
Table 5-61. Hardware Sequencing Commands and Opcode Requirements (Sheet 2 of 2)
Commands Opcode Notes
Program
Erase 256B, 4 Kbyte, 8 Kbyte or 64 Kbyte
mable
Full Chip Erase C7h
JEDEC ID 9Fh See Section 5.26.4.4.3.
5.26.4.4.1 Single Input, Dual Output Fast Read
The PCH now supports the functionality of a single input, dual output fast read. Opcode
and address phase are shifted in serially to the serial flash SI (Serial In) pin. Data is
read out after 8 clocks (dummy bits or wait states) from the both the SI and SO pin
effectively doubling the through put of each fast read output. In order to enable this
functionality, both Single Input Dual Output Fast Read Supported and Fast Read
supported must be enabled
5.26.4.4.2 Serial Flash Discoverable Parameters (SFDP)
As the number of features keeps growing in the serial flash, the need for correct,
accurate configuration increases. A method of determining configuration information is
Serial Flash Discoverable Parameters (SFDP). Information such as VSCC values and
flash attributes can be read directly from the flash parts. The discoverable parameter
read opcode behaves like a fast read command. The opcode is 5Ah and the address
cycle is 24 bits long. After the opcode 5Ah and address are clocked in, there will then
be eight clocks (8 wait states) before valid data is clocked out. SFDP is a capability of
the flash part, please confirm with target flash vendor to see if it is supported.
In order for BIOS to take advantage of the 5Ah opcode it needs to be programmed in
the Software sequencing registers.
5.26.4.4.3 JEDEC ID
Since each serial flash device may have unique capabilities and commands, the JEDEC
ID is the necessary mechanism for identifying the device so the uniqueness of the
device can be comprehended by the controller (master). The JEDEC ID uses the opcode
9Fh and a specified implementation and usage model. This JEDEC Standard
Manufacturer and Device ID read method is defined in Standard JESD21-C, PRN03-NV.
Datasheet 293
Functional Description
5.26.5 Multiple Page Write Usage Model
The system BIOS and Intel Management Engine firmware usage models require that
the serial flash device support multiple writes to a page (minimum of 512 writes)
without requiring a preceding erase command. BIOS commonly uses capabilities such
as counters that are used for error logging and system boot progress logging. These
counters are typically implemented by using byte-writes to ‘increment’ the bits within a
page that have been designated as the counter. The Intel ME firmware usage model
requires the capability for multiple data updates within any given page. These data
updates occur using byte-writes without executing a preceding erase to the given page.
Both the BIOS and Intel ME firmware multiple page write usage models apply to
sequential and non-sequential data writes.
Note: This usage model requirement is based on any given bit only being written once from a
‘1’ to a ‘0’without requiring the preceding erase. An erase would be required to change
bits back to the 1 state.
5.26.5.1 Soft Flash Protection
There are two types of flash protection that are not defined in the flash descriptor
supported by PCH:
1. BIOS Range Write Protection
2. SMI#-Based Global Write Protection
Both mechanisms are logically OR’d together such that if any of the mechanisms
indicate that the access should be blocked, then it is blocked. Table 5-62 provides a
summary of the mechanisms.
Table 5-62. Flash Protection Mechanism Summary
Reset-Override
Accesses Range Equivalent Function on
Mechanism or SMI#-
Blocked Specific? FWH
Override?
BIOS Range
Write Writes Yes Reset Override FWH Sector Protection
Protection
Same as Write Protect in
Write Protect Writes No SMI# Override
Intel® ICHs for FWH
A blocked command will appear to software to finish, except that the Blocked Access
status bit is set in this case.
5.26.5.2 BIOS Range Write Protection
The PCH provides a method for blocking writes to specific ranges in the SPI flash when
the Protected BIOS Ranges are enabled. This is achieved by checking the Opcode type
information (which can be locked down by the initial Boot BIOS) and the address of the
requested command against the base and limit fields of a Write Protected BIOS range.
Note: Once BIOS has locked down the Protected BIOS Range registers, this mechanism
remains in place until the next system reset.
294 Datasheet
Functional Description
5.26.5.3 SMI# Based Global Write Protection
The PCH provides a method for blocking writes to the SPI flash when the Write
Protected bit is cleared (that is, protected). This is achieved by checking the Opcode
type information (which can be locked down by the initial Boot BIOS) of the requested
command.
The Write Protect and Lock Enable bits interact in the same manner for SPI BIOS as
they do for the FWH BIOS.
5.26.6 Flash Device Configurations
The PCH-based platform must have a SPI flash connected directly to the PCH with a
valid descriptor and Intel Management Engine Firmware. BIOS may be stored in other
locations such as Firmware Hub and SPI flash hooked up directly to an embedded
controller for Mobile platforms. Note this will not avoid the direct SPI flash connected to
PCH requirement.
5.26.7 SPI Flash Device Recommended Pinout
Table 5-63 contains the recommended serial flash device pin-out for an 8-pin device.
Use of the recommended pin-out on an 8-pin device reduces complexities involved with
designing the serial flash device onto a motherboard and allows for support of a
common footprint usage model (refer to Section 5.26.8.1).
Table 5-63. Recommended Pinout for 8-Pin Serial Flash Device
Pin # Signal
1 Chips Select
2 Data Output
3 Write Protect
4 Ground
5 Data Input
6 Serial Clock
7 Hold / Reset
8 Supply Voltage
Although an 8-pin device is preferred over a 16-pin device due to footprint
compatibility, the following table contains the recommended serial flash device pin-out
for a 16-pin SOIC.
Datasheet 295
Functional Description
5.26.8 Serial Flash Device Package
Table 5-64. Recommended Pinout for 16-Pin Serial Flash Device
Pin # Signal Pin # Signal
1 Hold / Reset 9 Write Protect
2 Supply Voltage 10 Ground
3 No Connect 11 No Connect
4 No Connect 12 No Connect
5 No Connect 13 No Connect
6 No Connect 14 No Connect
7 Chip Select 15 Serial Data In
8 Serial Data Out 16 Serial Clock
5.26.8.1 Common Footprint Usage Model
In order to minimize platform motherboard redesign and to enable platform Bill of
Material (BOM) selectability, many PC System OEMs design their motherboard with a
single common footprint. This common footprint allows population of a soldered down
device or a socket that accepts a leadless device. This enables the board manufacturer
to support, using selection of the appropriate BOM, either of these solutions on the
same system without requiring any board redesign.
The common footprint usage model is desirable during system debug and by flash
content developers since the leadless device can be easily removed and reprogrammed
without damage to device leads. When the board and flash content is mature for high-
volume production, both the socketed leadless solution and the soldered down leaded
solution are available through BOM selection.
5.26.8.2 Serial Flash Device Package Recommendations
It is highly recommended that the common footprint usage model be supported. An
example of how this can be accomplished is as follows:
• The recommended pinout for 8-pin serial flash devices is used (see
Section 5.26.7).
• The 8-pin device is supported in either an 8-contact VDFPN (6x5 mm MLP) package
or an 8-contact WSON (5x6 mm) package. These packages can fit into a socket
that is land pattern compatible with the wide body SO8 package.
• The 8-pin device is supported in the SO8 (150 mil) and in the wide-body SO8
(200 mil) packages.
The 16-pin device is supported in the SO16 (300 mil) package.
296 Datasheet
Functional Description
5.26.9 PWM Outputs (Server/Workstation Only)
This signal is driven as open-drain. An external pull-up resistor is integrated into the
fan to provide the rising edge of the PWM output signal. The PWM output is driven low
during reset, which represents 0% duty cycle to the fans. After reset de-assertion, the
PWM output will continue to be driven low until one of the following occurs:
• The internal PWM control register is programmed to a non-zero value by
appropriate firmware.
• The watchdog timer expires (enabled and set at 4 seconds by default).
• The polarity of the signal is inverted by firmware.
If a PWM output will be programmed to inverted polarity for a particular fan, then the
low voltage driven during reset represents 100% duty cycle to the fan.
5.26.10 TACH Inputs (Server/Workstation Only)
This signal is driven as an open-collector or open-drain output from the fan. An
external pull-up is expected to be implemented on the motherboard to provide the
rising edge of the TACH input. This signal has analog hysteresis and digital filtering due
to the potentially slow rise and fall times. This signal has a weak internal pull-up
resistor to keep the input buffer from floating if the TACH input is not connected to a
fan.
5.27 Feature Capability Mechanism
A set of registers is included in the PCH LPC Interface (Device 31, Function 0, offset
E0h–EBh) that allows the system software or BIOS to easily determine the features
supported by the PCH. These registers can be accessed through LPC PCI configuration
space, thus allowing for convenient single point access mechanism for chipset feature
detection.
This set of registers consists of:
• Capability ID (FDCAP)
• Capability Length (FDLEN)
• Capability Version and Vendor-Specific Capability ID (FDVER)
• Feature Vector (FVECT)
Datasheet 297
Functional Description
5.28 PCH Display Interface and Intel® Flexible Display
Interface (Intel® FDI) Interconnect
Display is divided between processor and PCH. The processor houses memory
interface, display planes, pipes and digital display interfaces/ports while PCH has
transcoder and analog display interface or port. Intel FDI connects the processor and
PCH display engine. The new generation PCH integrates analog display interface only.
Figure 5-16 shows the PCH Display Architecture.
Figure 5-16. PCH Display Architecture
PCH Display Engine
Processor Display Engine
PWM
Backlight Enable
DMI Panel Power Enable
DDC
Contoller
Intel FDI
Transcoder Timing
(Rx Side) generator & FIFO CRT DAC
x2
DisplayPort
AUX CH
The PCH Analog Port uses an integrated 180 MHz RAMDAC that can directly drive a
standard progressive scan analog monitor up to a resolution of 1920x2000 pixels with
24-bit color at 60 Hz with reduced blanking.
298 Datasheet
Functional Description
5.28.1 Analog Display Interface Characteristics
The Analog Port provides a RGB signal output along with a HSYNC and VSYNC signal.
There is an associated Display Data Channel (DDC) signal pair that is implemented
using GPIO pins dedicated to the Analog Port. The intended target device is for a moni-
tor with a VGA connector. Display devices such as LCD panels with analog inputs may
work satisfactory but no functionality added to the signals to enhance that capability.
Figure 5-17. Analog Port Characteristics
5.28.1.1 Integrated RAMDAC
The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that
transforms the digital data from the graphics and video subsystems to analog data for
the VGA monitor. The PCH’s integrated 180 MHz RAMDAC supports resolutions up to
1920x2000 at 60 Hz. Three 8-bit DACs provide the R, G, and B signals to the monitor.
5.28.1.1.1 Sync Signals
HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector.
Since these levels cannot be generated internal to the device, external level shifting
buffers are required. These signals can be polarity adjusted and individually disabled in
one of the two possible states. The sync signals should power up disabled in the high
state. No composite sync or special flat panel sync support are included.
5.28.1.1.2 VESA*/VGA Mode
VESA/VGA mode provides compatibility for pre-existing software that set the display
mode using the VGA CRTC registers. Timings are generated based on the VGA register
values and the timing generator registers are not used.
5.28.1.2 DDC (Display Data Channel)
DDC is a standard defined by VESA. Its purpose is to allow communication between the
host system and display. Both configuration and control information can be exchanged
allowing plug- and-play systems to be realized. The PCH uses the DDC_CLK and
DDC_DATA signals to communicate with the analog monitor. These signals are open
drain and are 3.3 V tolerant. External pull-up resistors and level shifting circuitry should
be implemented on the board.
Datasheet 299
Functional Description
5.28.2 Digital Display Side Band Signals
The PCH integrates digital display side band signals AUX CH, DDC bus and Hot-Plug
Detect signals even though digital display interfaces are moved to processor. There are
three pairs of AUX CH, DDC Clock/Data and Hot-Plug Detect Signals on PCH that corre-
spond to digital display interface/ports B, C and D.
5.28.2.1 DisplayPort AUX CH
Auxiliary Channel (AUX CH) is a half-duplex bidirectional channel used for link manage-
ment and device control. AUX CH is a AC coupled differential signal.
5.28.2.2 DDC (Display Data Channel)
DDC bus as mentioned in the Section 5.28.1.2 is used for communication between the
host system and display. Three pairs of DDC (DDC_CLK and DDC_DATA) signals exist
on the PCH which corresponds to three digital ports on the Processor. DDC follows I2C
protocol.
5.28.2.3 Hot-Plug Detect
The Hot-Plug Detect (HPD) signal serves as an interrupt request for the sink device for
DisplayPort and HDMI. Its a 3.3 V tolerant signal pin on PCH.
5.28.2.4 Map of Digital Display Side Band Signals Per Display Configuration
The table below lists PCH display side band signals associated with each digital port in
the processor. Depending on whether a digital interface is configured as HDMI or
DisplayPort on the processor, the corresponding signal on the PCH must be routed on
the board as indicated by the table.
300 Datasheet
Functional Description
Display Digital Interface PCH Signals
Interface Configured as DisplayPort
• DDPB_AUXP
• DDPB_AUXN
Interface Configured as HDMI
Digital Display Interface B
• DDPB_CTRLCLK
• DDPB_CTRLDATA
Interface Configured as DisplayPort/HDMI
• DDPB_HPD
Interface Configured as DisplayPort
DDPC_AUXP
DDPC_AUXN
Interface Configured as HDMI
Digital Display Interface C
DDPC_CTRLCLK
DDPC_CTRLDATA
Interface Configured as DisplayPort/HDMI
DDPC_HPD
Interface Configured as DisplayPort
DDPD_AUXP
DDPD_AUXN
Interface Configured as HDMI
Digital Display Interface D
DDPD_CTRLCLK
DDPD_CTRLDATA
Interface Configured as DisplayPort/HDMI
DDPD_HPD
5.28.2.5 Panel Power Sequencing and Backlight Control
PCH continues to integrate Panel power sequencing and Backlight control signals for
the eDP interface on the processor.
This section provides details for the power sequence timing relationship of the panel
power, the backlight enable and the eDP* data timing delivery. To meet the panel
power timing specification requirements two signals, eDP_VDD_EN and eDP_BKLT_EN,
are provided to control the timing sequencing function of the panel and the backlight
power supplies.
A defined power sequence is recommended when enabling the panel or disabling the
panel. The set of timing parameters can vary from panel to panel vendor, provided that
they stay within a predefined range of values. The panel VDD power, the backlight on/
off state and the eDP data lines are all managed by an internal power sequencer.
Datasheet 301
Functional Description
Figure 5-18. Panel Power Sequencing
T4 T1+T2 T5 TX T3 T4
Panel
On
Panel VDD
Enable
Panel
BackLight
Enable
Off Off
Valid
Clock/Data Lines
Power On Sequence from off state and
Power Off Sequence after full On
NOTE: Support for programming parameters TX and T1 through T5 using software is provided.
5.28.3 Intel® Flexible Display Interface (Intel® FDI)
Intel FDI connects the display engine in the processor with the analog display interface/
port on the PCH. The display data from the frame buffer is processed in the display
engine of the processor and sent to the PCH over the Intel FDI where it is transcoded as
per the display protocol and driven through the DAC to the analog display monitor.
The new generation PCH supports two Intel FDI lanes to send the data to Analog VGA
interface. An Intel FDI channel consists of two lanes made up of differential signal pair.
An Intel FDI lane supports data rate of 2.7 Gb/s. Intel® FDI continues to support lane
reversal and polarity inversion.
5.29 Intel® Virtualization Technology (Intel® VT)
Intel Virtualization Technology (Intel VT) makes a single system appear as multiple
independent systems to software. This allows for multiple, independent operating
systems to be running simultaneously on a single system. Intel VT comprises
technology components to support virtualization of platforms based on Intel
architecture microprocessors and chipsets. The first revision of this technology (Intel
VT-x) added hardware support in the processor to improve the virtualization
performance and robustness. The second revision of this specification (Intel VT-d) adds
chipset hardware implementation to improve I/O performance and robustness.
The Intel VT-d specification and other VT documents can be referenced here: http://
www.intel.com/technology/platform-technology/virtualization/index.htm
5.29.1 Intel® Virtualization Technology (Intel® VT) for
Directed I/O (Intel® VT-d) Objectives
The key Intel VT-d objectives are domain based isolation and hardware based
virtualization. A domain can be abstractly defined as an isolated environment in a
platform to which a subset of host physical memory is allocated. Virtualization allows
for the creation of one or more partitions on a single system. This could be multiple
partitions in the same OS or there can be multiple operating system instances running
on the same system offering benefits such as system consolidation, legacy migration,
activity partitioning or security.
302 Datasheet
Functional Description
5.29.2 Intel® VT-d Features Supported
• The following devices and functions support FLR in the PCH:
— High Definition Audio (Device 27: Function 0)
— SATA Host Controller 1 (Device 31: Function 2)
— SATA Host Controller 2 (Device 31: Function 5)
— USB2 (EHCI) Host Controller 1 (Device 29: Function 0)
— USB2 (EHCI) Host Controller 2 (Device 26: Function 0)
— GbE Lan Host Controller (Device 25: Function 0)
• Interrupt virtualization support for IOxAPIC
• Virtualization support for HPETs
5.29.3 Support for Function Level Reset (FLR) in PCH
Intel VT-d allows system software (VMM/OS) to assign I/O devices to multiple domains.
The system software, then, requires ways to reset I/O devices or their functions within,
as it assigns/re-assigns I/O devices from one domain to another. The reset capability is
required to ensure the devices have undergone proper re-initialization and are not
keeping the stale state. A standard ability to reset I/O devices is also useful for the
VMM in case where a guest domain with assigned devices has become unresponsive or
has crashed.
PCI Express defines a form of device hot reset which can be initiated through the
Bridge Control register of the root/switch port to which the device is attached. How-
ever, the hot reset cannot be applied selectively to specific device functions. Also, no
similar standard functionality exists for resetting root-complex integrated devices.
Current reset limitations can be addressed through a function level reset (FLR) mecha-
nism that allows software to independently reset specific device functions.
5.29.4 Virtualization Support for PCH IOxAPIC
The Intel VT-d architecture extension requires Interrupt Messages to go through the
similar Address Remapping as any other memory requests. This is to allow domain
isolation for interrupts such that a device assigned in one domain is not allowed to
generate interrupts to another domain.
The Address Remapping for Intel VT-d is based on the Bus:Device:Function field
associated with the requests. Hence, it is required for the internal IOxAPIC to initiate
the Interrupt Messages using a unique Bus:Device:Function.
The PCH supports BIOS programmable unique Bus:Device:Function for the internal
IOxAPIC. The Bus:Device:Function field does not change the IOxAPIC functionality in
anyway, nor promoting IOxAPIC as a stand-alone device. The field is only used by the
IOxAPIC in the following:
• As the Requestor ID when initiating Interrupt Messages to the processor
• As the Completer ID when responding to the reads targeting the IOxAPIC’s
Memory-Mapped I/O registers
Datasheet 303
Functional Description
5.29.5 Virtualization Support for High Precision Event Timer
(HPET)
The Intel VT-d architecture extension requires Interrupt Messages to go through the
similar Address Remapping as any other memory requests. This is to allow domain
isolation for interrupts such that a device assigned in one domain is not allowed to
generate interrupts to another domain.
The Address Remapping for Intel VT-d is based on the Bus:Device:Function field
associated with the requests. Hence, it is required for the HPET to initiate the direct
FSB Interrupt Messages using unique Bus:Device:Function.
The PCH supports BIOS programmable unique Bus:Device:Function for each of the
HPET timers. The Bus:Device:Function field does not change the HPET functionality in
anyway, nor promoting it as a stand-alone device. The field is only used by the HPET
timer in the following:
• As the Requestor ID when initiating direct interrupt messages to the processor
• As the Completer ID when responding to the reads targeting its Memory-Mapped
registers
• The registers for the programmable Bus:Device:Function for HPET timer 7:0 reside
under the D31:F0 LPC Bridge’s configuration space.
§§
304 Datasheet
Ballout Definition
6 Ballout Definition
This chapter contains the PCH Ballout information.
6.1 Desktop/Server PCH Ballout
This section contains the Desktop/Server PCH ballout. Figure 6-1, Figure 6-2,
Figure 6-3, and Figure 6-4 show the ballout from a top of the package quadrant view.
Table 6-1 is the BGA ball list, sorted alphabetically by signal name.
Note: References to PWM[3:0], TACH[7:0], SST, NMI#, SMI# are for Server/Workstation
SKUs only. Pin names PWM[3:0], TACH[7:0], SST, NMI#, SMI# are Reserved on
Desktop SKUs. See Chapter 2 for further details.
Datasheet 305
Ballout Definition
Figure 6-1. Desktop/Server PCH Ballout (Top View - Upper Left)
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306 Datasheet
Ballout Definition
Figure 6-3. Desktop/Server PCH Ballout (Top View - Upper Right)
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s^^ ^>Wͺ^h^η ^>Wͺ^ϯη WtZdEη <
^>Wͺt>Eηͬ >EͺW,zͺWtZ
WtDϬ s^^
'W/KϮϵ ͺdZ>ͬ'W/KϭϮ >
></EͺϯϯD,> WZ ^ Edͬ
KKW<
s^^ s^^ d,Ϯͬ'W/Kϲ WtDϭ s^h^ϯͺϯ dWϮϱ s^^
'W/Kϯϭ
s^^ Z^DZ^dη ^tsZD E D
,ͺK<ͺZ^
dηͬ'W/Kϭϯ
>Ϭ >ϯ s^^ s^h^ϯͺϯ ^>Wͺη ZdyϮ Zdyϭ E
d,Ϭͬ
sh^W>> >&ZD η >ϭ
'W/Kϭϳ
WtDϮ sZd s^h^ϯͺϯ W
W/ZY ηͬ'W/KϮ s^^ s^^ ZdZ^dη ^ZdZ^dη /EdZh Zη Z
W/ZY,ηͬ d,ϰͬ d,ϳͬ
,ͺ^/Ϯ s^^ s^^ ,ͺ^/Ϭ
'W/Kϱ
s^^ s^^
'W/Kϲϴ
d,ϭͬ'W/Kϭ s^^
'W/Kϳϭ
^>Wͺ^ϰη s^^ s^^ WtZK< s^^ d
,ͺ^K ,ͺZ^dη W/ZYη W/ZYη 'W/Kϱϭ 'W/KϮϳ ^>Wͺ>Eη s^^ W^h^zW W^h^zW h
K< Eηͬ W/ZY'ηͬ d,ϱͬ
,ͺ^/ϭ ,ͺ>< ,ͺ^zE
'W/Kϯϯ
W/ZYη
'W/Kϰ
W/ZY&ηͬ'W/Kϯ WtDϯ 'W/Kϱϯ s^^ d,ϯͬ'W/Kϳ
'W/Kϲϵ
/EdsZD E WtZK< s^tϯͺϯ s^^ s^^ s
,ͺ^/ϯ s^h^, W/ZYη s^^ 'W/Kϱϰ WZd s^tϯͺϯ s^tϯͺϯ s^^ t
ϮϮ Ϯϯ Ϯϰ Ϯϱ Ϯϲ Ϯϳ Ϯϴ Ϯϵ ϯϬ ϯϭ ϯϮ ϯϯ ϯϰ ϯϱ ϯϲ ϯϳ ϯϴ ϯϵ ϰϬ ϰϭ
Datasheet 307
Ballout Definition
Table 6-1. Desktop/ Table 6-1. Desktop/ Table 6-1. Desktop/
Server PCH Ballout By Server PCH Ballout By Server PCH Ballout By
Signal Name (Sheet 1 of Signal Name (Sheet 2 of Signal Name (Sheet 3 of
18) 18) 18)
EDS Net Name EDS Net Name EDS Net Name
Pin # Pin # Pin #
REV 0.7 REV 0.7 REV 0.7
ACPRESENT / CLKOUT_PCIE_P3 W10 DMI_RCOMP B19
AM36
GPIO31 CLKOUT_PCIE_P4 Y2 DMI_RXN0 L24
APWROK AA32 CLKOUT_PCIE_P5 W6 DMI_RXN1 G24
BMBUSY# / GPIO0 G38 CLKOUT_PCIE_P6 AA6 DMI_RXN2 F26
CL_CLK U36 CLKOUT_PCIE_P7 R7 DMI_RXN3 K26
CL_DATA U35 CLKOUT_PEG_A_N AA3 DMI_RXP0 K24
CL_RST# U34 CLKOUT_PEG_A_P AA2 DMI_RXP1 H24
CLKIN_33MHZLOOP CLKOUT_PEG_B_N AE6 DMI_RXP2 G26
AM22
BACK
CLKOUT_PEG_B_P AE7 DMI_RXP3 L26
CLKIN_DMI_N G22
CLKOUTFLEX0 / DMI_TXN0 C20
CLKIN_DMI_P F22 AV8
GPIO64 DMI_TXN1 D21
CLKIN_DOT96_N AP11 CLKOUTFLEX1 /
AT9 DMI_TXN2 B22
CLKIN_DOT96_P AM11 GPIO65
DMI_TXN3 A24
CLKIN_GND_N G16 CLKOUTFLEX2 /
AV9 DMI_TXP0 B20
CLKIN_GND_P F16 GPIO66
DMI_TXP1 B21
CLKIN_SATA_N H35 CLKOUTFLEX3 /
AU8
GPIO67 DMI_TXP2 C22
CLKIN_SATA_P H36
DAC_IREF AF5 DMI_TXP3 B24
CLKOUT_33MHZ0 AV5
DCPRTC AW35 DOCKEN# / GPIO33 AV26
CLKOUT_33MHZ1 AV7
DCPSST AH28 DPWROK AV38
CLKOUT_33MHZ2 AU2
DCPSUS1 AE30 DRAMPWROK AE38
CLKOUT_33MHZ3 AN9
DCPSUS2 AJ22 DSWVRMEN AM41
CLKOUT_33MHZ4 AU5
DCPSUS3 P19 eDP_BKLTCTL AP2
CLKOUT_DMI_N R2
DCPSUSBYP AU40 eDP_BKLTEN AT2
CLKOUT_DMI_P T2
DCPSUSBYP AU41 eDP_VDDEN AP1
CLKOUT_DP_N T3
DDPB_AUXN AK6 FDI_CSYNC L2
CLKOUT_DP_P T5
DDPB_AUXP AK8 FDI_INT L3
CLKOUT_DPNS_N W2
DDPB_CTRLCLK AM1 FDI_IREF N11
CLKOUT_DPNS_P U2
DDPB_CTRLDATA AJ5 FDI_RCOMP K2
CLKOUT_ITPXDP_N U6
DDPB_HPD AJ2 FDI_RXN0 N1
CLKOUT_ITPXDP_P U7
DDPC_AUXN AG7 FDI_RXN1 P2
CLKOUT_PCIE_N0 AE10
DDPC_AUXP AG6 FDI_RXP0 N2
CLKOUT_PCIE_N1 AC6
DDPC_CTRLCLK AN3 FDI_RXP1 P3
CLKOUT_PCIE_N2 AC11
DDPC_CTRLDATA AM2 GPIO15 AC32
CLKOUT_PCIE_N3 W11
DDPC_HPD AH5 GPIO24 AE34
CLKOUT_PCIE_N4 Y4
DDPD_AUXN AG11 GPIO27 AU34
CLKOUT_PCIE_N5 W7
DDPD_AUXP AG10 GPIO28 V41
CLKOUT_PCIE_N6 AA7
DDPD_CTRLCLK AN4 GPIO32 N32
CLKOUT_PCIE_N7 R6
DDPD_CTRLDATA AN2 GPIO34 N34
CLKOUT_PCIE_P0 AE11
DDPD_HPD AJ4 GPIO35 / NMI# M40
CLKOUT_PCIE_P1 AC7
DIFFCLK_BIASREF R11 GPIO50 AH26
CLKOUT_PCIE_P2 AC10
DMI_IREF A19 GPIO51 AU31
308 Datasheet
Ballout Definition
Table 6-1. Desktop/ Table 6-1. Desktop/ Table 6-1. Desktop/
Server PCH Ballout By Server PCH Ballout By Server PCH Ballout By
Signal Name (Sheet 4 of Signal Name (Sheet 5 of Signal Name (Sheet 6 of
18) 18) 18)
EDS Net Name EDS Net Name EDS Net Name
Pin # Pin # Pin #
REV 0.7 REV 0.7 REV 0.7
GPIO52 AJ26 PCIE_IREF B13 PETn8 H2
GPIO53 AV31 PCIE_RCOMP C13 PETp1 / USB3Tp3 B11
GPIO54 AW33 PCIECLKRQ0# / PETp2 / USB3Tp4 C11
W34
GPIO55 R30 GPIO73 PETp3 A9
GPIO57 AC36 PCIECLKRQ1# / PETp4 C8
P39
GPIO18
GPIO72 AJ40 PETp5 A7
PCIECLKRQ2# /
GPIO8 AC40 P37 PETp6 D2
GPIO20 / SMI#
HDA_BCLK AV23 PETp7 G5
PCIECLKRQ3# /
AA39
HDA_DOCK_RST# / GPIO25 PETp8 H1
AN22
GPIO13 PCIECLKRQ4# / PIRQA# AU29
HDA_RST# AU24 W35
GPIO26 PIRQB# AU27
HDA_SDI0 AT26 PCIECLKRQ5# / PIRQC# AW28
AA36
HDA_SDI1 AV22 GPIO44
PIRQD# AV27
HDA_SDI2 AT22 PCIECLKRQ6# /
W32 PIRQE# / GPIO2 AR30
GPIO45
HDA_SDI3 AW23 PIRQF# / GPIO3 AV29
PCIECLKRQ7# /
HDA_SDO AU22 AA40 PIRQG# / GPIO4 AV28
GPIO46
HDA_SYNC AV24 PIRQH# / GPIO5 AT27
PECI G40
ICLK_IREF N10 PLTRST_PROC# F41
PERn1 / USB3Rn3 L14
INTRUDER# AR41 PLTRST# AA37
PERn2 / USB3Rn4 F14
INTVRMEN AV36 PME# AA31
PERn3 F11
JTAG_TCK Y40 PMSYNCH F40
PERn4 J11
JTAG_TDI W39 PROCPWRGD D40
PERn5 G9
JTAG_TDO Y38 PWM0 AL31
PERn6 F7
JTAG_TMS W40 PWM1 AM31
PERn7 K6
LAD0 AN24 PWM2 AP31
PERn8 J2
LAD1 AP26 PWM3 AV30
PERp1 / USB3Rp3 K14
LAD2 AJ24 PWRBTN# AK41
PERp2 / USB3Rp4 G14
LAD3 AN26 PWROK AT40
PERp3 H11
LAN_PHY_PWR_CTR RCIN# K36
AL40 PERp4 L11
L / GPIO12
PERp5 F9 REFCLK14IN AR7
LDRQ0# AK22
PERp6 H7 RI# AE36
LDRQ1# / GPIO23 AK26
PERp7 K8 RSMRST# AM40
LFRAME# AP24
PERP8 J3 RTCRST# AR38
OC0# / GPIO59 AE40
PETn1 / USB3Tn3 B12 RTCX1 AN40
OC1# / GPIO40 AF37
PETn2 / USB3Tn4 D11 RTCX2 AN39
OC2# / GPIO41 AD39
PETn3 B9 SATA_IREF A33
OC3# / GPIO42 AD40
PETn4 B8 SATA_RCOMP D33
OC4# / GPIO43 AF39
PETn5 B7 SATA_RXN0 B28
OC5# / GPIO9 AC41
PETn6 E1 SATA_RXN1 D30
OC6# / GPIO10 AF40
PETn7 G3 SATA_RXN2 A31
OC7# / GPIO14 AG40
SATA_RXN3 B32
Datasheet 309
Ballout Definition
Table 6-1. Desktop/ Table 6-1. Desktop/ Table 6-1. Desktop/
Server PCH Ballout By Server PCH Ballout By Server PCH Ballout By
Signal Name (Sheet 7 of Signal Name (Sheet 8 of Signal Name (Sheet 9 of
18) 18) 18)
EDS Net Name EDS Net Name EDS Net Name
Pin # Pin # Pin #
REV 0.7 REV 0.7 REV 0.7
SATA_RXN4 / PERn1 A26 SLP_WLAN# / TD_IREF C3
AL39
SATA_RXN5 / PERn2 C27 GPIO29 THRMTRIP# C40
SATA_RXP0 A28 SMBALERT# / TP1 A2
AG31
GPIO11
SATA_RXP1 C30 TP10 L5
SMBCLK AG36
SATA_RXP2 B31 TP11 L16
SMBDATA AG32
SATA_RXP3 C32 TP12 L22
SML0ALERT# /
SATA_RXP4 / PERp1 B26 AG35 TP13 N12
GPIO60
SATA_RXP5 / PERp2 B27 TP14 N30
SML0CLK AE32
SATA_TXN0 F31 SML0DATA AE35 TP15 P5
SATA_TXN1 B34 TP16 R4
SML1ALERT# /
SATA_TXN2 B35 TEMP_ALERT#/ AJ39 TP17 R12
SATA_TXN3 G33 GPIO74 TP18 U10
SATA_TXN4 / PETn1 L28 SML1CLK / GPIO58 AK36 TP19 U11
SATA_TXN5 / PETn2 G28 SML1DATA / GPIO75 AK33 TP2 A3
SATA_TXP0 H31 SPI_CLK U39 TP20 W37
SATA_TXP1 C34 SPI_CS0# R38 TP21 AC35
SATA_TXP2 D35 SPI_CS1# R35 TP22 AH24
SATA_TXP3 F33 SPI_CS2# R40 TP23 AJ14
SATA_TXP4 / PETp1 K28 SPI_IO2 U40 TP24 AK14
SATA_TXP5 / PETp2 F28 SPI_IO3 U37 TP25 AM34
SATA0GP / GPIO21 M37 SPI_MISO R36 TP3 B1
SATA1GP / GPIO19 J40 SPI_MOSI P40 TP4 B2
SATA2GP / GPIO36 H40 SPKR R32 TP5 K5
SATA3GP / GPIO37 N41 SRTCRST# AR39 TP6 K16
SATA4GP / GPIO16 M39 SST AJ31 TP7 K22
SATA5GP / GPIO49 N40 SUS_STAT# / TP8 K33
AD37
GPIO61
SATALED# J39 TP9 K34
SUSACK# AJ37
SCLOCK / GPIO22 L38 USB2n0 AV10
SUSCLK / GPIO62 W36
SDATAOUT0 / USB2n1 AV11
R31 SUSWARN# /
GPIO39 USB2n10 AJ18
SUSPWRDNACK / AG41
SDATAOUT1 / USB2n11 AP18
L40 GPIO30
GPIO48
SYS_PWROK W31 USB2n12 AW18
SERIRQ G39
SYS_RESET# N36 USB2n13 AP20
SLOAD / GPIO38 H41
TACH0 / GPIO17 AP28 USB2n2 AN14
SLP_A# AN37
TACH1 / GPIO1 AT31 USB2n3 AJ16
SLP_LAN# AU36
TACH2 / GPIO6 AM28 USB2n4 AU15
SLP_S3# AK40
TACH3 / GPIO7 AV34 USB2n5 AU12
SLP_S4# AT35
TACH4 / GPIO68 AT30 USB2n6 AV14
SLP_S5# / GPIO63 AA35
TACH5 / GPIO69 AV35 USB2n7 AU17
SLP_SUS# AK38
TACH6 / GPIO70 AK28 USB2n8 AW16
TACH7 / GPIO71 AT34 USB2n9 AN16
310 Datasheet
Ballout Definition
Table 6-1. Desktop/ Table 6-1. Desktop/ Table 6-1. Desktop/
Server PCH Ballout By Server PCH Ballout By Server PCH Ballout By
Signal Name (Sheet 10 Signal Name (Sheet 11 Signal Name (Sheet 12
of 18) of 18) of 18)
EDS Net Name EDS Net Name EDS Net Name
Pin # Pin # Pin #
REV 0.7 REV 0.7 REV 0.7
USB2p0 AU10 VCC W23 VCCCLK3_3 AG12
USB2p1 AW11 VCC W25 VCCCLK3_3 AK11
USB2p10 AK18 VCC AA19 VCCCLK3_3 AM7
USB2p11 AN18 VCC AA20 VCCCLK3_3 AM9
USB2p12 AV18 VCC AB1 VCCCLK3_3 AP5
USB2p13 AN20 VCC AB16 VCCCLK3_3 AP7
USB2p2 AP14 VCC AB17 VCCCLK3_3 AR4
USB2p3 AK16 VCC AB19 VCCCLK3_3 AT5
USB2p4 AV15 VCC AB20 VCCCLK3_3 AV3
USB2p5 AT12 VCC AD16 VCCCLK3_3 AV4
USB2p6 AW14 VCC3_3 B6 VCCCLK3_3 AW3
USB2p7 AT17 VCC3_3 U30 VCCCLK3_3 AW4
USB2p8 AV16 VCC3_3 W30 VCCCLK3_3 AW9
USB2p9 AP16 VCC3_3 AF26 VCCDSW3_3 AV39
USB3Rn1 F20 VCC3_3 AG1 VCCDSW3_3 AW38
USB3Rn2 G18 VCC3_3 AW21 VCCDSW3_3 AW39
USB3Rn5 K20 VCCADAC1_5 AF2 VCCIO M14
USB3Rn6 L18 VCCADACBG3_3 AE1 VCCIO P14
USB3Rp1 G20 VCCASW W26 VCCIO P16
USB3Rp2 H18 VCCASW AA23 VCCIO P17
USB3Rp5 L20 VCCASW AA25 VCCIO P22
USB3Rp6 K18 VCCASW AA26 VCCIO P23
USB3Tn1 B18 VCCASW AB22 VCCIO P25
USB3Tn2 B15 VCCASW AB23 VCCIO P26
USB3Tn5 D15 VCCASW AB25 VCCIO P28
USB3Tn6 B14 VCCASW AB26 VCCIO T19
USB3Tp1 C18 VCCASW AD17 VCCIO T20
USB3Tp2 B16 VCCASW AD19 VCCIO AC12
USB3Tp5 C15 VCCASW AD20 VCCIO AF19
USB3Tp6 A14 VCCASW AD22 VCCIO AF20
USBRBIAS AU20 VCCASW AD23 VCCIO AF22
USBRBIAS# AV20 VCCASW AD25 VCCIO AF23
V_PROC_IO C39 VCCASW AF25 VCCRTC AP33
VCC V17 VCCCLK T16 VCCSPI R41
VCC V19 VCCCLK U12 VCCSUS3_3 P20
VCC V20 VCCCLK V14 VCCSUS3_3 AH18
VCC V22 VCCCLK V16 VCCSUS3_3 AH20
VCC V23 VCCCLK W14 VCCSUS3_3 AH22
VCC V25 VCCCLK W16 VCCSUS3_3 AJ20
VCC W17 VCCCLK AA16 VCCSUS3_3 AK20
VCC W19 VCCCLK AB2 VCCSUS3_3 AM33
Datasheet 311
Ballout Definition
Table 6-1. Desktop/ Table 6-1. Desktop/ Table 6-1. Desktop/
Server PCH Ballout By Server PCH Ballout By Server PCH Ballout By
Signal Name (Sheet 13 Signal Name (Sheet 14 Signal Name (Sheet 15
of 18) of 18) of 18)
EDS Net Name EDS Net Name EDS Net Name
Pin # Pin # Pin #
REV 0.7 REV 0.7 REV 0.7
VCCSUS3_3 AN33 VSS D7 VSS H20
VCCSUS3_3 AP35 VSS D8 VSS H22
VCCSUSHDA AW26 VSS D9 VSS H26
VCCUSBPLL AP22 VSS D12 VSS H28
VCCVRM A4 VSS D13 VSS H33
VCCVRM A38 VSS D14 VSS H34
VCCVRM A39 VSS D16 VSS H38
VCCVRM A40 VSS D18 VSS J5
VCCVRM B4 VSS D19 VSS J31
VCCVRM B37 VSS D20 VSS J37
VCCVRM B39 VSS D22 VSS K4
VCCVRM C1 VSS D24 VSS K9
VCCVRM C2 VSS D25 VSS K31
VCCVRM K1 VSS D26 VSS L37
VCCVRM T14 VSS D27 VSS L41
VGA_BLUE AC3 VSS D28 VSS M16
VGA_DDC_CLK AL2 VSS D31 VSS M18
VGA_DDC_DATA AL3 VSS D32 VSS M20
VGA_GREEN AE2 VSS D34 VSS M22
VGA_HSYNC AH3 VSS D37 VSS M24
VGA_IRTN AG4 VSS D41 VSS M26
VGA_RED AC2 VSS E3 VSS M28
VGA_VSYNC AH2 VSS E4 VSS N4
VSS A12 VSS E5 VSS N8
VSS A16 VSS E7 VSS N31
VSS A21 VSS E12 VSS N35
VSS A35 VSS E31 VSS N38
VSS B3 VSS E35 VSS R1
VSS B25 VSS E38 VSS R8
VSS B30 VSS F18 VSS R10
VSS B33 VSS F24 VSS R34
VSS B38 VSS F35 VSS T17
VSS B40 VSS F37 VSS T22
VSS B41 VSS F38 VSS T23
VSS C6 VSS G2 VSS T25
VSS C25 VSS H4 VSS T26
VSS C37 VSS H6 VSS T28
VSS C41 VSS H8 VSS U1
VSS D1 VSS H9 VSS U4
VSS D4 VSS H14 VSS U8
VSS D6 VSS H16 VSS U31
312 Datasheet
Ballout Definition
Table 6-1. Desktop/ Table 6-1. Desktop/ Table 6-1. Desktop/
Server PCH Ballout By Server PCH Ballout By Server PCH Ballout By
Signal Name (Sheet 16 Signal Name (Sheet 17 Signal Name (Sheet 18
of 18) of 18) of 18)
EDS Net Name EDS Net Name EDS Net Name
Pin # Pin # Pin #
REV 0.7 REV 0.7 REV 0.7
VSS U32 VSS AE41 VSS AT10
VSS V26 VSS AF3 VSS AT11
VSS V28 VSS AF14 VSS AT14
VSS V38 VSS AF16 VSS AT15
VSS V40 VSS AF17 VSS AT16
VSS W3 VSS AF28 VSS AT18
VSS W5 VSS AG2 VSS AT20
VSS W8 VSS AG8 VSS AT21
VSS W12 VSS AG30 VSS AT23
VSS W20 VSS AG34 VSS AT24
VSS W22 VSS AG38 VSS AT28
VSS W28 VSS AH14 VSS AT29
VSS Y1 VSS AH16 VSS AT33
VSS Y41 VSS AJ1 VSS AT36
VSS AA5 VSS AJ28 VSS AT38
VSS AA8 VSS AK9 VSS AT41
VSS AA10 VSS AK24 VSS AU1
VSS AA11 VSS AK37 VSS AU3
VSS AA12 VSS AL5 VSS AU39
VSS AA14 VSS AL11 VSS AV1
VSS AA17 VSS AL37 VSS AV2
VSS AA22 VSS AM4 VSS AV12
VSS AA28 VSS AM6 VSS AV17
VSS AA30 VSS AM8 VSS AV21
VSS AA34 VSS AM14 VSS AV33
VSS AB4 VSS AM16 VSS AV40
VSS AB14 VSS AM18 VSS AV41
VSS AB28 VSS AM20 VSS AW2
VSS AC5 VSS AM24 VSS AW7
VSS AC8 VSS AM26 VSS AW30
VSS AC30 VSS AM35 VSS AW40
VSS AC31 VSS AM38 WAKE# AK34
VSS AC34 VSS AN28 XTAL25_IN N7
VSS AC38 VSS AP4 XTAL25_OUT N6
VSS AD14 VSS AP9
VSS AD26 VSS AR11
VSS AD28 VSS AR35
VSS AE4 VSS AR37
VSS AE8 VSS AT1
VSS AE12 VSS AT7
VSS AE31 VSS AT8
Datasheet 313
Ballout Definition
6.2 Mobile PCH Ballout
This section contains the PCH ballout. Figure 6-5, Figure 6-6, Figure 6-7 and Figure 6-8
show the ballout from a top of the package quadrant view. Table 6-2 is the BGA ball
list, sorted alphabetically by signal name.
Figure 6-5. Mobile PCH Ballout (Top View - Upper Left)
ϭ Ϯ ϯ ϰ ϱ ϲ ϳ ϴ ϵ ϭϬ ϭϭ ϭϮ ϭϯ ϭϰ ϭϱ ϭϲ ϭϳ ϭϴ ϭϵ ϮϬ Ϯϭ ϮϮ Ϯϯ
s^^ s^^ s^^ sZd /EdZh Zη 'W/Kϱϯ 'W/KϱϬ d,Ϯͬ'W/Kϲ s^tϯͺϯ >Ϯ >Ϭ ,ͺ^zE
K< Eηͬ
s^^ s^^ ZdyϮ Zdyϭ s^^ ^ZdZ^dη s^^ 'W/KϱϮ s^^
'W/Kϯϯ
s^^ >&ZD η s^^
d,Ϭͬ d,ϰͬ ,ͺK<ͺZ^
^>Wͺ^ϰη ^tsZD E 'W/Kϱϭ 'W/Kϱϰ
'W/Kϭϳ 'W/Kϲϴ
>ϯ >ϭ
dηͬ'W/Kϭϯ
^>Wͺt>Eηͬ d,ϱͬ ></EͺϯϯD,>
s^^
'W/KϮϵ
s^^ ZdZ^dη
'W/Kϲϵ KKW<
>ZYϬη
WZ ^ Edͬ
s^^
'W/Kϯϭ
& ^>Wͺ^h^η ^>Wͺη dWϮϱ WtZK< d,ϭͬ'W/Kϭ s^^ W/ZY&ηͬ'W/Kϯ s^^ ,ͺ^/ϯ
d,ϲͬ >ZYϭηͬ
' s^^ ^>Wͺ>Eη s^^ /EdsZD E
'W/KϳϬ
d,ϯͬ'W/Kϳ W/ZY ηͬ'W/KϮ
'W/KϮϯ
,ͺ^/Ϯ
^D>ϭ> Zdηͬ
d,ϳͬ
, ^>Wͺ^ϯη ZDWtZK< W,,Kdηͬ s^^ s^^ s^^
'W/Kϳϭ
s^^ W/ZYη s^^
'W/Kϳϰ
^h^tZEηͬ
: Z^DZ^dη ^h^WtZE<ͬ
'W/KϯϬ
^D>ϭ><ͬ d>Ktηͬ >EͺW,zͺWtZ
< WtZdEη t< η
'W/Kϱϴ 'W/KϳϮ
s^h^ϯͺϯ s^^
ͺdZ>ͬ'W/KϭϮ
s^^ W/ZYη s^^ ,ͺ^/ϭ
W/ZY'ηͬ
> s^^ WtZK<
'W/Kϰ
s^t W/ZYη ,ͺ^/Ϭ
W/ZY,ηͬ
D Kϳηͬ'W/Kϭϰ Kϰηͬ'W/Kϰϯ
'W/Kϱ
s^^ W/ZYη s^^
^D> Zdηͬ ^D>Ϭ> Zdηͬ ^D>ϭdͬ
E Kϲηͬ'W/KϭϬ Z/η s^^
'W/Kϭϭ 'W/KϲϬ
s^^
'W/Kϳϱ
s^^
W Kϯηͬ'W/KϰϮ KϬηͬ'W/Kϱϵ WZd WZd s s s^^
Z s^^ ^h^<η ^D>Ϭd s^^ ^D>< 'W/KϮϳ s^^ s^^ s^^ s^t s^h^ϯͺϯ s^h^ϯͺϯ
W/ ><ZYϯηͬ
d Kϱηͬ'W/Kϵ
'W/KϮϱ
W 'ͺͺ><ZYη ^h^ͺ^ddηͬ
h KϮηͬ'W/Kϰϭ
ͬ'W/Kϱϲ
s^^
'W/Kϲϭ
^D>Ϭ>< s^^ ^Dd 'W/Kϱϳ W^h^zW s^^ s^t s^t s^t
W/ ><ZYϰηͬ
s Kϭηͬ'W/KϰϬ
'W/KϮϲ
s^^ s^^ s^t s^t s^t
t s^^
W/ ><ZYϳηͬ ^h^><ͬ ^>Wͺ^ϱηͬ
z 'W/Kϴ
'W/Kϰϲ 'W/KϲϮ 'W/Kϲϯ
s^^ 'W/KϮϰ W>dZ^dη W^h^ϭ s^^ s^^ s^t s^t s^t
W/ ><ZYϱηͬ
'W/Kϰϰ
s^^ W^^d s^^ s^t s^^ s^^
W/ ><ZYϬηͬ
'W/Kϳϯ
:d'ͺd< dWϮϬ WtZK< s^^ dWϮϭ 'W/Kϭϱ s^^
Figure 6-6. Mobile PCH Ballout (Top View - Lower Left)
s^^
:d'ͺdD^ :d'ͺdK s^^ ^z^ͺWtZK< s^^ WD η 'W/KϮϴ s^W/ s^^ s^^ s^^ s s
W/ ><ZYϲηͬ
:d'ͺd/
'W/Kϰϱ
sϯͺϯ s^^ s s s
W/ ><ZYϭηͬ W/ ><ZYϮηͬ W 'ͺͺ><ZYη
& 'W/Kϭϴ 'W/KϮϬͬ^D/η ͬ'W/Kϰϳ
>ͺZ^dη s^^ >ͺd >ͺ>< sϯͺϯ
' s^^ sϯͺϯ s^^ s s s
, ^W/ͺDK^/ ^W/ͺD/^K
: ^W/ͺ/Kϯ ^W/ͺ/KϮ s^^ ^W/ͺ^Ϭη s^^ ^W/ͺ^Ϯη ^W/ͺ>< sͺWZKͺ/K sͺWZKͺ/K s^^ s^^ s^^ s^^
^dϯ'Wͬ ^dϱ'Wͬ
< 'W/Kϯϳ 'W/Kϰϵ
s^^ s^^ s/K s/K s/K
> s^^ 'W/Kϱϱ ^W/ͺ^ϭη s^^ ^W<Z ^ Z/ZY s^^
^dKhdϬͬ
D ^z^ͺZ ^ dη
'W/Kϯϵ
s^^ s^^ s/K s/K s/K
^dϰ'Wͬ ^dKhdϭͬ
E 'W/Kϭϲ 'W/Kϰϴ
'W/Kϯϰ ><ZhEη s^^ dWϭϰ ssZD
^dͺdyEϱͬ
W 'W/KϯϱͬED/η ^d> η s^^
W dŶϮ
D/ͺZyEϮ D/ͺZyWϭ s/K
^dͺdyWϱͬ
Z s^^ ^dͺdyEϯ
W dƉϮ
D/ͺZyWϮ D/ͺZyEϭ s/K
^dϬ'Wͬ ^dϮ'Wͬ ^>Kͬ Dh^zηͬ
d 'W/KϮϭ 'W/Kϯϲ
Z/Eη
'W/Kϯϴ 'W/KϬ
s^^ ^dͺdyWϯ s^^ s^^ s^^ s/K
^dϭ'Wͬ
h 'W/Kϭϵ
W>dZ^dͺWZKη
^dͺdyEϰͬ
s d,ZDdZ/Wη WZKWtZ' s^^ s^^ ^dͺdyEϭ s^^
W dŶϭ
dWϳ D/ͺZyEϯ s^^
^dͺdyWϰͬ
t s^^ ^dͺdyEϬ ^dͺdyWϭ ^dͺdyWϮ
W dƉϭ
dWϭϮ D/ͺZyWϯ D/ͺZyEϬ
z W / WD^zE, ^dͺZKDW s^^ ^dͺdyWϬ s^^ ^dͺdyEϮ s^^ D/ͺZKDW s^^ D/ͺZyWϬ
s^^ dWϵ
^>K<ͬ ^dͺZyWϰͬ
dWϴ
'W/KϮϮ
^dͺZyEϮ
W ZƉϭ
D/ͺdyWϮ D/ͺdyWϬ
^dͺZyEϱͬ
s^^ ></Eͺ^dͺW ^dͺZyEϬ ^dͺZyEϭ ^dͺZyEϯ
W ZŶϮ
s^^ D/ͺdyWϯ D/ͺdyWϭ s^^
^dͺZyEϰͬ
s^^ s^^ ^dͺ/Z & s^^ ^dͺZyWϮ s^^
W ZŶϭ
s^^ D/ͺdyEϮ s^^ D/ͺdyEϬ h^ϯdƉϭ
^dͺZyWϱͬ
s^^ s^^ s^^ ></Eͺ^dͺE ^dͺZyWϬ ^dͺZyWϭ ^dͺZyWϯ
W ZƉϮ
D/ͺ/Z & D/ͺdyEϯ D/ͺdyEϭ ssZD
ϭ Ϯ ϯ ϰ ϱ ϲ ϳ ϴ ϵ ϭϬ ϭϭ ϭϮ ϭϯ ϭϰ ϭϱ ϭϲ ϭϳ ϭϴ ϭϵ ϮϬ Ϯϭ ϮϮ Ϯϯ
314 Datasheet
Ballout Definition
Figure 6-7. Mobile PCH Ballout (Top View - Upper Right)
Ϯϰ Ϯϱ Ϯϲ Ϯϳ Ϯϴ Ϯϵ ϯϬ ϯϭ ϯϮ ϯϯ ϯϰ ϯϱ ϯϲ ϯϳ ϯϴ ϯϵ ϰϬ ϰϭ ϰϮ ϰϯ ϰϰ ϰϱ
><KhdͺϯϯD,
,ͺ^K s^h^, h^ϮŶϭϭ h^ϮŶϵ h^ϮŶϴ h^ϮŶϯ h^ϮŶϮ h^ϮŶϭ
ϰ
s^^ s^^ s^^
><KhdͺϯϯD,
,ͺ>< s^^ h^ϮŶϭϬ s^^ h^ϮŶϰ s^^ h^ϮŶϬ s^^
Ϯ
s^^ s^^
><Khd&> yϬͬ
,ͺZ^dη dWϮϮ h^ϮƉϭϭ h^ϮƉϵ h^ϮƉϴ h^ϮƉϯ h^ϮƉϮ h^ϮƉϭ
'W/Kϲϰ
s^^
><KhdͺϯϯD,
s^^ h^ϮƉϭϬ h^ϮƉϰ h^ϮƉϬ s^^
Ϭ
><KhdͺϯϯD,
ϭ
s^^
><Khd&> yϮͬ ><Khd&> yϭͬ ><Khd&> yϯͬ ><KhdͺϯϯD,
h^ϮŶϭϯ h^ϮƉϭϮ s^^ h^ϮŶϱ s^^
'W/Kϲϲ 'W/Kϲϱ 'W/Kϲϳ ϯ
s^^ Z &><ϭϰ/E &
></EͺKdϵϲͺ
h^ϮƉϭϯ h^ϮŶϭϮ h^ϮŶϳ h^ϮƉϱ
W
ĞWͺs E s^^ s^^ '
></EͺKdϵϲͺ
s^^ s^^ h^ϮƉϳ s^^
E
s^^ Wͺ,W s^^ WͺhyW WͺhyE ,
WͺhyE WͺhyW :
h^Z/^η h^Z/^ s^^ h^ϮŶϲ s^^ ĞWͺ<>d E Wͺ,W s^^ Wͺ,W WͺhyE WͺhyW <
sϯͺϯ s><ϯͺϯ s><ϯͺϯ h^ϮƉϲ dWϮϯ s^^ >
s'ϯͺ s'ͺͺd
s^^ s><ϯͺϯ s><ϯͺϯ
ϯ
dWϮϰ s'ͺͺ><
D
WͺdZ>
s^^ ĞWͺ<>dd>
d
s^^ WͺdZ>>< s'ͺ,^zE s'ͺs^zE E
s^^ s^^ s^^ s^^ s^^ s^^ sϭͺϱ W
WͺdZ> WͺdZ>
s^h^ϯͺϯ s^h^ϯͺϯ s^h^ϯͺϯ sϯͺϯ sϯͺϯ s^^ WͺdZ>><
d
s^^
d
WͺdZ>>< s^^ Z
s^^ s'ͺ>h d
s^t s^h^ϯͺϯ s^^ s/K s><ϯͺϯ s^^ sh^W>> s/K s^^ s'ͺ/ZdE ͺ/Z & s^^ s'ͺ'Z E h
s^t s^^ s/K s/K s><ϯͺϯ s^^ s'ͺZ s
s^^ t
><KhdͺW 'ͺ ><KhdͺW 'ͺ ><KhdͺW/ ͺ ><KhdͺW/ ͺ
s^^ s s^^ s/K s>< s^^ W^h^Ϯ s^^
ͺW ͺE
s^^
EϬ WϬ z
><KhdͺW/ ͺ ><KhdͺW/ ͺ
s s s^^ s>< s><
Wϭ Eϭ
><KhdͺW 'ͺ ><KhdͺW 'ͺ ><KhdͺW/ ͺ ><KhdͺW/ ͺ ><KhdͺW/ ͺ ><KhdͺW/ ͺ
s^^
ͺE ͺW
s^^
Wϲ Eϲ EϮ WϮ
Figure 6-8. Mobile PCH Ballout (Top View - Lower Right)
s^^
><KhdͺW/ ͺ ><KhdͺW/ ͺ
s s s s^^ s^^ s>< s>< s>< dWϭϴ dWϭϵ s^^
Eϯ Wϯ
><KhdͺW/ ͺ ><KhdͺW/ ͺ
s s s^^ s>< s><
Wϱ Eϱ
><KhdͺWE^ ><KhdͺWE^ ><KhdͺD/ͺ ><KhdͺD/ͺ ><KhdͺW/ ͺ ><KhdͺW/ ͺ
ssZD
ͺE ͺW
s^^
E W Eϰ Wϰ &
s s^^ s^^ s>< s>< s^^ '
><Khdͺ/dWy ><Khdͺ/dWy
WͺE WͺW ,
><KhdͺW/ ͺ ><KhdͺW/ ͺ
s^^ W^h^ϯ W^h^ϯ s^h^ϯͺϯ s^h^ϯͺϯ s^^ &/ͺZyEϬ &/ͺZyWϬ s^^ ><KhdͺWͺW ><KhdͺWͺE
Wϳ Eϳ :
s^^ ssZD ssZD sϯͺϯ sϯͺϯ s^^ s^^ <
s^^ &/ͺZyEϭ &/ͺZyWϭ s^^ &/ͺ^zE &/ͺ/Ed yd>ϮϱͺKhd >
s^^ s^^ s^^ s^^ s^^ yd>Ϯϱͺ/E /><ͺ/Z & D
/&&><ͺ/^Z
s/K s/K s^^ W ZŶϴ W ZƉϴ s^^ s^^
& E
s^^ h^ϯZƉϭ h^ϯZƉϲ s^^ s^^ s W
W ZƉϮͬ
></Eͺ'EͺE h^ϯZŶϭ h^ϯZŶϲ
h^ϯZƉϰ
W ZƉϰ &/ͺZKDW Z
W ZŶϮͬ
></Eͺ'EͺW s^^ s^^
h^ϯZŶϰ
W ZŶϰ s^^ s^^ W ZƉϳ W ZŶϳ s^^ &/ͺ/Z & d
dWϭϳ dWϭϯ h
s^^ h^ϯZƉϮ h^ϯZƉϱ s^^ s^^ W ZƉϱ s^^ dWϭϲ dWϭϱ s
W ZŶϭͬ
></EͺD/ͺW h^ϯZŶϮ h^ϯZŶϱ
h^ϯZŶϯ
W ZŶϯ W ZŶϱ W ZƉϲ ssZD dWϭϬ t
W ZƉϭͬ
></EͺD/ͺE s^^ s^^
h^ϯZƉϯ
W ZƉϯ s^^ W ZŶϲ dͺ/Z & dWϱ z
s^^ dWϭ
W dƉϮͬ
s^^ dWϲ
h^ϯdƉϰ
W dƉϱ s^^ ssZD
W dƉϭͬ
h^ϯdƉϮ h^ϯdƉϱ s^^ dWϭϭ
h^ϯdƉϯ
W dƉϯ W dƉϰ W dŶϲ W dƉϳ dWϮ
W dŶϮͬ
h^ϯdŶϮ h^ϯdŶϲ W/ ͺZKDW s^^
h^ϯdŶϰ
s^^ W dŶϱ s^^ W dƉϴ W dŶϴ s^^ s^^
W dŶϭͬ
h^ϯdŶϭ h^ϯdŶϱ h^ϯdƉϲ W/ ͺ/Z &
h^ϯdŶϯ
W dŶϯ W dŶϰ W dƉϲ W dŶϳ s^^ dWϰ dWϯ
Ϯϰ Ϯϱ Ϯϲ Ϯϳ Ϯϴ Ϯϵ ϯϬ ϯϭ ϯϮ ϯϯ ϯϰ ϯϱ ϯϲ ϯϳ ϯϴ ϯϵ ϰϬ ϰϭ ϰϮ ϰϯ ϰϰ ϰϱ
Datasheet 315
Ballout Definition
Table 6-2. Mobile PCH Table 6-2. Mobile PCH Table 6-2. Mobile PCH
Ballout by Signal Name Ballout by Signal Name Ballout by Signal Name
(Sheet 1 of 18) (Sheet 2 of 18) (Sheet 3 of 18)
EDS Net Name EDS Net Name EDS Net Name
Pin # Pin # Pin #
Rev 0.7 Rev 0.7 Rev 0.7
ACPRESENT / CLKOUT_PCIE_P2 AB45 DDPD_HPD H39
E6
GPIO31 CLKOUT_PCIE_P3 AD45 DIFFCLK_BIASREF AN44
APWROK AB7 CLKOUT_PCIE_P4 AF45 DMI_IREF BE16
BATLOW# / CLKOUT_PCIE_P5 AE42 DMI_RCOMP AY17
K7
GPIO72
CLKOUT_PCIE_P6 AB39 DMI_RXN0 AW22
BMBUSY# / GPIO0 AT8
CLKOUT_PCIE_P7 AJ42 DMI_RXN1 AR20
CL_CLK AF11
CLKOUT_PEG_A_N AB35 DMI_RXN2 AP17
CL_DATA AF10
CLKOUT_PEG_A_P AB36 DMI_RXN3 AV20
CL_RST# AF7
CLKOUT_PEG_B_N Y39 DMI_RXP0 AY22
CLKIN_33MHZLOO
D17 CLKOUT_PEG_B_P Y38 DMI_RXP1 AP20
PBACK
CLKOUTFLEX0 / DMI_RXP2 AR17
CLKIN_DMI_N AY24 C40
GPIO64 DMI_RXP3 AW20
CLKIN_DMI_P AW24
CLKOUTFLEX1 / DMI_TXN0 BD21
CLKIN_DOT96_N H33 F38
GPIO65
CLKIN_DOT96_P G33 DMI_TXN1 BE20
CLKOUTFLEX2 /
F36 DMI_TXN2 BD17
CLKIN_GND_N AR24 GPIO66
DMI_TXN3 BE18
CLKIN_GND_P AT24 CLKOUTFLEX3 /
F39
CLKIN_SATA_N BE6 GPIO67 DMI_TXP0 BB21
CLKRUN# AN7 DMI_TXP1 BC20
CLKIN_SATA_P BC6
DAC_IREF U40 DMI_TXP2 BB17
CLKOUT_33MHZ0 D44
CLKOUT_33MHZ1 E44 DCPRTC P14 DMI_TXP3 BC18
DCPRTC P16 DOCKEN# /
CLKOUT_33MHZ2 B42 B17
GPIO33
CLKOUT_33MHZ3 F41 DCPSST AA14
DCPSUS1 Y12 DPWROK L13
CLKOUT_33MHZ4 A40
DRAMPWROK H3
CLKOUT_DMI_N AF39 DCPSUS2 Y35
DSWVRMEN C8
CLKOUT_DMI_P AF40 DCPSUS3 AJ26
DCPSUS3 AJ28 eDP_BKLTCTL N36
CLKOUT_DP_N AJ40
eDP_BKLTEN K36
CLKOUT_DP_P AJ39 DCPSUSBYP U14
eDP_VDDEN G36
CLKOUT_DPNS_N AF35 DDPB_AUXN H45
DDPB_AUXP H43 FDI_CSYNC AL39
CLKOUT_DPNS_P AF36
FDI_INT AL40
CLKOUT_ITPXDP_N AH43 DDPB_CTRLCLK R40
FDI_IREF AT45
CLKOUT_ITPXDP_P AH45 DDPB_CTRLDATA R39
DDPB_HPD K40 FDI_RCOMP AR44
CLKOUT_PCIE_N0 Y43
FDI_RXN0 AJ35
CLKOUT_PCIE_N1 AA44 DDPC_AUXN K43
FDI_RXN1 AL35
CLKOUT_PCIE_N2 AB43 DDPC_AUXP K45
DDPC_CTRLCLK R35 FDI_RXP0 AJ36
CLKOUT_PCIE_N3 AD43
FDI_RXP1 AL36
CLKOUT_PCIE_N4 AF43 DDPC_CTRLDATA R36
GPIO15 AB11
CLKOUT_PCIE_N5 AE44 DDPC_HPD K38
DDPD_AUXN J42 GPIO24 Y10
CLKOUT_PCIE_N6 AB40
GPIO27 R11
CLKOUT_PCIE_N7 AJ44 DDPD_AUXP J44
GPIO28 AD11
CLKOUT_PCIE_P0 Y45 DDPD_CTRLCLK N40
DDPD_CTRLDATA N38 GPIO34 AN6
CLKOUT_PCIE_P1 AA42
GPIO35 / NMI# AP1
316 Datasheet
Ballout Definition
Table 6-2. Mobile PCH Table 6-2. Mobile PCH Table 6-2. Mobile PCH
Ballout by Signal Name Ballout by Signal Name Ballout by Signal Name
(Sheet 4 of 18) (Sheet 5 of 18) (Sheet 6 of 18)
EDS Net Name EDS Net Name EDS Net Name
Pin # Pin # Pin #
Rev 0.7 Rev 0.7 Rev 0.7
GPIO50 A12 PCIE_IREF BE30 PETn6 BC38
GPIO51 C10 PCIE_RCOMP BD29 PETn7 BE40
GPIO52 B13 PCIECLKRQ0# / PETn8 BD42
AB1
GPIO53 A10 GPIO73 PETp1 / USB3Tp3 BC32
GPIO54 C12 PCIECLKRQ1# / PETp2 / USB3Tp4 BB33
AF1
GPIO18
GPIO55 AL6 PETp3 BC34
PCIECLKRQ2# /
GPIO57 U12 AF3 PETp4 BC36
GPIO20 / SMI#
GPIO8 Y1 PCIECLKRQ3# / PETp5 BB37
HDA_BCLK B25 T3 PETp6 BE38
GPIO25
HDA_DOCK_RST# PCIECLKRQ4# / PETp7 BC40
C22 V3
/ GPIO13 GPIO26 PETp8 BD41
HDA_RST# C24 PCIECLKRQ5# / PIRQA# H20
AA2
HDA_SDI0 L22 GPIO44
PIRQB# L20
HDA_SDI1 K22 PCIECLKRQ6# /
AE4 PIRQC# K17
GPIO45
HDA_SDI2 G22 PIRQD# M20
PCIECLKRQ7# /
HDA_SDI3 F22 Y3 PIRQE# / GPIO2 G17
GPIO46
HDA_SDO A24 PIRQF# / GPIO3 F17
PECI AY1
HDA_SYNC A22 PIRQG# / GPIO4 L15
PEG_A_CLKRQ# /
ICLK_IREF AM45 AF6
GPIO47 PIRQH# / GPIO5 M15
INTRUDER# A8 PEG_B_CLKRQ# / PLTRST_PROC# AU4
U4
INTVRMEN G10 GPIO56
PLTRST# Y11
JTAG_TCK AB3 PERn1 / USB3Rn3 AW31 PME# AD10
JTAG_TDI AE2 PERn2 / USB3Rn4 AT31
PMSYNCH AY3
JTAG_TDO AD3 PERn3 AW33
PROCPWRGD AV3
JTAG_TMS AD1 PERn4 AT33 PWRBTN# K1
LAD0 A20 PERn5 AW36
PWROK F10
LAD1 C20 PERn6 AY38
RCIN# AT6
LAD2 A18 PERn7 AT40 REFCLK14IN F45
LAD3 C18 PERn8 AN38
RI# N4
LAN_PHY_PWR_CT PERp1 / USB3Rp3 AY31
K13 RSMRST# J2
RL / GPIO12 PERp2 / USB3Rp4 AR31 RTCRST# D9
LDRQ0# D21 PERp3 AY33
RTCX1 B5
LDRQ1# / GPIO23 G20 PERp4 AR33
RTCX2 B4
LFRAME# B21 PERp5 AV36 SATA_IREF BD4
OC0# / GPIO59 P3 PERp6 AW38
SATA_RCOMP AY5
OC1# / GPIO40 V1 PERp7 AT39
SATA_RXN0 BC8
OC2# / GPIO41 U2 PERP8 AN39 SATA_RXN1 BC10
OC3# / GPIO42 P1 PETn1 / USB3Tn3 BE32
SATA_RXN2 BB9
OC4# / GPIO43 M3 PETn2 / USB3Tn4 BD33
SATA_RXN3 BC12
OC5# / GPIO9 T1 PETn3 BE34 SATA_RXN4 /
OC6# / GPIO10 N2 PETn4 BE36 BD13
PERn1
OC7# / GPIO14 M1 PETn5 BD37
Datasheet 317
Ballout Definition
Table 6-2. Mobile PCH Table 6-2. Mobile PCH Table 6-2. Mobile PCH
Ballout by Signal Name Ballout by Signal Name Ballout by Signal Name
(Sheet 7 of 18) (Sheet 8 of 18) (Sheet 9 of 18)
EDS Net Name EDS Net Name EDS Net Name
Pin # Pin # Pin #
Rev 0.7 Rev 0.7 Rev 0.7
SATA_RXN5 / SLP_S5# / GPIO63 Y7 TACH7 / GPIO71 H15
BC14
PERn2 SLP_SUS# F1 TD_IREF AY43
SATA_RXP0 BE8 SLP_WLAN# / THRMTRIP# AV1
D2
SATA_RXP1 BE10 GPIO29 TP1 BA45
SATA_RXP2 BD9 SMBALERT# / TP10 AW44
N7
SATA_RXP3 BE12 GPIO11
TP11 BC30
SATA_RXP4 / SMBCLK R10
BB13 TP12 AW17
PERp1 SMBDATA U11
TP13 AU44
SATA_RXP5 / SML0ALERT# /
BE14 N8 TP14 AN10
PERp2 GPIO60
SATA_TXN0 AW8 SML0CLK U8 TP15 AV45
TP16 AV43
SATA_TXN1 AV10 SML0DATA R7
TP17 AU42
SATA_TXN2 AY13 SML1ALERT# /
SATA_TXN3 AR13 TEMP_ALERT#/ H6 TP18 AD38
GPIO74 TP19 AD39
SATA_TXN4 /
AV15 SML1CLK / GPIO58 K6 TP2 BC45
PETn1
SATA_TXN5 / SML1DATA / TP20 AB6
AP15 N11
PETn2 GPIO75
TP21 AB10
SATA_TXP0 AY8 SPI_CLK AJ11
TP22 C26
SATA_TXP1 AW10 SPI_CS0# AJ7
TP23 L33
SATA_TXP2 AW13 SPI_CS1# AL7
TP24 M33
SATA_TXP3 AT13 SPI_CS2# AJ10
TP25 F8
SATA_TXP4 / SPI_IO2 AJ4
AW15 TP3 BE44
PETp1 SPI_IO3 AJ2
TP4 BE43
SATA_TXP5 / SPI_MISO AH3
AR15 TP5 AY45
PETp2 SPI_MOSI AH1
TP6 BB29
SATA0GP / GPIO21 AT1 SPKR AL10
TP7 AV17
SATA1GP / GPIO19 AU2 SRTCRST# B9
TP8 BB2
SATA2GP / GPIO36 AT3 SUS_STAT# /
U7 TP9 BA2
SATA3GP / GPIO37 AK1 GPIO61
USB2n0 B37
SATA4GP / GPIO16 AN2 SUSACK# R6
USB2n1 A38
SATA5GP / GPIO49 AK3 SUSCLK / GPIO62 Y6
USB2n10 B29
SATALED# AP3 SUSWARN# /
SUSPWRNACK / J4 USB2n11 A28
SCLOCK / GPIO22 BB4
GPIO30 USB2n12 G26
SDATAOUT0 /
AM3 SYS_PWROK AD7 USB2n13 F24
GPIO39
SDATAOUT1 / SYS_RESET# AM1 USB2n2 A36
AN4
GPIO48 TACH0 / GPIO17 C14 USB2n3 A34
SERIRQ AL11 TACH1 / GPIO1 F13 USB2n4 B33
SLOAD / GPIO38 AT7 TACH2 / GPIO6 A14 USB2n5 F31
SLP_A# F3 TACH3 / GPIO7 G15 USB2n6 K31
SLP_LAN# G5 TACH4 / GPIO68 C16 USB2n7 G29
SLP_S3# H1 TACH5 / GPIO69 D13 USB2n8 A32
SLP_S4# C6 TACH6 / GPIO70 G13 USB2n9 A30
318 Datasheet
Ballout Definition
Table 6-2. Mobile PCH Table 6-2. Mobile PCH Table 6-2. Mobile PCH
Ballout by Signal Name Ballout by Signal Name Ballout by Signal Name
(Sheet 10 of 18) (Sheet 11 of 18) (Sheet 12 of 18)
EDS Net Name EDS Net Name EDS Net Name
Pin # Pin # Pin #
Rev 0.7 Rev 0.7 Rev 0.7
USB2p0 D37 VCC AD24 VCCCLK AD35
USB2p1 C38 VCC AD26 VCCCLK AD36
USB2p10 D29 VCC AD28 VCCCLK AE30
USB2p11 C28 VCC AE18 VCCCLK AE32
USB2p12 F26 VCC AE20 VCCCLK AG30
USB2p13 G24 VCC AE22 VCCCLK AG32
USB2p2 C36 VCC AE24 VCCCLK3_3 L26
USB2p3 C34 VCC AE26 VCCCLK3_3 L29
USB2p4 D33 VCC AG18 VCCCLK3_3 M26
USB2p5 G31 VCC AG20 VCCCLK3_3 M29
USB2p6 L31 VCC AG22 VCCCLK3_3 U32
USB2p7 H29 VCC AG24 VCCCLK3_3 V32
USB2p8 C32 VCC AP45 VCCDSW3_3 A16
USB2p9 C30 VCC3_3 L24 VCCIO U30
USB3Rn1 AR26 VCC3_3 R30 VCCIO U36
USB3Rn2 AW26 VCC3_3 R32 VCCIO V28
USB3Rn5 AW29 VCC3_3 AE14 VCCIO V30
USB3Rn6 AR29 VCC3_3 AF12 VCCIO Y30
USB3Rp1 AP26 VCC3_3 AG14 VCCIO AK18
USB3Rp2 AV26 VCC3_3 AK30 VCCIO AK20
USB3Rp5 AV29 VCC3_3 AK32 VCCIO AK22
USB3Rp6 AP29 VCCADAC1_5 P45 VCCIO AM18
USB3Tn1 BE24 VCCADACBG3_3 M31 VCCIO AM20
USB3Tn2 BD25 VCCASW L17 VCCIO AM22
USB3Tn5 BE26 VCCASW R18 VCCIO AN34
USB3Tn6 BD27 VCCASW U18 VCCIO AN35
USB3Tp1 BD23 VCCASW U20 VCCIO AP22
USB3Tp2 BC24 VCCASW U22 VCCIO AR22
USB3Tp5 BC26 VCCASW U24 VCCIO AT22
USB3Tp6 BE28 VCCASW V18 VCCRTC A6
USBRBIAS K26 VCCASW V20 VCCSPI AD12
USBRBIAS# K24 VCCASW V22 VCCSUS3_3 K8
V_PROC_IO AJ12 VCCASW V24 VCCSUS3_3 R20
V_PROC_IO AJ14 VCCASW Y18 VCCSUS3_3 R22
VCC P18 VCCASW Y20 VCCSUS3_3 R24
VCC P20 VCCASW Y22 VCCSUS3_3 R26
VCC Y26 VCCASW AA18 VCCSUS3_3 R28
VCC AA24 VCCCLK Y32 VCCSUS3_3 U26
VCC AA26 VCCCLK AA30 VCCSUS3_3 AJ30
VCC AD20 VCCCLK AA32 VCCSUS3_3 AJ32
VCC AD22 VCCCLK AD34 VCCSUSHDA A26
Datasheet 319
Ballout Definition
Table 6-2. Mobile PCH Table 6-2. Mobile PCH Table 6-2. Mobile PCH
Ballout by Signal Name Ballout by Signal Name Ballout by Signal Name
(Sheet 13 of 18) (Sheet 14 of 18) (Sheet 15 of 18)
EDS Net Name EDS Net Name EDS Net Name
Pin # Pin # Pin #
Rev 0.7 Rev 0.7 Rev 0.7
VCCUSBPLL U35 VSS F15 VSS R2
VCCVRM AF34 VSS F20 VSS R8
VCCVRM AK26 VSS F29 VSS R12
VCCVRM AK28 VSS F33 VSS R14
VCCVRM AN11 VSS F43 VSS R16
VCCVRM AW40 VSS G2 VSS R34
VCCVRM BB44 VSS G8 VSS R38
VCCVRM BE22 VSS G38 VSS R44
VGA_BLUE T45 VSS G44 VSS T43
VGA_DDC_CLK M43 VSS H7 VSS U6
VGA_DDC_DATA M45 VSS H10 VSS U10
VGA_GREEN U44 VSS H13 VSS U16
VGA_HSYNC N42 VSS H17 VSS U28
VGA_IRTN U39 VSS H22 VSS U34
VGA_RED V45 VSS H24 VSS U38
VGA_VSYNC N44 VSS H26 VSS U42
VSS A2 VSS H31 VSS V14
VSS A4 VSS H36 VSS V16
VSS A5 VSS H40 VSS V26
VSS A41 VSS K10 VSS V43
VSS A43 VSS K15 VSS W2
VSS A44 VSS K20 VSS W44
VSS B1 VSS K29 VSS Y8
VSS B2 VSS K33 VSS Y14
VSS B7 VSS K39 VSS Y16
VSS B11 VSS L2 VSS Y24
VSS B15 VSS L44 VSS Y28
VSS B19 VSS M17 VSS Y34
VSS B23 VSS M22 VSS Y36
VSS B27 VSS M24 VSS Y40
VSS B31 VSS N6 VSS AA4
VSS B35 VSS N10 VSS AA16
VSS B39 VSS N12 VSS AA20
VSS B44 VSS N35 VSS AA22
VSS B45 VSS N39 VSS AA28
VSS C45 VSS P22 VSS AB8
VSS D1 VSS P24 VSS AB12
VSS D4 VSS P26 VSS AB34
VSS D25 VSS P28 VSS AB38
VSS D42 VSS P30 VSS AC2
VSS E1 VSS P32 VSS AC44
VSS E45 VSS P43 VSS AD6
320 Datasheet
Ballout Definition
Table 6-2. Mobile PCH Table 6-2. Mobile PCH Table 6-2. Mobile PCH
Ballout by Signal Name Ballout by Signal Name Ballout by Signal Name
(Sheet 16 of 18) (Sheet 17 of 18) (Sheet 18 of 18)
EDS Net Name EDS Net Name EDS Net Name
Pin # Pin # Pin #
Rev 0.7 Rev 0.7 Rev 0.7
VSS AD8 VSS AM32 VSS BC22
VSS AD14 VSS AN8 VSS BC28
VSS AD16 VSS AN36 VSS BD1
VSS AD18 VSS AN40 VSS BD2
VSS AD30 VSS AN42 VSS BD7
VSS AD32 VSS AP13 VSS BD11
VSS AD40 VSS AP24 VSS BD15
VSS AE16 VSS AP31 VSS BD19
VSS AE28 VSS AP43 VSS BD31
VSS AF8 VSS AR2 VSS BD35
VSS AF38 VSS AT10 VSS BD39
VSS AG2 VSS AT15 VSS BD44
VSS AG16 VSS AT17 VSS BD45
VSS AG26 VSS AT20 VSS BE2
VSS AG28 VSS AT26 VSS BE3
VSS AG44 VSS AT29 VSS BE5
VSS AJ6 VSS AT36 VSS BE41
VSS AJ8 VSS AT38 WAKE# K3
VSS AJ16 VSS AT43 XTAL25_IN AM43
VSS AJ18 VSS AV6 XTAL25_OUT AL44
VSS AJ20 VSS AV7
VSS AJ22 VSS AV13
VSS AJ24 VSS AV22
§§
VSS AJ34 VSS AV24
VSS AJ38 VSS AV31
VSS AK14 VSS AV33
VSS AK16 VSS AV40
VSS AK24 VSS AW2
VSS AK43 VSS AY7
VSS AK45 VSS AY10
VSS AL2 VSS AY15
VSS AL8 VSS AY20
VSS AL12 VSS AY26
VSS AL34 VSS AY29
VSS AL38 VSS AY36
VSS AM14 VSS BA1
VSS AM16 VSS BA40
VSS AM24 VSS BB25
VSS AM26 VSS BB42
VSS AM28 VSS BC1
VSS AM30 VSS BC16
Datasheet 321
Ballout Definition
322 Datasheet
Package Information
7 Package Information
7.1 Desktop / Server PCH package
• FCBGA package
• Package size: 23 mm x 22 mm
• Z Height: 1.602 mm
• Ball Count: 708
• Ball pitch: 0.65 mm
The Desktop/Server PCH package information is shown in Figure 7-2.
Note: All dimensions, unless otherwise specified, are in millimeters.
7.1.1 Tape and Reel Pin 1 Placement
Figure 7-1. Tape and Reel Pin 1 Location
Datasheet 323
Package Information
Figure 7-2. Desktop / Server PCH Package Drawing
324 Datasheet
Package Information
7.2 Mobile PCH Package
• FCBGA package
• Package size: 20 mm x 20 mm
• Z Height: 1.573 mm
• Ball Count: 695
• Ball pitch: 0.593 mm
The Mobile PCH package information is shown in Figure 7-4.
Note: All dimensions, unless otherwise specified, are in millimeters.
7.2.1 Tape and Reel Pin 1 Placement
Figure 7-3. Tape and Reel Pin 1 Location
Datasheet 325
Package Information
Figure 7-4. Mobile PCH Package Drawing
§§
326 Datasheet
Electrical Characteristics
8 Electrical Characteristics
This chapter contains the DC and AC characteristics for the PCH. AC timing diagrams
are included.
8.1 Thermal Specifications
8.1.1 Storage Specifications and Thermal Design Power (TDP)
Additional desktop thermal information can be obtained in CDI#487848, “Intel® 8
Series / C220 Series Chipset Family Platform Controller Hub (PCH) Thermal Mechanical
Specifications and Design Guide”.
Table 8-1. Storage Conditions and Thermal Junction Operating Temperature Limits
Parameter Description Min Max Notes
The non-operating device storage
temperature. Damage (latent or
TABSOLUTE STORAGE -25 °C 125 °C 1,2,3
otherwise) may occur when exceeded for
any length of time.
The ambient storage temperature (in
TSUSTAINED STORAGE shipping media) for a sustained period of -5 °C 40 °C 4,5
time.
The maximum device storage relative
RHSUSTAINED STORAGE 60% @ 24 ° C 5,6
humidity for a sustained period of time.
A prolonged or extended period of time;
0 6
TIME SUSTAINED STORAGE typically associated with customer shelf 6
Months Months
life.
Thermal Junction Operating Temperature
Tj 0 °C 108 °C 7
limits.
Thermal Junction Catastrophic
Tcatastrophic 110 °C 128 °C 8
Temperature limits.
NOTES:
1. Refers to a component device that is not assembled in a board or socket and is not
electrically connected to a voltage reference or I/O signal.
2. Specified temperatures are not to exceed values based on data collected. Exceptions for
surface mount reflow are specified by the applicable JEDEC standard. Non-adherence may
affect PCH reliability.
3. TABSOLUTE STORAGE applies to the unassembled component only and does not apply to the
shipping media, moisture barrier bags, or desiccant.
4. Intel branded products are specified and certified to meet the following temperature and
humidity limits that are given as an example only (Non-Operating Temperature Limit:
-40 °C to 70 °C and Humidity: 50% to 90%, non-condensing with a maximum wet bulb of
28 °C.) Post board attach storage temperature limits are not specified for non-Intel
branded boards.
5. The JEDEC J-JSTD-020 moisture level rating and associated handling practices apply to all
moisture sensitive devices removed from the moisture barrier bag.
6. Nominal temperature and humidity conditions and durations are given and tested within
the constraints imposed by TSUSTAINED storage and customer shelf life in applicable Intel
boxes and bags.
Datasheet 327
Electrical Characteristics
7. The thermal solution needs to ensure that the temperature does not exceed the maximum
junction temperature (Tj,max) limit.
8. Default Catastrophic Trip Point for PCH is 120°C.
Table 8-2. Mobile Thermal Design Power
SKU Thermal Design Power (TDP) Notes
Standard 3 Watts
8.2 Absolute Maximum Ratings
Table 8-3. PCH Absolute Maximum Ratings
Parameter Maximum Limits
Voltage on any 3.3 V Pin with respect to Ground -0.5 to Vcc3_3 + 0.4 V
Voltage on any 1.5 V Pin with respect to Ground -0.5 to VccVRM + 0.5 V
Voltage on any 1.05 V Tolerant Pin with respect to Ground -0.5 to VccCore + 0.5 V
1.05 V Supply Voltage with respect to VSS -0.5 to 1.3 V
3.3 V Supply Voltage with respect to VSS -0.5 to 3.7 V
V_PROC_IO Supply Voltage with respect to VSS -0.5 to 1.3 V
1.5 V Supply Voltage for the analog PLL with respect to VSS -0.5 to 1.65 V
Table 8-3 specifies absolute maximum and minimum ratings. At conditions outside
functional operation condition limits, but within absolute maximum and minimum
ratings, neither functionality nor long-term reliability can be expected. If a device is
returned to conditions within functional operation limits after having been subjected to
conditions outside these limits (but within the absolute maximum and minimum
ratings) the device may be functional, but with its lifetime degraded depending on
exposure to conditions exceeding the functional operation condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time, it will either not function or its reliability will be
severely degraded when returned to conditions within the functional operating
condition limits.
Although the PCH contains protective circuitry to resist damage from Electrostatic
Discharge (ESD), precautions should always be taken to avoid high static voltages or
electric fields.
8.3 PCH Power Supply Range
Table 8-4. PCH Power Supply Range
Power Supply Minimum Nominal Maximum
1.05 V 0.998 V 1.05 V 1.10 V
1.5 V 1.43 V 1.50 V 1.58 V
1.8 V 1.71 V 1.80 V 1.89 V
3.3 V 3.14 V 3.30 V 3.47 V
NOTE: VccRTC can drop to 2.0Vmin in G3 state. Refer to Table 8-8 for more details.
328 Datasheet
Electrical Characteristics
8.4 General DC Characteristics
Table 8-5. Measured Silicon ICC Estimates (Desktop and Mobile) (Sheet 1 of 2)
S0 Iccmax S0 Iccmax S0 Idle S0 Idle
Sx
Current Current Current Current Sx Idle
Voltage Iccmax
Voltage Rail Integrated External External Integrated Current3, G3
(V) Current3,
Graphics3 Graphics3 Graphics3 Graphics3 4
4
(A)
(A)
(A) (A) (A) (A)
VCC (Internal
Suspend VR
1.05 1.312 1.312 0.130 0.130 0 0 0
mode using
INTVRMEN)7
VCC (External
Suspend VR
1.05 1.138 1.138 0.114 0.114 0 0 0
mode using
INTVRMEN)7
VCCIO 1.05 3.629 3.491 0.199 0.264 0 0 0
VCCADAC1_5 1.5 0.070 0.004 0.002 0.070 0 0 0
VCCADAC3_3 3.3 0.0133 <1 mA <1 mA 0.007 0 0 0
VCCCLK 1.05 0.306 0.306 0.089 0.089 0 0 0
VCCCLK3_3 3.3 0.055 0.055 0.011 0.011 0 0 0
VCCVRM 1.5 0.183 0.158 0.043 0.068 0 0 0
VCC3_3 3.3 0.133 0.133 0.003 0.003 0 0 0
VCCASW 1.05 0.670 0.670 0.034 0.034 0.211 0.034 0
VCCSUSHDA 3.3/1.5 0.010 0.010 <1 mA <1 mA 0.003 <1 mA 0
VCCSPI5 3.3 0.022 0.022 <1 mA <1 mA 0 0 0
VCCSUS3_3
(Internal
Suspend VR 3.3 0.261 0.261 0.006 0.006 0.054 0.020 0
mode using
INTVRMEN)7
VCCSUS3_3
(External
Suspend VR 3.3 0.261 0.261 0.006 0.006 0.054 0.004 0
mode using
INTVRMEN)7
VCCDSW3_36, 9 3.3 0.015 0.015 1.5 mA 1.5 mA 1.5 mA 1.5 mA 0
6 uA
VCCRTC 3.3 N/A N/A N/A N/A N/A N/A See
notes
1, 2
V_PROC_IO 1.05 0.004 0.004 0.002 0.002 0 0 0
Datasheet 329
Electrical Characteristics
Table 8-5. Measured Silicon ICC Estimates (Desktop and Mobile) (Sheet 2 of 2)
S0 Iccmax S0 Iccmax S0 Idle S0 Idle
Sx
Current Current Current Current Sx Idle
Voltage Iccmax
Voltage Rail Integrated External External Integrated Current3, G3
(V) Current3,
Graphics3 Graphics3 Graphics3 Graphics3 4
4
(A)
(A)
(A) (A) (A) (A)
DcpSus1
(External
Suspend VR 1.05 0.098 0.098 0.012 0.012 0.012 0.012 0
mode using
INTVRMEN)7,8
DcpSus2
(External
Suspend VR 1.05 0.028 0.028 0.002 0.002 0.002 0.002 0
mode using
INTVRMEN)7,8
DcpSus3
(External
Suspend VR 1.05 0.476 0.476 0.003 0.003 0.005 0.005 0
mode using
INTVRMEN)7,8
NOTES:
1. G3 state shown to provide an estimate of battery life.
2. Icc (RTC) data is taken with VccRTC at 3.0 V while the system in a mechanical off (G3) state at room
temperature.
3. S0 Iccmax Measurements taken at 110 °C and S0 Idle/Sx Iccmax/Sx Idle measurements taken at 50 °C.
4. Sx/Moff Iccmax and Icc Idle values can be derived by removing VCCASW current in Sx.
5. If VCCSPI follows ASW well, the Iccmax and Icc Idle values will also be 0 in Sx/Moff.
6. DeepSx Icc values can be derived by removing all Sx Iccmax and Icc Idle values except for VCCDSW3_3.
7. External Suspend VR mode supported on Mobile Only.
8. This applies to External Suspend VR powered mode. In Internal Suspend VR mode DcpSus1, DcpSus2 and
DcpSus3 is a No Connect and hence Iccmax and Icc Idle information is not applicable.
9. The VccDSW3_3 voltage regulator and associated power delivery circuitry should be capable of handling
temporary inrush currents up to 1.9 A until the internally generated 1.05 V DSW rail (DcpSusByp) ramps.
— VccDSW3_3 ramp only occurs when coming from the G3 mechanical off state (DC power
removed and dead/missing battery) to the Sx state.
— The limit of 1.9 A applies to VccDSW3_3 ramp rates of 100 µs and slower.
330 Datasheet
Electrical Characteristics
Table 8-6. Single-Ended Signal DC Characteristics as Inputs or Outputs (Sheet 1 of 6)
Type Symbol Parameter Min Max Unit Condition Notes
Associated Signals: CLKIN_33MHZLOOPBACK, GPIO15, GPIO27, GPIO28, GPIO32, GPIO72,
DOCKEN#/GPIO33, LDRQ1#/GPIO23, LDRQ0#, LAD[3:0], LFRAME#, SERIRQ, GPIO8,
PEG_A_CLKRQ#/GPIO47, PEG_B_CLKRQ#/GPIO56, PCIECLKRQ5#/GPIO44, PCIECLKRQ6#/GPIO45,
PCIECLKRQ7#/GPIO46, LAN_PHY_PWR_CTRL/GPIO12, SATA0GP/GPIO21, SATA1GP/GPIO19,
SATA2GP/GPIO36, SATA3GP/GPIO37, SATA4GP/GPIO16, SATA5GP/GPIO49, GPIO35/NMI#, 2
PCIECLKRQ0#/GPIO73, PCIECLKRQ1#/GPIO18, PCIECLKRQ2#/GPIO20/SMI#, PCIECLKRQ3#/
GPIO25, PCIECLKRQ4#/GPIO26, BMBUSY#/GPIO0, OC0#/GPIO59, OC1#/GPIO40, OC2#/GPIO41,
OC3#/GPIO42, OC4#/GPIO43, OC5#/GPIO9, OC6#/GPIO10, OC7#/GPIO14, PLTRST#, SPKR, PME#,
SPI_CLK, SPI_CS0#, SPI_CS1#, SPI_CS2#, SPI_MISO, SPI_MOSI, SPI_IO2, SPI_IO3
VCC Supply Voltage Reference 3.14 3.47 V
VIH Input High Voltage 0.5 x VCC VCC + 0.5 V
VIL Input Low Voltage -0.5 0.3 x VCC V
Input
IIL Input Leakage Current -10 10 uA 3
CIN Pin Input Capacitance — 10 pF 4
VOH Output High Voltage 0.9 x VCC — V Iout=-0.5mA 1
Output
VOL Output Low Voltage — 0.1 x VCC V Iout=1.5mA
Associated Signals: VGA_HSYNC, VGA_VSYNC 2
VCC Supply Voltage Reference 3.14 3.47 V
VIH Input High Voltage 2 VCC + 0.5 V
Input VIL Input Low Voltage -0.5 0.8 V
CIN Pin Input Capacitance — 10 pF
IOH/L Driver Output Current — 8 mA
Output VOH Output High Voltage 2.4 VCC V 1
VOL Output Low Voltage — 0.5 V
Associated Signals: SATALED#, SYS_RESET#, DRAMPWROK, GPIO24, GPIO34, GPIO57, GPIO51,
GPIO54, GPIO52, GPIO53, GPIO50, CL_RST#, RI#, SUS_STAT#/GPIO61, SUSACK#, SUSCLK/
GPIO62, SUSWARN#/SUSPWRNACK/GPIO30, WAKE#, ACPRESENT/GPIO31, SLP_A#, SLP_LAN#,
SLP_S3#, SLP_S4#, SLP_S5#/GPIO63, SLP_SUS#, SLP_WLAN#/GPIO29, PWRBTN#, TACH1/GPIO1, 2
TACH0/GPIO17, TACH2/GPIO6, TACH3/GPIO7, TACH4/GPIO68, TACH5/GPIO69, TACH6/GPIO70,
TACH7/GPIO71, PIRQE#/GPIO2, PIRQF#/GPIO3, PIRQG#/GPIO4, PIRQH#/GPIO5, PIRQA#, PIRQB#,
PIRQC#, PIRQD#
VCC Supply Voltage Reference 3.14 3.47 V
Schmitt Trigger
VHYS 250 — mVpp
Hysteresis
VIH Input High Voltage 2 VCC + 0.5 V
Input
VIL Input Low Voltage -0.5 0.8 V
IIL Input Leakage Current -10 10 uA
CIN Pin Input Capacitance — 10 pF
VOH Output High Voltage VCC – 0.5 VCC V 1
Output
VOL Output Low Voltage — 0.4 V
Datasheet 331
Electrical Characteristics
Table 8-6. Single-Ended Signal DC Characteristics as Inputs or Outputs (Sheet 2 of 6)
Type Symbol Parameter Min Max Unit Condition Notes
Associated Signals: SCLOCK/GPIO22, SDATAOUT0/GPIO39, SDATAOUT1/GPIO48, SLOAD/GPIO38,
GPIO55, SMBALERT#/GPIO11, SMBCLK, SMBDATA, SML0ALERT#/GPIO60, SML0CLK, SML0DATA,
2
SML1ALERT#/TEMP_ALERT#/GPIO74, SML1CLK/GPIO58, SML1DATA/GPIO75, RCIN#, SYS_PWROK,
APWROK, PWM0, PWM1, PWM2, PWM3
VCC Supply Voltage Reference 3.14 3.47 V
Schmitt Trigger
VHYS 250 — mVpp
Hysteresis
VIH Input High Voltage 2 VCC + 0.5 V
Input
VIL Input Low Voltage -0.5 0.8 V
IIL Input Leakage Current -10 10 uA
CIN Pin Input Capacitance — 10 pF
IOL Driver Output Current 3 20 mA
Output VOH Output High Voltage 2.4 VCC V 1
VOL Output Low Voltage — 0.4 V
Associated Signals: eDP_VDDEN, eDP_BKLTEN, eDP_BKLTCTL, DDPD_CTRLDATA, DDPD_CTRLCLK,
2
VGA_DDC_DATA, VGA_DDC_CLK, DDPC_CTRLDATA, DDPC_CTRLCLK
VCC Supply Voltage Reference 3.14 3.47 V
Schmitt Trigger
VHYS 0.05 x VCC — mVpp
Hysteresis
VIH Input High Voltage 0.7 x VCC VCC + 0.5 V
Input
VIL Input Low Voltage -0.5 0.3 x VCC V
IIL Input Leakage Current -10 10 uA
CIN Pin Input Capacitance — 10 pF
VOH Output High Voltage VCC – 0.5 VCC V 1
Output VOL Output Low Voltage 0.0 0.4 V
VOL Output Low Voltage 0.0 0.6 V 5
Associated Signals: RCIN#, SYS_PWROK, APWROK 2
VCC Supply Voltage Reference 3.14 3.47 V
Schmitt Trigger
VHYS 250 — mVpp
Hysteresis
Input VIH Input High Voltage 2.1 3.3 V
VIL Input Low Voltage — 0.8 V
IIL Input Leakage Current -10 10 uA
CIN Pin Input Capacitance — 50 pF
VOH Output High Voltage VCC – 0.5 VCC V 1
Output
VOL Output Low Voltage — 0.4 V
332 Datasheet
Electrical Characteristics
Table 8-6. Single-Ended Signal DC Characteristics as Inputs or Outputs (Sheet 3 of 6)
Type Symbol Parameter Min Max Unit Condition Notes
Associated Signals: JTAG_TCK, JTAG_TDI, JTAG_TDO, JTAG_TMS, FDI_CSYNC, FDI_INT 2
VCC Supply Voltage Reference 0.94 1.13 V
Schmitt Trigger
VHYS 250 — mVpp
Hysteresis
Input VIH Input High Voltage 0.75 VCC + 0.5 V
VIL Input Low Voltage -0.5 0.3 V
IIL Input Leakage Current -10 10 uA
CIN Pin Input Capacitance — 10 pF
VOH Output High Voltage 0.75 — V 1
Output
VOL Output Low Voltage — 0.3 V
Associated Signals: SST 2
VCC Supply Voltage Reference 1.43 1.58 V
Schmitt Trigger
VHYS 100 — mVpp
Hysteresis
Input VIH Input High Voltage 1.1 — V
VIL Input Low Voltage — 0.4 V
IIL Input Leakage Current -10 10 uA
CIN Pin Input Capacitance — 10 pF
VOH Output High Voltage 1.1 — V 1
Output
VOL Output Low Voltage — 0.4 V
Associated Signals: PECI 2
VCC Supply Voltage Reference 0.9 1.15 V
Schmitt Trigger
VHYS 0.1 x VCC — mVpp
Hysteresis
Negative edge threshold
Input Vn 0.275 x VCC 0.500 x VCC V
voltage
Positive edge threshold
Vp 0.550 x VCC 0.725 x VCC V
voltage
VIN Input Voltage Range -0.15 VCC + 0.15 V
Output High Source
ISOURCE -6 — mA 1
Current
Output
Output Low Source
ISINK 0.5 1.0 mA
Current
Datasheet 333
Electrical Characteristics
Table 8-6. Single-Ended Signal DC Characteristics as Inputs or Outputs (Sheet 4 of 6)
Type Symbol Parameter Min Max Unit Condition Notes
Associated Signals: PROCPWRGD, PLTRST_PROC#, PMSYNCH, THRMTRIP# 2
VCC Supply Voltage Reference 0.9 1.15 V
Schmitt Trigger
VHYS 0.1 x VCC — mVpp
Hysteresis
Input VIH Input High Voltage 0.81 x VCC — V
VIL Input Low Voltage — 0.51 x VCC V
IIL Input Leakage Current -10 10 uA
CIN Pin Input Capacitance — 10 pF
VOH Output High Voltage VCC - 0.3 — V 1
Output
VOL Output Low Voltage — 0.255 V
Associated Signals: CL_DATA, CL_CLK 2
0.12 x 0.12 x
CL_VRef Supply Voltage Reference V
VCCSUS3_3 VCCSUS3_3
Schmitt Trigger
VHYS 100 — mVpp
Hysteresis
CL_VRef +
Input VIH Input High Voltage — V
0.075
CL_VRef-
VIL Input Low Voltage — V
0.075
IIL Input Leakage Current -10 10 uA
CIN Pin Input Capacitance — 10 pF
VOH Output High Voltage 610 — mV 1
Output
VOL Output Low Voltage — 150 mV
334 Datasheet
Electrical Characteristics
Table 8-6. Single-Ended Signal DC Characteristics as Inputs or Outputs (Sheet 5 of 6)
Type Symbol Parameter Min Max Unit Condition Notes
Associated Signals: HDA_RST#, HDA_SDI0, HDA_SDI1, HDA_SDI2, HDA_SDI3, HDA_SDO,
2
HDA_SYNC, HDA_DOCK_RST#/GPIO13, HDA_BCLK
3.3 V Operation
VCC Supply Voltage Reference 3.0 3.6 V
LPIN Input Pin Inductance — 20 nH
VIH Input High Voltage 0.65 x VCC VCC + 0.5 V
Input
VIL Input Low Voltage -0.5 0.35 x Vcc V
IIL Input Leakage Current -10 10 uA
CIN Pin Input Capacitance — 7.5 pF
VOH Output High Voltage 0.9 x VCC — V 1
Output
VOL Output Low Voltage — 0.1 x VCC V
1.5 V Operation
VCC Supply Voltage Reference 1.35 1.65 V
LPIN Input Pin Inductance — 20 nH
VIH Input High Voltage 0.60 x VCC VCC + 0.5 V
Input
VIL Input Low Voltage -0.5 0.4 x Vcc V
IIL Input Leakage Current -10 10 uA
CIN Pin Input Capacitance — 7.5 pF
VOH Output High Voltage 0.9 x VCC — V 1
Output
VOL Output Low Voltage — 0.1 x VCC V
Associated Signals: RSMRST#, INTVRMEN, SRTCRST#, INTRUDER#, PWROK, DPWROK,
DSWVRMEN
VIL_RTC1 Input Low Voltage -0.5 0.78 V
VCCRTC+0.
VIH_RTC1 Input High Voltage 2.0 V 6
5
Associated Signals: RTCRST#
VIL_RTC2 Input Low Voltage -0.5 0.78 V
VCCRTC+0.
VIH_RTC2 Input High Voltage 2.0 V 6
5
Associated Signals: RTCX1
VIL_RTC3 Input Low Voltage -0.5 0.1 V
VIH_RTC3 Input High Voltage 0.8 1.2 V
Associated Signals: XTAL25_IN, XTAL25_OUT
Maximum Input Low
VIL -0.25 0.15 V
Voltage
Minimum Input High
VIH 0.7 1.2 V
Voltage
Datasheet 335
Electrical Characteristics
Table 8-6. Single-Ended Signal DC Characteristics as Inputs or Outputs (Sheet 6 of 6)
Type Symbol Parameter Min Max Unit Condition Notes
Associated Signals: FDI_CSYNC, FDI_INT 2
VCC Supply Voltage Reference 0.998 1.10 V
Input IIL Input Leakage Current — 100 uA
Sideband Output High
VOH 0.8 x VCC 1.2 V 1
Voltage
Sideband Output Low
Output VOL -0.1 0.2 x VCC V
Voltage
IOH Output Source Current 1.5 4.1 mA
IOL Output Sink Current 1.5 4.1 mA
NOTES:
1. The VOH specification does not apply to open-collector or open-drain drivers. Signals of this type must have
an external pull-up resistor, and that’s what determines the high-output voltage level. Refer to Chapter 2
for details on signal types.
2. Input characteristics apply when a signal is configured as Input or to signals that are only Inputs. Output
characteristics apply when a signal is configured as an Output or to signals that are only Outputs. Refer to
Chapter 2 for details on signal types.
3. PME# Input Current Leakage is 1uA max
4. CLKIN_33MHZLOOPBACK has a pin capacitance in the range of 1 pF to 12 pF.
5. Only applies to FAST MODE (400 kbits/s).
6. VCCRTC is the voltage applied to the VCCRTC well of the PCH. When the system is in a G3 state, this is
generally supplied by the coin cell battery, but for S5 and greater, this is generally VCCSUS3_3
336 Datasheet
Electrical Characteristics
Table 8-7. Differential Signal DC Characteristics (Sheet 1 of 4)
Symbol Parameter Min Max Unit Notes
Associated Signals: PETp[10:1], PETn[10:1], PERp[10:1], PERn[10:1]
Generation 1
Differential Peak to Peak
VTX-DIFF P-P 0.8 1.2 V 1
Output Voltage
Low power differential
VTX-DIFF P-P - Low Peak to Peak Output 0.4 1.2 V
Voltage
TX AC Common Mode
VTX_CM-ACp — 20 mV
Output Voltage (2.5GT/s)
DC Differential TX
ZTX-DIFF-DC 80 120
Impedance
Differential Input Peak to
VRX-DIFF p-p 0.175 1.2 V 1
Peak Voltage
AC peak Common Mode
VRX_CM-ACp — 150 mV
Input Voltage
Generation 2
Differential Peak to Peak
VTX-DIFF P-P 0.8 1.2 V 1
Output Voltage
Low power differential
VTX-DIFF P-P - Low Peak to Peak Output 0.8 1.2 V
Voltage
TX AC Common Mode
VTX_CM-Acp-p — 100 mV
Output Voltage (5GT/s)
DC Differential TX
ZTX-DIFF-DC — 120
Impedance
Differential Input Peak to
VRX-DIFF p-p 0.1 1.2 V 1
Peak Voltage
AC peak Common Mode
VRX_CM-ACp — 150 mV
Input Voltage
Associated Signals: USB3R[N/P][6:1], USB3T[N/P][6:1]
Differential Peak to Peak
VTX-DIFF-PP 0.8 1.2 V
Output Voltage
Low power differential
VTX-DIFF P-P - Low Peak to Peak Output 0.4 1.2 V 8
Voltage
Datasheet 337
Electrical Characteristics
Table 8-7. Differential Signal DC Characteristics (Sheet 2 of 4)
Symbol Parameter Min Max Unit Notes
Associated Signals: DMI_TX[P/N]_[3:0], DMI_RX[P/N]_[3:0]
Generation 1
Differential Peak to Peak
VTX-DIFF P-P 0.4 0.6 V
Output Voltage
Low power differential
VTX-DIFF P-P - Low Peak to Peak Output 0.4 0.6 V
Voltage
TX AC Common Mode
VTX_CM-ACp — 20 mV
Output Voltage (2.5GT/s)
DC Differential TX
ZTX-DIFF-DC 80 120
Impedance
Differential Input Peak to
VRX-DIFF p-p 0.175 1.2 V
Peak Voltage
AC peak Common Mode
VRX_CM-ACp — 150 mV
Input Voltage
Generation 2
Differential Peak to Peak
VTX-DIFF P-P 0.4 0.6 V
Output Voltage
Low power differential
VTX-DIFF P-P - Low Peak to Peak Output 0.4 0.6 V
Voltage
TX AC Common Mode
VTX_CM-Acp-p — 100 mV
Output Voltage (5GT/s)
DC Differential TX
ZTX-DIFF-DC — 120
Impedance
Differential Input Peak to
VRX-DIFF p-p 0.1 1.2 V
Peak Voltage
AC peak Common Mode
VRX_CM-ACp — 150 mV
Input Voltage
Associated Signals: FDI_RXP[1:0]
UI Unit Interval 370.37 ps
Minimum Rx eye width at
TRX-EYE 0.5 — UI
the Rx package pins
Differential Peak to Peak
VTX-DIFF P-P 175 1000 mV
Input Voltage
AC peak input common
VRX-CM-ACp — 150 mV
mode voltage
DC Differential Input
ZRX-DIFF-DC 80 120
Impedance
338 Datasheet
Electrical Characteristics
Table 8-7. Differential Signal DC Characteristics (Sheet 3 of 4)
Symbol Parameter Min Max Unit Notes
Associated Signals: SATA_RXN[5:0], SATA_RXP[5:0], SATA_TXN[5:0], SATA_TXP[5:0]
Minimum Input Voltage - mVdiff
VIMIN10- Gen1i 325 — 2
1.5 Gb/s internal SATA p-p
Maximum Input Voltage - mVdiff
VIMAX10-Gen1i — 600 2
1.5 Gb/s internal SATA p-p
Minimum Input Voltage - mVdiff
VIMIN10-Gen1m 240 — 2
1.5 Gb/s eSATA p-p
Maximum Input Voltage - mVdiff
VIMAX10-Gen1m — 600 2
1.5 Gb/s eSATA p-p
Minimum Input Voltage - mVdiff
VIMIN10-Gen2i 275 — 2
3.0 Gb/s internal SATA p-p
Maximum Input Voltage - mVdiff
VIMAX10-Gen2i — 750 2
3.0 Gb/s internal SATA p-p
Minimum Input Voltage - 3.0 mVdiff
VIMIN10-Gen2m 240 — 2
Gb/s eSATA p-p
Maximum Input Voltage - 3.0 mVdiff
VIMAX10-Gen2m — 750 2
Gb/s eSATA p-p
Minimum Input Voltage - mVdiff
VIMIN10-Gen3i 240 — 2
6.0 Gb/s internal SATA p-p
Maximum Input Voltage - mVdiff
VIMAX10-Gen3i — 1000 2
6.0 Gb/s internal SATA p-p
Minimum Output Voltage mVdiff
VOMIN7-Gen1i,m 400 — 3
1.5 Gb/s eSATA p-p
Maximum Output Voltage mVdiff
VOMAX7-Gen1i,m — 600 3
1.5 Gb/s eSATA p-p
Minimum Output Voltage mVdiff
VOMIN7-Gen2i,m 400 — 3
3.0 Gb/s internal SATA p-p
Maximum Output Voltage mVdiff
VOMAX7-Gen2i,m — 700 3
3.0 Gb/s internal SATA p-p
Minimum Output Voltage mVdiff
VOMIN7-Gen3i 200 — 3
6.0 Gb/s internal SATA p-p
Maximum Output Voltage mVdiff
VOMAX7-Gen3i — 900 3
6.0 Gb/s internal SATA p-p
Datasheet 339
Electrical Characteristics
Table 8-7. Differential Signal DC Characteristics (Sheet 4 of 4)
Symbol Parameter Min Max Unit Notes
Associated Signals: USB2n[13:0], USB2p[13:0]
Differential Input
VDI 0.2 — V 4, 6
Sensitivity - classic mode
Differential Common
VCM Mode Range - classic 0.8 2.5 V 5, 6
mode
Single-Ended Receiver
VSE 0.8 2 V 6
Threshold - classic mode
Output Signal Crossover
VCRS 1.3 2 V 6
Voltage - classic mode
HS Squelch Detection
VHSSQ 100 150 mV 7
Threshold - HS mode
HS Disconnect Detection
VHSDSC 525 625 mV 7
Threshold - HS mode
HS Data Signaling Common
VHSCM Mode Voltage Range - HS -50 500 mV 7
mode
VHSOI HS Idle Level -HS mode -10 10 mV 7
HS Data Signaling High -
VHSOH 360 440 mV 7
HS mode
HS Data Signaling Low -
VHSOL -10 10 mV 7
HS mode
VCHIRPJ Chirp J Level -HS mode 700 1100 mV 7
VCHIRPK Chirp K Level -HS mode -900 -500 mV 7
VOL Output Low Voltage — 0.4 V 6
VOH Output High Voltage 3.3 V – 0.5 — V 6
NOTES:
1. PCI Express mVdiff p-p = 2*|PETp[x] – PETn[x]|; PCI Express mVdiff p-p = 2*|PERp[x] – PERn[x]|
2. SATA Vdiff, RX (VIMAX/VIMIN) is measured at the SATA connector on the receiver side (generally, the
motherboard connector), where SATA mVdiff p-p = 2*|SATA[x]RXP – SATA[x]RXN|.
3. SATA Vdiff, tx (VOMIN/VOMAX) is measured at the SATA connector on the transmit side (generally, the
motherboard connector), where SATA mVdiff p-p = 2*|SATA[x]TXP – SATA[x]TXN|
4. VDI = | USBPx[P] – USBPx[N] |
5. Includes VDI range
6. Applies to Low-Speed/Full-Speed USB
7. Applies to High-Speed USB 2.0.
8. USB 3.0 mVdiff p-p = 2*|USB3Rp[x] – USB3Rn[x]|; USB 3.0 mVdiff p-p = 2*|USB3Tp[x] – USB3Tn[x]|
9. Max PCIe* DC voltage is 3.6 V, as specified in PCIe spec, and maximum spike should not exceed 5.4 V as
specified in JEDEC specification JESD78.
340 Datasheet
Electrical Characteristics
Table 8-8. Other DC Characteristics
Symbol Parameter Min Nom Max Unit Notes
V_PROC_IO Processor I/F .998 1.05 1.10 V 1
Vcc3_3 I/O Buffer Voltage 3.14 3.3 3.47 V 1
VccVRM Internal PLL and VRMs 1.455 1.5 1.545 V 1, 3
VccSus3_3 Suspend Well I/O Buffer Voltage 3.14 3.3 3.47 V 1
VccIO Core Well I/O buffers .998 1.05 1.10 V 1
VccSPI 3.3 V Supply for SPI Controller Logic 3.14 3.3 3.47 V 1
1.05 V Supply for Intel® Management
VccASW .998 1.05 1.10 V 1
Engine and Integrated LAN
VccRTC (G3-S0) Battery Voltage 2 — 3.47 V 1
Intel High Definition Audio Controller
VccSusHDA 3.14 3.3 3.47 V 1
Suspend Voltage
VccSusHDA (low Intel High Definition Audio Controller Low
1.43 1.5 1.58 V 1
voltage) Voltage Mode Suspend Voltage
Display DAC Analog Power. This power is
VccADAC 3.14 3.3 3.47 V 1
supplied by the core well.
VccDSW3_3 3.3 V supply for Deep Sx wells 3.14 3.3 3.47 V 1
NOTES:
1. The I/O buffer supply voltage is measured at the PCH package pins. The tolerances shown in Table 8-8 are
inclusive of all noise from DC up to 20 MHz. In testing, the voltage rails should be measured with a
bandwidth limited oscilloscope that has a rolloff of 3 dB/decade above 20 MHz.
2. Includes Single Ended clocks REFCLK14IN, CLKOUTFLEX[3:0] and PCICLKIN.
3. Includes only DC tolerance. AC tolerance will be 2% in addition to this range.
Datasheet 341
Electrical Characteristics
8.5 Display DC Characteristics
Table 8-9. Signal Groups
Signal Group Associated Signals Note
VGA DAC VGA_RED, VGA_GREEN, VGA_BLUE, VGA_IRTN
Digital DisplayPort DDP[D:B]_AUX[P,N]
Auxilliary
Table 8-10. CRT DAC Signal Group DC Characteristics: Functional Operating Range
(VccADAC = 3.3 V ±5%)
Parameter Min Nom Max Unit Notes
DAC Resolution — 8 — Bits 1
Max Luminance (full-scale) 1, 2, 4 white video level
0.665 0.7 0.77 V
voltage
Min Luminance 1, 3, 4 black video level
— 0 — V
voltage
LSB Current — 73.2 — uA 4, 5
Integral Linearity (INL) -1 — 1 LSB 1, 6
Differential Linearity (DNL) -1 — 1 LSB 1, 6
Video channel-channel voltage — — 6 % 7
amplitude mismatch
Monotonicity Yes
NOTES:
1. Measured at each R, G, B termination according to the VESA* Test Procedure – Evaluation
of Analog Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000).
2. Max steady-state amplitude
3. Min steady-state amplitude
4. Defined for a double 75- termination.
5. Set by external reference resistor value.
6. INL and DNL measured and calculated according to VESA video signal standards.
7. Max full-scale voltage difference among R,G,B outputs (percentage of steady-state full-
scale voltage).
Table 8-11. Display Port Auxiliary Signal Group DC Characteristics
Symbol Parameter Min Nom Max Unit
Aux peak-to-peak voltage at a transmit-
Vaux-diff-p-p 0.39 — 1.38 V
ting devices
Aux peak-to-peak voltage at a receiving
0.32 — 1.36 V
devices
Vaux-term-R AUX CH termination DC resistance — 100 —
V-aux-dc-cm AUX DC common mode voltage 0 — 2 V
V-aux_turn-CM Aux turn around common mode voltage — 0.4 V
342 Datasheet
Electrical Characteristics
8.6 AC Characteristics
Table 8-12. PCI Express* Interface Timings
Symbol Parameter Min Max Unit Figures Notes
Transmitter and Receiver Timings
Unit Interval – PCI Express*
UI 399.88 400.12 ps 5
Gen 1 (2.5 GT/s)
Unit Interval – PCI Express*
UI 199.9 200.1 ps 5
Gen 2 (5.0 GT/s)
Minimum Transmission Eye
TTX-EYE 0.7 — UI 8-29 1,2
Width
TTX-RISE/Fall D+/D- TX Out put Rise/Fall
0.125 UI 1,2
(Gen1) time
TTX-RISE/Fall D+/D- TX Out put Rise/Fall
0.15 UI 1,2
(Gen2) time
TRX-EYE Minimum Receiver Eye Width 0.40 — UI 8-30 3,4
NOTES:
1. Specified at the measurement point into a timing and voltage compliance test load and
measured over any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye
diagram)
2. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of
TTXJITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The
TTXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median
and the maximum deviation from the median is less than half of the total TX jitter budget
collected over any 250 consecutive TX UIs. It should be noted that the median is not the
same as the mean. The jitter median describes the point in time where the number of jitter
points on either side is approximately equal as opposed to the averaged time value.
3. Specified at the measurement point and measured over any 250 consecutive UIs. The test
load documented in the PCI Express* specification 2.0 should be used as the RX device
when taking measurements (also refer to the Receiver compliance eye diagram). If the
clocks to the RX and TX are not derived from the same reference clock, the TX UI
recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
4. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter
budget for the Transmitter and interconnect collected any 250 consecutive UIs. The TRX-
EYE-MEDIAN-to--MAX-JITTER specification ensures a jitter distribution in which the median and
the maximum deviation from the median is less than half of the total 0.6 UI jitter budget
collected over any 250 consecutive TX UIs. It should be noted that the median is not the
same as the mean. The jitter median describes the point in time where the number of jitter
points on either side is approximately equal as opposed to the averaged time value. If the
clocks to the RX and TX are not derived from the same reference clock, the TX UI
recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
5. Nominal Unit Interval is 400 ps for 2.5 GT/s and 200 ps for 5 GT/s.
Datasheet 343
Electrical Characteristics
Table 8-13. HDMI* Interface Timings (DDP[D:B][3:0])
Symbol Parameter Min Max Unit Figures Notes
Transmitter and Receiver Timings
UI Unit Interval 600 4000 ps
Minimum Transmission Eye
TTX-EYE 0.8 — UI 1,2
Width
D+/D- TX Out put Rise/Fall
TTX-RISE/Fall — 0.125 UI 1,2
time
TMDS
— 0.25 UI
Clock Jitter
T-skew- Intra pair skew at source
— 0.15 TBIT
intra-pair connector
T-skew- Inter pair skew at source Tchar
— 0.2
inter-pair connector acter
Duty Cycle Clock Duty Cycle 10 60% %
NOTES:
1. Specified at the measurement point into a timing and voltage compliance test load and
measured over any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye
diagram)
2. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of
TTXJITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The
TTXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median
and the maximum deviation from the median is less than half of the total TX jitter budget
collected over any 250 consecutive TX UIs. It should be noted that the median is not the
same as the mean. The jitter median describes the point in time where the number of jitter
points on either side is approximately equal as opposed to the averaged time value.
Table 8-14. Intel® SDVO Interface Timings
Symbol Parameter Min Max Unit Figures Notes
Transmitter and Receiver Timings
UI Unit Interval 369.89 1000 ps 5
Minimum Transmission
TTX-EYE 0.7 — UI 8-29 1,2
Eye Width
D+/D- TX Out put Rise/
TTX-RISE/Fall — 0.125 UI 1,2
Fall time
Minimum Receiver Eye
TRX-EYE 0.40 — UI 8-30 3,4
Width
NOTES:
1. Specified at the measurement point into a timing and voltage compliance test load and
measured over any 250 consecutive TX UIs. (Also refer to the Transmitter compliance eye
diagram)
2. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of
TTXJITTER-MAX = 0.30 UI for the Transmitter collected over any 250 consecutive TX UIs. The
TTXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median
and the maximum deviation from the median is less than half of the total TX jitter budget
collected over any 250 consecutive TX UIs. It should be noted that the median is not the
same as the mean. The jitter median describes the point in time where the number of jitter
points on either side is approximately equal as opposed to the averaged time value.
344 Datasheet
Electrical Characteristics
3. Specified at the measurement point and measured over any 250 consecutive UIs. The test
load documented in the PCI Express* specification 2.0 should be used as the RX device
when taking measurements (also refer to the Receiver compliance eye diagram). If the
clocks to the RX and TX are not derived from the same reference clock, the TX UI
recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
4. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter
budget for the Transmitter and interconnect collected any 250 consecutive UIs. The TRX-
EYE-MEDIAN-to--MAX-JITTER specification ensures a jitter distribution in which the median and
the maximum deviation from the median is less than half of the total 0.6 UI jitter budget
collected over any 250 consecutive TX UIs. It should be noted that the median is not the
same as the mean. The jitter median describes the point in time where the number of jitter
points on either side is approximately equal as opposed to the averaged time value. If the
clocks to the RX and TX are not derived from the same reference clock, the TX UI
recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
5. Nominal Unit Interval for highest Intel SDVO speed is 370 ps. However, depending on the
resolution on the interface, the UI may be more than 370 ps.
Table 8-15. DisplayPort* Interface Timings (DDP[D:B][3:0])
Symbol Parameter Min Nom Max Unit
Unit Interval for High Bit Rate
UI_High_Rate 370 — — ps
(2.7 Gbps/lane)
Unit Interval for Reduced Bit Rate
UI_Low_Rate 617 — — ps
(1.62 Gbps/lane)
Down_Spread_
Link clock down spreading 0 — 0.5 %
Amplitude
Down_Spread_
Link clock down-spreading frequency 30 — 33 kHz
Frequency
Ltx-skew- Lane Intra-pair output skew at Tx
— 20 ps
intrapair package pins
Ttx-rise/
Lane Intra-pair Rise/Fall time
fall_mismatch_ 5 % —
mismatch at Tx package pin
chipdiff
Differential Peak-to-peak Output
VTX-DIFFp-p-level1 0.34 0.4 0.46 V
Voltage level 1
Differential Peak-to-peak Output
VTX-DIFFp-p-level2 0.51 0.6 0.68 V
Voltage level 2
Differential Peak-to-peak Output
VTX-DIFFp-p-level3 0.69 0.8 0.92 V
Voltage level 3
VTX-preemp_ratio No Pre-emphasis 0 0 0 dB
VTX-preemp_ratio 3.5 dB Pre-emphasis Level 2.8 3.5 4.2 dB
VTX-preemp_ratio 6.0 dB Pre-emphasis Level 4.8 6 7.2 dB
LTX-SKEW- Lane-to-Lane Output Skew at Tx
— — 2 UI
INTER_PAIR package pins
Datasheet 345
Electrical Characteristics
Table 8-16. DisplayPort* Aux Interface
Symbol Parameter Min Nom Max Unit
UI Aux unit interval 0.4 0.5 0.6 µs
T-
AUX CH bus park time 10 — — ns
Aux_bus_park
Maximum allowable UI variation within
Tcycle-to-cycle
a single transaction at the connector 0.04 UI —
jitter
pins of a transmitting device
Maximum allowable UI variation within
a single transaction at the connector 0.05 UI —
pins of a receiving device
Table 8-17. DDC Characteristics
DDC Signals: VGA_DDC_CLK, VGA_DDC_DATA, DDP[D:C]_CTRLCLK,
DDP[D:C]_CTRLDATA
Standard
Fast Mode 1 MHz
Mode
Symbol Parameter Units
Max Min Max Min Max
Fscl Operating Frequency 100 0 400 0 1000 kHz
Tr Rise Time1 1000 20 + 0.1Cb 300 — 120 ns
Tf Fall Time1 300 20+0.1Cb2 300 — 120 ns
NOTE:
1. Measurement Point for Rise and Fall time: VIL(min) – VIL(max)
2. Cb = total capacitance of one bus line in pF. If mixed with High-speed mode devices, faster
fall times according to High-Speed mode Tr/Tf are allowed.
346 Datasheet
Electrical Characteristics
Table 8-18. CRT DAC AC Characteristics
Parameter Min Nom Max Units Notes
Pixel Clock Frequency 400 MHz
1, 2, 8 (10-90% of black-to-
R, G, B Video Rise Time 0.25 — 1.25 ns white transition, @ 400-MHz
pixel clock)
1, 3, 8 (90-10% of white-to-
R, G, B Video Fall Time 0.25 — 1.25 ns black transition, @ 400-MHz
pixel clock)
Settling Time 0.75 ns 1, 4, 8 @ 400 MHz pixel clock
Video channel-to-
0.625 ns 1, 5, 8 @ 400 MHz pixel clock
channel output skew
1, 6, 8 Full-scale voltage step
Overshoot/ Undershoot -0.084 — +0.084 V
of 0.7 V
Noise Injection Ratio 2.5 % 1, 7, 8
NOTES:
1. Measured at each R, G, B termination according to the VESA* Test Procedure – Evaluation
of Analog Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000).
2. R, G, B Max Video Rise/Fall Time: 50% of minimum pixel clock period.
3. R, G, B Min Video Rise/Fall Time: 10% of minimum pixel clock period.
4. Max settling time: 30% of minimum pixel clock period.
5. Video channel-channel output skew: 25% of minimum pixel clock period.
6. Overshoot/undershoot: ±12% of black-white video level (full-scale) step function.
7. Noise injection ratio: 2.5% of maximum luminance voltage (DC to maximum pixel
frequency).
8. R, G, B AC parameters are strongly dependent on the board implementation
Table 8-19. Clock Timings (Sheet 1 of 4)
Sym Parameter Min Max Unit Notes Figure
PCI Clock (CLKOUT_PCI[4:0])
t1 Period 29.566 30.584 ns 8-12
t2 High Time 10.826 17.850 ns 8-12
t3 Low Time 10.426 17.651 ns 8-12
Duty Cycle 40 60 %
t4 Rising Edge Rate 1.0 4 V/ns 8-12
t5 Falling Edge Rate 1.0 4 V/ns 8-12
Jitter — 500 ps 8,9
14.318 MHz Flex Clock
t6 Period 68.83 70.84 ns 8-12
t7 High Time 29.55 39.00 ns 8-12
t8 Low Time 29.16 38.80 ns 8-12
Duty Cycle 40 60 %
Rising Edge Rate 1.0 4 V/ns 5
Falling Edge Rate 1.0 4 V/ns 5
Jitter (14.318 MHz configured on
— 800 ps 8,9
CLKOUTFLEX1 or CLKOUTFLEX3)
Datasheet 347
Electrical Characteristics
Table 8-19. Clock Timings (Sheet 2 of 4)
Sym Parameter Min Max Unit Notes Figure
Jitter(14.318 MHz configured on
— 1000 ps 8,9
CLKOUTFLEX0 or CLKOUTFLEX2)
48 MHz Flex Clock
t9 Period 20.32 21.34 ns 8-12
t10 High Time 7.02 12.51 ns 8-12
t11 Low Time 6.63 12.30 ns 8-12
Duty Cycle 40 60 %
Rising Edge Rate 1.0 4 V/ns 5
Falling Edge Rate 1.0 4 V/ns 5
Jitter (48MHz configured on
— 410 ps 8,9
CLKOUTFLEX1 or CLKOUTFLEX3)
Jitter(48MHz configured on
— 510 ps 8,9
CLKOUTFLEX0 or CLKOUTFLEX2)
24 MHz Flex Clock
t12 Period 41.16 42.18 ns 8-12
t13 High Time 22.64 23.19 ns 8-12
t14 Low Time 18.52 18.98 ns 8-12
Duty Cycle 45 55 %
Rising Edge Rate 1.0 4 V/ns 5
Falling Edge Rate 1.0 4 V/ns 5
Jitter (24MHz configured on
— 330 ps 8,9
CLKOUTFLEX1 or CLKOUTFLEX3)
Jitter(24MHz configured on
— 510 ps 8,9
CLKOUTFLEX0 or CLKOUTFLEX2)
25 MHz Flex Clock
t51 Period 39.84 40.18 ns 8-12
t52 High Time 16.77 21.78 ns 8-12
t53 Low Time 16.37 21.58 ns 8-12
Duty Cycle 45 55 %
Rising Edge Rate 1.0 4 V/ns 5
Falling Edge Rate 1.0 4 V/ns 5
Jitter (25 MHz configured on
— — ps 16
CLKOUTFLEX2)
27 MHz Flex Clock
t15 Period 36.4 37.67 ns 8-12
t16 High Time 20.02 20.72 ns 8-12
t17 Low Time 16.38 16.95 ns 8-12
Duty Cycle 45 55 %
Rising Edge Rate 1.0 4 V/ns 5
Falling Edge Rate 1.0 4 V/ns 5
348 Datasheet
Electrical Characteristics
Table 8-19. Clock Timings (Sheet 3 of 4)
Sym Parameter Min Max Unit Notes Figure
Jitter (27MHz configured on
— 450 ps 8,9
CLKOUTFLEX1 or CLKOUTFLEX3)
Jitter (27MHz configured on 8,9
— 630 ps
CLKOUTFLEX0 or CLKOUTFLEX2)
CLKOUT_DP_[P,N]
Period Period SSC On 7.108 7.756 ns 8-31
Period Period SSC Off 7.108 7.704 ns 8-31
DtyCyc Duty Cycle 40 60 % 8-31
V_Swing Differential Output Swing 300 — mV 8-31
Slew_rise Rising Edge Rate 1.5 4 V/ns 8-31
Slew_fall Falling Edge Rate 1.5 4 V/ns 8-31
Jitter 150 ps 8,9
CLKOUT_PCIE[7:0]_[P,N], CLKOUT_DMI_[P,N], CLKOUT_PEG_[B:A]_[P,N],
CLKOUT_ITPXDP_[P,N]
Period Period SSC On 9.849 10.201 ns 8-31
Period Period SSC Off 9.849 10.151 ns 8-31
DtyCyc Duty Cycle 40 60 % 8-31
V_Swing Differential Output Swing 300 — mV 8-31
Slew_rise Rising Edge Rate 1.5 4 V/ns 8-31
Slew_fall Falling Edge Rate 1.5 4 V/ns 8-31
Jitter — 150 ps 8,9,10
SSC Spread Spectrum 0 0.5 % 13,14
SMBus/SMLink Clock (SMBCLK, SML1CLK)
fsmb Operating Frequency 10 100 KHz
t18 High time 4.0 50 s 2 8-21
t19 Low time 4.7 — s 8-21
t20 Rise time — 1000 ns 8-21
t21 Fall time — 300 ns 8-21
SMLink0 Clock (SML0CLK) (See note 15)
fsmb Operating Frequency 0 400 KHz
t18_SMLFM High time 0.6 50 s 2 8-21
t19_SMLFM Low time 1.3 — s 8-21
t20_SMLFM Rise time — 300 ns 8-21
t21_SMLFM Fall time — 300 ns 8-21
SMLink0 Clock (SML0CLK) (See note 17)
fsmb Operating Frequency 0 1000 KHz
t18_SMLFMP High time 0.26 s 2 8-21
t19_SMLFMP Low time 0.5 — s 8-21
t20_SMLFMP Rise time — 120 ns 8-21
t21_SMLFMP Fall time — 120 ns 8-21
Datasheet 349
Electrical Characteristics
Table 8-19. Clock Timings (Sheet 4 of 4)
Sym Parameter Min Max Unit Notes Figure
HDA_BCLK (Intel® High Definition Audio)
fHDA Operating Frequency 24.0 MHz
Frequency Tolerance — 100 ppm
Input Jitter (refer to Clock Chip
t26a — 300 ppm
Specification)
t27a High Time (Measured at 0.75 Vcc) 18.75 22.91 ns 8-12
t28a Low Time (Measured at 0.35 Vcc) 18.75 22.91 ns 8-12
Suspend Clock (SUSCLK)
fsusclk Operating Frequency 32 kHz 4
t39 High Time 9.5 — s 4
t39a Low Time 9.5 — s 4
XTAL25_IN/XTAL25_OUT
ppm12 CrystalTolerance cut accuracy max 35ppm(@ 25 °C +/- 3C)
ppm12 TempStability max 30ppm(10 °C to 70°C)
12
ppm Aging Max 5ppm
SPI_CLK
Output Rise Slew Rate (0.2Vcc -
Slew_Rise 1 4 V/ns 11 8-32
0.6Vcc)
Output Fall Slew Rate (0.6Vcc -
Slew_Fall 1 4 V/ns 11 8-32
0.2Vcc)
NOTES:
1. The CLK48 expects a 40/60% duty cycle.
2. The maximum high time (t18 Max) provide a simple ensured method for devices to detect
bus idle conditions.
3. BCLK Rise and Fall times are measured from 10%VDD and 90%VDD.
4. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
5. Edge rates in a system as measured from 0.8 V to 2.0 V.
6. The active frequency can be 5 MHz, 50 MHz, or 62.5 MHz depending on the interface
speed. Dynamic changes of the normal operating frequency are not allowed.
7. Testing condition: 1 K pull up to Vcc, 1 K pull down and 10 pF pull down and
1/2 inch trace (see Figure 8-32 for more detail).
8. Jitter is specified as cycle to cycle as measured between two rising edges of the clock being
characterized. Period min and max includes cycle to cycle jitter and is also measured
between two rising edges of the clock being characterized.
9. On all jitter measurements care should be taken to set the zero crossing voltage (for rising
edge) of the clock to be the point where the edge rate is the fastest. Using a Math function
= Average(Derivavitive(Ch1)) and set the averages to 64, place the cursors where the
slope is the highest on the rising edge – usually this lower half of the rising edge. The
reason this is defined is for users trying to measure in a system it is impossible to get the
probe exactly at the end of the Transmission line with large Flip Chip components, this
results in a reflection induced ledge in the middle of the rising edge and will significantly
increase measured jitter.
10. Phase jitter requirement: The designated Gen2 outputs will meet the reference clock jitter
requirements from the PCI Express* Gen2 Base Specification. The test is to be performed
on a component test board under quiet conditions with all clock outputs on. Jitter analysis
is performed using a standardized tool provided by the PCI SIG. Measurement
methodology is defined in Intel document “PCI Express Reference Clock Jitter
Measurements”. This is not for CLKOUT_PCIE[7:0].
11. Testing condition: 1-k pull-up to Vcc, 1 k pull down and 10 pF pull-down and
1/2 inch trace (see Figure 8-32 for more detail).
350 Datasheet
Electrical Characteristics
12. Total of crystal cut accuracy, frequency variations due to temperature, parasitics, load
capacitance variations and aging is recommended to be less than 90 ppm.
13. Spread Spectrum (SSC) is referenced to rising edge of the clock.
14. Spread Spectrum (SSC) of 0.25% on CLKOUT_PCIE[7:0] and CLKOUT_PEG_[B:A] is used
for WiMAX friendly clocking purposes.
15. When SMLink0 is configured to run in Fast Mode (FM) using a soft strap, the supported
operating range is 0 Hz ~ 400 kHz, but the typical operating frequency is in the range of
300 kHz – 400 kHz.
16. The 25 MHz output option for CLKOUTFLEX2 is derived from the 25 MHz crystal input to
the PCH. The PPM of the 25 MHz output is equivalent to that of the crystal.
17. When SMLink0 is configured to run in Fast Mode Plus (FMP) using a soft strap, the
supported operating range is 0 Hz ~ 1 MHz, but the typical operating frequency is in the
range of 900 kHz – 1000 kHz. This is the default mode for this interface.
Table 8-20. Universal Serial Bus Timing (Sheet 1 of 2)
Sym Parameter Min Max Units Notes Fig
Full-speed Source (Note 7)
1, 6 CL = 50
t100 USBPx+, USBPx- Driver Rise Time 4 20 ns 8-18
pF
1, 6 CL = 50
t101 USBPx+, USBPx- Driver Fall Time 4 20 ns 8-18
pF
Source Differential Driver Jitter
t102 - To Next Transition –3.5 3.5 ns 2, 3 8-19
- For Paired Transitions –4 4 ns
t103 Source SE0 interval of EOP 160 175 ns 4 8-20
Source Jitter for Differential
t104 –2 5 ns 5
Transition to SE0 Transition
Receiver Data Jitter Tolerance
t105 - To Next Transition –18.5 18.5 ns 3 8-19
- For Paired Transitions –9 9 ns
t106 EOP Width: Must accept as EOP 82 — ns 4 8-20
Width of SE0 interval during
t107 — 14 ns
differential transition
Low-speed Source (Note 8)
6
t108 USBPx+, USBPx – Driver Rise Time 75 300 ns CL = 200 pF 8-18
CL =600 pF
6
t109 USBPx+, USBPx – Driver Fall Time 75 300 ns CL = 200 pF 8-18
CL =600 pF
Source Differential Driver Jitter
t110 To Next Transition –25 25 ns 2, 3 8-19
For Paired Transitions –14 14 ns
t111 Source SE0 interval of EOP 1.25 1.50 µs 4 8-20
Source Jitter for Differential
t112 –40 100 ns 5
Transition to SE0 Transition
Datasheet 351
Electrical Characteristics
Table 8-20. Universal Serial Bus Timing (Sheet 2 of 2)
Sym Parameter Min Max Units Notes Fig
Full-speed Source (Note 7)
Receiver Data Jitter Tolerance
t113 - To Next Transition –152 152 ns 3 8-19
- For Paired Transitions –200 200 ns
t114 EOP Width: Must accept as EOP 670 — ns 4 8-20
Width of SE0 interval during
t115 — 210 ns
differential transition
NOTES:
1. Driver output resistance under steady state drive is specified at 28 at minimum and 43
at maximum.
2. Timing difference between the differential data signals.
3. Measured at crossover point of differential data signals.
4. Measured at 50% swing point of data signals.
5. Measured from last crossover point to 50% swing point of data line at leading edge of EOP.
6. Measured from 10% to 90% of the data signal.
7. Full-speed Data Rate has minimum of 11.97 Mb/s and maximum of 12.03 Mb/s.
8. Low-speed Data Rate has a minimum of 1.48 Mb/s and a maximum of 1.52 Mb/s.
Table 8-21. SATA Interface Timings
Sym Parameter Min Max Units Notes Figure
UI Gen I Operating Data Period 666.43 670.23 ps
Gen II Operating Data Period
UI-2 333.21 335.11 ps
(3Gb/s)
Gen III Operating Data Period
UI-3 166.6083 166.6667 ps
(6Gb/s)
t120gen1 Rise Time 0.15 0.41 UI 1
t121gen1 Fall Time 0.15 0.41 UI 2
t120gen2 Rise Time 0.2 0.41 UI 1
t121gen2 Fall Time 0.2 0.41 UI 2
t120gen3 Rise Time 0.2 0.48 UI 1
t121gen3 Fall Time 0.2 0.48 UI 2
t122 TX differential skew — 20 ps
t123 COMRESET 304 336 ns 3
t124 COMWAKE transmit spacing 101.3 112 ns 3
t125 OOB Operating Data period 646.67 686.67 ns 4
NOTES:
1. 20% – 80% at transmitter
2. 80% – 20% at transmitter
3. As measured from 100 mV differential crosspoints of last and first edges of burst.
4. Operating data period during Out-Of-Band burst transmissions.
352 Datasheet
Electrical Characteristics
Table 8-22. SMBus and SMLink Timing
Note
Sym Parameter Min Max Units Fig
s
Bus Free Time Between Stop and Start
t130 4.7 — µs 8-21
Condition
Bus Free Time Between Stop and Start
t130SMLFM 1.3 — µs 5 8-21
Condition
Bus Free Time Between Stop and Start
t130SMLFMP 0.5 — µs 5 8-21
Condition
Hold Time after (repeated) Start
t131 Condition. After this period, the first 4.0 — µs 8-21
clock is generated.
Hold Time after (repeated) Start
t131SMLFM Condition. After this period, the first 0.6 — µs 5 8-21
clock is generated.
Hold Time after (repeated) Start
t131SMLFMP Condition. After this period, the first 0.26 — µs 5 8-21
clock is generated.
t132 Repeated Start Condition Setup Time 4.7 — µs 8-21
t132SMLFM Repeated Start Condition Setup Time 0.6 — µs 5 8-21
t132SMLFMP Repeated Start Condition Setup Time 0.26 — µs 5 8-21
t133 Stop Condition Setup Time 4.0 — µs 8-21
t133SMLFM Stop Condition Setup Time 0.6 — µs 5 8-21
t133SMLFMP Stop Condition Setup Time 0.26 — µs 5 8-21
t134 Data Hold Time 300 — ns 4 8-21
t134SMLFM Data Hold Time 0 — ns 4, 5 8-21
t134SMLFMP Data Hold Time 0 — ns 4, 5 8-21
t135 Data Setup Time 250 — ns 8-21
t135SMLFM Data Setup Time 100 — ns 5 8-21
t135SMLFMP Data Setup Time 50 — ns 5 8-21
t136 Device Time Out 25 35 ms 1
Cumulative Clock Low Extend Time
t137 — 25 ms 2 8-22
(slave device)
Cumulative Clock Low Extend Time
t138 — 10 ms 3 8-22
(master device)
NOTES:
1. A device will timeout when any clock low exceeds this value.
2. t137 is the cumulative time a slave device is allowed to extend the clock cycles in one
message from the initial start to stop. If a slave device exceeds this time, it is expected to
release both its clock and data lines and reset itself.
3. t138 is the cumulative time a master device is allowed to extend its clock cycles within
each byte of a message as defined from start-to-ack, ack-to-ack or ack-to-stop.
4. t134 has a minimum timing for I2C of 0 ns, while the minimum timing for SMBus/SMLINK
is 300 ns.
5. Timings with the SMLFM designator apply only to SMLink0 and only when SMLink0 is
operating in Fast Mode.
Datasheet 353
Electrical Characteristics
Table 8-23. Intel® High Definition Audio (Intel® HD Audio) Timing
Sym Parameter Min Max Units Notes Fig
Time duration for which HDA_SD is
t143 7 — ns 8-24
valid before HDA_BCLK edge.
Time duration for which HDA_SDO is
t144 7 — ns 8-24
valid after HDA_BCLK edge.
Setup time for HDA_SDI[3:0] at rising
t145 15 — ns 8-24
edge of HDA_BCLK
Hold time for HDA_SDI[3:0] at rising
t146 0 — ns 8-24
edge of HDA_BCLK
Table 8-24. LPC Timing
Sym Parameter Min Max Units Notes Fig
LAD[3:0] Valid Delay from PCICLK
t150 2 11 ns 8-13
Rising
LAD[3:0] Output Enable Delay from
t151 2 — ns 8-17
PCICLK Rising
LAD[3:0] Float Delay from PCICLK
t152 — 28 ns 8-15
Rising
t153 LAD[3:0] Setup Time to PCICLK Rising 7 — ns 8-14
t154 LAD[3:0] Hold Time from PCICLK Rising 0 — ns 8-14
LDRQ[1:0]# Setup Time to PCICLK
t155 12 — ns 8-14
Rising
LDRQ[1:0]# Hold Time from PCICLK
t156 0 — ns 8-14
Rising
t157 eE# Valid Delay from PCICLK Rising 2 12 ns 8-13
Table 8-25. Miscellaneous Timings
Sym Parameter Min Max Units Notes Fig
t160 SERIRQ Setup Time to PCICLK Rising 7 — ns 8-14
t161 SERIRQ Hold Time from PCICLK Rising 0 — ns 8-14
t162 RI#, GPIO, USB Resume Pulse Width 2 — RTCCLK 8-16
t163 SPKR Valid Delay from OSC Rising — 200 ns 8-13
t164 SERR# Active to NMI Active — 200 ns
354 Datasheet
Electrical Characteristics
Table 8-26. SPI Timings (20 MHz)
Sym Parameter Min Max Units Notes Fig
Serial Clock Frequency - 20 MHz
t180a 17.2 18.73 MHz 1
Operation
Tco of SPI_MOSI and SPI_IO[2:3] with
t183a respect to serial clock falling edge at the -5 13 ns 8-23
host
Setup of SPI_MISO and SPI_IO[2:3]
t184a with respect to serial clock falling edge 16 — ns 8-23
at the host
Hold of SPI_MISO and SPI_IO[2:3] with
t185a respect to serial clock falling edge at the 0 — ns 8-23
host
Setup of SPI_CS[1:0]# assertion with
t186a 30 — ns 8-23
respect to serial clock rising at the host
Hold of SPI_CS[1:0]# de-assertion with
t187a 30 — ns 8-23
respect to serial clock falling at the host
t188a SPI_CLK High Time 26.37 — ns 8-23
t189a SPI_CLK Low Time 26.82 — ns 8-23
NOTES:
1. The typical clock frequency driven by the PCH is 17.86 MHz.
2. Measurement point for low time and high time is taken at 0.5(VccSPI).
Table 8-27. SPI Timings (33 MHz)
Sym Parameter Min Max Units Notes Fig
Serial Clock Frequency - 33 MHz
t180b 29.83 33.81 MHz 1
Operation
Tco of SPI_MOSI and SPI_IO[2:3] with
t183b respect to serial clock falling edge at -5 5 ns 8-23
the host
Setup of SPI_MISO and SPI_IO[2:3]
t184b with respect to serial clock falling edge 8 — ns 8-23
at the host
Hold of SPI_MISO and SPI_IO[2:3]
t185b with respect to serial clock falling edge 0 — ns 8-23
at the host
Setup of SPI_CS[1:0]# assertion with
t186b 30 — ns 8-23
respect to serial clock rising at the host
Hold of SPI_CS[1:0]# de-assertion
t187b with respect to serial clock falling at the 30 — ns 8-23
host
t188b SPI_CLK High Time 14.88 - ns 8-23
t189b SPI_CLK Low Time 15.18 - ns 8-23
NOTES:
1. The typical clock frequency driven by the PCH is 33 MHz.
2. Measurement point for low time and high time is taken at 0.5(VccSPI).
Datasheet 355
Electrical Characteristics
Table 8-28. SPI Timings (50 MHz)
Sym Parameter Min Max Units Notes Fig
Serial Clock Frequency - 50 MHz
t180c 46.99 53.40 MHz 1
Operation
Tco of SPI_MOSI and SPI_IO[2:3] with
t183c respect to serial clock falling edge at -3 3 ns 8-23
the host
Setup of SPI_MISO and SPI_IO[2:3]
t184c with respect to serial clock falling edge 8 — ns 8-23
at the host
Hold of SPI_MISO and SPI_IO[2:3]
t185c with respect to serial clock falling edge 0 — ns 8-23
at the host
Setup of SPI_CS[1:0]# assertion with
t186c respect to serial clock rising edge at the 30 — ns 8-23
host
Hold of SPI_CS[1:0]# assertion with
t187c respect to serial clock rising edge at the 30 — ns 8-23
host
t188c SPI_CLK High Time 7.1 — ns 2, 3 8-23
t189c SPI_CLK Low Time 11.17 — ns 2, 3 8-23
NOTE:
1. Typical clock frequency driven by the PCH is 50 MHz.
2. When using 50 MHz mode ensure target flash component can meet t188c and t189c
specifications. Measurement should be taken at a point as close as possible to the package
pin.
3. Measurement point for low time and high time is taken at 0.5(VccSPI).
Table 8-29. SST Timings (Server/Workstation Only)
Sym Parameter Min Max Units Notes Fig
Bit time (overall time evident on SST) 0.495 500 µs
tBIT 1 -
Bit time driven by an originator 0.495 250 µs
Bit time jitter between adjacent bits in an
tBIT,jitter SST message header or data bytes after — — %
timing has been negotiated
Change in bit time across a SST address
or SST message bits as driven by the
tBIT,drift — — %
originator. This limit only applies across
tBIT-A bit drift and tBIT-M drift.
tH1 High level time for logic '1' 0.6 0.8 x tBIT 2
tH0 High level time for logic '0' 0.2 0.4 x tBIT
Rise time (measured from VOL = 0.3V to ns/
tSSTR — 25 + 5
VIH,min) node
Fall time (measured from VOH = 1.1V to ns/
tSSTF — 33
VIL,max) node
NOTES:
1. The originator must drive a more restrictive time to allow for quantized sampling errors by
a client yet still attain the minimum time less than 500 µs. tBIT limits apply equally to tBIT-
A and tBIT-M. PCH is targeted on 1 Mbps which is 1 µs bit time.
2. The minimum and maximum bit times are relative to tBIT defined in the Timing Negotiation
pulse.
3. tBIT-A is the negotiated address bit time and tBIT-M is the negotiated message bit time.
356 Datasheet
Electrical Characteristics
Table 8-30. Controller Link Receive Timings
Sym Parameter Min Max Units Notes Fig
t190 Single bit time 13 — ns 8-33
t191 Single clock period 15 — ns 8-33
t192 Rise time/Fall time 0.11 3.5 V/ns 1 8-34
t193 Setup time before CL_CLK 0.9 — ns 8-33
t194 Hold time after CL_CLK 0.9 — ns 8-33
CL_Vref -
VIL_AC Input low voltage (AC) V 2
0.08
CL_Vref
VIH_AC Input high voltage (AC) V 2
+0.08
NOTES:
1. Measured from (CL_Vref – 50 mV to CL_Vref + 50 mV) at the receiving device side. No
test load is required for this measurement as the receiving device fulfills this purpose.
2. CL_Vref = 0.12*(VccSus3_3).
Table 8-31. USB 3.0 Interface Transmit and Receiver Timings
Sym Parameter Min Max Units Notes Fig
Unit Interval – USB 3.0
UI 199.94 200.06 ps
(5.0 GT/s)
Minimum Transmission Eye
TTX-EYE 0.625 — UI
Width
Datasheet 357
Electrical Characteristics
8.7 Power Sequencing and Reset Signal Timings
Table 8-32. Power Sequencing and Reset Signal Timings (Sheet 1 of 3)
Sym Parameter Min Max Units Notes Fig
8-1,
t200 VccRTC active to RTCRST# de-assertion 9 — ms 26
8-2
RTCRST# de-assertion to DPWROK 8-1,
t200a 1 — us
high 8-2
8-1,
t200b VccDSW3_3 active to DPWROK high 10 — ms
8-2
8-1,
t200c VccDSW3_3 active to VccSus3_3 active 0 — ms
8-2
VccSUS active to RSMRST# de- 8-1,
t201 10 — ms 1
assertion 8-2
DPWROK high to SLP_SUS# de- 8-1,
t202 95 — ms 2, 3
assertion 8-2
RSMRST# and SLP_SUS# de-assertion 8-1,
t202a 5 — ms 3, 4
to SUSCLK toggling 8-2
t203 SLP_S5# high to SLP_S4# high 30 µs 5, 29 8-3
t204 SLP_S4# high to SLP_S3# high 30 µs 6 8-3
t205a Vcc active to PWROK high 5 — ms 7, 13
t205b PWROK high to PLTRST# de-assertion 99 ms 24
t206 PWROK deglitch time 1 — ms 8
t207 VccASW active to APWROK high 1 — ms
PWROK high to PCH clock outputs
t208 1 — ms 9
stable
PCH clock output stable to
t209 1 — ms
PROCPWRGD high
PROCPWRGD and SYS_PWROK high to
t210 1 — ms
SUS_STAT# de-assertion
SUS_STAT# de-assertion to PLTRST#
t211 60 — µs
de-assertion
t212 APWROK high to SPI Soft Strap Reads 500 — µs 22
t213 APWROK high to CL_RST# de-asserted 500 — µs 10
DMI message and all PCI Express ports
t214 and DMI in L2/L3 state to SUS_STAT# 60 — µs 8-6
active
t215 SUS_STAT# active to PLTRST# active 210 — µs 8-6
PLTRST# active to PROCPWRGD
t217 30 — µs 8-6
inactive
t218 PROCPWRGD inactive to clocks invalid 10 — µs 8-6
t219 Clocks invalid to SLP_S3# assertion 1 — µs 8-6
t220 SLP_S3# low to SLP_S4# low 30 — µs 8-6
t221 SLP_S4# low to SLP_S5# low 30 — µs 8-6
t222 SLP_S3# active to PWROK de-asserted 0 — 8-6
358 Datasheet
Electrical Characteristics
Table 8-32. Power Sequencing and Reset Signal Timings (Sheet 2 of 3)
Sym Parameter Min Max Units Notes Fig
t223 PWROK rising to DRAMPWROK rising 0 — µs 8-8
t224 DRAMPWROK falling to SLP_S4# falling -100 — ns 11, 23 8-8
t225 VccRTC active to VccDSW3_3 active 0 — ms 1, 12 8-2
t227 VccSus active to VccASW active 0 — ms 1
t229 VccASW active to Vcc active 0 — ms
t230 APWROK high to PWROK high 0 — ms
13, 15,
t231 PWROK low to Vcc falling 40 — ns 16, 27,
28
15, 16,
t232 APWROK falling to VccASW falling 40 — ns
27, 28
t233 SLP_S3# assertion to Vcc rail falling 5 — µs 13, 14
DPWROK falling to VccDSW3_3 rail 15, 16,
t234 40 ns 8-7
falling 27, 28
1, 15,
RSMRST# assertion to VccSUS rail
t235 40 — ns 16, 27, 8-7
falling
28
RTCRST# de-assertion to VccRTC rail
t236 0 — ms 8-7
falling
SLP_LAN# (or LANPHYPC) rising to
t237 — 20 ms
Intel LAN Phy power high and stable
1, 13,
DPWROK falling to any of VccDSW3_3,
t238 70 — ns 15, 16,
VccSUS, VccASW, or Vcc falling
27, 28
VccSus supplies active to Vcc supplies
t241 0 — ms 1, 13
active
t242 HDA_RST# active low pulse width 1 — s
VccSus active to SLP_S5#, SLP_S4#,
t244 SLP_S3#, SUS_STAT#, PLTRST# and — 50 ns 21
PCIRST# valid
S4 Wake Event to SLP_S4# inactive
t246 See Note Below 5
(S4 Wake)
S3 Wake Event to SLP_S3# inactive
t247 See Note Below 6
(S3 Wake)
RSMRST# de-assertion to APWROK
t251 0 — ms
assertion
THRMTRIP# active to SLP_S3#,
t252 — 175 ns
SLP_S4#, SLP_S5# active
RSMRST# rising edge transition from
t253 — 50 s
20% to 80%
t254 RSMRST# falling edge transition — 50 µs 18, 19
Datasheet 359
Electrical Characteristics
Table 8-32. Power Sequencing and Reset Signal Timings (Sheet 3 of 3)
Sym Parameter Min Max Units Notes Fig
DPWROK rising edge transition from
t255 — 50 s
20% to 80%
t256 DPWROK falling edge transition — 50 µs 19, 20
Power cycle duration for a global reset
other than G3 or Deep Sx. Also the
t257 4-5 — sec 25
duration of a host reset with power
cycle.
NOTES:
1. VccSus supplies include VccSus3_3 and VccSusHDA. Also includes DcpSus for mobile
platforms that power DcpSus externally.
2. This timing is a nominal value counted using RTC clock. If RTC clock isn’t already stable at
the rising edge of RSMRST#, this timing could be shorter or longer than the specified
value.
3. Platforms not supporting Deep Sx will typically have SLP_SUS# left as no connect. Hence
DPWROK high and RSMRST# de-assertion to SUSCLK toggling would be
t202+t202a=100 ms minimum.
4. Platforms supporting Deep Sx will have SLP_SUS# de-assert prior to RSMRST#. Platforms
not supporting Deep Sx will have RSMRST# de-assert prior to SLP_SUS#.
5. Dependency on SLP_S4# and SLP_A# stretching
6. Dependency on SLP_S3# and SLP_A# stretching
7. It is required that the power rails associated with PCI/PCIe (typically the 3.3 V, 5 V, and
12 V core well rails) have been valid for 99 ms after PWROK assertion in order to comply
with the 100 ms PCI/PCIe 2.0 specification on PLTRST# de-assertion. System designers
must ensure the requirement is met on the platforms.
8. Ensure PWROK is a solid logic '1' before proceeding with the boot sequence. Note: If
PWROK drops after t206 it will be considered a power failure.
9. Timing is dependant on whether 25 MHz crystal is stable by the time PWROK is high.
10. Requires SPI messaging to be completed.
11. The negative min timing implies that DRAMPWROK must either fall before SLP_S4# or
within 100 ns after it.
12. The VccDSW3_3 supplies must never be active while the VccRTC supply is inactive.
13. Vcc includes VccIO, Vcc, Vcc3_3, VccADAC1_5, VccADACBG3_3, V_PROC_IO, VccCLK,
VccCLK3_3, VccVRM, and VccASW (if Intel ME only powered in S0).
14. A Power rail is considered to be inactive when the rail is at its nominal voltage minus 5% or
less.
15. Board design may meet (t231 AND t232 AND t234 AND t235) OR (t238).
16. The definition of rail falling for this timing requirement is as follows: 1) VCCDSW3_3 and
VCCSUS3_3 is 2.9V; 2) VCCASW and DCPSUS* (in external suspend VR mode) is 0.92V;
3) VCC is 0.99V.
17. If RTC clock is not already stable at RSMRST# rising edge, this time may be longer.
18. RSMRST# falling edge must transition to 0.8 V or less before VccSus3_3 drops to 2.9 V
19. The 50 µs should be measured from Vih to Vil (2 V to 0.78 V).
20. DPWROK falling edge must transition to 0.8V or less before VccDSW3_3 drops to 2.9V
21. This is an internal timing showing when the signals (SLP_S5#, SLP_S4#, SLP_S3#,
SUS_STAT#, PLTRST# and PCIRST#) are valid after VccSus rail is Active.
22. APWROK high to SPI Soft Strap Read is an internal PCH timing. The timing cannot be
measured externally and included here for general power sequencing reference.
23. If Deep Sx was entered from S3. SLP_S4# will remain high while DRAMPWROK is
undriven.
24. Timing enabled through soft strap. If T205b is not enabled, the platform is responsible for
controlling the assertion timing of PWROK and SYS_PWROK in such a way that it satisfies
the PCIe timing requirement of power stable to reset de-assertion.
25. Programmable using PM_CFG.PWR_CYC_DUR. Default is 4–5 seconds.
26. Measured from VCCRTC-10% to RTCRST# reaching 0.55*VCCRTC. VCCRTC is defined as
the final settling voltage that the rail ramps.
360 Datasheet
Electrical Characteristics
27. Requirement applies to power failure and surprise power down scenario.
28. Ensure respective PWROK signals (PCH_PWROK, APWROK and RSMRST#) toggle
appropriately during normal power state transition (for example S0->Sx->S0, S0->Deep
Sx->S0, and so on) even if the supply voltage does not drop below the specified value. Use
of the stretch registers can be used to achieve this.
29. Timing does not apply after Deep Sx exit when Intel ME has configured SLP_S5# and/or
SLP_S4# to rise with SLP_A#.
8.8 Power Management Timing Diagrams
Figure 8-1. G3 w/RTC Loss to S4/S5 (With Deep Sx Support) Timing Diagram
S o u rc e D e s tin a tio n S ig n a l N a m e
G3 D e e p S 4 /S 5 S 5 /S 4
B o a rd PCH V ccR TC t2 2 5
t2 0 0
B o a rd PCH RTCRST#
t2 0 0 a
B o a rd PCH V ccD S W 3_3
t2 0 0 b
B o a rd PCH DPW ROK
t2 0 0 c
PCH B o a rd SLP_SUS# t2 0 2
B o a rd PCH VccSus
t2 0 1
B o a rd PCH RSM RST# t2 2 6
PCH B o a rd S U S C LK v a lid
t2 0 2 a
PCH B o a rd S LP _S 5# O n ly fo r S 4 a fte r G 3 o r D e e p S x
Note: VCCSUS rail ramps up later in comparison to VCCDSW due to assumption that
SLP_SUS# is used to control power to VCCSUS.
Figure 8-2. G3 w/RTC Loss to S4/S5 (Without Deep Sx Support) Timing Diagram
S o u rc e D e s tin a tio n S ig n a l N a m e
G3 S 5 /S 4
B o a rd PCH VccR TC t2 2 5
t2 0 0
B o a rd PCH RTCRST#
t2 0 0 a
B o a rd PCH V ccD S W 3_3
t2 0 0 b
B o a rd PCH DPW ROK
t2 0 0 c
PCH B o a rd S LP_S U S# t2 0 2
B o a rd PCH VccSus
t2 0 1
B o a rd PCH RSMRST# t2 2 6
PCH B o a rd S U SC LK v a lid
t2 0 2 a
PCH B o a rd S LP_S 5# O n ly fo r S 4 a fte r G 3
Datasheet 361
Electrical Characteristics
Figure 8-3. S5 to S0 Timing Diagram
Source Dest Signal Name
PCH Board SLP_S5#
PCH Board SLP_S4# t203
PCH Board SLP_S3# t204
PCH Board SLP_A# Could already be high before this sequence begins (to support M3),
but will never go high later than SLP_S3#
PCH Board SLP_LAN# Could already be high before this sequence begins (to support WOL),
but will never go high later than SLP_S3# or SLP_A#
Board PCH VccASW
t229
Board PCH Vcc
PROCPWRGD
Serial VID
CPU CPU VRM CPU SVID Load
V_vid
Board CPU VccCore_CPU
CPU VRM PCH SYS_PWROK
t205
Board PCH PWROK t206
t207
Board PCH APWROK APWROK may come up earlier
than PWROK, but no later
PCH CPU DRAMPWROK t230
25 MHz
Board PCH stable
Crystal Osc
PCH
PCH Board stable
Output Clocks
PCH CPU PROCPWRGD t208
t209
PCH Board SUS_STAT# t210
Assumes soft strap programmed to start at
PROCPWRGD - expected setting for SNB
CPU PCH THRMTRIP# ignored honored
PCH CPU/Board PLTRST# t211
_A s
E
NE ite
CK
SE DM N
DO wr
RE V DO
_
CP SK ET
T
SE
T_
ex ES
U_ U
P_
ST ing
Fl _R
RA
ain
U
CP
Tr
PCH CPU DMI
362 Datasheet
Electrical Characteristics
Figure 8-4. S3/M3 to S0 Timing Diagram
Source Dest Signal Name
PCH Board SLP_S5#
PCH Board SLP_S4#
PCH Board SLP_S3#
PCH Board SLP_A#
PCH Board SLP_LAN#
Board PCH VccASW
Board PCH Vcc
PROCPWRGD
Serial VID
CPU CPU VRM CPU SVID Load
Note: V_PROC_IO may go to Vboot at
this time, but can also stay at 0V V_vid
(default)
Board CPU VccCore_CPU
CPU VRM PCH SYS_PWROK
t205
Board PCH PWROK t206
Board PCH APWROK
PCH CPU DRAMPWROK
25 MHz
Board PCH stable
Crystal Osc
PCH
PCH Board stable
Output Clocks
t208
PCH CPU PROCPWRGD t209
PCH Board SUS_STAT# t210
Assumes soft strap programmed to start at
PROCPWRGD
CPU PCH THRMTRIP# ignored honored
PCH CPU/Board PLTRST# t211 E s
N ite CK
O w r _A
_ D M O NE
ET ET V D _D
S E S K U SET
ng P_ _ R S _ RE
ni A
ai R P U ex U
Tr ST C Fl CP
PCH CPU DMI
Figure 8-5. S5/Moff - S5/M3 Timing Diagram
S o u rc e D est S ig n a l N a m e
PCH B o a rd S L P _S 5#
PCH B o a rd S L P _S 4#
PCH B o a rd S L P _S 3#
PCH B o a rd SLP_A#
PCH B o a rd SLP_LAN# C o u ld a lre ad y b e h ig h b e fo re this se qu e n ce be g in s (to
su p po rt W O L), b ut w ill n e ve r g o hig h la te r th a n S L P_A #
B o a rd PCH V ccA S W
t2 07
B o a rd PCH APW ROK
t21 2
PCH S P I F la sh SPI
C L_R ST1# t21 3
PCH C o n tro lle r L in k
(M o b ile O n ly)
Datasheet 363
Electrical Characteristics
Figure 8-6. S0 to S5 Timing Diagram
Source Dest Signal Name
DMI DMI Message L2/L3
PCIe* normal
PCH PCIe Ports L2/L3
Devices operation
PCH Board SUS_STAT# t214
t215
PCH Board PLTRST# t217
PCH Board PROCPWRGD
CPU PCH THRMTRIP# honored ignored
t218
PCH
PCH Board valid
Output Clocks
PCH Board SLP_S3#
t219
PCH Board SLP_S4#
t220
PCH Board SLP_S5#
t221
t222
Board PCH PWROK
May drop before or after
SLP_S4/5# and DRAMPWRGD
Board PCH SYS_PWROK
PCH CPU DRAMPWROK
PCH Controller Link CL_RST1# ME-Related Signals
Going to M3: stay high
Going to MOFF: go low
Only switch if going to MOFF
Source of Live value from Value from MAC
PCH GbE PHY LANPHYPC value GbE MAC latched in SUS well
PCH Board SLP_A# If appropriate, save MAC
PMCSR context here
Board PCH APWROK
PCH Board SLP_LAN# SLP_LAN# could stay
high for M3 or WOL
364 Datasheet
Electrical Characteristics
Figure 8-7. S3/S4/S5 to Deep Sx to G3 w/ RTC Loss Timing Diagram
S o u rc e D e s t in a t io n S ig n a l N a m e
S 3 /S 4 /S 5 Deep Sx G3
PCH B o a rd (E C ) SUSW ARN# u n d r iv e n
B o a rd ( E C ) PCH SUSACK# u n d r iv e n
PCH B o a rd SLP_SUS# u n d r iv e n
SLP_S3# /
PCH B o a rd SLP_A#
u n d r iv e n
PCH B o a rd SLP_S 4# u n d r iv e n
S L P _ S 4 # d ro p s h e re if
n o t a lr e a d y a s s e rte d
PCH B o a rd S LP_S 5# u n d r iv e n
S L P _ S 5 # d ro p s h e re if
n o t a lr e a d y a s s e rte d
B o a rd PCH RSM RST#
t2 3 5
B o a rd PCH VccS us
B o a rd PCH DPW ROK
t2 3 4
B o a rd PCH V ccD S W 3_3
B o a rd PCH RTCRST#
t2 3 6
B o a rd PCH V ccR T C
Figure 8-8. G3 to Deep Sx Timing Diagram
Note: On a Deep Sx supported platform, platform must transition to Sx state upon G3 exit,
prior to determining that conditions are met for a Deep Sx transition (G3->Sx->Deep
Sx).
S o u rc e D e s tin a tio n S ig n a l N a m e S 5 /S 4 /S 3 Deep Sx
G3 Deep Sx
B o a rd PCH V ccR TC t2 2 5
t2 0 0
B o a rd PCH RTCRST#
t2 0 0 a
B o a rd PCH V ccD S W 3_3
t2 0 0 b
B o a rd PCH DPW ROK
PCH B o a rd SUSW ARN# u n d riv e n u n d riv e n
B o a rd PCH SUSACK# u n d riv e n u n d riv e n
PCH B o a rd SLP_SU S# t2 0 2
t2 0 0 c
B o a rd PCH V ccS us
t2 0 1 t2 3 5
B o a rd PCH RSMRST# t2 2 6
t2 0 2 a
PCH B o a rd SUSC LK v a lid
PCH B o a rd SLP _S5# u n d riv e n D e p e n d o n S x s ta te p rio r to e n try
PCH B o a rd S LP_S4# u n d riv e n
PCH B o a rd S LP_S3# u n d riv e n
Datasheet 365
Electrical Characteristics
Figure 8-9. DRAMPWROK Timing Diagram
Source Destination Signal Name
PCH Board SLP_S4#
Board PCH PWROK
PCH CPU DRAMPWROK t223 t224
366 Datasheet
Electrical Characteristics
8.9 AC Timing Diagrams
Figure 8-10. Clock Cycle Time
Figure 8-11. Transmitting Position (Data to Strobe)
CLKA/
CLKB
Tppos0
YA/YB
Tppos1
Tppos2
Tppos3
Tppos4
Tppos5
Tppos6
Figure 8-12. Clock Timing
Period
High Time
2.0V
0.8V
Low Time
Fall Time Rise Time
Datasheet 367
Electrical Characteristics
Figure 8-13. Valid Delay from Rising Clock Edge
Clock 1.5V
Valid Delay
Output VT
Figure 8-14. Setup and Hold Times
Clock 1.5V
Setup Time Hold Time
Input VT VT
Figure 8-15. Float Delay
Input VT
Float
Delay
Output
Figure 8-16. Pulse Width
Pulse Width
VT VT
368 Datasheet
Electrical Characteristics
Figure 8-17. Output Enable Delay
Clock 1.5V
Output
Enable
Delay
Output VT
Figure 8-18. USB Rise and Fall Times
Rise Time Fall Time
90% 90%
CL
Differential
Data Lines
10% 10%
CL
tR tF
Low-speed: 75 ns at CL = 50 pF, 300 ns at C L = 350 pF
Full-speed: 4 to 20 ns at C L = 50 pF
High-speed: 0.8 to 1.2 ns at C L = 10 pF
Figure 8-19. USB Jitter
T period
Crossover
Points
Differential
Data Lines
Jitter
Consecutive
Transitions
Paired
Transitions
Datasheet 369
Electrical Characteristics
Figure 8-20. USB EOP Width
Tperiod
Data
Crossover
Differential Level
Data Lines
EOP
Width
Figure 8-21. SMBus / SMLink Transaction
t19 t20
t21
SMBCLK
t135 t133
t131
t18
t134 t132
SMBDATA
t130
Note: txx also refers to txx_SM, txxx also refers to txxxSMLFM, SMBCLK also refers to
SML[1:0]CLK, and SMBDATA also refers to SML[1:0]DATA in Figure 8-21.
Figure 8-22. SMBus / SMLink Timeout
Start Stop
t137
CLKack CLKack
t138 t138
SMBCLK
SMBDATA
Note: SMBCLK also refers to SML[1:0]CLK and SMBDATA also refers to SML[1:0]DATA in
Figure 8-22.
370 Datasheet
Electrical Characteristics
Figure 8-23. SPI Timings
t188 t189
SPI_CLK
t183
SPI_MOSI
t184 t185
SPI_MISO
t186 t187
SPI_CS#
Figure 8-24. Intel® High Definition Audio (Intel® HD Audio) Input and Output Timings
HDA_BIT_CLK
HDA_SDOUT
t143 t144 t143 t144
HDA_SDIN[3:0]
t145 t146
Datasheet 371
Electrical Characteristics
Figure 8-25. Dual Channel Interface Timings
tDQSL
tDQS
DQs
tDH tDS
tDH tDS
DQ[7:0]
Figure 8-26. Dual Channel Interface Timings
DQ
D Q [7 : 0 ]
tDV W
tDQ S Q
tQ H tDQ S Q
Figure 8-27. LVDS Load and Transition Times
372 Datasheet
Electrical Characteristics
Figure 8-28. Transmitting Position (Data to Strobe)
CLKA/
CLKB
Tppos0
YA/YB
Tppos1
Tppos2
Tppos3
Tppos4
Tppos5
Tppos6
Figure 8-29. PCI Express* Transmitter Eye
Datasheet 373
Electrical Characteristics
Figure 8-30. PCI Express* Receiver Eye
VTS-Diff = 0mV
D+/D- Crossing point
VRS-Diffp-p-Min>175mV
.4 UI =TRX-EYE min
374 Datasheet
Electrical Characteristics
Figure 8-31. Measurement Points for Differential Waveforms
Differential Clock – Single Ended Measurements
V max = 1.15V V max = 1.15V
Clock#
Vcross max = Vcross max =
550mV 550mV
Vcross min = 300 mV Vcross min = 300 mV
Clock
V min = -0.30V V min = -0.30V
Clock#
Vcross delta = 140mV Vcross delta = 140mV
Clock
Clock# Clock#
Vcross median
+75mV
i se
T
fa
Tr
Vcross median Vcross median
ll
Vcross median -75mV
Clock Clock
Differential Clock – Differential Measurements
Clock Period (Differential )
Positive Duty Cycle (Differential ) Negative Duty Cycle (Differential )
0.0V
Clock-Clock#
Rise Fall
Edge Edge
Rate Rate
Vih_min = +150 mV
0.0V
Vil_max = -150 mV
Clock-Clock#
Datasheet 375
Electrical Characteristics
Figure 8-32. PCH Test Load
VccASW3_3
Figure 8-33. Controller Link Receive Timings
t191
CL_CLK1
t190
t193 t194
CL_DATA1
Figure 8-34. Controller Link Receive Slew Rate
t192 t192
CL_Vref + 50mV
CL_Vref
CL_CLK1 / CL_DATA1 CL_Vref – 50mV
Figure 8-35. PCH Suspend Well Ramp Up/Down Requirement
376 Datasheet
Electrical Characteristics
Figure 8-36. Sequencing Requirements between PCH VCCSUS (1.05V) and External USB
Vbus
Vbus
1.05V
VCCSUS 1.05V-5%
(1.05V)
T=0us T=0us
1. VCCSUS(1.05V) is in reference to DCPSUS* rails.
Figure 8-37. Sequencing Requirements between PCH VCC3_3 and VCC Core Rail
VCC3_3
(3.3V)
2.6V T2 <= 35 ms 2.6V
T1 <= 25 ms
No Slew Rate
Requirement
0V
No Limit
No = Preferred Sequence
VCC (1.05V) Limit
0.6V = Alternative Sequence
No Slew Rate
0V
Requirement
Figure 8-38. Sequencing Requirements between PCH VCC1_5 and VCC Core Rail
VCC1_5
(1.5V)
1.35V T2 <= 35 ms 1.35V
T1 <= 25 ms
No Slew Rate
Requirement
0V
No Limit
No = Preferred Sequence
VCC (1.05V) Limit
0.6V = Alternative Sequence
No Slew Rate
0V
Requirement
Datasheet 377
Electrical Characteristics
8.10 Sequencing Rails Within The Same Well
Table 8-33. Suspend Well Voltage Ramp Up/Down Requirements
Voltage Rail 1 Voltage Rail 2 Power Up Requirement Power Down Requirement
VCCSUS3_3 must be VCCSUS3_3 must be
DCPSUS1, powered up before powered down after
VCCSUS3_3 DCPSUS2, DCPSUS*, or not more than DCPSUS*, or not more than
DCPSUS3 0.7V below DCPSUS* while 0.7V below DCPSUS* while
the two rails ramp up. the two rails ramp down.
VCCSUS ramps up before VCCSUS ramps down after
VCCSUS Platform USB
Vbus reaches 1.05V while Vbus reaches 1.05V while
(DCPSUS* rails) Vbus
ramping up. ramping down.
In external VR mode (Mobile Only), this relationship needs to be met by the platform.
In internal VR mode, the PCH will meet this timing.
Table 8-34. Core Well Voltage Ramp Up/Down Requirements
Voltage Rail 1 Voltage Rail 2 Power Up Requirement Power Down Requirement
Preferred Option: Preferred Option:
- VCC powers up before - VCC powers down after
VCC3_3 VCC3_3
Alternative Option: Alternative Option:
VCC (1.05V) VCC3_3 (3.3V) - VCC3_3 may power up - VCC may power down
before VCC, but VCC must before VCC3_3, but VCC3_3
ramp up to 0.6V within must ramp down to 2.6V
25ms of VCC3_3 ramping within 35ms assuming a
to 2.6V. linear ramp.
Preferred Option: Preferred Option:
- VCC powers up before - VCC powers down after
VCC1_5 VCC1_5
Alternative Option: Alternative Option:
VCC1_5 (1.5V) - VCC1_5 may power up - VCC may power down
VCC (1.05V)
Note 1, 2 before VCC, but VCC must before VCC1_5, but VCC1_5
ramp up to 0.6V within must ramp down to 1.35V
25ms of VCC1_5 ramping within 35ms assuming a
to 1.35V. linear ramp.
NOTES:
1. VCC1_5 includes VCCADAC and VCCVRM.
2. For platforms not supporting VGA functionality, the VCCDAC rails may be tied to GND
inherently meeting the “preferred” sequencing requirement. If they are tied to the 1.5V for
platform layout simplicity even though the VGA/DAC functionality is not used, they must
meet the specified sequencing requirement.
3. (Desktop Only) If T1 is < 25 ms, T2 35 ms + (25 ms – T1)
§§
378 Datasheet
Register and Memory Mapping
9 Register and Memory Mapping
The PCH contains registers that are located in the processor I/O space and memory
space and sets of PCI configuration registers that are located in PCI configuration
space. This chapter describes the PCH I/O and memory maps at the register-set level.
Register access is also described. Register-level address maps and Individual register
bit descriptions are provided in the following chapters. The following notations and
definitions are used in the register/instruction description chapters.
Note: All Chipset Registers are located in the core well unless otherwise indicated.
RO Read Only. In some cases, if a register is read only, writes to this
register location have no effect. However, in other cases, two
separate registers are located at the same location where a read
accesses one of the registers and a write accesses the other
register. See the I/O and memory map tables for details.
WO Write Only. In some cases, if a register is write only, reads to this
register location have no effect. However, in other cases, two
separate registers are located at the same location where a read
accesses one of the registers and a write accesses the other
register. See the I/O and memory map tables for details.
R/W Read/Write. A register with this attribute can be read and
written.
R/WC Read/Write Clear. A register bit with this attribute can be read
and written. However, a write of 1 clears (sets to 0) the
corresponding bit and a write of 0 has no effect.
R/WO Read/Write-Once. A register bit with this attribute can be
written only once after power up. After the first write, the bit
becomes read only.
R/WL Read/Write Lockable. A register bit with the attribute can be
read at any time but writes may only occur if the associated lock
bit is set to unlock. If the associated lock bit is set to lock, this
register bit becomes RO unless otherwise indicated.
R/WLO Read/Write, Lock-Once. A register bit with this attribute can be
written to the non-locked value multiple times, but to the locked
value only once. After the locked value has been written, the bit
becomes read only.
R/W/SN Read/Write register initial value loaded from NVM.
Reserved The value of reserved bits must never be changed. For details,
see Section 9.2.
Default When the PCH is reset, it sets its registers to predetermined
default states. It is the responsibility of the system initialization
software to determine configuration, operating parameters, and
optional system features that are applicable, and to program the
PCH registers accordingly.
Bold Register bits that are highlighted in bold text indicate that the
bit is implemented in the PCH. Register bits that are not
implemented or are hardwired will remain in plain text.
Datasheet 379
Register and Memory Mapping
9.1 PCI Devices and Functions
The PCH incorporates a variety of PCI devices and functions, as shown in Table 9-1.
Device Functions can individually be disabled. The integrated Gigabit Ethernet
controller will be disabled if no Platform LAN Connect component is detected (See
Section 5.4). When a function is disabled, it does not appear at all to the software. A
disabled function will not respond to any register reads or writes, insuring that these
devices appear hidden to software.
Table 9-1. PCI Devices and Functions
Bus:Device:Function Function Description
Bus 0:Device 31:Function 0 LPC Controller1
Bus 0:Device 31:Function 2 SATA Controller #1
Bus 0:Device 31:Function 3 SMBus Controller
Bus 0:Device 31:Function 5 SATA Controller #22
Bus 0:Device 31:Function 6 Thermal Subsystem
Bus 0:Device 29:Function 03 USB EHCI Controller #1
Bus 0:Device 26:Function 03 USB EHCI Controller #2
Bus 0:Device 28:Function 0 PCI Express* Port 1
Bus 0:Device 28:Function 1 PCI Express Port 2
Bus 0:Device 28:Function 2 PCI Express Port 3
Bus 0:Device 28:Function 3 PCI Express Port 4
Bus 0:Device 28:Function 4 PCI Express Port 5
Bus 0:Device 28:Function 5 PCI Express Port 6
Bus 0:Device 28:Function 6 PCI Express Port 7
Bus 0:Device 28:Function 7 PCI Express Port 8
Bus 0:Device 27:Function 0 Intel® High Definition Audio Controller
Bus 0:Device 25:Function 0 Gigabit Ethernet Controller
Bus 0:Device 22:Function 0 Intel® Management Engine Interface #1
Bus 0:Device 22:Function 1 Intel Management Engine Interface #2
Bus 0:Device 22:Function 2 IDE-R
Bus 0:Device 22:Function 3 KT
Bus 0:Device 20:Function 0 xHCI Controller
NOTES:
1. The PCI-to-LPC bridge contains registers that control LPC, Power Management, System
Management, GPIO, Processor Interface, RTC, Interrupts, Timers, and DMA.
2. SATA controller 2 (D31:F5) is only visible when D31:F2 CC.SCC=01h.
3. Prior to BIOS initialization of the PCH USB subsystem, the EHCI controllers will appear as
Function 7. After BIOS initialization, the EHCI controllers will be Function 0.
4. This table shows the default PCI Express* Function Number-to-Root Port mapping.
Function numbers for a given root port are assignable through the “Root Port Function
Number and Hide for PCI Express Root Ports” register (RCBA+0404h).
380 Datasheet
Register and Memory Mapping
9.2 PCI Configuration Map
Each PCI function on the PCH has a set of PCI configuration registers. The register
address map tables for these register sets are included at the beginning of the chapter
for the particular function.
Configuration Space registers are accessed through configuration cycles on the PCI bus
by the Host bridge using configuration mechanism #1 detailed in the PCI Local Bus
Specification, Revision 2.3.
Some of the PCI registers contain reserved bits. Software must deal correctly with
fields that are reserved. On reads, software must use appropriate masks to extract the
defined bits and not rely on reserved bits being any particular value. On writes,
software must ensure that the values of reserved bit positions are preserved. That is,
the values of reserved bit positions must first be read, merged with the new values for
other bit positions and then written back. The software does not need to perform read,
merge, write operation for the configuration address register.
In addition to reserved bits within a register, the configuration space contains reserved
locations. Software should not write to reserved PCI configuration locations in the
device-specific region (above address offset 3Fh).
9.3 I/O Map
The I/O map is divided into Fixed and Variable address ranges. Fixed ranges cannot be
moved, but in some cases can be disabled. Variable ranges can be moved and can also
be disabled.
9.3.1 Fixed I/O Address Ranges
Table 9-2 shows the Fixed I/O decode ranges from the processor perspective. For each
I/O range, there may be separate behavior for reads and writes. DMI (Direct Media
Interface) cycles that go to target ranges that are marked as “Reserved” will not be
decoded by the PCH, and will be passed to PCI, unless the Subtractive Decode Policy bit
is set (D31:F0:Offset 42h, bit 0). If a PCI master targets one of the fixed I/O target
ranges, it will be positively decoded by the PCH in medium speed.
Address ranges that are not listed or marked “Reserved” are not decoded by the PCH
(unless assigned to one of the variable ranges).
Datasheet 381
Register and Memory Mapping
Table 9-2. Fixed I/O Ranges Decoded by PCH (Sheet 1 of 2)
I/O Address Read Target Write Target Internal Unit
00h–08h DMA Controller DMA Controller DMA
09h–0Eh RESERVED DMA Controller DMA
0Fh DMA Controller DMA Controller DMA
10h–18h DMA Controller DMA Controller DMA
19h–1Eh RESERVED DMA Controller DMA
1Fh DMA Controller DMA Controller DMA
20h–21h Interrupt Controller Interrupt Controller Interrupt
24h–25h Interrupt Controller Interrupt Controller Interrupt
28h–29h Interrupt Controller Interrupt Controller Interrupt
2Ch–2Dh Interrupt Controller Interrupt Controller Interrupt
2Eh–2Fh LPC SIO LPC SIO Forwarded to LPC
30h–31h Interrupt Controller Interrupt Controller Interrupt
34h–35h Interrupt Controller Interrupt Controller Interrupt
38h–39h Interrupt Controller Interrupt Controller Interrupt
3Ch–3Dh Interrupt Controller Interrupt Controller Interrupt
40h–42h Timer/Counter Timer/Counter PIT (8254)
43h RESERVED Timer/Counter PIT
4Eh–4Fh LPC SIO LPC SIO Forwarded to LPC
50h–52h Timer/Counter Timer/Counter PIT
53h RESERVED Timer/Counter PIT
60h Microcontroller Microcontroller Forwarded to LPC
61h NMI Controller NMI Controller Processor I/F
62h Microcontroller Microcontroller Forwarded to LPC
64h Microcontroller Microcontroller Forwarded to LPC
66h Microcontroller Microcontroller Forwarded to LPC
1
70h RESERVED NMI and RTC Controller RTC
71h RTC Controller RTC Controller RTC
72h RTC Controller NMI and RTC Controller RTC
73h RTC Controller RTC Controller RTC
74h RTC Controller NMI and RTC Controller RTC
75h RTC Controller RTC Controller RTC
76h RTC Controller NMI and RTC Controller RTC
77h RTC Controller RTC Controller RTC
DMA Controller, LPC, PCI, or
80h DMA Controller and LPC, PCI, or PCIe DMA
PCIe*
81h–83h DMA Controller DMA Controller DMA
84h–86h DMA Controller DMA Controller and LPC, PCI, or PCIe DMA
87h DMA Controller DMA Controller DMA
88h DMA Controller DMA Controller and LPC, PCI, or PCIe DMA
89h–8Bh DMA Controller DMA Controller DMA
8Ch–8Eh DMA Controller DMA Controller and LPC, PCI, or PCIe DMA
382 Datasheet
Register and Memory Mapping
Table 9-2. Fixed I/O Ranges Decoded by PCH (Sheet 2 of 2)
I/O Address Read Target Write Target Internal Unit
8Fh DMA Controller DMA Controller DMA
90h–91h DMA Controller DMA Controller DMA
92h Reset Generator Reset Generator Processor I/F
93h–9Fh DMA Controller DMA Controller DMA
A0h–A1h Interrupt Controller Interrupt Controller Interrupt
A4h–A5h Interrupt Controller Interrupt Controller Interrupt
A8h–A9h Interrupt Controller Interrupt Controller Interrupt
ACh–ADh Interrupt Controller Interrupt Controller Interrupt
B0h–B1h Interrupt Controller Interrupt Controller Interrupt
B2h–B3h Power Management Power Management Power Management
B4h–B5h Interrupt Controller Interrupt Controller Interrupt
B8h–B9h Interrupt Controller Interrupt Controller Interrupt
BCh–BDh Interrupt Controller Interrupt Controller Interrupt
C0h–D1h DMA Controller DMA Controller DMA
D2h–DDh RESERVED DMA Controller DMA
DEh–DFh DMA Controller DMA Controller DMA
F0h FERR# / Interrupt Controller FERR# / Interrupt Controller Processor I/F
170h–177h SATA Controller, PCI, or PCIe SATA Controller, PCI, or PCIe* SATA
1F0h–1F7h SATA Controller, PCI, or PCIe SATA Controller, PCI, or PCIe SATA
200h–207h Gameport Low Gameport Low Forwarded to LPC
208h–20Fh Gameport High Gameport High Forwarded to LPC
376h SATA Controller, PCI, or PCIe SATA Controller, PCI, or PCIe SATA
3F6h SATA Controller, PCI, or PCIe SATA Controller, PCI, or PCIe SATA
4D0h–4D1h Interrupt Controller Interrupt Controller Interrupt
CF9h Reset Generator Reset Generator Processor I/F
NOTE:
1. See Section 12.7.2
Datasheet 383
Register and Memory Mapping
9.3.2 Variable I/O Decode Ranges
Table 9-3 shows the Variable I/O Decode Ranges. They are set using Base Address
Registers (BARs) or other configuration bits in the various PCI configuration spaces.
The PNP software (PCI or ACPI) can use their configuration mechanisms to set and
adjust these values.
Warning: The Variable I/O Ranges should not be set to conflict with the Fixed I/O Ranges.
Unpredictable results if the configuration software allows conflicts to occur. The PCH
does not perform any checks for conflicts.
Table 9-3. Variable I/O Decode Ranges
Size
Range Name Mappable Target
(Bytes)
ACPI Anywhere in 64 KB I/O Space 64 Power Management
1. SATA Host
1. 16 or 32
IDE Bus Master Anywhere in 64 KB I/O Space Controller #1, #2
2. 16
2. IDE-R
1. SATA Host
Native IDE Command Anywhere in 64 KB I/O Space1 8 Controller #1, #2
2. IDE-R
1. SATA Host
Native IDE Control Anywhere in 64 KB I/O Space1 4 Controller #1, #2
2. IDE-R
SATA Host Controller
SATA Index/Data Pair Anywhere in 64 KB I/O Space 16
#1, #2
SMBus Anywhere in 64 KB I/O Space 32 SMB Unit
TCO 96 Bytes above ACPI Base 32 TCO Unit
GPIO Anywhere in 64 KB I/O Space 128 GPIO Unit
Parallel Port 3 Ranges in 64 KB I/O Space 83 LPC Peripheral
Serial Port 1 8 Ranges in 64 KB I/O Space 8 LPC Peripheral
Serial Port 2 8 Ranges in 64 KB I/O Space 8 LPC Peripheral
Floppy Disk Controller 2 Ranges in 64 KB I/O Space 8 LPC Peripheral
LAN Anywhere in 64 KB I/O Space 322 LAN Unit
LPC Generic 1 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral
LPC Generic 2 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral
LPC Generic 3 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral
LPC Generic 4 Anywhere in 64 KB I/O Space 4 to 256 LPC Peripheral
I/O Trapping Ranges Anywhere in 64 KB I/O Space 1 to 256 Trap on Backbone
I/O Base/
PCI Bridge Anywhere in 64 KB I/O Space PCI Bridge
Limit
I/O Base/ PCI Express Root Ports
PCI Express* Root Ports Anywhere in 64 KB I/O Space
Limit 1–8
KT Anywhere in 64 KB I/O Space 8 KT
NOTES:
1. All ranges are decoded directly from DMI. The I/O cycles will not be seen on PCI, except
the range associated with PCI bridge.
2. The LAN range is typically not used, as the registers can also be accessed using a memory
space.
3. There is also an alias 400h above the parallel port range that is used for ECP parallel ports.
384 Datasheet
Register and Memory Mapping
9.4 Memory Map
Table 9-4 shows (from the processor perspective) the memory ranges that the PCH
decodes. Cycles that arrive from DMI that are not directed to any of the internal
memory targets that decode directly from DMI will be driven out on PCI unless the
Subtractive Decode Policy bit is set (D31:F0:Offset 42h, bit 0).
PCI cycles generated by external PCI masters will be positively decoded unless they fall
in the PCI-to-PCI bridge memory forwarding ranges (those addresses are reserved for
PCI peer-to-peer traffic). If the cycle is not in the internal LAN controller’s range, it will
be forwarded up to DMI. Software must not attempt locks to the PCH memory-mapped
I/O ranges for EHCI and HPET. If attempted, the lock is not honored which means
potential deadlock conditions may occur.
Table 9-4. Memory Decode Ranges from Processor Perspective (Sheet 1 of 3)
Memory Range Target Dependency/Comments
0000 0000h–000D FFFFh
0010 0000h–TOM Main Memory TOM registers in Host controller
(Top of Memory)
000E 0000h–000E FFFFh LPC or SPI Bit 6 in BIOS Decode Enable register is set
000F 0000h–000F FFFFh LPC or SPI Bit 7 in BIOS Decode Enable register is set
_ _is controlled using APIC Range Select (ASEL) field
FEC_ _000h–FEC_ _040h IO(x) APIC inside PCH
and APIC Enable (AEN) bit
FEC1 0000h–FEC1 7FFF PCI Express* Port 1 PCI Express* Root Port 1 I/OxAPIC Enable (PAE) set
FEC1 8000h–FEC1 FFFFh PCI Express* Port 2 PCI Express* Root Port 2 I/OxAPIC Enable (PAE) set
FEC2 0000h–FEC2 7FFFh PCI Express* Port 3 PCI Express* Root Port 3 I/OxAPIC Enable (PAE) set
FEC2 8000h–FEC2 FFFFh PCI Express* Port 4 PCI Express* Root Port 4 I/OxAPIC Enable (PAE) set
FEC3 0000h–FEC3 7FFFh PCI Express* Port 5 PCI Express* Root Port 5 I/OxAPIC Enable (PAE) set
FEC3 8000h–FEC3 FFFFh PCI Express* Port 6 PCI Express* Root Port 6 I/OxAPIC Enable (PAE) set
FEC4 0000h–FEC4 7FFF PCI Express* Port 7 PCI Express* Root Port 7 I/OxAPIC Enable (PAE) set
FEC4 8000h–FEC4 FFFF PCI Express* Port 8 PCI Express* Root Port 8 I/OxAPIC Enable (PAE) set
FFC0 0000h–FFC7 FFFFh
LPC or SPI (or PCI)2 Bit 8 in BIOS Decode Enable register is set
FF80 0000h–FF87 FFFFh
FFC8 0000h–FFCF FFFFh
LPC or SPI (or PCI)2 Bit 9 in BIOS Decode Enable register is set
FF88 0000h–FF8F FFFFh
FFD0 0000h–FFD7 FFFFh
LPC or SPI (or PCI)2 Bit 10 in BIOS Decode Enable register is set
FF90 0000h–FF97 FFFFh
FFD8 0000h–FFDF FFFFh
LPC or SPI (or PCI)2 Bit 11 in BIOS Decode Enable register is set
FF98 0000h–FF9F FFFFh
FFE0 000h–FFE7 FFFFh
LPC or SPI (or PCI)2 Bit 12 in BIOS Decode Enable register is set
FFA0 0000h–FFA7 FFFFh
FFE8 0000h–FFEF FFFFh
LPC or SPI (or PCI)2 Bit 13 in BIOS Decode Enable register is set
FFA8 0000h–FFAF FFFFh
FFF0 0000h–FFF7 FFFFh
LPC or SPI (or PCI)2 Bit 14 in BIOS Decode Enable register is set
FFB0 0000h–FFB7 FFFFh
Datasheet 385
Register and Memory Mapping
Table 9-4. Memory Decode Ranges from Processor Perspective (Sheet 2 of 3)
Memory Range Target Dependency/Comments
Always enabled.
FFF8 0000h–FFFF FFFFh
LPC or SPI (or PCI)2 The top two 64 KB blocks of this range can be
FFB8 0000h–FFBF FFFFh swapped, as described in Section 9.4.1.
FF70 0000h–FF7F FFFFh
LPC or SPI (or PCI)2 Bit 3 in BIOS Decode Enable register is set
FF30 0000h–FF3F FFFFh
FF60 0000h–FF6F FFFFh
LPC or SPI (or PCI)2 Bit 2 in BIOS Decode Enable register is set
FF20 0000h–FF2F FFFFh
FF50 0000h–FF5F FFFFh
LPC or SPI (or PCI)2 Bit 1 in BIOS Decode Enable register is set
FF10 0000h–FF1F FFFFh
FF40 0000h–FF4F FFFFh
LPC or SPI (or PCI)2 Bit 0 in BIOS Decode Enable register is set
FF00 0000h–FF0F FFFFh
128 KB anywhere in 4 GB Integrated LAN Enable using BAR in D25:F0 (Integrated LAN
range Controller Controller MBARA)
Integrated LAN Enable using BAR in D25:F0 (Integrated LAN
4 KB anywhere in 4 GB range
Controller Controller MBARB)
1 KB anywhere in 4 GB range USB EHCI Controller #11 Enable using standard PCI mechanism (D29:F0)
1 KB anywhere in 4 GB range USB EHCI Controller #21 Enable using standard PCI mechanism (D26:F0)
64 KB anywhere in 4 GB
USB xHCI Controller Enable using standard PCI mechanism (D20:F0)
range
16 KB anywhere in 64-bit Intel® High Definition
Enable using standard PCI mechanism (D27:F0)
addressing space Audio Host Controller
BIOS determines the “fixed” location which is one of
High Precision Event
FED0 X000h–FED0 X3FFh four, 1-KB ranges where X (in the first column) is 0h,
Timers 1
1h, 2h, or 3h.
FED4 0000h–FED4 FFFFh TPM on LPC None
Memory Base/Limit anywhere
PCI Bridge Enable using standard PCI mechanism (D30:F0)
in 4 GB range
Prefetchable Memory Base/
Limit anywhere in 64-bit PCI Bridge Enable using standard PCI mechanism (D30:F0)
address range
LPC Generic Memory Range. Enable using setting
64 KB anywhere in 4 GB
LPC bit[0] of the LPC Generic Memory Range register
range
(D31:F0:offset 98h).
32 Bytes anywhere in 64-bit
SMBus Enable using standard PCI mechanism (D31:F3)
address range
2 KB anywhere above 64 KB AHCI memory-mapped registers. Enable using
SATA Host Controller #1
to 4 GB range standard PCI mechanism (D31:F2)
Memory Base/Limit anywhere PCI Express* Root Ports
Enable using standard PCI mechanism (D28: F 0-7)
in 4 GB range 1-8
Prefetchable Memory Base/
PCI Express Root Ports
Limit anywhere in 64-bit Enable using standard PCI mechanism (D28:F 0-7)
1-8
address range
4 KB anywhere in 64-bit Enable using standard PCI mechanism (D31:F6
Thermal Reporting
address range TBAR/TBARH)
386 Datasheet
Register and Memory Mapping
Table 9-4. Memory Decode Ranges from Processor Perspective (Sheet 3 of 3)
Memory Range Target Dependency/Comments
4 KB anywhere in 64-bit Enable using standard PCI mechanism (D31:F6
Thermal Reporting
address range TBARB/TBARBH)
16 Bytes anywhere in 64-bit
Intel® MEI #1, #2 Enable using standard PCI mechanism (D22:F 1:0)
address range
4 KB anywhere in 4 GB range KT Enable using standard PCI mechanism (D22:F3)
16 KB anywhere in 4 GB Root Complex Register Enable using setting bit[0] of the Root Complex Base
range Block (RCRB) Address register (D31:F0:offset F0h).
NOTES:
1. Software must not attempt locks to memory mapped I/O ranges for USB EHCI or High
Precision Event Timers. If attempted, the lock is not honored, which means potential
deadlock conditions may occur.
2. PCI is the target when the Boot BIOS Destination selection bits are set to 10b (Chipset
Config Registers:Offset 3401 bits 11:10). When PCI selected, the Firmware Hub Decode
Enable bits have no effect.
9.4.1 Boot-Block Update Scheme
The PCH supports a “Top Swap” mode that has the PCH swap the top block in the FWH
or SPI flash (the boot-block) with another location. This allows for safe update of the
boot-block (even if a power failure occurs). When the “Top Swap” Enable bit is set, the
PCH will invert A16 for cycles going to the upper two 64 KB blocks in the FWH or
appropriate address lines as selected in BIOS Boot-Block size soft strap for SPI.
Specifically for FHW, in this mode accesses to FFFF_0000h–FFFF_FFFFh are directed to
FFFE_0000h–FFFE_FFFFh and vice versa. When the Top Swap Enable bit is 0, the PCH
will not invert A16.
Specifically for SPI, in this mode the “Top Swap” behavior is as described below. When
the Top Swap Enable bit is 0, the PCH will not invert any address bit.
Table 9-5. SPI Mode Address Swapping
BIOS Boot-Block
Accesses to Being Directed to
size Value
000 (64 KB) FFFF_0000h–FFFF_FFFFh FFFE_0000h–FFFE_FFFFh and vice versa
001 (128 KB) FFFE_0000h–FFFF_FFFFh FFFC_0000h–FFFD_FFFFh and vice versa
010 (256 KB) FFFC_0000h–FFFF_FFFFh FFF8_0000h–FFFB_FFFFh and vice versa
011 (512 KB)1 FFF8_0000h–FFFF_FFFFh FFF0_0000h–FFF7_FFFFh and vice versa
100 (1 MB)1 FFF0_0000h–FFFF_FFFFh FFE0_0000h–FFEF_FFFFh and vice versa
101–111 Reserved Reserved
NOTES:
1. Only available in Server SKU.
Datasheet 387
Register and Memory Mapping
This bit is automatically set to 0 by RTCRST#, but not by PLTRST#.
The scheme is based on the concept that the top block is reserved as the “boot” block,
and the block immediately below the top block is reserved for doing boot-block
updates.
The algorithm is:
1. Software copies the top block to the block immediately below the top
2. Software checks that the copied block is correct. This could be done by performing
a checksum calculation.
3. Software sets the Top Swap bit. This will invert the appropriate address bits for the
cycles going to the FWH or SPI.
4. Software erases the top block
5. Software writes the new top block
6. Software checks the new top block
7. Software clears the Top Swap bit
If a power failure occurs at any point after step 3, the system will be able to boot from
the copy of the boot-block that is stored in the block below the top. This is because the
Top Swap bit is backed in the RTC well.
Note: The “Top Swap” mode may be forced by an external strapping option (See
Section 2.26). When top swap mode is forced in this manner, the Top Swap bit cannot
be cleared by software. A re-boot with the strap removed will be required to exit a
forced top-block swap mode.
Note: Top swap mode only affects accesses to the Firmware Hub space, not feature space for
FWH.
Note: The top swap mode has no effect on accesses below FFFE_0000h for FWH.
§§
388 Datasheet
Chipset Configuration Registers
10 Chipset Configuration Registers
This section describes all registers and base functionality that is related to chipset
configuration and not a specific interface (such as LPC, USB, or PCI Express*). It
contains the root complex register block that describes the behavior of the upstream
internal link.
This block is mapped into memory space, using the Root Complex Base Address (RCBA)
register of the PCI-to-LPC bridge. Accesses in this space must be limited to 32 bit (DW)
quantities. Burst accesses are not allowed.
10.1 Chipset Configuration Registers (Memory Space)
Note: Address locations that are not shown should be treated as Reserved (see Section 9.2
for details).
Table 10-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 1 of 2)
Offset Mnemonic Register Name Default Attribute
0400h–0403 RPC Root Port Configuration 0000000yh R/W, RO
Root Port Function Number and Hide for
0404h–0407h RPFN 76543210h R/W, R/WO
PCI Express Root Ports
Function Level Reset Pending Status
0408h–040Bh FLRSTAT 00000000h RO/V
Summary
1E00h–1E03h TRSR Trap Status 00000000h R/WC, RO
1E10h–1E17h TRCR Trapped Cycle 0000000000000000h RO
1E18h–1E1Fh TWDR Trapped Write Data 0000000000000000h RO
1E80h–1E87h IOTR0 I/O Trap Register 0 0000000000000000h R/W
1E88h–1E8Fh IOTR1 I/O Trap Register 1 0000000000000000h R/W
1E90h–1E97h IOTR2 I/O Trap Register 2 0000000000000000h R/W
1E98h–1E9Fh IOTR3 I/O Trap Register 3 0000000000000000h R/W
2014h–2017h V0CTL Virtual Channel 0 Resource Control 80000010h R/WL, RO
201Ah–201Bh V0STS Virtual Channel 0 Resource Status 0000h RO
R/W, RO,
2020h–2023h V1CTL Virtual Channel 1 Resource Control 00000000h
R/WL
2026h–2027h V1STS Virtual Channel 1 Resource Status 0000h RO
20ACh–20AFh REC Root Error Command 0000h R/W
21A4h–21A7h LCAP Link Capabilities 00012A42h RO, R/WO
21A8h–21A9h LCTL Link Control 0000h R/W
21AAh–21ABh LSTS Link Status 0041h RO
21B0h–21B1h DLCTL2 DMI Link Control 2 Register 0001h R/W, RO
2234h–2327h DMIC DMI Control 00000000h R/W, RO
3000h TCTL TCO Configuration 00h R/W
3100h–3103h D31IP Device 31 Interrupt Pin 03243200h R/W, RO
3104h–3107h D30IP Device 30 Interrupt Pin 00000000h RO
Datasheet 389
Chipset Configuration Registers
Table 10-1. Chipset Configuration Register Memory Map (Memory Space) (Sheet 2 of 2)
Offset Mnemonic Register Name Default Attribute
3108h–310Bh D29IP Device 29 Interrupt Pin 10004321h R/W
310Ch–310Fh D28IP Device 28 Interrupt Pin 00214321h R/W
3110h–3113h D27IP Device 27 Interrupt Pin 00000001h R/W
3114h–3117h D26IP Device 26 Interrupt Pin 30000321h R/W
3118h–311Bh D25IP Device 25 Interrupt Pin 00000001h R/W
3124h–3127h D22IP Device 22 Interrupt Pin 00004321h R/W
3128h–312Bh D20IP Device 20 Interrupt Pin 00000021h R/W
3140h–3141h D31IR Device 31 Interrupt Route 3210h R/W
3144h–3145h D29IR Device 29 Interrupt Route 3210h R/W
3146h–3147h D28IR Device 28 Interrupt Route 3210h R/W
3148h–3149h D27IR Device 27 Interrupt Route 3210h R/W
314Ch–314Dh D26IR Device 26 Interrupt Route 3210h R/W
3150h–3151h D25IR Device 25 Interrupt Route 3210h R/W
315Ch–315Dh D22IR Device 22 Interrupt Route 3210h R/W
3160h–3161h D20IR Device 20 Interrupt Route 3210h R/W
31FEh–31FFh OIC Other Interrupt Control 0000h R/W
3300h–3303h WADT_AC Wake Alarm Device Timer – AC FFFFFFFFh R/W
3304h–3307h WADT_DC Wake Alarm Device Timer – DC FFFFFFFFh R/W
3308h–330Bh WADT_EXP_AC Wake Alarm Device Expired Timer – AC FFFFFFFFh R/W
330Ch–330Fh WADT_EXP_DC Wake Alarm Device Expired Timer – DC FFFFFFFFh R/W
3310h–3313h PRSTS Power and Reset Status 05000000h RO, R/WC
3318h–331Bh PM_CFG Power Management Configuration 00000020h R/W
3328h–332Bh DEEP_S3_POL Deep Sx From S3 Power Policies 00000000h R/W
332Ch–332Fh DEEP_S4_POL Deep Sx From S4 Power Policies 00000000h R/W
3330h–3333h DEEP_S5_POL Deep Sx From S5 Power Policies 00000000h R/W
3334–3337h DSX_CFG Deep Sx Configuration Register 00000000h R/W
33C8h–33CBh PMSYNC_CFG PMSYNC Configuration 00000000h R/W
R/W,
3400h–3403h RC RTC Configuration 00000000h
R/WLO
3404h–3407h HPTC High Precision Timer Configuration 00000000h R/W
R/W,
3410h–3413h GCS General Control and Status 000000yy0h
R/WLO
3414h BUC Backed Up Control 00h R/W
3418h–341Bh FD Function Disable 00000000h R/W
341Ch–341Fh CG Clock Gating 00000000h R/W
3420h FDSW Function Disable SUS Well 00h R/W
Display Bus, Device and Function
3424h–3425h DISPBDF 00040010h R/W
Initialization
3428h–342Bh FD2 Function Disable 2 00000000h R/W
390 Datasheet
Chipset Configuration Registers
10.1.1 RPC—Root Port Configuration Register
Offset Address: 0400–0403h Attribute: R/W, RO
Default Value: 0000000yh (y = 00xxb) Size: 32-bit
Bit Description
31:0 Reserved. BIOS may write to this register, as needed.
10.1.2 RPFN—Root Port Function Number and Hide for PCI
Express* Root Ports Register
Offset Address: 0404–0407h Attribute: R/W, R/WO
Default Value: 76543210h Size: 32-bit
For the PCI Express root ports, the assignment of a function number to a root port is
not fixed. BIOS may re-assign the function numbers on a port by port basis. This
capability will allow BIOS to disable/hide any root port and still have functions 0 thru N-
1 where N is the total number of enabled root ports.
Port numbers will remain fixed to a physical root port.
The existing root port Function Disable registers operate on physical ports (not
functions).
Port Configuration (1x4, 4x1, and so on) is not affected by the logical function number
assignment and is associated with physical ports.
Note: The difference between hiding vs disabling a port is that a hidde4n port is not able to
claim downstream Config cycles only. Memory and I/O cycles are still claimed by that
hidden port. A disabled port is turned off and not able to claim downstream
Configuration, Memory and I/O cycles – it saves power. For PCIe ports that are
multiplexed out through Flexible I/O (so the alternative I/O technology, USB3 or SATA,
is chosen), the PCIe* port is disabled (not hidden). Function disable is covered in
Section 10.1.54.
Bit Description
Root Port 8 Config Hide (RP8CH)—R/W. This bit is used to hide the root port and
31 any devices behind it from being discovered by the OS. When set to 1, the root port
will not claim any downstream configuration transactions.
Root Port 8 Function Number (RP8FN)—R/WO. These bits set the function
30:28 number for PCI Express* Root Port 8. This root port function number must be a
unique value from the other root port function numbers.
Root Port 7 Config Hide (RP7CH)—R/W. This bit is used to hide the root port and
27 any devices behind it from being discovered by the OS. When set to 1, the root port
will not claim any downstream configuration transactions.
Root Port 7 Function Number (RP7FN)—R/WO. These bits set the function
26:24 number for PCI Express Root Port 7. This root port function number must be a
unique value from the other root port function numbers.
Root Port 6 Config Hide (RP6CH)—R/W. This bit is used to hide the root port and
23 any devices behind it from being discovered by the OS. When set to 1, the root port
will not claim any downstream configuration transactions.
Root Port 6 Function Number (RP6FN)—R/WO. These bits set the function
22:20 number for PCI Express Root Port 6. This root port function number must be a
unique value from the other root port function numbers.
Datasheet 391
Chipset Configuration Registers
Bit Description
Root Port 5 Config Hide (RP5CH)—R/W. This bit is used to hide the root port and
19 any devices behind it from being discovered by the OS. When set to 1, the root port
will not claim any downstream configuration transactions.
Root Port 5 Function Number (RP5FN)—R/WO. These bits set the function
18:16 number for PCI Express Root Port 5. This root port function number must be a
unique value from the other root port function numbers.
Root Port 4 Config Hide (RP4CH)—R/W. This bit is used to hide the root port and
15 any devices behind it from being discovered by the OS. When set to 1, the root port
will not claim any downstream configuration transactions.
Root Port 4 Function Number (RP4FN)—R/WO. These bits set the function
14:12 number for PCI Express Root Port 4. This root port function number must be a
unique value from the other root port function numbers.
Root Port 3 Config Hide (RP3CH)—R/W. This bit is used to hide the root port and
11 any devices behind it from being discovered by the OS. When set to 1, the root port
will not claim any downstream configuration transactions.
Root Port 3 Function Number (RP3FN)—R/WO. These bits set the function
10:8 number for PCI Express Root Port 3. This root port function number must be a
unique value from the other root port function numbers.
Root Port 2 Config Hide (RP2CH)—R/W. This bit is used to hide the root port and
7 any devices behind it from being discovered by the OS. When set to 1, the root port
will not claim any downstream configuration transactions.
Root Port 2 Function Number (RP2FN)—R/WO. These bits set the function
6:4 number for PCI Express* Root Port 2. This root port function number must be a
unique value from the other root port function numbers.
Root Port 1 Config Hide (RP1CH)—R/W. This bit is used to hide the root port and
3 any devices behind it from being discovered by the OS. When set to 1, the root port
will not claim any downstream configuration transactions.
Root Port 1 Function Number (RP1FN)—R/WO. These bits set the function
2:0 number for PCI Express Root Port 1. This root port function number must be a
unique value from the other root port function numbers.
392 Datasheet
Chipset Configuration Registers
10.1.3 FLRSTAT—Function Level Reset Pending Status Register
Offset Address: 0408–040Bh Attribute: RO/V
Default Value: 00000000h Size: 32-bit
Bit Description
31:24 Reserved
FLR Pending Status for D29:F0, EHCI #1—RO/V.
23 0 = Function Level Reset is not pending.
1 = Function Level Reset is pending.
22:16 Reserved
FLR Pending Status for D26:F0, EHCI #2—RO/V.
15 0 = Function Level Reset is not pending.
1 = Function Level Reset is pending.
14:0 Reserved
10.1.4 TRSR—Trap Status Register
Offset Address: 1E00–1E03h Attribute: R/WC, RO
Default Value: 00000000h Size: 32-bit
Bit Description
31:4 Reserved
Cycle Trap SMI# Status (CTSS)—R/WC. These bits are set by hardware when the
corresponding Cycle Trap register is enabled and a matching cycle is received (and
trapped). These bits are OR’ed together to create a single status bit in the Power
Management register space.
3:0 The SMI# and trapping must be enabled in order to set these bits.
These bits are set before the completion is generated for the trapped cycle, thereby
ensuring that the processor can enter the SMI# handler when the instruction
completes. Each status bit is cleared by writing a 1 to the corresponding bit location
in this register.
Datasheet 393
Chipset Configuration Registers
10.1.5 TRCR—Trapped Cycle Register
Offset Address: 1E10–1E17h Attribute: RO
Default Value: 0000000000000000h Size: 64-bit
This register saves information about the I/O Cycle that was trapped and generated the
SMI# for software to read.
Bit Description
63:25 Reserved
Read/Write# (RWI)—RO.
24 0 = Trapped cycle was a write cycle.
1 = Trapped cycle was a read cycle.
23:20 Reserved
Active-high Byte Enables (AHBE)—RO. This is the DWord-aligned byte enables
19:16 associated with the trapped cycle. A 1 in any bit location indicates that the
corresponding byte is enabled in the cycle.
Trapped I/O Address (TIOA)—RO. This is the DWord-aligned address of the
15:2
trapped cycle.
1:0 Reserved
10.1.6 TWDR—Trapped Write Data Register
Offset Address: 1E18–1E1Fh Attribute: RO
Default Value: 0000000000000000h Size: 64-bit
This register saves the data from I/O write cycles that are trapped for software to read.
Bit Description
63:32 Reserved
Trapped I/O Data (TIOD)—RO. DWord of I/O write data. This field is undefined
31:0
after trapping a read cycle.
394 Datasheet
Chipset Configuration Registers
10.1.7 IOTRn—I/O Trap Register (0–3)
Offset Address: 1E80–1E87h Register 0 Attribute: R/W
1E88–1E8Fh Register 1
1E90–1E97h Register 2
1E98–1E9Fh Register 3
Default Value: 0000000000000000h Size: 64-bit
These registers are used to specify the set of I/O cycles to be trapped and to enable
this functionality.
Bit Description
63:50 Reserved
Read/Write Mask (RWM)—R/W.
49 0 = The cycle must match the type specified in bit 48.
1 = Trapping logic will operate on both read and write cycles.
Read/Write# (RWIO)—R/W.
0 = Write
48
1 = Read
NOTE: The value in this field does not matter if bit 49 is set.
47:40 Reserved
Byte Enable Mask (BEM)—R/W. A 1 in any bit position indicates that any value in
39:36 the corresponding byte enable bit in a received cycle will be treated as a match. The
corresponding bit in the Byte Enables field, below, is ignored.
35:32 Byte Enables (TBE)—R/W. Active-high DWord-aligned byte enables.
31:24 Reserved
Address[7:2] Mask (ADMA)—R/W. A 1 in any bit position indicates that any value
in the corresponding address bit in a received cycle will be treated as a match. The
23:18 corresponding bit in the Address field, below, is ignored. The mask is only provided
for the lower 6 bits of the DWord address, allowing for traps on address ranges up to
256 bytes in size.
17:16 Reserved
15:2 I/O Address[15:2] (IOAD)—R/W. DWord-aligned address
1 Reserved
Trap and SMI# Enable (TRSE)—R/W.
0 0 = Trapping and SMI# logic disabled.
1 = The trapping logic specified in this register is enabled.
Datasheet 395
Chipset Configuration Registers
10.1.8 V0CTL—Virtual Channel 0 Resource Control Register
Offset Address: 2014–2017h Attribute: R/WL, RO
Default Value: 80000010h Size: 32-bit
Bit Description
Virtual Channel Enable (EN)—RO. Always set to 1. VC0 is always enabled and
31
cannot be disabled.
30:27 Reserved
Virtual Channel Identifier (ID)—RO. Indicates the ID to use for this virtual
26:24
channel.
23:16 Reserved
Extended TC/VC Map (ETVM)—R/WL. Defines the upper 8-bits of the VC0 16-bit
15:10 TC/VC mapping registers. These registers use the PCI Express reserved TC[3] traffic
class bit. These bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is set.
9:7 Reserved
Transaction Class / Virtual Channel Map (TVM)—R/WL. Indicates which
transaction classes are mapped to this virtual channel. When a bit is set, this
6:1
transaction class is mapped to the virtual channel. These bits are locked if the
TCLOCKDN bit (RCBA+0050h:bit 31) is set.
0 Reserved
10.1.9 V0STS—Virtual Channel 0 Resource Status Register
Offset Address: 201A–201Bh Attribute: RO
Default Value: 0000h Size: 16-bit
Bit Description
15:2 Reserved
VC Negotiation Pending (NP)—RO. When set, this bit indicates the virtual channel
1
is still being negotiated with ingress ports.
0 Reserved
396 Datasheet
Chipset Configuration Registers
10.1.10 V1CTL—Virtual Channel 1 Resource Control Register
Offset Address: 2020–2023h Attribute: R/W, RO, R/WL
Default Value: 00000000h Size: 32-bit
Bit Description
Virtual Channel Enable (EN)—R/W. Enables the VC when set. Disables the VC
31
when cleared.
30:28 Reserved
Virtual Channel Identifier (ID)—R/W. Indicates the ID to use for this virtual
27:24
channel.
23:16 Reserved
Extended TC/VC Map (ETVM)—R/WL. Defines the upper 8-bits of the VC0 16-bit
TC/VC mapping registers. These registers use the PCI Express* reserved TC[3]
15:10
traffic class bit. These bits are locked if the TCLOCKDN bit (RCBA+0050h:bit 31) is
set.
9:8 Reserved
Transaction Class / Virtual Channel Map (TVM)—R/WL. Indicates which
transaction classes are mapped to this virtual channel. When a bit is set, this
7:1
transaction class is mapped to the virtual channel. These bits are locked if the
TCLOCKDN bit (RCBA+0050h:bit 31) is set.
0 Reserved
10.1.11 V1STS—Virtual Channel 1 Resource Status Register
Offset Address: 2026–2027h Attribute: RO
Default Value: 0000h Size: 16-bit
Bit Description
15:2 Reserved
VC Negotiation Pending (NP)—RO. When set, this bit indicates the virtual channel
1
is still being negotiated with ingress ports.
0 Reserved
10.1.12 REC—Root Error Command Register
Offset Address: 20AC–20AFh Attribute: R/W
Default Value: 0000h Size: 32-bit
Bit Description
Drop Poisoned Downstream Packets (DPDP)—R/W. Determines how
downstream packets on DMI are handled that are received with the EP field set,
indicating poisoned data:
0 = Packets are forwarded downstream without forcing the UT field set.
31
1 = This packet and all subsequent packets with data received on DMI for any VC will
have their Unsupported Transaction (UT) field set causing them to master Abort
downstream. Packets without data such as memory, I/O and config read requests
are allowed to proceed.
30:0 Reserved
Datasheet 397
Chipset Configuration Registers
10.1.13 LCAP—Link Capabilities Register
Offset Address: 21A4–21A7h Attribute: R/WO, RO
Default Value: 00012A42h Size: 32-bit
Bit Description
31:18 Reserved
L1 Exit Latency (EL1)—R/WO.
000b = Less than 1 µs
001b = 1 µs to less than 2 µs
010b = 2 µs to less than 4 µs
17:15 011b = 4 µs to less than 8 µs
100b = 8 µs to less than 16 µs
101b = 16 µs to less than 32 µs
110b = 32 µs to 64 µs
111b = More than 64 µs
L0s Exit Latency (EL0)—R/W. This field is update-able by BIOS. The default value
010b indicates that L0s exit latency is between 128 ns to less than 256 ns,
assuming a common-clock configuration between the processor and the PCH. If a
14:12 unique clock value is used, BIOS should update this field to 100b, indicating a L0s
exit latency between 512 ns to 1 us. DMI only supports a common clock
configuration. When BIOS sets this field, it must also update DMI’s L0s Entry
Control field at RCBA +2344h.
Active State Link PM Support (APMS)—R/W. Indicates the level of ASPM
support on DMI.
00 = Reserved
11:10
01 = L0s entry supported
10 = Reserved
11 = L0s and L1 entry supported
Maximum Link Width (MLW)—RO. Indicates the link width is set to the
9:4
maximum of 4 lanes.
Maximum Link Speed (MLS)—RO. The value 0001b indicates that only DMI Gen1
3:0 speed, 2.5 GT/s, is supported. The value 0010b indicates that DMI Gen2 speed, 5.0
GT/s, is supported (2.5GT/s is also supported in this setting).
398 Datasheet
Chipset Configuration Registers
10.1.14 LCTL—Link Control Register
Offset Address: 21A8–21A9h Attribute: R/W
Default Value: 0000h Size: 16-bit
Bit Description
15:8 Reserved
Extended Synch (ES)—R/W. When set, this bit forces extended transmission of FTS
7 ordered sets when exiting L0s prior to entering L0 and extra TS1 sequences at exit
from L1 prior to entering L0.
6:2 Reserved
Active State Link PM Control (ASPM)—R/W. Indicates whether DMI should enter
L0s, L1, or both.
00 = Disabled
1:0
01 = L0s entry enabled
10 = L1 entry enabled
11 = L0s and L1 entry enabled
10.1.15 LSTS—Link Status Register
Offset Address: 21AA–21ABh Attribute: RO
Default Value: 0041h Size: 16-bit
Bit Description
15:10 Reserved
9:4 Negotiated Link Width (NLW)—RO. Negotiated link width is x4 (000100b).
Current Link Speed (LS)—RO.
3:0 0001b = 2.5 GT/s
0010b = 5.0 GT/s
10.1.16 DLCTL2—DMI Link Control 2 Register
Offset Address: 21B0–21B1h Attribute: R/W, RO
Default Value: 0001h Size: 16-bit
Bit Description
15:4 Reserved
3:0 DLCTL2 Field 1—R/W. BIOS may program this field.
Datasheet 399
Chipset Configuration Registers
10.1.17 DMIC—DMI Control Register
Offset Address: 2234–2237h Attribute: R/W, RO
Default Value: 00000000h Size: 32-bit
10.1.18 DMC—DMI Miscellaneous Control Register
Bit Description
31:2 Reserved
1:0 DMI Clock Gate Enable (DMICGEN)—R/W. BIOS must program this field to 11b.
Offset Address: 2304–2307h Attribute: R/W
Default Value: 00000000h Size: 32-bit
31:0 DMC Field 1—R/W. BIOS must program this field to C0388400h.
10.1.19 TCTL—TCO Configuration Register
Offset Address: 3000h Attribute: R/W
Default Value: 00h Size: 8-bit
Bit Description
TCO IRQ Enable (IE)—R/W.
7 0 = TCO IRQ is disabled.
1 = TCO IRQ is enabled, as selected by the TCO_IRQ_SEL field.
6:3 Reserved
TCO IRQ Select (IS)—R/W. Specifies on which IRQ the TCO will internally appear. If
not using the APIC, the TCO interrupt must be routed to IRQ9–11, and that interrupt
is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If
using the APIC, the TCO interrupt can also be mapped to IRQ20–23, and can be
shared with other interrupt.
000 = IRQ 9
001 = IRQ 10
010 = IRQ 11
2:0 011 = Reserved
100 = IRQ 20 (only if APIC enabled)
101 = IRQ 21 (only if APIC enabled)
110 = IRQ 22 (only if APIC enabled)
111 = IRQ 23 (only if APIC enabled)
When setting the these bits, the IE bit should be cleared to prevent glitching.
When the interrupt is mapped to APIC interrupts 9, 10, or 11, the APIC should be
programmed for active-high reception. When the interrupt is mapped to APIC
interrupts 20 through 23, the APIC should be programmed for active-low reception.
400 Datasheet
Chipset Configuration Registers
10.1.20 D31IP—Device 31 Interrupt Pin Register
Offset Address: 3100–3103h Attribute: R/W, RO
Default Value: 03243200h Size: 32-bit
Bit Description
31:28 Reserved
Thermal Throttle Pin (TTIP)—R/W. Indicates which pin the Thermal Throttle
controller drives as its interrupt.
0h = No interrupt
27:24 1h = INTA#
2h = INTB#
3h = INTC# (Default)
4h = INTD#
5h–Fh = Reserved
SATA Pin 2 (SIP2)—R/W. Indicates which pin the SATA controller 2 drives as its
interrupt.
0h = No interrupt
23:20 1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
19:16 Reserved
SMBus Pin (SMIP)—R/W. Indicates which pin the SMBus controller drives as its
interrupt.
0h = No interrupt
1h = INTA#
15:12
2h = INTB#
3h = INTC# (Default)
4h = INTD#
5h–Fh = Reserved
SATA Pin (SIP)—R/W. Indicates which pin the SATA controller drives as its
interrupt.
0h = No interrupt
1h = INTA#
11:8
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
7:4 Reserved
LPC Bridge Pin (LIP)—RO. Currently, the LPC bridge does not generate an
3:0
interrupt, so this field is read-only and 0h.
Datasheet 401
Chipset Configuration Registers
10.1.21 D30IP—Device 30 Interrupt Pin Register
Offset Address: 3104–3107h Attribute: RO
Default Value: 00000000h Size: 32-bit
Bit Description
31:0 Reserved
10.1.22 D29IP—Device 29 Interrupt Pin Register
Offset Address: 3108–310Bh Attribute: R/W
Default Value: 10004321h Size: 32-bit
Bit Description
31:4 Reserved
EHCI #1 Pin (E1P)—R/W. Indicates which pin the EHCI controller #1 drives as its
interrupt, if controller exists.
0h = No interrupt
1h = INTA# (Default)
3:0 2h = INTB#
3h = INTC#
4h = INTD#
5h–7h = Reserved
NOTE: EHCI Controller #1 is mapped to Device 29 Function 0.
10.1.23 D28IP—Device 28 Interrupt Pin Register
Offset Address: 310C–310Fh Attribute: R/W
Default Value: 00214321h Size: 32-bit
Bit Description
PCI Express* #8 Pin (P8IP)—R/W. Indicates which pin the PCI Express* port #8
drives as its interrupt.
0h = No interrupt
1h = INTA#
31:28
2h = INTB#
3h = INTC#
4h = INTD# (Default)
5h–7h = Reserved
PCI Express #7 Pin (P7IP)—R/W. Indicates which pin the PCI Express port #7
drives as its interrupt.
0h = No interrupt
27:24 1h = INTA#
2h = INTB#
3h = INTC# (Default)
4h = INTD#
5h–7h = Reserved
402 Datasheet
Chipset Configuration Registers
Bit Description
PCI Express* #6 Pin (P6IP)—R/W. Indicates which pin the PCI Express* port #6
drives as its interrupt.
0h = No interrupt
1h = INTA#
23:20
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–7h = Reserved
PCI Express #5 Pin (P5IP)—R/W. Indicates which pin the PCI Express port #5
drives as its interrupt.
0h = No interrupt
19:16 1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–7h = Reserved
PCI Express #4 Pin (P4IP)—R/W. Indicates which pin the PCI Express* port #4
drives as its interrupt.
0h = No interrupt
1h = INTA#
15:12
2h = INTB#
3h = INTC#
4h = INTD# (Default)
5h–7h = Reserved
PCI Express #3 Pin (P3IP)—R/W. Indicates which pin the PCI Express port #3
drives as its interrupt.
0h = No interrupt
11:8 1h = INTA#
2h = INTB#
3h = INTC# (Default)
4h = INTD#
5h–7h = Reserved
PCI Express #2 Pin (P2IP)—R/W. Indicates which pin the PCI Express port #2
drives as its interrupt.
0h = No interrupt
1h = INTA#
7:4
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–7h = Reserved
PCI Express #1 Pin (P1IP)—R/W. Indicates which pin the PCI Express port #1
drives as its interrupt.
0h = No interrupt
1h = INTA# (Default)
3:0
2h = INTB#
3h = INTC#
4h = INTD#
5h–7h = Reserved
Datasheet 403
Chipset Configuration Registers
10.1.24 D27IP—Device 27 Interrupt Pin Register
Offset Address: 3110–3113h Attribute: R/W
Default Value: 00000001h Size: 32-bit
Bit Description
31:4 Reserved
Intel® High Definition Audio Pin (ZIP)—R/W. Indicates which pin the Intel High
Definition Audio controller drives as its interrupt.
0h = No interrupt
1h = INTA# (Default)
3:0
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
10.1.25 D26IP—Device 26 Interrupt Pin Register
Offset Address: 3114–3117h Attribute: R/W
Default Value: 30000321h Size: 32-bit
Bit Description
31:4 Reserved
EHCI #2 Pin (E2P)—R/W. Indicates which pin EHCI controller #2 drives as its
interrupt, if controller exists.
0h = No Interrupt
1h = INTA# (Default)
3:0 2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserve
NOTE: EHCI Controller #2 is mapped to Device 26 Function 0.
10.1.26 D25IP—Device 25 Interrupt Pin Register
Offset Address: 3118–311Bh Attribute: R/W
Default Value: 00000001h Size: 32-bit
Bit Description
31:4 Reserved
GbE LAN Pin (LIP)—R/W. Indicates which pin the internal GbE LAN controller drives
as its interrupt
0h = No Interrupt
3:0 1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
404 Datasheet
Chipset Configuration Registers
10.1.27 D22IP—Device 22 Interrupt Pin Register
Offset Address: 3124–3127h Attribute: R/W
Default Value: 00004321h Size: 32-bit
Bit Description
31:16 Reserved
KT Pin (KTIP)—R/W. Indicates which pin the Keyboard text PCI functionality drives
as its interrupt
0h = No Interrupt
15:12 1h = INTA#
2h = INTB#
3h = INTC#
4h = INTD# (Default)
5h–Fh = Reserved
IDE-R Pin (IDERIP)—R/W. Indicates which pin the IDE Redirect PCI functionality
drives as its interrupt
0h = No Interrupt
1h = INTA#
11:8
2h = INTB#
3h = INTC# (Default)
4h = INTD#
5h–Fh = Reserved
Intel® MEI #2 Pin (MEI2IP)—R/W. Indicates which pin the Management Engine
Interface #2 drives as its interrupt
0h = No Interrupt
7:4 1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
Intel® MEI #1 Pin (MEI1IP)—R/W. Indicates which pin the Management Engine
Interface controller #1 drives as its interrupt
0h = No Interrupt
1h = INTA# (Default)
3:0
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
10.1.28 D20IP—Device 20 Interrupt Pin Register
Offset Address: 3128–312bh Attribute: R/W
Default Value: 00000021h Size: 32-bit
Bit Description
31:4 Reserved
xHCI Pin (XHCIIP)—R/W. Indicates which pin the xHCI drives as its interrupt
0h = No Interrupt
1h = INTA# (Default)
3:0 2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
Datasheet 405
Chipset Configuration Registers
10.1.29 D31IR—Device 31 Interrupt Route Register
Offset Address: 3140–3141h Attribute: R/W
Default Value: 3210h Size: 16-bit
Bit Description
15 Reserved
Interrupt D Pin Route (IDR)—R/W. Indicates which physical pin on the PCH is
connected to the INTD# pin reported for device 31 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC#
14:12
3h = PIRQD# (Default)
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
11 Reserved
Interrupt C Pin Route (ICR)—R/W. Indicates which physical pin on the PCH is
connected to the INTC# pin reported for device 31 functions.
0h = PIRQA#
1h = PIRQB#
10:8 2h = PIRQC# (Default)
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
7 Reserved
Interrupt B Pin Route (IBR)—R/W. Indicates which physical pin on the PCH is
connected to the INTB# pin reported for device 31 functions.
0h = PIRQA#
1h = PIRQB# (Default)
6:4 2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
3 Reserved
Interrupt A Pin Route (IAR)—R/W. Indicates which physical pin on the PCH is
connected to the INTA# pin reported for device 31 functions.
0h = PIRQA# (Default)
1h = PIRQB#
2:0 2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
406 Datasheet
Chipset Configuration Registers
10.1.30 D30IR—Device 30 Interrupt Route Register
Offset Address: 3142–3143h Attribute: RO
Default Value: 0000h Size: 16-bit
Bit Description
15:0 Reserved. No interrupts generated from Device 30.
10.1.31 D29IR—Device 29 Interrupt Route Register
Offset Address: 3144–3145h Attribute: R/W
Default Value: 3210h Size: 16-bit
Bit Description
15 Reserved
Interrupt D Pin Route (IDR)—R/W. Indicates which physical pin on the PCH is
connected to the INTD# pin reported for device 29 functions.
0h = PIRQA#
1h = PIRQB#
14:12 2h = PIRQC#
3h = PIRQD# (Default)
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
11 Reserved
Interrupt C Pin Route (ICR)—R/W. Indicates which physical pin on the PCH is
connected to the INTC# pin reported for device 29 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC# (Default)
10:8
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
7 Reserved
Interrupt B Pin Route (IBR)—R/W. Indicates which physical pin on the PCH is
connected to the INTB# pin reported for device 29 functions.
0h = PIRQA#
1h = PIRQB# (Default)
6:4 2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
3 Reserved
Interrupt A Pin Route (IAR)—R/W. Indicates which physical pin on the PCH is
connected to the INTA# pin reported for device 29 functions.
0h = PIRQA# (Default)
1h = PIRQB#
2h = PIRQC#
2:0
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
Datasheet 407
Chipset Configuration Registers
10.1.32 D28IR—Device 28 Interrupt Route Register
Offset Address: 3146–3147h Attribute: R/W
Default Value: 3210h Size: 16-bit
Bit Description
15 Reserved
Interrupt D Pin Route (IDR)—R/W. Indicates which physical pin on the PCH is
connected to the INTD# pin reported for device 28 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC#
14:12
3h = PIRQD# (Default)
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
11 Reserved
Interrupt C Pin Route (ICR)—R/W. Indicates which physical pin on the PCH is
connected to the INTC# pin reported for device 28 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC# (Default)
10:8
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
7 Reserved
Interrupt B Pin Route (IBR)—R/W. Indicates which physical pin on the PCH is
connected to the INTB# pin reported for device 28 functions.
0h = PIRQA#
1h = PIRQB# (Default)
2h = PIRQC#
6:4
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
3 Reserved
Interrupt A Pin Route (IAR)—R/W. Indicates which physical pin on the PCH is
connected to the INTA# pin reported for device 28 functions.
0h = PIRQA# (Default)
1h = PIRQB#
2:0 2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
408 Datasheet
Chipset Configuration Registers
10.1.33 D27IR—Device 27 Interrupt Route Register
Offset Address: 3148–3149h Attribute: R/W
Default Value: 3210h Size: 16-bit
Bit Description
15 Reserved
Interrupt D Pin Route (IDR)—R/W. Indicates which physical pin on the PCH is
connected to the INTD# pin reported for device 27 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC#
14:12
3h = PIRQD# (Default)
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
11 Reserved
Interrupt C Pin Route (ICR)—R/W. Indicates which physical pin on the PCH is
connected to the INTC# pin reported for device 27 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC# (Default)
10:8
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
7 Reserved
Interrupt B Pin Route (IBR)—R/W. Indicates which physical pin on the PCH is
connected to the INTB# pin reported for device 27 functions.
0h = PIRQA#
1h = PIRQB# (Default)
2h = PIRQC#
6:4
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
3 Reserved
Interrupt A Pin Route (IAR)—R/W. Indicates which physical pin on the PCH is
connected to the INTA# pin reported for device 27 functions.
0h = PIRQA# (Default)
1h = PIRQB#
2:0 2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
Datasheet 409
Chipset Configuration Registers
10.1.34 D26IR—Device 26 Interrupt Route Register
Offset Address: 314C–314Dh Attribute: R/W
Default Value: 3210h Size: 16-bit
Bit Description
15 Reserved
Interrupt D Pin Route (IDR)—R/W. Indicates which physical pin on the PCH is
connected to the INTD# pin reported for device 26 functions:
0h = PIRQA#
1h = PIRQB#
2h = PIRQC#
14:12
3h = PIRQD# (Default)
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
11 Reserved
Interrupt C Pin Route (ICR)—R/W. Indicates which physical pin on the PCH is
connected to the INTC# pin reported for device 26 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC# (Default)
10:8
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
7 Reserved
Interrupt B Pin Route (IBR)—R/W. Indicates which physical pin on the PCH is
connected to the INTB# pin reported for device 26 functions.
0h = PIRQA#
1h = PIRQB# (Default)
2h = PIRQC#
6:4
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
3 Reserved
Interrupt A Pin Route (IAR)—R/W. Indicates which physical pin on the PCH is
connected to the INTA# pin reported for device 26 functions.
0h = PIRQA# (Default)
1h = PIRQB#
2:0 2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
410 Datasheet
Chipset Configuration Registers
10.1.35 D25IR—Device 25 Interrupt Route Register
Offset Address: 3150–3151h Attribute: R/W
Default Value: 3210h Size: 16-bit
Bit Description
15 Reserved
Interrupt D Pin Route (IDR):—R/W. Indicates which physical pin on the PCH is
connected to the INTD# pin reported for device 25 functions:
0h = PIRQA#
1h = PIRQB#
2h = PIRQC#
14:12
3h = PIRQD# (Default)
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
11 Reserved
Interrupt C Pin Route (ICR)—R/W. Indicates which physical pin on the PCH is
connected to the INTC# pin reported for device 25 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC# (Default)
10:8
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
7 Reserved
Interrupt B Pin Route (IBR)—R/W. Indicates which physical pin on the PCH is
connected to the INTB# pin reported for device 25 functions.
0h = PIRQA#
1h = PIRQB# (Default)
2h = PIRQC#
6:4
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
3 Reserved
Interrupt A Pin Route (IAR)—R/W. Indicates which physical pin on the PCH is
connected to the INTA# pin reported for device 25 functions.
0h = PIRQA# (Default)
1h = PIRQB#
2:0 2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
Datasheet 411
Chipset Configuration Registers
10.1.36 D22IR—Device 22 Interrupt Route Register
Offset Address: 315C–315Dh Attribute: R/W
Default Value: 3210h Size: 16-bit
Bit Description
15 Reserved
Interrupt D Pin Route (IDR):—R/W. Indicates which physical pin on the PCH is
connected to the INTD# pin reported for device 22 functions:
0h = PIRQA#
1h = PIRQB#
2h = PIRQC#
14:12
3h = PIRQD# (Default)
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
11 Reserved
Interrupt C Pin Route (ICR)—R/W. Indicates which physical pin on the PCH is
connected to the INTC# pin reported for device 22 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC# (Default)
10:8
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
7 Reserved
Interrupt B Pin Route (IBR)—R/W. Indicates which physical pin on the PCH is
connected to the INTB# pin reported for device 22 functions.
0h = PIRQA#
1h = PIRQB# (Default)
2h = PIRQC#
6:4
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
3 Reserved
Interrupt A Pin Route (IAR)—R/W. Indicates which physical pin on the PCH is
connected to the INTA# pin reported for device 22 functions.
0h = PIRQA# (Default)
1h = PIRQB#
2:0 2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
412 Datasheet
Chipset Configuration Registers
10.1.37 D20IR—Device 20 Interrupt Route Register
Offset Address: 3160–3161h Attribute: R/W
Default Value: 3210h Size: 16-bit
Bit Description
15 Reserved
Interrupt D Pin Route (IDR)—R/W. Indicates which physical pin on the PCH is
connected to the INTD# pin reported for device 20 functions:
0h = PIRQA#
1h = PIRQB#
2h = PIRQC#
14:12
3h = PIRQD# (Default)
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
11 Reserved
Interrupt C Pin Route (ICR)—R/W. Indicates which physical pin on the PCH is
connected to the INTC# pin reported for device 20 functions.
0h = PIRQA#
1h = PIRQB#
2h = PIRQC# (Default)
10:8
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
7 Reserved
Interrupt B Pin Route (IBR)—R/W. Indicates which physical pin on the PCH is
connected to the INTB# pin reported for device 20 functions.
0h = PIRQA#
1h = PIRQB# (Default)
2h = PIRQC#
6:4
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
3 Reserved
Interrupt A Pin Route (IAR)—R/W. Indicates which physical pin on the PCH is
connected to the INTA# pin reported for device 20 functions.
0h = PIRQA# (Default)
1h = PIRQB#
2:0 2h = PIRQC#
3h = PIRQD#
4h = PIRQE#
5h = PIRQF#
6h = PIRQG#
7h = PIRQH#
Datasheet 413
Chipset Configuration Registers
10.1.38 OIC—Other Interrupt Control Register
Offset Address: 31FE–31FFh Attribute: R/W
Default Value: 0000h Size: 16-bit
Bit Description
15:10 Reserved
Coprocessor Error Enable (CEN)—R/W.
0 = FERR# will not generate IRQ13 nor IGNNE#.
9
1 = If FERR# is low, the PCH generates IRQ13 internally and holds it until an I/O port
F0h write. It will also drive IGNNE# active.
APIC Enable (AEN)—R/W.
0 = The internal IOxAPIC is disabled.
8 1 = Enables the internal IOxAPIC and its address decode.
NOTE: Software should read this register after modifying APIC enable bit prior to
access to the IOxAPIC address range.
APIC Range Select (ASEL)—R/W. These bits define address bits 19:12 for the
IOxAPIC range. The default value of 00h enables compatibility with prior PCH products
7:0
as an initial value. This value must not be changed unless the IOxAPIC Enable bit is
cleared.
NOTE: FEC1_0000h–FEC3_FFFFh is allocated to PCIe when I/OxAPIC Enable (PAE) bit is set.
10.1.39 WADT_AC—Wake Alarm Device Timer – AC Register
Offset Address: 3300–3303h Attribute: R/W
Default Value: FFFFFFFFh Size: 32-bit
Bit Description
Wake Alarm Device Timer Value for AC Mode (WADT_AC_VAL): R/W. This field
contains the 32-bit wake alarm device timer value (1 second granularity) for AC
power. The timer begins decrementing when written to a value other than FFFFFFFFh
(regardless of the power source when the write occurs). Upon counting down to 0:
31:0 • If on AC power, GPE0_STS.WADT_STS will be set. This status bit being set will generate a
host wake if GPE0_EN.WADT_EN is ‘1’.
• If power source is DC at this time, the status bit is not set. However, if AC power
subsequently returns to the platform, the AC Expired Timer begins running. Refer to
WADT_EXP_AC for more details.
• The timer returns to its default value of FFFFFFFFh.
414 Datasheet
Chipset Configuration Registers
10.1.40 WADT_DC—Wake Alarm Device Timer – DC Register
Offset Address: 3304–3307h Attribute: R/W
Default Value: FFFFFFFFh Size: 32-bit
Bit Description
Wake Alarm Device Timer Value for DC Mode (WADT_DC_VAL): R/W. This field
contains the 32-bit wake alarm device timer value (1 second granularity) for DC
power. The timer begins decrementing when written to a value other than FFFFFFFFh
(regardless of the power source when the write occurs). Upon counting down to 0:
• If on DC power, GPE0_STS.WADT_STS will be set. This status bit being set will generate a
host wake if GPE0_EN.WADT_EN is ‘1’.
31:0 • If power source is AC at this time, the status bit is not set. However, if DC power
subsequently returns to the platform, the DC Expired Timer begins running. Refer to
WADT_EXP_DC for more details.
• The timer returns to its default value of FFFFFFFFh.
NOTE: Bits in this register only need to be valid for reading when the Main power
well is up.
10.1.41 WADT_EXP_AC—Wake Alarm Device Expired Timer – AC
Register
Offset Address: 3308–330Bh Attribute: R/W
Default Value: FFFFFFFFh Size: 32-bit
Bit Description
Wake Alarm Device Expired Timer Value for AC Mode (WADT_EXP_AC_VAL):
R/W. This field contains the 32-bit wake alarm device “Expired Timer” value (1
second granularity) for AC power. The timer begins decrementing after switching
from DC to AC power, in the case where the WADT_AC timer has already expired
while platform was on DC power. This timer only decrements while operating on AC
power. So if the power source switches back to DC power, the timer will stop (but not
reset). When AC power returns, the timer will again begin decrementing.
Upon expiration of this timer:
31:0
• If on AC power, GPE0_STS.WADT_STS will be set. This status bit being set will generate a
host wake if GPE0_EN.WADT_EN is ‘1’.
• Both the AC and DC Expired TImers return to their default value of FFFFFFFFh.
NOTE: This timer will only begin decrementing under the conditions described above
if this field has been configured for something other than its default value of
FFFFFFFFh.
NOTE: Bits in this register only need to be valid for reading when the Main power
well is up.
Datasheet 415
Chipset Configuration Registers
10.1.42 WADT_EXP_DC—Wake Alarm Device Expired Timer – DC
Register
Offset Address: 330C–330Fh Attribute: R/W
Default Value: FFFFFFFFh Size: 32-bit
Bit Description
Wake Alarm Device Expired Timer Value for DC Mode (WADT_EXP_DC_VAL):
R/W. This field contains the 32-bit wake alarm device “Expired Timer” value (1
second granularity) for DC power. The timer begins decrementing after switching
from AC to DC power, in the case where the WADT_DC timer has already expired
while platform was on AC power. This timer only decrements while operating on DC
power. So if the power source switches back to AC power, the timer will stop (but not
reset). When DC power returns, the timer will again begin decrementing.
31:0 Upon expiration of this timer:
• If on DC power, GPE0_STS.WADT_STS will be set. This status bit being set will generate a
host wake if GPE0_EN.WADT_EN is ‘1’.
• Both the AC and DC Expired TImers return to their default value of FFFFFFFFh.
•
NOTE: This timer will only begin decrementing under the conditions described above
if this field has been configured for something other than its default value of
FFFFFFFF.
NOTE: Bits in this register only need to be valid for reading when the Main power
well is up.
416 Datasheet
Chipset Configuration Registers
10.1.43 PRSTS—Power and Reset Status Register
Offset Address: 3310–3313h Attribute: RO, R/WC
Default Value: 05000000h Size: 32-bit
Bit Description
31:16 Reserved
Power Management Watchdog Timer—R/WC. This bit is set when the Power
15 Management watchdog timer causes a global reset. This bit is cleared when the
software writes it with a 1b.
14:7 Reserved
Intel® Management Engine Watchdog Timer Status—R/WC. This bit is set when
6 the Intel Management Engine watchdog timer causes a global reset. This bit is
cleared when the software writes it with a 1b.
Wake On LAN Override Wake Status (WOL_OVR_WK_STS)—R/WC. This bit
gets set when all of the following conditions are met:
• Integrated LAN Signals a Power Management Event
5 • The system is not in S0
• The “WoL Enable Override” bit is set in configuration space.
BIOS can read this status bit to determine this wake source.
Software clears this bit by writing a 1 to it.
4 PRSTS Field 1—R/WC. BIOS may program this field.
Intel ME Host Power Down (ME_HOST_PWRDN)—R/WC. This bit is set when the
3
Intel Management Engine generates a host reset with power down.
Intel ME Host Reset Warm Status (ME_HRST_WARM_STS)—R/WC. This bit is
2 set when the Intel Management Engine generates a Host reset without power cycling.
Software clears this bit by writing a 1 to this bit position.
Intel ME Host Reset Cold Status (ME_HRST_COLD_STS)—R/WC. This bit is set
1 when the Intel Management Engine generates a Host reset with power cycling.
Software clears this bit by writing a 1 to this bit position.
Intel ME WAKE STATUS (ME_WAKE_STS)—R/WC. This bit is set when the Intel
Management Engine generates a Non-Maskable wake event, and is not affected by
0
any other enable bit. When this bit is set, the Host Power Management logic wakes to
S0.
Datasheet 417
Chipset Configuration Registers
10.1.44 PM_CFG—Power Management Configuration Register
Offset Address: 3318–331Bh Attribute: R/W
Default Value: 00000020h Size: 32-bit
Bit Description
31:27 Reserved
26:24 PM_CFG Field 1—R/W. BIOS must program this field to 101b.
23:22 Reserved
RTC Wake from Deep Sx Disable (RTC_DS_WAKE_DIS)—R/W. When set, this
21 bit disables RTC wakes from waking the system from Deep Sx.
This bit is reset by RTCRST#.
20 Reserved
SLP_SUS# Minimum Assertion Width (SLP_SUS_MIN_ASST_WDTH)—R/WL.
This field indicates the minimum assertion width of the SLP_SUS# signal to ensure
that the SUS power supplies have been fully power cycled. This value may be
modified per platform depending on power supply capacitance, board capacitance,
power circuits, and so on.
Valid values are:
11 = 4 seconds
10 = 1 second
01 = 500 ms
00 = 0 ms (that is, stretching disabled – default)
19:18 These bits are cleared by RTCRST# assertion.
NOTES:
1. This field is RO when the SLP Stretching Policy Lock-Down bit is set.
2. This field is ignored when exiting G3 or Deep Sx states if the “Disable SLP
Stretching After SUS Well Power Up” bit is set. Unlike with all other SLP_* pin
stretching, this disable bit only impacts SLP_SUS# stretching during G3 exit,
rather than both G3 and Deep Sx exit. SLP_SUS# stretching always applies to
Deep Sx regardless of the disable bit.
3. For platforms that enable Deep Sx, BIOS must program SLP_SUS# stretching
to be greater than or equal to the largest stretching value on any other SLP_*
pin (SLP_S3#, SLP_S4#, SLP_LAN# or SLP_A#).
SLP_A# Minimum Assertion Width (SLP_A_MIN_ASST_WDTH)—R/W. This
field indicates the minimum assertion width of the SLP_A# signal to ensure that the
ASW power supplies have been fully power cycled. This value may be modified per
platform depending on power supply capacitance, board capacitance, power circuits,
and so on.
Valid values are:
11 = 2 seconds
17:16 10 = 98 ms
01 = 4 seconds
00 = 0 ms (that is, stretching disabled – default)
These bits are cleared by RTCRST# assertion.
NOTES:
1. This field is RO when the SLP Stretching Policy Lock-Down bit is set.
2. This field is ignored when exiting G3 or Deep Sx states if the “Disable SLP
Stretching After SUS Well Power Up” bit is set.
418 Datasheet
Chipset Configuration Registers
Bit Description
SLP_LAN# Minimum Assertion Width (SLP_LAN_MIN_ASST_WDTH)—R/WL.
This field indicates the minimum assertion width of the SLP_LAN# signal to ensure
that the PHY power supplies have been fully power cycled. This value may be
modified per platform depending on power supply capacitance, board capacitance,
power circuits, and so on.
Valid values are:
15:14
11 = 2 seconds
10 = 50 ms
01 = 1 ms
00 = 0 ms (that is, stretching disabled – default)
These bits are cleared by RTCRST# assertion.
NOTE: This field is RO when the SLP Stretching Policy Lock-Down bit is set.
13:10 Reserved
Reset Power Cycle Duration (PWR_CYC_DUR)—R/WL. This field indicates the
minimum time a platform will stay in reset (SLP_S3#, SLP_S4#, SLP_S5# asserted
and SLP_A# and SLP_LAN# asserted if applicable) during a host reset with power
cycle, host reset with power down or a global reset. The duration programmed in this
register takes precedence over the applicable SLP_# stretch timers in these reset
scenario.
Valid values are:
11 = 1-2 seconds
10 = 2-3 seconds
9:8 01 = 3-4 seconds
00 = 4-5 seconds (default)
These bits are cleared by RTCRST# assertion.
NOTES:
1. This field is RO when the SLP Stretching Policy Lock-Down bit is set.
2. The duration programmed in this register should never be smaller than the
stretch duration programmed in the following registers:
— GEN_PMCON_3.SLP_S3_MIN_ASST_WDTH
— GEN_PMCON_3.SLP_S4_MIN_ASST_WDTH
— PM_CFG.SLP_A_MIN_ASST_WDTH
— PM_CFG.SLP_LAN_MIN_ASST_WDTH
7:5 Reserved
Host Wireless LAN PHY Power Enable (HOST_WLAN_PP_EN)—R/W.
Set by host software when it desires the WiFi LAN PHY to be powered in Sx power
4
states for Wake Over WiFi (WoWLAN). See SLP_WLAN# for more information. Default
= 0b.
3:0 Reserved
Datasheet 419
Chipset Configuration Registers
10.1.45 DEEP_S3_POL—Deep Sx From S3 Power Policies Register
Offset Address: 3328–332Bh Attribute: R/W
Default Value: 00000000h Size: 32-bit
This register is in the RTC power well and is reset by RTCRST# assertion.
Bit Description
31:2 Reserved
Deep Sx From S3 Enable in DC Mode (DPS3_EN_DC)—R/W. A '1' in this bit
1 enables the platform to enter Deep Sx while operating in S3 on DC power (based on
the ACPRESENT pin value).
Deep Sx From S3 Enable in AC Mode (DPS3_EN_AC)—R/W. A '1' in this bit
0 enables the platform to enter Deep Sx while operating in S3 on AC power (based on
the ACPRESENT pin value).
10.1.46 DEEP_S4_POL—Deep Sx From S4 Power Policies Register
Offset Address: 332C–332Fh Attribute: R/W
Default Value: 00000000h Size: 32-bit
This register is in the RTC power well and is reset by RTCRST# assertion.
Bit Description
31:2 Reserved
Deep Sx From S4 Enable in DC Mode (DPS4_EN_DC)—R/W. A '1' in this bit
1 enables the platform to enter Deep Sx while operating in S4 on DC power (based on
the ACPRESENT pin value).
Deep Sx From S4 Enable in AC Mode (DPS4_EN_AC)—R/W. A '1' in this bit
0 enables the platform to enter Deep Sx while operating in S4 on AC power (based on
the ACPRESENT pin value). Required to be programmed to 0 on mobile.
10.1.47 DEEP_S5_POL—Deep Sx From S5 Power Policies Register
Offset Address: 3330–3333h Attribute: R/W
Default Value: 00000000h Size: 32-bit
This register is in the RTC power well and is reset by RTCRST# assertion.
Bit Description
31:16 Reserved
Deep Sx From S5 Enable in DC Mode (DPS5_EN_DC)—R/W. A '1' in this bit
15 enables the platform to enter Deep Sx while operating in S5 on DC power (based on
the ACPRESENT pin value).
Deep Sx From S5 Enable in AC Mode (DPS5_EN_AC)—R/W. A '1' in this bit
14 enables the platform to enter Deep Sx while operating in S5 on AC power (based on
the ACPRESENT pin value).
13:0 Reserved
420 Datasheet
Chipset Configuration Registers
10.1.48 DSX_CFG—Deep Sx Configuration Register
Offset Address: 3334–3337h Attribute: R/W
Default Value: 00000000h Size: 32-bit
This register is in the RTC power well and is reset by RTCRST# assertion.
Bit Description
31:3 Reserved
WAKE# Pin Deep Sx Enable (WAKE_PIN__DSX_EN)—R/W. When this bit is ‘1’,
the PCI Express* WAKE# pin is monitored while in Deep Sx, supporting wake from
Deep Sx due to assertion of this pin. In this case the platform must externally pull-up
the pin to the DSW (instead of pulling-up to the SUS as historically been the case).
When this bit is ‘0’:
2
• Deep Sx configurations: The PCH internal pull-down on the WAKE# pin is enabled in Deep Sx
and during G3 exit and the pin is not monitored during this time.
• Deep Sx disabled configurations: The PCH internal pull-down on the WAKE# pin is never
enabled.
NOTE: Deep Sx disabled configuration must leave this bit at ‘0’.
ACPRESENT Pin Pull-down in Deep Sx Disable (ACPRE_PD_DSX_DIS)—R/W.
When this bit is ‘1’, the internal pull-down on this ACPRESENT pin is disabled.
However, the pull-down is not necessarily enabled if the bit is ‘0’. To support ME
wakes from Deep Sx using MGPIO2, the pin is always monitored regardless of the
value of this host policy bit.
When this bit is ‘0’:
1
• Deep Sx configurations: The PCH internal pull-down on ACPRESENT is enabled in Deep Sx
and during G3 exit.
• Deep Sx disabled configurations: The PCH internal pull-down on ACPRESENT is always
disabled.
NOTE: Deep Sx disabled configuration must leave this bit at ‘0’ and the pull-down is
disabled even though the bit is ‘0’.
GP27 Pin Deep Sx Enable (GP27_PIN_DSX_EN)—R/W. When this bit is ‘1’, the
GP27 pin is monitored while in Deep Sx, supporting wake from Deep Sx due to
assertion of this pin. In this case the platform must drive the pin to the correct value
while in Deep Sx.
0 When this bit is ‘0’:
• Deep Sx configurations: The PCH internal pull-down on GP27 pin is enabled in Deep Sx and
during G3 exit and the pin is not monitored during this time.
• Deep Sx disabled configurations: The PCH internal pull-down on GP27 pin is never enabled.
NOTE: Deep Sx disabled configuration must leave this bit at ‘0’.
Datasheet 421
Chipset Configuration Registers
10.1.49 PMSYNC_CFG—PMSYNC Configuration Register
Offset Address: 33C8–33CBh Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:12 Reserved
GPIO_D Pin Selection (GPIO_D_SEL)—R/W. There are two possible GPIOs that
can be routed to the GPIO_D PMSYNC state. This bit selects between them:
11
0 = GPIO5 (default)
1 = GPIO0
GPIO_C Pin Selection (GPIO_C_SEL)—R/W. There are two possible GPIOs that
can be routed to the GPIO_C PMSYNC state. This bit selects between them:
10
0 = GPIO37 (default)
1 = GPIO4
GPIO_B Pin Selection (GPIO_B_SEL)—R/W. There are two possible GPIOs that
can be routed to the GPIO_B PMSYNC state. This bit selects between them:
9
0 = GPIO0 (default)
1 = GPIO37
GPIO_A Pin Selection (GPIO_A_SEL)—R/W. There are two possible GPIOs that
can be routed to the GPIO_A PMSYNC state. This bit selects between them:
8
0 = GPIO4 (default)
1 = GPIO5
7:0 Reserved
10.1.50 RC—RTC Configuration Register
Offset Address: 3400–3403h Attribute: R/W, R/WLO
Default Value: 00000000h Size: 32-bit
Bit Description
31:5 Reserved
Upper 128 Byte Lock (UL)—R/WLO.
0 = Bytes not locked.
4 1 = Bytes 38h–3Fh in the upper 128-byte bank of RTC RAM are locked and cannot be
accessed. Writes will be dropped and reads will not return any ensured data. Bit
reset on system reset.
Lower 128 Byte Lock (LL)—R/WLO.
0 = Bytes not locked.
3 1 = Bytes 38h–3Fh in the lower 128-byte bank of RTC RAM are locked and cannot be
accessed. Writes will be dropped and reads will not return any ensured data. Bit
reset on system reset.
Upper 128 Byte Enable (UE)—R/W.
2 0 = Bytes locked.
1 = The upper 128-byte bank of RTC RAM can be accessed.
1:0 Reserved
422 Datasheet
Chipset Configuration Registers
10.1.51 HPTC—High Precision Timer Configuration Register
Offset Address: 3404–3407h Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:8 Reserved
Address Enable (AE)—R/W.
0 = Address disabled.
7
1 = The PCH will decode the High Precision Timer memory address range selected by
bits 1:0 below.
6:2 Reserved
Address Select (AS)—R/W. This 2-bit field selects 1 of 4 possible memory address
ranges for the High Precision Timer functionality. The encodings are:
00 = FED0_0000h – FED0_03FFh
1:0
01 = FED0_1000h – FED0_13FFh
10 = FED0_2000h – FED0_23FFh
11 = FED0_3000h – FED0_33FFh
10.1.52 GCS—General Control and Status Register
Offset Address: 3410–3413h Attribute: R/W, R/WLO
Default Value: 00000yy0h (yy = xx0000x0b) Size: 32-bit
Bit Description
31:12 Reserved
Boot BIOS Straps (BBS)—R/W. This field determines the destination of accesses to
the BIOS memory range. The default values for these bits represent the strap values
of GPIO51 (bit 11) at the rising edge of PWROK and SATA1GP/GPIO19 (bit 10) at the
rising edge of PWROK.
Bits 11:10 Description
00b LPC
01b Reserved
10b Reserved
11:10
11b SPI
When SPI or LPC is selected, the range that is decoded is further qualified by other
configuration bits described in the respective sections.
The value in this field can be overwritten by software as long as the BIOS Interface
Lock-Down (bit 0) is not set.
Boot BIOS Destination Select to LPC by functional strap or using Boot BIOS
Destination Bit will not affect SPI accesses initiated by Intel Management Engine or
Integrated GbE LAN.
Datasheet 423
Chipset Configuration Registers
Bit Description
Server Error Reporting Mode (SERM)—R/W.
0 = The PCH is the final target of all errors. The processor sends a messages to the
PCH for the purpose of generating NMI.
9 1 = The processor is the final target of all errors from PCI Express* and DMI. In this
mode, if the PCH detects a fatal, non-fatal, or correctable error on DMI or its
downstream ports, it sends a message to the processor. If the PCH receives an
ERR_* message from the downstream port, it sends that message to the
processor.
8:6 Reserved
No Reboot (NR)—R/W. This bit is set when the “No Reboot” strap (SPKR pin on the
PCH) is sampled high on PWROK. This bit may be set or cleared by software if the
strap is sampled low but may not override the strap when it indicates “No Reboot”.
5
0 = System will reboot upon the second timeout of the TCO timer.
1 = The TCO timer will count down and generate the SMI# on the first timeout, but
will not reboot on the second timeout.
Alternate Access Mode Enable (AME)—R/W.
0 = Disabled.
1 = Alternate access read only registers can be written, and write only registers can
be read. Before entering a low power state, several registers from powered down
4 parts may need to be saved. In the majority of cases, this is not an issue, as
registers have read and write paths. However, several of the ISA compatible
registers are either read only or write only. To get data out of write-only
registers, and to restore data into read-only registers, the PCH implements an
alternate access mode. For a list of these registers see Section 5.14.9.
Shutdown Policy Select (SPS)—R/W.
0 = PCH will drive INIT# in response to the shutdown Vendor Defined Message
3 (VDM). (default)
1 = PCH will treat the shutdown VDM similar to receiving a CF9h I/O write with data
value 06h, and will drive PLTRST# active.
Reserved Page Route (RPR)—R/W. Determines where to send the reserved page
registers. These addresses are sent to PCI or LPC for the purpose of generating POST
codes. The I/O addresses modified by this field are: 80h, 84h, 85h, 86h, 88h, 8Ch,
8Dh, and 8Eh.
0 = Writes will be forwarded to LPC, shadowed within the PCH, and reads will be
returned from the internal shadow
2 1 = Writes will be forwarded to PCI, shadowed within the PCH, and reads will be
returned from the internal shadow.
NOTE: if some writes are done to LPC/PCI to these I/O ranges, and then this bit is
flipped, such that writes will now go to the other interface, the reads will not
return what was last written. Shadowing is performed on each interface.
The aliases for these registers, at 90h, 94h, 95h, 96h, 98h, 9Ch, 9Dh, and 9Eh, are
always decoded to LPC.
1 Reserved
BIOS Interface Lock-Down (BILD)—R/WLO.
0 = Disabled.
0
1 = Prevents BUC.TS (offset 3414, bit 0) and GCS.BBS (offset 3410h, bits 11:10)
from being changed. This bit can only be written from 0 to 1 once.
424 Datasheet
Chipset Configuration Registers
10.1.53 BUC—Backed Up Control Register
Offset Address: 3414h Attribute: R/W
Default Value: 0000000xb Size: 8-bit
All bits in this register are in the RTC well and only cleared by RTCRST#.
Bit Description
7:6 Reserved
LAN Disable—R/W.
0 = LAN is Enabled
1 = LAN is Disabled.
5 Changing the internal GbE controller from disabled to enabled requires a system
reset (write of 0Eh to CF9h (RST_CNT Register)) immediately after clearing the LAN
disable bit. A reset is not required if changing the bit from enabled to disabled.
This bit is locked by the Function Disable SUS Well Lockdown register. Once locked,
this bit cannot be changed by software.
Daylight Savings Override (SDO)—R/W.
0 = Daylight Savings is Enabled and configurable by software.
4 1 = The DSE bit in RTC Register B bit[0] is set to Read-only with a value of 0 to
disable daylight savings.
NOTE: System BIOS shall configure this bit accordingly during the boot process
before RTC time is initialized.
3:1 Reserved
Top Swap (TS)—R/W.
0 = PCH will not allow invert the boot block.
1 = PCH will allow boot block invert, for cycles going to the BIOS space.
NOTE: If Top Swap is enabled (TS = 1b):
1. If booting from SPI, then the BIOS boot block size (BOOT_BLOCK_SIZE) soft
0 strap determines if A16, A17, A18, A19 or A20 should be inverted.
2. If booting from LPC (FWH), then the boot-block size is hard-set to 64 KB and
only A16 is inverted (soft strap is ignored in this case).
3. If PCH is strapped for Top Swap (GPIO55 is low at rising edge of PWROK),
then this bit cannot be cleared by software. The strap jumper should be
removed and the system rebooted.
Datasheet 425
Chipset Configuration Registers
10.1.54 FD—Function Disable Register
Offset Address: 3418–341Bh Attribute: R/W
Default Value: See bit description Size: 32-bit
When disabling a function, only the configuration space is disabled. Software must
ensure that all functionality within a controller that is not desired (such as memory
spaces, I/O spaces, and DMA engines) is disabled prior to disabling the function.
When a function is disabled, software must not attempt to re-enable it. A disabled
function can only be re-enabled by a platform reset.
Bit Description
31:28 Reserved
XHCI Disable (XHD)—R/W. Default is 0.
27 0 = The XHCI controller is enabled.
1 = The XHCI controller is disabled.
26 Reserved
Serial ATA Disable 2 (SAD2)—R/W. Default is 0.
25 0 = The SATA controller #2 (D31:F5) is enabled.
1 = The SATA controller #2 (D31:F5) is disabled.
Thermal Sensor Registers Disable (TTD)—R/W. Default is 0.
24 0 = Thermal Sensor Registers (D31:F6) are enabled.
1 = Thermal Sensor Registers (D31:F6) are disabled.
PCI Express* 8 Disable (PE8D)—R/W. Default is 0. When disabled, the link for this
port is put into the “link down” state.
23
0 = PCI Express* port #8 is enabled.
1 = PCI Express port #8 is disabled.
PCI Express 7 Disable (PE7D)—R/W. Default is 0. When disabled, the link for this
port is put into the link down state.
22
0 = PCI Express port #7 is enabled.
1 = PCI Express port #7 is disabled.
PCI Express* 6 Disable (PE6D)—R/W. Default is 0. When disabled, the link for this
port is put into the “link down” state.
21
0 = PCI Express* port #6 is enabled.
1 = PCI Express port #6 is disabled.
PCI Express 5 Disable (PE5D)—R/W. Default is 0. When disabled, the link for this
port is put into the link down state.
20
0 = PCI Express port #5 is enabled.
1 = PCI Express port #5 is disabled.
PCI Express 4 Disable (PE4D)—R/W. Default is 0. When disabled, the link for this
port is put into the “link down” state.
19 0 = PCI Express port #4 is enabled.
1 = PCI Express port #4 is disabled.
NOTE: This bit must be set when Port 1 is configured as a x4.
PCI Express 3 Disable (PE3D)—R/W. Default is 0. When disabled, the link for this
port is put into the link down state.
18 0 = PCI Express port #3 is enabled.
1 = PCI Express port #3 is disabled.
NOTE: This bit must be set when Port 1 is configured as a x4.
426 Datasheet
Chipset Configuration Registers
Bit Description
PCI Express* 2 Disable (PE2D)—R/W. Default is 0. When disabled, the link for this
port is put into the link down state.
17 0 = PCI Express port #2 is enabled.
1 = PCI Express port #2 is disabled.
NOTE: This bit must be set when Port 1 is configured as a x4 or a x2.
PCI Express 1 Disable (PE1D)—R/W. Default is 0. When disabled, the link for this
port is put into the link down state.
16
0 = PCI Express port #1 is enabled.
1 = PCI Express port #1 is disabled.
EHCI #1 Disable (EHCI1D)—R/W. Default is 0.
15 0 = The EHCI #1 is enabled.
1 = The EHCI #1 is disabled.
LPC Bridge Disable (LBD)—R/W. Default is 0.
0 = The LPC bridge is enabled.
1 = The LPC bridge is disabled. Unlike the other disables in this register, the following
additional spaces will no longer be decoded by the LPC bridge:
• Memory cycles below 16 MB (1000000h)
14
• I/O cycles below 64 KB (10000h)
• The Internal I/OxAPIC at FEC0_0000 to FECF_FFFF
Memory cycle in the LPC BIOS range below 4 GB will still be decoded when this bit is
set; however, the aliases at the top of 1 MB (the E and F segment) no longer will be
decoded.
EHCI #2 Disable (EHCI2D)—R/W. Default is 0.
13 0 = The EHCI #2 is enabled.
1 = The EHCI #2 is disabled.
12:5 Reserved
Intel® High Definition Audio Disable (HDAD)—R/W. Default is 0.
0 = The Intel High Definition Audio controller is enabled.
4
1 = The Intel High Definition Audio controller is disabled and its PCI configuration
space is not accessible.
SMBus Disable (SD)—R/W. Default is 0.
0 = The SMBus controller is enabled.
3
1 = The SMBus controller is disabled. Setting this bit only disables the PCI
configuration space.
Serial ATA Disable 1 (SAD1)—R/W. Default is 0.
2 0 = The SATA controller #1 (D31:F2) is enabled.
1 = The SATA controller #1 (D31:F2) is disabled.
1 Reserved.
0 BIOS must program this field to 1b.
Datasheet 427
Chipset Configuration Registers
10.1.55 CG—Clock Gating Register
Offset Address: 341C–341Fh Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
Legacy (LPC) Dynamic Clock Gate Enable—R/W.
31 0 = Legacy Dynamic Clock Gating is Disabled
1 = Legacy Dynamic Clock Gating is Enabled
30:24 Reserved
LAN Static Clock Gating Enable (LANSCGE)—R/W.
0 = LAN Static Clock Gating is Disabled
23
1 = LAN Static Clock Gating is Enabled when the LAN Disable bit is set in the Backed
Up Control RTC register.
High Definition Audio Dynamic Clock Gate Enable—R/W.
22 0 = High Definition Audio Dynamic Clock Gating is Disabled
1 = High Definition Audio Dynamic Clock Gating is Enabled
High Definition Audio Static Clock Gate Enable—R/W.
21 0 = High Definition Audio Static Clock Gating is Disabled
1 = High Definition Audio Static Clock Gating is Enabled
20:17 Reserved
PCI Dynamic Gate Enable—R/W.
16 0 = PCI Dynamic Gating is Disabled
1 = PCI Dynamic Gating is Enabled
15:6 Reserved
SMBus Clock Gating Enable (SMBCGEN)—R/W.
0 = SMBus Clock Gating is Disabled.
5
1 = SMBus Clock Gating is Enabled.
NOTE: Setting this bit will also clock gate all the TCO logic functionality.
4:0 Reserved
10.1.56 FDSW—Function Disable SUS Well Register
Offset Address: 3420h Attribute: R/W
Default Value: 00h Size: 8-bit
Bit Description
Function Disable SUS Well Lockdown (FDSWL)—R/W03
0 = FDSW registers are not locked down
7
1 = FDSW registers are locked down
NOTE: This bit must be set when Intel AMT is enabled.
6:0 Reserved
428 Datasheet
Chipset Configuration Registers
10.1.57 DISPBDF—Display Bus, Device and Function
Initialization Register
Offset Address: 3424–3427h Attribute: R/W
Default Value: 00040010h Size: 32-bit
Bit Description
31:19 Reserved.
Display Target Block (DTB)—R/W. The Target BLK field that the PCH South Display
18:16 controller should use when sending RAVDM messages to the processor. BIOS must
program this field to 110h.
Display Bus Number (DBN)—R/W. The bus number of the Display in the processor.
15:8
BIOS must program this field to 0h.
Display Device Number (DDN)—R/W. The device number of the Display in the
7:3
processor. BIOS must program this field to 2h.
Display Function Number (DFN)—R/W. The function number of the Display in the
2:0
processor. BIOS must program this field to 0h.
10.1.58 FD2—Function Disable 2 Register
Offset Address: 3428–342Bh Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:5 Reserved
KT Disable (KTD)—R/W. Default is 0.
4 0 = Keyboard Text controller (D22:F3) is enabled.
1 = Keyboard Text controller (D22:F3) is Disabled
IDE-R Disable (IRERD)—R/W. Default is 0.
3 0 = IDE Redirect controller (D22:F2) is Enabled.
1 = IDE Redirect controller (D22:F2) is Disabled.
Intel® MEI #2 Disable (MEI2D)—R/W. Default is 0.
2 0 = Intel MEI controller #2 (D22:F1) is enabled.
1 = Intel MEI controller #2 (D22:F1) is disabled.
Intel MEI #1 Disable (MEI1D)—R/W. Default is 0.
1 0 = Intel MEI controller #1 (D22:F0) is enabled.
1 = Intel MEI controller #1 (D22:F0) is disabled.
0 Display BDF Enable (DBDFEN)—R/W. Default is 0.
Datasheet 429
Chipset Configuration Registers
10.2 Thermal Configuration Registers
Note: All registers here are an offset of TBARB (see Section 22.1.19).
Table 10-1. Thermal Initialization Registers
Offset Mnemonic Register Name Default Attribute
C0h–C3h TIRC0 Thermal Initialization Register C0 00000000h R/W
C4h–C7h TIRC4 Thermal Initialization Register C4 00000000h R/W
C8h–CBh TIRC8 Thermal Initialization Register C8 00000000h R/W
CCh–CFh TIRCC Thermal Initialization Register CC 00000000h R/W
D0h–D3h TIRD0 Thermal Initialization Register D0 00000000h R/W
E0h–E3h TIRE0 Thermal Initialization Register E0 00000000h R/W
F0h–F3h TIRF0 Thermal Initialization Register F0 00000000h R/W
10.2.1 TIRC0—Thermal Initialization Register C0
Offset Address: C0–C3h Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:0 R/W. BIOS must program this field to 8000390Bh. No other values are supported.
10.2.2 TIRC4—Thermal Initialization Register C4
Offset Address: C4–C7h Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:0 R/W. BIOS must program this field to C11F0201h. No other values are supported.
10.2.3 TIRC8—Thermal Initialization Register C8
Offset Address: C8–CBh Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:0 R/W. BIOS must program this field to 05800000h. No other values are supported.
10.2.4 TIRCC—Thermal Initialization Register CC
Offset Address: CC–CFh Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:0 R/W. BIOS must program this field to 0000C000h. No other values are supported.
430 Datasheet
Chipset Configuration Registers
10.2.5 TIRD0—Thermal Initialization Register D0
Offset Address: D0–D3h Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:0 R/W. BIOS must program this field to 00000320h. No other values are supported.
10.2.6 TIRE0—Thermal Initialization Register E0
Offset Address: E0–E3h Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:0 R/W. BIOS must program this field to 80001E4Fh. No other values are supported.
10.2.7 TIRF0—Thermal Initialization Register F0
Offset Address: F0–F3h Attribute: R/W
Default Value: 00000000h Size: 32-bit
Bit Description
31:0 R/W. BIOS must program this field to 00000003h. No other values are supported.
§§
Datasheet 431
Chipset Configuration Registers
432 Datasheet
Gigabit LAN Configuration Registers
11 Gigabit LAN Configuration
Registers
11.1 Gigabit LAN Configuration Registers
(Gigabit LAN—D25:F0)
Note: Register address locations that are not shown in Table 11-1 should be treated as
Reserved. All GbE registers are located in the VccASW power well.
/
Table 11-1. Gigabit LAN Configuration Registers Address Map
(Gigabit LAN—D25:F0) (Sheet 1 of 2)
Offset Mnemonic Register Name Default Attribute
00h–01h VID Vendor Identification 8086h RO
See register
02h–03h DID Device Identification RO
description
04h–05h PCICMD PCI Command 0000h R/W, RO
06h–07h PCISTS PCI Status 0010h R/WC, RO
See register
08h RID Revision Identification RO
description
09h–0Bh CC Class Code 020000h RO
0Ch CLS Cache Line Size 00h R/W
0Dh PLT Primary Latency Timer 00h RO
0Eh HEADTYP Header Type 00h RO
10h–13h MBARA Memory Base Address A 00000000h R/W, RO
14h–17h MBARB Memory Base Address B 00000000h R/W, RO
18h–1Bh MBARC Memory Base Address C 00000001h R/W, RO
See register
2Ch–2Dh SVID Subsystem Vendor ID RO
description
See register
2Eh–2Fh SID Subsystem ID RO
description
See register
30h–33h ERBA Expansion ROM Base Address RO
description
34h CAPP Capabilities List Pointer C8h RO
See register
3Ch–3Dh INTR Interrupt Information R/W, RO
description
3Eh–3Fh MLMG Maximum Latency / Minimum Grant 0000h RO
A0h–A3h STCL System Time Capture Low 00000000h RO
A4h–A7h STCH System Time Capture High 00000000h RO
A8h–ABh LTR Latency Tolerance Reporting 00000000h R/W
C8h–C9h CLIST1 Capabilities List 1 D001h RO
See register
CAh–CBh PMC PCI Power Management Capability RO
description
Datasheet 433
Gigabit LAN Configuration Registers
Table 11-1. Gigabit LAN Configuration Registers Address Map
(Gigabit LAN—D25:F0) (Sheet 2 of 2)
Offset Mnemonic Register Name Default Attribute
PCI Power Management Control and See register R/WC, R/W,
CCh–CDh PMCS
Status description RO
See register
CFh DR Data Register RO
description
D0h–D1h CLIST2 Capabilities List 2 E005h R/WO, RO
D2h–D3h MCTL Message Control 0080h R/W, RO
See register
D4h–D7h MADDL Message Address Low R/W
description
See register
D8h–dBh MADDH Message Address High R/W
description
See register
DCh–DDh MDAT Message Data R/W
description
E0h–E1h FLRCAP Function Level Reset Capability 0009h RO
Function Level Reset Capability See register
E2h–E3h FLRCLV R/WO, RO
Length and Value description
E4h–E5h DEVCTRL Device Control 0000h R/W, RO
11.1.1 VID—Vendor Identification Register
(Gigabit LAN—D25:F0)
Address Offset: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bits
Bit Description
Vendor ID—RO. This is a 16-bit value assigned to Intel. The field may be auto-loaded
15:0 from the NVM at address 0Dh during init time depending on the “Load Vendor/Device
ID” bit field in NVM word 0Ah with a default value of 8086h.
11.1.2 DID—Device Identification Register
(Gigabit LAN—D25:F0)
Address Offset: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bits
Bit Description
Device ID—RO. This is a 16-bit value assigned to the PCH Gigabit LAN controller. The
15:0 field may be auto-loaded from the NVM word 0Dh during initialization time depending
on the "Load Vendor/Device ID" bit field in NVM word 0Ah.
434 Datasheet
Gigabit LAN Configuration Registers
11.1.3 PCICMD—PCI Command Register
(Gigabit LAN—D25:F0)
Address Offset: 04h–05h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved
Interrupt Disable—R/W. This disables pin-based INTx# interrupts on enabled Hot-
Plug and power management events. This bit has no effect on MSI operation.
0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or
power management and MSI is not enabled.
10
1 = Internal INTx# messages will not be generated.
This bit does not affect interrupt forwarding from devices connected to the root port.
Assert_INTx and Deassert_INTx messages will still be forwarded to the internal
interrupt controllers if this bit is set.
9 Fast Back to Back Enable (FBE)—RO. Hardwired to 0.
SERR# Enable (SEE)—R/W.
0 = Disable
8
1 = Enables the Gb LAN controller to generate an SERR# message when PSTS.SSE is
set.
7 Wait Cycle Control (WCC)—RO. Hardwired to 0.
Parity Error Response (PER)—R/W.
0 = Disable.
6
1 = Indicates that the device is capable of reporting parity errors as a master on the
backbone.
5 Palette Snoop Enable (PSE)—RO. Hardwired to 0.
4 Postable Memory Write Enable (PMWE)—RO. Hardwired to 0.
3 Special Cycle Enable (SCE)—RO. Hardwired to 0.
Bus Master Enable (BME)—R/W.
0 = Disable. All cycles from the device are master aborted
2
1 = Enable. Allows the root port to forward cycles onto the backbone from a Gigabit
LAN* device.
Memory Space Enable (MSE)—R/W.
0 = Disable. Memory cycles within the range specified by the memory base and limit
1 registers are master aborted on the backbone.
1 = Enable. Allows memory cycles within the range specified by the memory base and
limit registers can be forwarded to the Gigabit LAN device.
I/O Space Enable (IOSE)—R/W. This bit controls access to the I/O space registers.
0 = Disable. I/O cycles within the range specified by the I/O base and limit registers
0 are master aborted on the backbone.
1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit
registers can be forwarded to the Gigabit LAN device.
Datasheet 435
Gigabit LAN Configuration Registers
11.1.4 PCISTS—PCI Status Register
(Gigabit LAN—D25:F0)
Address Offset: 06h–07h Attribute: R/WC, RO
Default Value: 0010h Size: 16 bits
Bit Description
Detected Parity Error (DPE)—R/WC.
0 = No parity error detected.
15
1 = Set when the Gb LAN controller receives a command or data from the backbone
with a parity error. This is set even if PCIMD.PER (D25:F0, bit 6) is not set.
Signaled System Error (SSE)—R/WC.
14 0 = No system error signaled.
1 = Set when the Gb LAN controller signals a system error to the internal SERR# logic.
Received Master Abort (RMA)—R/WC.
0 = Root port has not received a completion with unsupported request status from the
13 backbone.
1 = Set when the GbE LAN controller receives a completion with unsupported request
status from the backbone.
Received Target Abort (RTA)—R/WC.
0 = Root port has not received a completion with completer abort from the backbone.
12
1 = Set when the Gb LAN controller receives a completion with completer abort from
the backbone.
Signaled Target Abort (STA)—R/WC.
11 0 = No target abort received.
1 = Set whenever the Gb LAN controller forwards a target abort received from the
downstream device onto the backbone.
10:9 DEVSEL# Timing Status (DEV_STS)—RO. Hardwired to 0.
Master Data Parity Error Detected (DPED)—R/WC.
0 = No data parity error received.
8
1 = Set when the Gb LAN Controller receives a completion with a data parity error on
the backbone and PCIMD.PER (D25:F0, bit 6) is set.
7 Fast Back to Back Capable (FB2BC)—RO. Hardwired to 0.
6 Reserved
5 66 MHz Capable—RO. Hardwired to 0.
4 Capabilities List—RO. Hardwired to 1. Indicates the presence of a capabilities list.
Interrupt Status—RO. Indicates status of Hot-Plug and power management interrupts
on the root port that result in INTx# message generation.
0 = Interrupt is de-asserted.
3
1 = Interrupt is asserted.
This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the
state of PCICMD.Interrupt Disable bit (D25:F0:04h:bit 10).
2:0 Reserved
436 Datasheet
Gigabit LAN Configuration Registers
11.1.5 RID—Revision Identification Register
(Gigabit LAN—D25:F0)
Offset Address: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
Bit Description
Revision ID—RO. This field indicates the device specific revision identifier. See
7:0
Section 1.3 for the value of the RID Register.
11.1.6 CC—Class Code Register
(Gigabit LAN—D25:F0)
Address Offset: 09h–0Bh Attribute: RO
Default Value: 020000h Size: 24 bits
Bit Description
Class Code—RO. Identifies the device as an Ethernet Adapter.
23:0
020000h = Ethernet Adapter.
11.1.7 CLS—Cache Line Size Register
(Gigabit LAN—D25:F0)
Address Offset: 0Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Cache Line Size—R/W. This field is implemented by PCI devices as a read write field
7:0
for legacy compatibility purposes but has no impact on any device functionality.
11.1.8 PLT—Primary Latency Timer Register
(Gigabit LAN—D25:F0)
Address Offset: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
7:0 Latency Timer (LT)—RO. Hardwired to 0.
Datasheet 437
Gigabit LAN Configuration Registers
11.1.9 HEADTYP—Header Type Register
(Gigabit LAN—D25:F0)
Address Offset: 0Eh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
Header Type (HT)—RO.
7:0
00h = Indicates this is a single function device.
11.1.10 MBARA—Memory Base Address Register A
(Gigabit LAN—D25:F0)
Address Offset: 10h–13h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
The internal CSR registers and memories are accessed as direct memory mapped
offsets from the base address register. SW may only access whole DWord at a time.
Bit Description
Base Address (BA)—R/W. Software programs this field with the base address of this
31:17
region.
16:4 Memory Size (MSIZE)—RO. Memory size is 128 KB.
Prefetchable Memory (PM)—RO. The GbE LAN controller does not implement
3
prefetchable memory.
2:1 Memory Type (MT)—RO. Set to 00b indicating a 32 bit BAR.
0 Memory / IO Space (MIOS)—RO. Set to 0 indicating a Memory Space BAR.
11.1.11 MBARB—Memory Base Address Register B
(Gigabit LAN—D25:F0)
Address Offset: 14h–17h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
The internal registers that are used to access the LAN Space in the External FLASH
device. Access to these registers are direct memory mapped offsets from the base
address register. Software may only access a DWord at a time.
Bit Description
Base Address (BA)—R/W. Software programs this field with the base address of this
31:12
region.
11:4 Memory Size (MSIZE)—RO. Memory size is 4 KB.
Prefetchable Memory (PM)—RO. Set to 0b indicating the Gb LAN controller does not
3
implement prefetchable memory.
2:1 Memory Type (MT)—RO. Set to 00b indicating a 32 bit BAR.
0 Memory / I/O Space (MIOS)—RO. Set to 0 indicating a Memory Space BAR.
438 Datasheet
Gigabit LAN Configuration Registers
11.1.12 MBARC—Memory Base Address Register C
(Gigabit LAN—D25:F0)
Address Offset: 18h–1Bh Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
Internal registers, and memories, can be accessed using I/O operations. There are two
4 Byte registers in the I/O mapping window: Addr Reg and Data Reg. Software may
only access a DWord at a time.
Bit Description
Base Address (BA)—R/W. Software programs this field with the base address of this
31:5
region.
4:1 I/O Size (IOSIZE)—RO. I/O space size is 32 Bytes.
0 Memory / I/O Space (MIOS)—RO. Set to 1 indicating an I/O Space BAR.
11.1.13 SVID—Subsystem Vendor ID Register
(Gigabit LAN—D25:F0)
Address Offset: 2Ch–2Dh Attribute: RO
Default Value: See bit description Size: 16 bits
Bit Description
Subsystem Vendor ID (SVID)—RO. This value may be loaded automatically from
the NVM Word 0Ch upon power up or reset depending on the "Load Subsystem ID" bit
15:0 field in NVM word 0Ah. A value of 8086h is default for this field upon power up if the
NVM does not respond or is not programmed. All functions are initialized to the same
value.
11.1.14 SID—Subsystem ID Register
(Gigabit LAN—D25:F0)
Address Offset: 2Eh–2Fh Attribute: RO
Default Value: See bit description Size: 16 bits
Bit Description
Subsystem ID (SID)—RO. This value may be loaded automatically from the NVM
Word 0Bh upon power up or reset depending on the “Load Subsystem ID” bit field in
15:0
NVM word 0Ah with a default value of 0000h. This value is loadable from NVM word
location 0Ah.
Datasheet 439
Gigabit LAN Configuration Registers
11.1.15 ERBA—Expansion ROM Base Address Register
(Gigabit LAN—D25:F0)
Address Offset: 30h–33h Attribute: RO
Default Value: See bit description Size: 32 bits
Bit Description
Expansion ROM Base Address (ERBA)—RO. This register is used to define the
31:0 address and size information for boot-time access to the optional FLASH memory. If no
Flash memory exists, this register reports 00000000h.
11.1.16 CAPP—Capabilities List Pointer Register
(Gigabit LAN—D25:F0)
Address Offset: 34h Attribute: RO
Default Value: C8h Size: 8 bits
Bit Description
Capabilities Pointer (PTR)—RO. Indicates that the pointer for the first entry in the
7:0
capabilities list is at C8h in configuration space.
11.1.17 INTR—Interrupt Information Register
(Gigabit LAN—D25:F0)
Address Offset: 3Ch–3Dh Attribute: R/W, RO
Default Value: 0100h Size: 16 bits
Function Level Reset: No
Bit Description
Interrupt Pin (IPIN)—RO. Indicates the interrupt pin driven by the GbE LAN
15:8 controller.
01h = The GbE LAN controller implements legacy interrupts on INTA.
Interrupt Line (ILINE)—R/W. Default = 00h. Software written value to indicate which
7:0 interrupt line (vector) the interrupt is connected to. No hardware action is taken on this
register.
11.1.18 MLMG—Maximum Latency / Minimum Grant Register
(Gigabit LAN—D25:F0)
Address Offset: 3Eh–3Fh Attribute: RO
Default Value: 0000h Size: 16 bits
Bit Description
7:0 Maximum Latency/Minimum Grant (MLMG)—RO. Not used. Hardwired to 00h.
440 Datasheet
Gigabit LAN Configuration Registers
11.1.19 STCL—System Time Control Low Register
(Gigabit LAN—D25:F0)
Address Offset: A0h–A3h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
System Time Control Low (STCL)—RO. Lower 32 bits of the system time capture
31:0
used for audio stream synchronization.
11.1.20 STCH—System Time Control High Register
(Gigabit LAN—D25:F0)
Address Offset: A4h–A7h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
System Time Control High (STCH)—RO. Upper 32 bits of the system time capture
31:0
used for audio stream synchronization.
11.1.21 LTRCAP—System Time Control High Register
(Gigabit LAN—D25:F0)
Address Offset: A8h–ABh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:29 Reserved
Maximum Non-Snoop Latency Scale (MNSLS)—R/W. Provides a scale for the value
contained within the Maximum Non-Snoop Latency Value field.
000b = Value times 1 ns
001b = Value times 32 ns
28:26 010b = Value times 1,024 ns
011b = Value times 32,768 ns
100b = Value times 1,048,576 ns
101b = Value times 33,554,432 ns
110b–111b = Reserved
Maximum Non-Snoop Latency (MNSL)—R/W. Specifies the maximum non-snoop
latency that a device is permitted to request. Software should set this to the platform’s
25:16 maximum supported latency or less.
This field is also an indicator of the platforms maximum latency, should an endpoint
send up LTR Latency Values with the Requirement bit not set.
Datasheet 441
Gigabit LAN Configuration Registers
Bit Description
15:13 Reserved
Maximum Snoop Latency Scale (MSLS)—R/W. Provides a scale for the value
contained within the Maximum Snoop Latency Value field.
000b = Value times 1 ns
001b = Value times 32 ns
12:10 010b = Value times 1,024 ns
011b = Value times 32,768 ns
100b = Value times 1,048,576 ns
101b = Value times 33,554,432 ns
110b–111b = Reserved
Maximum Snoop Latency (MSL)—R/W. Specifies the maximum snoop latency that a
device is permitted to request. Software should set this to the platform’s maximum
9:0 supported latency or less.
This field is also an indicator of the platforms maximum latency, should an endpoint
send up LTR Latency Values with the Requirement bit not set.
11.1.22 CLIST1—Capabilities List Register 1
(Gigabit LAN—D25:F0)
Address Offset: C8h–C9h Attribute: RO
Default Value: D001h Size: 16 bits
Bit Description
15:8 Next Capability (NEXT)—RO. Value of D0h indicates the location of the next pointer.
Capability ID (CID)—RO. Indicates the linked list item is a PCI Power Management
7:0
Register.
442 Datasheet
Gigabit LAN Configuration Registers
11.1.23 PMC—PCI Power Management Capabilities Register
(Gigabit LAN—D25:F0)
Address Offset: CAh–CBh Attribute: RO
Default Value: See bit descriptions Size: 16 bits
Function Level Reset: No (Bits 15:11 only)
Bit Description
PME_Support (PMES)—RO. This five-bit field indicates the power states in which the
function may assert PME#. It depend on PM Ena and AUX-PWR bits in word 0Ah in the
NVM:
Condition Functionality Value
15:11 PM Ena=0 No PME at all states 0000b
PM Ena & AUX-PWR=0 PME at D0 and D3hot 01001b
PME at D0, D3hot and
PM Ena & AUX-PWR=1 11001b
D3cold
These bits are not reset by Function Level Reset.
10 D2_Support (D2S)—RO. The D2 state is not supported.
9 D1_Support (D1S)—RO. The D1 state is not supported.
8:6 Aux_Current (AC)—RO. Required current defined in the Data Register.
Device Specific Initialization (DSI)—RO. Set to 1. The GbE LAN Controller requires
5
its device driver to be executed following transition to the D0 un-initialized state.
4 Reserved
3 PME Clock (PMEC)—RO. Hardwired to 0.
Version (VS)—RO. Hardwired to 010b to indicate support for Revision 1.1 of the PCI
2:0
Power Management Specification.
Datasheet 443
Gigabit LAN Configuration Registers
11.1.24 PMCS—PCI Power Management Control and Status
Register (Gigabit LAN—D25:F0)
Address Offset: CCh–CDh Attribute: R/WC, R/W, RO
Default Value: See bit description Size: 16 bits
Function Level Reset: No (Bit 8 only)
Bit Description
PME Status (PMES)—R/WC. This bit is set to 1 when the function detects a wake-up
15
event independent of the state of the PMEE bit. Writing a 1 will clear this bit.
Data Scale (DSC)—RO. This field indicates the scaling factor to be used when
interpreting the value of the Data register.
For the GbE LAN and common functions this field equals 01b (indicating 0.1 watt units)
if the PM is enabled in the NVM, and the Data_Select field is set to 0, 3, 4, 7, (or 8 for
14:13
Function 0). Else it equals 00b.
For the manageability functions this field equals 10b (indicating 0.01 watt units) if the
PM is enabled in the NVM, and the Data_Select field is set to 0, 3, 4, 7. Else it equals
00b.
Data Select (DSL)—R/W. This four-bit field is used to select which data is to be
reported through the Data register (offset CFh) and Data_Scale field. These bits are
writeable only when the Power Management is enabled using NVM.
0h = D0 Power Consumption
12:9 3h = D3 Power Consumption
4h = D0 Power Dissipation
7h = D3 Power Dissipation
8h = Common Power
All other values are reserved.
PME Enable (PMEE)—R/W. If Power Management is enabled in the NVM, writing a 1 to
this register will enable Wakeup. If Power Management is disabled in the NVM, writing a
8
1 to this bit has no affect, and will not set the bit to 1. This bit is not reset by Function
Level Reset.
7:4 Reserved – Returns a value of 0000.
No Soft Reset (NSR)—RO. Defines if the device executed internal reset on the
3
transition to D0. the LAN controller always reports 0 in this field.
2 Reserved – Returns a value of 0b.
Power State (PS)—R/W. This field is used both to determine the current power state
of the GbE LAN Controller and to set a new power state. The values are:
00 = D0 state (default)
1:0 01 = Ignored
10 = Ignored
11 = D3 state (Power Management must be enabled in the NVM or this cycle will be
ignored).
444 Datasheet
Gigabit LAN Configuration Registers
11.1.25 DR—Data Register
(Gigabit LAN—D25:F0)
Address Offset: CFh Attribute: RO
Default Value: See bit description Size: 8 bits
Bit Description
Reported Data (RD)—RO. This register is used to report power consumption and heat
dissipation. This register is controlled by the Data_Select field in the PMCS (Offset CCh,
7:0 bits 12:9), and the power scale is reported in the Data_Scale field in the PMCS (Offset
CCh, bits 14:13). The data of this field is loaded from the NVM if PM is enabled in the
NVM or with a default value of 00h otherwise.
11.1.26 CLIST2—Capabilities List Register 2
(Gigabit LAN—D25:F0)
Address Offset: D0h–D1h Attribute: R/WO, RO
Default Value: E005h Size: 16 bits
Function Level Reset: No (Bits 15:8 only)
Bit Description
Next Capability (NEXT)—R/WO. Value of E0h points to the Function Level Reset
15:8 capability structure.
These bits are not reset by Function Level Reset.
Capability ID (CID)—RO. Indicates the linked list item is a Message Signaled
7:0
Interrupt Register.
11.1.27 MCTL—Message Control Register
(Gigabit LAN—D25:F0)
Address Offset: D2h–D3h Attribute: R/W, RO
Default Value: 0080h Size: 16 bits
Bit Description
15:8 Reserved
64-bit Capable (CID)—RO. Set to 1 to indicate that the GbE LAN Controller is capable
7
of generating 64-bit message addresses.
Multiple Message Enable (MME)—RO. Returns 000b to indicate that the GbE LAN
6:4
controller only supports a single message.
Multiple Message Capable (MMC)—RO. The GbE LAN controller does not support
3:1
multiple messages.
MSI Enable (MSIE)—R/W.
0 0 = MSI generation is disabled.
1 = The Gb LAN controller will generate MSI for interrupt assertion instead of INTx
signaling.
Datasheet 445
Gigabit LAN Configuration Registers
11.1.28 MADDL—Message Address Low Register
(Gigabit LAN—D25:F0)
Address Offset: D4h–D7h Attribute: R/W
Default Value: See bit description Size: 32 bits
Bit Description
Message Address Low (MADDL)—R/W. Written by the system to indicate the lower
31:0 32 bits of the address to use for the MSI memory write transaction. The lower two bits
will always return 0 regardless of the write operation.
11.1.29 MADDH—Message Address High Register
(Gigabit LAN—D25:F0)
Address Offset: D8h–dBh Attribute: R/W
Default Value: See bit description Size: 32 bits
Bit Description
Message Address High (MADDH)—R/W. Written by the system to indicate the upper
31:0
32 bits of the address to use for the MSI memory write transaction.
11.1.30 MDAT—Message Data Register
(Gigabit LAN—D25:F0)
Address Offset: DCh–DDh Attribute: R/W
Default Value: See bit description Size: 16 bits
Bit Description
Message Data (MDAT)—R/W. Written by the system to indicate the lower 16 bits of
31:0 the data written in the MSI memory write DWord transaction. The upper 16 bits of the
transaction are written as 0000h.
11.1.31 FLRCAP—Function Level Reset Capability
(Gigabit LAN—D25:F0)
Address Offset: E0h–E1h Attribute: RO
Default Value: 0009h Size: 16 bits
Bit Description
Next Pointer—RO. This field provides an offset to the next capability item in the
15:8
capability list. The value of 00h indicates the last item in the list.
Capability ID—RO. The value of this field depends on the FLRCSSEL bit.
13h = If FLRCSSEL = 0
7:0 09h = If FLRCSSEL = 1, indicating vendor specific capability.
FLRCSSEL is located at RCBA + 3410(bit 12). See Chapter 10-Chipset Configuration
Registers.
446 Datasheet
Gigabit LAN Configuration Registers
11.1.32 FLRCLV—Function Level Reset Capability Length and
Version Register (Gigabit LAN—D25:F0)
Address Offset: E2h–E3h Attribute: R/WO, RO
Default Value: See Description. Size: 16 bits
Function Level Reset: No (Bits 9:8 Only When FLRCSSEL = 0)
When FLRCSSEL = 0, this register is defined as follows:
Bit Description
15:10 Reserved
Function Level Reset Capability—R/WO.
9 1 = Support for Function Level Reset.
This bit is not reset by Function Level Reset.
TXP Capability—R/WO.
8 1 = Indicates support for the Transactions Pending (TXP) bit. TXP must be supported if
FLR is supported.
Capability Length—RO. The value of this field indicates the number of bytes of the
7:0 vendor specific capability as require by the PCI specification. It has the value of 06h for
the Function Level Reset capability.
When FLRCSSEL = 1, this register is defined as follows:
Bit Description
Vendor Specific Capability ID—RO. A value of 2h in this field identifies this capability
15:12
as Function Level Reset.
Capability Version—RO. The value of this field indicates the version of the Function
11:8
Level Reset Capability. Default is 0h.
Capability Length—RO. The value of this field indicates the number of bytes of the
7:0 vendor specific capability as require by the PCI specification. It has the value of 06h for
the Function Level Reset capability.
11.1.33 DEVCTRL—Device Control Register (Gigabit LAN—D25:F0)
Address Offset: E4–E5h Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:9 Reserved
Transactions Pending (TXP)—R/W.
1 = Indicates the controller has issued Non-Posted requests which have not been
8 completed.
0 = Indicates that completions for all Non-Posted requests have been received.
7:1 Reserved
Initiate Function Level Reset—R/W. This bit is used to initiate an FLT transition. A
0 write of 1 initiates the transition. Since hardware must not respond to any cycles until
Function Level Reset completion, the value read by software from this bit is 0.
Datasheet 447
Gigabit LAN Configuration Registers
11.2 Gigabit LAN Capabilities and Status Registers
(CSR)
The internal CSR registers and memories are accessed as direct memory mapped
offsets from the base address register in Section 11.1.10. Software may only access
whole DWord at a time.
Note: Register address locations that are not shown in Table 11-1 should be treated as
Reserved.
Table 11-2. Gigabit LAN Capabilities and Status Registers Address Map
(Gigabit LAN—MBARA)
MBARA +
Mnemonic Register Name Default Attribute
Offset
Gigabit Ethernet Capabilities
00h–03h GBECSR_00 00100241h R/W
and Status Register 00
Gigabit Ethernet Capabilities
18h–1Bh GBECSR_18 01501000h R/W/SN
and Status Register 18
Gigabit Ethernet Capabilities
20h–23h GBECSR_20 1000XXXXh R/W/V
and Status Register 20
Gigabit Ethernet Capabilities
2Ch–2Fh GBECSR_2C 00000000h R/W
and Status Register 2C
Gigabit Ethernet Capabilities
F00h–F03h GBECSR_F00 00010008h R/W/V
and Status Register F00
Gigabit Ethernet Capabilities
F10h–F13h GBECSR_F10 0004000Ch R/W/SN
and Status Register F10
Gigabit Ethernet Capabilities
5400h–5403h GBECSR_5400 XXXXXXXXh R/W
and Status Register 5400
Gigabit Ethernet Capabilities
5404h–5407h GBECSR_5404 XXXXXXXXh R/W
and Status Register 5404
Gigabit Ethernet Capabilities
5800h–5803h GBECSR_5800 00000008h R/W/SN
and Status Register 5800
Gigabit Ethernet Capabilities
5B54h–5B57h GBECSR_5B54 60000040h RO
and Status Register 5B54
11.2.1 GBECSR_00—Gigabit Ethernet Capabilities and Status
Register 00
Address Offset: MBARA + 00h Attribute: R/W
Default Value: 00100241h Size: 32 bit
Bit Description
31:25 Reserved
PHY Power Down (PHYPDN)—R/W.
24 When cleared (0b), the PHY power down setting is controlled by the internal logic of
PCH.
23:0 Reserved
448 Datasheet
Gigabit LAN Configuration Registers
11.2.2 GBECSR_18—Gigabit Ethernet Capabilities and Status
Register 18
Address Offset: MBARA + 18h Attribute: R/W/SN
Default Value: 01501000h Size: 32 bit
Bit Description
31:21 Reserved
PHY Power Down Enable (PHYPDEN)—R/W/SN.
20 When set, this bit enables the PHY to enter a low-power state when the LAN controller
is at the DMoff/D3 or with no WOL.
19:0 Reserved
11.2.3 GBECSR_20—Gigabit Ethernet Capabilities and Status
Register 20
Address Offset: MBARA + 20h Attribute: R/W/V
Default Value: 1000XXXXh Size: 32 bit
Bit Description
WAIT—RO.
31 Set to 1 by the Gigabit Ethernet Controller to indicate that a PCI Express* to SMBus
transition is taking place. The ME/Host should not issue new MDIC transactions while
this bit is set to 1. This bit is auto cleared by HW after the transition has occurred.
Error—R/W/V.
30 Set to 1 by the Gigabit Ethernet Controller when it fails to complete an MDI read.
Software should make sure this bit is clear before making an MDI read or write
command.
29 Reserved
Ready Bit (RB)—R/W/V.
28 Set to 1 by the Gigabit Ethernet Controller at the end of the MDI transaction. This bit
should be reset to 0 by software at the same time the command is written.
MDI Type—R/W/V.
01 = MDI Write
27:26
10 = MDI Read
All other values are reserved.
25:21 LAN Connected Device Address (PHYADD)—R/W/V.
20:16 LAN Connected Device Register Address (PHYREGADD)—R/W/V.
15:0 DATA—R/W/V.
Datasheet 449
Gigabit LAN Configuration Registers
11.2.4 GBECSR_2C—Gigabit Ethernet Capabilities and Status
Register 2C
Address Offset: MBARA + 2Ch Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
WOL Indication Valid (WIV)—R/W.
31 Set to 1 by BIOS to indicate that the WOL indication setting in bit 30 of this register is
valid.
WOL Enable Setting by BIOS (WESB)—R/W.
30 1 = WOL Enabled in BIOS.
0 = WOL Disabled in BIOS.
29:0 Reserved
11.2.5 GBECSR_F00—Gigabit Ethernet Capabilities and Status
Register F00
Address Offset: MBARA + F00h Attribute: R/W/V
Default Value: 00010008h Size: 32 bits
Bit Description
31:6 Reserved
SW Semaphore FLAG (SWFLAG)—R/W/V.
5 This bit is set by the device driver to gain access permission to shared CSR registers
with the firmware and hardware.
4:0 Reserved
450 Datasheet
Gigabit LAN Configuration Registers
11.2.6 GBECSR_F10—Gigabit Ethernet Capabilities and Status
Register F10
Address Offset: MBARA + F10h Attribute: R/W/SN
Default Value: 0004000Ch Size: 32 bits
Bit Description
31:7 Reserved
Global GbE Disable (GGD)—R/W/SN.
6
Prevents the PHY from auto-negotiating 1000Mb/s link in all power states.
5:4 Reserved
GbE Disable at non D0a—R/W/SN.
3 Prevents the PHY from auto-negotiating 1000Mb/s link in all power states except D0a.
This bit must be set since GbE is not supported in Sx states.
LPLU in non D0a (LPLUND)—R/W/SN.
2 Enables the PHY to negotiate for the slowest possible link in all power states except
D0a.
LPLU in D0a (LPLUD)—R/W/SN.
1 Enables the PHY to negotiate for the slowest possible link in all power states. This bit
overrides bit 2.
0 Reserved
11.2.7 GBECSR_5400—Gigabit Ethernet Capabilities and Status
Register 5400
Address Offset: MBARA + 5400h Attribute: R/W
Default Value: XXXXXXXXh Size: 32 bits
Bit Description
Receive Address Low (RAL)—R/W.
31:0
The lower 32 bits of the 48 bit Ethernet Address.
11.2.8 GBECSR_5404—Gigabit Ethernet Capabilities and Status
Register 5404
Address Offset: MBARA + 5404h Attribute: R/W
Default Value: XXXXXXXXh Size: 32 bits
Bit Description
31 Address Valid—R/W.
30:16 Reserved
Receive Address High (RAH)—R/W.
15:0
The lower 16 bits of the 48 bit Ethernet Address.
Datasheet 451
Gigabit LAN Configuration Registers
11.2.9 GBECSR_5800—Gigabit Ethernet Capabilities and Status
Register 5800
Address Offset: MBARA + 5800h Attribute: R/W/SN
Default Value: 00000008h Size: 32 bits
Bit Description
31:1 Reserved
Advanced Power Management Enable (APME)—R/W/SN.
0 1 = APM Wakeup is enabled
0 = APM Wakeup is disabled
11.2.10 GBECSR_5B54—Gigabit Ethernet Capabilities and Status
Register 5B54
Address Offset: MBARA + 5B54h Attribute: RO
Default Value: 60000040h Size: 32 bits
Bit Description
31:16 Reserved
Firmware Valid Bit (FWVAL)—RO.
15 1 = Firmware is ready
0 = Firmware is not ready
14:0 Reserved
§§
452 Datasheet
LPC Interface Bridge Registers (D31:F0)
12 LPC Interface Bridge Registers
(D31:F0)
The LPC bridge function of the PCH resides in PCI D31:F0. This function contains many
other functional units, such as DMA and Interrupt controllers, Timers, Power
Management, System Management, GPIO, RTC, and LPC Configuration Registers.
Registers and functions associated with other functional units are described in their
respective sections.
12.1 PCI Configuration Registers (LPC I/F—D31:F0)
Note: Address locations that are not shown should be treated as Reserved.
.
Table 12-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 1 of 2)
Offset Mnemonic Register Name Default Attribute
00h–01h VID Vendor Identification 8086h RO
See register
02h–03h DID Device Identification RO
description
04h–05h PCICMD PCI Command 0007h R/W, RO
06h–07h PCISTS PCI Status 0210h R/WC, RO
See register
08h RID Revision Identification R/WO
description
09h PI Programming Interface 00h RO
0Ah SCC Sub Class Code 01h RO
0Bh BCC Base Class Code 06h RO
0Dh PLT Primary Latency Timer 00h RO
0Eh HEADTYP Header Type 80h RO
2Ch–2Fh SS Sub System Identifiers 00000000h R/WO
40h–43h PMBASE ACPI Base Address 00000001h R/W, RO
44h ACPI_CNTL ACPI Control 00h R/W
48h–4Bh GPIOBASE GPIO Base Address 00000001h R/W, RO
4Ch GC GPIO Control 00h R/W
60h–63h PIRQ[n]_ROUT PIRQ[A,B,C,D] Routing Control 80808080h R/W
64h SIRQ_CNTL Serial IRQ Control 10h R/W, RO
68h–6Bh PIRQ[n]_ROUT PIRQ[E,F,G,H] Routing Control 80808080h R/W
6Ch–6Dh LPC_IBDF IOxAPIC Bus:Device:Function 00F8h R/W
70h–7Fh LPC_HnBDF HPET Configuration 00F8h R/W
80h LPC_I/O_DEC I/O Decode Ranges 0000h R/W
82h–83h LPC_EN LPC I/F Enables 0000h R/W
84h–87h GEN1_DEC LPC I/F Generic Decode Range 1 00000000h R/W
Datasheet 453
LPC Interface Bridge Registers (D31:F0)
Table 12-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 2 of 2)
Offset Mnemonic Register Name Default Attribute
88h–8Bh GEN2_DEC LPC I/F Generic Decode Range 2 00000000h R/W
8Ch–8Eh GEN3_DEC LPC I/F Generic Decode Range 3 00000000h R/W
90h–93h GEN4_DEC LPC I/F Generic Decode Range 4 00000000h R/W
USB Legacy Keyboard / Mouse RO, R/WC,
94h–97h ULKMC 00002000h
Control R/W
98h–9Bh LGMR LPC I/F Generic Memory Range 00000000h R/W
Power Management (See
A0h–CFh
Section 12.8.1)
D0h–D3h BIOS_SEL1 BIOS Select 1 00112233h R/W, RO
D4h–D5h BIOS_SEL2 BIOS Select 2 4567h R/W
D8h–D9h BIOS_DEC_EN1 BIOS Decode Enable 1 FFCFh R/W, RO
R/WLO, R/W,
DCh BIOS_CNTL BIOS Control 20h
RO
E0h–E1h FDCAP Feature Detection Capability ID 0009h RO
Feature Detection Capability
E2h FDLEN 0Ch RO
Length
E3h FDVER Feature Detection Version 10h RO
E4h–E7h FVECIDX Feature Vector Index 00000000h R/W
See
E8h–EBh FVECD Feature Vector Data RO
Description
F0h–F3h RCBA Root Complex Base Address 00000000h R/W
12.1.1 VID—Vendor Identification Register (LPC I/F—D31:F0)
Offset Address: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bits
Lockable: No Power Well: Core
Bit Description
15:0 Vendor ID—RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
12.1.2 DID—Device Identification Register (LPC I/F—D31:F0)
Offset Address: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bits
Lockable: No Power Well: Core
Bit Description
Device ID—RO. This is a 16-bit value assigned to the PCH LPC bridge. See
15:0
Section 1.3 for the value of the DID Register.
454 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.1.3 PCICMD—PCI COMMAND Register (LPC I/F—D31:F0)
Offset Address: 04h–05h Attribute: R/W, RO
Default Value: 0007h Size: 16 bits
Lockable: No Power Well: Core
Bit Description
15:10 Reserved
9 Fast Back to Back Enable (FBE)—RO. Hardwired to 0.
8 SERR# Enable (SERR_EN)—R/W. The LPC bridge generates SERR# if this bit is set.
7 Wait Cycle Control (WCC)—RO. Hardwired to 0.
Parity Error Response Enable (PERE)—R/W.
0 = No action is taken when detecting a parity error.
6
1 = Enables the PCH LPC bridge to respond to parity errors detected on backbone
interface.
5 VGA Palette Snoop (VPS)—RO. Hardwired to 0.
4 Memory Write and Invalidate Enable (MWIE)—RO. Hardwired to 0.
3 Special Cycle Enable (SCE)—RO. Hardwired to 0.
2 Bus Master Enable (BME)—RO. Bus Masters cannot be disabled.
1 Memory Space Enable (MSE)—RO. Memory space cannot be disabled on LPC.
0 I/O Space Enable (IOSE)—RO. I/O space cannot be disabled on LPC.
12.1.4 PCISTS—PCI Status Register (LPC I/F—D31:F0)
Offset Address: 06h–07h Attribute: RO, R/WC
Default Value: 0210h Size: 16 bits
Lockable: No Power Well: Core
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit Description
Detected Parity Error (DPE)—R/WC. Set when the LPC bridge detects a parity
error on the internal backbone. Set even if the PCICMD.PERE bit (D31:F0:04, bit 6) is
15 0.
0 = Parity Error Not detected.
1 = Parity Error detected.
Signaled System Error (SSE)—R/WC. Set when the LPC bridge signals a system
14
error to the internal SERR# logic.
Master Abort Status (RMA)—R/WC.
0 = Unsupported request status not received.
13
1 = The bridge received a completion with unsupported request status from the
backbone.
Received Target Abort (RTA)—R/WC.
12 0 = Completion abort not received.
1 = Completion with completion abort received from the backbone.
Datasheet 455
LPC Interface Bridge Registers (D31:F0)
Bit Description
Signaled Target Abort (STA)—R/WC.
0 = Target abort Not generated on the backbone.
11
1 = LPC bridge generated a completion packet with target abort status on the
backbone.
DEVSEL# Timing Status (DEV_STS)—RO.
10:9
01 = Medium Timing.
Data Parity Error Detected (DPED)—R/WC.
0 = All conditions listed below Not met.
1 = Set when all three of the following conditions are met:
8 • LPC bridge receives a completion packet from the backbone from a previous
request,
• Parity error has been detected (D31:F0:06, bit 15)
• PCICMD.PERE bit (D31:F0:04, bit 6) is set.
7 Fast Back to Back Capable (FBC)—RO. Hardwired to 0.
6 Reserved
5 66 MHz Capable (66MHZ_CAP)—RO. Hardwired to 0.
4 Capabilities List (CLIST)—RO. Capability list exists on the LPC bridge.
3 Interrupt Status (IS)—RO. The LPC bridge does not generate interrupts.
2:0 Reserved
12.1.5 RID—Revision Identification Register (LPC I/F—D31:F0)
Offset Address: 08h Attribute: R/WO
Default Value: See bit description Size: 8 bits
Bit Description
Revision ID (RID)—R/WO. This field indicates the device specific revision identifier.
7:0
See Section 1.3 for the value of the RID Register.
12.1.6 PI—Programming Interface Register (LPC I/F—D31:F0)
Offset Address: 09h Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
7:0 Programming Interface—RO.
12.1.7 SCC—Sub Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Ah Attribute: RO
Default Value: 01h Size: 8-bit
Bit Description
Sub Class Code—RO. 8-bit value that indicates the category of bridge for the LPC
7:0 bridge.
01h = PCI-to-ISA bridge.
456 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.1.8 BCC—Base Class Code Register (LPC I/F—D31:F0)
Offset Address: 0Bh Attribute: RO
Default Value: 06h Size: 8-bit
Bit Description
Base Class Code—RO. 8-bit value that indicates the type of device for the LPC bridge.
7:0
06h = Bridge device.
12.1.9 PLT—Primary Latency Timer Register (LPC I/F—D31:F0)
Offset Address: 0Dh Attribute: RO
Default Value: 00h Size: 8-bit
Bit Description
7:3 Master Latency Count (MLC)—Reserved
2:0 Reserved
12.1.10 HEADTYP—Header Type Register (LPC I/F—D31:F0)
Offset Address: 0Eh Attribute: RO
Default Value: 80h Size: 8-bit
Bit Description
7 Multi-Function Device—RO. This bit is 1 to indicate a multi-function device.
Header Type—RO. This 7-bit field identifies the header layout of the configuration
6:0
space.
Datasheet 457
LPC Interface Bridge Registers (D31:F0)
12.1.11 SS—Sub System Identifiers Register (LPC I/F—D31:F0)
Offset Address: 2Ch–2Fh Attribute: R/WO
Default Value: 00000000h Size: 32 bits
This register is initialized to logic 0 by the assertion of PLTRST#. This register can be
written only once after PLTRST# de-assertion.
Bit Description
Subsystem ID (SSID)—R/WO. This is written by BIOS. No hardware action taken on
31:16
this value.
Subsystem Vendor ID (SSVID)—R/WO. This is written by BIOS. No hardware action
15:0
taken on this value.
12.1.12 CAPP—Capability List Pointer Register (LPC I/F—D31:F0)
Offset Address: 34h Attribute: RO
Default Value: E0h Size: 8 bits
Bit Description
7:0 Capability Pointer (CP)—RO. Indicates the offset of the first Capability Item.
12.1.13 PMBASE—ACPI Base Address Register (LPC I/F—D31:F0)
Offset Address: 40h–43h Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
Lockable: No Usage: ACPI, Legacy
Power Well: Core
Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. These
registers can be mapped anywhere in the 64-K I/O space on 128-byte boundaries.
Bit Description
31:16 Reserved
Base Address—R/W. This field provides 128 bytes of I/O space for ACPI, GPIO, and
15:7
TCO logic. This is placed on a 128-byte boundary.
6:1 Reserved
0 Resource Type Indicator (RTE)—RO. Hardwired to 1 to indicate I/O space.
458 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.1.14 ACPI_CNTL—ACPI Control Register (LPC I/F—D31:F0)
Offset Address: 44h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Usage: ACPI, Legacy
Power Well: Core
Bit Description
ACPI Enable (ACPI_EN)—R/W.
0 = Disable.
7 1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the
ACPI power management function is enabled. The APM power management ranges
(B2/B3h) are always enabled and are not affected by this bit.
6:3 Reserved
SCI IRQ Select (SCI_IRQ_SEL)—R/W.
Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI
must be routed to IRQ9–11, and that interrupt is not sharable with the SERIRQ stream,
but is shareable with other PCI interrupts. If using the APIC, the SCI can also be
mapped to IRQ20–23, and can be shared with other interrupts.
Bits SCI Map
000b IRQ9
001b IRQ10
010b IRQ11
011b Reserved
2:0
IRQ20 (Only available if APIC
100b
enabled)
IRQ21 (Only available if APIC
101b
enabled)
IRQ22 (Only available if APIC
110b
enabled)
IRQ23 (Only available if APIC
111b
enabled)
When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be
programmed for active-high reception. When the interrupt is mapped to APIC interrupts
20 through 23, the APIC should be programmed for active-low reception.
12.1.15 GPIOBASE—GPIO Base Address Register (LPC I/F—
D31:F0)
Offset Address: 48h–4Bh Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved. Always 0.
15:7 Base Address (BA)—R/W. Provides the 128 bytes of I/O space for GPIO.
6:1 Reserved. Always 0.
0 RO. Hardwired to 1 to indicate I/O space.
Datasheet 459
LPC Interface Bridge Registers (D31:F0)
12.1.16 GC—GPIO Control Register (LPC I/F—D31:F0)
Offset Address: 4Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:5 Reserved
GPIO Enable (EN)—R/W. This bit enables/disables decode of the I/O range pointed to
by the GPIO Base Address register (D31:F0:48h) and enables the GPIO function.
4
0 = Disable.
1 = Enable.
3:1 Reserved
GPIO Lockdown Enable (GLE)—R/W. This bit enables lockdown of the following GPIO
registers:
• Offset 00h: GPIO_USE_SEL
• Offset 04h: GP_IO_SEL
• Offset 0Ch: GP_LVL
• Offset 30h: GPIO_USE_SEL2
• Offset 34h: GP_IO_SEL2
• Offset 38h: GP_LVL2
0
• Offset 40h: GPIO_USE_SEL3
• Offset 44h: GP_IO_SEL3
• Offset 48h: GP_LVL3
• Offset 60h: GP_RST_SEL
0 = Disable.
1 = Enable.
When this bit is written from 1-to-0, an SMI# is generated, if enabled. This ensures
that only SMM code can change the above GPIO registers after they are locked down.
460 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.1.17 PIRQ[n]_ROUT—PIRQ[A,B,C,D] Routing Control Register
(LPC I/F—D31:F0)
Offset Address: PIRQA – 60h, PIRQB – 61h, Attribute: R/W
PIRQC – 62h, PIRQD – 63h
Default Value: 80h Size: 8 bits
Lockable: No Power Well: Core
Bit Description
Interrupt Routing Enable (IRQEN)—R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts
specified in bits[3:0].
1 = The PIRQ is not routed to the 8259.
7
NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are
being used. The value of this bit may subsequently be changed by the OS
when setting up for I/O APIC interrupt delivery mode.
6:4 Reserved
IRQ Routing—R/W. (ISA compatible.)
Value IRQ Value IRQ
0000b Reserved 1000b Reserved
0001b Reserved 1001b IRQ9
0010b Reserved 1010b IRQ10
3:0
0011b IRQ3 1011b IRQ11
0100b IRQ4 1100b IRQ12
0101b IRQ5 1101b Reserved
0110b IRQ6 1110b IRQ14
0111b IRQ7 1111b IRQ15
Datasheet 461
LPC Interface Bridge Registers (D31:F0)
12.1.18 SIRQ_CNTL—Serial IRQ Control Register
(LPC I/F—D31:F0)
Offset Address: 64h Attribute: R/W, RO
Default Value: 10h Size: 8 bits
Lockable: No Power Well: Core
Bit Description
Serial IRQ Enable (SIRQEN)—R/W.
7 0 = The buffer is input only and internally SERIRQ will be a 1.
1 = Serial IRQs will be recognized. The SERIRQ pin will be configured as SERIRQ.
Serial IRQ Mode Select (SIRQMD)—R/W.
0 = The serial IRQ machine will be in quiet mode.
1 = The serial IRQ machine will be in continuous mode.
6
NOTE: For systems using Quiet Mode, this bit should be set to 1 (Continuous Mode) for
at least one frame after coming out of reset before switching back to Quiet
Mode. Failure to do so will result in the PCH not recognizing SERIRQ interrupts.
Serial IRQ Frame Size (SIRQSZ)—RO. Fixed field that indicates the size of the
5:2
SERIRQ frame as 21 frames.
Start Frame Pulse Width (SFPW)—R/W. This is the number of PCI clocks that the
SERIRQ pin will be driven low by the serial IRQ machine to signal a start frame. In
continuous mode, the PCH will drive the start frame for the number of clocks specified.
In quiet mode, the PCH will drive the start frame for the number of clocks specified
minus one, as the first clock was driven by the peripheral.
1:0
00 = 4 clocks
01 = 6 clocks
10 = 8 clocks
11 = Reserved
462 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.1.19 PIRQ[n]_ROUT—PIRQ[E,F,G,H] Routing Control Register
(LPC I/F—D31:F0)
Offset Address: PIRQE – 68h, PIRQF – 69h, Attribute: R/W
PIRQG – 6Ah, PIRQH – 6Bh
Default Value: 80h Size: 8 bits
Lockable: No Power Well: Core
Bit Description
Interrupt Routing Enable (IRQEN)—R/W.
0 = The corresponding PIRQ is routed to one of the ISA-compatible interrupts specified
in bits[3:0].
1 = The PIRQ is not routed to the 8259.
7
NOTE: BIOS must program this bit to 0 during POST for any of the PIRQs that are
being used. The value of this bit may subsequently be changed by the OS when
setting up for I/O APIC interrupt delivery mode.
6:4 Reserved
IRQ Routing—R/W. (ISA compatible.)
Value IRQ Value IRQ
0000b Reserved 1000b Reserved
0001b Reserved 1001b IRQ9
3:0 0010b Reserved 1010b IRQ10
0011b IRQ3 1011b IRQ11
0100b IRQ4 1100b IRQ12
0101b IRQ5 1101b Reserved
0110b IRQ6 1110b IRQ14
0111b IRQ7 1111b IRQ15
12.1.20 LPC_IBDF—IOxAPIC Bus:Device:Function
(LPC I/F—D31:F0)
Offset Address: 6Ch–6Dh Attribute: R/W
Default Value: 00F8h Size: 16 bits
Bit Description
IOxAPIC Bus:Device:Function (IBDF)—R/W. this field specifies the
bus:device:function that PCH’s IOxAPIC will be using for the following:
• As the Requester ID when initiating Interrupt Messages to the processor.
• As the Completer ID when responding to the reads targeting the IOxAPIC’s
Memory-Mapped I/O registers.
The 16-bit field comprises the following:
15:0 Bits Description
15:8 Bus Number
7:3 Device Number
2:0 Function Number
This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can program this
field to provide a unique bus:device:function number for the internal IOxAPIC.
Datasheet 463
LPC Interface Bridge Registers (D31:F0)
12.1.21 LPC_HnBDF—HPET n Bus:Device:Function
(LPC I/F—D31:F0)
Address Offset H0BDF 70h–71h
H1BDF 72h–73h
H2BDF 74h–75h
H3BDF 76h–77h
H4BDF 78h–79h
H5BDF 7Ah–7Bh
H6BDF 7Ch–7Dh
H7BDF 7Eh–7Fh Attribute: R/W
Default Value: 00F8h Size: 16 bits
Bit Description
HPET n Bus:Device:Function (HnBDF)—R/W. This field specifies the
bus:device:function that the PCH’s HPET n will be using in the following:
• As the Requester ID when initiating Interrupt Messages to the processor
• As the Completer ID when responding to the reads targeting the corresponding
HPET’s Memory-Mapped I/O registers
The 16-bit field comprises the following:
15:0 Bits Description
15:8 Bus Number
7:3 Device Number
2:0 Function Number
This field is default to Bus 0: Device 31: Function 0 after reset. BIOS shall program this
field accordingly if unique bus:device:function number is required for the
corresponding HPET.
464 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.1.22 LPC_I/O_DEC—I/O Decode Ranges Register
(LPC I/F—D31:F0)
Offset Address: 80h Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:13 Reserved
FDD Decode Range—R/W. Determines which range to decode for the FDD Port
12 0 = 3F0h–3F5h, 3F7h (Primary)
1 = 370h–375h, 377h (Secondary)
11:10 Reserved
LPT Decode Range—R/W. This field determines which range to decode for the LPT
Port.
00 = 378h–37Fh and 778h–77Fh
9:8
01 = 278h–27Fh (port 279h is read only) and 678h–67Fh
10 = 3BCh –3BEh and 7BCh–7BEh
11 = Reserved
7 Reserved
COMB Decode Range—R/W. This field determines which range to decode for the
COMB Port.
000 = 3F8h–3FFh (COM1)
001 = 2F8h–2FFh (COM2)
010 = 220h–227h
6:4
011 = 228h–22Fh
100 = 238h–23Fh
101 = 2E8h–2EFh (COM4)
110 = 338h–33Fh
111 = 3E8h–3EFh (COM3)
3 Reserved
COMA Decode Range—R/W. This field determines which range to decode for the
COMA Port.
000 = 3F8h–3FFh (COM1)
001 = 2F8h–2FFh (COM2)
010 = 220h–227h
2:0
011 = 228h–22Fh
100 = 238h–23Fh
101 = 2E8h–2EFh (COM4)
110 = 338h–33Fh
111 = 3E8h–3EFh (COM3)
Datasheet 465
LPC Interface Bridge Registers (D31:F0)
12.1.23 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)
Offset Address: 82h–83h Attribute: R/W
Default Value: 0000h Size: 16 bits
Power Well: Core
Bit Description
15:14 Reserved
CNF2_LPC_EN—R/W. Microcontroller Enable #2.
0 = Disable.
13
1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This
range is used for a microcontroller.
CNF1_LPC_EN—R/W. Super I/O Enable.
0 = Disable.
12
1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This
range is used for Super I/O devices.
MC_LPC_EN—R/W. Microcontroller Enable # 1.
11 0 = Disable.
1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This
range is used for a microcontroller.
KBC_LPC_EN—R/W. Keyboard Enable.
0 = Disable.
10
1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This
range is used for a microcontroller.
GAMEH_LPC_EN—R/W. High Gameport Enable
9 0 = Disable.
1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This
range is used for a gameport.
GAMEL_LPC_EN—R/W. Low Gameport Enable
0 = Disable.
8
1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This
range is used for a gameport.
7:4 Reserved
FDD_LPC_EN—R/W. Floppy Drive Enable
0 = Disable.
3
1 = Enables the decoding of the FDD range to the LPC interface. This range is selected
in the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 12).
LPT_LPC_EN—R/W. Parallel Port Enable
2 0 = Disable.
1 = Enables the decoding of the LPTrange to the LPC interface. This range is selected in
the LPC_FDD/LPT Decode Range Register (D31:F0:80h, bit 9:8).
COMB_LPC_EN—R/W. Com Port B Enable
0 = Disable.
1
1 = Enables the decoding of the COMB range to the LPC interface. This range is
selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 6:4).
COMA_LPC_EN—R/W. Com Port A Enable
0 = Disable.
0
1 = Enables the decoding of the COMA range to the LPC interface. This range is
selected in the LPC_COM Decode Range Register (D31:F0:80h, bits 3:2).
466 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.1.24 GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0)
Offset Address: 84h–87h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Power Well: Core
Bit Description
31:24 Reserved
Generic I/O Decode Range Address[7:2] Mask—R/W. A 1 in any bit position
indicates that any value in the corresponding address bit in a received cycle will be
23:18 treated as a match. The corresponding bit in the Address field, below, is ignored. The
mask is only provided for the lower 6 bits of the DWord address, allowing for decoding
blocks up to 256 bytes in size.
17:16 Reserved
Generic I/O Decode Range 1 Base Address (GEN1_BASE)—R/W.
15:2
NOTE: The PCH does not provide decode down to the word or byte level
1 Reserved
Generic Decode Range 1 Enable (GEN1_EN)—R/W.
0 0 = Disable.
1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F
12.1.25 GEN2_DEC—LPC I/F Generic Decode Range 2 Register
(LPC I/F—D31:F0)
Offset Address: 88h–8Bh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Power Well: Core
Bit Description
31:24 Reserved
Generic I/O Decode Range Address[7:2] Mask—R/W. A 1 in any bit position
indicates that any value in the corresponding address bit in a received cycle will be
23:18 treated as a match. The corresponding bit in the Address field, below, is ignored. The
mask is only provided for the lower 6 bits of the DWord address, allowing for decoding
blocks up to 256 bytes in size.
17:16 Reserved
Generic I/O Decode Range 2 Base Address (GEN1_BASE)—R/W.
15:2
NOTE: The PCH does not provide decode down to the word or byte level.
1 Reserved
Generic Decode Range 2 Enable (GEN2_EN)—R/W.
0 0 = Disable.
1 = Enable the GEN2 I/O range to be forwarded to the LPC I/F
Datasheet 467
LPC Interface Bridge Registers (D31:F0)
12.1.26 GEN3_DEC—LPC I/F Generic Decode Range 3 Register
(LPC I/F—D31:F0)
Offset Address: 8Ch–8Eh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Power Well: Core
Bit Description
31:24 Reserved
Generic I/O Decode Range Address[7:2] Mask—R/W. A 1 in any bit position
indicates that any value in the corresponding address bit in a received cycle will be
23:18 treated as a match. The corresponding bit in the Address field, below, is ignored. The
mask is only provided for the lower 6 bits of the DWord address, allowing for decoding
blocks up to 256 bytes in size.
17:16 Reserved
Generic I/O Decode Range 3 Base Address (GEN3_BASE)—R/W.
15:2
NOTE: The PCH Does not provide decode down to the word or byte level
1 Reserved
Generic Decode Range 3 Enable (GEN3_EN)—R/W.
0 0 = Disable.
1 = Enable the GEN3 I/O range to be forwarded to the LPC I/F
12.1.27 GEN4_DEC—LPC I/F Generic Decode Range 4 Register
(LPC I/F—D31:F0)
Offset Address: 90h–93h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Power Well: Core
Bit Description
31:24 Reserved
Generic I/O Decode Range Address[7:2] Mask—R/W. A 1 in any bit position
indicates that any value in the corresponding address bit in a received cycle will be
23:18 treated as a match. The corresponding bit in the Address field, below, is ignored. The
mask is only provided for the lower 6 bits of the DWord address, allowing for decoding
blocks up to 256 bytes in size.
17:16 Reserved
Generic I/O Decode Range 4 Base Address (GEN4_BASE)—R/W.
15:2
NOTE: The PCH Does not provide decode down to the word or byte level
1 Reserved
Generic Decode Range 4 Enable (GEN4_EN)—R/W.
0 0 = Disable.
1 = Enable the GEN4 I/O range to be forwarded to the LPC I/F
468 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.1.28 ULKMC—USB Legacy Keyboard / Mouse
Control Register(LPC I/F—D31:F0)
Offset Address: 94h–97h Attribute: RO, R/WC, R/W
Default Value: 00002000h Size: 32 bits
Power Well: Core
Bit Description
31:16 Reserved
SMI Caused by End of Pass-Through (SMIBYENDPS)—R/WC. This bit indicates if
the event occurred. Even if the corresponding enable bit is not set in bit 7, this bit will
still be active. It is up to the SMM code to use the enable bit to determine the exact
15
cause of the SMI#.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred
14:12 Reserved
SMI Caused by Port 64 Write (TRAPBY64W)—R/WC. This bit indicates if the event
occurred. Even if the corresponding enable bit is not set in bit 3, this bit will still be
active. It is up to the SMM code to use the enable bit to determine the exact cause of
11 the SMI#. The A20Gate Pass-Through Logic allows specific port 64h writes to complete
without setting this bit.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
SMI Caused by Port 64 Read (TRAPBY64R)—R/WC. This bit indicates if the event
occurred. Even if the corresponding enable bit is not set in bit 2, this bit will still be
active. It is up to the SMM code to use the enable bit to determine the exact cause of
10
the SMI#.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
SMI Caused by Port 60 Write (TRAPBY60W)—R/WC. This bit indicates if the event
occurred. Even if the corresponding enable bit is not set in bit 1, this bit will still be
active. It is up to the SMM code to use the enable bit to determine the exact cause of
9 the SMI#. The A20Gate Pass-Through Logic allows specific port 64h writes to complete
without setting this bit.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
SMI Caused by Port 60 Read (TRAPBY60R)—R/WC. This bit indicates if the event
occurred. Even if the corresponding enable bit is not set in the bit 0, this bit will still be
active. It is up to the SMM code to use the enable bit to determine the exact cause of
8
the SMI#.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
SMI at End of Pass-Through Enable (SMIATENDPS)—R/W. This bit enables SMI at
the end of a pass-through. This can occur if an SMI is generated in the middle of a
7 pass-through, and needs to be serviced later.
0 = Disable
1 = Enable
Pass Through State (PSTATE)—RO.
0 = If software needs to reset this bit, it should set bit 5 in all of the host controllers to
6 0.
1 = Indicates that the state machine is in the middle of an A20GATE pass-through
sequence.
Datasheet 469
LPC Interface Bridge Registers (D31:F0)
Bit Description
A20Gate Pass-Through Enable (A20PASSEN)—R/W.
0 = Disable.
1 = Enable. Allows A20GATE sequence Pass-Through function. A specific cycle
5
sequence involving writes to port 60h and 64h does not result in the setting of the
SMI status bits.
NOTE: A20M# functionality is not supported.
SMI on USB IRQ Enable (USBSMIEN)—R/W.
4 0 = Disable
1 = Enable. USB interrupt will cause an SMI event.
SMI on Port 64 Writes Enable (64WEN)—R/W.
3 0 = Disable
1 = Enable. A 1 in bit 11 will cause an SMI event.
SMI on Port 64 Reads Enable (64REN)—R/W.
2 0 = Disable
1 = Enable. A 1 in bit 10 will cause an SMI event.
SMI on Port 60 Writes Enable (60WEN)—R/W.
1 0 = Disable
1 = Enable. A 1 in bit 9 will cause an SMI event.
SMI on Port 60 Reads Enable (60REN)—R/W.
0 0 = Disable
1 = Enable. A 1 in bit 8 will cause an SMI event.
12.1.29 LGMR—LPC I/F Generic Memory Range Register
(LPC I/F—D31:F0)
Offset Address: 98h–9Bh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Power Well: Core
Bit Description
Memory Address[31:16]—R/W. This field specifies a 64 KB memory block anywhere
31:16 in the 4 GB memory space that will be decoded to LPC as standard LPC memory cycle if
enabled.
15:1 Reserved
LPC Memory Range Decode Enable—R/W. When this bit is set to 1, then the range
0
specified in bits 31:16 of this register is enabled for decoding to LPC.
470 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.1.30 BIOS_SEL1—BIOS Select 1 Register
(LPC I/F—D31:F0)
Offset Address: D0h–D3h Attribute: R/W, RO
Default Value: 00112233h Size: 32 bits
Bit Description
BIOS_F8_IDSEL—RO. IDSEL for two 512-KB BIOS memory ranges and one 128-KB
memory range. This field is fixed at 0000. The IDSEL programmed in this field
addresses the following memory ranges:
31:28
FFF8 0000h–FFFF FFFFh
FFB8 0000h–FFBF FFFFh
000E 0000h–000F FFFFh
BIOS_F0_IDSEL—R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
27:24
FFF0 0000h–FFF7 FFFFh
FFB0 0000h–FFB7 FFFFh
BIOS_E8_IDSEL—R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
23:20
FFE8 0000h–FFEF FFFFh
FFA8 0000h–FFAF FFFFh
BIOS_E0_IDSEL—R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
19:16
FFE0 0000h–FFE7 FFFFh
FFA0 0000h–FFA7 FFFFh
BIOS_D8_IDSEL—R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
15:12
FFD8 0000h–FFDF FFFFh
FF98 0000h–FF9F FFFFh
BIOS_D0_IDSEL—R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
11:8
FFD0 0000h–FFD7 FFFFh
FF90 0000h–FF97 FFFFh
BIOS_C8_IDSEL—R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
7:4
FFC8 0000h–FFCF FFFFh
FF88 0000h–FF8F FFFFh
BIOS_C0_IDSEL—R/W. IDSEL for two 512-KB BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
3:0
FFC0 0000h–FFC7 FFFFh
FF80 0000h–FF87 FFFFh
Datasheet 471
LPC Interface Bridge Registers (D31:F0)
12.1.31 BIOS_SEL2—BIOS Select 2 Register
(LPC I/F—D31:F0)
Offset Address: D4h–D5h Attribute: R/W
Default Value: 4567h Size: 16 bits
Bit Description
BIOS_70_IDSEL—R/W. IDSEL for two, 1-M BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
15:12
FF70 0000h–FF7F FFFFh
FF30 0000h–FF3F FFFFh
BIOS_60_IDSEL—R/W. IDSEL for two, 1-M BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
11:8
FF60 0000h–FF6F FFFFh
FF20 0000h–FF2F FFFFh
BIOS_50_IDSEL—R/W. IDSEL for two, 1-M BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
7:4
FF50 0000h–FF5F FFFFh
FF10 0000h–FF1F FFFFh
BIOS_40_IDSEL—R/W. IDSEL for two, 1-M BIOS memory ranges. The IDSEL
programmed in this field addresses the following memory ranges:
3:0
FF40 0000h–FF4F FFFFh
FF00 0000h–FF0F FFFFh
472 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.1.32 BIOS_DEC_EN1—BIOS Decode Enable
Register (LPC I/F—D31:F0)
Offset Address: D8h–D9h Attribute: R/W, RO
Default Value: FFCFh Size: 16 bits
Bit Description
BIOS_F8_EN—RO. This bit enables decoding two 512-KB BIOS memory ranges, and
one 128-KB memory range.
15 0 = Disable
1 = Enable the following ranges for the BIOS
FFF80000h–FFFFFFFFh
FFB80000h–FFBFFFFFh
BIOS_F0_EN—R/W. This bit enables decoding two 512-KB BIOS memory ranges.
0 = Disable.
14 1 = Enable the following ranges for the BIOS:
FFF00000h–FFF7FFFFh
FFB00000h–FFB7FFFFh
BIOS_E8_EN—R/W. This bit enables decoding two 512-KB BIOS memory ranges.
0 = Disable.
13 1 = Enable the following ranges for the BIOS:
FFE80000h–FFEFFFFh
FFA80000h–FFAFFFFFh
BIOS_E0_EN—R/W. This bit enables decoding two 512-KB BIOS memory ranges.
0 = Disable.
12 1 = Enable the following ranges for the BIOS:
FFE00000h–FFE7FFFFh
FFA00000h–FFA7FFFFh
BIOS_D8_EN—R/W. This bit enables decoding two 512-KB BIOS memory ranges.
0 = Disable.
11 1 = Enable the following ranges for the BIOS
FFD80000h–FFDFFFFFh
FF980000h–FF9FFFFFh
BIOS_D0_EN—R/W. This bit enables decoding two 512-KB BIOS memory ranges.
0 = Disable.
10 1 = Enable the following ranges for the BIOS
FFD00000h–FFD7FFFFh
FF900000h–FF97FFFFh
BIOS_C8_EN—R/W. This bit enables decoding two 512-KB BIOS memory ranges.
0 = Disable.
9 1 = Enable the following ranges for the BIOS
FFC80000h–FFCFFFFFh
FF880000h–FF8FFFFFh
BIOS_C0_EN—R/W. This bit enables decoding two 512-KB BIOS memory ranges.
0 = Disable.
8 1 = Enable the following ranges for the BIOS
FFC00000h–FFC7FFFFh
FF800000h–FF87FFFFh
Datasheet 473
LPC Interface Bridge Registers (D31:F0)
Bit Description
BIOS_Legacy_F_EN—R/W. This enables the decoding of the legacy 64KB range at
F0000h–FFFFFh.
0 = Disable.
7 1 = Enable the following legacy ranges for the BIOS
F0000h–FFFFFh
NOTE: The decode for the BIOS legacy F segment is enabled only by this bit and is not
affected by the GEN_PMCON_1.iA64_EN bit.
BIOS_Legacy_E_EN—R/W. This enables the decoding of the legacy 64KB range at
E0000h–EFFFFh.
0 = Disable.
6 1 = Enable the following legacy ranges for the BIOS
E0000h–EFFFFh
NOTE: The decode for the BIOS legacy E segment is enabled only by this bit and is not
affected by the GEN_PMCON_1.iA64_EN bit.
5:4 Reserved
BIOS_70_EN—R/W. Enables decoding two 1-M BIOS memory ranges.
0 = Disable.
3 1 = Enable the following ranges for the BIOS
FF70 0000h–FF7F FFFFh
FF30 0000h–FF3F FFFFh
BIOS_60_EN—R/W. Enables decoding two 1-M BIOS memory ranges.
0 = Disable.
2 1 = Enable the following ranges for the BIOS
FF60 0000h–FF6F FFFFh
FF20 0000h–FF2F FFFFh
BIOS_50_EN—R/W. Enables decoding two 1-M BIOS memory ranges.
0 = Disable.
1 1 = Enable the following ranges for the BIOS
FF50 0000h–FF5F FFFFh
FF10 0000h–FF1F FFFFh
BIOS_40_EN—R/W. Enables decoding two 1-M BIOS memory ranges.
0 = Disable.
0 1 = Enable the following ranges for the BIOS
FF40 0000h–FF4F FFFFh
FF00 0000h–FF0F FFFFh
NOTE: This register effects the BIOS decode regardless of whether the BIOS is resident on LPC or
SPI. The concept of Feature Space does not apply to SPI-based flash. The PCH simply
decodes these ranges as memory accesses when enabled for the SPI flash interface.
474 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.1.33 BIOS_CNTL—BIOS Control Register
(LPC I/F—D31:F0)
Offset Address: DCh Attribute: R/WLO, R/W, RO
Default Value: 20h Size: 8 bits
Lockable: No Power Well: Core
Bit Description
7:6 Reserved
SMM BIOS Write Protect Disable (SMM_BWP)—R/WL.
This bit set defines when the BIOS region can be written by the host.
5 0 = BIOS region SMM protection is disabled. The BIOS Region is writable regardless if
processors are in SMM or not. (Set this field to 0 for legacy behavior).
1 = BIOS region SMM protection is enabled. The BIOS Region is not writable unless all
processors are in SMM and BIOS Write Enable (BIOSWE) is set to ‘1’.
Top Swap Status (TSS)—RO. This bit provides a read-only path to view the state of
4
the Top Swap bit that is at offset 3414h, bit 0.
SPI Read Configuration (SRC)—R/W. This 2-bit field controls two policies related to
BIOS reads on the SPI interface:
Bit 3 – Prefetch Enable
Bit 2 – Cache Disable
Settings are summarized below:
Bits 3:2 Description
No prefetching, but caching enabled. 64B demand reads load
3:2 00b the read buffer cache with “valid” data, allowing repeated code
fetches to the same line to complete quickly.
No prefetching and no caching. One-to-one correspondence of
01b host BIOS reads to SPI cycles. This value can be used to invalidate
the cache.
Prefetching and Caching enabled. This mode is used for long
10b sequences of short reads to consecutive addresses (that is,
shadowing).
BIOS Lock Enable (BLE)—R/WLO.
0 = Transition of BIOSWE from ‘0’ to ‘1’ will not cause an SMI to be asserted.
1
1 = Enables setting the BIOSWE bit to cause SMIs and locks SMM_BWP. Once set, this
bit can only be cleared by a PLTRST#.
BIOS Write Enable (BIOSWE)—R/W.
0 = Only read cycles result in Firmware Hub or SPI I/F cycles.
0 1 = Access to the BIOS space is enabled for both read and write cycles. When this bit is
written from a 0 to a 1 and BIOS Lock Enable (BLE) is also set, an SMI# is
generated. This ensures that only SMI code can update BIOS.
Datasheet 475
LPC Interface Bridge Registers (D31:F0)
12.1.34 FDCAP—Feature Detection Capability ID Register
(LPC I/F—D31:F0)
Offset Address: E0h–E1h Attribute: RO
Default Value: 0009h Size: 16 bits
Power Well: Core
Bit Description
Next Item Pointer (NEXT)—RO. Configuration offset of the next Capability Item. 00h
15:8
indicates the last item in the Capability List.
7:0 Capability ID—RO. Indicates a Vendor Specific Capability
12.1.35 FDLEN—Feature Detection Capability Length Register
(LPC I/F—D31:F0)
Offset Address: E2h Attribute: RO
Default Value: 0Ch Size: 8 bits
Power Well: Core
Bit Description
Capability Length—RO. Indicates the length of this Vendor Specific capability, as
7:0
required by PCI Specification.
12.1.36 FDVER—Feature Detection Version Register
(LPC I/F—D31:F0)
Offset Address: E3h Attribute: RO
Default Value: 10h Size: 8 bits
Power Well: Core
Bit Description
Vendor-Specific Capability ID—RO. A value of 1h in this 4-bit field identifies this
7:4 Capability as Feature Detection Type. This field allows software to differentiate the
Feature Detection Capability from other Vendor-Specific capabilities
Capability Version—RO. This field indicates the version of the Feature Detection
3:0
capability
12.1.37 FVECIDX—Feature Vector Index Register
(LPC I/F—D31:F0)
Offset Address: E4h–E7h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Power Well: Core
Bit Description
31:6 Reserved
Index (IDX)—R/W. 4-bit index pointer into the 64-byte Feature Vector space. Data is
5:2
read from the FVECD register. This points to a DWord register.
1:0 Reserved
476 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.1.38 FVECD—Feature Vector Data Register
(LPC I/F—D31:F0)
Offset Address: E8h–EBh Attribute: RO
Default Value: See Description Size: 32 bits
Power Well: Core
Bit Description
Data (DATA)—RO. 32-bit data value that is read from the Feature Vector offset
31:0
pointed to by FVECIDX.
12.1.39 Feature Vector Space
12.1.39.1 FVEC0—Feature Vector Register 0
FVECIDX.IDX: 0000b Attribute: RO
Default Value: See Description Size: 32 bits
Power Well: Core
Bit Description
31:12 Reserved
USB Port Count Capability—RO
00 = 14 ports
11:10 01 = 12 ports
10 = 10 ports
11 = Reserved
9:8 Reserved
RAID Capability Bit 1—RO
7
See bit 5 Description.
SATA Ports 2 and 3—RO
6 0 = Capable
1 = Disabled
RAID Capability Bit 0—RO
RAID Capability is defined by the combination of bits 7 and 5 of this register.:
Bit 7 Bit 5 Capability
0 0 No RAID
5
0 1 RAID 1
1 0 RAID 0/1/5/10
RAID 0/1/5/10 and Intel Smart Response
1 1
Technology
4 Reserved
SATA Port 1 6 Gb/s Capability—RO
3 0 = Capable
1 = Disabled
SATA Port 0 6 Gb/s Capability—RO
2 0 = Capable
1 = Disabled
Datasheet 477
LPC Interface Bridge Registers (D31:F0)
Bit Description
PCI Interface Capability—RO
1 0 = Capable
1 = Disabled
0 Reserved
12.1.39.2 FVEC1—Feature Vector Register 1
FVECIDX.IDX: 0001b Attribute: RO
Default Value: See Description Size: 32 bits
Power Well: Core
Bit Description
31:23 Reserved
USB Redirect (USBr) Capability—RO
22 0 = Capable
1 = Disabled
21:0 Reserved
12.1.39.3 FVEC2—Feature Vector Register 2
FVECIDX.IDX: 0010b Attribute: RO
Default Value: See Description Size: 32 bits
Power Well: Core
Bit Description
31:23 Reserved
Intel® Anti-Theft Technology Capability—RO
22 0 = Disabled
1 = Capable
PCI Express* Ports 7 and 8—RO
21 0 = Capable
1 = Disabled
20:18 Reserved
PCH Integrated Graphics Support Capability—RO
17 0 = Capable
1 = Disabled
16:0 Reserved
478 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.1.39.4 FVEC3—Feature Vector Register 3
FVECIDX.IDX: 0011b Attribute: RO
Default Value: See Description Size: 32 bits
Power Well: Core
Bit Description
31:14 Reserved
Data Center Manageability Interface (DCMI) Capability—RO
13 0 = Capable
1 = Disabled
Node Manager Capability—RO
12 0 = Capable
1 = Disabled
11:0 Reserved
12.1.40 RCBA—Root Complex Base Address Register
(LPC I/F—D31:F0)
Offset Address: F0–F3h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Base Address (BA)—R/W. Base Address for the root complex register block decode
31:14
range. This address is aligned on a 16-KB boundary.
13:1 Reserved
Enable (EN)—R/W. When set, this bit enables the range specified in BA to be claimed
0
as the Root Complex Register Block.
Datasheet 479
LPC Interface Bridge Registers (D31:F0)
12.2 DMA I/O Registers
Table 12-2. DMA Registers (Sheet 1 of 2)
Port Alias Register Name Default Type
00h 10h Channel 0 DMA Base and Current Address Undefined R/W
01h 11h Channel 0 DMA Base and Current Count Undefined R/W
02h 12h Channel 1 DMA Base and Current Address Undefined R/W
03h 13h Channel 1 DMA Base and Current Count Undefined R/W
04h 14h Channel 2 DMA Base and Current Address Undefined R/W
05h 15h Channel 2 DMA Base and Current Count Undefined R/W
06h 16h Channel 3 DMA Base and Current Address Undefined R/W
07h 17h Channel 3 DMA Base and Current Count Undefined R/W
Channel 0–3 DMA Command Undefined WO
08h 18h
Channel 0–3 DMA Status Undefined RO
0Ah 1Ah Channel 0–3 DMA Write Single Mask 000001XXb WO
0Bh 1Bh Channel 0–3 DMA Channel Mode 000000XXb WO
0Ch 1Ch Channel 0–3 DMA Clear Byte Pointer Undefined WO
0Dh 1Dh Channel 0–3 DMA Master Clear Undefined WO
0Eh 1Eh Channel 0–3 DMA Clear Mask Undefined WO
0Fh 1Fh Channel 0–3 DMA Write All Mask 0Fh R/W
80h 90h Reserved Page Undefined R/W
81h 91h Channel 2 DMA Memory Low Page Undefined R/W
82h — Channel 3 DMA Memory Low Page Undefined R/W
83h 93h Channel 1 DMA Memory Low Page Undefined R/W
84h–86h 94h–96h Reserved Pages Undefined R/W
87h 97h Channel 0 DMA Memory Low Page Undefined R/W
88h 98h Reserved Page Undefined R/W
89h 99h Channel 6 DMA Memory Low Page Undefined R/W
8Ah 9Ah Channel 7 DMA Memory Low Page Undefined R/W
8Bh 9Bh Channel 5 DMA Memory Low Page Undefined R/W
8Ch–8Eh 9Ch–9Eh Reserved Page Undefined R/W
8Fh 9Fh Refresh Low Page Undefined R/W
C0h C1h Channel 4 DMA Base and Current Address Undefined R/W
C2h C3h Channel 4 DMA Base and Current Count Undefined R/W
C4h C5h Channel 5 DMA Base and Current Address Undefined R/W
C6h C7h Channel 5 DMA Base and Current Count Undefined R/W
C8h C9h Channel 6 DMA Base and Current Address Undefined R/W
CAh CBh Channel 6 DMA Base and Current Count Undefined R/W
CCh CDh Channel 7 DMA Base and Current Address Undefined R/W
CEh CFh Channel 7 DMA Base and Current Count Undefined R/W
480 Datasheet
LPC Interface Bridge Registers (D31:F0)
Table 12-2. DMA Registers (Sheet 2 of 2)
Port Alias Register Name Default Type
Channel 4–7 DMA Command Undefined WO
D0h D1h
Channel 4–7 DMA Status Undefined RO
D4h D5h Channel 4–7 DMA Write Single Mask 000001XXb WO
D6h D7h Channel 4–7 DMA Channel Mode 000000XXb WO
D8h D9h Channel 4–7 DMA Clear Byte Pointer Undefined WO
DAh dBh Channel 4–7 DMA Master Clear Undefined WO
DCh DDh Channel 4–7 DMA Clear Mask Undefined WO
DEh DFh Channel 4–7 DMA Write All Mask 0Fh R/W
12.2.1 DMABASE_CA—DMA Base and Current Address Registers
I/O Address: Ch. #0 = 00h; Ch. #1 = 02h Attribute: R/W
Ch. #2 = 04h; Ch. #3 = 06h Size: 16 bits (per channel),
Ch. #5 = C4h Ch. #6 = C8h but accessed in two 8 bits
Ch. #7 = CCh; quantities
Default Value: Undefined
Lockable: No Power Well: Core
Bit Description
Base and Current Address—R/W. This register determines the address for the
transfers to be performed. The address specified points to two separate registers. On
writes, the value is stored in the Base Address register and copied to the Current
Address register. On reads, the value is returned from the Current Address register.
The address increments/decrements in the Current Address register after each transfer,
depending on the mode of the transfer. If the channel is in auto-initialize mode, the
15:0 Current Address register will be reloaded from the Base Address register after a
terminal count is generated.
For transfers to/from a 16-bit slave (channels 5–7), the address is shifted left one bit
location. Bit 15 will be shifted into Bit 16.
The register is accessed in 8 bit quantities. The byte is pointed to by the current byte
pointer flip/flop. Before accessing an address register, the byte pointer flip/flop should
be cleared to ensure that the low byte is accessed first.
Datasheet 481
LPC Interface Bridge Registers (D31:F0)
12.2.2 DMABASE_CC—DMA Base and Current Count Registers
I/O Address: Ch. #0 = 01h; Ch. #1 = 03h Attribute: R/W
Ch. #2 = 05h; Ch. #3 = 07h Size: 16 bits (per channel),
Ch. #5 = C6h; Ch. #6 = CAh but accessed in two 8 bits
Ch. #7 = CEh; quantities
Default Value: Undefined
Lockable: No Power Well:Core
Bit Description
Base and Current Count—R/W. This register determines the number of transfers to
be performed. The address specified points to two separate registers. On writes, the
value is stored in the Base Count register and copied to the Current Count register. On
reads, the value is returned from the Current Count register.
The actual number of transfers is one more than the number programmed in the Base
Count Register (that is, programming a count of 4h results in 5 transfers). The count is
decrements in the Current Count register after each transfer. When the value in the
register rolls from 0 to FFFFh, a terminal count is generated. If the channel is in auto-
15:0
initialize mode, the Current Count register will be reloaded from the Base Count
register after a terminal count is generated.
For transfers to/from an 8-bit slave (channels 0–3), the count register indicates the
number of bytes to be transferred. For transfers to/from a 16-bit slave (channels 5–7),
the count register indicates the number of words to be transferred.
The register is accessed in 8 bit quantities. The byte is pointed to by the current byte
pointer flip/flop. Before accessing a count register, the byte pointer flip/flop should be
cleared to ensure that the low byte is accessed first.
12.2.3 DMAMEM_LP—DMA Memory Low Page Registers
I/O Address: Ch. #0 = 87h; Ch. #1 = 83h
Ch. #2 = 81h; Ch. #3 = 82h
Ch. #5 = 8Bh; Ch. #6 = 89h
Ch. #7 = 8Ah; Attribute: R/W
Default Value: Undefined Size: 8 bits
Lockable: No Power Well: Core
Bit Description
DMA Low Page (ISA Address bits [23:16])—R/W. This register works in conjunction
with the DMA controller's Current Address Register to define the complete 24-bit
7:0 address for the DMA channel. This register remains static throughout the DMA transfer.
Bit 16 of this register is ignored when in 16 bit I/O count by words mode as it is
replaced by the bit 15 shifted out from the current address register.
482 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.2.4 DMACMD—DMA Command Register
I/O Address: Ch. #0–3 = 08h;
Ch. #4–7 = D0h Attribute: WO
Default Value: Undefined Size: 8 bits
Lockable: No Power Well: Core
Bit Description
7:5 Reserved. Must be 0.
DMA Group Arbitration Priority—WO. Each channel group is individually assigned
either fixed or rotating arbitration priority. At part reset, each group is initialized in
4 fixed priority.
0 = Fixed priority to the channel group
1 = Rotating priority to the group.
3 Reserved. Must be 0.
DMA Channel Group Enable—WO. Both channel groups are enabled following part
reset.
2 0 = Enable the DMA channel group.
1 = Disable. Disabling channel group 4–7 also disables channel group 0–3, which is
cascaded through channel 4.
1:0 Reserved. Must be 0.
12.2.5 DMASTA—DMA Status Register
I/O Address: Ch. #0–3 = 08h;
Ch. #4–7 = D0h Attribute: RO
Default Value: Undefined Size: 8 bits
Lockable: No Power Well: Core
Bit Description
Channel Request Status—RO. When a valid DMA request is pending for a channel,
the corresponding bit is set to 1. When a DMA request is not pending for a particular
channel, the corresponding bit is set to 0. The source of the DREQ may be hardware or
a software request. Channel 4 is the cascade channel; thus, the request status of
7:4 channel 4 is a logical OR of the request status for channels 0 through 3.
4 = Channel 0
5 = Channel 1 (5)
6 = Channel 2 (6)
7 = Channel 3 (7)
Channel Terminal Count Status—RO. When a channel reaches terminal count (TC),
its status bit is set to 1. If TC has not been reached, the status bit is set to 0. Channel 4
is programmed for cascade; thus, the TC bit response for channel 4 is irrelevant:
3:0 0 = Channel 0
1 = Channel 1 (5)
2 = Channel 2 (6)
3 = Channel 3 (7)
Datasheet 483
LPC Interface Bridge Registers (D31:F0)
12.2.6 DMA_WRSMSK—DMA Write Single Mask Register
I/O Address: Ch. #0–3 = 0Ah;
Ch. #4–7 = D4h Attribute: WO
Default Value: 0000 01xx Size: 8 bits
Lockable: No Power Well: Core
Bit Description
7:3 Reserved. Must be 0.
Channel Mask Select—WO.
2 0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0].
Therefore, only one channel can be masked / unmasked at a time.
1 = Disable DREQ for the selected channel.
DMA Channel Select—WO. These bits select the DMA Channel Mode Register to
program.
00 = Channel 0 (4)
1:0
01 = Channel 1 (5)
10 = Channel 2 (6)
11 = Channel 3 (7)
484 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.2.7 DMACH_MODE—DMA Channel Mode Register
I/O Address: Ch. #0–3 = 0Bh;
Ch. #4–7 = D6h Attribute: WO
Default Value: 0000 00xx Size: 8 bits
Lockable: No Power Well: Core
Bit Description
DMA Transfer Mode—WO. Each DMA channel can be programmed in one of four
different modes:
00 = Demand mode
7:6
01 = Single mode
10 = Reserved
11 = Cascade mode
Address Increment/Decrement Select—WO. This bit controls address increment/
decrement during DMA transfers.
5
0 = Address increment. (default after part reset or Master Clear)
1 = Address decrement.
Autoinitialize Enable—WO.
0 = Autoinitialize feature is disabled and DMA transfers terminate on a terminal count.
4 A part reset or Master Clear disables autoinitialization.
1 = DMA restores the Base Address and Count registers to the current registers
following a terminal count (TC).
DMA Transfer Type—WO. These bits represent the direction of the DMA transfer.
When the channel is programmed for cascade mode, (bits [7:6] = 11) the transfer type
is irrelevant.
3:2 00 = Verify – No I/O or memory strobes generated
01 = Write – Data transferred from the I/O devices to memory
10 = Read – Data transferred from memory to the I/O device
11 = Invalid
DMA Channel Select—WO. These bits select the DMA Channel Mode Register that will
be written by bits [7:2].
00 = Channel 0 (4)
1:0
01 = Channel 1 (5)
10 = Channel 2 (6)
11 = Channel 3 (7)
Datasheet 485
LPC Interface Bridge Registers (D31:F0)
12.2.8 DMA Clear Byte Pointer Register
I/O Address: Ch. #0–3 = 0Ch;
Ch. #4–7 = D8h Attribute: WO
Default Value: xxxx xxxx Size: 8 bits
Lockable: No Power Well: Core
Bit Description
Clear Byte Pointer—WO. No specific pattern. Command enabled with a write to the I/
O port address. Writing to this register initializes the byte pointer flip/flop to a known
state. It clears the internal latch used to address the upper or lower byte of the 16-bit
7:0 Address and Word Count Registers. The latch is also cleared by part reset and by the
Master Clear command. This command precedes the first access to a 16-bit DMA
controller register. The first access to a 16-bit register will then access the significant
byte, and the second access automatically accesses the most significant byte.
12.2.9 DMA Master Clear Register
I/O Address: Ch. #0–3 = 0Dh;
Ch. #4–7 = DAh Attribute: WO
Default Value: xxxx xxxx Size: 8 bits
Bit Description
Master Clear—WO. No specific pattern. Enabled with a write to the port. This has the
7:0 same effect as the hardware Reset. The Command, Status, Request, and Byte Pointer
flip/flop registers are cleared and the Mask Register is set.
12.2.10 DMA_CLMSK—DMA Clear Mask Register
I/O Address: Ch. #0–3 = 0Eh;
Ch. #4–7 = DCh Attribute: WO
Default Value: xxxx xxxx Size: 8 bits
Lockable: No Power Well: Core
Bit Description
Clear Mask Register—WO. No specific pattern. Command enabled with a write to the
7:0
port.
486 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.2.11 DMA_WRMSK—DMA Write All Mask Register
I/O Address: Ch. #0–3 = 0Fh;
Ch. #4–7 = DEh Attribute: R/W
Default Value: 0000 1111 Size: 8 bits
Lockable: No Power Well: Core
Bit Description
7:4 Reserved. Must be 0.
Channel Mask Bits—R/W. This register permits all four channels to be simultaneously
enabled/disabled instead of enabling/disabling each channel individually, as is the case
with the Mask Register – Write Single Mask Bit. In addition, this register has a read
path to allow the status of the channel mask bits to be read. A channel's mask bit is
automatically set to 1 when the Current Byte/Word Count Register reaches terminal
count (unless the channel is in auto-initialization mode).
Setting the bit(s) to a 1 disables the corresponding DREQ(s). Setting the bit(s) to a 0
enables the corresponding DREQ(s). Bits [3:0] are set to 1 upon part reset or Master
3:0 Clear. When read, bits [3:0] indicate the DMA channel [3:0] ([7:4]) mask status.
Bit 0 = Channel 0 (4)1 = Masked, 0 = Not Masked
Bit 1 = Channel 1 (5)1 = Masked, 0 = Not Masked
Bit 2 = Channel 2 (6)1 = Masked, 0 = Not Masked
Bit 3 = Channel 3 (7)1 = Masked, 0 = Not Masked
NOTE: Disabling channel 4 also disables channels 0–3 due to the cascade of channels
0–3 through channel 4.
Datasheet 487
LPC Interface Bridge Registers (D31:F0)
12.3 Timer I/O Registers
Port Aliases Register Name Default Value Type
Counter 0 Interval Time Status Byte Format 0XXXXXXXb RO
40h 50h
Counter 0 Counter Access Port Undefined R/W
Counter 1 Interval Time Status Byte Format 0XXXXXXXb RO
41h 51h
Counter 1 Counter Access Port Undefined R/W
Counter 2 Interval Time Status Byte Format 0XXXXXXXb RO
42h 52h
Counter 2 Counter Access Port Undefined R/W
Timer Control Word Undefined WO
43h 53h Timer Control Word Register XXXXXXX0b WO
Counter Latch Command X0h WO
488 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.3.1 TCW—Timer Control Word Register
I/O Address: 43h Attribute: WO
Default Value: All bits undefined Size: 8 bits
This register is programmed prior to any counter being accessed to specify counter
modes. Following part reset, the control words for each register are undefined and each
counter output is 0. Each timer must be programmed to bring it into a known state.
Bit Description
Counter Select—WO. The Counter Selection bits select the counter the control word
acts upon as shown below. The Read Back Command is selected when bits[7:6] are
both 1.
7:6 00 = Counter 0 select
01 = Counter 1 select
10 = Counter 2 select
11 = Read Back Command
Read/Write Select—WO. These bits are the read/write control bits. The actual
counter programming is done through the counter port (40h for counter 0, 41h for
counter 1, and 42h for counter 2).
5:4 00 = Counter Latch Command
01 = Read/Write Least Significant Byte (LSB)
10 = Read/Write Most Significant Byte (MSB)
11 = Read/Write LSB then MSB
Counter Mode Selection—WO. These bits select one of six possible modes of
operation for the selected counter.
Bit Value Mode
000b Mode 0 Out signal on end of count (=0)
Mode 1 Hardware retriggerable one-
001b
3:1 shot
Mode 2 Rate generator (divide by n
x10b
counter)
x11b Mode 3 Square wave output
100b Mode 4 Software triggered strobe
101b Mode 5 Hardware triggered strobe
Binary/BCD Countdown Select—WO.
0 0 = Binary countdown is used. The largest possible binary count is 216
1 = Binary coded decimal (BCD) count is used. The largest possible BCD count is 104
There are two special commands that can be issued to the counters through this
register, the Read Back Command and the Counter Latch Command. When these
commands are chosen, several bits within this register are redefined. These register
formats are described as follows:
Datasheet 489
LPC Interface Bridge Registers (D31:F0)
RdBK_CMD—Read Back Command
The Read Back Command is used to determine the count value, programmed mode,
and current states of the OUT pin and Null count flag of the selected counter or
counters. Status and/or count may be latched in any or all of the counters by selecting
the counter during the register write. The count and status remain latched until read,
and further latch commands are ignored until the count is read. Both count and status
of the selected counters may be latched simultaneously by setting both bit 5 and bit 4
to 0. If both are latched, the first read operation from that counter returns the latched
status. The next one or two reads, depending on whether the counter is programmed
for one or two byte counts, returns the latched count. Subsequent reads return an
unlatched count.
Bit Description
7:6 Read Back Command. Must be 11 to select the Read Back Command
Latch Count of Selected Counters.
5 0 = Current count value of the selected counters will be latched
1 = Current count will not be latched
Latch Status of Selected Counters.
4 0 = Status of the selected counters will be latched
1 = Status will not be latched
Counter 2 Select.
3
1 = Counter 2 count and/or status will be latched
Counter 1 Select.
2
1 = Counter 1 count and/or status will be latched
Counter 0 Select.
1
1 = Counter 0 count and/or status will be latched.
0 Reserved. Must be 0.
LTCH_CMD—Counter Latch Command
The Counter Latch Command latches the current count value. This command is used to
insure that the count read from the counter is accurate. The count value is then read
from each counter's count register through the Counter Ports Access Ports Register
(40h for counter 0, 41h for counter 1, and 42h for counter 2). The count must be read
according to the programmed format; that is, if the counter is programmed for two
byte counts, two bytes must be read. The two bytes do not have to be read one right
after the other (read, write, or programming operations for other counters may be
inserted between the reads). If a counter is latched once and then latched again before
the count is read, the second Counter Latch Command is ignored.
Bit Description
Counter Selection. These bits select the counter for latching. If “11” is written, then
the write is interpreted as a read back command.
7:6 00 = Counter 0
01 = Counter 1
10 = Counter 2
Counter Latch Command.
5:4
00 = Selects the Counter Latch Command.
3:0 Reserved. Must be 0.
490 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.3.2 SBYTE_FMT—Interval Timer Status Byte Format Register
I/O Address: Counter 0 = 40h,
Counter 1 = 41h, Attribute: RO
Counter 2 = 42h Size: 8 bits per counter
Default Value: Bits[6:0] undefined, Bit 7=0
Each counter's status byte can be read following a Read Back Command. If latch status
is chosen (bit 4=0, Read Back Command) as a read back option for a given counter, the
next read from the counter's Counter Access Ports Register (40h for counter 0, 41h for
counter 1, and 42h for counter 2) returns the status byte. The status byte returns the
following:
Bit Description
Counter OUT Pin State—RO.
7 0 = OUT pin of the counter is also a 0
1 = OUT pin of the counter is also a 1
Count Register Status—RO. This bit indicates when the last count written to the
Count Register (CR) has been loaded into the counting element (CE). The exact time
this happens depends on the counter mode, but until the count is loaded into the
6 counting element (CE), the count value will be incorrect.
0 = Count has been transferred from CR to CE and is available for reading.
1 = Null Count. Count has not been transferred from CR to CE and is not yet available
for reading.
Read/Write Selection Status—RO. These reflect the read/write selection made
through bits[5:4] of the control register. The binary codes returned during the status
read match the codes used to program the counter read/write selection.
5:4 00 = Counter Latch Command
01 = Read/Write Least Significant Byte (LSB)
10 = Read/Write Most Significant Byte (MSB)
11 = Read/Write LSB then MSB
Mode Selection Status—RO. These bits return the counter mode programming. The
binary code returned matches the code used to program the counter mode, as listed
under the bit function above.
000 = Mode 0 – Out signal on end of count (=0)
3:1 001 = Mode 1 – Hardware retriggerable one-shot
x10 = Mode 2 – Rate generator (divide by n counter)
x11 = Mode 3 – Square wave output
100 = Mode 4 – Software triggered strobe
101 = Mode 5 – Hardware triggered strobe
Countdown Type Status—RO. This bit reflects the current countdown type.
0 0 = Binary countdown
1 = Binary Coded Decimal (BCD) countdown.
Datasheet 491
LPC Interface Bridge Registers (D31:F0)
12.3.3 Counter Access Ports Register
I/O Address: Counter 0 – 40h,
Counter 1 – 41h, Attribute: R/W
Counter 2 – 42h
Default Value: All bits undefined Size: 8 bits
Bit Description
Counter Port—R/W. Each counter port address is used to program the 16-bit Count
Register. The order of programming, either LSB only, MSB only, or LSB then MSB, is
7:0 defined with the Interval Counter Control Register at port 43h. The counter port is also
used to read the current count from the Count Register, and return the status of the
counter programming following a Read Back Command.
492 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.4 8259 Interrupt Controller (PIC) Registers
12.4.1 Interrupt Controller I/O MAP
The interrupt controller registers are located at 20h and 21h for the master controller
(IRQ 0–7), and at A0h and A1h for the slave controller (IRQ 8–13). These registers
have multiple functions, depending upon the data written to them. Table 12-3 shows
the different register possibilities for each address.
Table 12-3. PIC Registers
Default
Port Aliases Register Name Type
Value
24h, 28h, Master PIC ICW1 Init. Cmd Word 1 Undefined WO
20h 2Ch, 30h, Master PIC OCW2 Op Ctrl Word 2 001XXXXXb WO
34h, 38h, 3Ch Master PIC OCW3 Op Ctrl Word 3 X01XXX10b WO
Master PIC ICW2 Init. Cmd Word 2 Undefined WO
25h, 29h,
2Dh, 31h, Master PIC ICW3 Init. Cmd Word 3 Undefined WO
21h
35h, 39h, Master PIC ICW4 Init. Cmd Word 4 01h WO
3Dh
Master PIC OCW1 Op Ctrl Word 1 00h R/W
A4h, A8h, Slave PIC ICW1 Init. Cmd Word 1 Undefined WO
ACh, B0h, Slave PIC OCW2 Op Ctrl Word 2 001XXXXXb WO
A0h
B4h, B8h,
BCh Slave PIC OCW3 Op Ctrl Word 3 X01XXX10b WO
Slave PIC ICW2 Init. Cmd Word 2 Undefined WO
A5h, A9h,
ADh, B1h, Slave PIC ICW3 Init. Cmd Word 3 Undefined WO
A1h
B5h, B9h, Slave PIC ICW4 Init. Cmd Word 4 01h WO
BDh
Slave PIC OCW1 Op Ctrl Word 1 00h R/W
4D0h – Master PIC Edge/Level Triggered 00h R/W
4D1h – Slave PIC Edge/Level Triggered 00h R/W
Note: Refer to note addressing active-low interrupt sources in 8259 Interrupt Controllers
section (Chapter 5.9).
Datasheet 493
LPC Interface Bridge Registers (D31:F0)
12.4.2 ICW1—Initialization Command Word 1 Register
Offset Address: Master Controller – 20h Attribute: WO
Slave Controller – A0h Size: 8 bits /controller
Default Value: All bits undefined
A write to Initialization Command Word 1 starts the interrupt controller initialization
sequence, during which the following occurs:
1. The Interrupt Mask register is cleared.
2. IRQ7 input is assigned priority 7.
3. The slave mode address is set to 7.
4. Special mask mode is cleared and Status Read is set to IRR.
Once this write occurs, the controller expects writes to ICW2, ICW3, and ICW4 to
complete the initialization sequence.
Bit Description
ICW/OCW Select—WO. These bits are MCS-85 specific, and not needed.
7:5
000 = Should be programmed to “000”
ICW/OCW Select—WO.
4 1 = This bit must be a 1 to select ICW1 and enable the ICW2, ICW3, and ICW4
sequence.
Edge/Level Bank Select (LTIM)—WO. Disabled. Replaced by the edge/level
3
triggered control registers (ELCR, D31:F0:4D0h, D31:F0:4D1h).
ADI—WO.
2
0 = Ignored for the PCH. Should be programmed to 0.
Single or Cascade (SNGL)—WO.
1
0 = Must be programmed to a 0 to indicate two controllers operating in cascade mode.
ICW4 Write Required (IC4)—WO.
0 1 = This bit must be programmed to a 1 to indicate that ICW4 needs to be
programmed.
494 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.4.3 ICW2—Initialization Command Word 2 Register
Offset Address: Master Controller – 21h Attribute: WO
Slave Controller – A1h Size: 8 bits /controller
Default Value: All bits undefined
ICW2 is used to initialize the interrupt controller with the five most significant bits of
the interrupt vector address. The value programmed for bits[7:3] is used by the
processor to define the base address in the interrupt vector table for the interrupt
routines associated with each IRQ on the controller. Typical ISA ICW2 values are 08h
for the master controller and 70h for the slave controller.
Bit Description
Interrupt Vector Base Address—WO. Bits [7:3] define the base address in the
7:3 interrupt vector table for the interrupt routines associated with each interrupt request
level input.
Interrupt Request Level—WO. When writing ICW2, these bits should all be 0. During
an interrupt acknowledge cycle, these bits are programmed by the interrupt controller
with the interrupt to be serviced. This is combined with bits [7:3] to form the interrupt
vector driven onto the data bus during the second INTA# cycle. The code is a three bit
binary code:
Code Master Interrupt Slave Interrupt
000b IRQ0 IRQ8
2:0
001b IRQ1 IRQ9
010b IRQ2 IRQ10
011b IRQ3 IRQ11
100b IRQ4 IRQ12
101b IRQ5 IRQ13
110b IRQ6 IRQ14
111b IRQ7 IRQ15
12.4.4 ICW3—Master Controller Initialization Command
Word 3 Register
Offset Address: 21h Attribute: WO
Default Value: All bits undefined Size: 8 bits
Bit Description
7:3 0 = These bits must be programmed to 0.
Cascaded Interrupt Controller IRQ Connection—WO. This bit indicates that the
slave controller is cascaded on IRQ2. When IRQ8#–IRQ15 is asserted, it goes through
the slave controller’s priority resolver. The slave controller’s INTR output onto IRQ2.
2 IRQ2 then goes through the master controller’s priority solver. If it wins, the INTR
signal is asserted to the processor, and the returning interrupt acknowledge returns the
interrupt vector for the slave controller.
1 = This bit must always be programmed to a 1.
1:0 0 = These bits must be programmed to 0.
Datasheet 495
LPC Interface Bridge Registers (D31:F0)
12.4.5 ICW3—Slave Controller Initialization Command
Word 3 Register
Offset Address: A1h Attribute: WO
Default Value: All bits undefined Size: 8 bits
Bit Description
7:3 0 = These bits must be programmed to 0.
Slave Identification Code—WO. These bits are compared against the slave
identification code broadcast by the master controller from the trailing edge of the first
internal INTA# pulse to the trailing edge of the second internal INTA# pulse. These bits
2:0
must be programmed to 02h to match the code broadcast by the master controller.
When 02h is broadcast by the master controller during the INTA# sequence, the slave
controller assumes responsibility for broadcasting the interrupt vector.
12.4.6 ICW4—Initialization Command Word 4 Register
Offset Address: Master Controller – 021h Attribute: WO
Slave Controller – 0A1h Size: 8 bits
Default Value: 01h
Bit Description
7:5 0 = These bits must be programmed to 0.
Special Fully Nested Mode (SFNM)—WO.
4 0 = Should normally be disabled by writing a 0 to this bit.
1 = Special fully nested mode is programmed.
Buffered Mode (BUF)—WO.
3
0 = Must be programmed to 0 for the PCH. This is non-buffered mode.
Master/Slave in Buffered Mode—WO. Not used.
2
0 = Should always be programmed to 0.
Automatic End of Interrupt (AEOI)—WO.
1 0 = This bit should normally be programmed to 0. This is the normal end of interrupt.
1 = Automatic End of Interrupt (AEOI) mode is programmed.
Microprocessor Mode—WO.
0 1 = Must be programmed to 1 to indicate that the controller is operating in an Intel
Architecture-based system.
496 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.4.7 OCW1—Operational Control Word 1 (Interrupt Mask)
Register
Offset Address: Master Controller – 021h Attribute: R/W
Slave Controller – 0A1h Size: 8 bits
Default Value: 00h
Bit Description
Interrupt Request Mask—R/W. When a 1 is written to any bit in this register, the
corresponding IRQ line is masked. When a 0 is written to any bit in this register, the
7:0 corresponding IRQ mask bit is cleared, and interrupt requests will again be accepted by
the controller. Masking IRQ2 on the master controller will also mask the interrupt
requests from the slave controller.
12.4.8 OCW2—Operational Control Word 2 Register
Offset Address: Master Controller – 020h Attribute: WO
Slave Controller – 0A0h Size: 8 bits
Default Value: Bit[4:0]=undefined, Bit[7:5]=001
Following a part reset or ICW initialization, the controller enters the fully nested mode
of operation. Non-specific EOI without rotation is the default. Both rotation mode and
specific EOI mode are disabled following initialization.
Bit Description
Rotate and EOI Codes (R, SL, EOI)—WO. These three bits control the Rotate and End
of Interrupt modes and combinations of the two.
000 = Rotate in Auto EOI Mode (Clear)
001 = Non-specific EOI command
010 = No Operation
7:5 011 = *Specific EOI Command
100 = Rotate in Auto EOI Mode (Set)
101 = Rotate on Non-Specific EOI Command
110 = *Set Priority Command
111 = *Rotate on Specific EOI Command
*L0 – L2 Are Used
4:3 OCW2 Select—WO. When selecting OCW2, bits 4:3 = 00
Interrupt Level Select (L2, L1, L0)—WO. L2, L1, and L0 determine the interrupt level
acted upon when the SL bit is active. A simple binary code, outlined below, selects the
channel for the command to act upon. When the SL bit is inactive, these bits do not
have a defined function; programming L2, L1 and L0 to 0 is sufficient in this case.
Code Interrupt Level Code Interrupt Level
2:0
000b IRQ0/8 000b IRQ4/12
001b IRQ1/9 001b IRQ5/13
010b IRQ2/10 010b IRQ6/14
011b IRQ3/11 011b IRQ7/15
Datasheet 497
LPC Interface Bridge Registers (D31:F0)
12.4.9 OCW3—Operational Control Word 3 Register
Offset Address: Master Controller – 020h Attribute: WO
Slave Controller – 0A0h Size: 8 bits
Default Value: Bit[6,0]=0, Bit[7,4:2]=undefined,
Bit[5,1]=1
Bit Description
7 Reserved. Must be 0.
Special Mask Mode (SMM)—WO.
1 = The Special Mask Mode can be used by an interrupt service routine to dynamically
6 alter the system priority structure while the routine is executing, through selective
enabling/disabling of the other channel's mask bits. Bit 5, the ESMM bit, must be
set for this bit to have any meaning.
Enable Special Mask Mode (ESMM)—WO.
5 0 = Disable. The SMM bit becomes a “don't care”.
1 = Enable the SMM bit to set or reset the Special Mask Mode.
4:3 OCW3 Select—WO. When selecting OCW3, bits 4:3 = 01
Poll Mode Command—WO.
0 = Disable. Poll Command is not issued.
2 1 = Enable. The next I/O read to the interrupt controller is treated as an interrupt
acknowledge cycle. An encoded byte is driven onto the data bus, representing the
highest priority level requesting service.
Register Read Command—WO. These bits provide control for reading the In-Service
Register (ISR) and the Interrupt Request Register (IRR). When bit 1=0, bit 0 will not
affect the register read selection. When bit 1=1, bit 0 selects the register status
returned following an OCW3 read. If bit 0=0, the IRR will be read. If bit 0=1, the ISR
will be read. Following ICW initialization, the default OCW3 port address read will be
“read IRR”. To retain the current selection (read ISR or read IRR), always write a 0 to
bit 1 when programming this register. The selected register can be read repeatedly
1:0
without reprogramming OCW3. To select a new status register, OCW3 must be
reprogrammed prior to attempting the read.
00 = No Action
01 = No Action
10 = Read IRQ Register
11 = Read IS Register
498 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.4.10 ELCR1—Master Controller Edge/Level Triggered Register
Offset Address: 4D0h Attribute: R/W
Default Value: 00h Size: 8 bits
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In
level mode (bit[x] = 1), the interrupt is recognized by a high level. The cascade
channel, IRQ2, the heart beat timer (IRQ0), and the keyboard controller (IRQ1),
cannot be put into level mode.
Bit Description
IRQ7 ECL—R/W.
7 0 = Edge
1 = Level
IRQ6 ECL—R/W.
6 0 = Edge
1 = Level.
IRQ5 ECL—R/W.
5 0 = Edge
1 = Level
IRQ4 ECL—R/W.
4 0 = Edge
1 = Level
IRQ3 ECL—R/W.
3 0 = Edge
1 = Level
2:0 Reserved. Must be 0.
Datasheet 499
LPC Interface Bridge Registers (D31:F0)
12.4.11 ELCR2—Slave Controller Edge/Level Triggered Register
Offset Address: 4D1h Attribute: R/W
Default Value: 00h Size: 8 bits
In edge mode, (bit[x] = 0), the interrupt is recognized by a low to high transition. In
level mode (bit[x] = 1), the interrupt is recognized by a high level. The real time clock,
IRQ8#, and the floating point error interrupt, IRQ13, cannot be programmed for level
mode.
Bit Description
IRQ15 ECL—R/W.
7 0 = Edge
1 = Level
IRQ14 ECL—R/W.
6 0 = Edge
1 = Level
5 Reserved. Must be 0.
IRQ12 ECL—R/W.
4 0 = Edge
1 = Level
IRQ11 ECL—R/W.
3 0 = Edge
1 = Level
IRQ10 ECL—R/W.
2 0 = Edge
1 = Level
IRQ9 ECL—R/W.
1 0 = Edge
1 = Level
0 Reserved. Must be 0.
500 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.5 Advanced Programmable Interrupt Controller
(APIC)
12.5.1 APIC Register Map
The APIC is accessed using an indirect addressing scheme. Two registers are visible by
software for manipulation of most of the APIC registers. These registers are mapped
into memory space. The address bits 19:12 of the address range are programmable
through bits 7:0 of OIC register (Chipset Config Registers:Offset 31FEh) The registers
are shown in Table 12-4.
Table 12-4. APIC Direct Registers
Address Mnemonic Register Name Size Type
FEC_ _0000h IND Index 8 bits R/W
FEC_ _0010h DAT Data 32 bits R/W
FEC_ _0040h EOIR EOI 32 bits WO
Table 12-5 lists the registers that can be accessed within the APIC using the Index
Register. When accessing these registers, accesses must be done one DWord at a time.
For example, software should never access byte 2 from the Data register before
accessing bytes 0 and 1. The hardware will not attempt to recover from a bad
programming model in this case.
Table 12-5. APIC Indirect Registers
Index Mnemonic Register Name Size Type
00 ID Identification 32 bits R/W
01 VER Version 32 bits RO
02–0F — Reserved — RO
10–11 REDIR_TBL0 Redirection Table 0 64 bits R/W, RO
12–13 REDIR_TBL1 Redirection Table 1 64 bits R/W, RO
... ... ... ... ...
3E–3F REDIR_TBL23 Redirection Table 23 64 bits R/W, RO
40–FF — Reserved — RO
12.5.2 IND—Index Register
Memory Address FEC_ _0000h Attribute: R/W
Default Value: 00h Size: 8 bits
The Index Register will select which APIC indirect register to be manipulated by
software. The selector values for the indirect registers are listed in Table 12-5. Software
will program this register to select the desired APIC internal register.
.
Bit Description
7:0 APIC Index—R/W. This is an 8-bit pointer into the I/O APIC register table.
Datasheet 501
LPC Interface Bridge Registers (D31:F0)
12.5.3 DAT—Data Register
Memory Address FEC_ _0000h Attribute: R/W
Default Value: 00000000h Size: 32 bits
This is a 32-bit register specifying the data to be read or written to the register pointed
to by the Index register. This register can only be accessed in DWord quantities.
Bit Description
APIC Data—R/W. This is a 32-bit register for the data to be read or written to the APIC
7:0 indirect register (Figure 12-5) pointed to by the Index register (Memory Address
FEC0_0000h).
12.5.4 EOIR—EOI Register
Memory Address FEC_ _0000h Attribute: R/W
Default Value: N/A Size: 32 bits
The EOI register is present to provide a mechanism to maintain the level triggered
semantics for level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/O APIC will check the lower 8 bits written
to this register, and compare it with the vector field for each entry in the I/O
Redirection Table. When a match is found, the Remote_IRR bit (Index Offset 10h,
bit 14) for that I/O Redirection Entry will be cleared.
Note: If multiple I/O Redirection entries, for any reason, assign the same vector for more
than one interrupt input, each of those entries will have the Remote_IRR bit reset to 0.
The interrupt, which was prematurely reset, will not be lost because if its input
remained active when the Remote_IRR bit was cleared, the interrupt will be reissued
and serviced at a later time. Only bits 7:0 are actually used. Bits 31:8 are ignored by
the PCH.
Note: To provide for future expansion, the processor should always write a value of 0 to Bits
31:8.
Bit Description
Reserved. To provide for future expansion, the processor should always write a value of
31:8
0 to Bits 31:8.
Redirection Entry Clear—WO. When a write is issued to this register, the I/O APIC will
check this field, and compare it with the vector field for each entry in the I/O
7:0
Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection
Entry will be cleared.
502 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.5.5 ID—Identification Register
Index Offset: 00h Attribute: R/W
Default Value: 00000000h Size: 32 bits
The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the
APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset.
Bit Description
31:28 Reserved
27:24 APIC ID—R/W. Software must program this value before using the APIC.
23:16 Reserved
15 Scratchpad Bit.
14:0 Reserved
12.5.6 VER—Version Register
Index Offset: 01h Attribute: RO, R/WO
Default Value: 00170020h Size: 32 bits
Each I/O APIC contains a hardwired Version Register that identifies different
implementation of APIC and their versions. The maximum redirection entry information
also is in this register, to let software know how many interrupt are supported by this
APIC.
Bit Description
31:24 Reserved
Maximum Redirection Entries (MRE)—R/WO. This is the entry number (0 being the
lowest entry) of the highest entry in the redirection table. It is equal to the number of
interrupt input pins minus one and is in the range 0 through 239. In the PCH this field
23:16 is hardwired to 17h to indicate 24 interrupts.
BIOS must write to this field after PLTRST# to lockdown the value. this allows BIOS to
utilize some of the entries for its own purpose and thus advertising fewer IOxAPIC
Redirection Entries to the OS.
Pin Assertion Register Supported (PRQ)—RO. Indicate that the IOxAPIC does not
15
implement the Pin Assertion Register.
14:8 Reserved
Version (VS)—RO. This is a version number that identifies the implementation
7:0
version.
Datasheet 503
LPC Interface Bridge Registers (D31:F0)
12.5.7 REDIR_TBL—Redirection Table Register
Index Offset: 10h–11h (vector 0) through Attribute:R/W, RO
3E–3Fh (vector 23)
Default Value: Bit 16 = 1. All other bits undefined Size: 64 bits each, (accessed
as two 32 bit quantities)
The Redirection Table has a dedicated entry for each interrupt input pin. The
information in the Redirection Table is used to translate the interrupt manifestation on
the corresponding interrupt pin into an APIC message.
The APIC will respond to an edge triggered interrupt as long as the interrupt is held
until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery
status bit internally to the I/O APIC is set. The state machine will step ahead and wait
for an acknowledgment from the APIC unit that the interrupt message was sent. Only
then will the I/O APIC be able to recognize a new edge on that interrupt pin. That new
edge will only result in a new invocation of the handler if its acceptance by the
destination APIC causes the Interrupt Request Register bit to go from 0 to 1.
(In other words, if the interrupt was not already pending at the destination.)
Bit Description
Destination—R/W. If bit 11 of this entry is 0 (Physical), then bits 59:56 specifies an
APIC ID. In this case, bits 63:59 should be programmed by software to 0.
63:56
If bit 11 of this entry is 1 (Logical), then bits 63:56 specify the logical destination
address of a set of processors.
Extended Destination ID (EDID)—RO. These bits are sent to a local APIC only when
55:48
in Processor System Bus mode. They become bits 11:4 of the address.
47:17 Reserved
Mask—R/W.
0 = Not masked: An edge or level on this interrupt pin results in the delivery of the
interrupt to the destination.
1 = Masked: Interrupts are not delivered nor held pending. Setting this bit after the
16 interrupt is accepted by a local APIC has no effect on that interrupt. This behavior
is identical to the device withdrawing the interrupt before it is posted to the
processor. It is software's responsibility to deal with the case where the mask bit is
set after the interrupt message has been accepted by a local APIC unit but before
the interrupt is dispensed to the processor.
Trigger Mode—R/W. This field indicates the type of signal on the interrupt pin that
triggers an interrupt.
15
0 = Edge triggered.
1 = Level triggered.
Remote IRR—R/W. This bit is used for level triggered interrupts; its meaning is
undefined for edge triggered interrupts.
14
0 = Reset when an EOI message is received from a local APIC.
1 = Set when Local APIC/s accept the level interrupt sent by the I/O APIC.
Interrupt Input Pin Polarity—R/W. This bit specifies the polarity of each interrupt
signal connected to the interrupt pins.
13
0 = Active high.
1 = Active low.
Delivery Status—RO. This field contains the current status of the delivery of this
interrupt. Writes to this bit have no effect.
12
0 = Idle. No activity for this interrupt.
1 = Pending. Interrupt has been injected, but delivery is not complete.
504 Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit Description
Destination Mode—R/W. This field determines the interpretation of the Destination
field.
0 = Physical. Destination APIC ID is identified by bits 59:56.
11
1 = Logical. Destinations are identified by matching bit 63:56 with the Logical
Destination in the Destination Format Register and Logical Destination Register in
each Local APIC.
Delivery Mode—R/W. This field specifies how the APICs listed in the destination field
should act upon reception of this signal. Certain Delivery Modes will only operate as
10:8
intended when used in conjunction with a specific trigger mode. These encodings are
listed in the note below:
Vector—R/W. This field contains the interrupt vector for this interrupt. Values range
7:0
between 10h and FEh.
NOTE: Delivery Mode encoding:
000 = Fixed. Deliver the signal on the INTR signal of all processor cores listed in the destination.
Trigger Mode can be edge or level.
001 = Lowest Priority. Deliver the signal on the INTR signal of the processor core that is executing
at the lowest priority among all the processors listed in the specified destination. Trigger
Mode can be edge or level.
010 = SMI (System Management Interrupt). Requires the interrupt to be programmed as edge
triggered. The vector information is ignored but must be programmed to all 0s for future
compatibility: not supported
011 = Reserved
100 = NMI. Deliver the signal on the NMI signal of all processor cores listed in the destination.
Vector information is ignored. NMI is treated as an edge triggered interrupt even if it is
programmed as level triggered. For proper operation this redirection table entry must be
programmed to edge triggered. The NMI delivery mode does not set the RIRR bit. If the
redirection table is incorrectly set to level, the loop count will continue counting through
the redirection table addresses. Once the count for the NMI pin is reached again, the
interrupt will be sent again: not supported
101 = INIT. Deliver the signal to all processor cores listed in the destination by asserting the INIT
signal. All addressed local APICs will assume their INIT state. INIT is always treated as an
edge triggered interrupt even if programmed as level triggered. For proper operation this
redirection table entry must be programmed to edge triggered. The INIT delivery mode
does not set the RIRR bit. If the redirection table is incorrectly set to level, the loop count
will continue counting through the redirection table addresses. Once the count for the
INIT pin is reached again, the interrupt will be sent again: not supported
110 = Reserved
111 = ExtINT. Deliver the signal to the INTR signal of all processor cores listed in the destination
as an interrupt that originated in an externally connected 8259A compatible interrupt
controller. The INTA cycle that corresponds to this ExtINT delivery will be routed to the
external controller that is expected to supply the vector. Requires the interrupt to be
programmed as edge triggered.
Datasheet 505
LPC Interface Bridge Registers (D31:F0)
12.6 Real Time Clock Registers
12.6.1 I/O Register Address Map
The RTC internal registers and RAM are organized as two banks of 128 bytes each,
called the standard and extended banks. The first 14 bytes of the standard bank
contain the RTC time and date information along with four registers, A–D, that are used
for configuration of the RTC. The extended bank contains a full 128 bytes of battery
backed SRAM, and will be accessible even when the RTC module is disabled (using the
RTC configuration register). Registers A–D do not physically exist in the RAM.
All data movement between the host processor and the real-time clock is done through
registers mapped to the standard I/O space. The register map is shown in Table 12-6.
Table 12-6. RTC I/O Registers
I/O
If U128E bit = 0 Function
Locations
70h and 74h Also alias to 72h and 76h Real-Time Clock (Standard RAM) Index Register
71h and 75h Also alias to 73h and 77h Real-Time Clock (Standard RAM) Target Register
72h and 76h Extended RAM Index Register (if enabled)
73h and 77h Extended RAM Target Register (if enabled)
NOTES:
1. I/O locations 70h and 71h are the standard legacy location for the real-time clock.
The map for this bank is shown in Table 12-7. Locations 72h and 73h are for
accessing the extended RAM. The extended RAM bank is also accessed using an
indexed scheme. I/O address 72h is used as the address pointer and I/O address
73h is used as the data register. Index addresses above 127h are not valid. If the
extended RAM is not needed, it may be disabled.
2. Software must preserve the value of bit 7 at I/O addresses 70h and 74h. When
writing to this address, software must first read the value, and then write the same
value for bit 7 during the sequential address write. Port 70h is not directly readable.
The only way to read this register is through Alt Access mode. Although RTC Index
bits 6:0 are readable from port 74h, bit 7 will always return 0. If the NMI# enable
is not changed during normal operation, software can alternatively read this bit
once and then retain the value for all subsequent writes to port 70h.
506 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.6.2 Indexed Registers
The RTC contains two sets of indexed registers that are accessed using the two
separate Index and Target registers (70/71h or 72/73h), as shown in Table 12-7.
Table 12-7. RTC (Standard) RAM Bank
Index Name
00h Seconds
01h Seconds Alarm
02h Minutes
03h Minutes Alarm
04h Hours
05h Hours Alarm
06h Day of Week
07h Day of Month
08h Month
09h Year
0Ah Register A
0Bh Register B
0Ch Register C
0Dh Register D
0Eh–7Fh 114 Bytes of User RAM
Datasheet 507
LPC Interface Bridge Registers (D31:F0)
12.6.2.1 RTC_REGA—Register A
RTC Index: 0A Attribute: R/W
Default Value: Undefined Size: 8 bits
Lockable: No Power Well: RTC
This register is used for general configuration of the RTC functions. None of the bits are
affected by RSMRST# or any other PCH reset signal.
Bit Description
Update In Progress (UIP)—R/W. This bit may be monitored as a status flag.
0 = The update cycle will not start for at least 488 µs. The time, calendar, and alarm
7
information in RAM is always available when the UIP bit is 0.
1 = The update is soon to occur or is in progress.
Division Chain Select (DV[2:0])—R/W. These three bits control the divider chain for
the oscillator, and are not affected by RSMRST# or any other reset signal.
010 = Normal Operation
11X = Divider Reset
6:4 101 = Bypass 15 stages (test mode only)
100 = Bypass 10 stages (test mode only)
011 = Bypass 5 stages (test mode only)
001 = Invalid
000 = Invalid
Rate Select (RS[3:0])—R/W. Selects one of 13 taps of the 15 stage divider chain. The
selected tap can generate a periodic interrupt if the PIE bit is set in Register B.
Otherwise this tap will set the PF flag of Register C. If the periodic interrupt is not to be
used, these bits should all be set to 0. RS3 corresponds to bit 3.
0000 = Interrupt never toggles
0001 = 3.90625 ms
0010 = 7.8125 ms
0011 = 122.070 µs
0100 = 244.141 µs
0101 = 488.281 µs
3:0 0110 = 976.5625 µs
0111 = 1.953125 ms
1000 = 3.90625 ms
1001 = 7.8125 ms
1010 = 15.625 ms
1011 = 31.25 ms
1100 = 62.5 ms
1101 = 125 ms
1110 = 250 ms
1111= 500 ms
508 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.6.2.2 RTC_REGB—Register B (General Configuration)
RTC Index: 0Bh Attribute: R/W
Default Value: U0U00UUU (U: Undefined) Size: 8 bits
Lockable: No Power Well: RTC
Bit Description
Update Cycle Inhibit (SET)—R/W. Enables/Inhibits the update cycles. This bit is not
affected by RSMRST# nor any other reset signal.
0 = Update cycle occurs normally once each second.
1 = A current update cycle will abort and subsequent update cycles will not occur until
7 SET is returned to 0. When set is one, the BIOS may initialize time and calendar
bytes safely.
NOTE: This bit should be set then cleared early in BIOS POST after each powerup
directly after coin-cell battery insertion.
Periodic Interrupt Enable (PIE)—R/W. This bit is cleared by RSMRST#, but not on
any other reset.
6 0 = Disable.
1 = Enable. Allows an interrupt to occur with a time base set with the RS bits of register
A.
Alarm Interrupt Enable (AIE)—R/W. This bit is cleared by RTCRST#, but not on any
other reset.
5 0 = Disable.
1 = Enable. Allows an interrupt to occur when the AF is set by an alarm match from the
update cycle. An alarm can occur once a second, one an hour, once a day, or one a
month.
Update-Ended Interrupt Enable (UIE)—R/W. This bit is cleared by RSMRST#, but
not on any other reset.
4
0 = Disable.
1 = Enable. Allows an interrupt to occur when the update cycle ends.
Square Wave Enable (SQWE)—R/W. This bit serves no function in the PCH. It is left
3 in this register bank to provide compatibility with the Motorola 146818B. The PCH has
no SQW pin. This bit is cleared by RSMRST#, but not on any other reset.
Data Mode (DM)—R/W. This bit specifies either binary or BCD data representation.
This bit is not affected by RSMRST# nor any other reset signal.
2
0 = BCD
1 = Binary
Hour Format (HOURFORM)—R/W. This bit indicates the hour byte format. This bit is
not affected by RSMRST# nor any other reset signal.
1 0 = Twelve-hour mode. In twelve-hour mode, the seventh bit represents AM as 0 and
PM as one.
1 = Twenty-four hour mode.
Daylight Savings Legacy Software Support (DSLSWS)—R/W. Daylight savings
functionality is no longer supported. This bit is used to maintain legacy software
0
support and has no associated functionality. If BUC.DSO bit is set, the DSLSWS bit
continues to be R/W.
Datasheet 509
LPC Interface Bridge Registers (D31:F0)
12.6.2.3 RTC_REGC—Register C (Flag Register)
RTC Index: 0Ch Attribute: RO
Default Value: 00U00000 (U: Undefined) Size: 8 bits
Lockable: No Power Well: RTC
Writes to Register C have no effect.
Bit Description
Interrupt Request Flag (IRQF)—RO. IRQF = (PF * PIE) + (AF * AIE) + (UF *UFE).
7 This bit also causes the RTC Interrupt to be asserted. This bit is cleared upon RSMRST#
or a read of Register C.
Periodic Interrupt Flag (PF)—RO. This bit is cleared upon RSMRST# or a read of
Register C.
6 0 = If no taps are specified using the RS bits in Register A, this flag will not be set.
1 = Periodic interrupt Flag will be 1 when the tap specified by the RS bits of register A is
1.
Alarm Flag (AF)—RO.
5 0 = This bit is cleared upon RTCRST# or a read of Register C.
1 = Alarm Flag will be set after all Alarm values match the current time.
Update-Ended Flag (UF)—RO.
4 0 = The bit is cleared upon RSMRST# or a read of Register C.
1 = Set immediately following an update cycle for each second.
3:0 Reserved. Will always report 0.
12.6.2.4 RTC_REGD—Register D (Flag Register)
RTC Index: 0Dh Attribute: R/W
Default Value: 10UUUUUU (U: Undefined) Size: 8 bits
Lockable: No Power Well: RTC
Bit Description
Valid RAM and Time Bit (VRT)—R/W.
0 = This bit should always be written as a 0 for write cycle, however it will return a 1 for
7
read cycles.
1 = This bit is hardwired to 1 in the RTC power well.
6 Reserved. This bit always returns a 0 and should be set to 0 for write cycles.
Date Alarm—R/W. These bits store the date of month alarm value. If set to 000000b,
then a don’t care state is assumed. The host must configure the date alarm for these
5:0 bits to do anything, yet they can be written at any time. If the date alarm is not
enabled, these bits will return 0s to mimic the functionality of the Motorola 146818B.
These bits are not affected by any reset assertion.
510 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.7 Processor Interface Registers
Table 12-8 is the register address map for the processor interface registers.
Table 12-8. Processor Interface PCI Register Address Map
Offset Mnemonic Register Name Default Attribute
61h NMI_SC NMI Status and Control 00h R/W, RO
70h NMI_EN NMI Enable 80h R/W (special)
92h PORT92 Init 00h R/W
F0h COPROC_ERR Coprocessor Error 00h WO
CF9h RST_CNT Reset Control 00h R/W
12.7.1 NMI_SC—NMI Status and Control Register
I/O Address: 61h Attribute: R/W, RO
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Core
Bit Description
SERR# NMI Source Status (SERR#_NMI_STS)—RO.
1 = Bit is set if a PCI agent detected a system error and pulses the PCI SERR# line and
if bit 2 (PCI_SERR_EN) is cleared. This interrupt source is enabled by setting bit 2
to 0. To reset the interrupt, set bit 2 to 1 and then set it to 0. When writing to port
7
61h, this bit must be 0.
NOTE: This bit is set by any of the PCH internal sources of SERR; this includes SERR
assertions forwarded from the secondary PCI bus, errors on a PCI Express*
port, or other internal functions that generate SERR#.
IOCHK# NMI Source Status (IOCHK_NMI_STS)—RO.
1 = Bit is set if an LPC agent (using SERIRQ) asserted IOCHK# and if bit 3
6 (IOCHK_NMI_EN) is cleared. This interrupt source is enabled by setting bit 3 to 0.
To reset the interrupt, set bit 3 to 1 and then set it to 0. When writing to port 61h,
this bit must be a 0.
Timer Counter 2 OUT Status (TMR2_OUT_STS)—RO. This bit reflects the current
state of the 8254 counter 2 output. Counter 2 must be programmed following any PCI
5
reset for this bit to have a determinate value. When writing to port 61h, this bit must
be a 0.
Refresh Cycle Toggle (REF_TOGGLE)—RO. This signal toggles from either 0 to 1 or
4 1 to 0 at a rate that is equivalent to when refresh cycles would occur. When writing to
port 61h, this bit must be a 0.
IOCHK# NMI Enable (IOCHK_NMI_EN)—R/W.
3 0 = Enabled.
1 = Disabled and cleared.
PCI SERR# Enable (PCI_SERR_EN)—R/W.
2 0 = SERR# NMIs are enabled.
1 = SERR# NMIs are disabled and cleared.
Speaker Data Enable (SPKR_DAT_EN)—R/W.
1 0 = SPKR output is a 0.
1 = SPKR output is equivalent to the Counter 2 OUT signal value.
Timer Counter 2 Enable (TIM_CNT2_EN)—R/W.
0 0 = Disable
1 = Enable
Datasheet 511
LPC Interface Bridge Registers (D31:F0)
12.7.2 NMI_EN—NMI Enable (and Real Time Clock Index)
Register
I/O Address: 70h Attribute: R/W (special)
Default Value: 80h Size: 8 bits
Lockable: No Power Well: Core
Note: The RTC Index field is write-only for normal operation. This field can only be read in Alt-
Access Mode. Note, however, that this register is aliased to Port 74h (documented in
Table 12-6), and all bits are readable at that address.
Bits Description
NMI Enable (NMI_EN)—R/W (special).
7 0 = Enable NMI sources.
1 = Disable All NMI sources.
Real Time Clock Index Address (RTC_INDX)—R/W (special). This data goes to the
6:0
RTC to select which register or CMOS RAM address is being accessed.
12.7.3 PORT92—Init Register
I/O Address: 92h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Core
Bit Description
7:2 Reserved
Alternate A20 Gate (ALT_A20_GATE)—R/W. Functionality reserved. A20M#
1
functionality is not supported.
INIT_NOW—R/W. When this bit transitions from a 0 to a 1, the PCH will force INIT#
0
active for 16 PCI clocks.
12.7.4 COPROC_ERR—Coprocessor Error Register
I/O Address: F0h Attribute: WO
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Core
Bits Description
Coprocessor Error (COPROC_ERR)—WO. Any value written to this register will
7:0 cause IGNNE# to go active, if FERR# had generated an internal IRQ13. For FERR# to
generate an internal IRQ13, the COPROC_ERR_EN bit must be 1.
512 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.7.5 RST_CNT—Reset Control Register
I/O Address: CF9h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Core
Bit Description
7:4 Reserved
Full Reset (FULL_RST)—R/W. This bit is used to determine the states of SLP_S3#,
SLP_S4#, and SLP_S5# after a CF9 hard reset (SYS_RST =1 and RST_CPU is set to 1),
after PWROK going low (with RSMRST# high), or after two TCO timeouts.
0 = PCH will keep SLP_S3#, SLP_S4# and SLP_S5# high.
3
1 = PCH will drive SLP_S3#, SLP_S4# and SLP_S5# low for 3–5 seconds.
NOTE: When this bit is set, it also causes the full power cycle (SLP_S3/4/5# assertion)
in response to SYS_RESET#, PWROK#, and Watchdog timer reset sources.
Reset Processor (RST_CPU)—R/W. When this bit transitions from a 0 to a 1, it
2
initiates a hard or soft reset, as determined by the SYS_RST bit (bit 1 of this register).
System Reset (SYS_RST)—R/W. This bit is used to determine a hard or soft reset to
the processor.
0 = When RST_CPU bit goes from 0 to 1, the PCH performs a soft reset by activating
INIT# for 16 PCI clocks.
1 = When RST_CPU bit goes from 0 to 1, the PCH performs a hard reset by activating
1
PLTRST# and SUS_STAT# active for a minimum of about 1 milliseconds. In this
case, SLP_S3#, SLP_S4# and SLP_S5# state (assertion or de-assertion) depends
on FULL_RST bit setting. The PCH main power well is reset when this bit is 1. It
also resets the resume well bits (except for those noted throughout this
document).
0 Reserved
Datasheet 513
LPC Interface Bridge Registers (D31:F0)
12.8 Power Management Registers
The power management registers are distributed within the PCI Device 31: Function 0
space, as well as a separate I/O range. Each register is described below. Unless
otherwise indicated, bits are in the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to
a reserved bit, the value should always be 0. Software should not attempt to use the
value read from a reserved bit, as it may not be consistently 1 or 0.
12.8.1 Power Management PCI Configuration Registers
(PM—D31:F0)
Table 12-9 shows a small part of the configuration space for PCI Device 31: Function 0.
It includes only those registers dedicated for power management. Some of the
registers are only used for Legacy Power management schemes.
Table 12-9. Power Management PCI Register Address Map (PM—D31:F0)
Offset Mnemonic Register Name Default Attribute
General Power Management R/W, R/WLO,
A0h–A1h GEN_PMCON_1 0000h
Configuration 1 RO
General Power Management R/W, R/WC,
A2–A3h GEN_PMCON_2 2000h
Configuration 2 RO
General Power Management R/W, R/WC,
A4h–A5h GEN_PMCON_3 4206h
Configuration 3 RO, R/WL
GEN_PMCON_LO General Power Management
A6h 00h RO, R/WL
CK Configuration Lock
AAh BM_BREAK_EN_2 BM_BREAK_EN Register #2 00h R/W, RO
ABh BM_BREAK_EN BM_BREAK_EN Register 00h R/W, RO
ACh–AFh PMIR Power Management Initialization 00000000h R/W, R/WLO
B8h–BBh GPI_ROUT GPI Routing Control Register 00000000h R/W
BCh–BFh GPI_ROUT2 GPI Routing Control Register #2 00000000h R/W
514 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.8.1.1 GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0)
Offset Address: A0–A1h Attribute: R/W, RO, R/WLO
Default Value: 0000h Size: 16 bits
Lockable: No Usage: ACPI, Legacy
Power Well: Core
Bit Description
15 Reserved
14 GEN_PMCON_1 Field 4—R/W. BIOS may write to this field.
13 GEN_PMCON_1 Field 3—R/W. BIOS may write to this field.
12 GEN_PMCON_1 Field 2—R/W. BIOS may write to this field.
11 GEN_PMCON_1 Field 1—R/W. BIOS must program this field to 1b.
BIOS_PCI_EXP_EN—R/W. This bit acts as a global enable for the SCI associated
with the PCI Express* ports.
0 = The various PCI Express ports and processor cannot cause the PCI_EXP_STS
10
bit to go active.
1 = The various PCI Express ports and processor can cause the PCI_EXP_STS bit to
go active.
PWRBTN_LVL—RO. This bit indicates the current state of the PWRBTN# signal.
9 0 = Low.
1 = High.
8:7 Reserved
SMI_LOCK_GP22—R/WLO. When this bit is set, writes to GPI_ROUT2[7:6],
ALT_GPI_SMI_EN2[3], and GP_IO_SEL[22] will have no effect. Once the
6
SMI_LOCK_GP22 bit is set, writes of 0 to SMI_LOCK_GP22 have no effect (that is,
once set, this bit can only be cleared by PLTRST#).
SMI_LOCK_GP6—R/WLO. When this bit is set, writes to GPI_ROUT[13:12],
ALT_GPI_SMI_EN[6] and GP_IO_SEL[6] will have no effect. Once the
5
SMI_LOCK_GP6 bit is set, writes of 0 to SMI_LOCK_GP6 have no effect (that is,
once set, this bit can only be cleared by PLTRST#).
SMI_LOCK—R/WLO. When this bit is set, writes to the GLB_SMI_EN bit (PMBASE
+ 30h, bit 0) will have no effect. Once the SMI_LOCK bit is set, writes of 0 to
4
SMI_LOCK bit will have no effect (that is, once set, this bit can only be cleared by
PLTRST#).
3 (Mobile
Reserved
Only)
Pseudo CLKRUN_EN(PSEUDO_CLKRUN_EN)—R/W.
0 = Disable.
1 = Enable internal CLKRUN# logic to allow DMI PLL shutdown. This bit has no
impact on state of external CLKRUN# pin.
3 (Desktop
Only) NOTES:
1. PSEUDO_CLKRUN_EN bit does not result in STP_PCI# assertion to actually
stop the external PCICLK.
2. This bit should be set mutually exclusive with the CLKRUN_EN bit. Setting
PSEUDO_CLKRUN_EN in a mobile SKU could result in unspecified behavior.
Datasheet 515
LPC Interface Bridge Registers (D31:F0)
Bit Description
PCI CLKRUN# Enable (CLKRUN_EN)—R/W.
0 = Disable. PCH drives the CLKRUN# signal low.
1 = Enable CLKRUN# logic to control the system PCI clock using the CLKRUN# and
STP_PCI# signals.
2 (Mobile NOTES:
Only) 1. When the SLP_EN# bit is set, the PCH drives the CLKRUN# signal low
regardless of the state of the CLKRUN_EN bit. This ensures that the PCI and
LPC clocks continue running during a transition to a sleep state.
2. This bit should be set mutually exclusive with the PSEUDO_CLKRUN_EN bit.
Setting CLKRUN_EN in a non-mobile SKU could result in unspecified
behavior.
2 (Desktop
Reserved
Only)
Periodic SMI# Rate Select (PER_SMI_SEL)—R/W. Set by software to control
the rate at which periodic SMI# is generated.
1:0 00 = 64 seconds
01 = 32 seconds
10 = 16 seconds
11 = 8 seconds
12.8.1.2 GEN_PMCON_2—General PM Configuration 2 Register
(PM—D31:F0)
Offset Address: A2–A3h Attribute: R/W, RO, R/WC
Default Value: 2000h Size: 16 bits
Lockable: No Usage: ACPI, Legacy
Power Well: RTC, SUS
Bit Description
15 Reserved
DC_PP_DIS—R/W. On DC PHY Power Diable.
• When this bit is set, SLP_LAN# will be driven low when ACPRESENT is low. This
indicates that LAN PHY should be powered off on battery mode.
14 • When this bit is cleared (default), ACPRESENT state does not impact SLP_LAN#
value.
Refer to Section 5.14.10.5 for more details on SLP_LAN# value.
This bit is reset by RTCRST#.
DSX_PP_DIS—/W. In Deep Sx PHY Power Disable.
• When this bit is set (default), SLP_LAN# will be driven low in Deep Sx.
• When cleared, SLP_LAN# status in Deep Sx is dependant on status of Sx_PP_EN
13
setting.
Refer to Section 5.14.10.5 for more details on SLP_LAN# value.
This bit is reset by RTCRST#.
AG3_PP_EN—R/W. After G3 PHY Power Enable.
• When this bit is cleared (default), SLP_LAN# will be driven low upon exiting G3.
• When this bit is set, SLP_LAN# value is dependant on DSX_PP_DIS and Sx_PP_EN
12
setting.
Refer to Section 5.14.10.5 for more details on SLP_LAN# value.
This bit is reset by RTCRST#.
516 Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit Description
Sx_PP_EN—R/W. Sx PHY Power Enable (Non G3 to Sx entry)
• When this bit is cleared (default), SLP_LAN# will be driven low in Sx/Moff.
11 • When this bit is set, SLP_LAN# will be driven high in Sx/Moff.
Refer to Section 5.14.10.5 for more details on SLP_LAN# value.
This bit is on VCCDSW3_3 and is reset when DSW is reset.
10:8 Reserved
DRAM Initialization Bit—R/W. This bit does not affect hardware functionality in any
way. BIOS is expected to set this bit prior to starting the DRAM initialization sequence
and to clear this bit after completing the DRAM initialization sequence. BIOS can detect
7 that a DRAM initialization sequence was interrupted by a reset by reading this bit during
the boot sequence.
• If the bit is 1, then the DRAM initialization was interrupted.
• This bit is reset by the assertion of the RSMRST# pin.
6 Reserved
Memory Placed in Self-Refresh (MEM_SR)—RO.
• If the bit is 1, DRAM should have remained powered and held in Self-Refresh
5
through the last power state transition (that is, the last time the system left S0).
• This bit is reset by the assertion of the RSMRST# pin.
System Reset Status (SRS)—R/WC. Software clears this bit by writing a 1 to it.
0 = SYS_RESET# button Not pressed.
1 = PCH sets this bit when the SYS_RESET# button is pressed. BIOS is expected to
read this bit and clear it, if it is set.
4
NOTES:
1. This bit is also reset by RSMRST# and CF9h resets.
2. The SYS_RESET# is implemented in the Main power well. This pin must be
properly isolated and masked to prevent incorrectly setting this Suspend well
status bit.
Processor Thermal Trip Status (CTS)—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when PLTRST# is inactive and THRMTRIP# goes active while the
system is in an S0 or S1 state.
3 NOTES:
1. This bit is also reset by RSMRST#, and CF9h resets. It is not reset by the
shutdown and reboot associated with the processor THRMTRIP# event.
2. The CF9h reset in the description refers to CF9h type core well reset which
includes SYS_RESET#, PWROK/SYS_PWROK low, SMBus hard reset, TCO
Timeout. This type of reset will clear CTS bit.
Minimum SLP_S4# Assertion Width Violation Status—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Hardware sets this bit when the SLP_S4# assertion width is less than the time
programmed in the SLP_S4# Minimum Assertion Width field (D31:F0:Offset
A4h:bits 5:4). The PCH begins the timer when SLP_S4# is asserted during S4/S5
entry or when the RSMRST# input is de-asserted during SUS well power-up. This
2
bit is functional regardless of the values in the SLP_S4# Assertion Stretch Enable
(D31:F0:Offset A4h:bit 3) and in the Disable SLP Stretching after SUS Well Power
Up (D31:F0:Offset A4h:bit 12).
NOTE: This bit is reset by the assertion of the RSMRST# pin, but can be set in some
cases before the default value is readable.
Datasheet 517
LPC Interface Bridge Registers (D31:F0)
Bit Description
SYS_PWROK Failure (SYSPWR_FLR)—R/WC.
0 = This bit will be cleared only be software writing a 1 back to the bit or by SUS well
1 power loss.
1 = This bit will be set any time SYS_PWROK drops unexpectedly when the system was
in S0 or S1 state.
PWROK Failure (PWROK_FLR)—R/WC.
0 = This bit will be cleared only be software writing a 1 back to the bit or by SUS well
power loss.
0
1 = This bit will be set any time PWROK goes low when the system was in S0 or S1
state.
NOTE: See Chapter 5.14.10.3 for more details about the PWROK pin functionality.
12.8.1.3 GEN_PMCON_3—General PM Configuration 3 Register
(PM—D31:F0)
Offset Address: A4-A5h Attribute: R/W, R/WC, RO, R/WL
Default Value: 4206h Size: 16 bits
Lockable: No Usage: ACPI, Legacy
Power Well: RTC, SUS
Bit Description
PME B0 S5 Disable (PME_B0_S5_DIS)—R/W. When set to 1, this bit blocks
wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN.
When cleared (default), wake events from PME_B0_STS are allowed in S5 if
PME_B0_EN = 1.
Wakes from power states other than S5 are not affected by this policy bit.
The net effect of setting PME_B0_S5_DIS = '1' is described by the truth table
below:
Y = Wake; N = Don't wake; B0 = PME_B0_EN; OV = WoL Enable Override
15
B0/OV S1/S3/S4 S5
00 N N
01 N Y (LAN only)
11 Y (all PME B0 sources) Y (LAN only)
10 Y (all PME B0 sources) N
This bit is cleared by the RTCRST# pin.
SUS Well Power Failure (SUS_PWR_FLR)—R/WC.
0 = Software writes a 1 to this bit to clear it.
1 = This bit is set to '1' whenever SUS well power is lost, as indicated by RSMRST#
14
assertion.
This bit is in the SUS well, and defaults to '1' based on RSMRST# assertion (not
cleared by any type of reset).
WoL Enable Override (WOL_EN_OVRD)—R/W.
0 = WoL policies are determined by PMEB0 enable bit and appropriate LAN status
bits
13
1 = Enable appropriately configured integrated LAN to wake the system in S5 only
regardless of the value in the PME_B0_EN bit in the GPE0_EN register.
This bit is cleared by the RTCRST# pin.
518 Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit Description
Disable SLP Stretching After SUS Well Power Up
(DIS_SLP_STRCH_SUS_UP): R/WL
0 = Enables stretching on SLP signals after SUS power failure as enabled and
configured in other fields.
1 = Disables stretching on SLP signals when powering up after a SUS well power
loss. regardless of the state of the SLP_S4# Assertion Stretch Enable (bit 3).
This bit is cleared by the RTCRST# pin.
NOTES:
12 1. This field is RO when the SLP Stretching Policy Lock-Down bit is set.
2. If this bit is cleared, SLP stretch timers start on SUS well power up (the
PCH has no ability to count stretch time while the SUS well is powered
down).
3. This policy bit has a different effect on SLP_SUS# stretching than on the
other SLP_* pins since SLP_SUS# is the control signal for one of the
scenarios where SUS well power is lost (Deep Sx). The effect of setting this
bit to '1' on:
— SLP_S3# and SLP_S4# stretching: disabled after any SUS power loss.
— SLP_SUS# stretching: disabled after G3, but no impact on Deep Sx.
SLP_S3# Minimum Assertion Width (SLP_S3_MIN_ASST_WDTH): R/WL
This 2-bit value indicates the minimum assertion width of the SLP_S3# signal to
ensure that the Main power supplies have been fully power-cycled.
Valid Settings are:
00 = 60 us
11:10 01 = 1 ms
10 = 50 ms
11 = 2 s
This bit is cleared by the RSMRST# pin.
NOTE: This field is RO when the SLP Stretching Policy Lock-Down bit is set.
General Reset Status (GEN_RST_STS)—R/WC. This bit is set by hardware
whenever PLTRST# asserts for any reason other than going into a software-
entered sleep state (using PM1CNT.SLP_EN write) or a suspend well power failure
(RSMRST# pin assertion). BIOS is expected to consult and then write a 1 to clear
9
this bit during the boot flow before determining what action to take based on
PM1_STS.WAK_STS = 1. If GEN_RST_STS = 1, the cold reset boot path should be
followed rather than the resume path, regardless of the setting of WAK_STS.
This bit is cleared by the RSMRST# pin.
8 Reserved.
SWSMI_RATE_SEL—R/W. This field indicates when the SWSMI timer will time
out.
Valid values are:
00 = 1.5 ms ± 0.6 ms
7:6
01 = 16 ms ± 4 ms
10 = 32 ms ± 4 ms
11 = 64 ms ± 4 ms
These bits are not cleared by any type of reset except RTCRST#.
Datasheet 519
LPC Interface Bridge Registers (D31:F0)
Bit Description
SLP_S4# Minimum Assertion Width(SLP_S4_MIN_ASST_WDTH)—R/WL.
This field indicates the minimum assertion width of the SLP_S4# signal to ensure
that the DRAM modules have been safely power-cycled.
Valid values are:
11 = 1 second
10 = 2 seconds
01 = 3 seconds
00 = 4 seconds
This value is used in two ways:
1. If the SLP_S4# assertion width is ever shorter than this time, a status bit is
5:4
set for BIOS to read when S0 is entered.
2. If enabled by bit 3 in this register, the hardware will prevent the SLP_S4#
signal from de-asserting within this minimum time period after asserting.
RTCRST# forces this field to the conservative default state (00b).
NOTES:
1. This field is RO when the SLP Stretching Policy Lock-Down bit is set.
2. The logic that measures this time is in the suspend power well. Therefore,
when leaving a G3 or Deep Sx state, the minimum time is measured from
the de-assertion of the internal suspend well reset (unless the “Disable SLP
SLP_S4# Assertion Stretch Enable—R/WL.
0 = The SLP_S4# minimum assertion time is defined in Power Sequencing and
Reset Signal Timings table.
1 = The SLP_S4# signal minimally assert for the time specified in bits 5:4 of this
3
register.
This bit is cleared by RTCRST#.
NOTE: This bit is RO when the SLP Stretching Policy Lock-Down bit is set.
RTC Power Status (RTC_PWR_STS)—R/W. This bit is set when RTCRST#
2 indicates a weak or missing battery. The bit is not cleared by any type of reset. The
bit will remain set until the software clears it by writing a 0 back to this bit position.
Power Failure (PWR_FLR)—R/WC. This bit is in the DeepSx well and defaults to
1 based on DPWROK de-assertion (not cleared by any type of reset).
0 = Indicates that the trickle current has not failed since the last time the bit was
cleared. Software clears this bit by writing a 1 to it.
1 1 = Indicates that the trickle current (from the main battery or trickle supply) was
removed or failed.
NOTE: Clearing CMOS in a PCH-based platform can be done by using a jumper on
RTCRST# or GPI. Implementations should not attempt to clear CMOS by
using a jumper to pull VccRTC low.
AFTERG3_EN—R/W. This bit determines what state to go to when power is re-
applied after a power failure (G3 state). This bit is in the RTC well and is only
cleared by RTCRST# assertion.
0 = System will return to S0 state (boot) after power is re-applied.
0
1 = System will return to the S5 state (except if it was in S4, in which case it will
return to S4). In the S5 state, the only enabled wake event is the Power
Button or any enabled wake event that was preserved through the power
failure.
NOTE: RSMRST# is sampled using the RTC clock. Therefore, low times that are less than one RTC
clock period may not be detected by the PCH.
520 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.8.1.4 GEN_PMCON_LOCK—General Power Management Configuration
Lock Register
Offset Address: A6h Attribute: RO, R/WLO
Default Value: 00h Size: 8 bits
Lockable: No Usage: ACPI
Power Well: Core
Bit Description
7:3 Reserved
SLP Stretching Policy Lock-Down (SLP_STR_POL_LOCK)—R/WLO. When set
to 1, this bit locks down the Disable SLP Stretching After SUS Well Power Up,
SLP_S3# Minimum Assertion Width, SLP_S4# Minimum Assertion Width, SLP_S4#
Assertion Stretch Enable bits in the GEN_PMCON_3 register, making them read-
2 only.
This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit
are always ignored.
This bit is cleared by platform reset.
ACPI_BASE_LOCK—R/WLO. When set to 1, this bit locks down the ACPI Base
Address Register (ABASE) at offset 40h. The Base Address Field becomes read-
only.
1
This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit
are always ignored. Once locked by writing 1, the only way to clear this bit is to
perform a platform reset.
0 Reserved
12.8.1.5 BM_BREAK_EN_2 Register #2 (PM—D31:F0)
Offset Address: AAh Attribute: R/W, RO
Default Value: 00h Size: 8 bits
Lockable: No Usage: ACPI, Legacy
Power Well: Core
Bit Description
7:2 Reserved
xHCI Break Enable (xHCI_BREAK_EN)—R/W.
1 0 = xHCI traffic will not cause BM_STS to be set.
1 = xHCI traffic will cause BM_STS to be set.
SATA3 Break Enable (SATA3_BREAK_EN)—R/W.
0 0 = SATA3 traffic will not cause BM_STS to be set.
1 = SATA3 traffic will cause BM_STS to be set.
Datasheet 521
LPC Interface Bridge Registers (D31:F0)
12.8.1.6 BM_BREAK_EN Register (PM—D31:F0)
Offset Address: ABh Attribute: R/W, RO
Default Value: 00h Size: 8 bits
Lockable: No Usage: ACPI, Legacy
Power Well: Core
Bit Description
Storage Break Enable (STORAGE_BREAK_EN)—R/W.
7 0 = Serial ATA traffic will not cause BM_STS to be set.
1 = Serial ATA traffic will cause BM_STS to be set.
PCIE_BREAK_EN—R/W.
6 0 = PCI Express* traffic will not cause BM_STS to be set.
1 = PCI Express traffic will cause BM_STS to be set.
5:3 Reserved
EHCI_BREAK_EN—R/W.
2 0 = EHCI traffic will not cause BM_STS to be set.
1 = EHCI traffic will cause BM_STS to be set.
1 Reserved
HDA_BREAK_EN—R/W.
0 0 = Intel High Definition Audio traffic will not cause BM_STS to be set.
1 = Intel High Definition Audio traffic will cause BM_STS to be set.
522 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.8.1.7 GPI_ROUT—GPI Routing Control Register
(PM—D31:F0)
Offset Address: B8h–BBh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Lockable: No Power Well: Suspend
Bit Description
31:30 GPI 15 Route—R/W. See bits 1:0 for description.
29:28 GPI 14 Route—R/W. See bits 1:0 for description.
27:26 GPI 13 Route—R/W. See bits 1:0 for description.
25:24 GPI 12 Route—R/W. See bits 1:0 for description.
23:22 GPI 11 Route—R/W. See bits 1:0 for description.
21:20 GPI 10 Route—R/W. See bits 1:0 for description.
19:18 GPI 9 Route—R/W. See bits 1:0 for description.
17:16 GPI 8 Route—R/W. See bits 1:0 for description.
15:14 GPI 7 Route—R/W. See bits 1:0 for description.
13:12 GPI 6 Route—R/W. See bits 1:0 for description.
11:10 GPI 5 Route—R/W. See bits 1:0 for description.
9:8 GPI 4 Route—R/W. See bits 1:0 for description.
7:6 GPI 3 Route—R/W. See bits 1:0 for description.
5:4 GPI 2 Route—R/W. See bits 1:0 for description.
3:2 GPI 1 Route—R/W. See bits 1:0 for description.
GPI 0 Route—R/W. If the corresponding GPIO is implemented and is configured as an
Input, then a ‘1’ in the corresponding GP_LVL bit can be routed to cause an interrupt.
The type of interrupt (that is, NMI, SMI# or SCI) depends on the configuration bits in
this register as well as the configuration bits in related registers, as described below.
00 = No effect.
01 = SMI# (if corresponding ALT_GPI_SMI_EN bit is also set).
1:0 10 = SCI (if corresponding GPE0_EN bit is also set).
11 = NMI (if corresponding GPI_NMI_EN is also set).
If the system is in an S3–S5 state and if the GPE0_EN bit is also set, then the GPIO can
cause a Wake event from Sx state, even if the GPIO is NOT routed to cause an NMI,
SMI#, or SCI. Exception: If the system is in S5 state due to a power button override,
then the GPIs will not cause wake events. Further, Core well GPIs are not capable of
waking the system from sleep states where the Core well is not powered.
NOTE: If the GPIO is not set to an input, or if the Native function is selected, then the
corresponding field in this register has no effect.
Datasheet 523
LPC Interface Bridge Registers (D31:F0)
12.8.1.8 GPI_ROUT2—GPI Routing Control Register #2 (PM-D31:F0)
Offset Address: BCh–BFh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Lockable: No Power Well: Suspend
Bit Description
31:16 Reserved
15:14 GPI60 Route—R/W. See bits 1:0 for description.
13:12 GPI57 Route—R/W. See bits 1:0 for description.
11:10 GPI56 Route—R/W. See bits 1:0 for description.
9:8 GPI43 Route—R/W. See bits 1:0 for description.
7:6 GPI22 Route—R/W. See bits 1:0 for description.
5:4 GPI21 Route—R/W. See bits 1:0 for description.
3:2 GPI19 Route—R/W. See bits 1:0 for description.
GPI17 Route—R/W. If the corresponding GPIO is implemented and is configured as an
Input, then a ‘1’ in the corresponding GP_LVL bit can be routed to cause an interrupt.
The type of interrupt (that is, NMI, SMI# or SCI) depends on the configuration bits in
this register as well as the configuration bits in related registers, as described below.
00 = No effect.
01 = SMI# (if corresponding ALT_GPI_SMI_EN2 bit is also set).
1:0 10 = SCI (if corresponding GPE0_EN bit is also set).
11 = NMI (if corresponding GPI_NMI_EN is also set).
If the system is in an S3–S5 state and if the GPE0_EN bit is also set, then the GPIO can
cause a Wake event from Sx state, even if the GPIO is NOT routed to cause an NMI,
SMI# or SCI. Exception: If the system is in S5 state due to a power button override,
then the GPIs will not cause wake events. Further, Core well GPIs are not capable of
waking the system from sleep states where the Core well is not powered.
NOTE: If the GPIO is not set to an input, or if the Native function is selected, then the
corresponding field in this register has no effect.
12.8.2 APM I/O Decode Register
Table 12-10 shows the I/O registers associated with APM support. This register space is
enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved
(fixed I/O location).
Table 12-10. APM Register Map
Address Mnemonic Register Name Default Type
B2h APM_CNT Advanced Power Management Control Port 00h R/W
B3h APM_STS Advanced Power Management Status Port 00h R/W
524 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.8.2.1 APM_CNT—Advanced Power Management Control Port Register
I/O Address: B2h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Usage: Legacy Only
Power Well: Core
Bit Description
Used to pass an APM command between the OS and the SMI handler. Writes to this
7:0 port not only store data in the APMC register, but also generates an SMI# when the
APMC_EN bit is set.
12.8.2.2 APM_STS—Advanced Power Management Status Port Register
I/O Address: B3h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Usage: Legacy Only
Power Well: Core
Bit Description
Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad
7:0
register and is not affected by any other register or function (other than a PCI reset).
Datasheet 525
LPC Interface Bridge Registers (D31:F0)
12.8.3 Power Management I/O Registers
Table 12-11 shows the registers associated with ACPI and Legacy power management
support. These registers locations are all offsets from the ACPI base address defined in
the PCI Device 31: Function 0 space (PMBASE), and can be moved to any 128-byte
aligned I/O location. In order to access these registers, the ACPI Enable bit (ACPI_EN)
must be set. The registers are defined to support the ACPI 4.0a specification and
generally use the same bit names.
Note: All reserved bits and registers will always return 0 when read, and will have no effect
when written.
Table 12-11. ACPI and Legacy I/O Register Map
PMBASE
Mnemonic Register Name Default Attribute
+ Offset
00h–01h PM1_STS PM1 Status 0000h R/WC
02h–03h PM1_EN PM1 Enable 0000h R/W
04h–07h PM1_CNT PM1 Control 00000000h R/W, WO
08h–0Bh PM1_TMR PM1 Timer 00000000h RO
0000000000
20h–27h GPE0_STS General Purpose Event 0 Status RO, R/WC
000000h
00000000
28h–2Fh GPE0_EN General Purpose Event 0 Enables RO, R/W
00000000h
R/W, WO,
30h–33h SMI_EN SMI# Control and Enable 00000002h
R/WO
34h–37h SMI_STS SMI Status 00000000h R/WC, RO
38h–39h ALT_GPI_SMI_EN Alternate GPI SMI Enable 0000h R/W
3Ah–3Bh ALT_GPI_SMI_STS Alternate GPI SMI Status 0000h R/WC
42h GPE_CNTL General Purpose Event Control 00h R/W
44h–45h DEVACT_STS Device Activity Status 0000h R/WC
50h PM2_CNT PM2 Control 00h R/W
Alternate GPI SMI Enable 2
5Ch–5Dh ALT_GPI_SMI_EN2 0000h R/W, RO
Register
Alternate GPI SMI Status 2
5Eh–5Fh ALT_GPI_SMI_STS2 0000h RO, RWC
Register
60h–7Fh — Reserved for TCO — —
526 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.8.3.1 PM1_STS—Power Management 1 Status Register
I/O Address: PMBASE + 00h Attribute: R/WC
Default Value: 0000h Size: 16 bits
Lockable: No Usage: ACPI or Legacy
Power Well: Bits 0–7: Core,
Bits 12-15: Suspend
Bit 11: RTC,
Bits 8, 10 and 14: DSW
If bit 10 or 8 in this register is set, and the corresponding _EN bit is set in the PM1_EN
register, then the PCH will generate a Wake Event. Once back in an S0 state (or if
already in an S0 state when the event occurs), the PCH will also generate an SCI if the
SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set.
Note: Bit 5 does not cause an SMI# or a wake event. Bit 0 does not cause a wake event but
can cause an SMI# or SCI.
Bit Description
Wake Status (WAK_STS)—R/WC. This bit is not affected by hard resets caused by a
CF9 write, but is reset by RSMRST#.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the system is in one of the sleep states (using the SLP_EN
bit) and an enabled wake event occurs. Upon setting this bit, the PCH will transition
the system to the ON state.
15 If the AFTERG3_EN bit is not set and a power failure (such as removed batteries)
occurs without the SLP_EN bit set, the system will return to an S0 state when power
returns, and the WAK_STS bit will not be set.
If the AFTERG3_EN bit is set and a power failure occurs without the SLP_EN bit having
been set, the system will go into an S5 state when power returns, and a subsequent
wake event will cause the WAK_STS bit to be set. Any subsequent wake event would
have to be caused by either a Power Button press, or an enabled wake event that was
preserved through the power failure (enable bit in the RTC well).
PCI Express* Wake Status (PCIEXPWAK_STS)—R/WC.
0 = Software clears this bit by writing a 1 to it. If the WAKE# pin is still active during
the write or the PME message received indication has not been cleared in the root
port, then the bit will remain active (that is, all inputs to this bit are level-
sensitive).
1 = This bit is set by hardware to indicate that the system woke due to a PCI Express
wakeup event. This wakeup event can be caused by the PCI Express WAKE# pin
14 being active or receipt of a PCI Express PME message at a root port. This bit is set
only when one of these events causes the system to transition from a non-S0
system power state to the S0 system power state. This bit is set independent of the
state of the PCIEXP_WAKE_DIS bit.
NOTE: This bit does not itself cause a wake event or prevent entry to a sleeping state.
Thus, if the bit is 1 and the system is put into a sleeping state, the system will
not automatically wake.
13:12 Reserved
Datasheet 527
LPC Interface Bridge Registers (D31:F0)
Bit Description
Power Button Override Status (PWRBTNOR_STS)—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set any time a Power Button Override occurs (that is, the power button is
pressed for at least 4 consecutive seconds), due to the corresponding bit in the
SMBus slave message, Intel ME Initiated Power Button Override, Intel ME Initiated
11 Host Reset with Power down or due to an internal thermal sensor catastrophic
condition. The power button override causes an unconditional transition to the S5
state. The BIOS or SCI handler clears this bit by writing a 1 to it. This bit is not
affected by hard resets using CF9h writes, and is not reset by RSMRST#. Thus, this
bit is preserved through power failures. If this bit is still asserted when the global
SCI_EN is set, an SCI will be generated.
RTC Status (RTC_STS)—R/WC. This bit is not affected by hard resets caused by a
CF9 write, but is reset by DPWROK.
10 0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RTC generates an alarm (assertion of the IRQ8# signal).
Additionally if the RTC_EN bit (PMBASE + 02h, bit 10) is set, the setting of the
RTC_STS bit will generate a wake event.
9 Reserved
Power Button Status (PWRBTN__STS)—R/WC. This bit is not affected by hard
resets caused by a CF9 write but is reset by DPWROK.
0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears
the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to
the S5 state with only PWRBTN# enabled as a wake event.
This bit can be cleared by software by writing a one to the bit position.
1 = This bit is set by hardware when the PWRBTN# signal is asserted Low, independent
of any other enable bit.
8
In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or
SMI# if SCI_EN is not set) will be generated.
In any sleeping state S1–S5, while PWRBTN_EN (PMBASE + 02h, bit 8) and
PWRBTN_STS are both set, a wake event is generated.
NOTE: If the PWRBTN_STS bit is cleared by software while the PWRBTN# signal is sell
asserted, this will not cause the PWRBN_STS bit to be set. The PWRBTN# signal
must go inactive and active again to set the PWRBTN_STS bit.
7:6 Reserved
Global Status (GBL _STS)—R/WC.
0 = The SCI handler should then clear this bit by writing a 1 to the bit location.
5 1 = Set when an SCI is generated due to BIOS wanting the attention of the SCI
handler. BIOS has a corresponding bit, BIOS_RLS, which will cause an SCI and set
this bit.
Bus Master Status (BM_STS)—R/WC. This bit will not cause a wake event, SCI or
SMI#.
4 0 = Software clears this bit by writing a 1 to it.
1 = Set by the PCH when a PCH-visible bus master requests access to memory or the
BMBUSY# signal is active.
3:1 Reserved
Timer Overflow Status (TMROF_STS)—R/WC.
0 = The SCI or SMI# handler clears this bit by writing a 1 to the bit location.
0 1 = This bit gets set any time bit 22 of the 24-bit timer goes high (bits are numbered
from 0 to 23). This will occur every 2.3435 seconds. When the TMROF_EN bit
(PMBASE + 02h, bit 0) is set, then the setting of the TMROF_STS bit will
additionally generate an SCI or SMI# (depending on the SCI_EN).
528 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.8.3.2 PM1_EN—Power Management 1 Enable Register
I/O Address: PMBASE + 02h Attribute: R/W
Default Value: 0000h Size: 16 bits
Lockable: No Usage: ACPI or Legacy
Power Well: Bits 0–7: Core,
Bits 8–9, 11–13, 15: Suspend,
Bit 14: DSW,
Bit 10: RTC
Bit Description
15 Reserved
PCI Express* Wake Disable(PCIEXPWAK_DIS)—R/W. Modification of this bit has
no impact on the value of the PCIEXP_WAKE_STS bit.
0 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register enabled to wake
14
the system.
1 = Inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register disabled from
waking the system.
13:11 Reserved
RTC Event Enable (RTC_EN)—R/W. This bit is in the RTC well to allow an RTC event
to wake after a power failure.
0 = No SCI (or SMI#) or wake event is generated then RTC_STS (PMBASE + 00h, bit
10
10) goes active.
1 = An SCI (or SMI#) or wake event will occur when this bit is set and the RTC_STS bit
goes active.
9 Reserved
Power Button Enable (PWRBTN_EN)—R/W. This bit is used to enable the setting of
the PWRBTN_STS bit to generate a power management event (SMI#, SCI).
PWRBTN_EN has no effect on the PWRBTN_STS bit (PMBASE + 00h, bit 8) being set by
8 the assertion of the power button. The Power Button is always enabled as a Wake
event.
0 = Disable.
1 = Enable.
7:6 Reserved
Global Enable (GBL_EN)—R/W. When both the GBL_EN and the GBL_STS bit
(PMBASE + 00h, bit 5) are set, an SCI is raised.
5
0 = Disable.
1 = Enable SCI on GBL_STS going active.
4:1 Reserved
Timer Overflow Interrupt Enable (TMROF_EN)—R/W. Works in conjunction with
the SCI_EN bit (PMBASE + 04h, bit 0) as described below:
TMROF_EN SCI_EN Effect when TMROF_STS is set
0 0 X No SMI# or SCI
1 0 SMI#
1 1 SCI
Datasheet 529
LPC Interface Bridge Registers (D31:F0)
12.8.3.3 PM1_CNT—Power Management 1 Control Register
I/O Address: PMBASE + 04h
Attribute: R/W, WO
Default Value: 00000000h Size: 32 bits
Lockable: No Usage: ACPI or Legacy
Power Well: Bits 0–9, 13-31: Core,
Bits 10–12: RTC
Bit Description
31:14 Reserved
Sleep Enable (SLP_EN)—WO. Setting this bit causes the system to sequence into
13
the Sleep state defined by the SLP_TYP field.
Sleep Type (SLP_TYP)—R/W. This 3-bit field defines the type of Sleep the system
should enter when the SLP_EN bit is set to 1. These bits are only reset by RTCRST#.
Code Master Interrupt
000b ON: Typically maps to S0 state.
001b Puts Processor Core in S1 state.
010b Reserved
12:10 011b Reserved
100b Reserved
101b Suspend-To-RAM. Assert SLP_S3#: Typically maps to S3 state.
Suspend-To-Disk. Assert SLP_S3#, and SLP_S4#: Typically maps to
110b
S4 state.
Soft Off. Assert SLP_S3#, SLP_S4#, and SLP_S5#: Typically maps to
111b
S5 state.
9:3 Reserved
Global Release (GBL_RLS)—WO.
0 = This bit always reads as 0.
2 1 = ACPI software writes a 1 to this bit to raise an event to the BIOS. BIOS software
has a corresponding enable and status bits to control its ability to receive ACPI
events.
Bus Master Reload (BM_RLD)—R/W. This bit is treated as a scratchpad bit. This
bit is reset to 0 by PLTRST#
0 = Bus master requests will not cause a break from the C3 state.
1 1 = Enables Bus Master requests (internal or external) to cause a break from the C3
state.
If software fails to set this bit before going to C3 state, the PCH will still return to a
snoopable state from C3 or C4 states due to bus master activity.
SCI Enable (SCI_EN)—R/W. Selects the SCI interrupt or the SMI# interrupt for
various events including the bits in the PM1_STS register (bit 10, 8, 0), and bits in
0 GPE0_STS.
0 = These events will generate an SMI#.
1 = These events will generate an SCI.
530 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.8.3.4 PM1_TMR—Power Management 1 Timer Register
I/O Address: PMBASE + 08h Attribute: RO
Default Value: 00000000h Size: 32 bits
Lockable: No Usage: ACPI
Power Well: Core
Bit Description
31:24 Reserved
Timer Value (TMR_VAL)—RO. Returns the running count of the PM timer. This
counter runs off a 3.579545 MHz clock (14.31818 MHz divided by 4). It is reset to 0
during a PCI reset, and then continues counting as long as the system is in the S0
state. After an S1 state, the counter will not be reset (it will continue counting from the
23:0 last value in S0 state.
Anytime bit 22 of the timer goes HIGH to LOW (bits referenced from 0 to 23), the
TMROF_STS bit (PMBASE + 00h, bit 0) is set. The High-to-Low transition will occur
every 2.3435 seconds. If the TMROF_EN bit (PMBASE + 02h, bit 0) is set, an SCI
interrupt is also generated.
12.8.3.5 GPE0_STS—General Purpose Event 0 Status Register
I/O Address: PMBASE + 20h Attribute: Bits 0:32,35 R/WC
Bits 33:34, 36:63 RO
Default Value: 0000000000000000h Size: 64-bit
Lockable: No Usage: ACPI
Power Well: Bits 0–34, 36-37, 56–63: Suspend,
Bit 35, 38: DSW
This register is symmetrical to the General Purpose Event 0 Enable Register. Unless
indicated otherwise below, if the corresponding _EN bit is set, then when the _STS bit
get set, the PCH will generate a Wake Event. Once back in an S0 state (or if already in
an S0 state when the event occurs), the PCH will also generate an SCI if the SCI_EN bit
is set, or an SMI# if the SCI_EN bit (PMBASE + 04h, bit 0) is not set. Bits 31:16 are
reset by a CF9h full reset; bits 63:32 and 15:0 are not. All bits (except bit 35) are reset
by RSMRST#. Bit 35 is reset by DPWROK.
Bit Description
63 GPI60_STS - R/WC. Refer to bit[56] in this register for description.
62 GPI57_STS - R/WC. Refer to bit[56] in this register for description.
61 GPI56_STS - R/WC. Refer to bit[56] in this register for description.
60 GPI43_STS - R/WC. Refer to bit[56] in this register for description.
59 GPI22_STS - R/WC. Refer to bit[56] in this register for description.
58 GPI21_STS - R/WC. Refer to bit[56] in this register for description.
57 GPI19_STS - R/WC. Refer to bit[56] in this register for description.
Datasheet 531
LPC Interface Bridge Registers (D31:F0)
Bit Description
GPI17_STS—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = These bits are set any time the corresponding GPIO is set up as an input and the
corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set).
If the corresponding enable bit is set in the GPE0_EN register, then when the
56
GPI[n]_STS bit is set:
• If the system is in an S1–S5 state, the event will also wake the system.
• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be
caused depending on the GPI_ROUT2 bits (D31:F0:BCh, bits 15:0) for the
corresponding GPI.
55-39 Reserved
Wake Alarm Device Timer Status (WADT_STS)—R/WC. This bit is set whenever any
38
of the wake alarm device timers signal a timer expiration.
37:36 Reserved
GPI27_STS—R/WC.
0 = Disable.
1 = Set by hardware and can be reset by writing a one to this bit position or a
resume well reset. This bit is set whenever GPIO27 is seen asserted low. GPIO27
is always monitored as an input for the purpose of setting this bit, regardless of
35
the actual GPIO configuration.
NOTE: GPI27 can be configured as wake input to allow wakes from Deep Sx but,
since the pin is shared, the PCH counts on this pin remaining asserted until
PLTRST# de-asserts or the PCH may misinterpret the pin assertion as a LAN
wake request.
34:32 Reserved
GPIn_STS—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = These bits are set any time the corresponding GPIO is set up as an input and the
corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set).
If the corresponding enable bit is set in the GPE0_EN register, then when the
GPI[n]_STS bit is set:
31:16 • If the system is in an S1–S5 state, the event will also wake the system.
• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be
caused depending on the GPI_ROUT bits (D31:F0:B8h, bits 31:30) for the
corresponding GPI.
NOTE: Mapping is as follows: bit 31 corresponds to GPI[15]... and bit 16 corresponds
to GPI[0].
15:14 Reserved
532 Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit Description
GPI17_STS—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = These bits are set any time the corresponding GPIO is set up as an input and the
corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set).
If the corresponding enable bit is set in the GPE0_EN register, then when the
56
GPI[n]_STS bit is set:
• If the system is in an S1–S5 state, the event will also wake the system.
• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be
caused depending on the GPI_ROUT2 bits (D31:F0:BCh, bits 15:0) for the
corresponding GPI.
55-39 Reserved
Wake Alarm Device Timer Status (WADT_STS)—R/WC. This bit is set whenever any
38
of the wake alarm device timers signal a timer expiration.
37:36 Reserved
GPI27_STS—R/WC.
0 = Disable.
1 = Set by hardware and can be reset by writing a one to this bit position or a
resume well reset. This bit is set whenever GPIO27 is seen asserted low. GPIO27
is always monitored as an input for the purpose of setting this bit, regardless of
35
the actual GPIO configuration.
NOTE: GPI27 can be configured as wake input to allow wakes from Deep Sx but,
since the pin is shared, the PCH counts on this pin remaining asserted until
PLTRST# de-asserts or the PCH may misinterpret the pin assertion as a LAN
wake request.
34:32 Reserved
GPIn_STS—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = These bits are set any time the corresponding GPIO is set up as an input and the
corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set).
If the corresponding enable bit is set in the GPE0_EN register, then when the
GPI[n]_STS bit is set:
31:16 • If the system is in an S1–S5 state, the event will also wake the system.
• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be
caused depending on the GPI_ROUT bits (D31:F0:B8h, bits 31:30) for the
corresponding GPI.
NOTE: Mapping is as follows: bit 31 corresponds to GPI[15]... and bit 16 corresponds
to GPI[0].
15:14 Reserved
Datasheet 533
LPC Interface Bridge Registers (D31:F0)
Bit Description
PME_B0_STS—R/WC. This bit will be set to 1 by the PCH when any internal device
with PCI Power Management capabilities on bus 0 asserts the equivalent of the PME#
signal. Additionally, if the PME_B0_EN bit and SCI_EN bits are set, and the system is
in an S0 state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI#
if SCI_EN is not set). If the PME_B0_EN bit is set, and the system is in an S1–S4
state (or S5 state due to SLP_TYP and SLP_EN), then the setting of the PME_B0_STS
bit will generate a wake event. If the system is in an S5 state due to power button
override, then the PME_B0_STS bit will not cause a wake event or SCI.
13
The default for this bit is 0. Writing a 1 to this bit position clears this bit.
The following are internal devices which can set this bit:
• Intel HD Audio
• Intel Management Engine “maskable” wake events
• Integrated LAN
• SATA
• EHCI
12 Reserved
PME_STS—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN
and SCI_EN bits are set, and the system is in an S0 state, then the setting of the
11 PME_STS bit will generate an SCI or SMI# (if SCI_EN is not set). If the PME_EN
bit is set, and the system is in an S1–S4 state (or S5 state due to setting
SLP_TYP and SLP_EN), then the setting of the PME_STS bit will generate a wake
event. If the system is in an S5 state due to power button override or a power
failure, then PME_STS will not cause a wake event or SCI.
10
(Desktop Reserved
Only)
10 BATLOW_STS—R/WC. (Mobile Only) Software clears this bit by writing a 1 to it.
(Mobile 0 = BATLOW# Not asserted
Only) 1 = Set by hardware when the BATLOW# signal is asserted.
PCI_EXP_STS—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware to indicate that:
— The PME event message was received on one or more of the PCI Express* ports
— An Assert PMEGPE message received from the processor using DMI
NOTES:
1. The PCI WAKE# pin has no impact on this bit.
2. If the PCI_EXP_STS bit went active due to an Assert PMEGPE message, then a
9 Deassert PMEGPE message must be received prior to the software write in
order for the bit to be cleared.
3. If the bit is not cleared and the corresponding PCI_EXP_EN bit is set, the
level-triggered SCI will remain active.
4. A race condition exists where the PCI Express device sends another PME
message because the PCI Express device was not serviced within the time
when it must resend the message. This may result in a spurious interrupt,
and this is comprehended and approved by the PCI Express* Specification,
Revision 1.0a. The window for this race condition is approximately 95–
105 milliseconds.
534 Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit Description
RI_STS—R/WC.
8 0 = Software clears this bit by writing a 1 to it.
1 = Set by hardware when the RI# input signal goes active.
SMBus Wake Status (SMB_WAK_STS)—R/WC. Software clears this bit by writing
a 1 to it.
0 = Wake event not caused by the PCH’s SMBus logic.
1 = Set by hardware to indicate that the wake event was caused by the PCH’s SMBus
logic. The SMI handler should then clear this bit.
NOTES:
7 1. The SMBus controller will independently cause an SMI# so this bit does not need
to do so (unlike the other bits in this register).
2. This bit is set by the SMBus slave command 01h (Wake/SMI#) even when the
system is in the S0 state. Therefore, to avoid an instant wake on subsequent
transitions to sleep states, software must clear this bit after each reception of the
Wake/SMI# command or just prior to entering the sleep state.
3. The SMBALERT_STS bit (SMB_BASE+00h:Bit 5) should be cleared by software
before the SMB_WAK_STS bit is cleared.
TCOSCI_STS—R/WC. Software clears this bit by writing a 1 to it.
6 0 = TOC logic or thermal sensor logic did Not cause SCI.
1 = Set by hardware when the TCO logic or thermal sensor logic causes an SCI.
5:3 Reserved
SWGPE_STS—R/WC.
2
The SWGPE_CTRL bit (bit 1 of GPE_CTRL reg) acts as a level input to this bit.
HOT_PLUG_STS—R/WC.
0 = This bit is cleared by writing a 1 to this bit position.
1
1 = When a PCI Express* Hot-Plug event occurs. This will cause an SCI if the
HOT_PLUG_EN and SCI_EN bits are set.
0 Reserved
Datasheet 535
LPC Interface Bridge Registers (D31:F0)
12.8.3.6 GPE0_EN—General Purpose Event 0 Enables Register
I/O Address: PMBASE + 28h Attribute: R/W
Default Value: 0000000000000000h Size: 64-bit
Lockable: No Usage: ACPI
Power Well: Bits 0–7, 9, 12, 14–34, 36–63 Suspend,
Bits 8, 10–11, 13, 35 RTC
This register is symmetrical to the General Purpose Event 0 Status Register.
Bit Description
63 GPI[60]_EN - R/W. Refer to bit 56 for description.
62 GPI[57]_EN - R/W. Refer to bit 56 for description.
61 GPI[56]_EN - R/W. Refer to bit 56 for description.
60 GPI[43]_EN - R/W. Refer to bit 56 for description.
59 GPI[22]_EN - R/W. Refer to bit 56 for description.
58 GPI[21]_EN - R/W. Refer to bit 56 for description.
57 GPI[19]_EN - R/W. Refer to bit 56 for description.
GPI[17]_EN - R/W. This bit enables the corresponding GPI[n]_STS bits being set to
56
cause an SCI and/or wake event.
55:39 Reserved
WADT_EN - R/W. Used to enable the setting of the WADT_STS bit to generate wake/
38
SMI#/SCI.
37-36 Reserved
GPI27_EN—R/W.
0 = Disable.
1 = Enable the setting of the GPI27_STS bit to generate a wake event/SCI/SMI#.
GPIO27 is a valid host wake event from Deep Sx. The wake enable configuration
persists after a G3 state.
NOTE: Host wake events from the PHY through GPIO27 cannot be disabled by
35 clearing this bit.
NOTE: In the Deep S4/S5 state, GPIO27 has no GPIO functionality other than wake
enable capability if this corresponding bit is set.
NOTE: GPI27 can be configured as wake input to allow wakes from Deep Sx but,
since the pin is shared, the PCH counts on this pin remaining asserted until
PLTRST# de-asserts or the PCH may misinterpret the pin assertion as a LAN
wake request.
34:32 Reserved
GPIn_EN—R/W. These bits enable the corresponding GPI[n]_STS bits being set to
cause a SCI, and/or wake event. These bits are cleared by RSMRST#.
31:16
NOTE: Mapping is as follows: bit 31 corresponds to GPI15... and bit 16 corresponds
to GPI0.
15:14 Reserved
PME_B0_EN—R/W.
0 = Disable
13
NOTE: Enables the setting of the PME_B0_STS bit to generate a wake event and/or
an SCI or SMI#.
12 Reserved
536 Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit Description
PME_EN—R/W.
0 = Disable.
11 1 = Enables the setting of the PME_STS to generate a wake event and/or an SCI.
PME# can be a wake event from the S1–S4 state or from S5 (if entered using
SLP_EN, but not power button override).
10
(Desktop Reserved
Only)
BATLOW_EN—R/W. (Mobile Only)
10 0 = Disable.
(Mobile 1 = Enables the BATLOW# signal to cause an SMI# or SCI (depending on the
Only) SCI_EN bit) when it goes low. This bit does not prevent the BATLOW# signal
from inhibiting the wake event.
PCI_EXP_EN—R/W.
0 = Disable SCI generation upon PCI_EXP_STS bit being set.
9 1 = Enables PCH to cause an SCI when PCI_EXP_STS bit is set. This is used to allow
the PCI Express* ports, including the link to the processor, to cause an SCI due
to wake/PME events.
RI_EN—R/W. The value of this bit will be maintained through a G3 state and is not
affected by a hard reset caused by a CF9h write.
8
0 = Disable.
1 = Enables the setting of the RI_STS to generate a wake event.
7 Reserved
TCOSCI_EN—R/W.
6 0 = Disable.
1 = Enables the setting of the TCOSCI_STS to generate an SCI.
5:3 Reserved
SWGPE_EN—R/W. This bit allows software to control the assertion of SWGPE_STS
bit. This bit This bit, when set to 1, enables the SW GPE function. If SWGPE_CTRL is
written to a 1, hardware will set SWGPE_STS (acts as a level input)
2
If SWGPE_STS, SWGPE_EN, and SCI_EN are all 1s, an SCI will be generated
If SWGPE_STS = 1, SWGPE_EN = 1, SCI_EN = 0, and GBL_SMI_EN = 1 then an
SMI# will be generated
HOT_PLUG_EN—R/W.
0 = Disables SCI generation upon the HOT_PLUG_STS bit being set.
1
1 = Enables the PCH to cause an SCI when the HOT_PLUG_STS bit is set. This is
used to allow the PCI Express* ports to cause an SCI due to Hot-Plug events.
0 Reserved
Datasheet 537
LPC Interface Bridge Registers (D31:F0)
12.8.3.7 SMI_EN—SMI Control and Enable Register
I/O Address: PMBASE + 30h Attribute: R/W, R/WO, WO
Default Value: 00000002h Size: 32 bit
Lockable: No Usage: ACPI or Legacy
Power Well: Core
Note: This register is symmetrical to the SMI status register.
Bit Description
xHCI SMI Enable (xHCI _SMI_EN)—R/W.
31 0 = Disable
1 = Enables xHCI to generate an SMI#
ME SMI Enable (ME _SMI_EN)—R/W.
30 0 = Disable
1 = Enables ME to generate an SMI#
29:28 Reserved
GPIO_UNLOCK_SMI_EN—R/WO. Setting this bit will cause the PCH to generate an
27 SMI# when the GPIO_UNLOCK_SMI_STS bit is set in the SMI_STS register.
Once written to 1, this bit can only be cleared by PLTRST#.
26:19 Reserved
INTEL_USB2_EN—R/W.
18 0 = Disable
1 = Enables Intel-Specific EHCI SMI logic to cause SMI#.
LEGACY_USB2_EN—R/W.
17 0 = Disable
1 = Enables legacy EHCI logic to cause SMI#.
16:15 Reserved
PERIODIC_EN—R/W.
14 0 = Disable.
1 = Enables the PCH to generate an SMI# when the PERIODIC_STS bit (PMBASE +
34h, bit 14) is set in the SMI_STS register (PMBASE + 34h).
TCO_EN—R/W.
0 = Disables TCO logic generating an SMI#. If the NMI2SMI_EN bit is set, SMIs that
are caused by re-routed NMIs will not be gated by the TCO_EN bit. Even if the
13 TCO_EN bit is 0, NMIs will still be routed to cause SMIs.
1 = Enables the TCO logic to generate SMI#.
NOTE: This bit cannot be written once the TCO_LOCK bit is set.
12 Reserved
MCSMI_EN Microcontroller SMI Enable (MCSMI_EN)—R/W.
0 = Disable.
11 1 = Enables PCH to trap accesses to the microcontroller range (62h or 66h) and
generate an SMI#. The “trapped’ cycles will be claimed by the PCH on PCI, but not
forwarded to LPC.
10:8 Reserved
538 Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit Description
BIOS Release (BIOS_RLS)—WO.
0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect.
1 = Enables the generation of an SCI interrupt for ACPI software when a one is written
7 to this bit position by BIOS software.
NOTE: GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set.
Software must take great care not to set the BIOS_RLS bit (which causes
GBL_STS to be set) if the SCI handler is not in place.
Software SMI# Timer Enable (SWSMI_TMR_EN)—R/W.
0 = Disable. Clearing the SWSMI_TMR_EN bit before the timer expires will reset the
timer and the SMI# will not be generated.
6
1 = Starts Software SMI# Timer. When the SWSMI timer expires (the timeout period
depends upon the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set and an
SMI# is generated. SWSMI_TMR_EN stays set until cleared by software.
APMC_EN—R/W.
5 0 = Disable. Writes to the APM_CNT register will not cause an SMI#.
1 = Enables writes to the APM_CNT register to cause an SMI#.
SLP_SMI_EN—R/W.
0 = Disables the generation of SMI# on SLP_EN. This bit must be 0 before the
software attempts to transition the system into a sleep state by writing a 1 to the
4 SLP_EN bit.
1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an SMI#,
and the system will not transition to the sleep state based on that write to the
SLP_EN bit.
LEGACY_USB_EN—R/W.
3 0 = Disable.
1 = Enables legacy USB circuit to cause SMI#.
BIOS_EN—R/W.
0 = Disable.
1 = Enables the generation of SMI# when ACPI software writes a 1 to the GBL_RLS bit
2
(D31:F0:PMBase + 04h:bit 2). If the BIOS_STS bit (D31:F0:PMBase + 34h:bit 2),
which gets set when software writes 1 to GBL_RLS bit, is already a 1 at the time
that BIOS_EN becomes 1, an SMI# will be generated when BIOS_EN gets set.
End of SMI (EOS)—R/W (special). This bit controls the arbitration of the SMI signal to
the processor. This bit must be set for the PCH to assert SMI# low to the processor
after SMI# has been asserted previously.
0 = Once the PCH asserts SMI# low, the EOS bit is automatically cleared.
1 = When this bit is set to 1, SMI# signal will be de-asserted for 4 PCI clocks before its
1 assertion. In the SMI handler, the processor should clear all pending SMIs (by
servicing them and then clearing their respective status bits), set the EOS bit, and
exit SMM. This will allow the SMI arbiter to re-assert SMI upon detection of an SMI
event and the setting of a SMI status bit.
NOTE: The PCH is able to generate 1st SMI after reset even though EOS bit is not set.
Subsequent SMI require EOS bit is set.
GBL_SMI_EN—R/W.
0 = No SMI# will be generated by PCH. This bit is reset by a PCI reset event.
0 1 = Enables the generation of SMI# in the system upon any enabled SMI event.
NOTE: When the SMI_LOCK bit is set, this bit cannot be changed.
Datasheet 539
LPC Interface Bridge Registers (D31:F0)
12.8.3.8 SMI_STS—SMI Status Register
I/O Address: PMBASE + 34h Attribute: RO, R/WC
Default Value: 00000000h Size: 32 bits
Lockable: No Usage: ACPI or Legacy
Power Well: Core
Note: If the corresponding _EN bit is set when the _STS bit is set, the PCH will cause an SMI#
(except bits 8–10 and 12, which do not need enable bits since they are logic ORs of
other registers that have enable bits). The PCH uses the same GPE0_EN register (I/O
address: PMBase+2Ch) to enable/disable both SMI and ACPI SCI general purpose input
events. ACPI OS assumes that it owns the entire GPE0_EN register per the ACPI
specification. Problems arise when some of the general-purpose inputs are enabled as
SMI by BIOS, and some of the general purpose inputs are enabled for SCI. In this case
ACPI OS turns off the enabled bit for any GPIx input signals that are not indicated as
SCI general-purpose events at boot, and exit from sleeping states. BIOS should define
a dummy control method which prevents the ACPI OS from clearing the SMI GPE0_EN
bits.
Bit Description
31:28 Reserved
GPIO_UNLOCK_SMI_STS—R/WC. This bit will be set if the GPIO registers lockdown
27
logic is requesting an SMI#. Writing a 1 to this bit position clears this bit to 0.
SPI_STS—RO. This bit will be set if the SPI logic is generating an SMI#. This bit is read
26 only because the sticky status and enable bits associated with this function are located
in the SPI registers.
25:22 Reserved
MONITOR_STS—RO. This bit will be set if the Trap/SMI logic has caused the SMI. This
will occur when the processor or a bus master accesses an assigned register (or a
21
sequence of accesses). See Section 10.1.20 through Section 10.1.36 for details on the
specific cause of the SMI.
PCI_EXP_SMI_STS—RO. PCI Express* SMI event occurred. This could be due to a
20
PCI Express* PME event or Hot-Plug event.
19 Reserved
INTEL_USB2_STS—RO. This non-sticky read-only bit is a logical OR of each of the
SMI status bits in the Intel-Specific EHCI SMI Status Register ANDed with the
18 corresponding enable bits. This bit will not be active if the enable bits are not set.
Writes to this bit will have no effect.
All integrated EHCIs are represented with this bit.
LEGACY_USB2_STS—RO. This non-sticky read-only bit is a logical OR of each of the
SMI status bits in the EHCI Legacy Support Register ANDed with the corresponding
17 enable bits. This bit will not be active if the enable bits are not set. Writes to this bit will
have no effect.
All integrated ECHIs are represented with this bit.
540 Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit Description
SMBus SMI Status (SMBUS_SMI_STS)—R/WC. Software clears this bit by writing a
1 to it.
0 = This bit is set from the 64 kHz clock domain used by the SMBus. Software must
wait at least 15.63 s after the initial assertion of this bit before clearing it.
1 = Indicates that the SMI# was caused by:
16 1. The SMBus Slave receiving a message that an SMI# should be caused, or
2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the
SMBALERT_DIS bit is cleared, or
3. The SMBus Slave receiving a Host Notify message and the
HOST_NOTIFY_INTREN and the SMB_SMI_EN bits are set, or
4. The PCH detecting the SMLINK_SLAVE_SMI command while in the S0 state.
SERIRQ_SMI_STS—RO.
0 = SMI# was not caused by the SERIRQ decoder.
15
1 = Indicates that the SMI# was caused by the SERIRQ decoder.
NOTE: This is not a sticky bit
PERIODIC_STS—R/WC. Software clears this bit by writing a 1 to it.
14 0 = Software clears this bit by writing a 1 to it.
1 = This bit is set at the rate determined by the PER_SMI_SEL bits. If the
PERIODIC_EN bit (PMBASE + 30h, bit 14) is also set, the PCH generates an SMI#.
TCO_STS—R/WC. Software clears this bit by writing a 1 to it.
13 0 = SMI# not caused by TCO logic.
1 = Indicates the SMI# was caused by the TCO logic. This is not a wake event.
Device Monitor Status (DEVMON_STS)—RO.
0 = SMI# not caused by Device Monitor.
12
1 = Set if bit 0 of the DEVACT_STS register (PMBASE + 44h) is set. The bit is not sticky,
so writes to this bit will have no effect.
Microcontroller SMI# Status (MCSMI_STS)—R/WC. Software clears this bit by
writing a 1 to it.
0 = Indicates that there has been no access to the power management microcontroller
range (62h or 66h).
11 1 = Set if there has been an access to the power management microcontroller range
(62h or 66h) and the Microcontroller Decode Enable #1 bit in the LPC Bridge I/O
Enables configuration register is 1 (D31:F0:Offset 82h:bit 11). This implementation
assumes that the Microcontroller is on LPC. If this bit is set, and the MCSMI_EN bit
is also set, the PCH will generate an SMI#.
GPE1_STS—RO. This bit is a logical OR of the bits in the ALT_GPI_SMI_STS and the
ALT_GPI_SMI_STS2 registers that are also set up to cause an SMI# (as indicated by
the GPI_ROUT and GPI_ROUT2 registers) and have the corresponding bit set in the
10 ALT_GPI_SMI_EN and ALT_GPI_SMI_EN2 registers. Bits that are not routed to cause an
SMI# will have no effect on this bit.
0 = SMI# was not generated by a GPI assertion.
1 = SMI# was generated by a GPI assertion.
GPE0_STS—RO. This bit is a logical OR of the bits 35, 13, 11, 10, 8 and 2 in the
GPE0_STS register (PMBASE + 28h) that also have the corresponding bit set in the
9 GPE0_EN register (PMBASE + 2Ch).
0 = SMI# was not generated by a GPE0 event.
1 = SMI# was generated by a GPE0 event.
PM1_STS_REG—RO. This is an ORs of the bits in the ACPI PM1 Status Register (offset
PMBASE+00h) that can cause an SMI#.
8
0 = SMI# was not generated by a PM1_STS event.
1 = SMI# was generated by a PM1_STS event.
Datasheet 541
LPC Interface Bridge Registers (D31:F0)
Bit Description
7 Reserved
SWSMI_TMR_STS—R/WC. Software clears this bit by writing a 1 to it.
6 0 = Software SMI# Timer has Not expired.
1 = Set by the hardware when the Software SMI# Timer expires.
APM_STS—R/WC. Software clears this bit by writing a 1 to it.
0 = No SMI# generated by write access to APM Control register with APMCH_EN bit set.
5
1 = SMI# was generated by a write access to the APM Control register with the
APMC_EN bit set.
SLP_SMI_STS—R/WC. Software clears this bit by writing a 1 to the bit location.
0 = No SMI# caused by write of 1 to SLP_EN bit when SLP_SMI_EN bit is also set.
4
1 = Indicates an SMI# was caused by a write of 1 to SLP_EN bit when SLP_SMI_EN bit
is also set.
LEGACY_USB_STS—RO. This bit is a logical OR of each of the SMI status bits in the
USB Legacy Keyboard/Mouse Control Registers ANDed with the corresponding enable
3 bits. This bit will not be active if the enable bits are not set.
0 = SMI# was not generated by USB Legacy event.
1 = SMI# was generated by USB Legacy event.
BIOS_STS—R/WC.
0 = No SMI# generated due to ACPI software requesting attention.
2 1 = This bit gets set by hardware when a 1 is written by software to the GBL_RLS bit
(D31:F0:PMBase + 04h:bit 2). When both the BIOS_EN bit (D31:F0:PMBase +
30h:bit 2) and the BIOS_STS bit are set, an SMI# will be generated. The
BIOS_STS bit is cleared when software writes a 1 to its bit position.
1:0 Reserved
12.8.3.9 ALT_GPI_SMI_EN—Alternate GPI SMI Enable Register
I/O Address: PMBASE +38h Attribute: R/W
Default Value: 0000h Size: 16 bits
Lockable: No Usage: ACPI or Legacy
Power Well: Suspend
Bit Description
Alternate GPI SMI Enable—R/W. These bits are used to enable the corresponding
GPIO to cause an SMI#. For these bits to have any effect, the following must be true.
• The corresponding bit in the ALT_GPI_SMI_EN register is set.
15:0 • The corresponding GPI must be routed in the GPI_ROUT register to cause an SMI.
• The corresponding GPIO must be implemented.
NOTE: Mapping is as follows: bit 15 corresponds to GPI15... bit 0 corresponds to GPI0.
542 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.8.3.10 ALT_GPI_SMI_STS—Alternate GPI SMI Status Register
I/O Address: PMBASE +3Ah Attribute: R/WC
Default Value: 0000h Size: 16 bits
Lockable: No Usage: ACPI or Legacy
Power Well: Suspend
Bit Description
Alternate GPI SMI Status—R/WC. These bits report the status of the corresponding
GPIOs.
0 = Inactive. Software clears this bit by writing a 1 to it.
1 = Active
These bits are sticky. If the following conditions are true, then an SMI# will be
generated and the GPE0_STS bit set:
15:0 • The corresponding bit in the ALT_GPI_SMI_EN register (PMBASE + 38h) is set
• The corresponding GPIO must be routed in the GPI_ROUT register to cause an SMI.
• The corresponding GPIO must be implemented.
NOTE: All bits are in the resume well. Default for these bits is dependent on the state
of the GPIO pins.
NOTE: Mapping is as follows: bit 15 corresponds to GPIO15... bit 0 corresponds to
GPIO0.
Datasheet 543
LPC Interface Bridge Registers (D31:F0)
12.8.3.11 GPE_CNTL—General Purpose Control Register
I/O Address: PMBASE +42h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Usage: ACPI or Legacy
Power Well: Bits 0–1, 3–7: Suspend
Bit 2: RTC
Bit Description
7:2 Reserved
SWGPE_CTRL—R/W. This bit allows software to control the assertion of SWGPE_STS
bit. This bit is used by hardware as the level input signal for the SWGPE_STS bit in the
GPE0_STS register. When SWGPE_CTRL is 1, SWGPE_STS will be set to 1, and writes to
SWGPE_STS with a value of 1 to clear SWGPE_STS will result in SWGPE_STS being set
back to 1 by hardware. When SWGPE_CTRL is 0, writes to SWGPE_STS with a value of
1
1 will clear SWGPE_STS to 0.
In addition to being cleared by RSMRST# assertion, the PCH also clears this bit due to a
Power Button Override event, Intel ME Initiated Power Button Override, Intel ME
Initiated Host Reset with Power down, SMBus unconditional power down, processor
thermal trip event, or due to an internal thermal sensor catastrophic condition.
0 Reserved
12.8.3.12 DEVACT_STS—Device Activity Status Register
I/O Address: PMBASE +44h Attribute: R/WC
Default Value: 0000h Size: 16 bits
Lockable: No Usage: Legacy Only
Power Well: Core
Each bit indicates if an access has occurred to the corresponding device’s trap range, or
for bits 6:9 if the corresponding PCI interrupt is active. This register is used in
conjunction with the Periodic SMI# timer to detect any system activity for legacy power
management. The periodic SMI# timer indicates if it is the right time to read the
DEVACT_STS register (PMBASE + 44h).
Note: Software clears bits that are set in this register by writing a 1 to the bit position.
Bit Description
15:13 Reserved
KBC_ACT_STS—R/WC. KBC (60/64h).
12 0 = Indicates that there has been no access to this device I/O range.
1 = This device I/O range has been accessed. Clear this bit by writing a 1 to the bit
location.
11:10 Reserved
PIRQDH_ACT_STS—R/WC. PIRQ[D or H].
0 = The corresponding PCI interrupts have not been active.
9
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
PIRQCG_ACT_STS—R/WC. PIRQ[C or G].
0 = The corresponding PCI interrupts have not been active.
8
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
544 Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit Description
PIRQBF_ACT_STS—R/WC. PIRQ[B or F].
0 = The corresponding PCI interrupts have not been active.
7
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
PIRQAE_ACT_STS—R/WC. PIRQ[A or E].
6 0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been active. Clear this bit by
writing a 1 to the bit location.
5:0 Reserved
12.8.3.13 PM2_CNT—Power Management 2 Control Register
I/O Address: PMBASE + 50h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Usage: ACPI
Power Well: Core
Bit Description
7:1 Reserved
Arbiter Disable (ARB_DIS)—R/W This bit is a scratchpad bit for legacy software
0 compatibility.
12.8.3.14 ALT_GPI_SMI_EN2 - Alternate GPI SMI Enable 2 Register
I/O Address: PMBASE + 5Ch Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Lockable: No Usage: ACPI
Power Well: Suspend
Bit Description
15:8 Reserved
Alternate GPI[60] SMI Enable (ALT_GPI60_SMI_EN)—R/W. Refer to bit [0] in this
7
register for description.
Alternate GPI[57] SMI Enable (ALT_GPI57_SMI_EN)—R/W. Refer to bit [0] in this
6
register for description.
Alternate GPI[56] SMI Enable (ALT_GPI56_SMI_EN)—R/W. Refer to bit [0] in this
5
register for description.
Alternate GPI[43] SMI Enable (ALT_GPI43_SMI_EN)—R/W. Refer to bit [0] in this
4
register for description.
Alternate GPI[22] SMI Enable (ALT_GPI22_SMI_EN)—R/W. Refer to bit [0] in this
3
register for description.
Datasheet 545
LPC Interface Bridge Registers (D31:F0)
Bit Description
Alternate GPI[21] SMI Enable (ALT_GPI21_SMI_EN)—R/W. Refer to bit [0] in this
2
register for description.
Alternate GPI[19] SMI Enable (ALT_GPI19_SMI_EN)—R/W. Refer to bit [0] in this
1
register for description.
Alternate GPI[17] SMI Enable (ALT_GPI17_SMI_EN)—R/W. These bits are used
to enable the corresponding GPIO to cause an SMI#. For these bits to have any effect,
the following must be true.
0 • The corresponding bit in the ALT_GPI_SMI_STS2 register is set.
• The corresponding GPI must be routed in the GPI_ROUT2 register to cause an SMI.
• The corresponding GPIO must be implemented.
12.8.3.15 ALT_GPI_SMI_STS2—Alternate GPI SMI Status 2 Register
I/O Address: PMBASE + 5E-5Fh Attribute: R/W, RO
Default Value: 00h Size: 16 bits
Lockable: No Usage: ACPI
Power Well: Suspend
Bit Description
15:8 Reserved
Alternate GPI[60] SMI Status (ALT_GPI60_SMI_STS) - R/W. Refer to bit[0] in
7
this register for description.
Alternate GPI[57] SMI Status (ALT_GPI57_SMI_STS) - R/W. Refer to bit[0] in
6
this register for description.
Alternate GPI[56] SMI Status (ALT_GPI56_SMI_STS) - R/W. Refer to bit[0] in
5
this register for description.
Alternate GPI[43] SMI Status (ALT_GPI43_SMI_STS) - R/W. Refer to bit[0] in
4
this register for description.
Alternate GPI[22] SMI Status (ALT_GPI22_SMI_STS) - R/W. Refer to bit[0] in
3
this register for description.
Alternate GPI[21] SMI Status (ALT_GPI21_SMI_STS) - R/W. Refer to bit[0] in
2
this register for description.
Alternate GPI[19] SMI Status (ALT_GPI19_SMI_STS) - R/W. Refer to bit[0] in
1
this register for description.
Alternate GPI[17] SMI Status (ALT_GPI17_SMI_STS) - R/W. These bits report
the status of the corresponding GPIOs.
0 = Inactive. Software clears this bit by writing a 1 to it.
1 = Active
These bits are sticky. If the following conditions are true, then an SMI# will be
0 generated and the GPE0_STS bit set:
• The corresponding bit in the ALT_GPI_SMI_EN2 register (PMBASE + 5Ch) is set
• The corresponding GPIO must be routed in the GPI_ROUT2 register to cause an
SMI.
• The corresponding GPIO must be implemented.
546 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.9 System Management TCO Registers
The TCO logic is accessed using registers mapped to the PCI configuration space
(D31:F0) and the system I/O space. For TCO PCI Configuration registers, see LPC
D31:F0 PCI Configuration registers.
TCO Register I/O Map
The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE value, which
is, PMBASE + 60h in the PCI config space. The following table shows the mapping of
the registers within that 32-byte range. Each register is described in the following
sections.
Table 12-12. TCO I/O Register Address Map
TCOBASE
Mnemonic Register Name Default Attribute
+ Offset
TCO Timer Reload and Current
00h–01h TCO_RLD 0000h R/W
Value
02h TCO_DAT_IN TCO Data In 00h R/W
03h TCO_DAT_OUT TCO Data Out 00h R/W
04h–05h TCO1_STS TCO1 Status 0000h R/WC, RO
06h–07h TCO2_STS TCO2 Status 0000h R/WC
R/W,
08h–09h TCO1_CNT TCO1 Control 0000h
R/WLO, R/WC
0Ah–0Bh TCO2_CNT TCO2 Control 0008h R/W
TCO_MESSAGE1,
0Ch–0Dh TCO Message 1 and 2 00h R/W
TCO_MESSAGE2
0Eh TCO_WDCNT TCO Watchdog Control 00h R/W
0Fh — Reserved — —
10h SW_IRQ_GEN Software IRQ Generation 03h R/W
11h — Reserved — —
12h–13h TCO_TMR TCO Timer Initial Value 0004h R/W
14h–1Fh — Reserved — —
12.9.1 TCO_RLD—TCO Timer Reload and Current Value Register
I/O Address: TCOBASE +00h Attribute: R/W
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Core
Bit Description
15:10 Reserved
TCO Timer Value—R/W. Reading this register will return the current count of the TCO
9:0
timer. Writing any value to this register will reload the timer to prevent the timeout.
Datasheet 547
LPC Interface Bridge Registers (D31:F0)
12.9.2 TCO_DAT_IN—TCO Data In Register
I/O Address: TCOBASE +02h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Core
Bit Description
TCO Data In Value—R/W. This data register field is used for passing commands from
7:0 the OS to the SMI handler. Writes to this register will cause an SMI and set the
SW_TCO_SMI bit in the TCO1_STS register (D31:F0:04h).
12.9.3 TCO_DAT_OUT—TCO Data Out Register
I/O Address: TCOBASE +03h Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Core
Bit Description
TCO Data Out Value—R/W. This data register field is used for passing commands from
the SMI handler to the OS. Writes to this register will set the TCO_INT_STS bit in the
7:0
TCO1_STS register. It will also cause an interrupt, as selected by the TCO_INT_SEL
bits.
12.9.4 TCO1_STS—TCO1 Status Register
I/O Address: TCOBASE +04h Attribute: R/WC, RO
Default Value: 2000h Size: 16 bits
Lockable: No Power Well: Core
(Except bit 7, in RTC)
Bit Description
15:14 Reserved
TCO_SLVSEL (TCO Slave Select)—RO. This register bit is Read Only by Host and
13 indicates the value of TCO Slave Select Soft Strap. Refer to the PCH Soft Straps section
of the SPI Chapter for details.
DMISERR_STS—R/WC.
0 = Software clears this bit by writing a 1 to it.
12 1 = PCH received a DMI special cycle message using DMI indicating that it wants to
cause an SERR#. The software must read the processor to determine the reason
for the SERR#.
11 Reserved
DMISMI_STS—R/WC.
0 = Software clears this bit by writing a 1 to it.
10 1 = PCH received a DMI special cycle message using DMI indicating that it wants to
cause an SMI. The software must read the processor to determine the reason for
the SMI.
DMISCI_STS—R/WC.
0 = Software clears this bit by writing a 1 to it.
9 1 = PCH received a DMI special cycle message using DMI indicating that it wants to
cause an SCI. The software must read the processor to determine the reason for
the SCI.
548 Datasheet
LPC Interface Bridge Registers (D31:F0)
Bit Description
BIOSWR_STS—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = PCH sets this bit and generates and SMI# to indicate an invalid attempt to write to
8 the BIOS. This occurs when either:
a) The BIOSWP bit is changed from 0 to 1 and the BLD bit is also set, or
b) any write is attempted to the BIOS and the BIOSWP bit is also set.
NOTE: On write cycles attempted to the 4 MB lower alias to the BIOS space, the
BIOSWR_STS will not be set.
NEWCENTURY_STS—R/WC. This bit is in the RTC well.
0 = Cleared by writing a 1 to the bit position or by RTCRST# going active.
1 = This bit is set when the Year byte (RTC I/O space, index offset 09h) rolls over from
99 to 00. Setting this bit will cause an SMI# (but not a wake event).
NOTE: The NEWCENTURY_STS bit is not valid when the RTC battery is first installed (or
when RTC power has not been maintained). Software can determine if RTC
7 power has not been maintained by checking the RTC_PWR_STS bit
(D31:F0:A4h, bit 2), or by other means (such as a checksum on RTC RAM). If
RTC power is determined to have not been maintained, BIOS should set the
time to a valid value and then clear the NEWCENTURY_STS bit.
The NEWCENTURY_STS bit may take up to 3 RTC clocks for the bit to be cleared after a
1 is written to the bit to clear it. After writing a 1 to this bit, software should not exit the
SMI handler until verifying that the bit has actually been cleared. This will ensure that
the SMI is not re-entered.
6:4 Reserved
TIMEOUT—R/WC.
3 0 = Software clears this bit by writing a 1 to it.
1 = Set by PCH to indicate that the SMI was caused by the TCO timer reaching 0.
TCO_INT_STS—R/WC.
0 = Software clears this bit by writing a 1 to it.
2
1 = SMI handler caused the interrupt by writing to the TCO_DAT_OUT register
(TCOBASE + 03h).
SW_TCO_SMI—R/WC.
1 0 = Software clears this bit by writing a 1 to it.
1 = Software caused an SMI# by writing to the TCO_DAT_IN register (TCOBASE +
02h).
NMI2SMI_STS—RO.
0 = Cleared by clearing the associated NMI status bit.
0
1 = Set by the PCH when an SMI# occurs because an event occurred that would
otherwise have caused an NMI (because NMI2SMI_EN is set).
Datasheet 549
LPC Interface Bridge Registers (D31:F0)
12.9.5 TCO2_STS—TCO2 Status Register
I/O Address: TCOBASE +06h Attribute: R/WC
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Resume
(Except Bit 0, in RTC)
Bit Description
15:5 Reserved
SMLink Slave SMI Status (SMLINK_SLV_SMI_STS)—R/WC. Allow the software to
go directly into a pre-determined sleep state. This avoids race conditions. Software
clears this bit by writing a 1 to it.
4 0 = The bit is reset by RSMRST#, but not due to the PCI Reset associated with exit
from S3–S5 states.
1 = PCH sets this bit to 1 when it receives the SMI message on the SMLink Slave
Interface.
3 Reserved
BOOT_STS—R/WC.
0 = Cleared by PCH based on RSMRST# or by software writing a 1 to this bit. Software
should first clear the SECOND_TO_STS bit before writing a 1 to clear the
BOOT_STS bit.
1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not
2 fetched the first instruction.
If rebooting due to a second TCO timer timeout, and if the BOOT_STS bit is set, the
PCH will reboot using the ‘safe’ multiplier (1111). This allows the system to recover
from a processor frequency multiplier that is too high, and allows the BIOS to check the
BOOT_STS bit at boot. If the bit is set and the frequency multiplier is 1111, then the
BIOS knows that the processor has been programmed to an invalid multiplier.
SECOND_TO_STS—R/WC.
0 = Software clears this bit by writing a 1 to it, or by a RSMRST#.
1 = PCH sets this bit to 1 to indicate that the TIMEOUT bit had been (or is currently) set
1
and a second timeout occurred before the TCO_RLD register was written. If this bit
is set and the NO_REBOOT config bit is 0, then the PCH will reboot the system after
the second timeout. The reboot is done by asserting PLTRST#.
Intruder Detect (INTRD_DET)—R/WC.
0 = Software clears this bit by writing a 1 to it, or by RTCRST# assertion.
1 = Set by PCH to indicate that an intrusion was detected. This bit is set even if the
system is in G3 state.
NOTES:
1. This bit has a recovery time. After writing a 1 to this bit position (to clear it), the bit
may be read back as a 1 for up 65 microseconds before it is read as a 0. Software
must be aware of this recovery time when reading this bit after clearing it.
0 2. If the INTRUDER# signal is active when the software attempts to clear the
INTRD_DET bit, the bit will remain as a 1, and the SMI# will be generated again
immediately. The SMI handler can clear the INTRD_SEL bits (TCOBASE + 0Ah, bits
2:1), to avoid further SMIs. However, if the INTRUDER# signals goes inactive and
then active again, there will not be further SMI’s (because the INTRD_SEL bits
would select that no SMI# be generated).
3. If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is
written as a 1, then the INTRD_DET signal will go to a 0 when INTRUDER# input
signal goes inactive. This is slightly different than a classic sticky bit, since most
sticky bits would remain active indefinitely when the signal goes active and would
immediately go inactive when a 1 is written to the bit.
550 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.9.6 TCO1_CNT—TCO1 Control Register
I/O Address: TCOBASE +08h Attribute: R/W, R/WLO, R/WC
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Core
Bit Description
15:13 Reserved
TCO_LOCK—R/WLO. When set to 1, this bit prevents writes from changing the TCO_EN
bit (in offset 30h of Power Management I/O space). Once this bit is set to 1, it can not
12
be cleared by software writing a 0 to this bit location. A core-well reset is required to
change this bit from 1 to 0. This bit defaults to 0.
TCO Timer Halt (TCO_TMR_HLT)—R/W.
0 = The TCO Timer is enabled to count.
11 1 = The TCO Timer will halt. It will not count, and thus cannot reach a value that will
cause an SMI# or set the SECOND_TO_STS bit. When set, this bit will prevent
rebooting and prevent Alert On LAN event messages from being transmitted on the
SMLink (but not Alert On LAN* heartbeat messages).
10 Reserved
NMI2SMI_EN—R/W.
0 = Normal NMI functionality.
1 = Forces all NMIs to instead cause SMIs. The functionality of this bit is dependent
upon the settings of the NMI_EN bit and the GBL_SMI_EN bit as detailed in the
following table:
9 NMI_EN GBL_SMI_EN Description
0b 0b No SMI# at all because GBL_SMI_EN = 0
0b 1b SMI# will be caused due to NMI events
1b 0b No SMI# at all because GBL_SMI_EN = 0
1b 1b No SMI# due to NMI because NMI_EN = 1
NMI_NOW—R/WC.
0 = Software clears this bit by writing a 1 to it. The NMI handler is expected to clear
8 this bit. Another NMI will not be generated until the bit is cleared.
1 = Writing a 1 to this bit causes an NMI. This allows the BIOS or SMI handler to force
an entry to the NMI handler.
7:0 Reserved
Datasheet 551
LPC Interface Bridge Registers (D31:F0)
12.9.7 TCO2_CNT—TCO2 Control Register
I/O Address: TCOBASE +0Ah Attribute: R/W
Default Value: 0008h Size: 16 bits
Lockable: No Power Well: Resume
Bit Description
15:6 Reserved
OS_POLICY—R/W. OS-based software writes to these bits to select the policy that the
BIOS will use after the platform resets due the WDT. The following convention is
recommended for the BIOS and OS:
00 = Boot normally
01 = Shut down
5:4
10 = Do not load OS. Hold in pre-boot state and use LAN to determine next step
11 = Reserved
NOTE: These are just scratchpad bits. They should not be reset when the TCO logic
resets the platform due to Watchdog Timer.
GPIO11_ALERT_DISABLE—R/W. At reset (using RSMRST# asserted) this bit is set
and GPIO[11] alerts are disabled.
3 0 = Enable.
1 = Disable GPIO11/SMBALERT# as an alert source for the heartbeats and the SMBus
slave.
INTRD_SEL—R/W. This field selects the action to take if the INTRUDER# signal goes
active.
00 = No interrupt or SMI#
2:1
01 = Interrupt (as selected by TCO_INT_SEL).
10 = SMI
11 = Reserved
0 Reserved
12.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers
I/O Address: TCOBASE +0Ch (Message 1)Attribute: R/W
TCOBASE +0Dh (Message 2)
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Resume
Bit Description
TCO_MESSAGE[n]—R/W. BIOS can write into these registers to indicate its boot
7:0 progress. The external microcontroller can read these registers to monitor the boot
progress.
552 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.9.9 TCO_WDCNT—TCO Watchdog Control Register
Offset Address: TCOBASE + 0Eh Attribute: R/W
Default Value: 00h Size: 8 bits
Power Well: Resume
Bit Description
The BIOS or system management software can write into this register to indicate more
details on the boot progress. The register will reset to 00h based on a RSMRST# (but
7:0
not PLTRST#). The external microcontroller can read this register to monitor boot
progress.
12.9.10 SW_IRQ_GEN—Software IRQ Generation Register
Offset Address: TCOBASE + 10h Attribute: R/W
Default Value: 03h Size: 8 bits
Power Well: Core
Bit Description
7:2 Reserved
IRQ12_CAUSE—R/W. When software sets this bit to 1, IRQ12 will be asserted. When
1
software sets this bit to 0, IRQ12 will be de-asserted.
IRQ1_CAUSE—R/W. When software sets this bit to 1, IRQ1 will be asserted. When
0
software sets this bit to 0, IRQ1 will be de-asserted.
12.9.11 TCO_TMR—TCO Timer Initial Value Register
I/O Address: TCOBASE +12h Attribute: R/W
Default Value: 0004h Size: 16 bits
Lockable: No Power Well: Core
Bit Description
15:10 Reserved
TCO Timer Initial Value—R/W. Value that is loaded into the timer each time the
TCO_RLD register is written. Values of 0000h or 0001h will be ignored and should not
be attempted. The timer is clocked at approximately 0.6 seconds, and thus allows
9:0 timeouts ranging from 1.2 second to 613.8 seconds.
NOTE: The timer has an error of ±1 tick (0.6 S).
The TCO Timer will only count down in the S0 state.
Datasheet 553
LPC Interface Bridge Registers (D31:F0)
12.10 General Purpose I/O Registers
The control for the general purpose I/O signals is handled through a 128-byte I/O
space. The base offset for this space is selected by the GPIOBASE register.
Table 12-13. Registers to Control GPIO Address Map
GPIOBASE
Mnemonic Register Name Default Attribute
+ Offset
00h–03h GPIO_USE_SEL GPIO Use Select B96BA1FFh R/W
04h–07h GP_IO_SEL GPIO Input/Output Select EEFF6EFFh R/W
08h–0Bh — Reserved 0h —
GPIO Level for Input or
0Ch–0Fh GP_LVL 02FE0100h R/W
Output
10h–13h — Reserved 0h —
14h–17h — Reserved 0h —
18h–1Bh GPO_BLINK GPIO Blink Enable 00040000h R/W
1Ch–1Fh GP_SER_BLINK GP Serial Blink 00000000h R/W
GP Serial Blink Command
20h–23h GP_SB_CMDSTS 00080000h R/W
Status
24h–27h GP_SB_DATA GP Serial Blink Data 00000000h R/W
28h–29h GPI_NMI_EN GPI NMI Enable 0000h R/W
2Ah–2Bh GPI_NMI_STS GPI NMI Status 0000h R/WC
2Ch–2Fh GPI_INV GPIO Signal Invert 00000000h R/W
020300FEh
(mobile only) /
30h–33h GPIO_USE_SEL2 GPIO Use Select 2 R/W
020300FFh
(Desktop only)
34h–37h GP_IO_SEL2 GPIO Input/Output Select 2 1F57FFF4h R/W
GPIO Level for Input or
38h–3Bh GP_LVL2 A4AA0007h R/W
Output 2
3Ch–3Fh — Reserved 0h —
00000030h
(mobile only)/
40h–43h GPIO_USE_SEL3 GPIO Use Select 3 R/W
00000130h
(desktop only)
44h–47h GP_IO_SEL3 GPIO Input/Output Select 3 00000FF0h R/W
GPIO Level for Input or
48h–4Bh GP_LVL3 000000C0h R/W
Output 3
4Ch–5Fh — Reserved — —
60h–63h GP_RST_SEL1 GPIO Reset Select 1 01000000h R/W
64h–67h GP_RST_SEL2 GPIO Reset Select 2 00000000h R/W
68h–6Bh GP_RST_SEL3 GPIO Reset Select 3 00000000h R/W
6Ch–7Fh — Reserved — —
554 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.10.1 GPIO_USE_SEL—GPIO Use Select Register
Offset Address: GPIOBASE + 00h Attribute: R/W
Default Value: B96BA1FFh Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Bit Description
GPIO_USE_SEL[31:0]—R/W. Each bit in this register enables the corresponding GPIO
(if it exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
NOTES:
1. The following bits are always 1 because they are always unmultiplexed: 8, 15,
24, 27, and 28.
2. After a full reset (RSMRST#) all multiplexed signals in the resume and core
31:0
wells are configured as their default function. After only a PLTRST#, the GPIOs
in the core well are configured as their default function.
3. When configured to GPIO mode, the multiplexing logic will present the inactive
state to native logic that uses the pin as an input.
4. All GPIOs are reset to the default state by CF9h reset except GPIO24. Other
resume well GPIOs' reset behavior can be programmed using GP_RST_SEL
registers.
5. Bit 29 can be configured to GPIO when SLP_WLAN#/GPIO29 Select soft strap is
set to 1 (GPIO usage).
12.10.2 GP_IO_SEL—GPIO Input/Output Select Register
Offset Address: GPIOBASE +04h Attribute: R/W
Default Value: EEFF6EFFh Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Bit Description
GP_IO_SEL[31:0]—R/W.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits have
no effect. The value reported in this register is undefined when programmed as
31:0
native mode.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
Datasheet 555
LPC Interface Bridge Registers (D31:F0)
12.10.3 GP_LVL—GPIO Level for Input or Output Register
Offset Address: GPIOBASE +0Ch Attribute: R/W
Default Value: 02FE0100h Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Bit Description
GP_LVL[31:0]—R/W. These registers are implemented as dual read/write with
dedicated storage each. Write value will be stored in the write register, while read is
coming from the read register which will always reflect the value of the pin.
If GPIO[n] is programmed to be an output (using the corresponding bit in the
GP_IO_SEL register), then the corresponding GP_LVL[n] write register value will
drive a high or low value on the output pin. 1 = high, 0 = low.
31:0
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are
stored but have no effect to the pin value. The value reported in this register is
undefined when programmed as native mode.
NOTE: Bit 29 setting will be ignored if Intel ME FW is configuring SLP_LAN# behavior.
When GPIO29/SLP_LAN# Select soft strap is set to 1 (GPIO usage), bit 29 can
be used as regular GP_LVL bit.
12.10.4 GPO_BLINK—GPO Blink Enable Register
Offset Address: GPIOBASE +18h Attribute: R/W
Default Value: 00040000h Size: 32 bits
Lockable: No Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Bit Description
GP_BLINK[31:0]—R/W. The setting of this bit has no effect if the corresponding
GPIO signal is programmed as an input.
0 = The corresponding GPIO will function normally.
1 = If the corresponding GPIO is programmed as an output, the output signal will
blink at a rate of approximately once per second. The high and low times have
approximately 0.5 seconds each. The GP_LVL bit is not altered when this bit is
31:0 set.
The value of the corresponding GP_LVL bit remains unchanged during the blink
process, and does not effect the blink in any way. The GP_LVL bit is not altered
when programmed to blink. It will remain at its previous value.
These bits correspond to GPIO in the Resume well. These bits revert to the default
value based on RSMRST# or a write to the CF9h register (but not just on
PLTRST#).
NOTE: GPIO18 will blink by default immediately after reset. This signal could be connected to an
LED to indicate a failed boot (by programming BIOS to clear GP_BLINK18 after successful
POST).
556 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.10.5 GP_SER_BLINK—GP Serial Blink Register
Offset Address: GPIOBASE +1Ch Attribute: R/W
Default Value: 00000000h Size: 32 bits
Lockable: No Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Bit Description
GP_SER_BLINK[31:0]—R/W. The setting of this bit has no effect if the
corresponding GPIO is programmed as an input or if the corresponding GPIO has the
GPO_BLINK bit set.
When set to a 0, the corresponding GPIO will function normally.
When using serial blink, this bit should be set to a 1 while the corresponding
GP_IO_SEL bit is set to 1. Setting the GP_IO_SEL bit to 0 after the GP_SER_BLINK bit
31:0 ensures PCH will not drive a 1 on the pin as an output. When this corresponding bit is
set to a 1 and the pin is configured to output mode, the serial blink capability is
enabled. The PCH will serialize messages through an open-drain buffer configuration.
The value of the corresponding GP_LVL bit remains unchanged and does not impact
the serial blink capability in any way.
Writes to this register have no effect when the corresponding pin is configured in
native mode and the read value returned is undefined.
12.10.6 GP_SB_CMDSTS—GP Serial Blink Command
Status Register
Offset Address: GPIOBASE +20h Attribute: R/W, RO
Default Value: 00080000h Size: 32 bits
Lockable: No Power Well: Core
Bit Description
31:24 Reserved
Data Length Select (DLS)—R/W. This field determines the number of bytes to
serialize on GPIO.
00 = Serialize bits 7:0 of GP_SB_DATA (1 byte)
01 = Serialize bits 15:0 of GP_SB_DATA (2 bytes)
23:22 10 = Undefined – Software must not write this value
11 = Serialize bits 31:0 of GP_SB_DATA (4 bytes)
Software should not modify the value in this register unless the Busy bit is clear. Writes
to this register have no effect when the corresponding pin is configured in native mode
and the read value returned is undefined.
Data Rate Select (DRS)—R/W. This field selects the number of 120ns time intervals
to count between Manchester data transitions. The default of 8h results in a 960 ns
21:16 minimum time between transitions. A value of 0h in this register produces undefined
behavior.
Software should not modify the value in this register unless the Busy bit is clear.
15:9 Reserved
Busy—RO. This read-only status bit is the hardware indication that a serialization is in
8 progress. Hardware sets this bit to 1 based on the Go bit being set. Hardware clears
this bit when the Go bit is cleared by the hardware.
7:1 Reserved
Go—R/W. This bit is set to 1 by software to start the serialization process. Hardware
0 clears the bit after the serialized data is sent. Writes of 0 to this register have no effect.
Software should not write this bit to 1 unless the Busy status bit is cleared.
Datasheet 557
LPC Interface Bridge Registers (D31:F0)
12.10.7 GP_SB_DATA—GP Serial Blink Data Register
Offset Address: GPIOBASE +24h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Lockable: No Power Well: Core
Bit Description
GP_SB_DATA[31:0]—R/W. This register contains the data serialized out. The
31:0 number of bits shifted out are selected through the DLS field in the GP_SB_CMDSTS
register. This register should not be modified by software when the Busy bit is set.
12.10.8 GPI_NMI_EN—GPI NMI Enable Register
Offset Address: GPIOBASE +28h Attribute: R/W
Default Value: 00000h Size: 16 bits
Lockable: No Power Well: Core for 0:7
Resume for 8:15
Bit Description
GPI_NMI_EN[15:0]. GPI NMI Enable: This bit only has effect if the
corresponding GPIO is used as an input and its GPI_ROUT register is being
15:0
programmed to NMI functionality. When set to 1, it used to allow active-low and
active-high inputs (depends on inversion bit) to cause NMI.
12.10.9 GPI_NMI_STS—GPI NMI Status Register
Offset Address: GPIOBASE +2Ah Attribute: R/WC
Default Value: 00000h Size: 16 bits
Lockable: Yes Power Well: Core for 0:7
Resume for 8:15
Bit Description
GPI_NMI_STS[15:0]. GPI NMI Status: GPI_NMI_STS[15:0]. GPI NMI Status:
This bit is set if the corresponding GPIO is used as an input, and its GPI_ROUT
register is being programmed to NMI functionality and also GPI_NMI_EN bit is set
when it detects either:
15:0
1) active-high edge when its corresponding GPI_INV is configured with value 0.
2) active-low edge when its corresponding GPI_INV is configured with value 1.
NOTE: Writing value of 1 will clear the bit, while writing value of 0 have no effect.
558 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.10.10 GPI_INV—GPIO Signal Invert Register
Offset Address: GPIOBASE +2Ch Attribute: R/W
Default Value: 00000000h Size: 32 bits
Lockable: No Power Well: Core for 17, 16, 7:0
Bit Description
31:16 Reserved
Input Inversion (GP_INV[n])—R/W. This bit only has effect if the corresponding
GPIO is used as an input and used by the GPE logic, where the polarity matters. When
set to ‘1’, then the GPI is inverted as it is sent to the GPE logic that is using it. This bit
has no effect on the value that is reported in the GP_LVL register.
These bits are used to allow both active-low and active-high inputs to cause SMI# or
SCI. In the S0 or S1 state, the input signal must be active for at least two PCI clocks to
ensure detection by the PCH. In the S3, S4, or S5 states the input signal must be active
15:0 for at least 2 RTC clocks to ensure detection. The setting of these bits has no effect if
the corresponding GPIO is programmed as an output. These bits correspond to GPI that
are in the resume well, and will be reset to their default values by RSMRST# or by a
write to the CF9h register.
0 = The corresponding GPI_STS bit is set when the PCH detects the state of the input
pin to be high.
1 = The corresponding GPI_STS bit is set when the PCH detects the state of the input
pin to be low.
12.10.11 GPIO_USE_SEL2—GPIO Use Select 2 Register
Offset Address: GPIOBASE +30h Attribute: R/W
Default Value: 020300FFh (Desktop) Size: 32 bits
020300FEh (Mobile)
Lockable: Yes Power Well:
Core for 0:7, 16:23,
Resume for 8:15, 24:31
This register corresponds to GPIO[63:32]. Bit 0 corresponds to GPIO32 and bit 31 cor-
responds to GPIO63.
Bit Description
GPIO_USE_SEL2[63:32]—R/W. Each bit in this register enables the corresponding
GPIO (if it exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
NOTES:
1. The following bits are always 1 because they are always unmultiplexed: 3, 25.
The following bit is unmultiplexed in desktop and is also 1: 0.
31:0 2. If GPIO[n] does not exist, then, the (n-32) bit in this register will always read as
0 and writes will have no effect. The following bit is also not used in mobile and
is always 0 on mobile: 0.
3. After a full reset RSMRST# all multiplexed signals in the resume and core wells
are configured as their default function. After only a PLTRST#, the GPIOs in the
core well are configured as their default function.
4. When configured to GPIO mode, the multiplexing logic will present the inactive
state to native logic that uses the pin as an input.
5. Bit 26 is ignored, functionality is configured by bits 9:8 of FLMAP0 register.
6. GPIO47 and GPIO56 are mobile only GPIOs.
Datasheet 559
LPC Interface Bridge Registers (D31:F0)
12.10.12 GP_IO_SEL2—GPIO Input/Output Select 2 Register
Offset Address: GPIOBASE +34h Attribute: R/W
Default Value: 1F57FFF4h
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
This register corresponds to GPIO[63:32]. Bit 0 corresponds to GPIO32 and bit 31 cor-
responds to GPIO63.
Bit Description
GP_IO_SEL2[63:32]—R/W.
0 = GPIO signal is programmed as an output.
31:0
1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL2 register) is
programmed as an input.
12.10.13 GP_LVL2—GPIO Level for Input or Output 2 Register
Offset Address: GPIOBASE +38h Attribute: R/W
Default Value: A4AA0007h Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
This register corresponds to GPIO[63:32]. Bit 0 corresponds to GPIO32 and bit 31
corresponds to GPIO63.
Bit Description
GP_LVL[63:32]—R/W. These registers are implemented as dual read/write with
dedicated storage each. Write value will be stored in the write register, while read is
coming from the read register which will always reflect the value of the pin. If GPIO[n]
is programmed to be an output (using the corresponding bit in the GP_IO_SEL
register), then the corresponding GP_LVL[n] write register value will drive a high or low
31:0 value on the output pin.
1 = high, 0 = low.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are
stored but have no effect to the pin value. The value reported in this register is
undefined when programmed as native mode.
560 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.10.14 GPIO_USE_SEL3—GPIO Use Select 3 Register
Offset Address: GPIOBASE +40h Attribute: R/W
Default Value: 00000130h (Desktop) Size: 32 bits
00000030h (Mobile)
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
This register corresponds to GPIO[75:64]. Bit 0 corresponds to GPIO64 and bit 11
corresponds to GPIO75.
Bit Description
31:12 Always 0. No corresponding GPIO.
GPIO_USE_SEL3[75:64]—R/W. Each bit in this register enables the corresponding
GPIO (if it exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
NOTES:
1. The following bit is always 1 because it is always unmultiplexed: 8
11:0 2. If GPIO[n] does not exist, then, the (n-64) bit in this register will always read as
0 and writes will have no effect.
3. After a full reset RSMRST# all multiplexed signals in the resume and core wells
are configured as their default function. After only a PLTRST#, the GPIOs in the
core well are configured as their default function.
4. When configured to GPIO mode, the multiplexing logic will present the inactive
state to native logic that uses the pin as an input.
5. GPIO73 is a mobile only GPIO.
12.10.15 GP_IO_SEL3—GPIO Input/Output Select 3 Register
Offset Address: GPIOBASE +44h Attribute: R/W
Default Value: 00000FF0h Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
This register corresponds to GPIO[75:64]. Bit 0 corresponds to GPIO64 and bit 11
corresponds to GPIO75.
Bit Description
31:12 Always 0. No corresponding GPIO.
GP_IO_SEL3[75:64]—R/W.
0 = GPIO signal is programmed as an output.
11:0
1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL3 register) is
programmed as an input.
Datasheet 561
LPC Interface Bridge Registers (D31:F0)
12.10.16 GP_LVL3—GPIO Level for Input or Output 3 Register
Offset Address: GPIOBASE +48h Attribute: R/W
Default Value: 000000C0h Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
This register corresponds to GPIO[75:64]. Bit 0 corresponds to GPIO64 and bit 11
corresponds to GPIO75.
Bit Description
31:12 Always 0. No corresponding GPIO.
GP_LVL[75:64]—R/W.
These registers are implemented as dual read/write with dedicated storage each. Write
value will be stored in the write register, while read is coming from the read register
which will always reflect the value of the pin. If GPIO[n] is programmed to be an output
(using the corresponding bit in the GP_IO_SEL register), then the corresponding
11:0
GP_LVL[n] write register value will drive a high or low value on the output pin.
1 = high, 0 = low.
When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are
stored but have no effect to the pin value. The value reported in this register is
undefined when programmed as native mode.
12.10.17 GP_RST_SEL1—GPIO Reset Select Register
Offset Address: GPIOBASE +60h Attribute: R/W
Default Value: 01000000h Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Bit Description
GP_RST_SEL[31:24]—R/W.
0 = Corresponding GPIO registers will be reset by PWROK de-assertion, CF9h reset
(06h or 0Eh), or SYS_RESET# assertion.
31:24
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
NOTE: GPIO[24] register bits are not cleared by CF9h reset by default.
23:16 Reserved
GP_RST_SEL[15:8]—R/W.
15:8 0 = Corresponding GPIO registers will be reset by PWROK de-assertion, CF9h reset
(06h or 0Eh), or SYS_RESET# assertion.
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
7:0 Reserved
562 Datasheet
LPC Interface Bridge Registers (D31:F0)
12.10.18 GP_RST_SEL2—GPIO Reset Select Register
Offset Address: GPIOBASE +64h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Bit Description
GP_RST_SEL[63:56]—R/W.
31:24 0 = Corresponding GPIO registers will be reset by PWROK de-assertion, CF9h reset
(06h or 0Eh), or SYS_RESET# assertion.
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
23:16 Reserved
GP_RST_SEL[47:40]—R/W.
0 = Corresponding GPIO registers will be reset by PWROK de-assertion, CF9h reset
15:8
(06h or 0Eh), or SYS_RESET# assertion.
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
7:0 Reserved
12.10.19 GP_RST_SEL3—GPIO Reset Select Register
Offset Address: GPIOBASE +68h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Lockable: Yes Power Well: Core for 0:7, 16:23,
Resume for 8:15, 24:31
Bit Description
31:12 Reserved
GP_RST_SEL[75:72]—R/W.
11:8 0 = Corresponding GPIO registers will be reset by PWROK de-assertion, CF9h reset
(06h or 0Eh), or SYS_RESET# assertion.
1 = Corresponding GPIO registers will be reset by RSMRST# assertion only.
7:0 Reserved
§§
Datasheet 563
LPC Interface Bridge Registers (D31:F0)
564 Datasheet
SATA Controller Registers (D31:F2)
13 SATA Controller Registers
(D31:F2)
13.1 PCI Configuration Registers (SATA–D31:F2)
Note: Address locations that are not shown should be treated as Reserved.
All of the SATA registers are in the core well. None of the registers can be locked.
Table 13-1. SATA Controller PCI Register Address Map (SATA–D31:F2) (Sheet 1 of 2)
Offset Mnemonic Register Name Default Attribute
00h–01h VID Vendor Identification 8086h RO
See register
02h–03h DID Device Identification RO
description
04h–05h PCICMD PCI Command 0000h R/W, RO
06h–07h PCISTS PCI Status 02B0h R/WC, RO
See register
08h RID Revision Identification RO
description
See register See register
09h PI Programming Interface
description description
See register See register
0Ah SCC Sub Class Code
description description
0Bh BCC Base Class Code 01h RO
0Dh PMLT Primary Master Latency Timer 00h RO
0Eh HTYPE Header Type 00h RO
10h–13h PCMD_BAR Primary Command Block Base Address 00000001h R/W, RO
14h–17h PCNL_BAR Primary Control Block Base Address 00000001h R/W, RO
Secondary Command Block Base
18h–1Bh SCMD_BAR 00000001h R/W, RO
Address
1Ch–1Fh SCNL_BAR Secondary Control Block Base Address 00000001h R/W, RO
20h–23h BAR Legacy Bus Master Base Address 00000001h R/W, RO
ABAR / AHCI Base Address / SATA Index Data See register See register
24h–27h
SIDPBA Pair Base Address description description
2Ch–2Dh SVID Subsystem Vendor Identification 0000h R/WO
2Eh–2Fh SID Subsystem Identification 0000h R/WO
34h CAP Capabilities Pointer 80h RO
3Ch INT_LN Interrupt Line 00h R/W
See register
3Dh INT_PN Interrupt Pin RO
description
40h–41h IDE_TIM Primary IDE Timing 0000h R/W
42h–43h IDE_TIM Secondary IDE Timing 0000h R/W
44h SIDETIM Slave IDE Timing 00h R/W
Datasheet 565
SATA Controller Registers (D31:F2)
Table 13-1. SATA Controller PCI Register Address Map (SATA–D31:F2) (Sheet 2 of 2)
Offset Mnemonic Register Name Default Attribute
48h SDMA_CNT Synchronous DMA Control 00h R/W
4Ah–4Bh SDMA_TIM Synchronous DMA Timing 0000h R/W
54h–57h IDE_CONFIG IDE I/O Configuration 00000000h R/W
PCI Power Management Capability See register
70h–71h PID RO
Identification description
See register
72h–73h PC PCI Power Management Capabilities RO
description
PCI Power Management Control and See register R/W, RO,
74h–75h PMCS
Status description R/WC
Message Signaled Interrupt Capability
80h–81h MSICI 7005h RO
Identification
Message Signaled Interrupt Message
82h–83h MSIMC 0000h RO, R/W
Control
Message Signaled Interrupt Message
84h–87h MSIMA 00000000h RO, R/W
Address
Message Signaled Interrupt Message
88h–89h MSIMD 0000h R/W
Data
90h MAP Address Map 0000h R/W, R/WO
92h–93h PCS Port Control and Status 0000h R/W, RO
94h–97h SCLKCG SATA Clock Gating Control 00000000h R/W
9Ch–9Fh SGC SATA General Configuration 00000000h R/W, R/WO
A8h–ABh SATACR0 SATA Capability Register 0 0010B012h RO, R/WO
ACh–AFh SATACR1 SATA Capability Register 1 00000048h RO
B0h–B1h FLRCID FLR Capability Identification 0009h RO
See register
B2h–B3h FLRCLV FLR Capability Length and Version R/WO, RO
description
B4h–B5h FLRC FLR Control 0000h RO, R/W
C0h ATC APM Trapping Control 00h R/W
C4h ATS APM Trapping Status 00h R/WC
D0h–D3h SP Scratch Pad 00000000h R/W
E0h–E3h BFCS BIST FIS Control/Status 00000000h R/W, R/WC
E4h–E7h BFTD1 BIST FIS Transmit Data, DW1 00000000h R/W
E8h–EBh BFTD2 BIST FIS Transmit Data, DW2 00000000h R/W
NOTE: The PCH SATA controller is not arbitrated as a PCI device; therefore, it does not need a
master latency timer.
566 Datasheet
SATA Controller Registers (D31:F2)
13.1.1 VID—Vendor Identification Register (SATA—D31:F2)
Offset Address: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bit
Lockable: No Power Well: Core
Bit Description
15:0 Vendor ID—RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
13.1.2 DID—Device Identification Register (SATA—D31:F2)
Offset Address: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bit
Lockable: No Power Well: Core
Bit Description
Device ID—RO. This is a 16-bit value assigned to the PCH SATA controller.
15:0
NOTE: The value of this field will change dependent upon the value of the MAP
Register. See Section 13.1.34
13.1.3 PCICMD—PCI Command Register (SATA–D31:F2)
Address Offset: 04h–05h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved
Interrupt Disable—R/W. This disables pin-based INTx# interrupts. This bit has no
effect on MSI operation.
10 0 = Internal INTx# messages are generated if there is an interrupt and MSI is not
enabled.
1 = Internal INTx# messages will not be generated.
9 Fast Back to Back Enable (FBE)—RO. Hardwired to 0.
8 SERR# Enable (SERR_EN)—RO. Hardwired to 0.
7 Wait Cycle Control (WCC)—RO. Hardwired to 0.
Parity Error Response (PER)—R/W.
0 = Disabled. SATA controller will not generate PERR# when a data parity error is
6
detected.
1 = Enabled. SATA controller will generate PERR# when a data parity error is detected.
5 VGA Palette Snoop (VPS)—RO. Hardwired to 0.
4 Postable Memory Write Enable (PMWE)—RO. Hardwired to 0.
3 Special Cycle Enable (SCE)—RO. Hardwired to 0.
Bus Master Enable (BME)—R/W. This bit controls the SATA controller’s ability to act
2 as a master for data transfers. This bit does not impact the generation of completions
for split transaction commands.
Memory Space Enable (MSE)—R/W / RO. Controls access to the SATA controller’s
1
target memory space (for AHCI). This bit is RO 0 when not in AHCI/RAID modes.
I/O Space Enable (IOSE)—R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as
0 well as the Bus Master I/O registers.
1 = Enable. The Base Address register for the Bus Master registers should be
programmed before this bit is set.
Datasheet 567
SATA Controller Registers (D31:F2)
13.1.4 PCISTS—PCI Status Register (SATA–D31:F2)
Address Offset: 06h–07h Attribute: R/WC, RO
Default Value: 02B0h Size: 16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit Description
Detected Parity Error (DPE)—R/WC.
15 0 = No parity error detected by SATA controller.
1 = SATA controller detects a parity error on its interface.
14 Signaled System Error (SSE)—RO. Hardwired to 0.
Received Master Abort (RMA)—R/WC.
13 0 = Master abort not generated.
1 = SATA controller, as a master, generated a master abort.
12 Reserved—R/WC.
11 Signaled Target Abort (STA)—RO. Hardwired to 0.
DEVSEL# Timing Status (DEV_STS)—RO.
10:9
01 = Hardwired; Controls the device select time for the SATA controller’s PCI interface.
Data Parity Error Detected (DPED)—R/WC. For PCH, this bit can only be set on read
completions received from the bus when there is a parity error.
0 = No data parity error received.
8
1 = SATA controller, as a master, either detects a parity error or sees the parity error
line asserted, and the parity error response bit (bit 6 of the command register) is
set.
7 Fast Back to Back Capable (FB2BC)—RO. Hardwired to 1.
6 Reserved
5 66MHz Capable (66MHZ_CAP)—RO. Hardwired to 1.
Capabilities List (CAP_LIST)—RO. This bit indicates the presence of a capabilities
4 list. The minimum requirement for the capabilities list must be PCI power management
for the SATA controller.
Interrupt Status (INTS)—RO. Reflects the state of INTx# messages, IRQ14 or
IRQ15.
3 0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the
command register [offset 04h]).
1 = Interrupt is to be asserted
2:0 Reserved
13.1.5 RID—Revision Identification Register (SATA—D31:F2)
Offset Address: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
Bit Description
Revision ID—RO. This field indicates the device specific revision identifier. See
7:0
Section 1.3 for the value of the RID Register.
568 Datasheet
SATA Controller Registers (D31:F2)
13.1.6 PI—Programming Interface Register (SATA–D31:F2)
13.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h
Address Offset: 09h Attribute: R/W, RO
Default Value: 8Ah Size: 8 bits
Bit Description
Reserved. This read-only bit is a 1 to indicate that the PCH supports bus master
7
operation
6:4 Reserved. Will always return 0.
Secondary Mode Native Capable (SNC)—RO. Hardwired to ‘1’ to indicate secondary
3
controller supports both legacy and native modes.
Secondary Mode Native Enable (SNE)—R/W.
Determines the mode that the secondary channel is operating in.
0 = Secondary controller operating in legacy (compatibility) mode
2 1 = Secondary controller operating in native PCI mode.
If this bit is set by software, then the PNE bit (bit 0 of this register) must also be set by
software. While in theory these bits can be programmed separately, such a
configuration is not supported by hardware.
Primary Mode Native Capable (PNC)—RO. Hardwired to ‘1’ to indicate primary
1
controller supports both legacy and native modes.
Primary Mode Native Enable (PNE)—R/W.
Determines the mode that the primary channel is operating in.
0 = Primary controller operating in legacy (compatibility) mode.
0
1 = Primary controller operating in native PCI mode.
If this bit is set by software, then the SNE bit (bit 2 of this register) must also be set by
software simultaneously.
13.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h
Address Offset: 09h Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
Interface (IF)—RO.
7:0
When configured as RAID, this register becomes read only 0.
13.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h
Address Offset: 09h Attribute: RO
Default Value: 01h Size: 8 bits
Bit Description
Interface (IF)—RO.
7:0
Indicates that the SATA Controller is an AHCI HBA that has a major revision of 1.
Datasheet 569
SATA Controller Registers (D31:F2)
13.1.7 SCC—Sub Class Code Register (SATA–D31:F2)
Address Offset: 0Ah Attribute: RO
Default Value: See bit description Size: 8 bits
Bit Description
Sub Class Code (SCC)
This field specifies the sub-class code of the controller, per the table below:
MAP.SMS (D31:F2:Offset
SCC Register Value
90h:bit 7:6) Value
00b 01h (IDE Controller)
7:0
01b 06h (AHCI Controller)
10b 04h (RAID Controller)
NOTE: Not all SCC values may be available for a given SKU. See Section 1.3 for details
on storage controller capabilities.
13.1.8 BCC—Base Class Code Register
(SATA–D31:F2SATA–D31:F2)
Address Offset: 0Bh Attribute: RO
Default Value: 01h Size: 8 bits
Bit Description
Base Class Code (BCC)—RO.
7:0
01h = Mass storage device
13.1.9 PMLT—Primary Master Latency Timer Register
(SATA–D31:F2)
Address Offset: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
Master Latency Timer Count (MLTC)—RO.
7:0 00h = Hardwired. The SATA controller is implemented internally, and is not arbitrated
as a PCI device, so it does not need a Master Latency Timer.
570 Datasheet
SATA Controller Registers (D31:F2)
13.1.10 HTYPE—Header Type Register
(SATA–D31:F2)
Address Offset: 0Eh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
Multi-function Device (MFD)—RO.
7
Indicates this SATA controller is not part of a multifunction device.
Header Layout (HL)—RO.
6:0
Indicates that the SATA controller uses a target device layout.
13.1.11 PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F2)
Address Offset: 10h–13h Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
Base Address—R/W. This field provides the base address of the I/O space (8
15:3
consecutive I/O locations).
2:1 Reserved
Resource Type Indicator (RTE)—RO. Hardwired to 1 to indicate a request for I/O
0
space.
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
13.1.12 PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F2)
Address Offset: 14h–17h Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
Base Address—R/W. This field provides the base address of the I/O space (4
15:2
consecutive I/O locations).
1 Reserved
Resource Type Indicator (RTE)—RO. Hardwired to 1 to indicate a request for I/O
0
space.
NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Control Block.
Datasheet 571
SATA Controller Registers (D31:F2)
13.1.13 SCMD_BAR—Secondary Command Block Base Address
Register (SATA D31:F2)
Address Offset: 18h–1Bh Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
Base Address—R/W. This field provides the base address of the I/O space (8
15:3
consecutive I/O locations).
2:1 Reserved
Resource Type Indicator (RTE)—RO. Hardwired to 1 to indicate a request for I/O
0
space.
NOTE: This 8-byte I/O space is used in native mode for the Secondary Controller’s Command
Block.
13.1.14 SCNL_BAR—Secondary Control Block Base Address
Register (SATA D31:F2)
Address Offset: 1Ch–1Fh Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
Base Address—R/W. This field provides the base address of the I/O space (4
15:2
consecutive I/O locations).
1 Reserved
Resource Type Indicator (RTE)—RO. Hardwired to 1 to indicate a request for I/O
0
space.
NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Control Block.
572 Datasheet
SATA Controller Registers (D31:F2)
13.1.15 BAR—Legacy Bus Master Base Address Register
(SATA–D31:F2)
Address Offset: 20h–23h Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
The Bus Master IDE interface function uses Base Address register 5 to request a 16-
byte I/O space to provide a software interface to the Bus Master functions. Only 12
bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits [15:4]
are used to decode the address.
Bit Description
31:16 Reserved
Base Address—R/W. This field provides the base address of the I/O space (16
15:5
consecutive I/O locations).
Base—R/W / RO. When SCC is 01h, this bit will be R/W resulting in requesting 16B of I/
4 O space. When SCC is not 01h, this bit will be Read Only 0, resulting in requesting 32B
of I/O space.
3:1 Reserved
Resource Type Indicator (RTE)—RO. Hardwired to 1 to indicate a request for I/O
0
space.
13.1.16 ABAR/SIDPBA1—AHCI Base Address Register / Serial ATA
Index Data Pair Base Address (SATA–D31:F2)
When the programming interface is not IDE (that is, SCC is not 01h), this register is
named ABAR. When the programming interface is IDE, this register becomes SIDPBA.
Hardware does not clear those BA bits when switching from IDE component to non-IDE
component or vice versa. BIOS is responsible for clearing those bits to 0 since the
number of writable bits changes after component switching (as indicated by a change
in SCC). In the case, this register will then have to be re-programmed to a proper
value.
13.1.16.1 When SCC is not 01h
When the programming interface is not IDE, the register represents a memory BAR
allocating space for the AHCI memory registers defined in Section 13.4.
Address Offset: 24–27h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:11 Base Address (BA)—R/W. Base address of register memory space (aligned to 2 KB)
10:4 Reserved
3 Prefetchable (PF)—RO. Indicates that this range is not pre-fetchable
Type (TP)—RO. Indicates that this range can be mapped anywhere in 32-bit address
2:1
space.
Resource Type Indicator (RTE)—RO. Hardwired to 0 to indicate a request for
0
register memory space.
NOTE: The ABAR register must be set to a value of 0001_0000h or greater.
Datasheet 573
SATA Controller Registers (D31:F2)
13.1.16.2 When SCC is 01h
When the programming interface is IDE, the register becomes an I/O BAR allocating
16 bytes of I/O space for the I/O-mapped registers defined in Section 13.2. Although
16 bytes of locations are allocated, only 8 bytes are used as SINDX and SDATA
registers; with the remaining 8 bytes preserved for future enhancement.
Address Offset: 24h–27h Attribute: R/WO
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
15:4 Base Address (BA)—R/W. Base address of the I/O space.
3:1 Reserved
0 Resource Type Indicator (RTE)—RO. Indicates a request for I/O space.
13.1.17 SVID—Subsystem Vendor Identification Register
(SATA–D31:F2)
Address Offset: 2Ch–2Dh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Core
Function Level Reset: No
Bit Description
Subsystem Vendor ID (SVID)—R/WO. Value is written by BIOS. No hardware action
15:0
taken on this value.
13.1.18 SID—Subsystem Identification Register (SATA–D31:F2)
Address Offset: 2Eh–2Fh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Core
Function Level Reset: No
Bit Description
Subsystem ID (SID)—R/WO. Value is written by BIOS. No hardware action taken on
15:0
this value.
13.1.19 CAP—Capabilities Pointer Register (SATA–D31:F2)
Address Offset: 34h Attribute: RO
Default Value: 80h Size: 8 bits
Bit Description
Capabilities Pointer (CAP_PTR)—RO. Indicates that the first capability pointer offset
7:0 is 80h. This value changes to 70h if the Sub Class Code (SCC) (Dev 31:F2:0Ah) is
configure as IDE mode (value of 01).
574 Datasheet
SATA Controller Registers (D31:F2)
13.1.20 INT_LN—Interrupt Line Register (SATA–D31:F2)
Address Offset: 3Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Function Level Reset: No
Bit Description
Interrupt Line—R/W. This field is used to communicate to software the interrupt line
7:0 that the interrupt pin is connected to.
Interrupt Line register is not reset by FLR.
13.1.21 INT_PN—Interrupt Pin Register (SATA–D31:F2)
Address Offset: 3Dh Attribute: RO
Default Value: See Register Description Size: 8 bits
Bit Description
Interrupt Pin—RO. This reflects the value of D31IP.SIP (Chipset Config
7:0
Registers:Offset 3100h:bits 11:8).
13.1.22 IDE_TIM—IDE Timing Register (SATA–D31:F2)
Address Offset: Primary: 40h–41h Attribute: R/W
Secondary: 42h–43h
Default Value: 0000h Size: 16 bits
Bits 14:12 and 9:0 of this register are R/W to maintain software compatibility. These
bits have no effect on hardware.
Bit Description
IDE Decode Enable (IDE)—R/W. Individually enable/disable the Primary or
Secondary decode.
0 = Disable.
15 1 = Enables the PCH to decode the associated Command Block (1F0–1F7h for primary,
170–177h for secondary, or their native mode BAR equivalents) and Control Block
(3F6h for primary, 376h for secondary, or their native mode BAR equivalents).
This bit effects the IDE decode ranges for both legacy and native-mode decoding.
IDE_TIM Field 2—R/W. This field is R/W to maintain software compatibility. This field
14:12
has no effect on hardware.
11:10 Reserved
IDE_TIM Field 1—R/W. This field is R/W to maintain software compatibility. This field
9:0
has no effect on hardware.
Datasheet 575
SATA Controller Registers (D31:F2)
13.1.23 SIDETIM—Slave IDE Timing Register (SATA–D31:F2)
Address Offset: 44h Attribute: R/W
Default Value: 00h Size: 8 bits
Note: This register is R/W to maintain software compatibility. These bits have no effect on
hardware.
Bit Description
SIDETIM Field 1—R/W. This field is R/W to maintain software compatibility. This field
7:0
has no effect on hardware.
13.1.24 SDMA_CNT—Synchronous DMA Control Register
(SATA–D31:F2)
Address Offset: 48h Attribute: R/W
Default Value: 00h Size: 8 bits
Note: This register is R/W to maintain software compatibility. These bits have no effect on
hardware.
Bit Description
7:4 Reserved
SDMA_CNT Field 1—R/W. This field is R/W to maintain software compatibility. This
3:0
field has no effect on hardware.
13.1.25 SDMA_TIM—Synchronous DMA Timing Register
(SATA–D31:F2)
Address Offset: 4Ah–4Bh Attribute: R/W
Default Value: 0000h Size: 16 bits
Note: This register is R/W to maintain software compatibility. These bits have no effect on
hardware.
Bit Description
15:14 Reserved
SDMA_TIM Field 4—R/W. This field is R/W to maintain software compatibility. This
13:12
field has no effect on hardware.
11:10 Reserved
SDMA_TIM Field 3—R/W. This field is R/W to maintain software compatibility. This
9:8
field has no effect on hardware.
7:6 Reserved
SDMA_TIM Field 2—R/W. This field is R/W to maintain software compatibility. This
5:4
field has no effect on hardware.
3:2 Reserved
SDMA_TIM Field 1—R/W. This field is R/W to maintain software compatibility. This
1:0
field has no effect on hardware.
576 Datasheet
SATA Controller Registers (D31:F2)
13.1.26 IDE_CONFIG—IDE I/O Configuration Register
(SATA–D31:F2)
Address Offset: 54h–57h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: This register is R/W to maintain software compatibility. These bits have no effect on
hardware.
Bit Description
31:24 Reserved
IDE_CONFIG Field 2—R/W. This field is R/W to maintain software compatibility. This
23:12
field has no effect on hardware.
11:8 Reserved
IDE_CONFIG Field 1—R/W. This field is R/W to maintain software compatibility. This
7:0
field has no effect on hardware.
13.1.27 PID—PCI Power Management Capability Identification
Register (SATA–D31:F2)
Address Offset: 70h–71h Attribute: RO
Default Value: See Register Description Size: 16 bits
Bits Description
Next Capability (NEXT)—R/W. A8h is the location of the Serial ATA capability
structure. A8h is the recommended setting for non-IDE mode.
If the controller is to operate in IDE mode, BIOS is requested to program this field to
15:8
00h.
NOTE: Refer to the SGC.REGLOCK description in order to lock the register to become
RO.
Capability ID (CID)—RO. Hardwired to 01h. Indicates that this pointer is a PCI power
7:0
management.
Datasheet 577
SATA Controller Registers (D31:F2)
13.1.28 PC—PCI Power Management Capabilities Register
(SATA–D31:F2)
Address Offset: 72h–73h Attribute: RO
Default Value: See Register Description Size: 16 bits
Bits Description
PME Support (PME_SUP)—RO.
00000 = If SCC = 01h, indicates no PME support in IDE mode.
15:11
01000 = If SCC is not 01h, in a non-IDE mode, indicates PME# can be generated from
the D3HOT state in the SATA host controller.
10 D2 Support (D2_SUP)—RO. Hardwired to 0. The D2 state is not supported
9 D1 Support (D1_SUP)—RO. Hardwired to 0. The D1 state is not supported
Auxiliary Current (AUX_CUR)—RO. PME# from D3COLD state is not supported,
8:6
therefore this field is 000b.
Device Specific Initialization (DSI)—RO. Hardwired to 0 to indicate that no device-
5
specific initialization is required.
4 Reserved
PME Clock (PME_CLK)—RO. Hardwired to 0 to indicate that PCI clock is not required
3
to generate PME#.
Version (VER)—RO. Hardwired to 011 to indicates support for Revision 1.2 of the PCI
2:0
Power Management Specification.
13.1.29 PMCS—PCI Power Management Control and Status
Register (SATA–D31:F2)
Address Offset: 74h–75h Attribute: R/W, R/WC
Default Value: 0008h Size: 16 bits
Function Level Reset: No (Bits 8 and 15)
Bits Description
PME Status (PMES)—R/WC. Bit is set when a PME event is to be requested, and if this
bit and PMEE is set, a PME# will be generated from the SATA controller
15 NOTE: When SCC = 01h, hardware will automatically change the attribute of this bit to
RO 0. Software is advised to clear PMEE and PMES together prior to changing
SCC thru MAP.SMS.
This bit is not reset by Function Level Reset.
14:9 Reserved
PME Enable (PMEE)—R/W. When set, the SATA controller asserts PME# when exiting
D3HOT on a wake event.
8 NOTE: When SCCSCC = 01h, hardware will automatically change the attribute of this
bit to RO 0. Software is advised to clear PMEE and PMES together prior to
changing SCC thru MAP.SMS.
This bit is not reset by Function Level Reset.
7:4 Reserved
578 Datasheet
SATA Controller Registers (D31:F2)
Bits Description
No Soft Reset (NSFRST)—RO. These bits are used to indicate whether devices
transitioning from D3HOT state to D0 state will perform an internal reset.
0 = Device transitioning from D3HOT state to D0 state perform an internal reset.
1 = Device transitioning from D3HOT state to D0 state do not perform an internal reset.
3 Configuration content is preserved. Upon transition from the D3HOT state to D0 state
initialized state, no additional operating system intervention is required to preserve
configuration context beyond writing to the PowerState bits.
Regardless of this bit, the controller transition from D3HOT state to D0 state by a system
or bus segment reset will return to the state D0 uninitialized with only PME context
preserved if PME is supported and enabled.
2 Reserved
Power State (PS)—R/W. These bits are used both to determine the current power
state of the SATA controller and to set a new power state.
00 = D0 state
1:0
11 = D3HOT state
When in the D3HOT state, the controller’s configuration space is available; however, the
I/O and memory spaces are not. Additionally, interrupts are blocked.
13.1.30 MSICI—Message Signaled Interrupt Capability
Identification Register (SATA–D31:F2)
Address Offset: 80h–81h Attribute: RO
Default Value: 7005h Size: 16 bits
Note: There is no support for MSI when the software is operating in legacy (IDE) mode when
AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make
sure that MSI is disabled.
Bits Description
Next Pointer (NEXT)—R/W. Indicates the next item in the list is the PCI power
management pointer.
BIOS may program this field to A8h indicating that the next item is Serial ATA Capability
Structure.
15:8
NOTE: Refer to the SGC.REGLOCK description in order to lock the register to become
RO.
This bit is not reset by a Function Level Reset
7:0 Capability ID (CID)—RO. Capabilities ID indicates MSI.
13.1.31 MSIMC—Message Signaled Interrupt Message
Control Register (SATA–D31:F2)
Address Offset: 82h–83h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Note: There is no support for MSI when the software is operating in legacy (IDE) mode when
AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make
sure that MSI is disabled.
Datasheet 579
SATA Controller Registers (D31:F2)
Bits Description
15:8 Reserved
7 64 Bit Address Capable (C64)—RO. Capable of generating a 32-bit message only.
Multiple Message Enable (MME)—RO.
= 000 (and MSIE is set), a single MSI message will be generated for all SATA ports, and
bits [15:0] of the message vector will be driven from MD[15:0].
For 6 port components:
Value Driven on MSI Memory Write
MME
Bits[15:3] Bit[2] Bit[1] Bit[0]
000,
MD[15:3] MD[2] MD[1] MD[0]
001, 010
Port 0: 0 Port 0: 0 Port 0: 0
Port 1: 0 Port 1: 0 Port 1: 1
Port 2: 0 Port 2: 1 Port 2: 0
011 MD[15:3]
Port 3: 0 Port 3: 1 Port 3: 1
Port 4: 1 Port 4: 0 Port 4: 0
Port 5: 1 Port 5: 0 Port 5: 1
6:4 For 4 port components:
Value Driven on MSI Memory Write
MME
Bits[15:3] Bit[2] Bit[1] Bit[0]
000,
MD[15:3] MD[2] MD[1] MD[0]
001, 010
Port 0: 0 Port 0: 0 Port 0: 0
Port 1: 0 Port 1: 0 Port 1: 1
011 MD[15:3]
Port 4: 1 Port 2: 0 Port 2: 0
Port 5: 1 Port 3: 0 Port 3: 1
All other MME values are reserved. If this field is set to one of these reserved values, the
results are undefined.
NOTE: The CCC interrupt is generated on unimplemented port (AHCI PI register bit
equal to 0). If CCC interrupt is disabled, no MSI shall be generated for the port
dedicated to the CCC interrupt. When CCC interrupt occurs, MD[2:0] is
dependant on CCC_CTL.INT (in addition to MME).
3:1 Multiple Message Capable (MMC)—RO. MMC is not supported.
MSI Enable (MSIE)—R/W /RO. If set, MSI is enabled and traditional interrupt pins are
not used to generate interrupts. This bit is R/W when SC.SCC is not 01h and is read-
only 0 when SCC is 01h. The CMD.ID bit has no effect on MSI.
0
NOTE: Software must clear this bit to 0 to disable MSI first before changing the number
of messages allocated in the MMC field. Software must also make sure this bit is
cleared to ‘0’ when operating in legacy mode (when GHC.AE = 0).
580 Datasheet
SATA Controller Registers (D31:F2)
13.1.32 MSIMA—Message Signaled Interrupt Message
Address Register (SATA–D31:F2)
Address Offset: 84h–87h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: There is no support for MSI when the software is operating in legacy (IDE) mode when
AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make
sure that MSI is disabled.
Bits Description
Address (ADDR)—R/W. Lower 32 bits of the system specified message address,
31:2
always DWord aligned.
1:0 Reserved
13.1.33 MSIMD—Message Signaled Interrupt Message
Data Register (SATA–D31:F2)
Address Offset: 88h–89h Attribute: R/W
Default Value: 0000h Size: 16 bits
Note: There is no support for MSI when the software is operating in legacy (IDE) mode when
AHCI is not enabled. Prior to switching from AHCI to IDE mode, software must make
sure that MSI is disabled.
Bits Description
Data (DATA)—R/W. This 16-bit field is programmed by system software if MSI is
enabled. Its content is driven onto the lower word of the data bus of the MSI memory
15:0 write transaction. When the MME field is set to ‘001’ or ‘010’, bit [0] and bits [1:0]
respectively of the MSI memory write transaction will be driven based on the source of
the interrupt rather than from MD[2:0]. See the description of the MME field.
Datasheet 581
SATA Controller Registers (D31:F2)
13.1.34 MAP—Address Map Register (SATA–D31:F2)
Address Offset: 90h Attribute: R/W, R/WO
Default Value: 0000h Size: 16 bits
Function Level Reset: No (Bits 7:5 and 13:8 only)
Bits Description
15:8 Reserved
SATA Mode Select (SMS)—R/W. Software programs these bits to control the mode in
which the SATA Controller should operate:
00b = IDE mode
01b = AHCI mode
10b = RAID mode
11b = Reserved
NOTES:
7:6 1. The SATA Function Device ID will change based on the value of this register.
2. When switching from AHCI or RAID mode to IDE mode, a 2 port SATA controller
(Device 31, Function 5) will be enabled.
3. SW shall not manipulate SMS during runtime operation; that is. the OS will not
do this. The BIOS may choose to switch from one mode to another during POST.
4. Not all register values may be available for a given SKU. See Section 1.3 for
details on storage controller capabilities.
These bits are not reset by Function Level Reset.
SATA Port-to-Controller Configuration (SC)—R/W. This bit changes the number of
SATA ports available within each SATA Controller.
0 = Up to 4 SATA ports are available for Controller 1 (Device 31 Function 2) with ports
[3:0] and up to 2 SATA ports are available for Controller 2 (Device 31 Function 5)
with ports [5:4].
5
1 = Up to 6 SATA ports are available for Controller 1 (Device 31 Function 2) with ports
[5:0] and no SATA ports are available for Controller 2 (Device 31 Function 5).
NOTE: This bit should be set to 1 in AHCI/RAID mode. This bit is not reset by Function
Level Reset.
4:0 Reserved
582 Datasheet
SATA Controller Registers (D31:F2)
13.1.35 PCS—Port Control and Status Register (SATA–D31:F2)
Address Offset: 92h–93h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Function Level Reset: No
By default, the SATA ports are set to the disabled state (bits [5:0] = 0). When enabled
by software, the ports can transition between the on, partial, and slumber states and
can detect devices. When disabled, the port is in the “off” state and cannot detect any
devices.
If an AHCI-aware or RAID enabled operating system is being booted, then system BIOS
shall insure that all supported SATA ports are enabled prior to passing control to the
OS. Once the AHCI aware OS is booted, it becomes the enabling/disabling policy owner
for the individual SATA ports. This is accomplished by manipulating a port’s PxSCTL and
PxCMD fields. Because an AHCI or RAID aware OS will typically not have knowledge of
the PxE bits and because the PxE bits act as master on/off switches for the ports, pre-
boot software must insure that these bits are set to 1 prior to booting the OS,
regardless as to whether or not a device is currently on the port.
Bits Description
OOB Retry Mode (ORM)—R/W.
15 0 = The SATA controller will not retry after an OOB failure
1 = The SATA controller will continue to retry after an OOB failure until successful
(infinite retry)
14 Reserved
Port 5 Present (P5P)—RO. The status of this bit may change at any time. This bit is
cleared when the port is disabled using P5E. This bit is not cleared upon surprise
13 removal of a device.
0 = No device detected.
1 = The presence of a device on Port 5 has been detected.
Port 4 Present (P4P)—RO. The status of this bit may change at any time. This bit is
cleared when the port is disabled using P4E. This bit is not cleared upon surprise
12 removal of a device.
0 = No device detected.
1 = The presence of a device on Port 4 has been detected.
Port 3 Present (P3P)—RO. The status of this bit may change at any time. This bit is
cleared when the port is disabled using P3E. This bit is not cleared upon surprise
removal of a device.
11 0 = No device detected.
1 = The presence of a device on Port 3 has been detected.
NOTE: Bit may be Reserved depending on if port is available in the given SKU. See
Section 1.3 for details if port is available.
Port 2 Present (P2P)—RO. The status of this bit may change at any time. This bit is
cleared when the port is disabled using P2E. This bit is not cleared upon surprise
removal of a device.
10 0 = No device detected.
1 = The presence of a device on Port 2 has been detected.
NOTE: Bit may be Reserved depending on if port is available in the given SKU. See
Section 1.3 for details if port is available.
Port 1 Present (P1P)—RO. The status of this bit may change at any time. This bit is
cleared when the port is disabled using P1E. This bit is not cleared upon surprise
9 removal of a device.
0 = No device detected.
1 = The presence of a device on Port 1 has been detected.
Datasheet 583
SATA Controller Registers (D31:F2)
Bits Description
Port 0 Present (P0P)—RO. The status of this bit may change at any time. This bit is
cleared when the port is disabled using P0E. This bit is not cleared upon surprise
8 removal of a device.
0 = No device detected.
1 = The presence of a device on Port 0 has been detected.
7:6 Reserved
Port 5 Enabled (P5E)—R/W / RO.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
5 can detect devices.
NOTES:
1. This bit takes precedence over P5CMD.SUD (offset ABAR+398h:bit 1)
2. If MAP.SC is 0, SCC is 01h, MAP.SPD[5] is 1h,or set to a PCIe* Port then this
bit will be read only 0.
Port 4 Enabled (P4E)—R/W / RO.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
4 can detect devices.
NOTE:
1. This bit takes precedence over P4CMD.SUD (offset ABAR+318h:bit 1)
2. If MAP.SC is 0, SCC is 01h, MAP.SPD[4] is 1h,or set to a PCIe Port then this bit
will be read only 0.
Port 3 Enabled (P3E)—R/W / RO.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
can detect devices.
3 NOTES:
1. This bit takes precedence over P3CMD.SUD (offset ABAR+298h:bit 1). When
MAP.SPD[3] is 1 this is reserved and is read-only 0.
2. Bit may be Reserved and RO depending on if port is available in the given SKU.
See Section 1.3 for details if port is available.
Port 2 Enabled (P2E)—R/W / RO.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 = Enabled. The port can transition between the on, partial, and slumber states and
can detect devices.
2 NOTES:
1. This bit takes precedence over P2CMD.SUD (offset ABAR+218h:bit 1). When
MAP.SPD[2] is 1 this is reserved and is read-only 0.
2. Bit may be Reserved and RO depending on if port is available in the given SKU.
See Section 1.3 for details if port is available.
Port 1 Enabled (P1E)—R/W / RO.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 1 = Enabled. The port can transition between the on, partial, and slumber states and
can detect devices.
NOTE: This bit takes precedence over P1CMD.SUD (offset ABAR+198h:bit 1). When
MAP.SPD[1] is 1 this is reserved and is read-only 0.
Port 0 Enabled (P0E)—R/W / RO.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
0 1 = Enabled. The port can transition between the on, partial, and slumber states and
can detect devices.
NOTE: This bit takes precedence over P0CMD.SUD (offset ABAR+118h:bit 1). When
MAP.SPD[0] is 1 this is reserved and is read-only 0.
584 Datasheet
SATA Controller Registers (D31:F2)
13.1.36 SCLKCG—SATA Clock Gating Control Register
Address Offset: 94h–97h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:30 Reserved
Port Clock Disable (PCD)—R/W.
0 = All clocks to the associated port logic will operate normally.
1 = The backbone clock driven to the associated port logic is gated and will not
toggle.
Bit 29: Port 5
Bit 28: Port 4
Bit 27: Port 3
29:24
BIt 26: Port 2
Bit 25: Port 1
Bit 24: Port 0
If a port is not available, software shall set the corresponding bit to 1. Software can
also set the corresponding bits to 1 on ports that are disabled.
Software cannot set the PCD [port x]=1 if the corresponding PCS.PxE=1 in either
Dev31Func2 or Dev31Func5 (dual controller IDE mode) or AHCI GHC.PI[x] = “1”.
23:0 Reserved
Datasheet 585
SATA Controller Registers (D31:F2)
13.1.37 SGC—SATA General Configuration Register
Address Offset: 9Ch–9Fh Attribute: R/W, R/WO
Default Value: 00000000h Size: 32 bits
Function Level Reset: No
Bit Description
Register Lock (REGLOCK)—R/WO.
0 = Will not lock CAP.CAP_PTR, PID.NEXT, MSICI.NEXT, or SATACR0.NEXT
1 = Setting this bit will lock CAP.CAP_PTR, PID.NEXT, MSICI.NEXT, and
31
SATACR0.NEXT. Once locked these register bits will become RO. BIOS is
requested to program this field prior to IOS handoff.
This bit is not reset by a Function Level Reset.
30:8 Reserved
7
(non-RAID
Capable Reserved
SKUs
Only)
Alternate ID Enable (AIE)—R/WO.
0 = Clearing this bit when in RAID mode, the SATA Controller located at Device 31:
Function 2 will report its Device ID as 2822h for all Desktop SKUs of the PCH
or 282Ah for all Mobile SKUs of the PCH. Clearing this bit is required for the
Intel Rapid Storage Technology driver (including the Microsoft* Windows
Vista* OS and later in-box version of the driver) to load on the platform. Intel
7 Smart Response Technology also requires that the bit be cleared in order to be
(RAID enabled on the platform.
Capable 1 = Setting this bit when in RAID mode, the SATA Controller located at Device 31:
SKUs Function 2 will report its Device ID as called out in the table below for Desktop
Only) SKUs or 1E07h for all Mobile SKUs of the chipset. This setting will prevent the
Intel Rapid Storage Technology driver (including the Microsoft Windows* OS
in-box version of the driver) from loading on the platform. During the Microsoft
Windows OS installation, the user will be required to “load” (formerly done by
pressing the F6 button on the keyboard) the appropriate RAID storage driver
that is enabled by this setting.
This field is reset by PLTRST#. BIOS is required to reprogram the value of this
bit after resuming from S3, S4 and S5.
6 Alternate ID Select (AIES)—R/WO. BIOS must write to this bit field.
5 Reserved - BIOS may write to this field.
4:1 Reserved
SATA 4-port All Master Configuration Indicator (SATA4PMIND)—RO.
0 = Normal configuration.
1 = Two IDE Controllers are implemented, each supporting two ports for a Primary
0 Master and a Secondary Master.
NOTE: BIOS must also make sure that corresponding port clocks are gated (using
SCLKCG configuration register).
586 Datasheet
SATA Controller Registers (D31:F2)
13.1.38 SATACR0—SATA Capability Register 0 (SATA–D31:F2)
Address Offset: A8h–ABh Attribute: RO, R/WO
Default Value: 0010B012h Size: 32 bits
Function Level Reset: No (Bits 15:8 only)
Note: This register is read-only 0 when SCC is 01h.
Bit Description
31:24 Reserved
Major Revision (MAJREV)—RO. Major revision number of the SATA Capability Pointer
23:20
implemented.
Minor Revision (MINREV)—RO. Minor revision number of the SATA Capability Pointer
19:16
implemented.
Next Capability Pointer (NEXT)—R/WO. Points to the next capability structure.
15:8
These bits are not reset by Function Level Reset.
Capability ID (CAP)—RW. The value 00h indicates the final item in the SATA
Capability List.
7:0
NOTE: Refer to the SGC.REGLOCK description in order to lock the register to become
RO.
13.1.39 SATACR1—SATA Capability Register 1 (SATA–D31:F2)
Address Offset: ACh–AFh Attribute: RO
Default Value: 00000048h Size: 32 bits
Note: When SCC is 01h, this register is read-only 0.
Bit Description
31:16 Reserved
BAR Offset (BAROFST)—RO. Indicates the offset into the BAR where the Index/Data
pair are located (in DWord granularity). The Index and Data I/O registers are located at
offset 10h within the I/O space defined by LBAR. A value of 004h indicates offset 10h.
000h = 0h offset
15:4 001h = 4h offset
002h = 8h offset
003h = Bh offset
004h = 10h offset
...
FFFh = 3FFFh offset (max 16KB)
BAR Location (BARLOC)—RO. Indicates the absolute PCI Configuration Register
address of the BAR containing the Index/Data pair (in DWord granularity). The Index
and Data I/O registers reside within the space defined by LBAR in the SATA controller. A
value of 8h indicates offset 20h, which is LBAR.
0000 – 0011b = reserved
0100b = 10h => BAR0
3:0 0101b = 14h => BAR1
0110b = 18h => BAR2
0111b = 1Ch => BAR3
1000b = 20h => LBAR
1001b = 24h => BAR5
1010–1110b = Reserved
1111b = Index/Data pair in PCI Configuration space. This is not supported in the PCH.
Datasheet 587
SATA Controller Registers (D31:F2)
13.1.40 FLRCID—FLR Capability Identification Register (SATA–
D31:F2)
Address Offset: B0–B1h Attribute: RO
Default Value: 0009h Size: 16 bits
Bit Description
15:8 Next Capability Pointer—RO. 00h indicates the final item in the capability list.
Capability ID—RO. The value of this field depends on the FLRCSSEL (RCBA+3410h:bit
12) bit.
FLRCSSEL Capability ID
7:0 (RCBA+3410h:bit 12) Value Register Value
0b 13h
1b 00h (Vendor Specific)
13.1.41 FLRCLV—FLR Capability Length and Version Register
(SATA–D31:F2)
Address Offset: B2–B3h Attribute: RO, R/WO
Default Value: xx06h Size: 16 bits
Function Level Reset: No (Bit 9:8 Only when FLRCSSEL = 0)
When FLRCSSEL (RCBA+3410h:bit 12) = 1, this register is RO.
Bit Description
15:10 Reserved
FLR Capability—R/WO.
9 1 = Support for Function Level reset.
This bit is not reset by the Function Level Reset.
TXP Capability—R/WO.
8 1 = Support for Transactions Pending (TXP) bit. TXP must be supported if FLR is
supported.
Vendor-Specific Capability ID—RO. This field indicates the number of bytes of this
7:0 Vendor Specific capability as required by the PCI specification. It has the value of 06h
for the FLR capability.
588 Datasheet
SATA Controller Registers (D31:F2)
13.1.42 FLRC—FLR Control Register (SATA–D31:F2)
Address Offset: B4h–B5h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
When FLRCSSEL (RCBA+3410h:bit 12) = 1, this register is RO.
Bit Description
15:9 Reserved
Transactions Pending (TXP)—RO.
8 0 = Controller has received all non-posted requests.
1 = Controller has issued non-posted requests which has not been completed.
7:1 Reserved
Initiate FLR—R/W. Used to initiate FLR transition. A write of 1 indicates FLR transition.
0 Since hardware must not respond to any cycles till FLR completion the value read by
software from this bit is 0.
13.1.43 ATC—APM Trapping Control Register (SATA–D31:F2)
Address Offset: C0h Attribute: R/W
Default Value: 00h Size: 8 bits
Function Level Reset: No
.
Bit Description
7:4 Reserved
Secondary Slave Trap (SST)—R/W. Enables trapping and SMI# assertion on legacy
3 I/O accesses to 170h–177h and 376h. The active device on the secondary interface
must be device 1 for the trap and/or SMI# to occur.
Secondary Master Trap (SPT)—R/W. Enables trapping and SMI# assertion on legacy
2 I/O accesses to 170h-177h and 376h. The active device on the secondary interface
must be device 0 for the trap and/or SMI# to occur.
Primary Slave Trap (PST)—R/W. Enables trapping and SMI# assertion on legacy I/O
1 accesses to 1F0h–1F7h and 3F6h. The active device on the primary interface must be
device 1 for the trap and/or SMI# to occur.
Primary Master Trap (PMT)—R/W. Enables trapping and SMI# assertion on legacy I/
0 O accesses to 1F0h–1F7h and 3F6h. The active device on the primary interface must be
device 0 for the trap and/or SMI# to occur.
Datasheet 589
SATA Controller Registers (D31:F2)
13.1.44 ATS—APM Trapping Status Register (SATA–D31:F2)
Address Offset: C4h Attribute: R/WC
Default Value: 00h Size: 8 bits
Function Level Reset: No
.
Bit Description
7:4 Reserved
Secondary Slave Trap (SST)—R/WC. Indicates that a trap occurred to the secondary
3
slave device.
Secondary Master Trap (SPT)—R/WC. Indicates that a trap occurred to the
2
secondary master device.
Primary Slave Trap (PST)—R/WC. Indicates that a trap occurred to the primary slave
1
device.
Primary Master Trap (PMT)—R/WC. Indicates that a trap occurred to the primary
0
master device.
13.1.45 SP—Scratch Pad Register (SATA–D31:F2)
Address Offset: D0h Attribute: R/W
Default Value: 00000000h Size: 32 bits
.
Bit Description
Data (DT)—R/W. This is a read/write register that is available for software to use. No
31:0
hardware action is taken on this register.
590 Datasheet
SATA Controller Registers (D31:F2)
13.1.46 BFCS—BIST FIS Control/Status Register (SATA–D31:F2)
Address Offset: E0h–E3h Attribute: R/W, R/WC
Default Value: 00000000h Size: 32 bits
Bits Description
31:16 Reserved
Port 5 BIST FIS Initiate (P5BFI)—R/W. When a rising edge is detected on this bit
field, the PCH initiates a BIST FIS to the device on Port 5, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 5 is present and ready (not partial/slumber
state). After a BIST FIS is successfully completed, software must disable and re-
15
enable the port using the PxE bits at offset 92h prior to attempting additional BIST
FISs or to return the PCH to a normal operational mode. If the BIST FIS fails to
complete, as indicated by the BFF bit in the register, then software can clear then set
the P5BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS
eventually completes successfully.
Port 4 BIST FIS Initiate (P4BFI)—R/W. When a rising edge is detected on this bit
field, the PCH initiates a BIST FIS to the device on Port 4, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 4 is present and ready (not partial/slumber
state). After a BIST FIS is successfully completed, software must disable and re-
14
enable the port using the PxE bits at offset 92h prior to attempting additional BIST
FISs or to return the PCH to a normal operational mode. If the BIST FIS fails to
complete, as indicated by the BFF bit in the register, then software can clear then set
the P4BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS
eventually completes successfully.
Port 3 BIST FIS Initiate (P3BFI)—R/W. When a rising edge is detected on this bit
field, the PCH initiates a BIST FIS to the device on Port 3, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 3 is present and ready (not partial/slumber
state). After a BIST FIS is successfully completed, software must disable and re-
enable the port using the PxE bits at offset 92h prior to attempting additional BIST
13 FISs or to return the PCH to a normal operational mode. If the BIST FIS fails to
complete, as indicated by the BFF bit in the register, then software can clear then set
the P3BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS
eventually completes successfully.
NOTE: Bit may be Reserved depending on if port is available in the given SKU. See
Section 1.3 for details if port is available.
Port 2 BIST FIS Initiate (P2BFI)—R/W. When a rising edge is detected on this bit
field, the PCH initiates a BIST FIS to the device on Port 2, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 2 is present and ready (not partial/slumber
state). After a BIST FIS is successfully completed, software must disable and re-
enable the port using the PxE bits at offset 92h prior to attempting additional BIST
12 FISes or to return the PCH to a normal operational mode. If the BIST FIS fails to
complete, as indicated by the BFF bit in the register, then software can clear then set
the P2BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS
eventually completes successfully.
NOTE: Bit may be Reserved depending on if port is available in the given SKU. See
Section 1.3 for details if port is available.
Datasheet 591
SATA Controller Registers (D31:F2)
Bits Description
BIST FIS Successful (BFS)—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set any time a BIST FIS transmitted by PCH receives an R_OK
11
completion status from the device.
NOTE: This bit must be cleared by software prior to initiating a BIST FIS.
BIST FIS Failed (BFF)—R/WC.
0 = Software clears this bit by writing a 1 to it.
10 1 = This bit is set any time a BIST FIS transmitted by PCH receives an R_ERR
completion status from the device.
NOTE: This bit must be cleared by software prior to initiating a BIST FIS.
Port 1 BIST FIS Initiate (P1BFI)—R/W. When a rising edge is detected on this bit
field, the PCH initiates a BIST FIS to the device on Port 1, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 1 is present and ready (not partial/slumber
state). After a BIST FIS is successfully completed, software must disable and re-
9
enable the port using the PxE bits at offset 92h prior to attempting additional BIST
FISes or to return the PCH to a normal operational mode. If the BIST FIS fails to
complete, as indicated by the BFF bit in the register, then software can clear then set
the P1BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS
eventually completes successfully.
Port 0 BIST FIS Initiate (P0BFI)—R/W. When a rising edge is detected on this bit
field, the PCH initiates a BIST FIS to the device on Port 0, using the parameters
specified in this register and the data specified in BFTD1 and BFTD2. The BIST FIS
will only be initiated if a device on Port 0 is present and ready (not partial/slumber
state). After a BIST FIS is successfully completed, software must disable and re-
8
enable the port using the PxE bits at offset 92h prior to attempting additional BIST
FISes or to return the PCH to a normal operational mode. If the BIST FIS fails to
complete, as indicated by the BFF bit in the register, then software can clear then set
the P0BFI bit to initiate another BIST FIS. This can be retried until the BIST FIS
eventually completes successfully.
BIST FIS Parameters (BFP)—R/W. These 6 bits form the contents of the upper 6
bits of the BIST FIS Pattern Definition in any BIST FIS transmitted by the PCH. This
field is not port specific – its contents will be used for any BIST FIS initiated on port 0,
port 1, port 2, or port 3. The specific bit definitions are:
Bit 7: T – Far End Transmit mode
7:2 Bit 6: A – Align Bypass mode
Bit 5: S – Bypass Scrambling
Bit 4: L – Far End Retimed Loopback
Bit 3: F – Far End Analog Loopback
Bit 2: P – Primitive bit for use with Transmit mode
1:0 Reserved
592 Datasheet
SATA Controller Registers (D31:F2)
13.1.47 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2)
Address Offset: E4h–E7h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bits Description
BIST FIS Transmit Data 1—R/W. The data programmed into this register will form the
contents of the second DWord of any BIST FIS initiated by the PCH. This register is not
port specific—its contents will be used for BIST FIS initiated on any port. Although the
31:0 2nd and 3rd DWs of the BIST FIS are only meaningful when the “T” bit of the BIST FIS
is set to indicate “Far-End Transmit mode”, this register’s contents will be transmitted as
the BIST FIS 2nd DW regardless of whether or not the “T” bit is indicated in the BFCS
register (D31:F2:E0h).
13.1.48 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2)
Address Offset: E8h–EBh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bits Description
BIST FIS Transmit Data 2—R/W. The data programmed into this register will form the
contents of the third DWord of any BIST FIS initiated by the PCH. This register is not
port specific—its contents will be used for BIST FIS initiated on any port. Although the
31:0 2nd and 3rd DWs of the BIST FIS are only meaningful when the “T” bit of the BIST FIS
is set to indicate “Far-End Transmit mode”, this register’s contents will be transmitted as
the BIST FIS 3rd DW regardless of whether or not the “T” bit is indicated in the BFCS
register (D31:F2:E0h).
Datasheet 593
SATA Controller Registers (D31:F2)
13.2 Bus Master IDE I/O Registers (D31:F2)
The bus master IDE function uses 16 bytes of I/O space, allocated using the BAR
register, located in D31:F2 Configuration space, offset 20h. All bus master IDE I/O
space registers can be accessed as byte, word, or DWord quantities. Reading reserved
bits returns an indeterminate, inconsistent value, and writes to reserved bits have no
affect (but should not be attempted). These registers are only used for legacy
operation. Software must not use these registers when running AHCI. All I/O registers
are reset by Function Level Reset. The register address I/O map is shown in Table 13-2.
Table 13-2. Bus Master IDE I/O Register Address Map
BAR+
Mnemonic Register Default Attribute
Offset
00h BMICP Command Register Primary 00h R/W
01h — Reserved — RO
R/W, R/WC,
02h BMISP Bus Master IDE Status Register Primary 00h
RO
03h — Reserved — RO
04h– Bus Master IDE Descriptor Table Pointer
BMIDP xxxxxxxxh R/W
07h Primary
08h BMICS Command Register Secondary 00h R/W
09h — Reserved — RO
R/W, R/WC,
0Ah BMISS Bus Master IDE Status Register Secondary 00h
RO
0Bh — Reserved — RO
0Ch– Bus Master IDE Descriptor Table Pointer
BMIDS xxxxxxxxh R/W
0Fh Secondary
10h AIR AHCI Index Register 00000000h R/W, RO
14h AIDR AHCI Index Data Register xxxxxxxxh R/W
594 Datasheet
SATA Controller Registers (D31:F2)
13.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2)
Address Offset: Primary: BAR + 00h Attribute: R/W
Secondary: BAR + 08h
Default Value: 00h Size: 8 bits
Bit Description
7:4 Reserved. Returns 0.
Read / Write Control (R/WC)—R/W. This bit sets the direction of the bus master
transfer. This bit must NOT be changed when the bus master function is active.
3
0 = Memory reads
1 = Memory writes
2:1 Reserved. Returns 0.
Start/Stop Bus Master (START)—R/W.
0 = All state information is lost when this bit is cleared. Master mode operation cannot
be stopped and then resumed. If this bit is reset while bus master operation is still
active (that is, the Bus Master IDE Active bit (D31:F2:BAR + 02h, bit 0) of the Bus
Master IDE Status register for that IDE channel is set) and the drive has not yet
finished its data transfer (the Interrupt bit in the Bus Master IDE Status register for
that IDE channel is not set), the bus master command is said to be aborted and
data transferred from the drive may be discarded instead of being written to
system memory.
1 = Enables bus master operation of the controller. Bus master operation does not
actually start unless the Bus Master Enable bit (D31:F2:04h, bit 2) in PCI
0 configuration space is also set. Bus master operation begins when this bit is
detected changing from 0 to 1. The controller will transfer data between the IDE
device and memory only when this bit is set. Master operation can be halted by
writing a 0 to this bit.
NOTE: This bit is intended to be cleared by software after the data transfer is
completed, as indicated by either the Bus Master IDE Active bit being cleared or
the Interrupt bit of the Bus Master IDE Status register for that IDE channel
being set, or both. Hardware does not clear this bit automatically. If this bit is
cleared to 0 prior to the DMA data transfer being initiated by the drive in a
device to memory data transfer, then the PCH will not send DMAT to terminate
the data transfer. SW intervention (such as, sending SRST) is required to reset
the interface in this condition.
Datasheet 595
SATA Controller Registers (D31:F2)
13.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2)
Address Offset: Primary: BAR + 02h Attribute: R/W, R/WC, RO
Secondary: BAR + 0Ah
Default Value: 00h Size: 8 bits
Bit Description
Simplex Only—RO.
0 = Both bus master channels (primary and secondary) can be operated independently
7
and can be used at the same time.
1 = Only one channel may be used at the same time.
Drive 1 DMA Capable—R/W.
0 = Not Capable.
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that
6
drive 1 for this channel is capable of DMA transfers, and that the controller has
been initialized for optimum performance. The PCH does not use this bit. It is
intended for systems that do not attach BMIDE to the PCI bus.
Drive 0 DMA Capable—R/W.
0 = Not Capable
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that
5
drive 0 for this channel is capable of DMA transfers, and that the controller has
been initialized for optimum performance. The PCH does not use this bit. It is
intended for systems that do not attach BMIDE to the PCI bus.
4:3 Reserved. Returns 0.
Interrupt—R/WC.
0 = Software clears this bit by writing a 1 to it.
2
1 = Set when a device FIS is received with the ‘I’ bit set, provided that software has not
disabled interrupts using the IEN bit of the Device Control Register.
Error—R/WC.
0 = Software clears this bit by writing a 1 to it.
1
1 = This bit is set when the controller encounters a target abort or master abort when
transferring data on PCI.
Bus Master IDE Active (ACT)—RO.
0 = This bit is cleared by the PCH when the last transfer for a region is performed,
where EOT for that region is set in the region descriptor. It is also cleared by the
PCH when the Start Bus Master bit (D31:F2:BAR+ 00h, bit 0) is cleared in the
0
Command register. When this bit is read as a 0, all data transferred from the drive
during the previous bus master command is visible in system memory, unless the
bus master command was aborted.
1 = Set by the PCH when the Start bit is written to the Command register.
596 Datasheet
SATA Controller Registers (D31:F2)
13.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F2)
Address Offset: Primary: BAR + 04h–07h Attribute: R/W
Secondary: BAR + 0Ch–0Fh
Default Value: All bits undefined Size: 32 bits
Bit Description
Address of Descriptor Table (ADDR)—R/W. The bits in this field correspond to bits
[31:2] of the memory location of the Physical Region Descriptor (PRD). The Descriptor
31:2
Table must be DWord-aligned. The Descriptor Table must not cross a 64-K boundary in
memory.
1:0 Reserved
13.2.4 AIR—AHCI Index Register (D31:F2)
Address Offset: Primary: BAR + 10h Attribute: R/W
Default Value: 00000000h Size: 32 bits
This register is available only when SCC is not 01h.
Bit Description
31:11 Reserved
Index (INDEX)—R/W. This Index register is used to select the DWord offset of the
10:2 Memory Mapped AHCI register to be accessed. A DWord, Word or Byte access is
specified by the active byte enables of the I/O access to the Data register.
1:0 Reserved
13.2.5 AIDR—AHCI Index Data Register (D31:F2)
Address Offset: Primary: BAR + 14h Attribute: R/W
Default Value: All bits undefined Size: 32 bits
This register is available only when SCC is not 01h.
Bit Description
Data (DATA)—R/W. This Data register is a “window” through which data is read or
written to the AHCI memory mapped registers. A read or write to this Data register
triggers a corresponding read or write to the memory mapped register pointed to by
the Index register. The Index register must be setup prior to the read or write to this
31:0 Data register.
A physical register is not actually implemented as the data is actually stored in the
memory mapped registers.
Since this is not a physical register, the “default” value is the same as the default value
of the register pointed to by Index.
Datasheet 597
SATA Controller Registers (D31:F2)
13.3 Serial ATA Index/Data Pair Superset Registers
All of these I/O registers are in the core well. They are exposed only when SCC is 01h
(that is, IDE programming interface).
These are Index/Data Pair registers that are used to access the SerialATA superset
registers (SerialATA Status (PxSSTS), SerialATA Control (PxSCTL) and SerialATA Error
(PxSERR)). The I/O space for these registers is allocated through SIDPBA. Locations
with offset from 08h to 0Fh are reserved for future expansion. Software-write
operations to the reserved locations will have no effect while software-read operations
to the reserved locations will return 0.
Offset Mnemonic Register
00h–03h SINDEX Serial ATA Index
04h–07h SDATA Serial ATA Data
08h–0Ch — Reserved
0Ch–0Fh — Reserved
13.3.1 SINDX—Serial ATA Index Register (D31:F2)
Address Offset: SIDPBA + 00h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:16 Reserved
Port Index (PIDX)—R/W. This Index field is used to specify the port of the SATA
controller at which the port-specific SSTS, SCTL, and SERR registers are located.
00h = Primary Master (Port 0)
15.8 01h = Primary Slave (Port 2)
02h = Secondary Master (Port 1)
03h = Secondary Slave (Port 3)
All other values are Reserved.
Register Index (RIDX)—R/W. This index field is used to specify one out of three
registers currently being indexed into. These three registers are the Serial ATA superset
SStatus, SControl and SError memory registers and are port specific, hence for this
SATA controller, there are four sets of these registers. Refer to Section 13.4.2.10,
Section 13.4.2.11, and Section 13.4.2.12 for definitions of the SStatus, SControl and
7:0 SError registers.
00h = SSTS
01h = SCTL
02h = SERR
All other values are Reserved.
598 Datasheet
SATA Controller Registers (D31:F2)
13.3.2 SDATA—Serial ATA Data Register (D31:F2)
Address Offset: SIDPBA + 04h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Data (DATA)—R/W. This Data register is a “window” through which data is read or
written to from the register pointed to by the Serial ATA Index (SINDX) register above.
A physical register is not actually implemented as the data is actually stored in the
31:0 memory mapped registers.
Since this is not a physical register, the “default” value is the same as the default value
of the register pointed to by SINDX.RIDX field.
13.3.2.1 PxSSTS—Serial ATA Status Register (D31:F2)
Address Offset: Attribute: RO
Default Value: 00000000h Size: 32 bits
SDATA when SINDX.RIDX is 00h. This is a 32-bit register that conveys the current state
of the interface and host. The PCH updates it continuously and asynchronously. When
the PCH transmits a COMRESET to the device, this register is updated to its reset
values.
Bit Description
31:12 Reserved
Interface Power Management (IPM)—RO. Indicates the current interface state:
Value Description
0h Device not present or communication not established
1h Interface in active state
11:8
2h Interface in PARTIAL power management state
6h Interface in SLUMBER power management state
All other values reserved.
Current Interface Speed (SPD)—RO. Indicates the negotiated interface
communication speed.
Value Description
0h Device not present or communication not established
1h Generation 1 communication rate negotiated
7:4 2h Generation 2 communication rate negotiated
3h Generation 3 communication rate negotiated
All other values reserved
The PCH Supports Generation 1 communication rates (1.5 Gb/s), Gen 2 rates
(3.0 Gb/s) and Gen 3 rates (6.0Gb/s)
Device Detection (DET)—RO. Indicates the interface device detection and Phy state:
Value Description
0h No device detected and Phy communication not established
1h Device presence detected but Phy communication not established
3:0
3h Device presence detected and Phy communication established
Phy in offline mode as a result of the interface being disabled or
4h
running in a BIST loopback mode
All other values reserved.
Datasheet 599
SATA Controller Registers (D31:F2)
13.3.2.2 PxSCTL—Serial ATA Control Register (D31:F2)
Address Offset: Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
SDATA when SINDX.RIDX is 01h. This is a 32-bit read-write register by which software
controls SATA capabilities. Writes to the SControl register result in an action being
taken by the PCH or the interface. Reads from the register return the last value written
to it.
Bit Description
31:20 Reserved
19:16 Port Multiplier Port (PMP)—R/W. This field is not used by AHCI.
15:12 Select Power Management (SPM)—R/W. This field is not used by AHCI.
Interface Power Management Transitions Allowed (IPM)—R/W. Indicates which
power states the PCH is allowed to transition to:
Value Description
0h No interface restrictions
11:8
1h Transitions to the PARTIAL state disabled
2h Transitions to the SLUMBER state disabled
3h Transitions to both PARTIAL and SLUMBER states disabled
All other values reserved
Speed Allowed (SPD)—R/W. Indicates the highest allowable speed of the interface.
This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field.
Value Description
0h No speed negotiation restrictions
1h Limit speed negotiation to Generation 1 communication rate
7:4
2h Limit speed negotiation to Generation 2 communication rate
3h Limit speed negotiation to Generation 3 communication rate
All other values reserved.
The PCH Supports Generation 1 communication rates (1.5 Gb/s), Gen 2 rates
(3.0 Gb/s) and Gen 3 rates (6.0Gb/s)
Device Detection Initialization (DET)—R/W. Controls the PCH’s device detection
and interface initialization.
Value Description
0h No device detection or initialization action requested
Perform interface communication initialization sequence to establish
communication. This is functionally equivalent to a hard reset and
1h
results in the interface being reset and communications re-
3:0 initialized
4h Disable the Serial ATA interface and put Phy in offline mode
All other values reserved.
When this field is written to a 1h, the PCH initiates COMRESET and starts the
initialization process. When the initialization is complete, this field shall remain 1h until
set to another value by software.
This field may only be changed to 1h or 4h when PxCMD.ST is 0. Changing this field
while the PCH is running results in undefined behavior.
600 Datasheet
SATA Controller Registers (D31:F2)
13.3.2.3 PxSERR—Serial ATA Error Register (D31:F2)
Address Offset: Attribute: R/WC
Default Value: 00000000h Size: 32 bits
SDATA when SINDx.RIDX is 02h.
Bits 26:16 of this register contains diagnostic error information for use by diagnostic
software in validating correct operation or isolating failure modes. Bits 11:0 contain
error information used by host software in determining the appropriate response to the
error condition. If one or more of bits 11:8 of this register are set, the controller will
stop the current transfer.
Bit Description
31:27 Reserved
Exchanged (X): When set to one, this bit indicates that a change in device presence
26 has been detected since the last time this bit was cleared. This bit shall always be set to
1 anytime a COMINIT signal is received. This bit is reflected in the P0IS.PCS bit.
Unrecognized FIS Type (F): Indicates that one or more FISs were received by the
25
Transport layer with good CRC, but had a type field that was not recognized.
Transport state transition error (T): Indicates that an error has occurred in the
24 transition from one state to another within the Transport layer since the last time this
bit was cleared.
Link Sequence Error (S): Indicates that one or more Link state machine error
23 conditions was encountered. The Link Layer state machine defines the conditions under
which the link layer detects an erroneous transition.
Handshake (H). Indicates that one or more R_ERR handshake response was received
in response to frame transmission. Such errors may be the result of a CRC error
22
detected by the recipient, a disparity or 8b/10b decoding error, or other error condition
leading to a negative handshake on a transmitted frame.
21 CRC Error (C). Indicates that one or more CRC errors occurred with the Link Layer.
20 Disparity Error (D). This field is not used by AHCI.
10b to 8b Decode Error (B). Indicates that one or more 10b to 8b decoding errors
19
occurred.
18 Comm Wake (W). Indicates that a Comm Wake signal was detected by the Phy.
17 Phy Internal Error (I). Indicates that the Phy detected some internal error.
PhyRdy Change (N): When set to 1, this bit indicates that the internal PhyRdy signal
changed state since the last time this bit was cleared. In the PCH, this bit will be set
16 when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this bit is then reflected in
the PxIS.PRCS interrupt status bit and an interrupt will be generated if enabled.
Software clears this bit by writing a 1 to it.
15:12 Reserved
Internal Error (E). The SATA controller failed due to a master or target abort when
11
attempting to access system memory.
Protocol Error (P). A violation of the Serial ATA protocol was detected.
10
NOTE: The PCH does not set this bit for all protocol violations that may occur on the
SATA link.
Datasheet 601
SATA Controller Registers (D31:F2)
Bit Description
Persistent Communication or Data Integrity Error (C). A communication error
that was not recovered occurred that is expected to be persistent. Persistent
9
communications errors may arise from faulty interconnect with the device, from a
device that has been removed or has failed, or a number of other causes.
Transient Data Integrity Error (T): A data integrity error occurred that was not
8
recovered by the interface.
7:2 Reserved
Recovered Communications Error (M). Communications between the device and
host was temporarily lost but was re-established. This can arise from a device
1 temporarily being removed, from a temporary loss of Phy synchronization, or from
other causes and may be derived from the PhyNRdy signal between the Phy and Link
layers.
Recovered Data Integrity Error (I). A data integrity error occurred that was
0
recovered by the interface through a retry operation or other recovery action.
602 Datasheet
SATA Controller Registers (D31:F2)
13.4 AHCI Registers (D31:F2)
Note: These registers are AHCI-specific and available when the PCH is properly configured.
The Serial ATA Status, Control, and Error registers are special exceptions and may be
accessed on all PCH components if properly configured; see Section 13.3 for details.
The memory mapped registers within the SATA controller exist in non-cacheable
memory space. Additionally, locked accesses are not supported. If software attempts to
perform locked transactions to the registers, indeterminate results may occur. Register
accesses shall have a maximum size of 64-bits; 64-bit access must not cross an 8-byte
alignment boundary. All memory registers are reset by Function Level Reset unless
specified otherwise.
The registers are broken into two sections – generic host control and port control. The
port control registers are the same for all ports, and there are as many registers banks
as there are ports.
Table 13-3. AHCI Register Address Map
ABAR + Offset Mnemonic Register
00–1Fh GHC Generic Host Control
20h–FFh — Reserved
100h–17Fh P0PCR Port 0 port control registers
180h–1FFh P1PCR Port 1 port control registers
Port 2 port control registers
NOTE: Registers may be Reserved depending on if port is
200h–27Fh P2PCR
available in the given SKU. See Section 1.3 for details if
port is available.
Port 3 port control registers
NOTE: Registers may be Reserved depending on if port is
280h–2FFh P3PCR
available in the given SKU. See Section 1.3 for details if
port is available.
300h–37Fh P4PCR Port 4 port control registers
380h–3FFh P5PCR Port 5 port control registers
Datasheet 603
SATA Controller Registers (D31:F2)
13.4.1 AHCI Generic Host Control Registers (D31:F2)
Table 13-4. Generic Host Controller Register Address Map
ABAR +
Mnemonic Register Default Attribute
Offset
FF22FFC2h
(desktop)
00h–03h CAP Host Capabilities R/WO, RO
DE127F03h
(mobile)
04h–07h GHC Global PCH Control 00000000h R/W, RO
08h–0Bh IS Interrupt Status 00000000h R/WC
0Ch–0Fh PI Ports Implemented 00000000h R/WO, RO
10h–13h VS AHCI Version 00010300h RO
1Ch–1Fh EM_LOC Enclosure Management Location 01600002h RO
R/W, R/WO,
20h–23h EM_CTRL Enclosure Management Control 07010000h
RO
24h–27h CAP2 HBA Capabilities Extended 00000004h RO
®
C8h–C9h RSTF Intel RST Feature Capabilities 003Fh R/WO
13.4.1.1 CAP—Host Capabilities Register (D31:F2)
Address Offset: ABAR + 00h–03h Attribute: R/WO, RO
Default Value: FF22FFC2h (Desktop) Size: 32 bits
DE127F03h (Mobile)
Function Level Reset:No
All bits in this register that are R/WO are reset only by PLTRST#.
Bit Description
Supports 64-bit Addressing (S64A)—RO. Indicates that the SATA controller can
31 access 64-bit data structures. The 32-bit upper bits of the port DMA Descriptor, the
PRD Base, and each PRD entry are read/write.
Supports Command Queue Acceleration (SCQA)—R/WO. When set to 1,
indicates that the SATA controller supports SATA command queuing using the DMA
30
Setup FIS. The PCH handles DMA Setup FISes natively, and can handle auto-
activate optimization through that FIS.
Supports SNotification Register (SSNTF)—R/WO. The PCH SATA Controller
29
does not support the SNotification register. BIOS must write a 0 to this field.
Supports Mechanical Presence Switch (SMPS)—R/WO. When set to 1,
indicates whether the SATA controller supports mechanical presence switches on its
ports for use in Hot-Plug operations. This value is loaded by platform BIOS prior to
28 OS initialization.
If this bit is set, BIOS must also map the SATAGP pins to the SATA controller
through GPIO space.
Supports Staggered Spin-up (SSS)—R/WO. Indicates whether the SATA
controller supports staggered spin-up on its ports, for use in balancing power
27 spikes. This value is loaded by platform BIOS prior to OS initialization.
0 = Staggered spin-up not supported.
1 = Staggered spin-up supported.
604 Datasheet
SATA Controller Registers (D31:F2)
Bit Description
Supports Aggressive Link Power Management (SALP)—R/WO.
26 0 = Software shall treat the PxCMD.ALPE and PxCMD.ASP bits as reserved.
1 = The SATA controller supports auto-generating link requests to the partial or
slumber states when there are no commands to process.
Supports Activity LED (SAL)—RO. Indicates that the SATA controller supports a
25
single output pin (SATALED#) which indicates activity.
Supports Command List Override (SCLO)—R/WO. When set to 1, indicates that
the Controller supports the PxCMD.CLO bit and its associated function. When
24 cleared to 0, the Controller is not capable of clearing the BSY and DRQ bits in the
Status register in order to issue a software reset if these bits are still set from a
previous operation.
Interface Speed Support (ISS)—R/WO. Indicates the maximum speed the SATA
controller can support on its ports.
1h = 1.5 Gb/s; 2h =3 Gb/s; 3h = 6 Gb/s
23:20 The default of this field is dependent upon the PCH SKU. If at least one PCH SATA
port supports 6 Gb/s, the default will be 3h. If no PCH SATA ports support 6 Gb/s,
then the default will be 2h and writes of 3h will be ignored by the PCH. See
Section 1.3 for details on 6 Gb/s port availability.
Supports Non-Zero DMA Offsets (SNZO)—RO. Reserved, as per the AHCI
19
Revision 1.3 specification
Supports AHCI Mode Only (SAM)—RO. The SATA controller may optionally
support AHCI access mechanism only.
18
0 = SATA controller supports both IDE and AHCI Modes
1 = SATA controller supports AHCI Mode Only
17:16 Reserved
PIO Multiple DRQ Block (PMD)—RO. Hardwired to 1. The SATA controller
15
supports PIO Multiple DRQ Command Block
Slumber State Capable (SSC)—R/WO. When set to 1, the SATA controller
14
supports the slumber state.
Partial State Capable (PSC)—R/WO. When set to 1, the SATA controller supports
13
the partial state.
Number of Command Slots (NCS)—RO. Hardwired to 1Fh to indicate support for
12:8
32 slots.
Command Completion Coalescing Supported (CCCS)—R/WO.
7 0 = Command Completion Coalescing Not Supported
1 = Command Completion Coalescing Supported
Enclosure Management Supported (EMS)—R/WO.
6 0 = Enclosure Management Not Supported
1 = Enclosure Management Supported
Supports External SATA (SXS)—R/WO.
0 = External SATA is not supported on any ports
5 1 = External SATA is supported on one or more ports
When set, software can examine each SATA port’s Command Register (PxCMD) to
determine which port is routed externally.
Number of Ports (NPS)—RO. Indicates number of supported ports. The number
of ports indicated in this field may be more than the number of ports indicated in
4:0 the PI (ABAR + 0Ch) register.
Field value dependent on number of ports available in a given SKU. See Section 1.3
for details.
Datasheet 605
SATA Controller Registers (D31:F2)
13.4.1.2 GHC—Global PCH Control Register (D31:F2)
Address Offset: ABAR + 04h–07h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
AHCI Enable (AE)—R/W. When set, this bit indicates that an AHCI driver is loaded and
the controller will be talked to using AHCI mechanisms. This can be used by an PCH
that supports both legacy mechanisms (such as SFF-8038i) and AHCI to know when the
controller will not be talked to as legacy.
31
0 = Software will communicate with the PCH using legacy mechanisms.
1 = Software will communicate with the PCH using AHCI. The PCH will not have to allow
command processing using both AHCI and legacy mechanisms.
Software shall set this bit to 1 before accessing other AHCI registers.
30:3 Reserved
MSI Revert to Single Message (MRSM)—RO. When set to 1 by hardware, this bit
indicates that the host controller requested more than one MSI vector but has reverted
to using the first vector only. When this bit is cleared to 0, the controller has not
reverted to single MSI mode (that is, hardware is already in single MSI mode, software
has allocated the number of messages requested, or hardware is sharing interrupt
vectors if MC.MME < MC.MMC).
"MC.MSIE = 1 (MSI is enabled)
"MC.MMC > 0 (multiple messages requested)
"MC.MME > 0 (more than one message allocated)
2 "MC.MME!= MC.MMC (messages allocated not equal to number requested)
When this bit is set to 1, single MSI mode operation is in use and software is
responsible for clearing bits in the IS register to clear interrupts.
This bit shall be cleared to 0 by hardware when any of the four conditions stated is
false. This bit is also cleared to 0 when MC.MSIE = 1 and MC.MME = 0h. In this case,
the hardware has been programmed to use single MSI mode, and is not “reverting” to
that mode.
For PCH, the controller shall always revert to single MSI mode when the number of
vectors allocated by the host is less than the number requested. This bit is ignored
when GHC.HR = 1.
Interrupt Enable (IE)—R/W. This global bit enables interrupts from the PCH.
1 0 = All interrupt sources from all ports are disabled.
1 = Interrupts are allowed from the AHCI controller.
Controller Reset (HR)—R/W. Resets the PCH AHCI controller.
0 = No effect
1 = When set by software, this bit causes an internal reset of the PCH AHCI controller.
All state machines that relate to data transfers and queuing return to an idle
0
condition, and all ports are re-initialized using COMRESET.
NOTE: For further details, consult Section 10.4.3 of the Serial ATA Advanced Host
Controller Interface Specification, Revision 1.3.
606 Datasheet
SATA Controller Registers (D31:F2)
13.4.1.3 IS—Interrupt Status Register (D31:F2)
Address Offset: ABAR + 08h–0Bh Attribute: R/WC
Default Value: 00000000h Size: 32 bits
This register indicates which of the ports within the controller have an interrupt pending
and require service.
Bit Description
31:6 Reserved. Returns 0.
Interrupt Pending Status Port[5] (IPS[5])—R/WC.
5 0 = No interrupt pending.
1 = Port 5 has an interrupt pending. Software can use this information to determine
which ports require service after an interrupt.
Interrupt Pending Status Port[4] (IPS[4])—R/WC.
0 = No interrupt pending.
4
1 = Port 4 has an interrupt pending. Software can use this information to determine
which ports require service after an interrupt.
Interrupt Pending Status Port[3] (IPS[3])—R/WC.
0 = No interrupt pending.
1 = Port 3 has an interrupt pending. Software can use this information to determine
3
which ports require service after an interrupt.
NOTE: Bit may be Reserved depending on if port is available in the given SKU. See
Section 1.3 for details if port is available.
Interrupt Pending Status Port[2] (IPS[2])—R/WC.
0 = No interrupt pending.
1 = Port 2 has an interrupt pending. Software can use this information to determine
2
which ports require service after an interrupt.
NOTE: Bit may be Reserved depending on if port is available in the given SKU. See
Section 1.3 for details if port is available.
Interrupt Pending Status Port[1] (IPS[1])—R/WC.
0 = No interrupt pending.
1
1 = Port 1has an interrupt pending. Software can use this information to determine
which ports require service after an interrupt.
Interrupt Pending Status Port[0] (IPS[0])—R/WC.
0 = No interrupt pending.
0
1 = Port 0 has an interrupt pending. Software can use this information to determine
which ports require service after an interrupt.
Datasheet 607
SATA Controller Registers (D31:F2)
13.4.1.4 PI—Ports Implemented Register (D31:F2)
Address Offset: ABAR + 0Ch–0Fh Attribute: R/WO, RO
Default Value: 00000000h Size: 32 bits
Function Level Reset: No
This register indicates which ports are exposed to the PCH. It is loaded by platform
BIOS. It indicates which ports that the device supports are available for software to
use. For ports that are not available, software must not read or write to registers within
that port. After BIOS issues initial write to this register, BIOS is requested to issue two
reads to this register. If BIOS accesses any of the port specific AHCI address range
before setting PI bit, BIOS is required to read the PI register before the initial write to
the PI register.
Bit Description
31:6 Reserved. Returns 0.
Ports Implemented Port 5 (PI5)—R/WO.
0 = The port is not implemented.
5
1 = The port is implemented.
This bit is read-only 0 if this is a PCIe Port, MAP.SC = 0 or SCC = 01h.
Ports Implemented Port 4 (PI4)—R/WO.
0 = The port is not implemented.
4
1 = The port is implemented.
This bit is read-only 0 if this is a PCIe Port, MAP.SC = 0 or SCC = 01h.
Ports Implemented Port 3 (PI3)—R/WO.
0 = The port is not implemented.
3 1 = The port is implemented.
NOTE: Bit may be Reserved and RO ‘0’ depending on if port is available in the given
SKU. See Section 1.3 for details if port is available.
Ports Implemented Port 2 (PI2)—R/WO.
0 = The port is not implemented.
2 1 = The port is implemented.
NOTE: Bit may be Reserved and RO ‘0’ depending on if port is available in the given
SKU. See Section 1.3 for details if port is available.
Ports Implemented Port 1 (PI1)—R/WO.
1 0 = The port is not implemented.
1 = The port is implemented.
Ports Implemented Port 0 (PI0)—R/WO.
0 0 = The port is not implemented.
1 = The port is implemented.
608 Datasheet
SATA Controller Registers (D31:F2)
13.4.1.5 VS—AHCI Version Register (D31:F2)
Address Offset: ABAR + 10h–13h Attribute: RO
Default Value: 00010300h Size: 32 bits
This register indicates the major and minor version of the AHCI specification. It is BCD
encoded. The upper two bytes represent the major version number, and the lower two
bytes represent the minor version number. Example: Version 3.12 would be
represented as 00030102h. The current version of the specification is 1.30
(00010300h).
Bit Description
31:16 Major Version Number (MJR)—RO. Indicates the major version is 1
15:0 Minor Version Number (MNR)—RO. Indicates the minor version is 30.
13.4.1.6 EM_LOC—Enclosure Management Location Register (D31:F2)
Address Offset: ABAR + 1Ch–1Fh Attribute: RO
Default Value: 01600002h Size: 32 bits
This register identifies the location and size of the enclosure management message
buffer. This register is reserved if enclosure management is not supported (that is,
CAP.EMS = 0).
Bit Description
Offset (OFST)—RO. The offset of the message buffer in DWords from the beginning
31:16
of the ABAR.
Buffer Size (SZ)—RO. Specifies the size of the transmit message buffer area in
15:0 DWords. The PCH SATA controller only supports transmit buffer.
A value of 0 is invalid.
Datasheet 609
SATA Controller Registers (D31:F2)
13.4.1.7 EM_CTRL—Enclosure Management Control Register (D31:F2)
Address Offset: ABAR + 20h–23h Attribute: R/W, R/WO, RO
Default Value: 07010000h Size: 32 bits
This register is used to control and obtain status for the enclosure management
interface. This register includes information on the attributes of the implementation,
enclosure management messages supported, the status of the interface, whether any
message are pending, and is used to initiate sending messages. This register is
reserved if enclosure management is not supported (CAP_EMS = 0).
Bit Description
31:27 Reserved
Activity LED Hardware Driven (ATTR.ALHD)—R/WO.
1 = The SATA controller drives the activity LED for the LED message type in hardware
26 and does not utilize software for this LED.
The host controller does not begin transmitting the hardware based activity signal
until after software has written CTL.TM=1 after a reset condition.
Transmit Only (ATTR.XMT)—RO.
25 0 = The SATA controller supports transmitting and receiving messages.
1 = The SATA controller only supports transmitting messages and does not support
receiving messages.
Single Message Buffer (ATTR.SMB)—RO.
0 = There are separate receive and transmit buffers such that unsolicited messages
could be supported.
24
1 = The SATA controller has one message buffer that is shared for messages to
transmit and messages received. Unsolicited receive messages are not supported
and it is software’s responsibility to manage access to this buffer.
23:20 Reserved
SGPIO Enclosure Management Messages (SUPP.SGPIO)—RO.
19
1 = The SATA controller supports the SGPIO register interface message type.
SES-2 Enclosure Management Messages (SUPP.SES2)—RO.
18
1 = The SATA controller supports the SES-2 message type.
SAF-TE Enclosure Management Messages (SUPP.SAFTE)—RO.
17
1 = The SATA controller supports the SAF-TE message type.
LED Message Types (SUPP.LED)—RO.
16
1 = The SATA controller supports the LED message type.
15:10 Reserved
Reset (RST):—R/W.
0 = A write of 0 to this bit by software will have no effect.
1 = When set by software, The SATA controller resets all enclosure management
9
message logic and takes all appropriate reset actions to ensure messages can be
transmitted / received after the reset. After the SATA controller completes the
reset operation, the SATA controller sets the value to 0.
Transmit Message (CTL.TM)—R/W.
0 = A write of 0 to this bit by software will have no effect.
1 = When set by software, The SATA controller transmits the message contained in
8 the message buffer. When the message is completely sent, the SATA controller
sets the value to 0.
Software must not change the contents of the message buffer while CTL.TM is set to
1.
7:1 Reserved
0 Message Received (STS.MR):—RO. Message Received is not supported in the PCH.
610 Datasheet
SATA Controller Registers (D31:F2)
13.4.1.8 CAP2—HBA Capabilities Extended Register
Address Offset: ABAR + 24h–27h Attribute: RO
Default Value: 00000004h Size: 32 bits
Function Level Reset: No
Bit Description
31:3 Reserved
Automatic Partial to Slumber Transitions (APST)
2 0= Not supported
1= Supported
1:0 Reserved
13.4.1.9 RSTF—Intel® RST Feature Capabilities Register
Address Offset: ABAR + C8h–C9h Attribute: R/WO
Default Value: 003Fh Size: 16 bits
Function Level Reset: No
No hardware action is taken on this register. This register is needed for the Intel Rapid
Storage Technology software. These bits are set by BIOS to request the feature from
the appropriate Intel Rapid Storage Technology software.
Bit Description
15:12 Reserved
OROM UI Normal Delay (OUD)—R/WO. The values of these bits specify the delay of
the OROM UI Splash Screen in a normal status.
00 = 2 Seconds (Default)
11:10 01 = 4 Seconds
10 = 6 Seconds
11 = 8 Seconds
If bit 5 = 0b these values will be disregarded.
Intel® Smart Response Technology Enable Request (SEREQ)—R/WO. Indicates
the requested status of the Intel Smart Response Technology support.
9
0 = Disabled
1 = Enabled
Intel® RRT Only on eSATA (ROES)—R/WO. Indicates the request that only Intel
Rapid Recovery Technology (RRT) volumes can span internal and external SATA
8 (eSATA). If not set, any RAID volume can span internal and external SATA.
0 = Disabled
1 = Enabled
7 Reserved
HDD Unlock (HDDLK)—R/WO
Indicates the requested status of HDD password unlock in the OS.
6
0 = Disabled
1 = Enabled
Datasheet 611
SATA Controller Registers (D31:F2)
Bit Description
Intel RST OROM UI (RSTOROMUI)—R/WO. Indicates the requested status of the
Intel RST OROM UI display.
5 0 = The Intel RST OROM UI and banner are not displayed if all disks and RAID volumes
have a normal status.
1 = The Intel RST OROM UI is displayed during each boot.
Intel® RRT Enable (RSTE)—R/WO
Indicates the requested status of the Intel Rapid Recovery Technology support.
4
0 = Disabled
1 = Enabled
RAID 5 Enable (R5E)—R/WO
Indicates the requested status of RAID 5 support.
3
0 = Disabled
1 = Enabled
RAID 10 Enable (R10E)—R/WO
Indicates the requested status of RAID 10 support.
2
0 = Disabled
1 = Enabled
RAID 1 Enable (R1E)—R/WO
Indicates the requested status of RAID 1 support.
1
0 = Disabled
1 = Enabled
RAID 0 Enable (R0E)—R/WO
Indicates the requested status of RAID 0 support.
0
0 = Disabled
1 = Enabled
612 Datasheet
SATA Controller Registers (D31:F2)
13.4.2 Port Registers (D31:F2)
Ports not available will result in the corresponding Port DMA register space being
reserved. The controller shall ignore writes to the reserved space on write cycles and
shall return 0 on read cycle accesses to the reserved location.
Table 13-5. Port [5:0] DMA Register Address Map (Sheet 1 of 3)
ABAR +
Mnemonic Register
Offset
100h–103h P0CLB Port 0 Command List Base Address
104h–107h P0CLBU Port 0 Command List Base Address Upper 32-Bits
108h–10Bh P0FB Port 0 FIS Base Address
10Ch–10Fh P0FBU Port 0 FIS Base Address Upper 32-Bits
110h–113h P0IS Port 0 Interrupt Status
114h–117h P0IE Port 0 Interrupt Enable
118h–11Bh P0CMD Port 0 Command
11Ch–11Fh — Reserved
120h–123h P0TFD Port 0 Task File Data
124h–127h P0SIG Port 0 Signature
128h–12Bh P0SSTS Port 0 Serial ATA Status
12Ch–12Fh P0SCTL Port 0 Serial ATA Control
130h–133h P0SERR Port 0 Serial ATA Error
134h–137h P0SACT Port 0 Serial ATA Active
138h–13Bh P0CI Port 0 Command Issue
13Ch–17Fh — Reserved
180h–183h P1CLB Port 1 Command List Base Address
184h–187h P1CLBU Port 1 Command List Base Address Upper 32-Bits
188h–18Bh P1FB Port 1 FIS Base Address
18Ch–18Fh P1FBU Port 1 FIS Base Address Upper 32-Bits
190h–193h P1IS Port 1 Interrupt Status
194h–197h P1IE Port 1 Interrupt Enable
198h–19Bh P1CMD Port 1 Command
19Ch–19Fh — Reserved
1A0h–1A3h P1TFD Port 1 Task File Data
1A4h–1A7h P1SIG Port 1 Signature
1A8h–1ABh P1SSTS Port 1 Serial ATA Status
1ACh–1AFh P1SCTL Port 1 Serial ATA Control
1B0h–1B3h P1SERR Port 1 Serial ATA Error
1B4h–1B7h P1SACT Port 1 Serial ATA Active
1B8h–1BBh P1CI Port 1 Command Issue
1BCh–1FFh — Reserved
Datasheet 613
SATA Controller Registers (D31:F2)
Table 13-5. Port [5:0] DMA Register Address Map (Sheet 2 of 3)
ABAR +
Mnemonic Register
Offset
Registers may be Reserved depending on if port is available in
200h–27Fh —
the given SKU. See Section 1.3 for details if port is available.
200h–203h P2CLB Port 2 Command List Base Address
204h–207h P2CLBU Port 2 Command List Base Address Upper 32-Bits
208h–20Bh P2FB Port 2 FIS Base Address
20Ch–20Fh P2FBU Port 2 FIS Base Address Upper 32-Bits
210h–213h P2IS Port 2 Interrupt Status
214h–217h P2IE Port 2 Interrupt Enable
218h–21Bh P2CMD Port 2 Command
21Ch–21Fh — Reserved
220h–223h P2TFD Port 2 Task File Data
224h–227h P2SIG Port 2 Signature
228h–22Bh P2SSTS Port 2 Serial ATA Status
22Ch–22Fh P2SCTL Port 2 Serial ATA Control
230h–233h P2SERR Port 2 Serial ATA Error
234h–237h P2SACT Port 2 Serial ATA Active
238h–23Bh P2CI Port 2 Command Issue
23Ch–27Fh — Reserved
Registers may be Reserved depending on if port is available in
280h–2FFh —
the given SKU. See Section 1.3 for details if port is available.
280h–283h P3CLB Port 3 Command List Base Address
284h–287h P3CLBU Port 3 Command List Base Address Upper 32-Bits
288h–28Bh P3FB Port 3 FIS Base Address
28Ch–28Fh P3FBU Port 3 FIS Base Address Upper 32-Bits
290h–293h P3IS Port 3 Interrupt Status
294h–297h P3IE Port 3 Interrupt Enable
298h–29Bh P3CMD Port 3 Command
29Ch–29Fh — Reserved
2A0h–2A3h P3TFD Port 3 Task File Data
2A4h–2A7h P3SIG Port 3 Signature
2A8h–2ABh P3SSTS Port 3 Serial ATA Status
2ACh–2AFh P3SCTL Port 3 Serial ATA Control
2B0h–2B3h P3SERR Port 3 Serial ATA Error
2B4h–2B7h P3SACT Port 3 Serial ATA Active
2B8h–2BBh P3CI Port 3 Command Issue
2BCh–2FFh — Reserved
300h–303h P4CLB Port 4 Command List Base Address
304h–307h P4CLBU Port 4 Command List Base Address Upper 32-Bits
614 Datasheet
SATA Controller Registers (D31:F2)
Table 13-5. Port [5:0] DMA Register Address Map (Sheet 3 of 3)
ABAR +
Mnemonic Register
Offset
308h–30Bh P4FB Port 4 FIS Base Address
30Ch–30Fh P4FBU Port 4 FIS Base Address Upper 32-Bits
310h–313h P4IS Port 4 Interrupt Status
314h–317h P4IE Port 4 Interrupt Enable
318h–31Bh P4CMD Port 4 Command
31Ch–31Fh — Reserved
320h–323h P4TFD Port 4 Task File Data
324h–327h P4SIG Port 4 Signature
328h–32Bh P4SSTS Port 4 Serial ATA Status
32Ch–32Fh P4SCTL Port 4 Serial ATA Control
330h–333h P4SERR Port 4 Serial ATA Error
334h–337h P4SACT Port 4 Serial ATA Active
338h–33Bh P4CI Port 4 Command Issue
33Ch–37Fh — Reserved
380h–383h P5CLB Port 5 Command List Base Address
384h–387h P5CLBU Port 5 Command List Base Address Upper 32-Bits
388h–38Bh P5FB Port 5 FIS Base Address
38Ch–38Fh P5FBU Port 5 FIS Base Address Upper 32-Bits
390h–393h P5IS Port 5 Interrupt Status
394h–397h P5IE Port 5 Interrupt Enable
398h–39Bh P5CMD Port 5 Command
39Ch–39Fh — Reserved
3A0h–3A3h P5TFD Port 5 Task File Data
3A4h–3A7h P5SIG Port 5 Signature
3A8h–3ABh P5SSTS Port 5 Serial ATA Status
3ACh–3AFh P5SCTL Port 5 Serial ATA Control
3B0h–3B3h P5SERR Port 5 Serial ATA Error
3B4h–3B7h P5SACT Port 5 Serial ATA Active
3B8h–3BBh P5CI Port 5 Command Issue
3BCh–FFFh — Reserved
Datasheet 615
SATA Controller Registers (D31:F2)
13.4.2.1 PxCLB—Port [5:0] Command List Base Address Register
(D31:F2)
Address Offset: Port 0: ABAR + 100h Attribute: R/W
Port 1: ABAR + 180h
Port 2: ABAR + 200h (if port available; see Section 1.3)
Port 3: ABAR + 280h (if port available; see Section 1.3)
Port 4: ABAR + 300h
Port 5: ABAR + 380h
Default Value: Undefined Size: 32 bits
Bit Description
Command List Base Address (CLB)—R/W. Indicates the 32-bit base for the
command list for this port. This base is used when fetching commands to execute. The
31:10 structure pointed to by this address range is 1 KB in length. This address must be 1-KB
aligned as indicated by bits 31:10 being read/write.
These bits are not reset on a controller reset.
9:0 Reserved
13.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper
32-Bits Register (D31:F2)
Address Offset: Port 0: ABAR + 104h Attribute: R/W
Port 1: ABAR + 184h
Port 2: ABAR + 204h (if port available; see Section 1.3)
Port 3: ABAR + 284h (if port available; see Section 1.3)
Port 4: ABAR + 304h
Port 5: ABAR + 384h
Default Value: Undefined Size: 32 bits
Bit Description
Command List Base Address Upper (CLBU)—R/W. Indicates the upper 32-bits for
the command list base address for this port. This base is used when fetching
31:0 commands to execute.
These bits are not reset on a controller reset.
13.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2)
Address Offset: Port 0: ABAR + 108h Attribute: R/W
Port 1: ABAR + 188h
Port 2: ABAR + 208h (if port available; see Section 1.3)
Port 3: ABAR + 288h (if port available; see Section 1.3)
Port 4: ABAR + 308h
Port 5: ABAR + 388h
Default Value: Undefined Size: 32 bits
Bit Description
FIS Base Address (FB)—R/W. Indicates the 32-bit base for received FISes. The
structure pointed to by this address range is 256 bytes in length. This address must be
31:8
256-byte aligned, as indicated by bits 31:3 being read/write.
These bits are not reset on a controller reset.
7:0 Reserved
616 Datasheet
SATA Controller Registers (D31:F2)
13.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits
Register (D31:F2)
Address Offset: Port 0: ABAR + 10Ch Attribute: R/W
Port 1: ABAR + 18Ch
Port 2: ABAR + 20Ch (if port available; see Section 1.3)
Port 3: ABAR + 28Ch (if port available; see Section 1.3)
Port 4: ABAR + 30Ch
Port 5: ABAR + 38Ch
Default Value: Undefined Size: 32 bits
Bit Description
FIS Base Address Upper (FBU)—R/W. Indicates the upper 32-bits for the received
31:0 FIS base for this port.
These bits are not reset on a controller reset.
13.4.2.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2)
Address Offset: Port 0: ABAR + 110h Attribute: R/WC, RO
Port 1: ABAR + 190h
Port 2: ABAR + 210h (if port available; see Section 1.3)
Port 3: ABAR + 290h (if port available; see Section 1.3)
Port 4: ABAR + 310h
Port 5: ABAR + 390h
Default Value: 00000000h Size: 32 bits
Bit Description
31 Cold Port Detect Status (CPDS)—RO. Cold presence detect is not supported.
Task File Error Status (TFES)—R/WC. This bit is set whenever the status register is
30
updated by the device and the error bit (PxTFD.bit 0) is set.
Host Bus Fatal Error Status (HBFS)—R/WC. Indicates that the PCH encountered an
29 error that it cannot recover from due to a bad software pointer. In PCI, such an
indication would be a target or master abort.
Host Bus Data Error Status (HBDS)—R/WC. Indicates that the PCH encountered a
28
data error (uncorrectable ECC / parity) when reading from or writing to system memory.
Interface Fatal Error Status (IFS)—R/WC. Indicates that the PCH encountered an
27
error on the SATA interface which caused the transfer to stop.
Interface Non-fatal Error Status (INFS)—R/WC. Indicates that the PCH encountered
26
an error on the SATA interface but was able to continue operation.
25 Reserved
Overflow Status (OFS)—R/WC. Indicates that the PCH received more bytes from a
24
device than was specified in the PRD table for the command.
Incorrect Port Multiplier Status (IPMS)—R/WC. The PCH SATA controller does not
23
support Port Multipliers.
PhyRdy Change Status (PRCS)—RO. When set to one, this bit indicates the internal
PhyRdy signal changed state. This bit reflects the state of PxSERR.DIAG.N. Unlike most
of the other bits in the register, this bit is RO and is only cleared when PxSERR.DIAG.N is
cleared.
22
The internal PhyRdy signal also transitions when the port interface enters partial or
slumber power management states. Partial and slumber must be disabled when
Surprise Removal Notification is desired, otherwise the power management state
transitions will appear as false insertion and removal events.
Datasheet 617
SATA Controller Registers (D31:F2)
Bit Description
21:8 Reserved
Device Interlock Status (DIS)—R/WC. When set, this bit indicates that a platform
mechanical presence switch has been opened or closed, which may lead to a change in
the connection state of the device. This bit is only valid in systems that support an
7 mechanical presence switch (CAP.SIS [ABAR+00:bit 28] set).
For systems that do not support an mechanical presence switch, this bit will always be
0.
Port Connect Change Status (PCS)—RO. This bit reflects the state of
PxSERR.DIAG.X. (ABAR+130h/1D0h/230h/2D0h, bit 26) Unlike other bits in this
6 register, this bit is only cleared when PxSERR.DIAG.X is cleared.
0 = No change in Current Connect Status.
1 = Change in Current Connect Status.
Descriptor Processed (DPS)—R/WC. A PRD with the I bit set has transferred all its
5
data.
Unknown FIS Interrupt (UFS)—RO. When set to 1, this bit indicates that an unknown
FIS was received and has been copied into system memory. This bit is cleared to 0 by
software clearing the PxSERR.DIAG.F bit to 0. This bit does not directly reflect the
4 PxSERR.DIAG.F bit. PxSERR.DIAG.F is set immediately when an unknown FIS is
detected, whereas this bit is set when the FIS is posted to memory. Software should
wait to act on an unknown FIS until this bit is set to 1 or the two bits may become out of
sync.
Set Device Bits Interrupt (SdBS)—R/WC. A Set Device Bits FIS has been received
3
with the I bit set and has been copied into system memory.
DMA Setup FIS Interrupt (DSS)—R/WC. A DMA Setup FIS has been received with the
2
I bit set and has been copied into system memory.
PIO Setup FIS Interrupt (PSS)—R/WC. A PIO Setup FIS has been received with the I
1 bit set, it has been copied into system memory, and the data related to that FIS has
been transferred.
Device to Host Register FIS Interrupt (DHRS)—R/WC. A D2H Register FIS has been
0
received with the I bit set, and has been copied into system memory.
618 Datasheet
SATA Controller Registers (D31:F2)
13.4.2.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2)
Address Offset: Port 0: ABAR + 114h Attribute: R/W, RO
Port 1: ABAR + 194h
Port 2: ABAR + 214h (if port available; see Section 1.3)
Port 3: ABAR + 294h (if port available; see Section 1.3)
Port 4: ABAR + 314h
Port 5: ABAR + 394h
Default Value: 00000000h Size: 32 bits
This register enables and disables the reporting of the corresponding interrupt to
system software. When a bit is set (1) and the corresponding interrupt condition is
active, then an interrupt is generated. Interrupt sources that are disabled (0) are still
reflected in the status registers.
Bit Description
31 Cold Presence Detect Enable (CPDE)—RO. Cold Presence Detect is not supported.
Task File Error Enable (TFEE)—R/W. When set, and GHC.IE and PxTFD.STS.ERR (due
30 to a reception of the error register from a received FIS) are set, the PCH will generate
an interrupt.
Host Bus Fatal Error Enable (HBFE)—R/W. When set, and GHC.IE and PxS.HBFS are
29
set, the PCH will generate an interrupt.
Host Bus Data Error Enable (HBDE)—R/W. When set, and GHC.IE and PxS.HBDS are
28
set, the PCH will generate an interrupt.
Host Bus Data Error Enable (HBDE)—R/W. When set, GHC.IE is set, and PxIS.HBDS
27
is set, the PCH will generate an interrupt.
Interface Non-fatal Error Enable (INFE)—R/W. When set, GHC.IE is set, and
26
PxIS.INFS is set, the PCH will generate an interrupt.
25 Reserved
Overflow Error Enable (OFE)—R/W. When set, and GHC.IE and PxS.OFS are set, the
24
PCH will generate an interrupt.
Incorrect Port Multiplier Enable (IPME)—R/W. The PCH SATA controller does not
23
support Port Multipliers. BIOS and storage software should keep this bit cleared to 0.
PhyRdy Change Interrupt Enable (PRCE)—R/W. When set, and GHC.IE is set, and
22
PxIS.PRCS is set, the PCH shall generate an interrupt.
21:8 Reserved
Device Interlock Enable (DIE)—R/W. When set, and PxIS.DIS is set, the PCH will
generate an interrupt.
7
For systems that do not support an mechanical presence switch, this bit shall be a read-
only 0.
Port Change Interrupt Enable (PCE)—R/W. When set, and GHC.IE and PxS.PCS are
6
set, the PCH will generate an interrupt.
Descriptor Processed Interrupt Enable (DPE)—R/W. When set, and GHC.IE and
5
PxS.DPS are set, the PCH will generate an interrupt.
Unknown FIS Interrupt Enable (UFIE)—R/W. When set, and GHC.IE is set and an
4
unknown FIS is received, the PCH will generate this interrupt.
Set Device Bits FIS Interrupt Enable (SdBE)—R/W. When set, and GHC.IE and
3
PxS.SdBS are set, the PCH will generate an interrupt.
DMA Setup FIS Interrupt Enable (DSE)—R/W. When set, and GHC.IE and PxS.DSS
2
are set, the PCH will generate an interrupt.
PIO Setup FIS Interrupt Enable (PSE)—R/W. When set, and GHC.IE and PxS.PSS
1
are set, the PCH will generate an interrupt.
Device to Host Register FIS Interrupt Enable (DHRE)—R/W. When set, and
0
GHC.IE and PxS.DHRS are set, the PCH will generate an interrupt.
Datasheet 619
SATA Controller Registers (D31:F2)
13.4.2.7 PxCMD—Port [5:0] Command Register (D31:F2)
Address Offset: Port 0: ABAR + 118h Attribute: R/W, RO, R/WO
Port 1: ABAR + 198h
Port 2: ABAR + 218h (if port available; see Section 1.3)
Port 3: ABAR + 298h (if port available; see Section 1.3)
Port 4: ABAR + 318h
Port 5: ABAR + 398h
Default Value: 0000w00wh Size: 32 bits
where w = 00?0b (for?, see bit description)
Function Level Reset:No (Bit 21, 19 and 18 only)
Bit Description
Interface Communication Control (ICC)—R/W.This is a four bit field that can be
used to control reset and power states of the interface. Writes to this field will cause
actions on the interface, either as primitives or an OOB sequence, and the resulting
status of the interface will be reported in the PxSSTS register (Address offset Port
0:ABAR+124h, Port 1: ABAR+1A4h, Port 2: ABAR+224h, Port 3: ABAR+2A4h, Port 4:
ABAR+224h, Port 5: ABAR+2A4h).
Value Definition
Fh–7h Reserved
Slumber: This will cause the PCH to request a transition of the
6h interface to the slumber state. The SATA device may reject the
request and the interface will remain in its current state
5h–3h Reserved
Partial: This will cause the PCH to request a transition of the
31:28 2h interface to the partial state. The SATA device may reject the
request and the interface will remain in its current state.
Active: This will cause the PCH to request a transition of the
1h
interface into the active
No-Op / Idle: When software reads this value, it indicates the PCH is
0h not in the process of changing the interface state or sending a
device reset, and a new link command may be issued.
When system software writes a non-reserved value other than No-Op (0h), the PCH
will perform the action and update this field back to Idle (0h).
If software writes to this field to change the state to a state the link is already in
(such as, interface is in the active state and a request is made to go to the active
state), the PCH will take no action and return this field to Idle.
NOTE: When the ALPE bit (bit 26) is set, this register should not be set to 02h or
06h.
Aggressive Slumber / Partial (ASP)—R/W. When set to 1, and the ALPE bit (bit
26) is set, the PCH shall aggressively enter the slumber state when it clears the PxCI
register and the PxSACT register is cleared. When cleared, and the ALPE bit is set, the
27
PCH will aggressively enter the partial state when it clears the PxCI register and the
PxSACT register is cleared. If CAP.SALP is cleared to 0, software shall treat this bit as
reserved.
Aggressive Link Power Management Enable (ALPE)—R/W. When set to 1, the
26 PCH will aggressively enter a lower link power state (partial or slumber) based upon
the setting of the ASP bit (bit 27).
620 Datasheet
SATA Controller Registers (D31:F2)
Bit Description
Drive LED on ATAPI Enable (DLAE)—R/W. When set to 1, the PCH will drive the
LED pin active for ATAPI commands (PxCLB[CHz.A] set) in addition to ATA
25
commands. When cleared, the PCH will only drive the LED pin active for ATA
commands. See Section 5.17.11 for details on the activity LED.
Device is ATAPI (ATAPI)—R/W. When set to 1, the connected device is an ATAPI
24 device. This bit is used by the PCH to control whether or not to generate the desktop
LED when commands are active. See Section 5.17.11 for details on the activity LED.
Automatic Partial Slumber Transitions Enabled (APSTE)—R/W.
0 = This port will not perform Automatic Partial to Slumber Transitions.
23 1 = The HBA may perform Automatic Partial to Slumber Transitions.
NOTE: Software should only set this bit to ‘1’ if CAP2.APST is set to ‘1’.
22 Reserved
External SATA Port (ESP)—R/WO.
0 = This port supports internal SATA devices only.
21 1 = This port will be used with an external SATA device and Hot-Plug is supported.
When set, CAP.SXS must also be set.
This bit is not reset by Function Level Reset.
20 Reserved
Mechanical Switch Attached to Port (MPSP)—R/WO. If set to 1, the PCH
supports a mechanical presence switch attached to this port.
The PCH takes no action on the state of this bit – it is for system software only. For
19 example, if this bit is cleared, and an mechanical presence switch toggles, the PCH
still treats it as a proper mechanical presence switch event.
NOTE: This bit is not reset on a Controller reset or by a Function Level Reset.
Hot-Plug Capable Port (HPCP)—R/WO.
0 = Port is not capable of Hot-Plug.
1 = Port is Hot-Plug capable.
This indicates whether the platform exposes this port to a device which can be Hot-
Plugged. SATA by definition is hot-pluggable, but not all platforms are constructed to
18 allow the device to be removed (it may be screwed into the chassis, for example).
This bit can be used by system software to indicate a feature such as “eject device” to
the end-user. The PCH takes no action on the state of this bit – it is for system
software only. For example, if this bit is cleared, and a Hot-Plug event occurs, the PCH
still treats it as a proper Hot-Plug event.
NOTE: This bit is not reset on a Controller reset or by a Function Level Reset.
17:16 Reserved
Controller Running (CR)—RO. When this bit is set, the DMA engines for a port are
15
running.
FIS Receive Running (FR)—RO. When set, the FIS Receive DMA engine for the port
14
is running.
Mechanical Presence Switch State (MPSS)—RO. The MPSS bit reports the state
of a mechanical presence switch attached to this port. If CAP.SMPS is set to 1 and the
mechanical presence switch is closed then this bit is cleared to 0. If CAP.SMPS is set
13
to 1 and the mechanical presence switch is open then this bit is set to 1. If CAP.SMPS
is set to '0' then this bit is cleared to 0. Software should only use this bit if both
CAP.SMPS and PxCMD.MPSP are set to 1.
Datasheet 621
SATA Controller Registers (D31:F2)
Bit Description
Current Command Slot (CCS)—RO. Indicates the current command slot the PCH is
processing. This field is valid when the ST bit is set in this register, and is constantly
updated by the PCH. This field can be updated as soon as the PCH recognizes an
active command slot, or at some point soon after when it begins processing the
12:8 command.
This field is used by software to determine the current command issue location of the
PCH. In queued mode, software shall not use this field, as its value does not
represent the current command being executed. Software shall only use PxCI and
PxSACT when running queued commands.
7:5 Reserved
FIS Receive Enable (FRE)—R/W. When set, the PCH may post received FISes into
the FIS receive area pointed to by PxFB (ABAR+108h/188h/208h/288h) and PxFBU
(ABAR+10Ch/18Ch/20Ch/28Ch). When cleared, received FISes are not accepted by
the PCH, except for the first D2H (device-to-host) register FIS after the initialization
4 sequence.
System software must not set this bit until PxFB (PxFBU) have been programmed
with a valid pointer to the FIS receive area, and if software wishes to move the base,
this bit must first be cleared, and software must wait for the FR bit (bit 14) in this
register to be cleared.
Command List Override (CLO)—R/W. Setting this bit to 1 causes PxTFD.STS.BSY
and PxTFD.STS.DRQ to be cleared to 0. This allows a software reset to be transmitted
to the device regardless of whether the BSY and DRQ bits are still set in the
PxTFD.STS register. The Controller sets this bit to 0 when PxTFD.STS.BSY and
PxTFD.STS.DRQ have been cleared to 0. A write to this register with a value of 0 shall
3 have no effect.
This bit shall only be set to 1 immediately prior to setting the PxCMD.ST bit to 1 from
a previous value of 0. Setting this bit to 1 at any other time is not supported and will
result in indeterminate behavior. Software must wait for CLO to be cleared to 0 before
setting PxCMD.ST to 1.
2 Power On Device (POD)—RO. Cold presence detect not supported. Defaults to 1.
Spin-Up Device (SUD)—R/W / RO
This bit is R/W and defaults to 0 for systems that support staggered spin-up (R/W
when CAP.SSS (ABAR+00h:bit 27) is 1). Bit is RO 1 for systems that do not support
staggered spin-up (when CAP.SSS is 0).
1 0 = No action.
1 = On an edge detect from 0 to 1, the PCH starts a COMRESET initialization
sequence to the device.
Clearing this bit to 0 does not cause any OOB signal to be sent on the interface. When
this bit is cleared to 0 and PxSCTL.DET=0h, the controller will enter listen mode.
Start (ST)—R/W. When set, the PCH may process the command list. When cleared,
the PCH may not process the command list. Whenever this bit is changed from a 0 to
a 1, the PCH starts processing the command list at entry 0. Whenever this bit is
0 changed from a 1 to a 0, the PxCI register is cleared by the PCH upon the PCH putting
the controller into an idle state.
Refer to Section 10.3 of the Serial ATA AHCI Specification for important restrictions
on when ST can be set to 1 and cleared to 0.
622 Datasheet
SATA Controller Registers (D31:F2)
13.4.2.8 PxTFD—Port [5:0] Task File Data Register (D31:F2)
Address Offset: Port 0: ABAR + 120h Attribute: RO
Port 1: ABAR + 1A0h
Port 2: ABAR + 220h (if port available; see Section 1.3)
Port 3: ABAR + 2A0h (if port available; see Section 1.3)
Port 4: ABAR + 320h
Port 5: ABAR + 3A0h
Default Value: 0000007Fh Size: 32 bits
This is a 32-bit register that copies specific fields of the task file when FISes are
received. The FISes that contain this information are: D2H Register FIS,PIO Setup FIS
and Set Device Bits FIS
Bit Description
31:16 Reserved
15:8 Error (ERR)—RO. Contains the latest copy of the task file error register.
Status (STS)—RO. Contains the latest copy of the task file status register. Fields in
this register that affect AHCI.
Bit Field Definition
7 BSY Indicates the interface is busy
7:0 6:4 N/A Not applicable
3 DRQ Indicates a data transfer is requested
2:1 N/A Not applicable
0 ERR Indicates an error during the transfer
13.4.2.9 PxSIG—Port [5:0] Signature Register (D31:F2)
Address Offset: Port 0: ABAR + 124h Attribute: RO
Port 1: ABAR + 1A4h
Port 2: ABAR + 224h (if port available; see Section 1.3)
Port 3: ABAR + 2A4h (if port available; see Section 1.3)
Port 4: ABAR + 324h
Port 5: ABAR + 3A4h
Default Value: FFFFFFFFh Size: 32 bits
This is a 32-bit register which contains the initial signature of an attached device when
the first D2H Register FIS is received from that device. It is updated once after a reset
sequence.
Bit Description
Signature (SIG)—RO. Contains the signature received from a device on the first D2H
register FIS. The bit order is as follows:
Bit Field
31:0 31:24 LBA High Register
23:16 LBA Mid Register
15:8 LBA Low Register
7:0 Sector Count Register
Datasheet 623
SATA Controller Registers (D31:F2)
13.4.2.10 PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2)
Address Offset: Port 0: ABAR + 128h Attribute: RO
Port 1: ABAR + 1A8h
Port 2: ABAR + 228h (if port available; see Section 1.3)
Port 3: ABAR + 2A8h (if port available; see Section 1.3)
Port 4: ABAR + 328h
Port 5: ABAR + 3A8h
Default Value: 00000000h Size: 32 bits
This is a 32-bit register that conveys the current state of the interface and host. The
PCH updates it continuously and asynchronously. When the PCH transmits a COMRESET
to the device, this register is updated to its reset values.
Bit Description
31:12 Reserved
Interface Power Management (IPM)—RO. Indicates the current interface state:
Value Description
0h Device not present or communication not established
11:8 1h Interface in active state
2h Interface in PARTIAL power management state
6h Interface in SLUMBER power management state
All other values reserved.
Current Interface Speed (SPD)—RO. Indicates the negotiated interface
communication speed.
Value Description
0h Device not present or communication not established
1h Generation 1 communication rate negotiated
7:4
2h Generation 2 communication rate negotiated
3h Generation 3 communication rate negotiated
All other values reserved.
The PCH supports Gen 1 communication rates (1.5 Gb/s), Gen 2 rates (3.0 Gb/s) and
Gen 3 rates (6.0 Gb/s) (supported speeds are determined by SKU; see Section 1.3)
Device Detection (DET)—RO. Indicates the interface device detection and Phy state:
Value Description
0h No device detected and Phy communication not established
1h Device presence detected but Phy communication not established
3:0
3h Device presence detected and Phy communication established
Phy in offline mode as a result of the interface being disabled or
4h
running in a BIST loopback mode
All other values reserved.
624 Datasheet
SATA Controller Registers (D31:F2)
13.4.2.11 PxSCTL—Port [5:0] Serial ATA Control Register (D31:F2)
Address Offset: Port 0: ABAR + 12Ch Attribute: R/W, RO
Port 1: ABAR + 1ACh
Port 2: ABAR + 22Ch (if port available; see Section 1.3)
Port 3: ABAR + 2ACh (if port available; see Section 1.3)
Port 4: ABAR + 32Ch
Port 5: ABAR + 3ACh
Default Value: 00000004h Size: 32 bits
This is a 32-bit read-write register by which software controls SATA capabilities. Writes
to the SControl register result in an action being taken by the PCH or the interface.
Reads from the register return the last value written to it.
Bit Description
31:20 Reserved
19:16 Port Multiplier Port (PMP)—R/W. This field is not used by AHCI
15:12 Select Power Management (SPM)—R/W. This field is not used by AHCI
Interface Power Management Transitions Allowed (IPM)—R/W. Indicates which
power states the PCH is allowed to transition to:
Value Description
0h No interface restrictions
11:8 1h Transitions to the PARTIAL state disabled
2h Transitions to the SLUMBER state disabled
3h Transitions to both PARTIAL and SLUMBER states disabled
All other values reserved
Speed Allowed (SPD)—R/W. Indicates the highest allowable speed of the interface.
This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field.
Value Description
0h No speed negotiation restrictions
1h Limit speed negotiation to Generation 1 communication rate
2h Limit speed negotiation to Generation 2 communication rate
7:4
3h Limit speed negotiation to Generation 3 communication rate
The PCH Supports Gen 1 communication rates (1.5 Gb/s), Gen 2 rates (3.0 Gb/s) and
Gen 3 rates (6.0 Gb/s) (supported speeds are determined by SKU; see Section 1.3)
If software changes SPD after port has been enabled, software is required to perform a
port reset using DET=1h. This field shall remain 1h until set to another value by
software.
Datasheet 625
SATA Controller Registers (D31:F2)
Bit Description
Device Detection Initialization (DET)—R/W. Controls the PCH’s device detection
and interface initialization.
Value Description
0h No device detection or initialization action requested
Perform interface communication initialization sequence to
establish communication. This is functionally equivalent to a hard
1h
reset and results in the interface being reset and communications
re-initialized
4h Disable the Serial ATA interface and put Phy in offline mode
3:0
All other values reserved.
When this field is written to a 1h, the PCH initiates COMRESET and starts the
initialization process. When the initialization is complete, this field shall remain 1h until
set to another value by software.
This field may only be changed to 1h or 4h when PxCMD.ST is 0. Changing this field
while the PCH is running results in undefined behavior.
NOTE: It is permissible to implement any of the Serial ATA defined behaviors for
transmission of COMRESET when DET=1h.
13.4.2.12 PxSERR—Port [5:0] Serial ATA Error Register (D31:F2)
Address Offset: Port 0: ABAR + 130h Attribute: R/WC
Port 1: ABAR + 1B0h
Port 2: ABAR + 230h (if port available; see Section 1.3)
Port 3: ABAR + 2B0h (if port available; see Section 1.3)
Port 4: ABAR + 330h
Port 5: ABAR + 3B0h
Default Value: 00000000h Size: 32 bits
Bits 26:16 of this register contain diagnostic error information for use by diagnostic
software in validating correct operation or isolating failure modes. Bits 11:0 contain
error information used by host software in determining the appropriate response to the
error condition. If one or more of bits 11:8 of this register are set, the controller will
stop the current transfer.
Bit Description
31:27 Reserved
Exchanged (X)—R/WC. When set to 1, this bit indicates that a change in device
presence has been detected since the last time this bit was cleared. This bit shall
26
always be set to 1 anytime a COMINIT signal is received. This bit is reflected in the
P0IS.PCS bit.
Unrecognized FIS Type (F)—R/WC. Indicates that one or more FISs were received
25
by the Transport layer with good CRC, but had a type field that was not recognized.
Transport state transition error (T)—R/WC. Indicates that an error has occurred in
24 the transition from one state to another within the Transport layer since the last time
this bit was cleared.
Link Sequence Error (S): Indicates that one or more Link state machine error
23 conditions was encountered. The Link Layer state machine defines the conditions under
which the link layer detects an erroneous transition.
Handshake (H)—R/WC. Indicates that one or more R_ERR handshake response was
received in response to frame transmission. Such errors may be the result of a CRC
22
error detected by the recipient, a disparity or 8b/10b decoding error, or other error
condition leading to a negative handshake on a transmitted frame.
626 Datasheet
SATA Controller Registers (D31:F2)
Bit Description
CRC Error (C)—R/WC. Indicates that one or more CRC errors occurred with the Link
21
Layer.
20 Disparity Error (D)—R/WC. This field is not used by AHCI.
10b to 8b Decode Error (B)—R/WC. Indicates that one or more 10b to 8b decoding
19
errors occurred.
Comm Wake (W)—R/WC. Indicates that a Comm Wake signal was detected by the
18
Phy.
17 Phy Internal Error (I)—R/WC. Indicates that the Phy detected some internal error.
PhyRdy Change (N)—R/WC. When set to 1, this bit indicates that the internal PhyRdy
signal changed state since the last time this bit was cleared. In the PCH, this bit will be
16 set when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this bit is then
reflected in the PxIS.PRCS interrupt status bit and an interrupt will be generated if
enabled. Software clears this bit by writing a 1 to it.
15:12 Reserved
Internal Error (E)—R/WC. The SATA controller failed due to a master or target abort
11
when attempting to access system memory.
Protocol Error (P)—R/WC. A violation of the Serial ATA protocol was detected.
10
NOTE: The PCH does not set this bit for all protocol violations that may occur on the
SATA link.
Persistent Communication or Data Integrity Error (C)—R/WC. A communication
error that was not recovered occurred that is expected to be persistent. Persistent
9
communications errors may arise from faulty interconnect with the device, from a
device that has been removed or has failed, or a number of other causes.
Transient Data Integrity Error (T)—R/WC. A data integrity error occurred that was
8
not recovered by the interface.
7:2 Reserved.
Recovered Communications Error (M)—R/WC. Communications between the device
and host was temporarily lost but was re-established. This can arise from a device
1 temporarily being removed, from a temporary loss of Phy synchronization, or from
other causes and may be derived from the PhyNRdy signal between the Phy and Link
layers.
Recovered Data Integrity Error (I)—R/WC. A data integrity error occurred that was
0
recovered by the interface through a retry operation or other recovery action.
Datasheet 627
SATA Controller Registers (D31:F2)
13.4.2.13 PxSACT—Port [5:0] Serial ATA Active Register (D31:F2)
Address Offset: Port 0: ABAR + 134h Attribute: R/W
Port 1: ABAR + 1B4h
Port 2: ABAR + 234h (if port available; see Section 1.3)
Port 3: ABAR + 2B4h (if port available; see Section 1.3)
Port 4: ABAR + 334h
Port 5: ABAR + 3B4h
Default Value: 00000000h Size: 32 bits
Bit Description
Device Status (DS)—R/W. System software sets this bit for SATA queuing operations
prior to setting the PxCI.CI bit in the same command slot entry. This field is cleared
31:0 using the Set Device Bits FIS.
This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is
cleared by software, and as a result of a COMRESET or SRST.
13.4.2.14 PxCI—Port [5:0] Command Issue Register (D31:F2)
Address Offset: Port 0: ABAR + 138h Attribute: R/W
Port 1: ABAR + 1B8h
Port 2: ABAR + 238h (if port available; see Section 1.3)
Port 3: ABAR + 2B8h (if port available; see Section 1.3)
Port 4: ABAR + 338h
Port 5: ABAR + 3B8h
Default Value: 00000000h Size: 32 bits
Bit Description
Commands Issued (CI)—R/W. This field is set by software to indicate to the PCH that
a command has been built-in system memory for a command slot and may be sent to
the device. When the PCH receives a FIS which clears the BSY and DRQ bits for the
31:0 command, it clears the corresponding bit in this register for that command slot. Bits in
this field shall only be set to 1 by software when PxCMD.ST is set to 1.
This field is also cleared when PxCMD.ST (ABAR+118h/198h/218h/298h:bit 0) is
cleared by software.
§§
628 Datasheet
SATA Controller Registers (D31:F5)
14 SATA Controller Registers
(D31:F5)
14.1 PCI Configuration Registers (SATA–D31:F5)
Note: Address locations that are not shown should be treated as Reserved.
All of the SATA registers are in the core well. None of the registers can be locked.
Table 14-1. SATA Controller PCI Register Address Map (SATA–D31:F5) (Sheet 1 of 2)
Offset Mnemonic Register Name Default Attribute
00h–01h VID Vendor Identification 8086h RO
See register
02h–03h DID Device Identification RO
description
04h–05h PCICMD PCI Command 0000h R/W, RO
06h–07h PCISTS PCI Status 02B0h R/WC, RO
See register
08h RID Revision Identification RO
description
See
See register
09h PI Programming Interface register
description
description
See
See register
0Ah SCC Sub Class Code register
description
description
0Bh BCC Base Class Code 01h RO
10h–13h PCMD_BAR Primary Command Block Base Address 00000001h R/W, RO
14h–17h PCNL_BAR Primary Control Block Base Address 00000001h R/W, RO
Secondary Command Block Base
18h–1Bh SCMD_BAR 00000001h R/W, RO
Address
1Ch–1Fh SCNL_BAR Secondary Control Block Base Address 00000001h R/W, RO
20h–23h BAR Legacy Bus Master Base Address 00000001h R/W, RO
See
Serial ATA Index / Data Pair Base
24h–27h SIDPBA 00000000h register
Address
description
2Ch–2Dh SVID Subsystem Vendor Identification 0000h R/WO
2Eh–2Fh SID Subsystem Identification 0000h R/WO
34h CAP Capabilities Pointer 80h RO
3Ch INT_LN Interrupt Line 00h R/W
See register
3Dh INT_PN Interrupt Pin RO
description
40h–41h IDE_TIM Primary IDE Timing 0000h R/W
42h–43h IDE_TIM Secondary IDE Timing 0000h R/W
44h SIDETIM Slave IDE Timing 00h R/W
48h SDMA_CNT Synchronous DMA Control 00h R/W
Datasheet 629
SATA Controller Registers (D31:F5)
Table 14-1. SATA Controller PCI Register Address Map (SATA–D31:F5) (Sheet 2 of 2)
Offset Mnemonic Register Name Default Attribute
4Ah–4Bh SDMA_TIM Synchronous DMA Timing 0000h R/W
54h–57h IDE_CONFIG IDE I/O Configuration 00000000h R/W
PCI Power Management Capability See register
70h–71h PID RO
Identification description
72h–73h PC PCI Power Management Capabilities 4003h RO
PCI Power Management Control and R/W, RO,
74h–75h PMCS 0008h
Status R/WC
90h–91h MAP Address Map 0000h R/W
R/W, RO,
92h–93h PCS Port Control and Status 0000h
R/WC
A8h–ABh SATACR0 SATA Capability Register 0 0010B012h RO, R/WO
ACh–AFh SATACR1 SATA Capability Register 1 00000048h RO
B0h–B1h FLRCID FLR Capability ID 0009h RO
B2h–B3h FLRCLV FLR Capability Length and Value 2006h RO
B4h–B5h FLRCTRL FLR Control 0000h R/W, RO
C0h ATC APM Trapping Control 00h R/W
C4h ATS APM Trapping Status 00h R/WC
NOTE: The PCH SATA controller is not arbitrated as a PCI device; therefore, it does not need a
master latency timer.
14.1.1 VID—Vendor Identification Register (SATA—D31:F5)
Offset Address: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bit
Lockable: No Power Well: Core
Bit Description
15:0 Vendor ID—RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
14.1.2 DID—Device Identification Register (SATA—D31:F5)
Offset Address: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bit
Lockable: No Power Well: Core
Bit Description
Device ID—RO. This is a 16-bit value assigned to the PCH SATA controller.
15:0
NOTE: The value of this field will change dependent upon the value of the MAP
Register. See Section 1.3 for the value of the RID Register and Section 14.1.27.
630 Datasheet
SATA Controller Registers (D31:F5)
14.1.3 PCICMD—PCI Command Register (SATA–D31:F5)
Address Offset: 04h–05h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved
Interrupt Disable—R/W. This disables pin-based INTx# interrupts. This bit has no
effect on MSI operation.
10 0 = Internal INTx# messages are generated if there is an interrupt and MSI is not
enabled.
1 = Internal INTx# messages will not be generated.
9 Fast Back to Back Enable (FBE)—RO. Hardwired to 0.
8 SERR# Enable (SERR_EN)—RO. Hardwired to 0.
7 Wait Cycle Control (WCC)—RO. Hardwired to 0.
Parity Error Response (PER)—R/W.
0 = Disabled. SATA controller will not generate PERR# when a data parity error is
6
detected.
1 = Enabled. SATA controller will generate PERR# when a data parity error is detected.
5 VGA Palette Snoop (VPS)—RO. Hardwired to 0.
4 Postable Memory Write Enable (PMWE)—RO. Hardwired to 0.
3 Special Cycle Enable (SCE)—RO. Hardwired to 0.
Bus Master Enable (BME)—R/W. This bit controls the PCH ability to act as a PCI
2 master for IDE Bus Master transfers. This bit does not impact the generation of
completions for split transaction commands.
Memory Space Enable (MSE)—RO. This controller does not support AHCI; therefore,
1
no memory space is required.
I/O Space Enable (IOSE)—R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as
0 well as the Bus Master I/O registers.
1 = Enable. The Base Address register for the Bus Master registers should be
programmed before this bit is set.
Datasheet 631
SATA Controller Registers (D31:F5)
14.1.4 PCISTS—PCI Status Register (SATA–D31:F5)
Address Offset: 06h–07h Attribute: R/WC, RO
Default Value: 02B0h Size: 16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit Description
Detected Parity Error (DPE)—R/WC.
15 0 = No parity error detected by SATA controller.
1 = SATA controller detects a parity error on its interface.
14 Signaled System Error (SSE)—RO. Hardwired to 0.
Received Master Abort (RMA)—R/WC.
13 0 = Master abort Not generated.
1 = SATA controller, as a master, generated a master abort.
12 Reserved
11 Signaled Target Abort (STA)—RO. Hardwired to 0.
DEVSEL# Timing Status (DEV_STS)—RO.
10:9
01 = Hardwired; Controls the device select time for the SATA controller’s PCI interface.
Data Parity Error Detected (DPED)—R/WC. For PCH, this bit can only be set on
read completions received from SiBUS where there is a parity error.
8 1 = SATA controller, as a master, either detects a parity error or sees the parity error
line asserted, and the parity error response bit (bit 6 of the command register) is
set.
7 Fast Back to Back Capable (FB2BC)—RO. Hardwired to 1.
6 User Definable Features (UDF)—RO. Hardwired to 0.
5 66MHz Capable (66MHZ_CAP)—RO. Hardwired to 1.
Capabilities List (CAP_LIST)—RO. This bit indicates the presence of a capabilities
4 list. The minimum requirement for the capabilities list must be PCI power management
for the SATA controller.
Interrupt Status (INTS)—RO. Reflects the state of INTx# messages, IRQ14 or
IRQ15.
3 0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the
command register [offset 04h]).
1 = Interrupt is to be asserted
2:0 Reserved
14.1.5 RID—Revision Identification Register (SATA—D31:F5)
Offset Address: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
Bit Description
Revision ID—RO. This field indicates the device specific revision identifier. See
7:0
Section 1.3 for the value of the RID Register.
632 Datasheet
SATA Controller Registers (D31:F5)
14.1.6 PI—Programming Interface Register (SATA–D31:F5)
Address Offset: 09h Attribute: RO
Default Value: 85h Size: 8 bits
When SCC = 01h
Bit Description
7 This read-only bit is a 1 to indicate that the PCH supports bus master operation
6:4 Reserved
Secondary Mode Native Capable (SNC)—RO. Indicates whether or not the
secondary channel has a fixed mode of operation.
3
0 = Indicates the mode is fixed and is determined by the (read-only) value of bit 2.
This bit will always return 0.
Secondary Mode Native Enable (SNE)—RO.
Determines the mode that the secondary channel is operating in.
2
1 = Secondary controller operating in native PCI mode.
This bit will always return 1.
Primary Mode Native Capable (PNC)—RO. Indicates whether or not the primary
channel has a fixed mode of operation.
1
0 = Indicates the mode is fixed and is determined by the (read-only) value of bit 0.
This bit will always return 0.
Primary Mode Native Enable (PNE)—RO.
Determines the mode that the primary channel is operating in.
0
1 = Primary controller operating in native PCI mode.
This bit will always return 1.
14.1.7 SCC—Sub Class Code Register (SATA–D31:F5)
Address Offset: 0Ah Attribute: RO
Default Value: 01h Size: 8 bits
Bit Description
Sub Class Code (SCC)—RO.
7:0
The value of this field determines whether the controller supports legacy IDE mode.
14.1.8 BCC—Base Class Code Register
(SATA–D31:F5SATA–D31:F5)
Address Offset: 0Bh Attribute: RO
Default Value: 01h Size: 8 bits
Bit Description
Base Class Code (BCC)—RO.
7:0
01h = Mass storage device
Datasheet 633
SATA Controller Registers (D31:F5)
14.1.9 PCMD_BAR—Primary Command Block Base Address
Register (SATA–D31:F5)
Address Offset: 10h–13h Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
Base Address—R/W. This field provides the base address of the I/O space (8
15:3
consecutive I/O locations).
2:1 Reserved
Resource Type Indicator (RTE)—RO. Hardwired to 1 to indicate a request for I/O
0
space.
NOTE: This 8-byte I/O space is used in native mode for the Primary Controller’s Command Block.
14.1.10 PCNL_BAR—Primary Control Block Base Address Register
(SATA–D31:F5)
Address Offset: 14h–17h Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
Base Address—R/W. This field provides the base address of the I/O space (4
15:2
consecutive I/O locations).
1 Reserved
Resource Type Indicator (RTE)—RO. Hardwired to 1 to indicate a request for I/O
0
space.
NOTE: This 4-byte I/O space is used in native mode for the Primary Controller’s Command Block.
634 Datasheet
SATA Controller Registers (D31:F5)
14.1.11 SCMD_BAR—Secondary Command Block Base Address
Register (SATA D31:F5)
Address Offset: 18h–1Bh Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
Base Address—R/W. This field provides the base address of the I/O space (8
15:3
consecutive I/O locations).
2:1 Reserved
Resource Type Indicator (RTE)—RO. Hardwired to 1 to indicate a request for I/O
0
space.
NOTE: This 8-byte I/O space is used in native mode for the Secondary Controller’s Command
Block.
14.1.12 SCNL_BAR—Secondary Control Block Base Address
Register (SATA D31:F5)
Address Offset: 1Ch–1Fh Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
Base Address—R/W. This field provides the base address of the I/O space (4
15:2
consecutive I/O locations).
1 Reserved
Resource Type Indicator (RTE)—RO. Hardwired to 1 to indicate a request for I/O
0
space.
NOTE: This 4-byte I/O space is used in native mode for the Secondary Controller’s Command
Block.
Datasheet 635
SATA Controller Registers (D31:F5)
14.1.13 BAR—Legacy Bus Master Base Address Register
(SATA–D31:F5)
Address Offset: 20h–23h Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
The Bus Master IDE interface function uses Base Address register 5 to request a 16-
byte I/O space to provide a software interface to the Bus Master functions. Only
12 bytes are actually used (6 bytes for primary, 6 bytes for secondary). Only bits
[15:4] are used to decode the address.
Bit Description
31:16 Reserved
Base Address—R/W. This field provides the base address of the I/O space (16
15:5
consecutive I/O locations).
Base Address 4 (BA4)—R/W.
4
When SCC is 01h, this bit will be R/W resulting in requesting 16B of I/O space.
3:1 Reserved
Resource Type Indicator (RTE)—RO. Hardwired to 1 to indicate a request for I/O
0
space.
14.1.14 SIDPBA—SATA Index/Data Pair Base Address Register
(SATA–D31:F5)
Address Offset: 24h–27h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
When SCC is 01h
When the programming interface is IDE, the register represents an I/O BAR allocating
16B of I/O space for the I/O mapped registers defined in Section 14.3. While 16B of
locations are allocated, some maybe reserved.
Bit Description
31:16 Reserved
15:4 Base Address (BA)—R/W. Base address of register I/O space
3:1 Reserved
Resource Type Indicator (RTE)—RO. Hardwired to 1 to indicate a request for I/O
0
space.
636 Datasheet
SATA Controller Registers (D31:F5)
14.1.15 SVID—Subsystem Vendor Identification Register
(SATA–D31:F5)
Address Offset: 2Ch–2Dh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Core
Function Level Reset: No
Bit Description
Subsystem Vendor ID (SVID)—R/WO. Value is written by BIOS. No hardware action
15:0
taken on this value.
14.1.16 SID—Subsystem Identification Register (SATA–D31:F5)
Address Offset: 2Eh–2Fh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Core
Bit Description
Subsystem ID (SID)—R/WO. Value is written by BIOS. No hardware action taken on
15:0
this value.
14.1.17 CAP—Capabilities Pointer Register (SATA–D31:F5)
Address Offset: 34h Attribute: RO
Default Value: 70h Size: 8 bits
Bit Description
Capabilities Pointer (CAP_PTR)—RO. Indicates that the first capability pointer offset
7:0 is 70h if the Sub Class Code (SCC) (Dev 31:F2:0Ah) is configure as IDE mode (value of
01).
14.1.18 INT_LN—Interrupt Line Register (SATA–D31:F5)
Address Offset: 3Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Function Level Reset: No
Bit Description
Interrupt Line—R/W. This field is used to communicate to software the interrupt line
7:0
that the interrupt pin is connected to. These bits are not reset by FLR.
14.1.19 INT_PN—Interrupt Pin Register (SATA–D31:F5)
Address Offset: 3Dh Attribute: RO
Default Value: See Register Description Size: 8 bits
Bit Description
Interrupt Pin—RO. This reflects the value of D31IP.SIP1 (Chipset Config
7:0
Registers:Offset 3100h:bits 11:8).
Datasheet 637
SATA Controller Registers (D31:F5)
14.1.20 IDE_TIM—IDE Timing Register (SATA–D31:F5)
Address Offset: Primary: 40h–41h Attribute: R/W
Secondary: 42h–43h
Default Value: 0000h Size: 16 bits
Bits 14:12 and 9:0 of this register are R/W to maintain software compatibility. These bits
have no effect on hardware.
Bit Description
IDE Decode Enable (IDE)—R/W. Individually enable/disable the Primary or
Secondary decode.
15
0 = Disable.
1 = Enables the PCH to decode the associated Command Block and Control Block.
IDE_TIM Field 2—R/W. This field is R/W to maintain software compatibility. This field
14:12
has no effect on hardware.
11:10 Reserved
IDE_TIM Field 1—R/W. This field is R/W to maintain software compatibility. This field
9:0
has no effect on hardware.
14.1.21 SDMA_CNT—Synchronous DMA Control Register
(SATA–D31:F5)
Address Offset: 48h Attribute: R/W
Default Value: 00h Size: 8 bits
Note: This register is R/W to maintain software compatibility. These bits have no effect on
hardware.
Bit Description
7:3 Reserved
Secondary Master ATAxx Enable (SDAE0)—R/W.
2 0 = Disable (default)
1 = Enable DMA timing modes for the secondary master device.
1 Reserved
Primary Master ATAxx Enable (PDAE0)—R/W.
0 0 = Disable (default)
1 = Enable DMA timing modes for the primary master device
638 Datasheet
SATA Controller Registers (D31:F5)
14.1.22 SDMA_TIM—Synchronous DMA Timing Register
(SATA–D31:F5)
Address Offset: 4Ah–4Bh Attribute: R/W
Default Value: 0000h Size: 16 bits
Note: This register is R/W to maintain software compatibility. These bits have no effect on
hardware.
Bit Description
15:10 Reserved
SDMA_TIM Field 2—R/W. This field is R/W to maintain software compatibility. This
9:8
field has no effect on hardware.
7:2 Reserved
SDMA_TIM Field 1—R/W. This field is R/W to maintain software compatibility. This
1:0
field has no effect on hardware.
14.1.23 IDE_CONFIG—IDE I/O Configuration Register
(SATA–D31:F5)
Address Offset: 54h–57h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: This register is R/W to maintain software compatibility. These bits have no effect on
hardware.
Bit Description
31:24 Reserved
IDE_CONFIG Field 6—R/W. This field is R/W to maintain software compatibility. This
23:16
field has no effect on hardware.
15 Reserved
IDE_CONFIG Field 5—R/W. This field is R/W to maintain software compatibility. This
14
field has no effect on hardware.
13 Reserved
IDE_CONFIG Field 4—R/W. This field is R/W to maintain software compatibility. This
12
field has no effect on hardware.
11:8 Reserved
IDE_CONFIG Field 3—R/W. This field is R/W to maintain software compatibility. This
7:4
field has no effect on hardware.
3 Reserved
IDE_CONFIG Field 2—R/W. This field is R/W to maintain software compatibility. This
2
field has no effect on hardware.
1 Reserved
IDE_CONFIG Field 1—R/W. This field is R/W to maintain software compatibility. This
0
field has no effect on hardware.
Datasheet 639
SATA Controller Registers (D31:F5)
14.1.24 PID—PCI Power Management Capability Identification
Register (SATA–D31:F5)
Address Offset: 70h–71h Attribute: RO
Default Value: B001h Size: 16 bits
Bits Description
Next Capability (NEXT)—RO. When SCC is 01h, this field will be B0h indicating the
15:8
next item is FLR Capability Pointer in the list.
7:0 Capability ID (CID)—RO. Indicates that this pointer is a PCI power management.
14.1.25 PC—PCI Power Management Capabilities Register
(SATA–D31:F5)
Address Offset: 72h–73h Attribute: RO
Default Value: 4003h Size: 16 bits
Bits Description
PME Support (PME_SUP)—RO. By default with SCC = 01h, the default value of 00000
15:11
indicates no PME support in IDE mode.
10 D2 Support (D2_SUP)—RO. Hardwired to 0. The D2 state is not supported
9 D1 Support (D1_SUP)—RO. Hardwired to 0. The D1 state is not supported
Auxiliary Current (AUX_CUR)—RO. PME# from D3COLD state is not supported, therefore
8:6
this field is 000b.
Device Specific Initialization (DSI)—RO. Hardwired to 0 to indicate that no device-
5
specific initialization is required.
4 Reserved
PME Clock (PME_CLK)—RO. Hardwired to 0 to indicate that PCI clock is not required to
3
generate PME#.
Version (VER)—RO. Hardwired to 011 to indicates support for Revision 1.2 of the PCI
2:0
Power Management Specification.
640 Datasheet
SATA Controller Registers (D31:F5)
14.1.26 PMCS—PCI Power Management Control and Status
Register (SATA–D31:F5)
Address Offset: 74h–75h Attribute: RO, R/W, R/WC
Default Value: 0008h Size: 16 bits
Function Level Reset: No (Bits 8 and 15 only)
Bits Description
PME Status (PMES)—R/WC. Bit is set when a PME event is to be requested, and if this
bit and PMEE is set, a PME# will be generated from the SATA controller.
15
NOTE: When SCC=01h this bit will be RO 0. Software is advised to clear PMEE together
with PMES prior to changing SCC through MAP.SMS.
This bit is not reset by Function Level Reset.
14:9 Reserved
PME Enable (PMEE)—R/W. When SCC is not 01h, this bit R/W. When set, the SATA
controller generates PME# form D3HOT on a wake event.
8 NOTE: When SCC=01h, this bit will be RO 0. Software is advised to clear PMEE together
with PMES prior to changing SCC through MAP.SMS.
This bit is not reset by Function Level Reset.
7:4 Reserved
No Soft Reset (NSFRST)—RO. These bits are used to indicate whether devices
transitioning from D3HOT state to D0 state will perform an internal reset.
0 = Device transitioning from D3HOT state to D0 state perform an internal reset.
1 = Device transitioning from D3HOT state to D0 state do not perform an internal reset.
3 Configuration content is preserved. Upon transition from the D3HOT state to D0 state
initialized state, no additional operating system intervention is required to preserve
configuration context beyond writing to the PowerState bits.
Regardless of this bit, the controller transition from D3HOT state to D0 state by a system
or bus segment reset will return to the state D0 uninitialized with only PME context
preserved if PME is supported and enabled.
2 Reserved
Power State (PS)—R/W. These bits are used both to determine the current power
state of the SATA controller and to set a new power state.
00 = D0 state
1:0
11 = D3HOT state
When in the D3HOT state, the controller’s configuration space is available, but the I/O
and memory spaces are not. Additionally, interrupts are blocked.
Datasheet 641
SATA Controller Registers (D31:F5)
14.1.27 MAP—Address Map Register (SATA–D31:F5)
Address Offset: 90h–91h Attribute: R/W, R/WO, RO
Default Value: 0000h Size: bits
Function Level Reset: No (Bits 9:8 only)
Bits Description
15:8 Reserved
SATA Mode Select (SMS)—R/W. Software programs these bits to control the mode in
which the SATA Controller should operate.
7:6
00b = IDE Mode
All other combinations are reserved.
5:2 Reserved
1:0 Map Value (MV)—Reserved.
14.1.28 PCS—Port Control and Status Register (SATA–D31:F5)
Address Offset: 92h–93h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Function Level Reset: No
By default, the SATA ports are set to the disabled state (bits [5:0] = 0). When enabled
by software, the ports can transition between the on, partial, and slumber states and
can detect devices. When disabled, the port is in the “off” state and cannot detect any
devices.
If an AHCI-aware or RAID enabled operating system is being booted, then system BIOS
shall insure that all supported SATA ports are enabled prior to passing control to the
OS. Once the AHCI aware OS is booted, it becomes the enabling/disabling policy owner
for the individual SATA ports. This is accomplished by manipulating a port PxSCTL and
PxCMD fields. Because an AHCI or RAID aware OS will typically not have knowledge of
the PxE bits and because the PxE bits act as master on/off switches for the ports, pre-
boot software must insure that these bits are set to 1 prior to booting the OS,
regardless as to whether or not a device is currently on the port.
Bits Description
15:10 Reserved
Port 5 Present (P5P)—RO. The status of this bit may change at any time. This bit is
cleared when the port is disabled using P1E. This bit is not cleared upon surprise
9 removal of a device.
0 = No device detected.
1 = The presence of a device on Port 1 has been detected.
Port 4 Present (P4P)—RO. The status of this bit may change at any time. This bit is
cleared when the port is disabled using P0E. This bit is not cleared upon surprise
8 removal of a device.
0 = No device detected.
1 = The presence of a device on Port 0 has been detected.
7:2 Reserved
642 Datasheet
SATA Controller Registers (D31:F5)
Bits Description
Port 5 Enabled (P5E)—R/W.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
1 1 = Enabled. The port can transition between the on, partial, and slumber states and
can detect devices.
This bit is read-only 0 when MAP.SPD[1]= 1 pr is a PCIe Port.
Port 4 Enabled (P4E)—R/W.
0 = Disabled. The port is in the ‘off’ state and cannot detect any devices.
0 1 = Enabled. The port can transition between the on, partial, and slumber states and
can detect devices.
This bit is read-only 0 when MAP.SPD[0]= 1 or is a PCIe Port.
14.1.29 SATACR0—SATA Capability Register 0 (SATA–D31:F5)
Address Offset: A8h–ABh Attribute: RO, R/WO
Default Value: 0010B012h Size: 32 bits
Function Level Reset: No (Bits 15:8 only)
When SCC is 01h, this register is read-only 0.
Bit Description
31:24 Reserved
Major Revision (MAJREV)—RO. Major revision number of the SATA Capability Pointer
23:20
implemented.
Minor Revision (MINREV)—RO. Minor revision number of the SATA Capability Pointer
19:16
implemented.
15:8 Next Capability Pointer (NEXT)—R/WO. Points to the next capability structure.
Capability ID (CAP)—RO. The value of 12h has been assigned by the PCI SIG to
7:0
designate the SATA capability pointer.
14.1.30 SATACR1—SATA Capability Register 1 (SATA–D31:F5)
Address Offset: ACh–AFh Attribute: RO
Default Value: 00000048h Size: 32 bits
When SCC is 01h, this register is read-only 0.
Bit Description
31:16 Reserved
BAR Offset (BAROFST)—RO. Indicates the offset into the BAR where the index/Data
pair are located (in DWord granularity). The index and Data I/O registers are located at
15:4
offset 10h within the I/O space defined by LBAR (BAR4). A value of 004h indicates
offset 10h.
BAR Location (BARLOC)—RO. Indicates the absolute PCI Configuration Register
address of the BAR containing the Index/Data pair (in DWord granularity). The Index
3:0
and Data I/O registers reside within the space defined by LBAR (BAR4) in the SATA
controller. a value of 8h indicates and offset of 20h, which is LBAR (BAR4).
Datasheet 643
SATA Controller Registers (D31:F5)
14.1.31 FLRCID—FLR Capability ID Register (SATA–D31:F5)
Address Offset: B0h–B1h Attribute: RO
Default Value: 0009h Size: 16 bits
Bit Description
Next Capability Pointer—RO. A value of 00h indicates the final item in the Capability
15:8
List.
Capability ID—RO. The value of this field depends on the FLRCSSECL bit.
7:0 If FLRCSSEL = 0, this field is 13h
If FLRCSSEL = 1, this field is 00h.
14.1.32 FLRCLV—FLR Capability Length and
Value Register (SATA–D31:F5)
Address Offset: B2h–B3h Attribute: RO, R/WO
Default Value: 2006h Size: 16 bits
Function Level Reset:No (Bits 9:8 only)
When FLRCSSEL = 0, this register is RO.
Bit Description
15:10 Reserved
9 FLR Capability—R/WO. This field indicates support for Function Level Reset.
TXP Capability—R/WO. This field indicates support for the Transactions Pending (TXP)
8
bit. TXP must be supported if FLR is supported.
Capability Length—RO. This field indicates the number of bytes of the Vendor Specific
7:0 capability as required by the PCI specification. It has the value of 06h for FLR
Capability.
14.1.33 FLRCTRL—FLR Control Register (SATA–D31:F5)
Address Offset: B4h–B5h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:9 Reserved
Transactions Pending (TXP)—RO.
8 0 = Completions for all Non-Posted requests have been received by the controller.
1 = Controller has issued Non-Posted request which has not been completed.
7:1 Reserved
0 Initiate FLR—R/W. Used to initiate FLR transition. A write of 1 indicates FLR transition.
644 Datasheet
SATA Controller Registers (D31:F5)
14.1.34 ATC—APM Trapping Control Register (SATA–D31:F5)
Address Offset: C0h Attribute: R/W
Default Value: 00h Size: 8 bits
Note: This SATA controller does not support legacy I/O access. Therefore, this register is
reserved. Software shall not change the default values of the register; otherwise, the
result will be undefined.
Bit Description
7:0 Reserved
14.1.35 ATC—APM Trapping Control Register (SATA–D31:F5)
Address Offset: C4h Attribute: R/WC
Default Value: 00h Size: 8 bits
Note: This SATA controller does not support legacy I/O access. Therefore, this register is
reserved. Software shall not change the default values of the register; otherwise the
result will be undefined.
Bit Description
7:0 Reserved
14.2 Bus Master IDE I/O Registers (D31:F5)
The bus master IDE function uses 16 bytes of I/O space, allocated using the BAR
register, located in D31:F2 Configuration space, offset 20h. All bus master IDE I/O
space registers can be accessed as byte, word, or DWord quantities. Reading reserved
bits returns an indeterminate, inconsistent value, and writes to reserved bits have no
affect (but should not be attempted). These registers are only used for legacy
operation. Software must not use these registers when running AHCI. The description
of the I/O registers is shown in Table 14-2.
Table 14-2. Bus Master IDE I/O Register Address Map
BAR+
Mnemonic Register Default Attribute
Offset
00 BMICP Command Register Primary 00h R/W
01 — Reserved — RO
R/W, R/WC,
02 BMISP Bus Master IDE Status Register Primary 00h
RO
03 — Reserved — RO
Bus Master IDE Descriptor Table Pointer
04–07 BMIDP xxxxxxxxh R/W
Primary
08 BMICS Command Register Secondary 00h R/W
09 — Reserved — RO
R/W, R/WC,
0Ah BMISS Bus Master IDE Status Register Secondary 00h
RO
0Bh — Reserved — RO
Bus Master IDE Descriptor Table Pointer
0Ch–0Fh BMIDS xxxxxxxxh R/W
Secondary
Datasheet 645
SATA Controller Registers (D31:F5)
14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F5)
Address Offset: Primary: BAR + 00h Attribute: R/W
Secondary: BAR + 08h
Default Value: 00h Size: 8 bits
Bit Description
7:4 Reserved
Read / Write Control (R/WC)—R/W. This bit sets the direction of the bus master
transfer: This bit must NOT be changed when the bus master function is active.
3
0 = Memory reads
1 = Memory writes
2:1 Reserved
Start/Stop Bus Master (START)—R/W.
0 = All state information is lost when this bit is cleared. Master mode operation cannot
be stopped and then resumed. If this bit is reset while bus master operation is still
active (that is, the Bus Master IDE Active bit (D31:F5:BAR + 02h, bit 0) of the Bus
Master IDE Status register for that IDE channel is set) and the drive has not yet
finished its data transfer (the Interrupt bit in the Bus Master IDE Status register for
that IDE channel is not set), the bus master command is said to be aborted and
data transferred from the drive may be discarded instead of being written to
system memory.
1 = Enables bus master operation of the controller. Bus master operation does not
actually start unless the Bus Master Enable bit (D31:F5:04h, bit 2) in PCI
configuration space is also set. Bus master operation begins when this bit is
0
detected changing from 0 to 1. The controller will transfer data between the IDE
device and memory only when this bit is set. Master operation can be halted by
writing a 0 to this bit.
NOTE: This bit is intended to be cleared by software after the data transfer is
completed, as indicated by either the Bus Master IDE Active bit being cleared or
the Interrupt bit of the Bus Master IDE Status register for that IDE channel
being set, or both. Hardware does not clear this bit automatically. If this bit is
cleared to 0 prior to the DMA data transfer being initiated by the drive in a
device to memory data transfer, then the PCH will not send DMAT to terminate
the data transfer. SW intervention (such as, sending SRST) is required to reset
the interface in this condition.
646 Datasheet
SATA Controller Registers (D31:F5)
14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F5)
Address Offset: Primary: BAR + 02h Attribute: R/W, R/WC, RO
Secondary: BAR + 0Ah
Default Value: 00h Size: 8 bits
Bit Description
PRD Interrupt Status (PRDIS)—R/WC.
0 = Software clears this bit by writing a 1 to it.
7
1 = This bit is set when the host controller execution of a PRD that has its PRD_INT bit
set.
6 Reserved
Drive 0 DMA Capable—R/W.
0 = Not Capable
1 = Capable. Set by device dependent code (BIOS or device driver) to indicate that
5
drive 0 for this channel is capable of DMA transfers, and that the controller has
been initialized for optimum performance. The PCH does not use this bit. It is
intended for systems that do not attach BMIDE to the PCI bus.
4:3 Reserved
Interrupt—R/WC.
0 = Software clears this bit by writing a 1 to it.
2 1 = Set when a device FIS is received with the ‘I’ bit set, provided that software has not
disabled interrupts using the IEN bit of the Device Control Register (see chapter 5
of the Serial ATA Specification, Revision 1.0a).
Error—R/WC.
0 = Software clears this bit by writing a 1 to it.
1
1 = This bit is set when the controller encounters a target abort or master abort when
transferring data on PCI.
Bus Master IDE Active (ACT)—RO.
0 = This bit is cleared by the PCH when the last transfer for a region is performed,
where EOT for that region is set in the region descriptor. It is also cleared by the
PCH when the Start Bus Master bit (D31:F5:BAR+ 00h, bit 0) is cleared in the
0
Command register. When this bit is read as a 0, all data transferred from the drive
during the previous bus master command is visible in system memory, unless the
bus master command was aborted.
1 = Set by the PCH when the Start bit is written to the Command register.
14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F5)
Address Offset: Primary: BAR + 04h–07h Attribute: R/W
Secondary: BAR + 0Ch–0Fh
Default Value: All bits undefined Size: 32 bits
Bit Description
Address of Descriptor Table (ADDR)—R/W. The bits in this field correspond to bits
[31:2] of the memory location of the Physical Region Descriptor (PRD). The Descriptor
31:2
Table must be DWord-aligned. The Descriptor Table must not cross a 64-K boundary in
memory.
1:0 Reserved
Datasheet 647
SATA Controller Registers (D31:F5)
14.3 Serial ATA Index/Data Pair Superset Registers
All of these I/O registers are in the core well. They are exposed only when SCC is 01h
(that is, IDE programming interface) and the controller is not in combined mode. These
are Index/Data Pair registers that are used to access the SerialATA superset registers
(SerialATA Status, SerialATA Control and SerialATA Error). The I/O space for these
registers is allocated through SIDPBA. Locations with offset from 08h to 0Fh are
reserved for future expansion. Software-write operations to the reserved locations shall
have no effect while software-read operations to the reserved locations shall return 0.
14.3.1 SINDX—SATA Index Register (D31:F5)
Address Offset: SIDPBA + 00h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: These are Index/Data Pair Registers that are used to access the SSTS, SCTL, and
SERR. The I/O space for these registers is allocated through SIDPBA.
Bit Description
31:16 Reserved
Port Index (PIDX)—R/W. This Index field is used to specify the port of the SATA
controller at which the port-specific SSTS, SCTL, and SERR registers are located.
15:8 00h = Primary Master (Port 4)
02h = Secondary Master (Port 5)
All other values are Reserved.
Register Index (RIDX)—R/W. This Index field is used to specify one out of three
registers currently being indexed into.
00h = SSTS
7:0
01h = SCTL
02h = SERR
All other values are Reserved.
14.3.2 SDATA—SATA Index Data Register (D31:F5)
Address Offset: SIDPBA + 04h Attribute: R/W
Default Value: All bits undefined Size: 32 bits
Note: These are Index/Data Pair Registers that are used to access the SSTS, SCTL, and
SERR. The I/O space for these registers is allocated through SIDPBA.
Bit Description
Data (DATA)—R/W. This Data register is a “window” through which data is read or
written to the memory mapped registers. A read or write to this Data register triggers a
corresponding read or write to the memory mapped register pointed to by the Index
register. The Index register must be setup prior to the read or write to this Data
31:0 register.
A physical register is not actually implemented as the data is actually stored in the
memory mapped registers.
Since this is not a physical register, the “default” value is the same as the default value
of the register pointed to by Index.
648 Datasheet
SATA Controller Registers (D31:F5)
14.3.2.1 PxSSTS—Serial ATA Status Register (D31:F5)
Address Offset: Attribute: RO
Default Value: 00000000h Size: 32 bits
SDATA when SINDX.RIDX is 00h.
This is a 32-bit register that conveys the current state of the interface and host. The
PCH updates it continuously and asynchronously. When the PCH transmits a COMRESET
to the device, this register is updated to its reset values.
Bit Description
31:12 Reserved
Interface Power Management (IPM)—RO. Indicates the current interface state:
Value Description
0h Device not present or communication not established
11:8 1h Interface in active state
2h Interface in PARTIAL power management state
6h Interface in SLUMBER power management state
All other values reserved.
Current Interface Speed (SPD)—RO. Indicates the negotiated interface
communication speed.
Value Description
0h Device not present or communication not established
1h Generation 1 communication rate negotiated
7:4 2h Generation 2 communication rate negotiated
3h Generation 3 communication rate negotiated
All other values reserved.
The PCH Supports Gen 1 communication rates (1.5 Gb/s), Gen 2 rates
(3.0 Gb/s) and Gen 3 rates (6.0 Gb/s).
Device Detection (DET)—RO. Indicates the interface device detection and Phy state:
Value Description
0h No device detected and Phy communication not established
1h Device presence detected but Phy communication not established
3:0
3h Device presence detected and Phy communication established
Phy in offline mode as a result of the interface being disabled or
4h
running in a BIST loopback mode
All other values reserved.
Datasheet 649
SATA Controller Registers (D31:F5)
14.3.2.2 PxSCTL—Serial ATA Control Register (D31:F5)
Address Offset: Attribute: R/W, RO
Default Value: 00000004h Size: 32 bits
SDATA when SINDX.RIDX is 01h.
This is a 32-bit read-write register by which software controls SATA capabilities. Writes
to the SControl register result in an action being taken by the PCH or the interface.
Reads from the register return the last value written to it.
Bit Description
31:20 Reserved
19:16 Port Multiplier Port (PMP)—RO. This field is not used by AHCI.
15:12 Select Power Management (SPM)—RO. This field is not used by AHCI.
Interface Power Management Transitions Allowed (IPM)—R/W. Indicates which
power states the PCH is allowed to transition to:
Value Description
0h No interface restrictions
11:8
1h Transitions to the PARTIAL state disabled
2h Transitions to the SLUMBER state disabled
3h Transitions to both PARTIAL and SLUMBER states disabled
All other values reserved
Speed Allowed (SPD)—R/W. Indicates the highest allowable speed of the interface.
This speed is limited by the CAP.ISS (ABAR+00h:bit 23:20) field.
Value Description
0h No speed negotiation restrictions
1h Limit speed negotiation to Generation 1 communication rate
7:4
2h Limit speed negotiation to Generation 2 communication rate
3h Limit speed negotiation to Generation 3 communication rate
All other values reserved.
The PCH Supports Gen 1 communication rates (1.5 Gb/s), Gen 2 rates
(3.0 Gb/s) and Gen 3 rates (6 Gb/s).
Device Detection Initialization (DET)—R/W. Controls the PCH’s device detection
and interface initialization.
Value Description
0h No device detection or initialization action requested
3:0 Perform interface communication initialization sequence to
establish communication. This is functionally equivalent to a hard
1h
reset and results in the interface being reset and communications
re-initialized
4h Disable the Serial ATA interface and put Phy in offline mode
All other values reserved.
650 Datasheet
SATA Controller Registers (D31:F5)
14.3.2.3 PxSERR—Serial ATA Error Register (D31:F5)
Address Offset: Attribute: R/WC
Default Value: 00000000h Size: 32 bits
SDATA when SINDx.RIDX is 02h.
Bits 26:16 of this register contains diagnostic error information for use by diagnostic
software in validating correct operation or isolating failure modes. Bits 11:0 contain
error information used by host software in determining the appropriate response to the
error condition. If one or more of bits 11:8 of this register are set, the controller will
stop the current transfer.
Bit Description
31:27 Reserved
Exchanged (X)—R/WC. When set to 1, this bit indicates that a change in device
presence has been detected since the last time this bit was cleared. This bit shall
26
always be set to 1 anytime a COMINIT signal is received. This bit is reflected in the
P0IS.PCS bit.
Unrecognized FIS Type (F)—R/WC. Indicates that one or more FISs were received
25
by the Transport layer with good CRC, but had a type field that was not recognized.
Transport state transition error (T)—R/WC. Indicates that an error has occurred in
24 the transition from one state to another within the Transport layer since the last time
this bit was cleared.
Link Sequence Error (S): Indicates that one or more Link state machine error
23 conditions was encountered. The Link Layer state machine defines the conditions under
which the link layer detects an erroneous transition.
Handshake (H)—R/WC. Indicates that one or more R_ERR handshake response was
received in response to frame transmission. Such errors may be the result of a CRC
22
error detected by the recipient, a disparity or 8b/10b decoding error, or other error
condition leading to a negative handshake on a transmitted frame.
CRC Error (C)—R/WC. Indicates that one or more CRC errors occurred with the Link
21
Layer.
20 Disparity Error (D)—R/WC. This field is not used by AHCI.
10b to 8b Decode Error (B)—R/WC. Indicates that one or more 10b to 8b decoding
19
errors occurred.
Comm Wake (W)—R/WC. Indicates that a Comm Wake signal was detected by the
18
Phy.
17 Phy Internal Error (I)—R/WC. Indicates that the Phy detected some internal error.
PhyRdy Change (N)—R/WC. When set to 1, this bit indicates that the internal PhyRdy
signal changed state since the last time this bit was cleared. In the PCH, this bit will be
16 set when PhyRdy changes from a 0 -> 1 or a 1 -> 0. The state of this bit is then
reflected in the PxIS.PRCS interrupt status bit and an interrupt will be generated if
enabled. Software clears this bit by writing a 1 to it.
15:12 Reserved
Internal Error (E)—R/WC. The SATA controller failed due to a master or target abort
11
when attempting to access system memory.
Protocol Error (P)—R/WC. A violation of the Serial ATA protocol was detected.
10 NOTE: The PCH does not set this bit for all protocol violations that may occur on the
SATA link.
Datasheet 651
SATA Controller Registers (D31:F5)
Bit Description
Persistent Communication or Data Integrity Error (C)—R/WC. A communication
error that was not recovered occurred that is expected to be persistent. Persistent
9
communications errors may arise from faulty interconnect with the device, from a
device that has been removed or has failed, or a number of other causes.
Transient Data Integrity Error (T)—R/WC. A data integrity error occurred that was
8
not recovered by the interface.
7:2 Reserved
Recovered Communications Error (M)—R/WC. Communications between the device
and host was temporarily lost but was re-established. This can arise from a device
1 temporarily being removed, from a temporary loss of Phy synchronization, or from
other causes and may be derived from the PhyNRdy signal between the Phy and Link
layers.
Recovered Data Integrity Error (I)—R/WC. A data integrity error occurred that was
0
recovered by the interface through a retry operation or other recovery action.
§§
652 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15 EHCI Controller Registers
(D29:F0, D26:F0)
15.1 USB EHCI Configuration Registers
(USB EHCI—D29:F0, D26:F0)
Note: Prior to BIOS initialization of the PCH USB subsystem, the EHCI controllers will appear
as Function 7. After BIOS initialization, the EHCI controllers will be Function 0.
Note: Register address locations that are not shown in Table 15-1 should be treated as
Reserved (see Section 9.2 for details).
Table 15-1. USB EHCI PCI Register Address Map (USB EHCI—D29:F0, D26:F0) (Sheet 1 of
2)
Offset Mnemonic Register Name Default Value Attribute
00h–01h VID Vendor Identification 8086h RO
See register
02h–03h DID Device Identification RO
description
04h–05h PCICMD PCI Command 0000h R/W, RO
06h–07h PCISTS PCI Status 0290h R/W, RO
See register
08h RID Revision Identification RO
description
09h PI Programming Interface 20h RO
0Ah SCC Sub Class Code 03h RO
0Bh BCC Base Class Code 0Ch RO
0Dh PMLT Primary Master Latency Timer 00h RO
0Eh HEADTYP Header Type 00h RO
10h–13h MEM_BASE Memory Base Address 00000000h R/W, RO
USB EHCI Subsystem Vendor
2Ch–2Dh SVID XXXXh R/W
Identification
USB EHCI Subsystem
2Eh–2Fh SID XXXXh R/W
Identification
34h CAP_PTR Capabilities Pointer 50h RO
3Ch INT_LN Interrupt Line 00h R/W
See register
3Dh INT_PN Interrupt Pin RO
description
PCI Power Management Capability
50h PWR_CAPID 01h RO
ID
51h NXT_PTR1 Next Item Pointer 58h R/W
52h–53h PWR_CAP Power Management Capabilities C9C2h R/W
Power Management Control / R/W, R/WC,
54h–55h PWR_CNTL_STS 0000h
Status RO
58h DEBUG_CAPID Debug Port Capability ID 0Ah RO
59h NXT_PTR2 Next Item Pointer #2 98h RWS
5Ah–5Bh DEBUG_BASE Debug Port Base Offset 20A0h RO
60h USB_RELNUM USB Release Number 20h RO
Datasheet 653
EHCI Controller Registers (D29:F0, D26:F0)
Table 15-1. USB EHCI PCI Register Address Map (USB EHCI—D29:F0, D26:F0) (Sheet 2 of
2)
Offset Mnemonic Register Name Default Value Attribute
61h FL_ADJ Frame Length Adjustment 20h R/W, RO
62h–63h PWAKE_CAP Port Wake Capabilities 07FFh R/W, RO
64h PDO Port Disable Override Register 0000h R/W, RO
RMH Device Removable Field
66h RMHDEVR 0000h R/W, RO
Register
USB EHCI Legacy Support
68h–6Bh LEG_EXT_CAP 00000001h R/W, RO
Extended Capability
USB EHCI Legacy Extended R/W, R/WC,
6Ch–6Fh LEG_EXT_CS 00000000h
Support Control/Status RO
70h–73h SPECIAL_SMI Intel Specific USB 2.0 SMI 00000000h R/W, R/WC
74h–77h OCMAP Over-Current Mapping C0300C03h R/W
78h–7Dh — Reserved — —
7Eh–7Fh RMHWKCTL RMH Wake Control 0000h R/W, RO
80h ACCESS_CNTL Access Control 00h R/W, RO
84h–87h EHCIIR1 EHCI Initialization Register 1 01h R/W
98h FLR_CID FLR Capability ID 13h RO
99h FLR_NEXT FLR Next Capability Pointer 00h RO
9Ch FLR_CTRL FLR Control 00h R/W, RO
9Dh FLR_STS FLR Status 00h RO
Note: All configuration registers in this section are in the core well and reset by a core well
reset and the D3-to-D0 warm reset, except as noted.
15.1.1 VID—Vendor Identification Register
(USB EHCI—D29:F0, D26:F0)
Offset Address: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bits
Bit Description
15:0 Vendor ID—RO. This is a 16-bit value assigned to Intel.
15.1.2 DID—Device Identification Register
(USB EHCI—D29:F0, D26:F0)
Offset Address: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bits
Bit Description
Device ID—RO. This is a 16-bit value assigned to the PCH USB EHCI controller. See
15:0
Section 1.3 for the value of the DID Register.
654 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.1.3 PCICMD—PCI Command Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 04h–05h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved Read Only
Interrupt Disable—R/W.
0 = The function is capable of generating interrupts.
10 1 = The function can not generate its interrupt to the interrupt controller.
The corresponding Interrupt Status bit (D29:F0, D26:F0:06h, bit 3) is not affected by
the interrupt enable.
9 Fast Back to Back Enable (FBE)—RO. Hardwired to 0.
SERR# Enable (SERR_EN)—R/W.
0 = Disables EHC’s capability to generate an SERR#.
1 = The Enhanced Host controller (EHC) is capable of generating (internally) SERR# in
the following cases:
8 • When it receive a completion status other than “successful” for one of its DMA initiated
memory reads on DMI (and subsequently on its internal interface).
• When it detects an address or command parity error and the Parity Error Response bit is
set.
• When it detects a data parity error (when the data is going into the EHC) and the Parity
Error Response bit is set.
7 Wait Cycle Control (WCC)—RO. Hardwired to 0.
Parity Error Response (PER)—R/W.
0 = The EHC is not checking for correct parity (on its internal interface).
1 = The EHC is checking for correct parity (on its internal interface) and halt operation
when bad parity is detected during the data phase.
6 NOTE: If the EHC detects bad parity on the address or command phases when the bit is
set to 1, the host controller does not take the cycle. It halts the host controller
(if currently not halted) and sets the Host System Error bit in the USBSTS
register. This applies to both requests and completions from the system
interface.
This bit must be set in order for the parity errors to generate SERR#.
5 VGA Palette Snoop (VPS)—RO. Hardwired to 0.
4 Postable Memory Write Enable (PMWE)—RO. Hardwired to 0.
3 Special Cycle Enable (SCE)—RO. Hardwired to 0.
Bus Master Enable (BME)—R/W.
2 0 = Disables this functionality.
1 = Enables the PCH to act as a master on the PCI bus for USB transfers.
Memory Space Enable (MSE)—R/W. This bit controls access to the USB 2.0 Memory
Space registers.
1 0 = Disables this functionality.
1 = Enables accesses to the USB 2.0 registers. The Base Address register (D29:F0,
D26:F0:10h) for USB 2.0 should be programmed before this bit is set.
0 I/O Space Enable (IOSE)—RO. Hardwired to 0.
Datasheet 655
EHCI Controller Registers (D29:F0, D26:F0)
15.1.4 PCISTS—PCI Status Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 06h–07h Attribute: R/WC, RO
Default Value: 0290h Size: 16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit Description
Detected Parity Error (DPE)—R/WC.
0 = No parity error detected.
15 1 = This bit is set by the PCH when a parity error is seen by the EHCI controller,
regardless of the setting of bit 6 or bit 8 in the Command register or any other
conditions.
Signaled System Error (SSE)—R/WC.
0 = No SERR# signaled by the PCH.
14
1 = This bit is set by the PCH when it signals SERR# (internally). The SER_EN bit (bit 8
of the Command Register) must be 1 for this bit to be set.
Received Master Abort (RMA)—R/WC.
0 = No master abort received by EHC on a memory access.
13 1 = This bit is set when EHC, as a master, receives a master abort status on a memory
access. This is treated as a Host Error and halts the DMA engines. This event can
optionally generate an SERR# by setting the SERR# Enable bit.
Received Target Abort (RTA)—R/WC.
0 = No target abort received by EHC on memory access.
1 = This bit is set when EHC, as a master, receives a target abort status on a memory
12
access. This is treated as a Host Error and halts the DMA engines. This event can
optionally generate an SERR# by setting the SERR# Enable bit (D29:F0,
D26:F0:04h, bit 8).
Signaled Target Abort (STA)—RO. This bit is used to indicate when the EHCI function
11 responds to a cycle with a target abort. There is no reason for this to happen, so this bit
is hardwired to 0.
DEVSEL# Timing Status (DEVT_STS)—RO. This 2-bit field defines the timing for
10:9
DEVSEL# assertion. Read Only
Master Data Parity Error Detected (DPED)—R/WC.
0 = No data parity error detected on USB2.0 read completion packet.
8 1 = This bit is set by the PCH when a data parity error is detected on a USB 2.0 read
completion packet on the internal interface to the EHCI host controller and bit 6 of
the Command register is set to 1.
7 Fast Back to Back Capable (FB2BC)—RO. Hardwired to 1.
6 User Definable Features (UDF)—RO. Hardwired to 0.
5 66 MHz Capable (66 MHz _CAP)—RO. Hardwired to 0.
Capabilities List (CAP_LIST)—RO. Hardwired to 1 indicating that offset 34h contains a
4
valid capabilities pointer.
Interrupt Status—RO. This bit reflects the state of this function’s interrupt at the
input of the enable/disable logic.
3 0 = This bit will be 0 when the interrupt is de-asserted.
1 = This bit is a 1 when the interrupt is asserted.
The value reported in this bit is independent of the value in the Interrupt Enable bit.
2:0 Reserved
656 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.1.5 RID—Revision Identification Register
(USB EHCI—D29:F0, D26:F0)
Offset Address: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
Bit Description
Revision ID—RO. This field indicates the device specific revision identifier. See
7:0
Section 1.3 for the value of the RID Register.
15.1.6 PI—Programming Interface Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 09h Attribute: RO
Default Value: 20h Size: 8 bits
Bit Description
Programming Interface—RO. A value of 20h indicates that this USB 2.0 host
7:0
controller conforms to the EHCI Specification.
15.1.7 SCC—Sub Class Code Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 0Ah Attribute: RO
Default Value: 03h Size: 8 bits
Bit Description
Sub Class Code (SCC)—RO.
7:0
03h = Universal serial bus host controller.
15.1.8 BCC—Base Class Code Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 0Bh Attribute: RO
Default Value: 0Ch Size: 8 bits
Bit Description
Base Class Code (BCC)—RO.
7:0
0Ch = Serial bus controller.
Datasheet 657
EHCI Controller Registers (D29:F0, D26:F0)
15.1.9 PMLT—Primary Master Latency Timer Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
Master Latency Timer Count (MLTC)—RO. Hardwired to 00h. Because the EHCI
7:0 controller is internally implemented with arbitration on an interface (and not PCI), it
does not need a master latency timer.
15.1.10 HEADTYP—Header Type Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 0Eh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
Multi-Function Device—RO. When set to ‘1’ indicates this is a multifunction device:
7 0 = Single-function device
1 = Multi-function device.
Configuration Layout. Hardwired to 00h, which indicates the standard PCI configuration
6:0
layout.
15.1.11 MEM_BASE—Memory Base Address Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 10h–13h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
Base Address—R/W. Bits [31:10] correspond to memory address signals [31:10],
31:10
respectively. This gives 1-KB of locatable memory space aligned to 1-KB boundaries.
9:4 Reserved
3 Prefetchable—RO. Hardwired to 0 indicating that this range should not be prefetched.
Type—RO. Hardwired to 00b indicating that this range can be mapped anywhere within
2:1
32-bit address space.
Resource Type Indicator (RTE)—RO. Hardwired to 0 indicating that the base
0
address field in this register maps to memory space.
658 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.1.12 SVID—USB EHCI Subsystem Vendor ID Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 2Ch–2Dh Attribute: R/W
Default Value: XXXXh Size: 16 bits
Reset: None Power Well: Core
Bit Description
Subsystem Vendor ID (SVID)—R/W. This register, in combination with the USB 2.0
Subsystem ID register, enables the operating system to distinguish each subsystem
from the others.
15:0
NOTE: Writes to this register are enabled when the WRT_RDONLY bit (D29:F0,
D26:F0:80h, bit 0) is set to 1.
15.1.13 SID—USB EHCI Subsystem ID Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 2Eh–2Fh Attribute: R/W
Default Value: XXXXh Size: 16 bits
Reset: None Power Well: Core
Bit Description
Subsystem ID (SID)—R/W. BIOS sets the value in this register to identify the
Subsystem ID. This register, in combination with the Subsystem Vendor ID register,
enables the operating system to distinguish each subsystem from other(s).
15:0
NOTE: Writes to this register are enabled when the WRT_RDONLY bit (D29:F0,
D26:F0:80h, bit 0) is set to 1.
15.1.14 CAP_PTR—Capabilities Pointer Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 34h Attribute: RO
Default Value: 50h Size: 8 bits
Power Well: Core
Bit Description
Capabilities Pointer (CAP_PTR)—RO. This register points to the starting offset of the
7:0
USB 2.0 capabilities ranges.
Datasheet 659
EHCI Controller Registers (D29:F0, D26:F0)
15.1.15 INT_LN—Interrupt Line Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 3Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Reset: No Power Well: Core
Bit Description
Interrupt Line (INT_LN)—R/W. This data is not used by the PCH. It is used as a
7:0 scratchpad register to communicate to software the interrupt line that the interrupt pin
is connected to.
15.1.16 INT_PN—Interrupt Pin Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 3Dh Attribute: RO
Default Value: See Description Size: 8 bits
Bit Description
Interrupt Pin—RO. This reflects the value of D29IP.E1IP (Chipset Config
Registers:Offset 3108:bits 3:0) or D26IP.E2IP (Chipset Config Registers:Offset
3114:bits 3:0).
7:0 NOTE: As a single function device, only INTA# may be used while the other three
interrupt lines have no meaning. (refer to PCI 3.0 specification, Section 2.2.6,
Interrupt Pins).
NOTE: Bits 7:4 are always 0h
15.1.17 PWR_CAPID—PCI Power Management Capability
Identification Register (USB EHCI—D29:F0, D26:F0)
Address Offset: 50h Attribute: RO
Default Value: 01h Size: 8 bits
Bit Description
Power Management Capability ID—RO. A value of 01h indicates that this is a PCI
7:0
Power Management capabilities field.
660 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.1.18 NXT_PTR1—Next Item Pointer #1 Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 51h Attribute: R/W
Default Value: 58h Size: 8 bits
Power Well: Core
Bit Description
Next Item Pointer 1 Value—R/W (special). This register defaults to 58h that
indicates that the next capability registers begin at configuration offset 58h. This
register is writable when the WRT_RDONLY bit (D29:F0, D26:F0:80h, bit 0) is set. This
allows BIOS to effectively hide the Debug Port capability registers, if necessary. This
7:0 register should only be written during system initialization before the plug-and-play
software has enabled any master-initiated traffic. Only values of 58h (Debug Port and
FLR capabilities visible) and 98h (Debug Port invisible, next capability is FLR) are
expected to be programmed in this register.
NOTE: Register not reset by D3-to-D0 warm reset.
15.1.19 PWR_CAP—Power Management Capabilities Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 52h–53h Attribute: R/W, RO
Default Value: C9C2h Size: 16 bits
Power Well: Core
Bit Description
PME Support (PME_SUP)—R/W. This 5-bit field indicates the power states in which
the function may assert PME#. The PCH EHC does not support the D1 or D2 states. For
15:11
all other states, the PCH EHC is capable of generating PME#. Software should never
need to modify this field.
D2 Support (D2_SUP)—RO.
10
0 = D2 State is not supported
D1 Support (D1_SUP)—RO.
9
0 = D1 State is not supported
Auxiliary Current (AUX_CUR)—R/W. The PCH EHC reports 375 mA maximum
8:6
suspend well current required when in the D3COLD state.
Device Specific Initialization (DSI)—RO. The PCH reports 0, indicating that no
5
device-specific initialization is required.
4 Reserved
PME Clock (PME_CLK)—RO. The PCH reports 0, indicating that no PCI clock is
3
required to generate PME#.
Version (VER)—RO. The PCH reports 010b, indicating that it complies with Revision
2:0
1.1 of the PCI Power Management Specification.
NOTES:
1. Normally, this register is read-only to report capabilities to the power management software.
To report different power management capabilities, depending on the system in which the
PCH is used, bits 15:11 and 8:6 in this register are writable when the WRT_RDONLY bit
(D29:F0, D26:F0:80h, bit 0) is set. The value written to this register does not affect the
hardware other than changing the value returned during a read.
2. Reset: core well, but not D3-to-D0 warm reset.
Datasheet 661
EHCI Controller Registers (D29:F0, D26:F0)
15.1.20 PWR_CNTL_STS—Power Management Control /
Status Register (USB EHCI—D29:F0, D26:F0)
Address Offset: 54h–55h Attribute: R/W, R/WC, RO
Default Value: 0000h Size: 16 bits
Power Well Bits 1,0: Core; Power Well Bits 15,8: Suspend
Bit Description
PME Status—R/WC.
0 = Writing a 1 to this bit will clear it and cause the internal PME to de-assert (if
enabled).
1 = This bit is set when the PCH EHC would normally assert the PME# signal
15 independent of the state of the PME_En bit.
NOTE: This bit must be explicitly cleared by the operating system each time the
operating system is loaded.
This bit is not reset by Function Level Reset.
Data Scale—RO. Hardwired to 00b indicating it does not support the associated Data
14:13
register.
Data Select—RO. Hardwired to 0000b indicating it does not support the associated Data
12:9
register.
PME Enable—R/W.
0 = Disable.
1 = Enables the PCH EHC to generate an internal PME signal when PME_Status is 1.
8
NOTE: This bit must be explicitly cleared by the operating system each time it is
initially loaded.
This bit is not reset by Function Level Reset.
7:2 Reserved
Power State—R/W. This 2-bit field is used both to determine the current power state
of EHC function and to set a new power state. The definition of the field values are:
00 = D0 state
11 = D3HOT state
If software attempts to write a value of 10b or 01b in to this field, the write operation
1:0 must complete normally; however, the data is discarded and no state change occurs.
When in the D3HOT state, the PCH must not accept accesses to the EHC memory range;
but the configuration space must still be accessible. When not in the D0 state, the
generation of the interrupt output is blocked. Specifically, the PIRQH is not asserted by
the PCH when not in the D0 state.
When software changes this value from the D3HOT state to the D0 state, an internal
warm (soft) reset is generated, and software must re-initialize the function.
NOTE: Reset (bits 15, 8): suspend well, and not D3-to-D0 warm reset nor core well reset.
662 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.1.21 DEBUG_CAPID—Debug Port Capability ID Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 58h Attribute: RO
Default Value: 0Ah Size: 8 bits
Bit Description
Debug Port Capability ID—RO. Hardwired to 0Ah indicating that this is the start of a
7:0
Debug Port Capability structure.
15.1.22 NXT_PTR2—Next Item Pointer #2 Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 59h Attribute: RO
Default Value: 98h Size: 8 bits
Function Level Reset: No
Bit Description
Next Item Pointer 2 Capability—RO. This register points to the next capability in the
7:0
Function Level Reset capability structure.
15.1.23 DEBUG_BASE—Debug Port Base Offset Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 5Ah–5Bh Attribute: RO
Default Value: 20A0h Size: 16 bits
Bit Description
BAR Number—RO. Hardwired to 001b to indicate the memory BAR begins at offset
15:13
10h in the EHCI configuration space.
Debug Port Offset—RO. Hardwired to 0A0h to indicate that the Debug Port registers
12:0
begin at offset A0h in the EHCI memory range.
15.1.24 USB_RELNUM—USB Release Number Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 60h Attribute: RO
Default Value: 20h Size: 8 bits
Bit Description
USB Release Number—RO. A value of 20h indicates that this controller follows
7:0
Universal Serial Bus (USB) Specification, Revision 2.0.
Datasheet 663
EHCI Controller Registers (D29:F0, D26:F0)
15.1.25 FL_ADJ—Frame Length Adjustment Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 61h Attribute: R/W
Default Value: 20h Size: 8 bits
Function Level Reset: No Power Well: Suspend
This feature is used to adjust any offset from the clock source that generates the clock
that drives the SOF counter. When a new value is written into these six bits, the length
of the frame is adjusted. Its initial programmed value is system dependent based on
the accuracy of hardware USB clock and is initialized by system BIOS. This register
should only be modified when the HChalted bit (D29:F0, D26:F0:CAPLENGTH + 24h,
bit 12) in the USB2.0_STS register is a 1. Changing value of this register while the host
controller is operating yields undefined results. It should not be reprogrammed by USB
system software unless the default or BIOS programmed values are incorrect, or the
system is restoring the register while returning from a suspended state.
These bits in suspend well and not reset by a D3-to-D0 warm rest or a core well reset.
Bit Description
7:6 Reserved—RO. These bits are reserved for future use and should read as 00b.
Frame Length Timing Value—R/W. Each decimal value change to this register
corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter
clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this
field. The default value is decimal 32 (20h) that gives a SOF cycle time of 60000.
Frame Length (# 480 MHz Frame Length Timing Value (this
Clocks) (decimal) register) (decimal)
59488 0
5:0 59504 1
59520 2
— —
59984 31
60000 32
— —
60480 62
664 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.1.26 PWAKE_CAP—Port Wake Capability Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 62–63h Attribute: R/W, RO
Default Value: 07FFh Size: 16 bits
Function Level Reset: No Power Well: Suspend
This register is in the suspend power well. The intended use of this register is to
establish a policy about which ports are to be used for wake events. Bit positions 1–
8(D29) or 1–6(D26) in the mask correspond to a physical port implemented on the
current EHCI controller. A 1 in a bit position indicates that a device connected below the
port can be enabled as a wake-up device and the port may be enabled for disconnect/
connect or overcurrent events as wake-up events. This is an information-only mask
register. The bits in this register do not affect the actual operation of the EHCI host
controller. The system-specific policy can be established by BIOS initializing this
register to a system-specific value. System software uses the information in this
register when enabling devices and ports for remote wake-up.
These bits are not reset by a D3-to-D0 warm rest or a core well reset.
s
Bit Description
15:11 Reserved, Read Only
Port Wake Up Capability Mask—R/W. Bit positions 1-10 correspond to a
10:1 (D29) physical port implemented on this host controller. For example, bit position 1
corresponds to port 1, bit position 2 corresponds to port 2, and so on.
Port Wake Implemented—R/W. A 1 in this bit indicates that this register is
0
implemented to software.
15.1.27 PDO—Port Disable Override Register
Address Offset: 64h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Power Well: Suspend
Bit Description
15:8 Reserved, Read Only
USB Port Disable: A ‘1’ in a bit position prevents the corresponding USB port from
reporting a Device Connection to the hub. Attempts to enable the port will be
ignored by the hardware when this bit is 1.
7:0
For EHCI 2, bit 7 and 6 are reserved. Writing to these bits has no significance.
This register cannot be written when the USB Per-Port Registers Write Enable bit
(in Power Management I/O Space) is 0.
Datasheet 665
EHCI Controller Registers (D29:F0, D26:F0)
15.1.28 RMHDEVR—RMH Device Removable Field Register
Address Offset: 66h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Power Well: Suspend
Bit Description
15:9 Reserved, Read Only
Device Removable Bit Map: A ‘1’ in a given bit position in this field indicates that
the corresponding downstream port of the RMH is connected to a non-removable
device. A ‘0’ indicates that the port is exposed to the user.
Bits 8:1 are mapped to Ports 8:1 (on EHCI #1, Device. 29)
Bits 6:1 are mapped to Ports 6:1 (on EHCI #2, Device. 26)
This bits control the value returned by the RMH in the Deviceremovable field of the
8:1 Hub Descriptor. A ‘1’ in a given bit position in this register will result in the
corresponding bit in the DeviceRemovable field of the hub descriptor being set to
‘1’ as well (indicating that the port is connected to a non-removable device).
System BIOS is expected to set these values upon Boot and resume from Sx
states.
NOTE: Bits 8:7 are reserved (maintained as RW but with no significance) for
EHCI2 (Device 26) since RMH#2 corresponding to EHCI2 has only 6 ports.
0 Reserved, Read Only
15.1.29 LEG_EXT_CAP—USB EHCI Legacy Support Extended
Capability Register (USB EHCI—D29:F0, D26:F0)
Address Offset: 68–6Bh Attribute: R/W, RO
Default Value: 00000001h Size: 32 bits
Power Well: Suspend
Function Level Reset: No
Note: These bits are not reset by a D3-to-D0 warm rest or a core well reset.
Bit Description
31:25 Reserved—RO. Hardwired to 00h
HC OS Owned Semaphore—R/W. System software sets this bit to request ownership
24 of the EHCI controller. Ownership is obtained when this bit reads as 1 and the HC BIOS
Owned Semaphore bit reads as clear.
23:17 Reserved—RO. Hardwired to 00h
HC BIOS Owned Semaphore—R/W. The BIOS sets this bit to establish ownership of
16 the EHCI controller. System BIOS will clear this bit in response to a request for
ownership of the EHCI controller by system software.
Next EHCI Capability Pointer—RO. Hardwired to 00h to indicate that there are no
15:8
EHCI Extended Capability structures in this device.
Capability ID—RO. Hardwired to 01h to indicate that this EHCI Extended Capability is
7:0
the Legacy Support Capability.
666 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.1.30 LEG_EXT_CS—USB EHCI Legacy Support Extended
Control / Status Register (USB EHCI—D29:F0, D26:F0)
Address Offset: 6C–6Fh Attribute: R/W, R/WC, RO
Default Value: 00000000h Size: 32 bits
Power Well: Suspend
Function Level Reset: No
Note: These bits are not reset by a D3-to-D0 warm rest or a core well reset.
Bit Description
SMI on BAR—R/WC. Software clears this bit by writing a 1 to it.
31 0 = Base Address Register (BAR) not written.
1 = This bit is set to 1 when the Base Address Register (BAR) is written.
SMI on PCI Command—R/WC. Software clears this bit by writing a 1 to it.
30 0 = PCI Command (PCICMD) Register Not written.
1 = This bit is set to 1 when the PCI Command (PCICMD) Register is written.
SMI on OS Ownership Change—R/WC. Software clears this bit by writing a 1 to it.
0 = No HC OS Owned Semaphore bit change.
29
1 = This bit is set to 1 when the HC OS Owned Semaphore bit in the LEG_EXT_CAP
register (D29:F0, D26:F0:68h, bit 24) transitions from 1 to 0 or 0 to 1.
28:22 Reserved
SMI on Async Advance—RO. This bit is a shadow bit of the Interrupt on Async
Advance bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register.
21
NOTE: To clear this bit system software must write a 1 to the Interrupt on Async
Advance bit in the USB2.0_STS register.
SMI on Host System Error—RO. This bit is a shadow bit of Host System Error bit in
the USB2.0_STS register (D29:F0, D26:F0:CAPLENGTH + 24h, bit 4).
20
NOTE: To clear this bit system software must write a 1 to the Host System Error bit in
the USB2.0_STS register.
SMI on Frame List Rollover—RO. This bit is a shadow bit of Frame List Rollover bit
(D29:F0, D26:F0:CAPLENGTH + 24h, bit 3) in the USB2.0_STS register.
19
NOTE: To clear this bit system software must write a 1 to the Frame List Rollover bit in
the USB2.0_STS register.
SMI on Port Change Detect—RO. This bit is a shadow bit of Port Change Detect bit
(D29:F0, D26:F0:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register.
18
NOTE: To clear this bit system software must write a 1 to the Port Change Detect bit in
the USB2.0_STS register.
SMI on USB Error—RO. This bit is a shadow bit of USB Error Interrupt (USBERRINT)
bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 1) in the USB2.0_STS register.
17
NOTE: To clear this bit system software must write a 1 to the USB Error Interrupt bit in
the USB2.0_STS register.
SMI on USB Complete—RO. This bit is a shadow bit of USB Interrupt (USBINT) bit
(D29:F0, D26:F0:CAPLENGTH + 24h, bit 0) in the USB2.0_STS register.
16
NOTE: To clear this bit system software must write a 1 to the USB Interrupt bit in the
USB2.0_STS register.
Datasheet 667
EHCI Controller Registers (D29:F0, D26:F0)
Bit Description
SMI on BAR Enable—R/W.
0 = Disable.
15
1 = Enable. When this bit is 1 and SMI on BAR (D29:F0, D26:F0:6Ch, bit 31) is 1, then
the host controller will issue an SMI.
SMI on PCI Command Enable—R/W.
14 0 = Disable.
1 = Enable. When this bit is 1 and SMI on PCI Command (D29:F0, D26:F0:6Ch, bit 30)
is 1, then the host controller will issue an SMI.
SMI on OS Ownership Enable—R/W.
0 = Disable.
13
1 = Enable. When this bit is a 1 AND the OS Ownership Change bit (D29:F0,
D26:F0:6Ch, bit 29) is 1, the host controller will issue an SMI.
12:6 Reserved
SMI on Async Advance Enable—R/W.
0 = Disable.
5
1 = Enable. When this bit is a 1, and the SMI on Async Advance bit (D29:F0,
D26:F0:6Ch, bit 21) is a 1, the host controller will issue an SMI immediately.
SMI on Host System Error Enable—R/W.
0 = Disable.
4
1 = Enable. When this bit is a 1, and the SMI on Host System Error (D29:F0,
D26:F0:6Ch, bit 20) is a 1, the host controller will issue an SMI.
SMI on Frame List Rollover Enable—R/W.
0 = Disable.
3
1 = Enable. When this bit is a 1, and the SMI on Frame List Rollover bit (D29:F0,
D26:F0:6Ch, bit 19) is a 1, the host controller will issue an SMI.
SMI on Port Change Enable—R/W.
2 0 = Disable.
1 = Enable. When this bit is a 1, and the SMI on Port Change Detect bit (D29:F0,
D26:F0:6Ch, bit 18) is a 1, the host controller will issue an SMI.
SMI on USB Error Enable—R/W.
0 = Disable.
1
1 = Enable. When this bit is a 1, and the SMI on USB Error bit (D29:F0, D26:F0:6Ch,
bit 17) is a 1, the host controller will issue an SMI immediately.
SMI on USB Complete Enable—R/W.
0 = Disable.
0
1 = Enable. When this bit is a 1, and the SMI on USB Complete bit (D29:F0,
D26:F0:6Ch, bit 16) is a 1, the host controller will issue an SMI immediately.
668 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.1.31 SPECIAL_SMI—Intel® Specific USB 2.0 SMI Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 70h–73h Attribute: R/W, R/WC
Default Value: 00000000h Size: 32 bits
Power Well: Suspend
Function Level Reset: No
Note: These bits are not reset by a D3-to-D0 warm rest or a core well reset.
Bit Description
31:25 Reserved
SMI on PortOwner—R/WC. Software clears these bits by writing a 1 to it.
0 = No Port Owner bit change.
24:22 1 = Bits 24:22 correspond to the Port Owner bits for ports 0 (22) through 3 (24).
These bits are set to 1 when the associated Port Owner bits transition from 0
to 1 or 1 to 0.
SMI on PMCSR—R/WC. Software clears these bits by writing a 1 to it.
21 0 = Power State bits Not modified.
1 = Software modified the Power State bits in the Power Management Control/
Status (PMCSR) register (D29:F0, D26:F0:54h).
SMI on Async—R/WC. Software clears these bits by writing a 1 to it.
20 0 = No Async Schedule Enable bit change
1 = Async Schedule Enable bit transitioned from 1 to 0 or 0 to 1.
SMI on Periodic—R/WC. Software clears this bit by writing a 1 it.
19 0 = No Periodic Schedule Enable bit change.
1 = Periodic Schedule Enable bit transitions from 1 to 0 or 0 to 1.
SMI on CF—R/WC. Software clears this bit by writing a 1 it.
18 0 = No Configure Flag (CF) change.
1 = Configure Flag (CF) transitions from 1 to 0 or 0 to 1.
SMI on HCHalted—R/WC. Software clears this bit by writing a 1 it.
17 0 = HCHalted did Not transition to 1 (as a result of the Run/Stop bit being
cleared).
1 = HCHalted transitions to 1 (as a result of the Run/Stop bit being cleared).
SMI on HCReset—R/WC. Software clears this bit by writing a 1 it.
16 0 = HCRESET did Not transitioned to 1.
1 = HCRESET transitioned to 1.
SMI on PortOwner Enable—R/W.
0 = Disable.
15:6 1 = Enable. When any of these bits are 1 and the corresponding SMI on
PortOwner bits are 1, then the host controller will issue an SMI. Unused
ports should have their corresponding bits cleared.
SMI on PMSCR Enable—R/W.
5 0 = Disable.
1 = Enable. When this bit is 1 and SMI on PMSCR is 1, then the host controller
will issue an SMI.
SMI on Async Enable—R/W.
0 = Disable.
4
1 = Enable. When this bit is 1 and SMI on Async is 1, then the host controller will
issue an SMI
Datasheet 669
EHCI Controller Registers (D29:F0, D26:F0)
Bit Description
SMI on Periodic Enable—R/W.
0 = Disable.
3
1 = Enable. When this bit is 1 and SMI on Periodic is 1, then the host controller
will issue an SMI.
SMI on CF Enable—R/W.
2 0 = Disable.
1 = Enable. When this bit is 1 and SMI on CF is 1, then the host controller will
issue an SMI.
SMI on HCHalted Enable—R/W.
0 = Disable.
1
1 = Enable. When this bit is a 1 and SMI on HCHalted is 1, then the host
controller will issue an SMI.
SMI on HCReset Enable—R/W.
0 = Disable.
0
1 = Enable. When this bit is a 1 and SMI on HCReset is 1, then host controller
will issue an SMI.
15.1.32 OCMAP—Over-Current Mapping Register
Address Offset: 74-77h Attribute: R/W
Default Value: C0300C03h Size: 32 bits
Function Level Reset: No Power well: Suspend
Bit Description
OC3/OC7 Mapping Each bit position maps OC3 (EHCI 1) and OC7 (EHCI2) to a
set of ports as follows:
EHCI 1: Map OC3
Bit: 31 30 29 28 27 26 25 24
Port: 7 6 5 4 3 2 1 0
31:24
EHCI 2: Map OC7
Bit: 31 30 29 28 27 26 25 24
Port: Rsvd Rsvd 13 12 11 10 9 8
It is software responsibility to ensure that a given port‘s bit map is set only for
one OC pin.
670 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
Bit Description
OC2/OC6 Mapping Each bit position maps OC2 (EHCI 1) and OC6 (EHCI2) to a
set of ports as follows:
EHCI 1: Map OC2
Bit: 23 22 21 20 19 18 17 16
Port: 7 6 5 4 3 2 1 0
23:16
EHCI 2: Map OC6
Bit: 23 22 21 20 19 18 17 16
Port: Rsvd Rsvd 13 12 11 10 9 8
It is software responsibility to ensure that a given port‘s bit map is set only for
one OC pin.
OC1/OC5 Mapping Each bit position maps OC1 (EHCI 1) and OC5 (EHCI2) to a
set of ports as follows:
EHCI 1: Map OC1
Bit: 15 14 13 12 11 10 9 8
Port: 7 6 5 4 3 2 1 0
15:08
EHCI 2: Map OC5
Bit: 15 14 13 12 11 10 9 8
Port: Rsvd Rsvd 13 12 11 10 9 8
It is software responsibility to ensure that a given port‘s bit map is set only for
one OC pin.
OC0/OC4 Mapping Each bit position maps OC0 (EHCI 1) and OC4 (EHCI2) to a
set of ports as follows:
EHCI 1: Map OC0
Bit: 7 6 5 4 3 2 1 0
Port: 7 6 5 4 3 2 1 0
07:00
EHCI 2: Map OC4
Bit: 7 6 5 4 3 2 1 0
Port: Rsvd Rsvd 13 12 11 10 9 8
It is software responsibility to ensure that a given port‘s bit map is set only for
one OC pin.
Datasheet 671
EHCI Controller Registers (D29:F0, D26:F0)
15.1.33 RMHWKCTL—RMH Wake Control Register
Address Offset: 7Eh Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Function Level Reset: No Power well: Suspend
Bit Description
15:09 Reserved
RMH Inherit EHCI Wake Control Settings -R/W.
0 = bits 2:0 of this register DO NOT reflect the appropriate bits of EHCI PORTSC0
08 bits 22:20.
1 = Bits 2:0 of this register reflect the appropriate bits of EHCI PORTSC0 bits
22:20.
07:04 Reserved
RMH Upstream Wake on Device Resume Disable- R/W
0 = The RMH will initiate a resume on its upstream port and cause a wake when a
03 device resume occurs on an enabled downstream port
1 = The RMH will NOT initiate a resume on its upstream port and cause a wake
when a device resume occurs on an enabled downstream port
RMH Upstream Wake on OC Disable - R/W
0 = The RMH will initiate a resume on its upstream port and cause a wake when
02 over-current condition occurs downstream port
1 = The RMH will NOT initiate a resume on its upstream port and cause a wake
when over-current condition occurs downstream port
RMH Upstream Wake on Disconnect Disable - R/W
0 = The RMH will initiate a resume on its upstream port and cause a wake when a
01 disconnect event occurs on a downstream port
1 = The RMH will NOT initiate a resume on its upstream port and cause a wake
when a disconnect event occurs on a downstream port
RMH Upstream Wake on Connect Disable- R/W
0 = The RMH will initiate a resume on its upstream port and cause a wake when a
00 connect event occurs on a downstream port
1 = The RMH will NOT initiate a resume on its upstream port and cause a wake
when a connect event occurs on a downstream port
15.1.34 ACCESS_CNTL—Access Control Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 80h Attribute: R/W
Default Value: 00h Size: 8 bits
Function Level Reset: No
Bit Description
7:1 Reserved
WRT_RDONLY—R/W. When set to 1, this bit enables a select group of normally
read-only registers in the EHC function to be written by software. Registers that
may only be written when this mode is entered are noted in the summary tables
0 and detailed description as “Read/Write-Special”. The registers fall into two
categories:
1. System-configured parameters
2. Status bits
672 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.1.35 EHCIIR1—EHCI Initialization Register 1
(USB EHCI—D29:F0, D26:F0)
Address Offset: 84h Attribute: R/W
Default Value: 01h Size: 32 bits
Power well: Core
Bit Description
31:29 Reserved
EHCI Prefetch Entry Clear—R/W.
28 0 = EHC will clear prefetched entries in DMA.
1 = EHC will not clear prefetched entries in DMA
27:5 Reserved
Intel® Pre-fetch Based Pause Enable—R/W.
4 0 = Intel Pre-fetch Based Pause is disabled.
1 = Intel Pre-fetch Based Pause is enabled.
3:0 Reserved
15.1.36 FLR_CID—Function Level Reset Capability ID Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 98h Attribute: RO
Default Value: 13h Size: 8 bits
Function Level Reset: No
Bit Description
Capability ID—RO.
7:0
13h = Capability ID
15.1.37 FLR_NEXT—Function Level Reset Next Capability
Pointer Register (USB EHCI—D29:F0, D26:F0)
Address Offset: 99h Attribute: RO
Default Value: 00h Size: 8 bits
Function Level Reset: No
Bit Description
7:0 A value of 00h in this register indicates this is the last capability field.
Datasheet 673
EHCI Controller Registers (D29:F0, D26:F0)
15.1.38 FLR_CLV—Function Level Reset Capability Length and
Version Register (USB EHCI—D29:F0, D26:F0)
Address Offset: 9Ah–9Bh Attribute: R/WO, RO
Default Value: 0306h Size: 16 bits
Function Level Reset: No
When FLRCSSEL = 0, this register is defined as follows:
Bit Description
15:10 Reserved
FLR Capability—R/WO.
9
1 = Support for Function Level Reset (FLR).
TXP Capability—R/WO.
8 1 = Support for Transactions Pending (TXP) bit. TXP must be supported if FLR is
supported.
Capability Length—RO. This field indicates the # of bytes of this vendor specific
7:0 capability as required by the PCI specification. It has the value of 06h for the FLR
capability.
15.1.39 FLR_CTRL—Function Level Reset Control Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 9Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Function Level Reset: No
Bit Description
7:1 Reserved
Initiate FLR—R/W. This bit is used to initiate FLR transition. A write of 1 initiates FLR
0 transition. Since hardware must not respond to any cycles until FLR completion, the
value read by software from this bit is always 0.
15.1.40 FLR_STS—Function Level Reset Status Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 9Dh Attribute: RO
Default Value: 00h Size: 8 bits
Function Level Reset: No
Bit Description
7:1 Reserved
Transactions Pending (TXP)—RO.
0 0 = Completions for all non-posted requests have been received.
1 = Controller has issued non-posted requests which have not been completed.
674 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.2 Memory-Mapped I/O Registers
The EHCI memory-mapped I/O space is composed of two sets of registers—Capability
Registers and Operational Registers.
Note: The PCH EHCI controller will not accept memory transactions (neither reads nor writes)
as a target that are locked transactions. The locked transactions should not be
forwarded to PCI as the address space is known to be allocated to USB.
Note: When the EHCI function is in the D3 PCI power state, accesses to the USB 2.0 memory
range are ignored and result a master abort. Similarly, if the Memory Space Enable
(MSE) bit (D29:F0, D26:F0:04h, bit 1) is not set in the Command register in
configuration space, the memory range will not be decoded by the PCH enhanced host
controller (EHC). If the MSE bit is not set, the PCH must default to allowing any
memory accesses for the range specified in the BAR to go to PCI. This is because the
range may not be valid and, therefore, the cycle must be made available to any other
targets that may be currently using that range.
15.2.1 Host Controller Capability Registers
These registers specify the limits, restrictions and capabilities of the host controller
implementation. Within the host controller capability registers, only the structural
parameters register is writable. These registers are implemented in the suspend well
and is only reset by the standard suspend-well hardware reset, not by HCRESET or the
D3-to-D0 reset.
Note: The EHCI controller does not support as a target memory transactions that are locked
transactions. Attempting to access the EHCI controller Memory-Mapped I/O space
using locked memory transactions will result in undefined behavior.
Note: When the USB2 function is in the D3 PCI power state, accesses to the USB2 memory
range are ignored and will result in a master abort. Similarly, if the Memory Space
Enable (MSE) bit is not set in the Command register in configuration space, the
memory range will not be decoded by the Enhanced Host Controller (EHC). If the MSE
bit is not set, the EHC will not claim any memory accesses for the range specified in the
BAR.
Table 15-2. Enhanced Host Controller Capability Registers
MEM_BASE
Mnemonic Register Default Attribute
+ Offset
00h CAPLENGTH Capabilities Registers Length 20h RO
Host Controller Interface Version
02h–03h HCIVERSION 0100h RO
Number
00204208h
Host Controller Structural (D29:F0) R/W
04h–07h HCSPARAMS
Parameters 00203206 (special), RO
(D26:F0)
Host Controller Capability
08h–0Bh HCCPARAMS 0003688h R/W, RO
Parameters
NOTE: “Read/Write Special” means that the register is normally read-only, but may be written
when the WRT_RDONLY bit is set. Because these registers are expected to be programmed
by BIOS during initialization, their contents must not get modified by HCRESET or D3-to-
D0 internal reset.
Datasheet 675
EHCI Controller Registers (D29:F0, D26:F0)
15.2.1.1 CAPLENGTH—Capability Registers Length Register
Offset: MEM_BASE + 00h Attribute: RO
Default Value: 20h Size: 8 bits
Bit Description
Capability Register Length Value—RO. This register is used as an offset to add to
the Memory Base Register (D29:F0, D26:F0:10h) to find the beginning of the
7:0
Operational Register Space. This field is hardwired to 20h indicating that the Operation
Registers begin at offset 20h.
15.2.1.2 HCIVERSION—Host Controller Interface Version Number
Register
Offset: MEM_BASE + 02h–03h Attribute: RO
Default Value: 0100h Size: 16 bits
Bit Description
Host Controller Interface Version Number—RO. This is a two-byte register
15:0 containing a BCD encoding of the version number of interface that this host controller
interface conforms.
15.2.1.3 HCSPARAMS—Host Controller Structural Parameters
Offset: MEM_BASE + 04h–07h Attribute: R/W, RO
Default Value: 00200008h (D29:F0) Size: 32 bits
00200006h (D26:F0)
Function Level Reset: No
Note: This register is reset by a suspend well reset and not a D3-to-D0 reset or HCRESET.
Bit Description
31:24 Reserved
Debug Port Number (DP_N)—RO. Hardwired to 2h indicating that the Debug Port is
on the second lowest numbered port on the EHCI.
23:20
EHCI#1: Port 1
EHCI#2: Port 9
19:16 Reserved
Number of Companion Controllers (N_CC)—RO. This field indicates the number of
15:12 companion controllers associated with this USB EHCI host controller.There are no
companion controllers so this field is set to zero as a read only bit.
Number of Ports per Companion Controller (N_PCC)—RO. This field indicates the
11:8 number of ports supported per companion host controller. This field is 0h indication no
other companion controller support.
7:4 Reserved. These bits are reserved and default to 0.
N_PORTS—R/W. This field specifies the number of physical downstream ports
implemented on this host controller. The value of this field determines how many port
registers are addressable in the Operational Register Space. Valid values are in the
range of 1h to Fh. A 0 in this field is undefined.
3:0
For Integrated USB 2.0 Rate Matching Hub Enabled: Each EHCI reports 2 ports by
default. Port 0 assigned to the RMH and port 1 assigned as the debug port. When the
KVM/USB-R feature is enabled it will show up as Port2 on the EHCI, and BIOS would
need to update this field to 3h.
NOTE: This register is writable when the WRT_RDONLY bit is set.
676 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.2.1.4 HCCPARAMS—Host Controller Capability Parameters
Register
Offset: MEM_BASE + 08h–0Bh Attribute: R/W, RO
Default Value: 00036881h Size: 32 bits
Bit Description
31:18 Reserved
Asynchronous Schedule Update Capability (ASUC)—R/W. This bit indicates that
17 the hardware supports the Asynch schedule prefetch enable bit in the USB command
register.
Periodic Schedule Update Capability (PSUC)—R/W. This field indicates that the
16
EHC hardware supports the Periodic Schedule prefetch bit in the USB2.0_CMD register.
EHCI Extended Capabilities Pointer (EECP)—RO. This field is hardwired to 68h,
15:8 indicating that the EHCI capabilities list exists and begins at offset 68h in the PCI
configuration space.
Isochronous Scheduling Threshold—R/W. This field indicates, relative to the current
position of the executing host controller, where software can reliably update the
isochronous schedule. When bit 7 is 0, the value of the least significant 3 bits indicates
the number of micro-frames a host controller hold a set of isochronous data structures
7:4 (one or more) before flushing the state. When bit 7 is a 1, then host software assumes
the host controller may cache an isochronous data structure for an entire frame. Refer
to the EHCI specification for details on how software uses this information for
scheduling isochronous transfers.
This field is hardwired to 8h.
3 Reserved
Asynchronous Schedule Park Capability—RO. This bit is hardwired to 0 indicating
2
that the host controller does not support this optional feature
Programmable Frame List Flag—RO.
0 = System software must use a frame list length of 1024 elements with this host
controller. The USB2.0_CMD register (D29:F0, D26:F0:CAPLENGTH + 20h, bits
3:2) Frame List Size field is a read-only register and must be set to 0.
1
1 = System software can specify and use a smaller frame list and configure the host
controller using the USB2.0_CMD register Frame List Size field. The frame list must
always be aligned on a 4K page boundary. This requirement ensures that the frame
list is always physically contiguous.
64-bit Addressing Capability—RO. This field documents the addressing range
capability of this implementation. The value of this field determines whether software
should use the 32-bit or 64-bit data structures.
0
This bit is hardwired to 1.
NOTE: The PCH supports 64 bit addressing only.
Datasheet 677
EHCI Controller Registers (D29:F0, D26:F0)
15.2.2 Host Controller Operational Registers
This section defines the enhanced host controller operational registers. These registers
are located after the capabilities registers. The operational register base must be
DWord-aligned and is calculated by adding the value in the first capabilities register
(CAPLENGTH) to the base address of the enhanced host controller register address
space (MEM_BASE). Since CAPLENGTH is always 20h, Table 15-3 already accounts for
this offset. All registers are 32 bits in length.
Table 15-3. Enhanced Host Controller Operational Register Address Map
MEM_BASE Special
Mnemonic Register Name Default Attribute
+ Offset Notes
20h–23h USB2.0_CMD USB 2.0 Command 00080000h R/W, RO
24h–27h USB2.0_STS USB 2.0 Status 00001000h R/WC, RO
28h–2Bh USB2.0_INTR USB 2.0 Interrupt Enable 00000000h R/W, RO
2Ch–2Fh FRINDEX USB 2.0 Frame Index 00000000h R/W, RO
30h–33h CTRLDSSEGMENT Control Data Structure Segment 00000000h R/W, RO
34h–37h PERIODICLISTBASE Periodic Frame List Base Address 00000000h R/W, RO
Current Asynchronous List
38h–3Bh ASYNCLISTADDR 00000000h R/W, RO
Address
3Ch–5Fh — Reserved 0h RO
60h–63h CONFIGFLAG Configure Flag 00000000h Suspend R/W, RO
64h–67h PORT1SC Port 1 Status and Control 00003000h Suspend R/W, R/WC, RO
68h–6Bh PORT2SC Port 2 Status and Control 00003000h Suspend R/W, R/WC, RO
6Ch–6Fh PORT3SC Port 3 Status and Control 00003000h Suspend R/W, R/WC, RO
A0h–B3h — Debug Port Registers Undefined R/W, RO
B4h–3FFh — Reserved Undefined RO
Note: Software must read and write these registers using only DWord accesses.These
registers are divided into two sets. The first set at offsets MEM_BASE + 00:3Bh are
implemented in the core power well. Unless otherwise noted, the core well registers are
reset by the assertion of any of the following:
• Core well hardware reset
• HCRESET
• D3-to-D0 reset
The second set at offsets MEM_BASE + 60h to the end of the implemented register
space are implemented in the Suspend power well. Unless otherwise noted, the
suspend well registers are reset by the assertion of either of the following:
• Suspend well hardware reset
• HCRESET
15.2.2.1 USB2.0_CMD—USB 2.0 Command Register
Offset: MEM_BASE + 20–23h Attribute: R/W, RO
Default Value: 00080000h Size: 32 bits
Bit Description
31:24 Reserved
678 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
Bit Description
Interrupt Threshold Control—R/W. System software uses this field to select the
maximum rate at which the host controller will issue interrupts. The only valid values
are defined below. If software writes an invalid value to this register, the results are
undefined.
Value Maximum Interrupt Interval
00h Reserved
01h 1 micro-frame
23:16
02h 2 micro-frames
04h 4 micro-frames
08h 8 micro-frames (default, equates to 1 ms)
10h 16 micro-frames (2 ms)
20h 32 micro-frames (4 ms)
40h 64 micro-frames (8 ms)
15:14 Reserved
Asynch Schedule Update (ASC)—R/W. This bit is used by the EHCI Asycnh schedule
caching function.when operating in C0 mode. it is ignored when Asynch caching
13 operates in Cx mode. When this bit is set, it allows the asynch schedule to be cached.
When cleared, it causes the cache to be disabled and all modified entries to be written
back.
Periodic Schedule Prefetch Enable—R/W. This bit is used by software to enable the
host controller to prefetch the periodic schedule even in C0.
0 = Pre-fetch based pause enabled only when not in C0.
1 = Pre-fetch based pause enable in C0.
12 Once software has written a 1b to this bit to enable periodic schedule prefetching, it
must disable prefetching by writing a 0b to this bit whenever periodic schedule updates
are about to begin. Software should continue to dynamically disable and re-enable the
prefetcher surrounding any updates to the periodic scheduler (that is, until the host
controller has been reset using a HCRESET).
Unimplemented Asynchronous Park Mode Bits—RO. Hardwired to 000b indicating the
11:8
host controller does not support this optional feature.
Light Host Controller Reset—RO. Hardwired to 0. The PCH does not implement this
7
optional reset.
Interrupt on Async Advance Doorbell—R/W. This bit is used as a doorbell by
software to tell the host controller to issue an interrupt the next time it advances
asynchronous schedule.
0 = The host controller sets this bit to a 0 after it has set the Interrupt on Async
Advance status bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 5) in the USB2.0_STS
register to a 1.
1 = Software must write a 1 to this bit to ring the doorbell. When the host controller
6 has evicted all appropriate cached schedule state, it sets the Interrupt on Async
Advance status bit in the USB2.0_STS register. If the Interrupt on Async Advance
Enable bit in the USB2.0_INTR register (D29:F0, D26:F0:CAPLENGTH + 28h, bit 5)
is a 1 then the host controller will assert an interrupt at the next interrupt
threshold. See the EHCI specification for operational details.
NOTE: Software should not write a 1 to this bit when the asynchronous schedule is
inactive. Doing so will yield undefined results.
Asynchronous Schedule Enable—R/W. This bit controls whether the host controller
skips processing the Asynchronous Schedule.
5
0 = Do not process the Asynchronous Schedule
1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
Datasheet 679
EHCI Controller Registers (D29:F0, D26:F0)
Bit Description
Interrupt Threshold Control—R/W. System software uses this field to select the
maximum rate at which the host controller will issue interrupts. The only valid values
are defined below. If software writes an invalid value to this register, the results are
undefined.
Value Maximum Interrupt Interval
00h Reserved
01h 1 micro-frame
23:16
02h 2 micro-frames
04h 4 micro-frames
08h 8 micro-frames (default, equates to 1 ms)
10h 16 micro-frames (2 ms)
20h 32 micro-frames (4 ms)
40h 64 micro-frames (8 ms)
15:14 Reserved
Asynch Schedule Update (ASC)—R/W. This bit is used by the EHCI Asycnh schedule
caching function.when operating in C0 mode. it is ignored when Asynch caching
13 operates in Cx mode. When this bit is set, it allows the asynch schedule to be cached.
When cleared, it causes the cache to be disabled and all modified entries to be written
back.
Periodic Schedule Prefetch Enable—R/W. This bit is used by software to enable the
host controller to prefetch the periodic schedule even in C0.
0 = Pre-fetch based pause enabled only when not in C0.
1 = Pre-fetch based pause enable in C0.
12 Once software has written a 1b to this bit to enable periodic schedule prefetching, it
must disable prefetching by writing a 0b to this bit whenever periodic schedule updates
are about to begin. Software should continue to dynamically disable and re-enable the
prefetcher surrounding any updates to the periodic scheduler (that is, until the host
controller has been reset using a HCRESET).
Unimplemented Asynchronous Park Mode Bits—RO. Hardwired to 000b indicating the
11:8
host controller does not support this optional feature.
Light Host Controller Reset—RO. Hardwired to 0. The PCH does not implement this
7
optional reset.
Interrupt on Async Advance Doorbell—R/W. This bit is used as a doorbell by
software to tell the host controller to issue an interrupt the next time it advances
asynchronous schedule.
0 = The host controller sets this bit to a 0 after it has set the Interrupt on Async
Advance status bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 5) in the USB2.0_STS
register to a 1.
1 = Software must write a 1 to this bit to ring the doorbell. When the host controller
6 has evicted all appropriate cached schedule state, it sets the Interrupt on Async
Advance status bit in the USB2.0_STS register. If the Interrupt on Async Advance
Enable bit in the USB2.0_INTR register (D29:F0, D26:F0:CAPLENGTH + 28h, bit 5)
is a 1 then the host controller will assert an interrupt at the next interrupt
threshold. See the EHCI specification for operational details.
NOTE: Software should not write a 1 to this bit when the asynchronous schedule is
inactive. Doing so will yield undefined results.
Asynchronous Schedule Enable—R/W. This bit controls whether the host controller
skips processing the Asynchronous Schedule.
5
0 = Do not process the Asynchronous Schedule
1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
680 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
Bit Description
Interrupt Threshold Control—R/W. System software uses this field to select the
maximum rate at which the host controller will issue interrupts. The only valid values
are defined below. If software writes an invalid value to this register, the results are
undefined.
Value Maximum Interrupt Interval
00h Reserved
01h 1 micro-frame
23:16
02h 2 micro-frames
04h 4 micro-frames
08h 8 micro-frames (default, equates to 1 ms)
10h 16 micro-frames (2 ms)
20h 32 micro-frames (4 ms)
40h 64 micro-frames (8 ms)
15:14 Reserved
Asynch Schedule Update (ASC)—R/W. This bit is used by the EHCI Asycnh schedule
caching function.when operating in C0 mode. it is ignored when Asynch caching
13 operates in Cx mode. When this bit is set, it allows the asynch schedule to be cached.
When cleared, it causes the cache to be disabled and all modified entries to be written
back.
Periodic Schedule Prefetch Enable—R/W. This bit is used by software to enable the
host controller to prefetch the periodic schedule even in C0.
0 = Pre-fetch based pause enabled only when not in C0.
1 = Pre-fetch based pause enable in C0.
12 Once software has written a 1b to this bit to enable periodic schedule prefetching, it
must disable prefetching by writing a 0b to this bit whenever periodic schedule updates
are about to begin. Software should continue to dynamically disable and re-enable the
prefetcher surrounding any updates to the periodic scheduler (that is, until the host
controller has been reset using a HCRESET).
Unimplemented Asynchronous Park Mode Bits—RO. Hardwired to 000b indicating the
11:8
host controller does not support this optional feature.
Light Host Controller Reset—RO. Hardwired to 0. The PCH does not implement this
7
optional reset.
Interrupt on Async Advance Doorbell—R/W. This bit is used as a doorbell by
software to tell the host controller to issue an interrupt the next time it advances
asynchronous schedule.
0 = The host controller sets this bit to a 0 after it has set the Interrupt on Async
Advance status bit (D29:F0, D26:F0:CAPLENGTH + 24h, bit 5) in the USB2.0_STS
register to a 1.
1 = Software must write a 1 to this bit to ring the doorbell. When the host controller
6 has evicted all appropriate cached schedule state, it sets the Interrupt on Async
Advance status bit in the USB2.0_STS register. If the Interrupt on Async Advance
Enable bit in the USB2.0_INTR register (D29:F0, D26:F0:CAPLENGTH + 28h, bit 5)
is a 1 then the host controller will assert an interrupt at the next interrupt
threshold. See the EHCI specification for operational details.
NOTE: Software should not write a 1 to this bit when the asynchronous schedule is
inactive. Doing so will yield undefined results.
Asynchronous Schedule Enable—R/W. This bit controls whether the host controller
skips processing the Asynchronous Schedule.
5
0 = Do not process the Asynchronous Schedule
1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
Datasheet 681
EHCI Controller Registers (D29:F0, D26:F0)
Bit Description
Periodic Schedule Enable—R/W. This bit controls whether the host controller skips
processing the Periodic Schedule.
4
0 = Do not process the Periodic Schedule
1 = Use the PERIODICLISTBASE register to access the Periodic Schedule.
Frame List Size—RO. This field is R/W only if Programmable Frame List Flag in the
HCCPARAMS registers is set to a one. This field specifies the size of the frame list.
3:2 00b = 1024 elements (4096 bytes) - Default value
01b = 512 elements (2048 bytes)
10b = 256 elements (1024 bytes) for resource constrained environments.
Host Controller Reset (HCRESET)—R/W. This control bit used by software to reset
the host controller. The effects of this on root hub registers are similar to a Chip
Hardware Reset (that is, RSMRST# assertion and PWROK de-assertion on the PCH).
When software writes a 1 to this bit, the host controller resets its internal pipelines,
timers, counters, state machines, and so on to their initial value. Any transaction
currently in progress on USB is immediately terminated. A USB reset is not driven on
downstream ports.
NOTE: PCI configuration registers and Host controller capability registers are not
effected by this reset.
1
All operational registers, including port registers and port state machines are set to
their initial values. Port ownership reverts to the companion host controller(s), with the
side effects described in the EHCI specification. Software must re-initialize the host
controller in order to return the host controller to an operational state.
This bit is set to 0 by the host controller when the reset process is complete. Software
cannot terminate the reset process early by writing a 0 to this register.
Software should not set this bit to a 1 when the HCHalted bit (D29:F0,
D26:F0:CAPLENGTH + 24h, bit 12) in the USB2.0_STS register is a 0. Attempting to
reset an actively running host controller will result in undefined behavior. This reset me
be used to leave EHCI port test modes.
Run/Stop (RS)—R/W.
0 = Stop (default)
1 = Run. When set to a 1, the Host controller proceeds with execution of the schedule.
The Host controller continues execution as long as this bit is set. When this bit is
set to 0, the Host controller completes the current transaction on the USB and then
halts. The HCHalted bit in the USB2.0_STS register indicates when the Host
controller has finished the transaction and has entered the stopped state.
Software should not write a 1 to this field unless the host controller is in the Halted
state (that is, HCHalted in the USBSTS register is a 1). The Halted bit is cleared
immediately when the Run bit is set.
The following table explains how the different combinations of Run and Halted should
0 be interpreted:
Run/Stop Halted Interpretation
0b 0b In the process of halting
0b 1b Halted
1b 0b Running
1b 1b Invalid – the HCHalted bit clears immediately
Memory read cycles initiated by the EHC that receive any status other than Successful
will result in this bit being cleared.
NOTE: The Command Register indicates the command to be executed by the serial bus host
controller. Writing to the register causes a command to be executed.
682 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.2.2.2 USB2.0_STS—USB 2.0 Status Register
Offset: MEM_BASE + 24h–27h Attribute: R/WC, RO
Default Value: 00001000h Size: 32 bits
This register indicates pending interrupts and various states of the Host controller. The
status resulting from a transaction on the serial bus is not indicated in this register. See
the Interrupts description in section 4 of the EHCI specification for additional
information concerning USB 2.0 interrupt conditions.
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 has
no effect.
Bit Description
31:16 Reserved
Asynchronous Schedule Status RO. This bit reports the current real status of the
Asynchronous Schedule.
0 = Disabled. (Default)
1 = Enabled.
15
NOTE: The Host controller is not required to immediately disable or enable the
Asynchronous Schedule when software transitions the Asynchronous Schedule
Enable bit (D29:F0, D26:F0:CAPLENGTH + 20h, bit 5) in the USB2.0_CMD
register. When this bit and the Asynchronous Schedule Enable bit are the same
value, the Asynchronous Schedule is either enabled (1) or disabled (0).
Periodic Schedule Status RO. This bit reports the current real status of the Periodic
Schedule.
0 = Disabled. (Default)
1 = Enabled.
14
NOTE: The Host controller is not required to immediately disable or enable the Periodic
Schedule when software transitions the Periodic Schedule Enable bit (D29:F0,
D26:F0:CAPLENGTH + 20h, bit 4) in the USB2.0_CMD register. When this bit and
the Periodic Schedule Enable bit are the same value, the Periodic Schedule is
either enabled (1) or disabled (0).
Reclamation RO. This read-only status bit is used to detect an empty asynchronous
13 schedule. The operational model and valid transitions for this bit are described in
Section 4 of the EHCI Specification.
HCHalted RO.
0 = This bit is a 0 when the Run/Stop bit is a 1.
12 1 = The Host controller sets this bit to 1 after it has stopped executing as a result of the
Run/Stop bit being set to 0, either by software or by the Host controller hardware
(such as, internal error). (Default)
11:6 Reserved
Interrupt on Async Advance—R/WC. System software can force the host controller to
issue an interrupt the next time the host controller advances the asynchronous schedule
5 by writing a 1 to the Interrupt on Async Advance Doorbell bit (D29:F0,
D26:F0:CAPLENGTH + 20h, bit 6) in the USB2.0_CMD register. This bit indicates the
assertion of that interrupt source.
Datasheet 683
EHCI Controller Registers (D29:F0, D26:F0)
Bit Description
Host System Error—R/WC.
0 = No serious error occurred during a host system access involving the Host controller
module
1 = The Host controller sets this bit to 1 when a serious error occurs during a host
system access involving the Host controller module. A hardware interrupt is
generated to the system. Memory read cycles initiated by the EHC that receive any
4
status other than Successful will result in this bit being set.
When this error occurs, the Host controller clears the Run/Stop bit in the
USB2.0_CMDregister (D29:F0, D26:F0:CAPLENGTH + 20h, bit 0) to prevent further
execution of the scheduled TDs. A hardware interrupt is generated to the system (if
enabled in the Interrupt Enable Register).
Frame List Rollover—R/WC.
0 = No Frame List Index rollover from its maximum value to 0.
3 1 = The Host controller sets this bit to a 1 when the Frame List Index rolls over from its
maximum value to 0. Since the PCH only supports the 1024-entry Frame List Size,
the Frame List Index rolls over every time FRNUM13 toggles.
Port Change Detect—R/WC. This bit is allowed to be maintained in the Auxiliary power
well. Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC
device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force
port resume, overcurrent change, enable/disable change and connect status change).
Regardless of the implementation, when this bit is readable (that is, in the D0 state), it
2 must provide a valid view of the Port Status registers.
0 = No change bit transition from a 0 to 1 or No Force Port Resume bit transition from 0
to 1 as a result of a J-K transition detected on a suspended port.
1 = The Host controller sets this bit to 1 when any port for which the Port Owner bit is
set to 0 has a change bit transition from a 0 to 1 or a Force Port Resume bit
transition from 0 to 1 as a result of a J-K transition detected on a suspended port.
USB Error Interrupt (USBERRINT)—R/WC.
0 = No error condition.
1 = The Host controller sets this bit to 1 when completion of a USB transaction results in
1 an error condition (such as, error counter underflow). If the TD on which the error
interrupt occurred also had its IOC bit set, both this bit and Bit 0 are set. See the
EHCI specification for a list of the USB errors that will result in this interrupt being
asserted.
USB Interrupt (USBINT)—R/WC.
0 = No completion of a USB transaction whose Transfer Descriptor had its IOC bit set.
No short packet is detected.
0 1 = The Host controller sets this bit to 1 when the cause of an interrupt is a completion
of a USB transaction whose Transfer Descriptor had its IOC bit set.
The Host controller also sets this bit to 1 when a short packet is detected (actual
number of bytes received was less than the expected number of bytes).
684 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.2.2.3 USB2.0_INTR—USB 2.0 Interrupt Enable Register
Offset: MEM_BASE + 28h–2Bh Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
This register enables and disables reporting of the corresponding interrupt to the
software. When a bit is set and the corresponding interrupt is active, an interrupt is
generated to the host. Interrupt sources that are disabled in this register still appear in
the USB2.0_STS Register to allow the software to poll for events. Each interrupt enable
bit description indicates whether it is dependent on the interrupt threshold mechanism
(see Section 4 of the EHCI specification), or not.
Bit Description
31:6 Reserved
Interrupt on Async Advance Enable—R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the Interrupt on Async Advance bit (D29:F0,
5
D26:F0:CAPLENGTH + 24h, bit 5) in the USB2.0_STS register is a 1, the host
controller will issue an interrupt at the next interrupt threshold. The interrupt is
acknowledged by software clearing the Interrupt on Async Advance bit.
Host System Error Enable—R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the Host System Error Status bit (D29:F0,
4
D26:F0:CAPLENGTH + 24h, bit 4) in the USB2.0_STS register is a 1, the host
controller will issue an interrupt. The interrupt is acknowledged by software clearing
the Host System Error bit.
Frame List Rollover Enable—R/W.
0 = Disable.
3 1 = Enable. When this bit is a 1, and the Frame List Rollover bit (D29:F0,
D26:F0:CAPLENGTH + 24h, bit 3) in the USB2.0_STS register is a 1, the host
controller will issue an interrupt. The interrupt is acknowledged by software clearing
the Frame List Rollover bit.
Port Change Interrupt Enable—R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the Port Change Detect bit (D29:F0,
2
D26:F0:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register is a 1, the host
controller will issue an interrupt. The interrupt is acknowledged by software clearing
the Port Change Detect bit.
USB Error Interrupt Enable—R/W.
0 = Disable.
1 = Enable. When this bit is a 1, and the USBERRINT bit (D29:F0, D26:F0:CAPLENGTH
1
+ 24h, bit 1) in the USB2.0_STS register is a 1, the host controller will issue an
interrupt at the next interrupt threshold. The interrupt is acknowledged by software
by clearing the USBERRINT bit in the USB2.0_STS register.
USB Interrupt Enable—R/W.
0 = Disable.
0 1 = Enable. When this bit is a 1, and the USBINT bit (D29:F0, D26:F0:CAPLENGTH +
24h, bit 0) in the USB2.0_STS register is a 1, the host controller will issue an
interrupt at the next interrupt threshold. The interrupt is acknowledged by software
by clearing the USBINT bit in the USB2.0_STS register.
Datasheet 685
EHCI Controller Registers (D29:F0, D26:F0)
15.2.2.4 FRINDEX—Frame Index Register
Offset: MEM_BASE + 2Ch–2Fh Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
The SOF frame number value for the bus SOF token is derived or alternatively managed
from this register. Refer to Section 4 of the EHCI specification for a detailed explanation
of the SOF value management requirements on the host controller. The value of
FRINDEX must be within 125 µs (1 micro-frame) ahead of the SOF token value. The
SOF value may be implemented as an 11-bit shadow register. For this discussion, this
shadow register is 11 bits and is named SOFV. SOFV updates every 8 micro-frames
(1 millisecond). An example implementation to achieve this behavior is to increment
SOFV each time the FRINDEX[2:0] increments from 0 to 1.
Software must use the value of FRINDEX to derive the current micro-frame number,
both for high-speed isochronous scheduling purposes and to provide the get micro-
frame number function required to client drivers. Therefore, the value of FRINDEX and
the value of SOFV must be kept consistent if chip is reset or software writes to
FRINDEX. Writes to FRINDEX must also write-through FRINDEX[13:3] to
SOFV[10:0]. In order to keep the update as simple as possible, software should never
write a FRINDEX value where the three least significant bits are 111b or 000b.
Note: This register is used by the host controller to index into the periodic frame list. The
register updates every 125 microseconds (once each micro-frame). Bits [12:3] are
used to select a particular entry in the Periodic Frame List during periodic schedule
execution. The number of bits used for the index is fixed at 10 for the PCH since it only
supports 1024-entry frame lists. This register must be written as a DWord. Word and
byte writes produce undefined results. This register cannot be written unless the Host
controller is in the Halted state as indicated by the HCHalted bit (D29:F0,
D26:F0:CAPLENGTH + 24h, bit 12). A write to this register while the Run/Stop bit
(D29:F0, D26:F0:CAPLENGTH + 20h, bit 0) is set to a 1 (USB2.0_CMD register)
produces undefined results. Writes to this register also effect the SOF value. See
Section 4 of the EHCI specification for details.
Bit Description
31:14 Reserved
Frame List Current Index/Frame Number—R/W. The value in this register
increments at the end of each time frame (such as, micro-frame).
13:0 Bits [12:3] are used for the Frame List current index. This means that each location of
the frame list is accessed 8 times (frames or micro-frames) before moving to the next
index.
686 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.2.2.5 CTRLDSSEGMENT—Control Data Structure Segment
Register
Offset: MEM_BASE + 30h–33h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
This 32-bit register corresponds to the most significant address bits [63:32] for all
EHCI data structures. Since the PCH hardwires the 64-bit Addressing Capability field in
HCCPARAMS to 1, this register is used with the link pointers to construct 64-bit
addresses to EHCI control data structures. This register is concatenated with the link
pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data
structure link field to construct a 64-bit address. This register allows the host software
to locate all control data structures within the same 4 GB memory segment.
Bit Description
Upper Address[63:44]—RO. Hardwired to 0s. The PCH EHC is only capable of
31:12
generating addresses up to 16 terabytes (44 bits of address).
Upper Address[43:32]—R/W. This 12-bit field corresponds to address bits 43:32
11:0
when forming a control data structure address.
15.2.2.6 PERIODICLISTBASE—Periodic Frame List Base Address
Register
Offset: MEM_BASE + 34h–37h Attribute: R/W
Default Value: 00000000h Size: 32 bits
This 32-bit register contains the beginning address of the Periodic Frame List in the
system memory. Since the PCH host controller operates in 64-bit mode (as indicated by
the 1 in the 64-bit Addressing Capability field in the HCCSPARAMS register) (offset 08h,
bit 0), then the most significant 32 bits of every control data structure address comes
from the CTRLDSSEGMENT register. HCD loads this register prior to starting the
schedule execution by the host controller. The memory structure referenced by this
physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this
register are combined with the Frame Index Register (FRINDEX) to enable the Host
controller to step through the Periodic Frame List in sequence.
Bit Description
Base Address (Low)—R/W. These bits correspond to memory address signals 31:12,
31:12
respectively.
11:0 Reserved
Datasheet 687
EHCI Controller Registers (D29:F0, D26:F0)
15.2.2.7 ASYNCLISTADDR—Current Asynchronous List Address
Register
Offset: MEM_BASE + 38h–3Bh Attribute: R/W
Default Value: 00000000h Size: 32 bits
This 32-bit register contains the address of the next asynchronous queue head to be
executed. Since the PCH host controller operates in 64-bit mode (as indicated by a 1 in
64-bit Addressing Capability field in the HCCPARAMS register) (offset 08h, bit 0), then
the most significant 32 bits of every control data structure address comes from the
CTRLDSSEGMENT register (offset 08h). Bits [4:0] of this register cannot be modified by
system software and will always return 0s when read. The memory structure
referenced by this physical memory pointer is assumed to be 32-byte aligned.
Bit Description
Link Pointer Low (LPL)—R/W. These bits correspond to memory address signals
31:5
31:5, respectively. This field may only reference a Queue Head (QH).
4:0 Reserved
15.2.2.8 CONFIGFLAG—Configure Flag Register
Offset: MEM_BASE + 60h–63h Attribute: R/W
Default Value: 00000000h Size: 32 bits
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset.
Bit Description
31:1 Reserved
Configure Flag (CF)—R/W. Host software sets this bit as the last action in its process
of configuring the Host controller. This bit controls the default port-routing control logic.
Bit values and side-effects are listed below. See Chapter 4 of the EHCI specification for
0
operation details.
0 = Compatibility debug only (default).
1 = Port routing control logic default-routes all ports to this host controller.
688 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.2.2.9 PORTSC—Port N Status and Control Register
Offset: Port 0 RMH: MEM_BASE + 64h–67h
Port 1 Debug Port: MEM_BASE + 68–6Bh
Port 2 USB redirect (if enabled): MEM_BASE + 6C–6Fh
Attribute: R/W, R/WC, RO
Default Value: 00003000h Size: 32 bits
Note: This register is associated with the upstream ports of the EHCI controller and does not
represent downstream hub ports. USB Hub class commands must be used to determine
RMH port status and enable test modes. See Chapter 11 of the USB Specification,
Revision 2.0 for more details. Rate Matching Hub wake capabilities can be configured
by the RMHWKCTL Register (RCBA+35B0h) located in the Chipset Configuration
chapter.
A host controller must implement one or more port registers. Software uses the N_Port
information from the Structural Parameters Register to determine how many ports
need to be serviced. All ports have the structure defined below. Software must not
write to unreported Port Status and Control Registers.
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset. The initial
conditions of a port are:
• No device connected
• Port disabled.
When a device is attached, the port state transitions to the attached state and system
software will process this as with any status change notification. Refer to Section 4 of
the EHCI specification for operational requirements for how change events interact with
port suspend mode.
Bit Description
31:23 Reserved
Wake on Overcurrent Enable (WKOC_E)—R/W.
0 = Disable. (Default)
22 1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15) when the overcurrent Active
bit (bit 4 of this register) is set.
Wake on Disconnect Enable (WKDSCNNT_E)—R/W.
0 = Disable. (Default)
21 1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15) when the Current Connect
Status changes from connected to disconnected (that is, bit 0 of this register
changes from 1 to 0).
Wake on Connect Enable (WKCNNT_E)—R/W.
0 = Disable. (Default)
20 1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15) when the Current Connect
Status changes from disconnected to connected (that is, bit 0 of this register
changes from 0 to 1).
Datasheet 689
EHCI Controller Registers (D29:F0, D26:F0)
Bit Description
Port Test Control—R/W. When this field is 0s, the port is NOT operating in a test mode.
A non-zero value indicates that it is operating in test mode and the specific test mode is
indicated by the specific value. The encoding of the test mode bits are (0110b – 1111b
are reserved):
Value Maximum Interrupt Interval
0000b Test mode not enabled (default)
19:16 0001b Test J_STATE
0010b Test K_STATE
0011b Test SE0_NAK
0100b Test Packet
0101b FORCE_ENABLE
Refer to the USB Specification Revision 2.0, Chapter 7 for details on each test mode.
15:14 Reserved
Port Owner—R/W. This bit unconditionally goes to a 0 when the Configured Flag bit in
the USB2.0_CMD register makes a 0 to 1 transition.
System software uses this field to release ownership of the port to a selected host
13 controller (in the event that the attached device is not a high-speed device). Software
writes a 1 to this bit when the attached device is not a high-speed device. A 1 in this bit
means that a companion host controller owns and controls the port. See Section 4 of the
EHCI Specification for operational details.
Port Power (PP)—RO. Read-only with a value of 1. This indicates that the port does
12
have power.
Line Status—RO.These bits reflect the current logical levels of the D+ (bit 11) and D–
(bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to
the port reset and enable sequence. This field is valid only when the port enable bit is 0
and the current connect status bit is set to a 1.
11:10
00 = SE0
10 = J-state
01 = K-state
11 = Undefined
9 Reserved
Port Reset—R/W. When software writes a 1 to this bit (from a 0), the bus reset
sequence as defined in the USB Specification, Revision 2.0 is started. Software writes a
0 to this bit to terminate the bus reset sequence. Software must keep this bit at a 1 long
enough to ensure the reset sequence completes as specified in the USB Specification,
Revision 2.0.
1 = Port is in Reset.
0 = Port is not in Reset.
NOTE: When software writes a 0 to this bit, there may be a delay before the bit status
changes to a 0. The bit status will not read as a 0 until after the reset has
completed. If the port is in high-speed mode after reset is complete, the host
8 controller will automatically enable this port (such as, set the Port Enable bit to a
1). A host controller must terminate the reset and stabilize the state of the port
within 2 milliseconds of software transitioning this bit from 0 to 1.
For example: if the port detects that the attached device is high-speed during
reset, then the host controller must have the port in the enabled state within
2 ms of software writing this bit to a 0. The HCHalted bit (D29:F0,
D26:F0:CAPLENGTH + 24h, bit 12) in the USB2.0_STS register should be a 0
before software attempts to use this bit. The host controller may hold Port Reset
asserted to a 1 when the HCHalted bit is a 1. This bit is 0 if Port Power is 0
NOTE: System software should not attempt to reset a port if the HCHalted bit in the
USB2.0_STS register is a 1. Doing so will result in undefined behavior.
690 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
Bit Description
Suspend—R/W.
0 = Port not in suspend state.(Default)
1 = Port in suspend state.
Port Enabled Bit and Suspend bit of this register define the port states as follows:
Port Enabled Suspend Port State
0 X Disabled
1 0 Enabled
7 1 1 Suspend
When in suspend state, downstream propagation of data is blocked on this port, except
for port reset. The bit status does not change until the port is suspended and that there
may be a delay in suspending a port depending on the activity on the port.
The host controller will unconditionally set this bit to a 0 when software sets the Force
Port Resume bit to a 0 (from a 1). A write of 0 to this bit is ignored by the host
controller.
If host software sets this bit to a 1 when the port is not enabled (that is, Port enabled bit
is a 0), the results are undefined.
Force Port Resume—R/W.
0 = No resume (K-state) detected/driven on port. (Default)
1 = Resume detected/driven on port. Software sets this bit to a 1 to drive resume
signaling. The Host controller sets this bit to a 1 if a J-to-K transition is detected
while the port is in the Suspend state. When this bit transitions to a 1 because a
J-to-K transition is detected, the Port Change Detect bit (D29:F0,
D26:F0:CAPLENGTH + 24h, bit 2) in the USB2.0_STS register is also set to a 1. If
software sets this bit to a 1, the host controller must not set the Port Change Detect
6 bit.
NOTE: When the EHCI controller owns the port, the resume sequence follows the
defined sequence documented in the USB Specification, Revision 2.0. The
resume signaling (Full-speed 'K') is driven on the port as long as this bit remains
a 1. Software must appropriately time the Resume and set this bit to a 0 when
the appropriate amount of time has elapsed. Writing a 0 (from 1) causes the port
to return to high-speed mode (forcing the bus below the port into a high-speed
idle). This bit will remain a 1 until the port has switched to the high-speed idle.
Overcurrent Change—R/WC. The functionality of this bit is not dependent upon the
port owner. Software clears this bit by writing a 1 to it.
5
0 = No change. (Default)
1 = There is a change to Overcurrent Active.
Overcurrent Active—RO.
0 = This port does not have an overcurrent condition. (Default)
4 1 = This port currently has an overcurrent condition. This bit will automatically
transition from 1 to 0 when the over current condition is removed. The PCH
automatically disables the port when the overcurrent active bit is 1.
Port Enable/Disable Change—R/WC. For the root hub, this bit gets set to a 1 only
when a port is disabled due to the appropriate conditions existing at the EOF2 point (See
Chapter 11 of the USB Specification for the definition of a port error). This bit is not set
3 due to the Disabled-to-Enabled transition, nor due to a disconnect. Software clears this
bit by writing a 1 to it.
0 = No change in status. (Default).
1 = Port enabled/disabled status has changed.
Port Enabled/Disabled—R/W. Ports can only be enabled by the host controller as a
part of the reset and enable. Software cannot enable a port by writing a 1 to this bit.
Ports can be disabled by either a fault condition (disconnect event or other fault
condition) or by host software. The bit status does not change until the port state
2 actually changes. There may be a delay in disabling or enabling a port due to other host
controller and bus events.
0 = Disable
1 = Enable (Default)
Datasheet 691
EHCI Controller Registers (D29:F0, D26:F0)
Bit Description
Connect Status Change—R/WC. This bit indicates a change has occurred in the port’s
Current Connect Status. Software sets this bit to 0 by writing a 1 to it.
0 = No change (Default).
1 1 = Change in Current Connect Status. The host controller sets this bit for all changes to
the port device connect status, even if system software has not cleared an existing
connect status change. For example, the insertion status changes twice before
system software has cleared the changed condition, hub hardware will be “setting”
an already-set bit (that is, the bit will remain set).
Current Connect Status—RO. This value reflects the current state of the port, and
may not correspond directly to the event that caused the Connect Status Change bit (Bit
0 1) to be set.
0 = No device is present. (Default)
1 = Device is present on port.
15.2.3 USB 2.0-Based Debug Port Registers
The Debug port’s registers are located in the same memory area, defined by the Base
Address Register (MEM_BASE), as the standard EHCI registers. The base offset for the
debug port registers (A0h) is declared in the Debug Port Base Offset Capability Register
at Configuration offset 5Ah (D29:F0, D26:F0:offset 5Ah). The specific EHCI port that
supports this debug capability (Port 1 for D29:F0 and Port 9 for D26:F0) is indicated by
a 4-bit field (bits 20–23) in the HCSPARAMS register of the EHCI controller. The address
map of the Debug Port registers is shown in Table 15-4.
Table 15-4. Debug Port Register Address Map
MEM_BASE +
Mnemonic Register Name Default Attribute
Offset
R/W, R/WC,
A0–A3h CNTL_STS Control / Status 00000000h
RO
A4–A7h USBPID USB PIDs 00000000h R/W, RO
00000000
A8–AFh DATABUF[7:0] Data Buffer (Bytes 7:0) R/W
00000000h
B0–B3h CONFIG Configuration 00007F01h R/W
NOTES:
1. All of these registers are implemented in the core well and reset by PLTRST#, EHC
HCRESET, and a EHC D3-to-D0 transition.
2. The hardware associated with this register provides no checks to ensure that software
programs the interface correctly. How the hardware behaves when programmed
improperly is undefined.
692 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.2.3.1 CNTL_STS—Control / Status Register
Offset: MEM_BASE + A0h Attribute: R/W, R/WC, RO
Default Value: 00000000h Size: 32 bits
Power well: Suspend
Bit Description
31 Reserved
OWNER_CNT—R/W.
0 = Ownership of the debug port is NOT forced to the EHCI controller (Default)
30 1 = Ownership of the debug port is forced to the EHCI controller (that is, immediately
taken away from the companion Classic USB Host controller) If the port was
already owned by the EHCI controller, then setting this bit has no effect. This bit
overrides all of the ownership-related bits in the standard EHCI registers.
29 Reserved
ENABLED_CNT—R/W.
0 = Software can clear this by writing a 0 to it. The hardware clears this bit for the
same conditions where the Port Enable/Disable Change bit (in the PORTSC
28 register) is set. (Default)
1 = Debug port is enabled for operation. Software can directly set this bit if the port is
already enabled in the associated PORTSC register (this is enforced by the
hardware).
27:17 Reserved
DONE_STS—R/WC. Software can clear this by writing a 1 to it.
16 0 = Request Not complete
1 = Set by hardware to indicate that the request is complete.
LINK_ID_STS—RO. This field identifies the link interface.
15:12
0h = Hardwired. Indicates that it is a USB Debug Port.
11 Reserved
IN_USE_CNT—R/W. Set by software to indicate that the port is in use. Cleared by
10 software to indicate that the port is free and may be used by other software. This bit
is cleared after reset. (This bit has no affect on hardware.)
EXCEPTION_STS—RO. This field indicates the exception when the
ERROR_GOOD#_STS bit is set. This field should be ignored if the
ERROR_GOOD#_STS bit is 0.
000 =No Error. (Default)
Note: This should not be seen since this field should only be checked if there is
9:7 an error.
001 =Transaction error: Indicates the USB 2.0 transaction had an error (CRC, bad
PID, timeout, and so on)
010 =Hardware error. Request was attempted (or in progress) when port was
suspended or reset.
All Other combinations are reserved.
ERROR_GOOD#_STS—RO.
0 = Hardware clears this bit to 0 after the proper completion of a read or write.
6 (Default)
1 = Error has occurred. Details on the nature of the error are provided in the
Exception field.
GO_CNT—R/W.
0 = Hardware clears this bit when hardware sets the DONE_STS bit. (Default)
5 1 = Causes hardware to perform a read or write request.
NOTE: Writing a 1 to this bit when it is already set may result in undefined behavior.
Datasheet 693
EHCI Controller Registers (D29:F0, D26:F0)
Bit Description
WRITE_READ#_CNT—R/W. Software clears this bit to indicate that the current
request is a read. Software sets this bit to indicate that the current request is a write.
4
0 = Read (Default)
1 = Write
DATA_LEN_CNT—R/W. This field is used to indicate the size of the data to be
transferred.
default = 0h.
For write operations, this field is set by software to indicate to the hardware how
many bytes of data in Data Buffer are to be transferred to the console. A value of 0h
indicates that a zero-length packet should be sent. A value of 1–8 indicates 1–8 bytes
are to be transferred. Values 9–Fh are invalid and how hardware behaves if used is
3:0 undefined.
For read operations, this field is set by hardware to indicate to software how many
bytes in Data Buffer are valid in response to a read operation. A value of 0h indicates
that a zero length packet was returned and the state of Data Buffer is not defined. A
value of 1–8 indicates 1–8 bytes were received. Hardware is not allowed to return
values 9–Fh.
The transferring of data always starts with byte 0 in the data area and moves toward
byte 7 until the transfer size is reached.
NOTES:
1. Software should do Read-Modify-Write operations to this register to preserve the contents
of bits not being modified. This include Reserved bits.
2. To preserve the usage of RESERVED bits in the future, software should always write the
same value read from the bit until it is defined. Reserved bits will always return 0 when
read.
15.2.3.2 USBPID—USB PIDs Register
Offset: MEM_BASE + A4h–A7h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Power well: Suspend
This DWord register is used to communicate PID information between the USB debug
driver and the USB debug port. The debug port uses some of these fields to generate
USB packets, and uses other fields to return PID information to the USB debug driver.
Bit Description
31:24 Reserved
RECEIVED_PID_STS[23:16]—RO. Hardware updates this field with the received PID
for transactions in either direction. When the controller is writing data, this field is
updated with the handshake PID that is received from the device. When the host
23:16
controller is reading data, this field is updated with the data packet PID (if the device
sent data), or the handshake PID (if the device NAKs the request). This field is valid
when the hardware clears the GO_DONE#_CNT bit.
SEND_PID_CNT[15:8]—R/W. Hardware sends this PID to begin the data packet
15:8 when sending data to USB (that is, WRITE_READ#_CNT is asserted). Software
typically sets this field to either DATA0 or DATA1 PID values.
TOKEN_PID_CNT[7:0]—R/W. Hardware sends this PID as the Token PID for each
7:0 USB transaction. Software typically sets this field to either IN, OUT, or SETUP PID
values.
694 Datasheet
EHCI Controller Registers (D29:F0, D26:F0)
15.2.3.3 DATABUF[7:0]—Data Buffer Bytes[7:0] Register
Offset: MEM_BASE + A8h–AFh Attribute: R/W
Default Value: 0000000000000000h Size: 64 bits
This register can be accessed as 8 separate 8-bit registers or 2 separate 32-bit register.
Bit Description
DATABUFFER[63:0]—R/W. This field is the 8 bytes of the data buffer. Bits 7:0
correspond to least significant byte (byte 0). Bits 63:56 correspond to the most
significant byte (byte 7).
63:0 The bytes in the Data Buffer must be written with data before software initiates a write
request. For a read request, the Data Buffer contains valid data when DONE_STS bit
(offset A0, bit 16) is cleared by the hardware, ERROR_GOOD#_STS (offset A0, bit 6) is
cleared by the hardware, and the DATA_LENGTH_CNT field (offset A0, bits 3:0)
indicates the number of bytes that are valid.
15.2.3.4 CONFIG—Configuration Register
Offset: MEM_BASE + B0–B3h Attribute: R/W
Default Value: 00007F01h Size: 32 bits
Bit Description
31:15 Reserved
USB_ADDRESS_CNF—R/W. This 7-bit field identifies the USB device address used
14:8
by the controller for all Token PID generation. (Default = 7Fh)
7:4 Reserved
USB_ENDPOINT_CNF—R/W. This 4-bit field identifies the endpoint used by the
3:0
controller for all Token PID generation. (Default = 1h)
§§
Datasheet 695
EHCI Controller Registers (D29:F0, D26:F0)
696 Datasheet
xHCI Controller Registers (D20:F0)
16 xHCI Controller Registers
(D20:F0)
16.1 USB xHCI Configuration Registers
(USB xHCI—D20:F0)
Note: Register address locations that are not shown in Table 16-1 should be treated as
Reserved (see Section 9.2 for details).
Note: “Multiple” in the Power Well column means that multiple power wells apply to this
register since the individual fields in the register may be on different power wells.
Table 16-1. USB xHCI PCI Register Address Map (USB xHCI—D20:F0)
(Sheet 1 of 2)
Power
Offset Mnemonic Register Name Default Value Type
Well
00h–01h Core VID Vendor Identification 8086h RO
See register
02h–03h Core DID Device Identification RO
description
04h–05h Core PCICMD PCI Command 0000h R/W, RO
06h–07h Core PCISTS PCI Status 0290h R/WC, RO
08h Core RID Revision Identification 00h RO
09h Core PI Programming Interface 30h RO
0Ah Core SCC Sub Class Code 03h RO
0Bh Core BCC Base Class Code 0Ch RO
0Dh Core PMLT Primary Master Latency Timer 00h RO
0Eh Core HEADTYP Header Type 00h RO
10h–13h Core MEM_BASE_L Memory Base Address Low 00000004h R/W, RO
14h–17h Core MEM_BASE_H Memory Base Address High 00000000h R/W
USB xHCI Subsystem Vendor
2Ch–2Dh Core SVID 0000h R/W
Identification
USB xHCI Subsystem
2Eh–2Fh Core SID 0000h R/W
Identification
34h Core CAP_PTR Capabilities Pointer 70h RO
3Ch Core INT_LN Interrupt Line 00h R/W
See register
3Dh Core INT_PN Interrupt Pin RO
description
40h–43h Core XHCC xHC System Bus Configuration 0000F0FDh R/W, R/WC
44h–47h Multiple XHCC2 xHC System Bus Configuration 2 00000000h R/WO
60h Sus SBRN Serial Bus Release Number 30h RO
61h Multiple FL_ADJ Frame Length Adjustment 20h R/W
Datasheet 697
xHCI Controller Registers (D20:F0)
Table 16-1. USB xHCI PCI Register Address Map (USB xHCI—D20:F0)
(Sheet 2 of 2)
Power
Offset Mnemonic Register Name Default Value Type
Well
PCI Power Management
70h Core PWR_CAPID 01h RO
Capability ID
71h Core NXT_PTR1 Next Item Pointer #1 80h R/W
72h–73h Core PWR_CAP Power Management Capabilities C9C2h R/W, RO
Power Management Control / R/W, R/WC,
74h–75h Multiple PWR_CNTL_STS 0000h
Status RO
Message Signaled Interrupt
80h Core MSI_CAPID 05h RO
Capability ID
81h Core NXT_PTR2 Next Item Pointer #2 00h RO
82h–83h Core MSI_MCTL MSI Message Control Register 0086h RO, R/W
84h–87h Core MSI_LMAD MSI Lower Message Address 00000000h RW, RO
88h–8Bh Core MSI_UMAD MSI Upper Message Address 000000h R/W
8Ch–8Fh Core MSI_MD MSI Message Data 00000000h R/W
XHCI USB2 Overcurrent Pin
C0h–C3h Sus U2OCM1 00000000h R/W, RO
Mapping 1
XHCI USB2 Overcurrent Pin
C4h–C7h Sus U2OCM2 00000000h R/W, RO
Mapping 2
XHCI USB3 Overcurrent Pin
C8h–CBh Sus U3OCM1 00000000h R/W, RO
Mapping 1
XHCI USB3 Overcurrent Pin
CCh–CFh Sus U3OCM2 00000000h R/W, RO
Mapping 2
D0h–D3h Multiple XUSB2PR xHC USB 2.0 Port Routing 00000000h R/W, RO
D4h–D7h Core XUSB2PRM xHC USB 2.0 Port Routing Mask 00000000h RO, R/WLO
USB 3.0 Port SuperSpeed Enable
D8h–dBh USB3_PSSEN 00000000h RO, R/W
Register
D8h–dBh Multiple USB3PR USB3 Port Routing 00000000h R/W, RO
DCh–DFh Core USB3PRM USB 3.0 Port Routing Mask 00000000h R/W, RO
E4h–E7h Multiple USB2PDO USB2 Port Disable Override 00000000h R/WO
E8h–EBh Multiple USB3PDO USB3 Port Disable Override 00000000h R/WO
698 Datasheet
xHCI Controller Registers (D20:F0)
16.1.1 VID—Vendor Identification Register
(USB xHCI—D20:F0)
Offset Address: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bits
Bit Description
15:0 Vendor ID—RO. This is a 16-bit value assigned to Intel.
16.1.2 DID—Device Identification Register
(USB xHCI—D20:F0)
Offset Address: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bits
Bit Description
Device ID—RO. This is a 16-bit value assigned to the PCH USB xHCI controller. See
15:0
Section 1.3 for the value of the DID Register.
Datasheet 699
xHCI Controller Registers (D20:F0)
16.1.3 PCICMD—PCI Command Register
(USB xHCI—D20:F0)
Address Offset: 04h–05h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved
Interrupt Disable—R/W.
0 = The function is capable of generating interrupts.
10 1 = The function can not generate its interrupt to the interrupt controller.
The corresponding Interrupt Status bit (D20:F0, Offset 06h, bit 3) is not affected by the
interrupt enable.
9 Fast Back to Back Enable (FBE)—RO. Hardwired to 0.
SERR# Enable (SERR_EN)—R/W.
0 = Disables xHC’s capability to generate an SERR#.
1 = The xHCI Host controller (xHC) is capable of generating (internally) SERR# in the
following cases:
8 — When it receive a completion status other than “successful” for one of its DMA initiated
memory reads on DMI (and subsequently on its internal interface).
— When it detects an address or command parity error and the Parity Error Response bit is
set.
— When it detects a data parity error (when the data is going into the xHC) and the Parity
Error Response bit is set.
7 Wait Cycle Control (WCC)—RO. Hardwired to 0.
Parity Error Response (PER)—R/W.
0 = The xHC is not checking for correct parity (on its internal interface).
1 = The xHC is checking for correct parity (on its internal interface) and halt operation
6 when bad parity is detected during the data phase.
NOTE: This applies to both requests and completions from the system interface.
This bit must be set in order for the parity errors to generate SERR#.
5 VGA Palette Snoop (VPS)—RO. Hardwired to 0.
4 Postable Memory Write Enable (PMWE)—RO. Hardwired to 0.
3 Special Cycle Enable (SCE)—RO. Hardwired to 0.
Bus Master Enable (BME)—R/W.
2 0 = Disables this functionality.
1 = Enables the xHC to act as a master on the PCI bus for USB transfers.
Memory Space Enable (MSE)—R/W. This bit controls access to the xHC Memory
Space registers.
1 0 = Disables this functionality.
1 = Enables accesses to the xHC Memory Space registers. The Base Address register
(D20:F0:10h) should be programmed before this bit is set.
0 I/O Space Enable (IOSE)—RO. Hardwired to 0.
700 Datasheet
xHCI Controller Registers (D20:F0)
16.1.4 PCISTS—PCI Status Register
(USB xHCI—D20:F0)
Address Offset: 06h–07h Attribute: R/WC, RO
Default Value: 0290h Size: 16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit Description
Detected Parity Error (DPE)—R/WC.
0 = No parity error detected.
15 1 = This bit is set by the PCH when a parity error is seen by the xHCI controller,
regardless of the setting of bit 6 or bit 8 in the Command register or any other
conditions.
Signaled System Error (SSE)—R/WC.
0 = No SERR# signaled by the PCH.
14
1 = This bit is set by the PCH when it signals SERR# (internally). The SER_EN bit (bit 8
of the Command Register) must be 1 for this bit to be set.
Received Master Abort (RMA)—R/WC.
0 = No master abort received by xHC on a memory access.
13 1 = This bit is set when xHC, as a master, receives a master abort status on a memory
access. This is treated as a Host Error and halts the DMA engines. This event can
optionally generate an SERR# by setting the SERR# Enable bit.
Received Target Abort (RTA)—R/WC.
0 = No target abort received by xHC on memory access.
12 1 = This bit is set when xHC, as a master, receives a target abort status on a memory
access. This is treated as a Host Error and halts the DMA engines. This event can
optionally generate an SERR# by setting the SERR# Enable bit.
Signaled Target Abort (STA)—RO. This bit is used to indicate when the xHCI function
11 responds to a cycle with a target abort. There is no reason for this to happen, so this bit
is hardwired to 0.
DEVSEL# Timing Status (DEVT_STS)—RO. This 2-bit field defines the timing for
10:9
DEVSEL# assertion.
Master Data Parity Error Detected (DPED)—R/WC.
0 = No data parity error detected on USB read completion packet.
8 1 = This bit is set by the PCH when a data parity error is detected on a xHC read
completion packet on the internal interface to the xHCI host controller and bit 6 of
the Command register is set to 1.
7 Fast Back to Back Capable (FB2BC)—RO. Hardwired to 1.
6 User Definable Features (UDF)—RO. Hardwired to 0.
5 66 MHz Capable (66 MHz _CAP)—RO. Hardwired to 0.
Capabilities List (CAP_LIST)—RO. Hardwired to 1 indicating that offset 34h contains a
4
valid capabilities pointer.
Interrupt Status—RO. This bit reflects the state of this function’s interrupt at the
input of the enable/disable logic.
3 0 = This bit will be 0 when the interrupt is de-asserted.
1 = This bit is a 1 when the interrupt is asserted.
The value reported in this bit is independent of the value in the Interrupt Enable bit.
2:0 Reserved
Datasheet 701
xHCI Controller Registers (D20:F0)
16.1.5 RID—Revision Identification Register
(USB xHCI—D20:F0)
Offset Address: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
Bit Description
Revision ID—RO. This field indicates the device specific revision identifier. See
7:0
Section 1.3 for the value of the Revision ID Register.
16.1.6 PI—Programming Interface Register
(USB xHCI—D20:F0)
Address Offset: 09h Attribute: RO
Default Value: 30h Size: 8 bits
Bit Description
Programming Interface—RO. A value of 30h indicates that this USB host controller
7:0
conforms to the xHCI Specification.
16.1.7 SCC—Sub Class Code Register
(USB xHCI—D20:F0)
Address Offset: 0Ah Attribute: RO
Default Value: 03h Size: 8 bits
Bit Description
Sub Class Code (SCC)—RO.
7:0
03h = Universal Serial Bus host controller.
16.1.8 BCC—Base Class Code Register
(USB xHCI—D20:F0)
Address Offset: 0Bh Attribute: RO
Default Value: 0Ch Size: 8 bits
Bit Description
Base Class Code (BCC)—RO.
7:0
0Ch = Serial bus controller.
702 Datasheet
xHCI Controller Registers (D20:F0)
16.1.9 PMLT—Primary Master Latency Timer Register
(USB xHCI—D20:F0)
Address Offset: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
Master Latency Timer Count (MLTC)—RO. Hardwired to 00h. Because the xHCI
7:0 controller is internally implemented with arbitration on an interface (and not PCI), it
does not need a master latency timer.
16.1.10 HEADTYP—Header Type Register
(USB xHCI—D20:F0)
Address Offset: 0Eh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
Multi-Function Device—RO. When set to ‘1’ indicates this is a multifunction device:
7 0 = Single-function device
1 = Multi-function device.
Configuration Layout. Hardwired to 00h, which indicates the standard PCI configuration
6:0
layout.
16.1.11 MEM_BASE_L—Memory Base Address Low Register
(USB xHCI—D20:F0)
Address Offset: 10h–13h Attribute: R/W, RO
Default Value: 00000004h Size: 32 bits
Bit Description
Base Address—R/W. Bits [31:16] correspond to memory address signals [31:16],
31:16 respectively. This gives 64 KB of relocatable memory space aligned to 64 KB
boundaries.
15:4 Reserved
3 Prefetchable—RO. Hardwired to 0 indicating that this range should not be prefetched.
Type—RO. Hardwired to 10 indicating that this range can be mapped anywhere within
2:1
64-bit address space.
Resource Type Indicator (RTE)—RO. Hardwired to 0 indicating that the base
0
address field in this register maps to memory space.
Datasheet 703
xHCI Controller Registers (D20:F0)
16.1.12 MEM_BASE_H—Memory Base Address High Register
(USB xHCI—D20:F0)
Address Offset: 14h–17h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Base Address—R/W. Bits [63:32] correspond to memory address signals [63:32],
31:0 respectively. This gives 64 KB of relocatable memory space aligned to 64 KB
boundaries.
16.1.13 SVID—USB xHCI Subsystem Vendor ID Register
(USB xHCI—D20:F0)
Address Offset: 2Ch–2Dh Attribute: R/W
Default Value: 0000h Size: 16 bits
Reset: None
Bit Description
Subsystem Vendor ID (SVID)—R/W. This register, in combination with the xHC
15:0 Subsystem ID register, enables the operating system to distinguish each subsystem
from the others.
16.1.14 SID—USB xHCI Subsystem ID Register
(USB xHCI—D20:F0)
Address Offset: 2Eh–2Fh Attribute: R/W
Default Value: 0000h Size: 16 bits
Reset: None
Bit Description
Subsystem ID (SID)—R/W. BIOS sets the value in this register to identify the
15:0 Subsystem ID. This register, in combination with the Subsystem Vendor ID register,
enables the operating system to distinguish each subsystem from other(s).
16.1.15 CAP_PTR—Capabilities Pointer Register
(USB xHCI—D20:F0)
Address Offset: 34h Attribute: RO
Default Value: 70h Size: 8 bits
Bit Description
Capabilities Pointer (CAP_PTR)—RO. This register points to the starting offset of the
7:0
xHC capabilities ranges.
704 Datasheet
xHCI Controller Registers (D20:F0)
16.1.16 INT_LN—Interrupt Line Register
(USB xHCI—D20:F0)
Address Offset: 3Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Function Level Reset: No
Bit Description
Interrupt Line (INT_LN)—R/W. This data is not used by the PCH. It is used as a
7:0 scratchpad register to communicate to software the interrupt line that the interrupt pin
is connected to.
16.1.17 INT_PN—Interrupt Pin Register
(USB xHCI—D20:F0)
Address Offset: 3Dh Attribute: RO
Default Value: See Description Size: 8 bits
Bit Description
Interrupt Pin—RO. Bits 3:0 reflect the value of the interrupt pin registers in chipset
7:0
configuration space. Bits 7:4 are always 0h
16.1.18 XHCC—xHC System Bus Configuration Register
(USB xHCI—D20:F0)
Address Offset: 40-43h Attribute: R/W, R/WC
Default Value: 0000F0FDh Size: 32 bits
Bit Description
31:25 Reserved
Master/Target Abort SERR (RMTASERR)—R/W. When set, this bit allows the out-
24 of-band error reporting from the xHCI Controller to be reported as SERR# (if SERR#
reporting is enabled) and thus setting the STS.SSE bit.
Unsupported Request Detected (URD)—R/WC. This bit is set by HW when the xHCI
23 Controller received an unsupported request posted cycle. Once set, this bit is cleared by
SW.
Unsupported Request Report Enable (URRE)—R/W. When set, this bit allows the
22 URD bit to be reported as SERR# (if SERR# reporting is enabled) and thus setting the
STS.SSE bit.
Inactivity Initiated L1 Enable (IIL1E)—R/W. If programmed to a non-zero value,
the bit field allows L1 power management to be enabled after the time-out period
specified.
000 = Disabled
001 = 32 bb_cclk
21:19 010 = 64 bb_cclk
011 = 128 bb_cclk
100 = 256 bb_cclk
101 = 512 bb_cclk
110 = 1024 bb_cclk
111 = 131072 bb_cclk
Datasheet 705
xHCI Controller Registers (D20:F0)
Bit Description
xHC Initiated L1 Enable (XHCIL1E)—R/W.
18 0 = xHC-initiated L1 power management is disabled
1 = Allows xHC-initiated L1 power management to be enabled
D3 Initiated L1 Enable (D3IL1E)—R/W.
17 0 = PCI device state D3-initiated L1 power management is disabled
1 = Allows PCI device state D3-initiated L1 power management to be enabled
16:0 Reserved
16.1.19 XHCC2—xHC System Bus Configuration Register 2
(USB xHCI—D20:F0)
Address Offset: 44-47h Attribute: R/WO
Default Value: 00000000h Size: 32 bits
Bit Description
OC Configuration Done (OCCFDONE)—R/WO. This bit is used by BIOS to prevent
spurious switching during OC configuration.
31
NOTE: This bit must be set by BIOS after configuration of the OC mapping bits is
complete. Once this bit is set, OC mapping shall not be changed by SW.
30:0 Reserved
16.1.20 SBRN—Serial Bus Release Number
Register (USB xHCI—D20:F0)
Address Offset: 60h Attribute: RO
Default Value: 30h Size: 8 bits
Bit Description
Serial Bus Release Number (SBRN)—RO. A value of 30h indicates that this controller
7:0
follows USB release 3.0.
706 Datasheet
xHCI Controller Registers (D20:F0)
16.1.21 FL_ADJ—Frame Length Adjustment Register
(USB xHCI—D20:F0)
Address Offset: 61h Attribute: R/W
Default Value: 20h Size: 8 bits
Function Level Reset: No
This feature is used to adjust any offset from the clock source that generates the clock
that drives the SOF counter. When a new value is written into these six bits, the length
of the frame is adjusted. Its initial programmed value is system dependent based on
the accuracy of hardware USB clock and is initialized by system BIOS. This register
should only be modified when the HChalted bit (D20:F0:CAPLENGTH + 84h, bit 0) in
the USB_STS register is a 1. Changing value of this register while the host controller is
operating yields undefined results. It should not be reprogrammed by USB system
software unless the default or BIOS programmed values are incorrect, or the system is
restoring the register while returning from a suspended state.
These bits in suspend well and not reset by a D3-to-D0 warm rest or a core well reset.
Bit Description
7:6 Reserved—RO. These bits are reserved for future use and should read as 00b.
Frame Length Timing Value—R/W. Each decimal value change to this register
corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter
clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this
field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000.
Frame Length (# 480 MHz Frame Length Timing Value (this
Clocks) (decimal) register) (decimal)
59488 0
5:0 59504 1
59520 2
... ...
59984 31
... ...
60496 63
60480 62
16.1.22 PWR_CAPID—PCI Power Management Capability ID
Register (USB xHCI—D20:F0)
Address Offset: 70h Attribute: RO
Default Value: 01h Size: 8 bits
Bit Description
Power Management Capability ID—RO. A value of 01h indicates that this is a PCI
7:0
Power Management capabilities field.
Datasheet 707
xHCI Controller Registers (D20:F0)
16.1.23 NXT_PTR1—Next Item Pointer #1 Register
(USB xHCI—D20:F0)
Address Offset: 71h Attribute: R/W
Default Value: 80h Size: 8 bits
Bit Description
Next Item Pointer 1 Value—R/W (special). This register defaults to 80h, which
indicates that the next capability registers begin at configuration offset 80h. This
register is writable when the ACCTRL bit (D20:F0:40h, bit 31) is ‘0’. This allows BIOS to
7:0 effectively hide the next capability registers, if necessary. This register should only be
written during system initialization before the plug-and-play software has enabled any
master-initiated traffic. Values of 80h implies the next capability is MSI. Values of 00h
implies that the MSI capability is hidden.
16.1.24 PWR_CAP—Power Management Capabilities Register
(USB xHCI—D20:F0)
Address Offset: 72h–73h Attribute: R/W, RO
Default Value: C9C2h Size: 16 bits
Bit Description
PME Support (PME_SUP)—R/W. This 5-bit field indicates the power states in which
the function may assert PME#. The PCH xHC does not support the D1 or D2 states. For
15:11
all other states, the PCH xHC is capable of generating PME#. Software should never
need to modify this field.
D2 Support (D2_SUP)—RO.
10
0 = D2 State is not supported
D1 Support (D1_SUP)—RO.
9
0 = D1 State is not supported
Auxiliary Current (AUX_CUR)—R/W. The PCH xHC reports 375 mA maximum
8:6
suspend well current required when in the D3COLD state.
Device Specific Initialization (DSI)—RO. The PCH reports 0, indicating that no
5
device-specific initialization is required.
4 Reserved
PME Clock (PME_CLK)—RO. The PCH reports 0, indicating that no PCI clock is
3
required to generate PME#.
Version (VER)—RO. The PCH reports 010b, indicating that it complies with Revision
2:0
1.1 of the PCI Power Management Specification.
NOTES:
1. Normally, this register is read-only to report capabilities to the power management
software. To report different power management capabilities, depending on the system in
which the PCH is used, the write access to this register is controlled by the Access Control
bit (D20:F0:40h, bit 31). The value written to this register does not affect the hardware
other than changing the value returned during a read.
2. This register is modified and maintained by BIOS.
3. Reset: core well, but not D3-to-D0 warm reset.
708 Datasheet
xHCI Controller Registers (D20:F0)
16.1.25 PWR_CNTL_STS—Power Management Control /
Status Register (USB xHCI—D20:F0)
Address Offset: 74h–75h Attribute: R/W, R/WC, RO
Default Value: 0000h Size: 16 bits
Bit Description
PME Status—R/WC. This bit is set when the PCH xHC would normally assert the PME#
signal independent of the state of the PME_En bit. Writing a 1 to this bit will clear it and
cause the internal PME to de-assert (if enabled).
15
NOTE: This bit must be explicitly cleared by the operating system each time the
operating system is loaded.
This bit is not reset by Function Level Reset.
Data Scale—RO. Hardwired to 00b indicating it does not support the associated Data
14:13
register.
Data Select—RO. Hardwired to 0000b indicating it does not support the associated Data
12:9
register.
PME Enable (PME_En)—R/W.
0 = Disable.
1 = Enables the PCH xHC to generate an internal PME signal when PME_Status is 1.
8
NOTE: This bit must be explicitly cleared by the operating system each time it is
initially loaded.
This bit is not reset by Function Level Reset.
7:2 Reserved
Power State—R/W. This 2-bit field is used both to determine the current power state
of EHC function and to set a new power state. The definition of the field values are:
00 = D0 state
1:0 11 = D3HOT state
If software attempts to write a value of 10b or 01b in to this field, the write operation
must complete normally; however, the data is discarded and no state change occurs.
When in the D3HOT state, the PCH must not accept accesses to the EHC memory range;
but the configuration space must still be accessible.
Datasheet 709
xHCI Controller Registers (D20:F0)
16.1.26 MSI_CAPID—Message Signaled Interrupt Capability ID
Register
(USB xHCI—D20:F0)
Address Offset: 80h Attribute: RO
Default Value: 05h Size: 8 bits
Bit Description
Capability ID—RO. Hardwired to 05h indicating that this is the start of a MSI
7:0
Capability structure.
16.1.27 NEXT_PTR2—Next Item Pointer Register #2
(USB xHCI—D20:F0)
Address Offset: 81h Attribute: RO
Default Value: 00h Size: 8 bits
Function Level Reset: No
Bit Description
7:0 Next Item Pointer Capability—RO. This register points to the next capability.
16.1.28 MSI_MCTL—MSI Message Control Register
(USB xHCI—D20:F0)
Address Offset: 82h-83h Attribute: RO, R/W
Default Value: 0086h Size: 16 bits
Bit Description
15:8 Reserved.
7 64 Bit Address Capable (C64)—RO. Capable of generating 64-bit messages.
Multiple Message Enable (MME)—RW. Indicates the number of messages the
6:4
controller should assert. This device supports multiple message MSI.
Multiple Message Capable (MMC)—RO. This field is set by HW to reflect the number
of Interrupters supported. The controller supports up to 8 interrupters.
Encoding for number of Interrupters:
000 1
001 2
3:1
010 4
011 8
100 16
101 32
110-111 Reserved
MSI Enable (MSIE)—RW. If set to 1, MSI is enabled and the traditional interrupt pins
0 are not used to generate interrupts.
If cleared to 0, MSI operation is disabled and the traditional interrupt pins are used.
710 Datasheet
xHCI Controller Registers (D20:F0)
16.1.29 MSI_LMAD—MSI Lower Message Address Register
(USB xHCI—D20:F0)
Address Offset: 84h-87h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
Lower Message Address—RW. Lower DWord of the system specified message
31:2
address.
1:0 Reserved.
16.1.30 MSI_UMAD—MSI Upper Message Address Register
(USB xHCI—D20:F0)
Address Offset: 88h-8Bh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Upper Message Address—RW. Upper DWord of the system specified message
31:0
address.
16.1.31 MSI_MD—MSI Message Data Register
(USB xHCI—D20:F0)
Address Offset: 8Ch-8Fh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:16 Reserved.
Data—R/W. This 16-bit field is programmed by system software if MSI is enabled. Its
15:0 content is driven onto the lower word (PCI AD[15:0]) during the data phase of the MSI
memory write transaction.
Datasheet 711
xHCI Controller Registers (D20:F0)
16.1.32 U2OCM1 - XHCI USB2 Overcurrent Mapping Register1
(USB xHCI—D20:F0)
Address Offset: C0–C3h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
OC3 Mapping Each bit position maps OC3# to a set of ports as follows: The OC3#
pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is software responsibility to ensure that a given port‘s bit map is set only for
31:24 one OC pin.
Bit 31 30 29 28 27 26 25 24
Port 13 12 9 8 3 2 1 0
OC2 Mapping Each bit position maps OC2# to a set of ports as follows: The OC2#
pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is software responsibility to ensure that a given port‘s bit map is set only for
23:16 one OC pin.
Bit 23 22 21 20 19 18 17 16
Port 13 12 9 8 3 2 1 0
OC1 Mapping Each bit position maps OC1# to a set of ports as follows: The OC1#
pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is software responsibility to ensure that a given port‘s bit map is set only for
15:8 one OC pin.
Bit 15 14 13 12 11 10 9 8
Port 13 12 9 8 3 2 1 0
OC0 Mapping Each bit position maps OC0# to a set of ports as follows: The OC0#
pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is software responsibility to ensure that a given port‘s bit map is set only for
7:0 one OC pin.
Bit 7 6 5 4 3 2 1 0
Port 13 12 9 8 3 2 1 0
712 Datasheet
xHCI Controller Registers (D20:F0)
16.1.33 U2OCM2 - XHCI USB2 Overcurrent Mapping Register 2
(USB xHCI—D20:F0)
Address Offset: C4–C7h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:30 Reserved
OC7 Mapping Each bit position maps OC7 to a set of ports as follows: The OC7
pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is software responsibility to ensure that a given port‘s bit map is set only for
29:24 one OC pin.
Bit 29 28 27 26 25 24
Port 11 10 7 6 5 4
23:22 Reserved
OC6 Mapping Each bit position maps OC6 to a set of ports as follows: The OC6
pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is software responsibility to ensure that a given port‘s bit map is set only for
21:16 one OC pin.
Bit 21 20 19 18 17 16
Port 11 10 7 6 5 4
15:14 Reserved
OC5 Mapping Each bit position maps OC5 to a set of ports as follows: The OC5
pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is software responsibility to ensure that a given port‘s bit map is set only for
13:8 one OC pin.
Bit 13 12 11 10 9 8
Port 11 10 7 6 5 4
7:6 Reserved
OC4 Mapping Each bit position maps OC4 to a set of ports as follows: The OC4
pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is software responsibility to ensure that a given port‘s bit map is set only for
5:0 one OC pin.
Bit 5 4 3 2 1 0
Port 11 10 7 6 5 4
Datasheet 713
xHCI Controller Registers (D20:F0)
16.1.34 U3OCM1 - XHCI USB3 Overcurrent Pin Mapping 1
(USB xHCI—D20:F0)
Address Offset: C8–CBh Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:30 Reserved
OC3 Mapping Each bit position maps OC3to a set of ports as follows: The OC3 pin
is ganged to the overcurrent signal of each port that has its corresponding bit set.
It is software responsibility to ensure that a given port‘s bit map is set only for one
29:24 OC pin.
Bit 29 28 27 26 25 24
Port 6 5 4 3 2 1
23:22 Reserved
OC2 Mapping Each bit position maps OC2 to a set of ports as follows: The OC2
pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is software responsibility to ensure that a given port‘s bit map is set only for
21:16 one OC pin.
Bit 21 20 19 18 17 16
Port 6 5 4 3 2 1
15:14 Reserved
OC1 Mapping Each bit position maps OC1 to a set of ports as follows: The OC1
pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is software responsibility to ensure that a given port‘s bit map is set only for
13:8 one OC pin.
Bit 13 12 11 10 9 8
Port 6 5 4 3 2 1
7:6 Reserved
OC0 Mapping Each bit position maps OC0 to a set of ports as follows: The OC0
pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is software responsibility to ensure that a given port‘s bit map is set only for
5:0 one OC pin.
Bit 5 4 3 2 1 0
Port 6 5 4 3 2 1
714 Datasheet
xHCI Controller Registers (D20:F0)
16.1.35 U3OCM2 - XHCI USB3 Overcurrent Pin Mapping 2
(USB xHCI—D20:F0)
Address Offset: CC–CFh Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:30 Reserved
OC7 Mapping Each bit position maps OC7 to a set of ports as follows: The OC7
pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is software responsibility to ensure that a given port‘s bit map is set only for
29:24 one OC pin.
Bit 29 28 27 26 25 24
Port 6 5 4 3 2 1
23:22 Reserved
OC6 Mapping Each bit position maps OC6 to a set of ports as follows: The OC6
pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is software responsibility to ensure that a given port‘s bit map is set only for
21:16 one OC pin.
Bit 21 20 19 18 17 16
Port 6 5 4 3 2 1
15:14 Reserved
OC5 Mapping Each bit position maps OC5 to a set of ports as follows: The OC5
pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is software responsibility to ensure that a given port‘s bit map is set only for
13:8 one OC pin.
Bit 13 12 11 10 9 8
Port 6 5 4 3 2 1
7:6 Reserved
OC4 Mapping Each bit position maps OC4 to a set of ports as follows: The OC4
pin is ganged to the overcurrent signal of each port that has its corresponding bit
set. It is software responsibility to ensure that a given port‘s bit map is set only for
5:0 one OC pin.
Bit 5 4 3 2 1 0
Port 6 5 4 3 2 1
Datasheet 715
xHCI Controller Registers (D20:F0)
16.1.36 XUSB2PR—xHC USB 2.0 Port Routing Register
(USB xHCI—D20:F0)
Address Offset: D0–D3h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Note: Bits 3:0 are located in the Suspend Well.
Bit Description
31:15 Reserved.
USB 2.0 Host Controller Selector (USB2HCSEL)—R/W. Maps a USB 2.0 port to the
xHC or EHC #1 host controller.
When set to 0, this bit routes all the corresponding USB 2.0 port pins to the EHCI
controller (D29:F0) and RMH #1. The USB 2.0 port is masked from the xHC and the
USB 2.0 port’s OC pin is routed to the EHCI controller (D29:F0).
When set to 1, this bit routes all the corresponding USB 2.0 pins to the xHC controller.
14:0 The USB 2.0 port is masked from the EHC and the USB 2.0 port’s OC pin is routed to
the xHC controller (D20:F0).
Port to bit mapping is in one-hot encoding; that is, bit 0 controls port 1 and so on.
Bit 0 = USB 2.0 Port 0
....
Bit 13 = USB 2.0 Port 13
16.1.37 XUSB2PRM—xHC USB 2.0 Port Routing Mask Register
(USB xHCI—D20:F0)
Address Offset: D4–D7h Attribute: RO, R/WLO
Default Value: 00000000h Size: 32 bits
Note: The R/WL property of this register is controlled by the ACCTRL bit (D20:F0:40h, bit
31).
Bit Description
31:15 Reserved.
USB 2.0 Host Controller Selector Mask (USB2HCSELM)—R/W. This bit field allows
the BIOS to communicate to the OS which USB 2.0 ports can be switched from the EHC
controller to the xHC controller.
When set to 1, the OS may switch the USB 2.0 port between the EHCI and xHCI host
controllers by modifying the corresponding USB2HCSEL bit (D20:F0:D0h, bit 3:0).
14:0 When set to 0, The OS shall not modify the corresponding USB2HCSEL bit.
Port to bit mapping is in one-hot encoding: that is, bit 0 controls port 1 and so on.
Bit 0 = USB 2.0 Port 0
....
Bit 13 = USB 2.0 Port 13
716 Datasheet
xHCI Controller Registers (D20:F0)
16.1.38 USB3_PSSEN—USB 3.0 Port SuperSpeed Enable Register
(USB xHCI—D20:F0)
Address Offset: D8h–dBh Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
Note: Bits 3:0 are located in the Suspend Well.
Bit Description
31:6 Reserved.
USB 3.0 Port SuperSpeed Enable (USB3PSSEN)—R/W. This field controls
whether SuperSpeed capability is enabled for a given USB 3.0 port.
When set to 1, this bit enables the SuperSpeed terminations and allows the xHC
to view the SuperSpeed connections on the USB port.
Enables PORTSC to see the connects on the ports.
When set to 0, the port’s SuperSpeed capability is not visible to the xHC.
5:0
Bit 0 = USB 3.0 Port 1
Bit 1 = USB 3.0 Port 2
Bit 2 = USB 3.0 Port 3
Bit 3 = USB 3.0 Port 4
Bit 4 = USB 3.0 Port 5
Bit 5 = USB 3.0 Port 6
16.1.39 USB3PRM—USB 3.0 Port Routing Mask Register
(USB xHCI—D20:F0)
Address Offset: DC–DFh Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
Power Well: Core
Note: The R/WL property of this register is controlled by the ACCTRL bit (D20:F0:40h, bit
31).
Bit Description
31:6 Reserved.
USB 2.0 Host Controller Selector Mask (USB2HCSELM)—R/W. This bit field allows
the BIOS to communicate to the OS which USB 3.0 ports can have the SuperSpeed
capabilities enabled.
When set to 1, the OS may enable or disable the SuperSpeed capabilities by modifying
the corresponding USB3PSSEN bit (D20:F0:D8h, bit 3:0).
When set to 0, the OS shall not modify the corresponding USB3PSSEN bit.
5:0
Bit 0 = USB 3.0 Port 1
Bit 1 = USB 3.0 Port 2
Bit 2 = USB 3.0 Port 3
Bit 3 = USB 3.0 Port 4
Bit 4 = USB 3.0 Port 5
Bit 5 = USB 3.0 Port 6
Datasheet 717
xHCI Controller Registers (D20:F0)
16.1.40 USB2PDO—xHCI USB Port Disable Override Register
(USB xHCI—D20:F0)
Address Offset: E4–E7h Attribute: R/WO
Default Value: 00000000h Size: 32 bits
Power Well: Suspend
Bit Description
31:15 Reserved.
xHCI USB Port Disable Override (XUSBPDO)—R/WO.
0 = Allows corresponding USB port to report a Device Connection to the xHC.
1 = Prevents the corresponding USB port from reporting a Device Connection to the
xHC.
14:0
Port to bit mapping is in one-hot encoding; that is, bit 0 controls port 1 and so on.
Bit 0 = USB 2.0 Port 0
....
Bit 13 = USB 2.0 Port 13
16.1.41 USB3PDO—USB3 Port Disable Override
(USB xHCI—D20:F0)
Address Offset: E8–EBh Attribute: R/WO
Default Value: 00000000h Size: 32 bits
Power Well: Suspend
Bit Description
31:15 Reserved.
xHCI USB Port Disable Override (XUSBPDO)—R/WO.
0 = Allows corresponding USB port to report a Device Connection to the xHC.
1 = Prevents the corresponding USB port from reporting a Device Connection to the
xHC.
Bit 0 = USB 3.0 Port 1
14:0 Bit 1 = USB 3.0 Port 2
Bit 2 = USB 3.0 Port 3
Bit 3 = USB 3.0 Port 4
Bit 4 = USB 3.0 Port 5
Bit 5 = USB 3.0 Port 6
718 Datasheet
xHCI Controller Registers (D20:F0)
16.2 Memory-Mapped I/O Registers
The xHCI memory-mapped I/O space is composed of two sets of registers: Capability
Registers and Operational Registers.
Note: The PCH xHC controller will not accept locked memory transactions (neither reads nor
writes) as a target. The locked transactions should not be forwarded to PCI as the
address space is known to be allocated to USB. Attempting to access the xHCI
controller Memory-Mapped I/O space using locked memory transactions will result in
undefined behavior.
Note: When the xHCI function is in the D3 PCIe power state, accesses to the xHCI memory
range are ignored and result in a master abort. Similarly, if the Memory Space Enable
(MSE) bit (D20:F0:04h, bit 1) is not set in the Command register in configuration
space, the memory range will not be decoded by the PCH xHC. If the MSE bit is not set,
the PCH must default to allowing any memory accesses for the range specified in the
BAR to go to PCI. This is because the range may not be valid and, therefore, the cycle
must be made available to any other targets that may be currently using that range.
16.2.1 Host Controller Capability Registers
These registers specify the limits, restrictions and capabilities of the host controller
implementation.
Table 16-2. Enhanced Host Controller Capability Registers
MEM_BASE Power
Mnemonic Register Default Type
+ Offset Well
00h Core CAPLENGTH Capabilities Registers Length 80h RW/L
Host Controller Interface Version
02h–03h Core HCIVERSION 0100h RO
Number
Host Controller Structural
04h–07h Core HCSPARAMS1 15000820h RW/L
Parameters #1
Host Controller Structural
08h–0Bh Core HCSPARAMS2 84000054h RW/L
Parameters #2
Host Controller Structural
0Ch–0Fh Core HCSPARAMS3 00040001h RW/L
Parameters #3
Host Controller Capability
10h–13h Core HCCPARAMS 200071E9h RW/L
Parameters
14h–17h Core dBOFF Doorbell Offset 0000C000h RO
18h–1Bh Core RTSOFF Runtime Register Space Offset 00001000h RO
Datasheet 719
xHCI Controller Registers (D20:F0)
16.2.1.1 CAPLENGTH—Capability Registers Length Register
Offset: MEM_BASE + 00h Attribute: RW/L
Default Value: 80h Size: 8 bits
Bit Description
Capability Register Length Value—RW. This register is used as an offset to add to
7:0 the Memory Base Register (D20:F0:10h) to find the beginning of the Operational
Register Space. This register is modified and maintained by BIOS.
16.2.1.2 HCIVERSION—Host Controller Interface Version Number
Register
Offset: MEM_BASE + 02h–03h Attribute: RO
Default Value: 0100h Size: 16 bits
Bit Description
Host Controller Interface Version Number—RO. This is a two-byte register
15:0 containing a BCD encoding of the version number of interface that this host controller
interface conforms to.
16.2.1.3 HCSPARAMS1—Host Controller Structural Parameters #1 Register
Offset: MEM_BASE + 04h–07h Attribute: RW/L
Default Value: 15000820h Size: 32 bits
Bit Description
Number of Ports (MaxPorts)—RW/L. This field specifies the number of physical
downstream ports implemented on this host controller. The value of this field determines
31:24
how many port registers are addressable in the Operational Register Space. Default
value = 15h
23:19 Reserved
Number of Interrupters (MaxIntrs)—RW/L. This field specifies the number of
18:8 interrupters implemented on this host controller. Each interrupter is allocated to a vector
of MSI and controls its generation and moderation.
Number of Device Slots (MaxSlots)—RW/L. This field specifies the number of Device
7:0 Context Structures and Doorbell Array entries this host controller can support. Valid
values are in the range of 1 to 255.
720 Datasheet
xHCI Controller Registers (D20:F0)
16.2.1.4 HCSPARAMS2—Host Controller Structural Parameters #2 Register
Offset: MEM_BASE + 08h–0Bh Attribute: RW/L
Default Value: 84000054h Size: 32 bits
Bit Description
Max Scratchpad Buffers (MaxScratchpadBufs)—RW/L. Indicates the number of
31:27
Scratchpad Buffers system software shall reserve for the xHC.
Scratchpad Restore (SPR)—RW/L.
0 = Indicates the Scratchpad buffer space may be freed and reallocated between power
26 events.
1 = Indicates that the xHC requires the integrity of the Scratchpad buffer space to be
maintained across power events.
25:8 Reserved.
Event Ring Segment Table Max (ERSTMax)—RW/L. This field determines the
7:4
maximum value supported by the Event Ring Segment Table Base Size registers.
Isochronous Scheduling Threshold (IST)—RW/L. This field indicates to system
software the minimum distance (in time) that it is required to stay ahead of the xHC
while adding TRBs, in order to have the xHC process them at the correct time. The
value is specified in the number if frames/microframes.
3:0
If bit [3] of IST is cleared to 0b, software can add a TRB no later than IST [2:0]
microframes before that TRB is scheduled to be executed.
If bit [3] of IST is set to 1b, software can add a TRB no later than IST[2:0] frames
before that TRB is scheduled to be executed.
Datasheet 721
xHCI Controller Registers (D20:F0)
16.2.1.5 HCSPARAMS3—Host Controller Structural Parameters #3 Register
Offset: MEM_BASE + 0Ch–0Fh Attribute: RW/L
Default Value: 00040001h Size: 32 bits
Bit Description
U2 Device Exit Latency (U2DEL)—RW/L. Indicates the worst case latency to
transition from U2 to U0. Applies to all root hub ports.
The following are permissible values:
Value Description
31:16 00h Zero
01h Less than 1 s
02h Less than 2 s
...
0Bh-FFh Reserved
15:8 Reserved.
U1 Device Exit Latency (U1DEL)—RW/L. Worst case latency to transition a root hub
Port Link State (PLS) from U1 to U0. Applies to all root hub ports.
The following are permissible values:
Value Description
00h Zero
7:0
01h Less than 1 s
02h Less than 2 s
...
0800h-
Reserved
FFFFh
722 Datasheet
xHCI Controller Registers (D20:F0)
16.2.1.6 HCCPARAMS—Host Controller Capability Parameters Register
Offset: MEM_BASE + 10h–13h Attribute: RW/L
Default Value: 200071E9h Size: 32 bits
Bit Description
xHCI Extended Capabilities Pointer (xECP)—RW/L This field indicates the existence
31:16 of a capabilities list. The value of this field indicates a relative offset, in 32-bit words,
from Base to the beginning of the first extended capability.
Maximum Primary Stream Array Size (MaxPSASize)—RW/L. This fields identifies
15:12 the maximum size Primary Stream Array that the xHC supports. The Primary Stream
Array size = 2MaxPSASize+1. Valid MaxPSASize values are 1 to 15.
11 Reserved.
Stopped EDLTA Capability (SEC)—RW/L. This flag indicates that the host controller
10
implementation Stream Context support a Stopped EDLTA field.
Stopped Short Packet Capability (SPC)—RW/L. This flag indicates that the host
9 controller implementation is capable of generating a Stopped - Short Packet Completion
Code.
8 Reserved.
No Secondary SID Support (NSS)—RW/L. Hardwired to ‘0’ indicating Secondary
7
Stream ID decoding is supported.
Latency Tolerance Messaging Capability (LTC)—RW/L.
6 0 = Latency Tolerance Messaging is not supported.
1 = Latency Tolerance Messaging is supported
Light HC Reset Capability (LHRC)—RW/L.
5 0 = Light Host Controller Reset is not supported.
1 = Light Host Controller Reset is supported
Port Indicators (PIND)—RW/L. This bit indicates whether the xHC root hub ports
4 support port indicator control. When this bit is a ‘1’, the port status and control
registers include a read/writeable field for controlling the state of the port indicator.
Port Power Control (PPC)—RO. This bit indicates whether the host controller
3 implementation includes port power control. A ‘1’ in this bit indicates the ports have
port power switches. A ‘0’ in this bit indicates the port do not have port power switches.
Context Size (CSZ)—RW/L. If this bit is set to ‘1’, then the xHC uses 64 byte Context
data structures. If this bit is cleared to ‘0’, then the xHC uses 32 byte Context data
2 structures.
NOTE: This flag does not apply to Stream Contexts.
BW Negotiation Capability (BNC)—RW/L.
1 0 = Not capable of BW Negotiation.
1 = Capable of BW Negotiation.
64-bit Addressing Capability (AC64)—RW/L. This bit documents the addressing
range capability of the xHC. The value of this flag determines whether the xHC has
implemented the high order 32 bits of 64 bit register and data structure pointer fields.
Values for this flag have the following interpretation:
0 0 = Supports 32-bit address memory pointers
1 = Supports 64-bit address memory pointers
If 32-bit address memory pointers are implemented, the xHC shall ignore the high
order 32 bits of 64 bit data structure pointer fields, and system software shall ignore
the high order 32 bits of 64 bit xHC registers.
Datasheet 723
xHCI Controller Registers (D20:F0)
16.2.1.7 dBOFF—Doorbell Offset Register
Offset: MEM_BASE + 14h–17h Attribute: RO
Default Value: 0000C000h Size: 32 bits
Bit Description
Doorbell Array Offset—RO. This field defines the DWord offset of the Doorbell Array
31:2 base address from the Base (that is, the base address of the xHCI Capability register
address space).
1:0 Reserved.
16.2.1.8 RTSOFF—Runtime Register Space Offset Register
Offset: MEM_BASE + 18h–1Bh Attribute: RO
Default Value: 00001000h Size: 32 bits
Bit Description
Runtime Register Space Offset—RO. This field defines the 32-byte offset of the xHCI
31:2 Runtime Registers from the Base. That is, Runtime Register Base Address = Base +
Runtime Register Set Offset.
1:0 Reserved.
724 Datasheet
xHCI Controller Registers (D20:F0)
16.2.2 Host Controller Operational Registers
This section defines the xHC operational registers. These registers are located after the
capabilities registers. The operational register base must be DWord-aligned and is
calculated by adding the value in the first capabilities register (CAPLENGTH) to the base
address of the xHC register address space (MEM_BASE). Since CAPLENGTH is always
80h, Table 16-3 already accounts for this offset. All registers are 32 bits in length.
Table 16-3. Enhanced Host Controller Operational Register Address Map
MEM_BASE Power
Mnemonic Register Name Default Type
+ Offset Well
80h–83h Core USB_CMD USB Command 00000000h R/W, RO
84h–87h Core USB_STS USB Status 00000001h R/WC, RO
88h–8Bh Core PAGESIZE Page Size 00000001h RO
94h–97h Core DNCTRL Device Notification Control 00000000h R/W, RO
98h–9Bh Core CRCRL Command Ring Control Low 00000000h R/W, RO
9Ch–9Fh Core CRCRH Command Ring Control High 00000000h R/W, RO
Device Context Base Address
B0h–B3h Core DCBAAPL 00000000h R/W, RO
Array Pointer Low
Device Context Base Address
B4h–B7h Core DCBAAPH 00000000h R/W, RO
Array Pointer High
B8h–BBh Core CONFIG Configure 00000000h R/W, RO
480h, 490h,
4A0h, 4B0h,
4C0h, 4D0h,
R/W, R/WC,
4E0h, 4F0h,
Multiple PORTSCNUSB2 Port N Status and Control USB2 000002A0h RO, R/WO,
500h, 510h,
R/WOC
520h, 530h,
540h, 550h,
560h
484h, 494h,
4A4h, 4B4h,
4C4h, 4D4h,
4E4h, 4F4h, Port N Power Management
Multiple PORTPMSCNUSB2 00000000h R/W, RO
504h, 514h, Status and Control USB2
524h, 534h,
544h, 554h,
564h
570h, 580h,
590h, 5A0h, Multiple PORTSCNUSB3 Port N Status and Control USB3 000002A0h R/W, RO
5B0h, 5C0h
574h, 584h,
Port N Power Management
594h, 5A4h, Suspend PORTPMSCN 00000000h R/W, RO
Status and Control USB3
5B4h, 5C4h
578h, 588h,
598h, 5A8h, Core PORTLIX USB 3.0 Port Link Info 00000000h RO
5B8h, 5C8h
NOTE: Software must read and write these registers using only DWord accesses.
Datasheet 725
xHCI Controller Registers (D20:F0)
16.2.2.1 USB_CMD—USB Command Register
Offset: MEM_BASE + 80h–83h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:12 Reserved.
Enable U3 MFINDEX Stop (EU3S)—R/W.
When set to 1b, the xHC may stop the MFINDEX counting action if all Root Hub ports
11 are in the U3, Disconnected, Disabled, or Powered-off state.
When cleared to 0b, the xHC may stop the MFINDEX counting action if all Root Hub
ports are in the Disconnected, Disabled, or Powered-off state.
Enable Wrap Event (EWE)—R/W.
When set to 1b, the xHC shall generate a MFINDEX Wrap Event every time the
10
MFINDEX register transitions from 03FFFh to 0.
When cleared to 0b, no MFINDEX Wrap Events are generated.
Controller Restore State (CRS)—R/W. When set to 1b, MEM_BASE+80h:bit 0= 0b,
and MEM_BASE+80h:bit 8 = 1b, the xHC shall perform a Restore State operation and
restore its internal state.
9
When set to 1b and MEM_BASE+80h:bit 0= 1b or MEM_BASE+80h:bit 8 = 0b, or when
cleared to ‘0’, no Restore State operation shall be performed.
NOTE: This flag always returns ‘0’ when read.
Controller Save State (CSS)—R/W. When written by software with 1b and
MEM_BASE+80h:bit 0= 0b, the xHC shall save any internal state that will be restored
by a subsequent Restore State operation.
8 When written by software with 1b and MEM_BASE+80h:bit 0= 1b, or written with ‘0’,
no Save State operation shall be performed.
NOTE: This flag always returns ‘0’ when read.
Light Host Controller Reset (LHCRST)—R/W. If the Light HC Reset Capability
(LHRC) bit (MEM_BASE=10h:bit 5) is 1b, then setting this bit to 1b allows the driver to
reset the xHC without affecting the state of the ports.
A system software read of this bit as 0b indicates the Light Host Controller Reset has
7 completed and it is safe for software to re-initialize the xHC. A software read of this bit
as a 1b indicates the Light Host Controller Reset has not yet completed.
NOTE: If Light HC Reset Capability is not implemented, a read of this flag will always
return a 0b.
6:4 Reserved.
Host System Error Enable (HSEE)—R/W. When this bit is set to 1b, and the HSE bit
3 (MEM_BASE+84h:bit 2) is set to 1b, the xHC shall assert out-of-band error signaling to
the host. The signaling is acknowledged by software clearing the HSE bit.
Interrupter Enable (INTE)—R/W. This bit provides system software with a means of
enabling or disabling the host system interrupts generated by interrupters.
When this bit is set to 1b, then Interrupter host system interrupt generation is allowed,
2
such that the xHC shall issue an interrupt at the next interrupt threshold if the host
system interrupt mechanism (such that MSI, MSIX, and so on) is enabled. The interrupt
is acknowledged by a host system interrupt specific mechanism.
726 Datasheet
xHCI Controller Registers (D20:F0)
Bit Description
Host Controller Reset (HCRST)—R/W. This control bit is used by software to reset
the host controller.
When software sets this bit to 1b, the Host Controller resets its internal pipelines,
timers, counters, state machines, and so on to their initial value. Any transaction
currently in progress on USB is immediately terminated. A USB reset is not driven on
downstream ports.
PCI Configuration registers are not affected by this reset. All operational registers,
including port registers and port state machines are set to their initial values.
1
NOTES:
1. This bit is cleared to 0b by the Host Controller when the reset process is
complete. Software cannot terminate the reset process early by writing a 0b to
this bit and shall not write any xHC Operational or Runtime registers while
HCRST is set to 1b.
2. Software shall not set this bit to 1b when the HCHalted (HCH) bit
(MEM_BASE+84h:bit 0) is set to 0b. Attempting to reset an actively running
host controller will result in undefined behavior.
Run/Stop (R/S)—R/W.
When set to 1b, the xHC proceeds with execution of the schedule. The xHC continues
execution as long as this bit is set to 1b.
When this bit is cleared to 0b, the xHC completes the current and any actively pipelined
0 transactions on the USB and then halts. The xHC shall halt within 16 microframes after
software clears the Run/Stop bit. The HCHalted (HCH) bit (MEM_BASE+84h:bit 0)
indicates when the xHC has finished its pending pipelined transactions and has entered
the stopped state. Software shall not write a ‘1’ to this flag unless the xHC is in the
Halted state (that is, HCH in the USBSTS register is ‘1’); doing so will yield undefined
results.
Datasheet 727
xHCI Controller Registers (D20:F0)
16.2.2.2 USB_STS—USB Status Register
Offset: MEM_BASE + 84h–87h Attribute: R/WC, RO
Default Value: 00000001h Size: 32 bits
This register indicates pending interrupts and various states of the Host controller. The
status resulting from a transaction on the serial bus is not indicated in this register. See
the Interrupts description in Section 4 of the xHCI specification for additional
information concerning interrupt conditions.
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 has
no effect.
Bit Description
31:13 Reserved.
Host Controller Error (HCE) RO. This flag shall be set to indicate that an internal
error condition has been detected which requires software to reset and re-initialize the
12 xHC.
0 = No internal xHC error conditions exist.
1 = Internal xHC error condition exists.
Controller Not Ready (CNR) RO.
0 = Ready
1 = Not Ready
11 Software shall not write any Doorbell or Operational register of the xHC, other than the
USBSTS register, until CNR = 0b. This flag is set by the xHC after a Hardware Reset and
cleared when the xHC is ready to begin accepting register writes. This flag shall remain
cleared (0b) until the next Chip Hardware Reset.
Save/Restore Error (SRE) R/WC. If an error occurs during a Save or Restore
10 operation this bit shall be set to 1b. This bit shall be cleared to 0b when a Save or
Restore operation is initiated or when written with 1b.
Restore State Status (RSS) RO. When the Controller Restore State (CRS) flag in
the USB_CMD register is written with 1b this bit shall be set to 1b and remain set while
9 the xHC restores its internal state.
NOTE: When the Restore State operation is complete, this bit shall be cleared to 0b.
Save State Status (SSS) RO. When the Controller Save State (CSS) flag in the
USB_CMD register is written with 1b this bit shall be set to 1b and remain set while the
8 xHC saves its internal state.
NOTE: When the Save State operation is complete, this bit shall be cleared to 0b.
7:5 Reserved.
Port Change Detect (PCD)—R/WC. This bit is allowed to be maintained in the
Auxiliary power well. Alternatively, it is also acceptable that on a D3 to D0 transition of
the xHC, this bit is loaded with the OR of all of the PORTSC change bits (including: Force
port resume, overcurrent change, enable/disable change and connect status change).
Regardless of the implementation, when this bit is readable (that is, in the D0 state), it
4 must provide a valid view of the Port Status registers.
0 = No change bit transition from a 0 to 1 or No Force Port Resume bit transition from 0
to 1 as a result of a J-K transition detected on a suspended port.
1 = The Host controller sets this bit to 1 when any port for which the Port Owner bit is
set to 0 has a change bit transition from a 0 to 1 or a Force Port Resume bit
transition from 0 to 1 as a result of a J-K transition detected on a suspended port.
728 Datasheet
xHCI Controller Registers (D20:F0)
Bit Description
Event Interrupt (EINT)—R/WC. The xHC sets this bit to 1b when the Interrupt
Pending (IP) bit of any Interrupter is transitions from 0b to 1b.
Software that uses EINT shall clear it prior to clearing any IP flags. A race condition will
3
occur if software clears the IP flags then clears the EINT flag, and between the
operations another IP ‘0’ to '1' transition occurs. In this case the new IP transition will be
lost.
Host System Error (HSE)—R/WC. The xHC sets this bit to 1b when a serious error is
detected, either internal to the xHC or during a host system access involving the xHC
module. Conditions that set this bit to ‘1’ include PCI Parity error, PCI Master Abort, and
2 PCI Target Abort. When this error occurs, the xHC clears the Run/Stop (R/S) bit in the
USB_CMD register to prevent further execution of the scheduled TDs. If the HSEE bit in
the USB_CMD register is 1b, the xHC shall also assert out-of-band error signaling to the
host.
1 Reserved.
HCHalted (HCH)—RO. This bit is a ‘0’ whenever the Run/Stop (R/S) bit is set to 1b.
The xHC sets this bit to 1b after it has stopped executing as a result of the Run/Stop (R/
S) bit being cleared to 0b, either by software or by the xHC hardware (such as internal
0
error).
If this bit is set to1b, then SOFs, microSOFs, or Isochronous Timestamp Packets (ITP)
shall not be generated by the xHC.
16.2.2.3 PAGESIZE—Page Size Register
Offset: MEM_BASE + 88h–8Bh Attribute: RO
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
15:0 Page Size—RO. Hardwired to 1h to indicate support for 4k byte page sizes.
16.2.2.4 DNCTRL—Device Notification Control Register
Offset: MEM_BASE + 94h–97h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:16 Reserved.
Notification Enable—R/W. When a Notification Enable bit is set, a Device Notification
Event will be generated when a Device Notification Transaction Packet is received with
the matching value in the Notification Type field. For example, setting N1 to ‘1’ enables
15:0 Device Notification Event generation if a Device Notification TP is received with its
Notification Type field set to ‘1’ (FUNCTION_WAKE), and so on.
Refer to the USB 3.0 Specification for more information on Notification Types.
Datasheet 729
xHCI Controller Registers (D20:F0)
16.2.2.5 CRCRL—Command Ring Control Low Register
Offset: MEM_BASE + 98h–9Bh Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
Command Ring Pointer—R/W. This field defines low order bits of the initial value of
the 64-bit Command Ring Dequeue Pointer.
NOTES:
1. Writes to this field are ignored when Command Ring Running bit (CRR) = 1b.
2. If the CRCR register is written while the Command Ring is stopped (CRR = 0b),
31:6 the value of this field shall be used to fetch the first Command TRB the next
time the Host Controller Doorbell register is written with the dB Reason field set
to Host Controller Command.
3. If the CRCR register is not written while the Command Ring is stopped (CRR =
0b), then the Command Ring shall begin fetching Command TRBs at the current
value of the internal xHC Command Ring Dequeue Pointer.
4. Reading this field always returns 0b.
5:4 Reserved.
Command Ring Running (CRR)—RO. This bit is set to 1b if the Run/Stop (R/S) bit is
1b and the Host Controller Doorbell register is written with the dB Reason field set to
3 Host Controller Command. It is cleared to 0b when the Command Ring is stopped after
writing a 1b to the Command Stop (CS) or Command Abort (CA) bits, or if the R/S bit is
cleared to 0b.
Command Abort (CA)—R/W. Writing a 1b to this bit shall immediately terminate the
currently executing command, stop the Command Ring, and generate a Command
Completion Event with the Completion Code set to Command Ring Stopped.
The next write to the Host Controller Doorbell with dB Reason field set to Host
2 Controller Command shall restart the Command Ring operation.
NOTES:
1. Writes to this flag are ignored by the xHC if Command Ring Running (CRR) =
0b.
2. Reading this bit always returns 0b.
Command Stop (CS)—R/W. Writing a 1b to this bit shall stop the operation of the
Command Ring after the completion of the currently executing command, and generate
a Command Completion Event with the Completion Code set to Command Ring Stopped
and the Command TRB Pointer set to the current value of the Command Ring Dequeue
Pointer.
1 The next write to the Host Controller Doorbell with dB Reason field set to Host
Controller Command shall restart the Command Ring operation.
NOTES:
1. Writes to this flag are ignored by the xHC if Command Ring Running (CRR) bit =
0b.
2. Reading this bit always returns 0b.
730 Datasheet
xHCI Controller Registers (D20:F0)
Bit Description
Ring Cycle State (RCS)—R/W. This bit identifies the value of the xHC Consumer Cycle
State (CCS) flag for the TRB referenced by the Command Ring Pointer.
NOTES:
1. Writes to this bit are ignored when the Command Ring Running (CRR) bit = 1b.
2. If the CRCR register is written while the Command Ring is stopped (CCR = 0b),
0 then the value of this flag shall be used to fetch the first Command TRB the next
time the Host Controller Doorbell register is written with the dB Reason field set
to Host Controller Command.
3. If the CRCR register is not written while the Command Ring is stopped (CCR =
0b), then the Command Ring will begin fetching Command TRBs using the
current value of the internal Command Ring CCS flag.
4. Reading this flag always returns 0b.
NOTES:
1. Setting the Command Stop (CS) or Command Abort (CA) flags while CRR = 1b shall
generate a Command Ring Stopped Command Completion Event.
2. Setting both the Command Stop (CS) and Command Abort (CA) flags with a single write to
the CRCR register while CRR = ‘1’ shall be interpreted as a Command Abort (CA) by the
xHC.
3. The values of the internal xHC Command Ring CCS flag and Dequeue Pointer are undefined
after hardware reset, so these fields shall be initialized before setting USB_CMD Run/Stop
(R/S) bit (MEM_BASE+80:bit 0) to 1b.
16.2.2.6 CRCRH—Command Ring Control High Register
Offset: MEM_BASE + 9Ch–9Fh Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
Command Ring Pointer—R/W. This field defines high order bits of the initial value of
the 64-bit Command Ring Dequeue Pointer.
NOTES:
1. Writes to this field are ignored when Command Ring Running bit (CRR) = 1b.
2. If the CRCR register is written while the Command Ring is stopped (CRR = 0b),
31:0 the value of this field shall be used to fetch the first Command TRB the next
time the Host Controller Doorbell register is written with the dB Reason field set
to Host Controller Command.
3. If the CRCR register is not written while the Command Ring is stopped (CRR =
0b), then the Command Ring shall begin fetching Command TRBs at the current
value of the internal xHC Command Ring Dequeue Pointer.
4. Reading this field always returns 0b.
16.2.2.7 DCBAAPL—Device Context Base Address Array Pointer Low
Register
Offset: MEM_BASE + B0h–B3h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
Device Context Base Address Array Pointer—R/W. This field defines low order bits
31:6 of the 64-bit base address of the Device Context Pointer Array table (a table of address
pointers that reference Device Context structures for the devices attached to the host.)
5:0 Reserved.
Datasheet 731
xHCI Controller Registers (D20:F0)
16.2.2.8 DCBAAPH—Device Context Base Address Array Pointer High
Register
Offset: MEM_BASE + B4h–B7h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
Device Context Base Address Array Pointer—R/W. This field defines high order bits
31:0 of the 64-bit base address of the Device Context Pointer Array table (a table of address
pointers that reference Device Context structures for the devices attached to the host.)
16.2.2.9 CONFIG—Configure Register
Offset: MEM_BASE + B8h–BBh Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:8 Reserved.
Max Device Slots Enabled (MaxSlotsEn)—R/W. This field specifies the maximum
number of enabled Device Slots. Valid values are in the range of 0h to 20h. Enabled
Devices Slots are allocated contiguously (such that a value of 16 specifies that Device
Slots 1 to 16 are active.)
7:0
A value of ‘0’ disables all Device Slots. A disabled Device Slot shall not respond to
Doorbell Register references.
NOTE: This field shall not be modified if the xHC is running (Run/Stop (R/S) = ‘1’).
732 Datasheet
xHCI Controller Registers (D20:F0)
16.2.2.10 PORTSCNUSB2—Port N Status and Control USB2 Register
Offset: There are 15 USB2 PORTSC registers at offsets: 480h, 490h, 4A0h,
4B0h, 4C0h, 4D0h, 4E0h, 4F0h, 500h, 510h, 520h, 530h, 540h, 550h,
560h
Attribute: R/W, R/WC, RO, R/WO, R/WOC
Default Value: 000002A0h Size: 32 bits
A host controller must implement one or more port registers. Software uses the N_Port
information from the Structural Parameters Register to determine how many ports
need to be serviced. All ports have the structure defined below. Software must not
write to unreported Port Status and Control Registers.
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset. The initial
conditions of a port are:
• No device connected
• Port disabled.
When a device is attached, the port state transitions to the attached state and system
software will process this as with any status change notification. Refer to Section 4 of
the xHCI Specification for operational requirements for how change events interact with
port suspend mode.
Bit Description
Warm Port Reset (WPR)—R/WO. When software sets this bit to 1b, the Warm Reset
sequence is initiated and the PR bit is set to 1b. Once initiated, the PR, PRC, and WRC
bits shall reflect the progress of the Warm Reset sequence. This flag shall always return
0b when read.
31
NOTE: This bit applies only to USB 3.0 capable ports. For ports that are only USB 2.0
capable, this bit is Reserved.
NOTE: This bit is in the Suspend Well.
Device Removable (DR)—RO. This bit indicates if this port has a removable device
attached.
30 0 = Device is removable.
1 = Device is non-removable.
NOTE: This bit is in the Core Well.
29:28 Reserved.
Wake on Over-current Enable (WOE)—R/W.
0 = Disable. (Default)
27 1 = Enable. Writing this bit to a 1b enables the port to be sensitive to over-current
conditions as system wake-up events.
NOTE: This bit is in the Suspend Well.
Wake on Disconnect Enable (WDE)—R/W.
0 = Disable. (Default)
26 1 = Enable. Writing this bit to a 1b enables the port to be sensitive to device
disconnects as system wake-up events.
NOTE: This bit is in the Suspend Well.
Wake on Connect Enable (WCE)—R/W.
0 = Disable. (Default)
25 1 = Enable. Writing this bit to a 1b enables the port to be sensitive to device connects
as system wake-up events.
NOTE: This bit is in the Suspend Well.
Datasheet 733
xHCI Controller Registers (D20:F0)
Bit Description
Cold Attach Status (CAS)—RO. This bit indicates that far-end terminations were
detected in the Disconnected state and the Root Hub Port State Machine was unable to
advance to the Enabled state.
24 Software shall clear this bit by writing a 1b to the WPR bit or the xHC shall clear this bit
if the CSS bit transitions to 1.
NOTE: This bit is 0b if the PP bit is 0b or for USB 2.0 capable-only ports.
NOTE: This bit is in the Suspend Well.
Port Config Error Change (CEC)—R/WOC. This flag indicates that the port failed to
configure its link partner.
Software shall clear this bit by writing a 1 to it.
23
NOTE: This bit applies only to USB 3.0 capable ports. This bit is Reserved for USB 2.0
capable-only ports.
NOTE: This bit is in the Suspend Well.
Port Link State Change (PLC)—R/WC.
0 = No change
1 = Link Status Change
This flag is set to ‘1’ due to the following Port Link State (PLS) transitions:
Transition Condition
U3 -> Resume Wakeup signaling from a device
Device Resume complete (USB 3.0 capable
Resume -> Recovery -> U0
ports only)
Device Resume complete (USB 2.0 capable-
Resume -> U0
only ports)
Software Resume complete (USB 3.0
U3 -> Recovery -> U0
capable ports only)
22 Software Resume complete (USB 2.0
U3 -> U0
capable-only ports)
L1 Resume complete (USB 2.0 capable-only
U2 -> U0
ports)
L1 Entry Reject (USB 2.0 capable-only
U0 -> U0
ports)
U0 -> Disabled L1 Entry Error (USB 2.0 capable-only ports)
Any state -> Inactive Error (USB 3.0 capable ports only)
NOTES:
1. This bit shall not be set if the PLS transition was due to software setting the PP
bit to 0b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit is in the Suspend Well.
Port Reset Change (PRC)—R/WC. This flag is set to ‘1’ due a '1' to '0' transition of
Port Reset (PR); such as when any reset processing on this port is complete.
0 = No change
1 = Reset Complete
21 NOTES:
1. This bit shall not be set to 1b if the reset processing was forced to terminate due
to software clearing the PP bit or PED bit to 0b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit is in the Suspend Well.
734 Datasheet
xHCI Controller Registers (D20:F0)
Bit Description
Over-current Change (OCC)—R/WC. The functionality of this bit is not dependent
upon the port owner. Software clears this bit by writing a 1 to it.
20 0 = No change. (Default)
1 = There is a change to Overcurrent Active.
NOTE: This bit is in the Suspend Well.
Warm Port Reset Change (WRC)—R/WC. This bit is set when Warm Reset
processing on this port completes.
0 = No change. (Default)
1 = Warm reset complete
NOTES:
19 1. This bit shall not be set to 1b if the reset processing was forced to terminate due
to software clearing the PP bit or PED bit to 0b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit applies only to USB 3.0 capable ports. This bit is Reserved for USB 2.0
capable-only ports.
4. This bit is in the Suspend Well.
Port Enabled/Disabled Change (PEC)—R/WC.
0 = No change. (Default)
1 = There is a change to PED bit.
NOTES:
1. This bit shall not be set if the PED transition was due to software setting the PP
bit to 0.
2. Software shall clear this bit by writing a 1 to it.
18
3. For a USB 2.0-only port, this bit shall be set to 1 only when the port is disabled
due to the appropriate conditions existing at the EOF2 point. (See Chapter 11 of
the USB Specification for the definition of a port error).
4. For a USB 3.0 port, this bit shall be set to ‘1’ if an enabled port transitions to a
Disabled state (that is, a ‘1’ to ‘0’ transition of PED). Refer to Section 4 of the
xHCI Specification for more information.
5. This bit is in the Suspend Well.
Connect Status Change (CSC)—R/WC. This flag indicates a change has occurred in
the port’s Current Connect Status (CCS) or Cold Attach Status (CAS) bits.
0 = No change. (Default)
1 = There is a change to the CCS or CAS bit.
The xHC sets this bit to 1b for all changes to the port device connect status, even if
system software has not cleared an existing Connect Status Change. For example, the
17 insertion status changes twice before system software has cleared the changed
condition, root hub hardware will be “setting” an already-set bit (that is, the bit will
remain 1b).
NOTES:
1. This bit shall not be set if the CCS transition was due to software setting the PP
bit to 0b, or the CAS bit transition was die to software setting the WPR bit to 1b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit is in the Suspend Well.
Port Link State Write Strobe (LWS)—R/W.
0 = When 0b, write data in PLS field is ignored. (Default)
1 = When this bit is set to 1b on a write reference to this register, this flag enables
16 writes to the PLS field.
Reads to this bit return ‘0’.
NOTE: This bit is in the Suspend Well.
15:14 Reserved.
Datasheet 735
xHCI Controller Registers (D20:F0)
Bit Description
Port Speed (Port_Speed).
A device attached to this port operates at a speed defined by the following codes:
Value Speed
0001b Full-speed (12 Mb/s)
13:10 0010b Low-speed (1.5 Mb/s)
0011b High-speed (480 Mb/s)
All other values reserved. Please refer to the eXtensible Host Controller Interface for
Universal Serial Bus Specification for additional details.
NOTE: This bit is in the Suspend Well.
Port Power (PP)—RO. Read-only with a value of 1. This indicates that the port does
9 have power.
NOTE: This bit is in the Suspend Well.
736 Datasheet
xHCI Controller Registers (D20:F0)
Bit Description
Port Link State (PLS)—R/W. This field is used to power manage the port and reflects
its current link state.
When the port is in the Enabled state, system software may set the link U-state by
writing this field. System software may also write this field to force a Disabled to
Disconnected state transition of the port.
Write Value Description
0 The link shall transition to a U0 state from any of the U-states.
2 USB 2.0 ports only. The link should transition to the U2 State.
The link shall transition to a U3 state from any of the U-states.
This action selectively suspends the device connected to this port.
3 While the Port Link State = U3, the hub does not propagate
downstream-directed traffic to this port, but the hub will respond
to resume signaling from the port.
USB 3.0 ports only. If the port is in the Disabled state (PLS =
Disabled, PP = 1), then the link shall transition to a RxDetect
5
state and the port shall transition to the Disconnected state, else
ignored.
USB 2.0 ports only. If the port is in the U3 state (PLS = U3), then
15 the link shall remain in the U3 state and the port shall transition
to the U3Exit substate, else ignored.
All other values Ignored
8:5 NOTE: The Port Link State Write Strobe (LWS) shall be set to 1b to write this field.
Read Value Definition
0 Link is in the U0 State
1 Link is in the U1 State
2 Link is in the U2 State
3 Link is in the U3 State (Device Suspended)
4 Link is in the Disabled State
5 Link is in the RxDetect State
6 Link is in the Inactive State
7 Link is in the Polling State
8 Link is in the Recovery State
9 Link is in the Hot Reset State
10 Link is in the Compliance Mode State
11 Link is in the Test Mode State
12-14 Reserved
15 Link is in the Resume State
NOTES:
1. This field is undefined if PP = 0.
2. Transitions between different states are not reflected until the transition is
complete.
3. This bit is in the Suspend Well.
Datasheet 737
xHCI Controller Registers (D20:F0)
Bit Description
Port Reset (PR)—R/W. When software writes a 1 to this bit (from a 0), the bus reset
sequence as defined in the USB Specification, Revision 2.0 is started. Software writes a
0 to this bit to terminate the bus reset sequence. Software must keep this bit at a 1
long enough to ensure the reset sequence completes as specified in the USB
Specification, Revision 2.0. USB 3.0 ports shall execute the Hot Reset sequence as
4 defined in the USB 3.0 Specification. PR remains set until reset signaling is completed
by the root hub.
1 = Port is in Reset.
0 = Port is not in Reset.
NOTE: This bit is in the Suspend Well.
Overcurrent Active (OCA)—RO.
0 = This port does not have an overcurrent condition. (Default)
1 = This port currently has an overcurrent condition. This bit will automatically
3
transition from 1 to 0 when the over current condition is removed. The PCH
automatically disables the port when the overcurrent active bit is 1.
NOTE: This bit is in the Suspend Well.
2 Reserved.
Port Enabled/Disabled—R/W. Ports can only be enabled by the host controller as a
part of the reset and enable. Software cannot enable a port by writing a 1 to this bit.
Ports can be disabled by either a fault condition (disconnect event or other fault
condition) or by host software. The bit status does not change until the port state
1 actually changes. There may be a delay in disabling or enabling a port due to other host
controller and bus events.
0 = Disable
1 = Enable (Default)
NOTE: This bit is in the Suspend Well.
Current Connect Status—RO. This value reflects the current state of the port, and
may not correspond directly to the event that caused the Connect Status Change bit
(Bit 1) to be set.
0
0 = No device is present. (Default)
1 = Device is present on port.
NOTE: This bit is in the Suspend Well.
738 Datasheet
xHCI Controller Registers (D20:F0)
16.2.2.11 PORTPMSCNUSB2—xHCI Port N Power Management Status and
Control USB2 Register
Offset: There are 15 USB2 PORTPMSC registers at offsets: 484h, 494h, 4A4h,
4B4h, 4C4h, 4D4h, 4E4h, 4F4h, 504h, 514h, 524h, 534h, 544h, 554h,
564h
Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
Port Test Control—R/W. When this field is ‘0’, the port is not operating in a test mode.
(Default)
A non-zero value indicates that the port is operating in test mode and the specific test
mode is indicated by the specific value.
A non-zero Port Test Control value is only valid to a port that is in the Disabled state. If
the port is not in this state, the xHC shall respond with the Port Test Control field set to
Port Test Control Error.
The encoding of the Test Mode bits for a USB 2.0 port are:
Value Test Mode
0h Test mode not enabled
31:28 1h Test J_STATE
2h Test K_STATE
3h Test SE0_NAK
4h Test Packet
5h Test FORCE_ENABLE
6h-14h Reserved.
15 Port Test Control Error
Refer to the Sections 7.1.20 and 11.24.2.13 of the USB 2.0 Specification for more
information on Test Modes.
NOTE: This bit is in the Suspend Well.
27:17 Reserved.
Hardware LPM Enable (HLE)—RO.
0 = Disable.
16 1 = Enable. When this bit is a 1, hardware controlled LPM shall be enabled for this port.
Refer to Section 4 of the USB 2.0 LPM Specification for more information.
NOTE: This bit is in the Suspend Well.
L1 Device Slot—R/W. System software sets this field to indicate the ID of the Device
Slot associated with the device directly attached to the Root Hub port. A value of 0
15:8 indicates there is no device present.
NOTE: This bit is in the Suspend Well.
Host Initiated Resume Duration (HIRD)—R/W. System software sets this field to
indicate to the recipient device how long the xHC will drive resume if it (the xHC)
initiates an exit from L1.
The HIRD value is encoded as follows: The value of 0000b is interpreted as 50 s. Each
7:4 incrementing value up adds 75 s to the previous value. For example, 0001b is 125 s,
0010b is 200 s and so on. Based on this rule, the maximum value resume drive time is
at encoding value 1111b which represents 1.2ms. Refer to Section 4 of the USB 2.0
LPM Specification for more information.
NOTE: This bit is in the Suspend Well.
Datasheet 739
xHCI Controller Registers (D20:F0)
Bit Description
Remote Wake Enable (RWE)—R/W. The host system sets this flag to enable or
disable the device for remote wake from L1.
0 = Disable. (Default)
1 = Enable.
3
The value of this flag will temporarily (while in L1) override the current setting of the
Remote Wake feature set by the standard Set/ClearFeature() commands defined in
Universal Serial Bus Specification, revision 2.0, Chapter 9.
NOTE: This bit is in the Suspend Well.
L1 status—RO.
2:0
NOTE: This bit is in the Suspend Well.
16.2.2.12 PORTSCNUSB3—xHCI USB 3.0 Port N Status and Control Register
Offset: There are 6 USB3 PORTSC registers at offsets: 570h, 580h, 590h,
5A0h, 5B0h, 5C0h
Attribute: R/W,RO
Default Value: 000002A0h Size: 32 bits
A host controller must implement one or more port registers. Software uses the N_Port
information from the Structural Parameters Register to determine how many ports
need to be serviced. All ports have the structure defined below. Software must not
write to unreported Port Status and Control Registers.
This register is in the suspend power well. It is only reset by hardware when the
suspend power is initially applied or in response to a host controller reset. The initial
conditions of a port are:
• No device connected
• Port disabled.
When a device is attached, the port state transitions to the attached state and system
software will process this as with any status change notification. Refer to Section 4 of
the xHCI Specification for operational requirements for how change events interact with
port suspend mode.
Bit Description
Warm Port Reset (WPR)—R/WO. When software sets this bit to 1b, the Warm Reset
sequence is initiated and the PR bit is set to 1b. Once initiated, the PR, PRC, and WRC
bits shall reflect the progress of the Warm Reset sequence. This flag shall always return
0b when read.
31
NOTE: This bit applies only to USB 3.0 capable ports. For ports that are only USB 2.0
capable, this bit is Reserved.
NOTE: This bit is in the Suspend Well.
Device Removable (DR)—RO. This bit indicates if this port has a removable device
attached.
30 0 = Device is removable.
1 = Device is non-removable.
NOTE: This bit is in the Core Well.
29:28 Reserved.
740 Datasheet
xHCI Controller Registers (D20:F0)
Bit Description
Wake on Over-current Enable (WOE)—R/W.
0 = Disable. (Default)
27 1 = Enable. Writing this bit to a 1b enables the port to be sensitive to over-current
conditions as system wake-up events.
NOTE: This bit is in the Suspend Well.
Wake on Disconnect Enable (WDE)—R/W.
0 = Disable. (Default)
26 1 = Enable. Writing this bit to a 1b enables the port to be sensitive to device
disconnects as system wake-up events.
NOTE: This bit is in the Suspend Well.
Wake on Connect Enable (WCE)—R/W.
0 = Disable. (Default)
25 1 = Enable. Writing this bit to a 1b enables the port to be sensitive to device connects
as system wake-up events.
NOTE: This bit is in the Suspend Well.
Cold Attach Status (CAS)—RO. This bit indicates that far-end terminations were
detected in the Disconnected state and the Root Hub Port State Machine was unable to
advance to the Enabled state.
24 Software shall clear this bit by writing a 1b to the WPR bit or the xHC shall clear this bit
if the CSS bit transitions to 1.
NOTE: This bit is 0b if the PP bit is 0b or for USB 2.0 capable-only ports.
NOTE: This bit is in the Suspend Well.
Port Config Error Change (CEC)—R/WOC. This flag indicates that the port failed to
configure its link partner.
Software shall clear this bit by writing a 1 to it.
23
NOTE: This bit applies only to USB 3.0 capable ports. This bit is Reserved for USB 2.0
capable-only ports.
NOTE: This bit is in the Suspend Well.
Datasheet 741
xHCI Controller Registers (D20:F0)
Bit Description
Port Link State Change (PLC)—R/WC.
0 = No change
1 = Link Status Change
This flag is set to ‘1’ due to the following Port Link State (PLS) transitions:
Transition Condition
U3 -> Resume Wakeup signaling from a device
Device Resume complete (USB 3.0 capable
Resume -> Recovery -> U0
ports only)
Device Resume complete (USB 2.0 capable-
Resume -> U0
only ports)
Software Resume complete (USB 3.0
U3 -> Recovery -> U0
capable ports only)
22
Software Resume complete (USB 2.0
U3 -> U0
capable-only ports)
L1 Resume complete (USB 2.0 capable-only
U2 -> U0
ports)
L1 Entry Reject (USB 2.0 capable-only
U0 -> U0
ports)
U0 -> Disabled L1 Entry Error (USB 2.0 capable-only ports)
Any state -> Inactive Error (USB 3.0 capable ports only)
NOTES:
1. This bit shall not be set if the PLS transition was due to software setting the PP
bit to 0b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit is in the Suspend Well.
Port Reset Change (PRC)—R/WC. This flag is set to ‘1’ due a '1' to '0' transition of
Port Reset (PR); such as when any reset processing on this port is complete.
0 = No change
1 = Reset Complete
21 NOTES:
1. This bit shall not be set to 1b if the reset processing was forced to terminate due
to software clearing the PP bit or PED bit to 0b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit is in the Suspend Well.
Over-current Change (OCC)—R/WC. The functionality of this bit is not dependent
upon the port owner. Software clears this bit by writing a 1 to it.
20 0 = No change. (Default)
1 = There is a change to Overcurrent Active.
NOTE: This bit is in the Suspend Well.
Warm Port Reset Change (WRC)—R/WC. This bit is set when Warm Reset
processing on this port completes.
0 = No change. (Default)
1 = Warm reset complete
NOTES:
19 1. This bit shall not be set to 1b if the reset processing was forced to terminate due
to software clearing the PP bit or PED bit to 0b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit applies only to USB 3.0 capable ports. This bit is Reserved for USB 2.0
capable-only ports.
4. This bit is in the Suspend Well.
742 Datasheet
xHCI Controller Registers (D20:F0)
Bit Description
Port Enabled/Disabled Change (PEC)—R/WC.
0 = No change. (Default)
1 = There is a change to PED bit.
NOTES:
1. This bit shall not be set if the PED transition was due to software setting the PP
bit to 0.
18 2. Software shall clear this bit by writing a 1 to it.
3. For a USB 2.0-only port, this bit shall be set to 1 only when the port is disabled
due to the appropriate conditions existing at the EOF2 point. (See Chapter 11 of
the USB Specification for the definition of a port error).
4. For a USB 3.0 port, this bit shall be set to ‘1’ if an enabled port transitions to a
Disabled state (that is, a ‘1’ to ‘0’ transition of PED). Refer to Section 4 of the
xHCI Specification for more information.
5. This bit is in the Suspend Well.
Connect Status Change (CSC)—R/WC. This flag indicates a change has occurred in
the port’s Current Connect Status (CCS) or Cold Attach Status (CAS) bits.
0 = No change. (Default)
1 = There is a change to the CCS or CAS bit.
The xHC sets this bit to 1b for all changes to the port device connect status, even if
system software has not cleared an existing Connect Status Change. For example, the
17 insertion status changes twice before system software has cleared the changed
condition, root hub hardware will be “setting” an already-set bit (that is, the bit will
remain 1b).
NOTES:
1. This bit shall not be set if the CCS transition was due to software setting the PP
bit to 0b, or the CAS bit transition was die to software setting the WPR bit to 1b.
2. Software shall clear this bit by writing a 1 to it.
3. This bit is in the Suspend Well.
Port Link State Write Strobe (LWS)—R/W.
0 = When 0b, write data in PLS field is ignored. (Default)
1 = When this bit is set to 1b on a write reference to this register, this flag enables
16 writes to the PLS field.
Reads to this bit return ‘0’.
NOTE: This bit is in the Suspend Well.
15:14 Reserved.
Port Speed (Port_Speed).
A device attached to this port operates at a speed defined by the following codes:
Value Speed
13:10
0100 SuperSpeed (5 Gb/s)
All other values reserved. Please refer to the eXtensible Host Controller Interface for
Universal Serial Bus Specification for additional details.
Port Power (PP)—RO. Read-only with a value of 1. This indicates that the port does
9 have power.
NOTE: This bit is in the Suspend Well.
Datasheet 743
xHCI Controller Registers (D20:F0)
Bit Description
Port Link State (PLS)—R/W. This field is used to power manage the port and reflects
its current link state.
When the port is in the Enabled state, system software may set the link U-state by
writing this field. System software may also write this field to force a Disabled to
Disconnected state transition of the port.
Write Value Description
0 The link shall transition to a U0 state from any of the U-states.
2 USB 2.0 ports only. The link should transition to the U2 State.
The link shall transition to a U3 state from any of the U-states.
This action selectively suspends the device connected to this
3 port. While the Port Link State = U3, the hub does not
propagate downstream-directed traffic to this port, but the hub
will respond to resume signaling from the port.
USB 3.0 ports only. If the port is in the Disabled state (PLS =
Disabled, PP = 1), then the link shall transition to a RxDetect
5
state and the port shall transition to the Disconnected state,
else ignored.
USB 2.0 ports only. If the port is in the U3 state (PLS = U3),
15 then the link shall remain in the U3 state and the port shall
transition to the U3Exit substate, else ignored.
All other values Ignored
8:5 NOTE: The Port Link State Write Strobe (LWS) shall be set to 1b to write this field.
Read Value Definition
0 Link is in the U0 State
1 Link is in the U1 State
2 Link is in the U2 State
3 Link is in the U3 State (Device Suspended)
4 Link is in the Disabled State
5 Link is in the RxDetect State
6 Link is in the Inactive State
7 Link is in the Polling State
8 Link is in the Recovery State
9 Link is in the Hot Reset State
10 Link is in the Compliance Mode State
11 Link is in the Test Mode State
12–14 Reserved
15 Link is in the Resume State
NOTES:
1. This field is undefined if PP = 0.
2. Transitions between different states are not reflected until the transition is
complete.
3. This bit is in the Suspend Well.
744 Datasheet
xHCI Controller Registers (D20:F0)
Bit Description
Port Reset (PR)—R/W. When software writes a 1 to this bit (from a 0), the bus reset
sequence as defined in the USB Specification, Revision 2.0 is started. Software writes a
0 to this bit to terminate the bus reset sequence. Software must keep this bit at a 1
long enough to ensure the reset sequence completes as specified in the USB
Specification, Revision 2.0. USB 3.0 ports shall execute the Hot Reset sequence as
4 defined in the USB 3.0 Specification. PR remains set until reset signaling is completed
by the root hub.
1 = Port is in Reset.
0 = Port is not in Reset.
NOTE: This bit is in the Suspend Well.
Overcurrent Active (OCA)—RO.
0 = This port does not have an overcurrent condition. (Default)
1 = This port currently has an overcurrent condition. This bit will automatically
3
transition from 1 to 0 when the over current condition is removed. The PCH
automatically disables the port when the overcurrent active bit is 1.
NOTE: This bit is in the Suspend Well.
2 Reserved.
Port Enabled/Disabled—R/W. Ports can only be enabled by the host controller as a
part of the reset and enable. Software cannot enable a port by writing a 1 to this bit.
Ports can be disabled by either a fault condition (disconnect event or other fault
condition) or by host software. The bit status does not change until the port state
1 actually changes. There may be a delay in disabling or enabling a port due to other host
controller and bus events.
0 = Disable
1 = Enable (Default)
NOTE: This bit is in the Suspend Well.
Current Connect Status—RO. This value reflects the current state of the port, and
may not correspond directly to the event that caused the Connect Status Change bit
(Bit 1) to be set.
0
0 = No device is present. (Default)
1 = Device is present on port.
NOTE: This bit is in the Suspend Well.
Datasheet 745
xHCI Controller Registers (D20:F0)
16.2.2.13 PORTPMSCN—Port N Power Management Status and Control
USB3 Register
Offset: There are 6 USB3 PORTPMSCN registers at offsets: 574h, 584h, 594h,
5A4h, 5B4h, 5C4h
Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:17 Reserved.
Force Link PM Accept (FLA)—R/W. When this bit is set to ‘1’, the port shall generate
a Set Link Function LMP with the Force_LinkPM_Accept bit asserted.
This bit shall be set to 0b by the assertion of PR to 1 or when CCS = transitions from 0
to 1.
16
Writes to this flag have no affect if PP = 0b.
The Set Link Function LMP is sent by the xHC to the device connected on this port when
this bit transitions from 0’ to 1. Refer to Sections 8.4.1, 10.4.2.2 and 10.4.2.9 of the
USB 3.0 Specification for more details.
U2 Timeout—R/W. Timeout value for U2 inactivity timer.
If equal to FFh, the port is disabled from initiating U2 entry. This field shall be set to 0
by the assertion of PR to 1. Refer to Section 4 of the xHCI Specification for more
information on U2 Timeout operation. The following are permissible values:
Value Description
15:8 00h Zero (default)
01h 256 s
02h 512 s
...
FEh 65.024 ms
FFh Infinite
U1 Timeout—R/W. Timeout value for U1 inactivity timer.
If equal to FFh, the port is disabled from initiating U1 entry. This field shall be set to 0
by the assertion of PR to 1. Refer to Section 4 of the xHCI Specification for more
information on U1 Timeout operation. The following are permissible values:
Value Description
00h Zero (default)
7:0
01h 1 s
02h 2 s
...
7Fh 127 s
80h-FEh Reserved
FFh Infinite
746 Datasheet
xHCI Controller Registers (D20:F0)
16.2.2.14 PORTLIX—USB 3.0 Port X Link Info Register
Offset: There are 6 USB3 PORTLIX registers at offsets: 578h, 588h, 598h,
5A8h, 5B8h, 5C8h
Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:16 Reserved.
15:0 Link Error Count - RO.
16.2.3 Host Controller Runtime Registers
This section defines the xHC runtime registers. The base address of this register space
is referred to as Runtime Base. The Runtime Base shall be 32-byte aligned and is
calculated by adding the value Runtime Register Space Offset register
(MEM_BASE+18h:bits 31:2) to the Capability Base address. All Runtime registers are
multiples of 32 bits in length.
Table 16-4. Enhanced Host Controller Operational Register Address Map
Runtime
Power
Base + Mnemonic Register Name Default Type
Well
Offset
00h–03h Core MFINDEX Microframe Index 00000000h RO
Interrupter X RO, R/W,
20h–23h Core IMAN 00000000h
Management R/WC
Interrupter X
24h–27h Core IMOD 00000FA0h R/W
Moderation
Event Ring Segment
28h–2Bh Core ERSTSZ 00000000h R/W, RO
Table Size X
Event Ring Segment
30h–33h Core ERSTBAL Table Base Address 00000000h R/W, RO
Low X
Event Ring Segment
34h–37h Core ERSTBAH Table Base Address 00000000h R/W
High X
Event Ring Dequeue
38h–3Bh Core ERDPL 00000000h R/W, R/WC
Pointer Low X
Event Ring Dequeue
3Ch–3Fh Core ERDPH 00000000h R/W
Pointer High X
16.2.3.1 MFINDEX—Microframe Index Register
Offset: Runtime Base + 00h-03h Attribute: RO,
Default Value: 00000000h Size: 32 bits
Bit Description
31:14 Reserved.
Microframe Index—RO. The value in this register increments at the end of each
13:0 microframe (such as 125 us.). Bits 13:3 may be used to determine the current 1ms.
Frame Index.
Datasheet 747
xHCI Controller Registers (D20:F0)
16.2.3.2 IMAN—Interrupter X Management Register
Offset: Interrupter 1: Runtime Base + 20h–23h
Interrupter 2: Runtime Base + 40h–43h
Interrupter 3: Runtime Base + 60h–63h
Interrupter 4: Runtime Base + 80h–83h
Interrupter 5: Runtime Base + A0h–A3h
Interrupter 6: Runtime Base + C0h–C3h
Interrupter 7: Runtime Base + E0h–E3h
Interrupter 8: Runtime Base + 100h–103h
Attribute: RO, R/W, R/WC
Default Value: 00000000h Size: 32 bits
Note: The xHC implements up to 8 Interrupters. There are 8 IMAN registers, one for each
Interrupter.
Bit Description
31:2 Reserved.
Interrupt Enable (IE)—RO. This flag specifies whether the Interrupter is capable of
generating an interrupt.
1 0 = The Interrupter is prohibited from generating interrupts.
1 = When this bit and the IP bit are set (1b), the Interrupter shall generate an interrupt
when the Interrupter Moderation Counter reaches ‘0’.
Interrupt Pending (IP)—R/WC.
0 = No interrupt is pending for the Interrupter.
1 = An interrupt is pending for this Interrupter.
This bit is set to 1b when IE = 1, the IMODI Interrupt Moderation Counter field = 0b,
0 the Event Ring associated with the Interrupter is not empty (or for the Primary
Interrupter when the HCE flag is set to 1b), and EHB = 0.
If MSI interrupts are enabled, this flag shall be cleared automatically when the PCI
DWord write generated by the Interrupt assertion is complete. If PCI Pin Interrupts are
enabled, this flag shall be cleared by software.
748 Datasheet
xHCI Controller Registers (D20:F0)
16.2.3.3 IMOD—Interrupter X Moderation Register
Offset: Interrupter 1: Runtime Base + 24h–27h
Interrupter 2: Runtime Base + 44h–47h
Interrupter 3: Runtime Base + 64h–67h
Interrupter 4: Runtime Base + 84h–87h
Interrupter 5: Runtime Base + A4h–A7h
Interrupter 6: Runtime Base + C4h–C7h
Interrupter 7: Runtime Base + E4h–E7h
Interrupter 8: Runtime Base + 104h–107h
Attribute: R/W
Default Value: 00000FA0h Size: 32 bits
Note: The xHC implements up to 8 Interrupters. There are 8 IMOD registers, one for each
Interrupter.
Bit Description
Interrupt Moderation Counter (IMODC)—R/W. Down counter. Loaded with Interval
Moderation value (value of bits 15:0) whenever the IP bit is cleared to 0b, counts down
31:16 to ‘0’, and stops. The associated interrupt shall be signaled whenever this counter is ‘0’,
the Event Ring is not empty, the IE and IP bits = 1, and EHB = 0.
This counter may be directly written by software at any time to alter the interrupt rate.
Interrupt Moderation Interval (IMODI)—R/W. Minimum inter-interrupt interval.
The interval is specified in 250ns increments. A value of ‘0’ disables interrupt throttling
15:0
logic and interrupts shall be generated immediately if IP = 0, EHB = 0, and the Event
Ring is not empty.
16.2.3.4 ERSTSZ—Event Ring Segment Table Size X Register
Offset: 1: Runtime Base + 28h–2Bh
2: Runtime Base + 48h–4Bh
3: Runtime Base + 68h–6Bh
4: Runtime Base + 88h–8Bh
5: Runtime Base + A8h–ABh
6: Runtime Base + C8h–CBh
7: Runtime Base + E8h–EBh
8: Runtime Base + 108h–10Bh
Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Note: There are 8 ERSTSZ registers.
Bit Description
31:16 Reserved.
Event Ring Segment Table Size—R/W. This field identifies the number of valid Event
15:0 Ring Segment Table entries in the Event Ring Segment Table pointed to by the Event
Ring Segment Table Base Address register.
Datasheet 749
xHCI Controller Registers (D20:F0)
16.2.3.5 ERSTBAL—Event Ring Segment Table Base Address Low X
Register
Offset: 1: Runtime Base + 30h–33h
2: Runtime Base + 50h–53h
3: Runtime Base + 70h–73h
4: Runtime Base + 90h–93h
5: Runtime Base + B0h–B3h
6: Runtime Base + D0h–D3h
7: Runtime Base + F0h–F3h
8: Runtime Base + 110h–113h
Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Note: There are 8 ERSTBAL registers.
Bit Description
Event Ring Segment Table Base Address Register (ERSTBA_LO)—R/W. This field
31:6 defines the low order bits of the start address of the Event Ring Segment Table.
This field shall not be modified if HCHalted (HCH) = 0.
5:0 Reserved.
16.2.3.6 ERSTBAH—Event Ring Segment Table Base Address High X
Register
Offset: 1: Runtime Base + 34h–37h
2: Runtime Base + 54h–57h
3: Runtime Base + 74h–77h
4: Runtime Base + 94h–97h
5: Runtime Base + B4h–B7h
6: Runtime Base + D4h–D7h
7: Runtime Base + F4h–F7h
8: 1Runtime Base + 14h–117h
Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: There are 8 ERSTBAH registers.
Bit Description
Event Ring Segment Table Base Address Register (ERSTBA_HI)—R/W. This field
31:0 defines the low order bits of the start address of the Event Ring Segment Table.
This field shall not be modified if HCHalted (HCH) = 0.
750 Datasheet
xHCI Controller Registers (D20:F0)
16.2.3.7 ERDPL—Event Ring Dequeue Pointer Low X Register
Offset: 1: Runtime Base + 38h–3Bh
2: Runtime Base + 58h–5Bh
3: Runtime Base + 78h–7Bh
4: Runtime Base + 98h–9Bh
5: Runtime Base + B8h–BBh
6: Runtime Base + D8h–dBh
7: Runtime Base + F8h–FBh
8: Runtime Base + 118h–11Bh
Attribute: R/W, R/WC
Default Value: 00000000h Size: 32 bits
Note: There are 8 ERDPL registers.
Bit Description
Event Ring Dequeue Pointer—R/W. This field defines the low order bits of the 64- bit
31:4
address of the current Event Ring Dequeue Pointer.
Event Handler Busy (EHB)—R/WC. This flag shall be set to ‘1’ when the IP bit is set
3
to ‘1’ and cleared to ‘0’ by software when the Dequeue Pointer register is written.
Dequeue ERST Segment Index (DESI)—R/W. This field may be used by the xHC to
accelerate checking the Event Ring full condition. This field is written with the low order
2:0
3 bits of the offset of the ERST entry which defines the Event Ring segment that Event
Ring Dequeue Pointer resides in.
16.2.3.8 ERDPH—Event Ring Dequeue Pointer High X Register
Offset: 1: Runtime Base + 3Ch–3Fh
2: Runtime Base + 5Ch–5Fh
3: Runtime Base + 7Ch–7Fh
4: Runtime Base + 9Ch–9Fh
5: Runtime Base + BCh–BFh
6: Runtime Base + DCh–DFh
7: Runtime Base + FCh–FFh
8: Runtime Base + 11Ch–11Fh
Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: There are 8 ERDPH registers.
Bit Description
Event Ring Dequeue Pointer—R/W. This field defines the low order bits of the 64- bit
31:0
address of the current Event Ring Dequeue Pointer.
Datasheet 751
xHCI Controller Registers (D20:F0)
16.2.4 Doorbell Registers
Door Bell registers are an array of 64 registers, with 0 to 32 being used by the xHC and
the remainder being reserved. One 32-bit Doorbell Register is defined in the array for
each Device Slot. System software utilizes the Doorbell Register to notify the xHC that
it has Device Slot related work for the xHC to perform.
These registers are pointed to by the Doorbell Offset Register (dBOFF) in the xHC
Capability register space. The Doorbell Array base address shall be DWord aligned and
is calculated by adding the value in the dBOFF register (MEM_BASE+14h-17h) to
“Base” (the base address of the xHCI Capability register address space).
All registers are 32 bits in length. Software should read and write these registers using
only DWord accesses.
16.2.4.1 DOORBELL—Doorbell X Register
Offset: Doorbell 1: dBOFF + 00h-03h
Doorbell 2: dBOFF + 04h-07h
....
Doorbell 32: dBOFF + 7Ch-7Fh
Attribute: R/W
Default Value: 00000000h Size: 32 bits
Power Well Core
Note: There are 32 contiguous DOORBELL registers.
Note: Reading this register will always show 00000000h.
Bit Description
dB Stream ID—R/W. If the endpoint of a Device Context Doorbell defines Streams,
then this field shall be used to identify which Stream of the endpoint the doorbell
reference is targeting. System software is responsible for ensuring that the value
written to this field is valid.
31:16 If the endpoint does not define Streams (MaxPStreams = 0) and a non-'0' value is
written to this field, the doorbell reference shall be ignored.
This field only applies to Device Context Doorbells and shall be cleared to ‘0’ for Host
Controller Commands.
This field returns ‘0’ when read.
15:8 Reserved.
dB Target—R/W. This field defines the target of the doorbell reference. The table below
defines the xHC notification that is generated by ringing the doorbell. The Doorbell
7:0 Register 0 is dedicated to Command Ring and decodes this field differently than the
other Doorbell Registers.
Refer to the xHCI Specification for definitions of the values.
§§
752 Datasheet
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17 Integrated Intel® High
Definition Audio (Intel® HD
Audio) Controller Registers
17.1 Intel® High Definition Audio (Intel® HD Audio)
Controller Registers (D27:F0)
The Intel High Definition Audio controller resides in PCI Device 27, Function 0 on bus 0.
This function contains a set of DMA engines that are used to move samples of digitally
encoded data between system memory and external codecs.
Note: All registers in this function (including memory-mapped registers) are addressable in
byte, word, and DWord quantities. The software must always make register accesses
on natural boundaries (that is, DWord accesses must be on DWord boundaries; word
accesses on word boundaries, and so on). Register access crossing the DWord
boundary are ignored. In addition, the memory-mapped register space must not be
accessed with the LOCK semantic exclusive-access mechanism. If software attempts
exclusive-access mechanisms to the Intel High Definition Audio memory-mapped
space, the results are undefined.
Note: Users interested in providing feedBack on the Intel High Definition Audio specification
or planning to implement the Intel High Definition Audio specification into a future
product will need to execute the Intel® High Definition Audio Specification Developer’s
Agreement. For more information, contact [email protected].
17.1.1 Intel® High Definition Audio PCI Configuration Space
(Intel® High Definition Audio—D27:F0)
Note: Address locations that are not shown should be treated as Reserved.
Table 17-1. Intel® High Definition Audio (Intel® HD Audio) PCI Register Address Map
(Intel® High Definition Audio D27:F0) (Sheet 1 of 3)
Offset Mnemonic Register Name Default Attribute
00h–01h VID Vendor Identification 8086h RO
See register
02h–03h DID Device Identification RO
description
04h–05h PCICMD PCI Command 0000h R/W, RO
06h–07h PCISTS PCI Status 0010h R/WC, RO
See register
08h RID Revision Identification RO
description
09h PI Programming Interface 00h RO
0Ah SCC Sub Class Code 03h RO
0Bh BCC Base Class Code 04h RO
0Ch CLS Cache Line Size 00h R/W
0Dh LT Latency Timer 00h RO
0Eh HEADTYP Header Type 00h RO
Datasheet 753
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
Table 17-1. Intel® High Definition Audio (Intel® HD Audio) PCI Register Address Map
(Intel® High Definition Audio D27:F0) (Sheet 2 of 3)
Offset Mnemonic Register Name Default Attribute
®
Intel High Definition Audio Lower Base
10h–13h HdBARL 00000004h R/W, RO
Address (Memory)
Intel® High Definition Audio Upper Base
14h–17h HdBARU 00000000h R/W
Address (Memory)
2Ch–2Dh SVID Subsystem Vendor Identification 0000h R/WO
2Eh–2Fh SID Subsystem Identification 0000h R/WO
34h CAPPTR Capability List Pointer 50h RO
3Ch INTLN Interrupt Line 00h R/W
See Register
3Dh INTPN Interrupt Pin RO
Description
40h HDCTL Intel® High Definition Audio Control 01h R/W, RO
4Ch DCKCTL Docking Control (Mobile Only) 00h R/W, RO
4Dh DCKSTS Docking Status (Mobile Only) 80h R/WO, RO
50h–51h PID PCI Power Management Capability ID 6001h R/WO, RO
52h–53h PC Power Management Capabilities C842h RO
R/W, RO,
54h–57h PCS Power Management Control and Status 00000000h
R/WC
60h–61h MID MSI Capability ID 7005h RO
62h–63h MMC MSI Message Control 0080h R/W, RO
64h–67h MMLA MSI Message Lower Address 00000000h R/W, RO
68h–6Bh MMUA MSI Message Upper Address 00000000h R/W
6Ch–6Dh MMD MSI Message Data 0000h R/W
70h–71h PXID PCI Express* Capability Identifiers 0010h RO
72h–73h PXC PCI Express Capabilities 0091h RO
74h–77h DEVCAP Device Capabilities 10000000h RO, R/WO
78h–79h DEVC Device Control 0800h R/W, RO
7Ah–7Bh DEVS Device Status 0010h RO
Virtual Channel Enhanced Capability
100h–103h VCCAP 13010002h R/WO
Header
104h–107h PVCCAP1 Port VC Capability Register 1 00000001h RO
108h–10Bh PVCCAP2 Port VC Capability Register 2 00000000h RO
10Ch–10D PVCCTL Port VC Control 0000h RO
10Eh–10Fh PVCSTS Port VC Status 0000h RO
110h–113h VC0CAP VC0 Resource Capability 00000000h RO
114h–117h VC0CTL VC0 Resource Control 800000FFh R/W, RO
11Ah–11Bh VC0STS VC0 Resource Status 0000h RO
11Ch–11Fh VCiCAP VCi Resource Capability 00000000h RO
120h–123h VCiCTL VCi Resource Control 00000000h R/W, RO
126h–127h VCiSTS VCi Resource Status 0000h RO
754 Datasheet
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
Table 17-1. Intel® High Definition Audio (Intel® HD Audio) PCI Register Address Map
(Intel® High Definition Audio D27:F0) (Sheet 3 of 3)
Offset Mnemonic Register Name Default Attribute
Root Complex Link Declaration Enhanced
130h–133h RCCAP 00010005h RO
Capability Header
134h–137h ESD Element Self Description 0F000100h RO
140h–143h L1DESC Link 1 Description 00000001h RO
See Register
148h–14Bh L1ADDL Link 1 Lower Address RO
Description
14Ch–14Fh L1ADDU Link 1 Upper Address 00000000h RO
17.1.1.1 VID—Vendor Identification Register
(Intel® High Definition Audio Controller—D27:F0)
Offset: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bits
Bit Description
15:0 Vendor ID—RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
17.1.1.2 DID—Device Identification Register
(Intel® High Definition Audio Controller—D27:F0)
Offset Address: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bits
Bit Description
Device ID—RO. This is a 16-bit value assigned to the PCH’s Intel® High Definition
15:0
Audio controller. See Section 1.3 for the value of the DID Register.
Datasheet 755
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.1.3 PCICMD—PCI Command Register
(Intel® High Definition Audio Controller—D27:F0)
Offset Address: 04h–05h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved
Interrupt Disable (ID)—R/W.
0= The INTx# signals may be asserted.
10 1= The Intel High Definition Audio controller’s INTx# signal will be de-asserted.
NOTE: This bit does not affect the generation of MSIs.
9 Fast Back to Back Enable (FBE)—RO. Hardwired to 0.
SERR# Enable (SERR_EN)—R/W. SERR# is not generated by the PCH Intel High
8
Definition Audio Controller.
7 Wait Cycle Control (WCC)—RO. Hardwired to 0.
6 Parity Error Response (PER)—R/W. PER functionality not implemented.
5 VGA Palette Snoop (VPS)—RO. Hardwired to 0.
4 Memory Write and Invalidate Enable (MWIE)—RO. Hardwired to 0.
3 Special Cycle Enable (SCE)—RO. Hardwired to 0.
Bus Master Enable (BME)—R/W. Controls standard PCI Express* bus mastering
capabilities for Memory and I/O, reads and writes. This bit also controls MSI
2 generation since MSI’s are essentially Memory writes.
0 = Disable
1 = Enable
Memory Space Enable (MSE)—R/W. Enables memory space addresses to the Intel
High Definition Audio controller.
1
0 = Disable
1 = Enable
I/O Space Enable (IOSE)—RO. Hardwired to 0 since the Intel High Definition Audio
0
controller does not implement I/O space.
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17.1.1.4 PCISTS—PCI Status Register
(Intel® High Definition Audio Controller—D27:F0)
Offset Address: 06h–07h Attribute: RO, R/WC
Default Value: 0010h Size: 16 bits
Bit Description
15 Detected Parity Error (DPE)—RO. Hardwired to 0.
14 SERR# Status (SERRS)—RO. Hardwired to 0.
Received Master Abort (RMA)—R/WC. Software clears this bit by writing a 1 to it.
0 = No master abort received.
13 1 = The Intel High Definition Audio controller sets this bit when, as a bus master, it
receives a master abort. When set, the Intel High Definition Audio controller
clears the run bit for the channel that received the abort.
12 Received Target Abort (RTA)—RO. Hardwired to 0.
11 Signaled Target Abort (STA)—RO. Hardwired to 0.
10:9 DEVSEL# Timing Status (DEV_STS)—RO. Hardwired to 0.
8 Data Parity Error Detected (DPED)—RO. Hardwired to 0.
7 Fast Back to Back Capable (FB2BC)—RO. Hardwired to 0.
6 Reserved
5 66 MHz Capable (66MHZ_CAP)—RO. Hardwired to 0.
Capabilities List (CAP_LIST)—RO. Hardwired to 1. Indicates that the controller
4 contains a capabilities pointer list. The first item is pointed to by looking at
configuration offset 34h.
Interrupt Status (IS)—RO.
0 = This bit is 0 after the interrupt is cleared.
3
1 = This bit is 1 when the INTx# is asserted.
This bit is not set by an MSI.
2:0 Reserved
17.1.1.5 RID—Revision Identification Register
(Intel® High Definition Audio Controller—D27:F0)
Offset: 08h Attribute: RO
Default Value: See bit description Size: 8 Bits
Bit Description
Revision ID—RO. This field indicates the device specific revision identifier. See
7:0
Section 1.3 for the value of the RID Register.
17.1.1.6 PI—Programming Interface Register
(Intel® High Definition Audio Controller—D27:F0)
Offset: 09h Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
7:0 Programming Interface—RO.
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17.1.1.7 SCC—Sub Class Code Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 0Ah Attribute: RO
Default Value: 03h Size: 8 bits
Bit Description
Sub Class Code (SCC)—RO.
7:0
03h = Audio Device
17.1.1.8 BCC—Base Class Code Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 0Bh Attribute: RO
Default Value: 04h Size: 8 bits
Bit Description
Base Class Code (BCC)—RO.
7:0
04h = Multimedia device
17.1.1.9 CLS—Cache Line Size Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 0Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Cache Line Size—R/W. Implemented as R/W register, but has no functional impact to
7:0
the PCH
17.1.1.10 LT—Latency Timer Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
7:0 Latency Timer—RO. Hardwired to 00
17.1.1.11 HEADTYP—Header Type Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 0Eh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
7:0 Header Type—RO. Hardwired to 00.
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17.1.1.12 HdBARL—Intel® High Definition Audio Lower Base Address
Register (Intel® High Definition Audio—D27:F0)
Address Offset: 10h–13h Attribute: R/W, RO
Default Value: 00000004h Size: 32 bits
Bit Description
Lower Base Address (LBA)—R/W. Base address for the Intel High Definition Audio
31:14 controller’s memory mapped configuration registers. 16 Kbytes are requested by
hardwiring bits 13:4 to 0s.
13:4 Reserved
Prefetchable (PREF)—RO. Hardwired to 0 to indicate that this BAR is NOT
3
prefetchable
Address Range (ADDRNG)—RO. Hardwired to 10b, indicating that this BAR can be
2:1
located anywhere in 64-bit address space.
Space Type (SPTYP)—RO. Hardwired to 0. Indicates this BAR is located in memory
0
space.
17.1.1.13 HdBARU—Intel® High Definition Audio Upper Base Address
Register (Intel® High Definition Audio Controller—D27:F0)
Address Offset: 14h–17h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Upper Base Address (UBA)—R/W. Upper 32 bits of the Base address for the Intel
31:0
High Definition Audio controller’s memory mapped configuration registers.
17.1.1.14 SVID—Subsystem Vendor Identification Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 2Ch–2Dh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Function Level Reset: No
The SVID register, in combination with the Subsystem ID register (D27:F0:2Eh),
enable the operating environment to distinguish one audio subsystem from the
other(s).
This register is implemented as write-once register. Once a value is written to it, the
value can be read back. Any subsequent writes will have no effect.
This register is not affected by the D3HOT to D0 transition.
Bit Description
Subsystem Vendor ID—R/WL.
15:0
Locked when HDCTL.BCLD = 1.
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17.1.1.15 SID—Subsystem Identification Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 2Eh–2Fh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Function Level Reset: No
The SID register, in combination with the Subsystem Vendor ID register (D27:F0:2Ch)
make it possible for the operating environment to distinguish one audio subsystem
from the other(s).
This register is implemented as write-once register. Once a value is written to it, the
value can be read back. Any subsequent writes will have no effect.
This register is not affected by the D3HOT to D0 transition.
Bit Description
Subsystem ID—R/WL.
15:0
Locked when HDCTL.BCLD = 1.
17.1.1.16 CAPPTR—Capabilities Pointer Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 34h Attribute: RO
Default Value: 50h Size: 8 bits
This register indicates the offset for the capability pointer.
Bit Description
Capabilities Pointer (CAP_PTR)—RO. This field indicates that the first capability
7:0
pointer offset is offset 50h (Power Management Capability).
17.1.1.17 INTLN—Interrupt Line Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 3Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Function Level Reset: No
Bit Description
Interrupt Line (INT_LN)—R/W. This data is not used by the PCH. It is used to
7:0
communicate to software the interrupt line that the interrupt pin is connected to.
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17.1.1.18 INTPN—Interrupt Pin Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 3Dh Attribute: RO
Default Value: See Description Size: 8 bits
Bit Description
7:4 Reserved
Interrupt Pin (IP)—RO. This reflects the value of D27IP.ZIP (Chipset Config
3:0
Registers:Offset 3110h:bits 3:0).
17.1.1.19 HDCTL—Intel® High Definition Audio Control Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 40h Attribute: RO
Default Value: 01h Size: 8 bits
Bit Description
7:2 Reserved
BIOS Configuration Lock Down Bit (BCLD): This bit being set is an indication that
BIOS configuration is done and HD-Audio Controller hardware can start operates using
1
the defined configurations. Setting this bit also lock down the read only field that BIOS
initialized
Intel® High Definition Signal Mode—RO.
0
This bit is hardwired to 1 (High Definition Audio mode).
17.1.1.20 DCKCTL—Docking Control Register (Mobile Only)
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 4Ch Attribute: R/W, RO
Default Value: 00h Size: 8 bits
Function Level Reset: No
Bit Description
7:1 Reserved
Dock Attach (DA)—R/W / RO. Software writes a 1 to this bit to initiate the docking
sequence on the HDA_DOCK_EN# and HDA_DOCK_RST# signals. When the docking
sequence is complete, hardware will set the Dock Mated (GSTS.DM) status bit to 1.
Software writes a 0 to this bit to initiate the undocking sequence on the
HDA_DOCK_EN# and HDA_DOCK_RST# signals. When the undocking sequence is
0 complete, hardware will set the Dock Mated (GSTS.DM) status bit to 0.
Software must check the state of the Dock Mated (GSTS.DM) bit prior to writing to the
Dock Attach bit. Software shall only change the DA bit from 0 to 1 when DM=0.
Likewise, software shall only change the DA bit from 1 to 0 when DM=1. If these rules
are violated, the results are undefined.
This bit is Read Only when the DCKSTS.DS bit = 0.
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17.1.1.21 DCKSTS—Docking Status Register (Mobile Only)
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 4Dh Attribute: R/WO, RO
Default Value: 80h Size: 8 bits
Function Level Reset: No
Bit Description
Docking Supported (DS)—R/WL. A 1 indicates that the PCH supports HD Audio
Docking. The DCKCTL.DA bit is only writable when this DS bit is 1. ACPI BIOS software
should only branch to the docking routine when this DS bit is 1. BIOS may clear this bit
7 to 0 to prohibit the ACPI BIOS software from attempting to run the docking routines.
This bit is reset to its default value only on a PLTRST#, but not on a CRST# or D3hot-
to-D0 transition.
Locked when HDCTL.BCLD = 1.
6:1 Reserved
Dock Mated (DM)—RO. This bit effectively communicates to software that an Intel HD
Audio docked codec is physically and electrically attached.
Controller hardware sets this bit to 1 after the docking sequence triggered by writing a
1 to the Dock Attach (GCTL.DA) bit is completed (HDA_DOCK_RST# de-assertion). This
0 bit indicates to software that the docked codec(s) may be discovered using the
STATESTS register and then enumerated.
Controller hardware sets this bit to 0 after the undocking sequence triggered by writing
a 0 to the Dock Attach (GCTL.DA) bit is completed (HDA_DOCK_EN# de-asserted). This
bit indicates to software that the docked codec(s) may be physically undocked.
17.1.1.22 PID—PCI Power Management Capability ID Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 50h–51h Attribute: R/WO, RO
Default Value: 6001h Size: 16 bits
Function Level Reset: No (Bits 7:0 only)
Bit Description
Next Capability (Next)—R/WL. Points to the next capability structure (MSI).
15:8
Locked when HDCTL.BCLD = 1.
Cap ID (CAP)—RO. Hardwired to 01h. Indicates that this pointer is a PCI power
7:0
management capability. These bits are not reset by Function Level Reset.
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17.1.1.23 PC—Power Management Capabilities Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 52h–53h Attribute: RO
Default Value: C842h Size: 16 bits
Bit Description
PME Support—RO. Hardwired to 11001b. Indicates PME# can be generated from D3
15:11
and D0 states.
10 D2 Support—RO. Hardwired to 0. Indicates that D2 state is not supported.
9 D1 Support—RO. Hardwired to 0. Indicates that D1 state is not supported.
Aux Current—RO. Hardwired to 001b. Reports 55 mA maximum suspend well current
8:6
required when in the D3COLD state.
Device Specific Initialization (DSI)—RO. Hardwired to 0. Indicates that no device
5
specific initialization is required.
4 Reserved
3 PME Clock (PMEC)—RO. Does not apply. Hardwired to 0.
Version—RO. Hardwired to 010b. Indicates support for version 1.1 of the PCI Power
2:0
Management Specification.
17.1.1.24 PCS—Power Management Control and Status Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 54h–57h Attribute: RO, R/W, R/WC
Default Value: 00000000h Size: 32 bits
Function Level Reset: No
Bit Description
31:24 Data—RO. Does not apply. Hardwired to 0.
23 Bus Power/Clock Control Enable—RO. Does not apply. Hardwired to 0.
22 B2/B3 Support—RO. Does not apply. Hardwired to 0.
21:16 Reserved
PME Status (PMES)—R/WC.
0 = Software clears the bit by writing a 1 to it.
1 = This bit is set when the Intel High Definition Audio controller would normally assert
15
the PME# signal independent of the state of the PME_EN bit (bit 8 in this register).
This bit is in the resume well and is cleared by a power-on reset. Software must not
make assumptions about the reset state of this bit and must set it appropriately.
14:9 Reserved
PME Enable (PMEE)—R/W.
0 = Disable
1 = When set and if corresponding PMES also set, the Intel High Definition Audio
8
controller sets the PME_B0_STS bit in the GPE0_STS register (PMBASE +28h).
This bit is in the resume well and is cleared on a power-on reset. Software must not
make assumptions about the reset state of this bit and must set it appropriately.
7:2 Reserved
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Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
Bit Description
Power State (PS)—R/W. This field is used both to determine the current power state
of the Intel High Definition Audio controller and to set a new power state.
00 = D0 state
11 = D3HOT state
Others = reserved
NOTES:
1:0 1. If software attempts to write a value of 01b or 10b in to this field, the write
operation must complete normally; however, the data is discarded and no state
change occurs.
2. When in the D3HOT states, the Intel High Definition Audio controller’s configuration
space is available, but the I/O and memory space are not. Additionally, interrupts
are blocked.
3. When software changes this value from D3HOT state to the D0 state, an internal
warm (soft) reset is generated, and software must re-initialize the function.
17.1.1.25 MID—MSI Capability ID Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 60h–61h Attribute: RO
Default Value: 7005h Size: 16 bits
Bit Description
Next Capability (Next)—RO. Hardwired to 70h. Points to the PCI Express* capability
15:8
structure.
7:0 Cap ID (CAP)—RO. Hardwired to 05h. Indicates that this pointer is a MSI capability.
17.1.1.26 MMC—MSI Message Control Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 62h–63h Attribute: RO, R/W
Default Value: 0080h Size: 16 bits
Bit Description
15:8 Reserved
64b Address Capability (64ADD)—RO. Hardwired to 1. Indicates the ability to
7
generate a 64-bit message address.
Multiple Message Enable (MME)—RO. Normally this is a R/W register. However since
6:4
only 1 message is supported, these bits are hardwired to 000 = 1 message.
Multiple Message Capable (MMC)—RO. Hardwired to 0 indicating request for 1
3:1
message.
MSI Enable (ME)—R/W.
0 0 = an MSI may not be generated
1 = an MSI will be generated instead of an INTx signal.
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17.1.1.27 MMLA—MSI Message Lower Address Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 64h–67h Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:2 Message Lower Address (MLA)—R/W. Lower address used for MSI message.
1:0 Reserved
17.1.1.28 MMUA—MSI Message Upper Address Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 68h–6Bh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Message Upper Address (MUA)—R/W. Upper 32-bits of address used for MSI
31:0
message.
17.1.1.29 MMD—MSI Message Data Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 6Ch–6Dh Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:0 Message Data (MD)—R/W. Data used for MSI message.
17.1.1.30 PXID—PCI Express* Capability ID Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 70h–71h Attribute: RO
Default Value: 0010h Size: 16 bits
Bit Description
Next Capability (Next)—RO. Hardwired to 0. Indicates that this is the last capability
15:8
structure in the list.
Cap ID (CAP)—RO. Hardwired to 10h. Indicates that this pointer is a PCI Express*
7:0
capability structure.
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17.1.1.31 PXC—PCI Express* Capabilities Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 72h–73h Attribute: RO
Default Value: 0091h Size: 16 bits
Bit Description
15:14 Reserved
13:9 Interrupt Message Number (IMN)—RO. Hardwired to 0.
8 Slot Implemented (SI)—RO. Hardwired to 0.
Device/Port Type (DPT)—RO. Hardwired to 1001b. Indicates that this is a Root
7:4
Complex Integrated endpoint device.
Capability Version (CV)—RO. Hardwired to 0001b. Indicates version #1 PCI Express
3:0
capability
17.1.1.32 DEVCAP—Device Capabilities Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 74h–77h Attribute: R/WO, RO
Default Value: 10000000h Size: 32 bits
Function Level Reset: No
Bit Description
31:29 Reserved
Function Level Reset (FLR)—R/WL. A 1 indicates that the PCH HD Audio Controller
28 supports the Function Level Reset Capability.
Locked when HDCTL.BCLD = 1.
27:26 Captured Slot Power Limit Scale (SPLS)—RO. Hardwired to 0.
25:18 Captured Slot Power Limit Value (SPLV)—RO. Hardwired to 0.
17:15 Reserved
14 Power Indicator Present—RO. Hardwired to 0.
13 Attention Indicator Present—RO. Hardwired to 0.
12 Attention Button Present—RO. Hardwired to 0.
Endpoint L1 Acceptable Latency—R/WL. BIOS must write to this bit field during boot.
11:9
Locked when HDCTL.BCLD = 1.
Endpoint L0s Acceptable Latency—R/WL. BIOS must write to this bit field during
8:6 boot.
Locked when HDCTL.BCLD = 1.
5 Extended Tag Field Support—RO. Hardwired to 0. Indicates 5-bit tag field support
Phantom Functions Supported—RO. Hardwired to 0. Indicates that phantom functions
4:3
not supported.
Max Payload Size Supported—RO. Hardwired to 0. Indicates 128-B maximum
2:0
payload size capability.
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17.1.1.33 DEVC—Device Control Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 78h–79h Attribute: R/W, RO
Default Value: 0800h Size: 16 bits
Function Level Reset: No (Bit 11 Only)
Bit Description
Initiate FLR (IF)—R/W. This bit is used to initiate FLR transition.
15 1 = A write of 1 initiates FLR transition. Since hardware does not respond to any cycles
until FLR completion, the read value by software from this bit is 0.
Max Read Request Size—RO. Hardwired to 0 enabling 128B maximum read request
14:12
size.
No Snoop Enable (NSNPEN)—R/W.
0 = The Intel High Definition Audio controller will not set the No Snoop bit. In this case,
isochronous transfers will not use VC1 (VCi) even if it is enabled since VC1 is never
snooped. Isochronous transfers will use VC0.
1 = The Intel High Definition Audio controller is permitted to set the No Snoop bit in the
11
Requester Attributes of a bus master transaction. In this case, VC0 or VC1 may be
used for isochronous transfers.
NOTE: This bit is not reset on D3HOT to D0 transition; however, it is reset by PLTRST#.
This bit is not reset by Function Level Reset.
Auxiliary Power Enable—RO. Hardwired to 0, indicating that Intel High Definition Audio
10
device does not draw AUX power
9 Phantom Function Enable—RO. Hardwired to 0 disabling phantom functions.
8 Extended Tag Field Enable—RO. Hardwired to 0 enabling 5-bit tag.
7:5 Max Payload Size—RO. Hardwired to 0 indicating 128B.
4 Enable Relaxed Ordering—RO. Hardwired to 0 disabling relaxed ordering.
3 Unsupported Request Reporting Enable—R/W. Not implemented.
2 Fatal Error Reporting Enable—R/W. Not implemented.
1 Non-Fatal Error Reporting Enable—R/W. Not implemented.
0 Correctable Error Reporting Enable—R/W. Not implemented.
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17.1.1.34 DEVS—Device Status Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 7Ah–7Bh Attribute: RO
Default Value: 0010h Size: 16 bits
Bit Description
15:6 Reserved
Transactions Pending—RO.
5 0 = Indicates that completions for all non-posted requests have been received
1 = Indicates that Intel High Definition Audio controller has issued non-posted requests
which have not been completed.
AUX Power Detected—RO. Hardwired to 1 indicating the device is connected to
4
resume power
3 Unsupported Request Detected—RO. Not implemented. Hardwired to 0.
2 Fatal Error Detected—RO. Not implemented. Hardwired to 0.
1 Non-Fatal Error Detected—RO. Not implemented. Hardwired to 0.
0 Correctable Error Detected—RO. Not implemented. Hardwired to 0.
17.1.1.35 VCCAP—Virtual Channel Enhanced Capability Header
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 100h–103h Attribute: R/WO
Default Value: 13010002h Size: 32 bits
Bit Description
Next Capability Offset—R/WL. Points to the next capability header.
130h = Root Complex Link Declaration Enhanced Capability Header
31:20
000h = Root Complex Link Declaration Enhanced Capability Header is not supported.
Locked when HDCTL.BCLD = 1.
Capability Version—R/WL.
0h =PCI Express Virtual channel capability and the Root Complex Topology Capability
structure are not supported.
19:16
1h =PCI Express Virtual channel capability and the Root Complex Topology Capability
structure are supported.
Locked when HDCTL.BCLD = 1.
PCI Express* Extended Capability—R/WL.
0000h =PCI Express Virtual channel capability and the Root Complex Topology
Capability structure are not supported.
15:0
0002h =PCI Express Virtual channel capability and the Root Complex Topology
Capability structure are supported.
Locked when HDCTL.BCLD = 1.
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17.1.1.36 PVCCAP1—Port VC Capability Register 1
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 104h–107h Attribute: RO
Default Value: 00000001h Size: 32 bits
Bit Description
31:12 Reserved
11:10 Port Arbitration Table Entry Size—RO. Hardwired to 0 since this is an endpoint device.
9:8 Reference Clock—RO. Hardwired to 0 since this is an endpoint device.
7 Reserved
Low Priority Extended VC Count—RO. Hardwired to 0. Indicates that only VC0 belongs
6:4
to the low priority VC group.
3 Reserved
Extended VC Count—RO. Hardwired to 001b. Indicates that 1 extended VC (in
2:0
addition to VC0) is supported by the Intel High Definition Audio controller.
17.1.1.37 PVCCAP2—Port VC Capability Register 2
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 108h–10Bh Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
VC Arbitration Table Offset—RO. Hardwired to 0 indicating that a VC arbitration table is
31:24
not present.
23:8 Reserved
VC Arbitration Capability—RO. Hardwired to 0. These bits are not applicable since the
7:0 Intel High Definition Audio controller reports a 0 in the Low Priority Extended VC Count
bits in the PVCCAP1 register.
17.1.1.38 PVCCTL—Port VC Control Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 10Ch–10Dh Attribute: RO
Default Value: 0000h Size: 16 bits
Bit Description
15:4 Reserved
VC Arbitration Select—RO. Hardwired to 0. Normally these bits are R/W. However, these
3:1 bits are not applicable since the Intel High Definition Audio controller reports a 0 in the
Low Priority Extended VC Count bits in the PVCCAP1 register.
0 Load VC Arbitration Table—RO. Hardwired to 0 since an arbitration table is not present.
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17.1.1.39 PVCSTS—Port VC Status Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 10Eh–10Fh Attribute: RO
Default Value: 0000h Size: 16 bits
Bit Description
15:1 Reserved
0 VC Arbitration Table Status—RO. Hardwired to 0 since an arbitration table is not present.
17.1.1.40 VC0CAP—VC0 Resource Capability Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 110h–113h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
Port Arbitration Table Offset—RO. Hardwired to 0 since this field is not valid for endpoint
31:24
devices
23 Reserved
Maximum Time Slots—RO. Hardwired to 0 since this field is not valid for endpoint
22:16
devices.
Reject Snoop Transactions—RO. Hardwired to 0 since this field is not valid for endpoint
15
devices.
Advanced Packet Switching—RO. Hardwired to 0 since this field is not valid for endpoint
14
devices.
13:8 Reserved
Port Arbitration Capability—RO. Hardwired to 0 since this field is not valid for endpoint
7:0
devices.
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17.1.1.41 VC0CTL—VC0 Resource Control Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 114h–117h Attribute: R/W, RO
Default Value: 800000FFh Size: 32 bits
Function Level Reset: No
Bit Description
31 VC0 Enable—RO. Hardwired to 1 for VC0.
30:27 Reserved
26:24 VC0 ID—RO. Hardwired to 0 since the first VC is always assigned as VC0.
23:20 Reserved
Port Arbitration Select—RO. Hardwired to 0 since this field is not valid for endpoint
19:17
devices.
Load Port Arbitration Table—RO. Hardwired to 0 since this field is not valid for endpoint
16
devices.
15:8 Reserved
TC/VC0 Map—R/W, RO. Bit 0 is hardwired to 1 since TC0 is always mapped VC0. Bits
7:0
[7:1] are implemented as R/W bits.
17.1.1.42 VC0STS—VC0 Resource Status Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 11Ah–11Bh Attribute: RO
Default Value: 0000h Size: 16 bits
Bit Description
15:2 Reserved
VC0 Negotiation Pending—RO. Hardwired to 0 since this bit does not apply to the
1
integrated Intel High Definition Audio device.
Port Arbitration Table Status—RO. Hardwired to 0 since this field is not valid for
0
endpoint devices.
Datasheet 771
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.1.43 VCiCAP—VCi Resource Capability Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 11Ch–11Fh Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
Port Arbitration Table Offset—RO. Hardwired to 0 since this field is not valid for endpoint
31:24
devices.
23 Reserved
Maximum Time Slots—RO. Hardwired to 0 since this field is not valid for endpoint
22:16
devices.
Reject Snoop Transactions—RO. Hardwired to 0 since this field is not valid for endpoint
15
devices.
Advanced Packet Switching—RO. Hardwired to 0 since this field is not valid for endpoint
14
devices.
13:8 Reserved
Port Arbitration Capability—RO. Hardwired to 0 since this field is not valid for endpoint
7:0
devices.
17.1.1.44 VCiCTL—VCi Resource Control Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 120h–123h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Function Level Reset: No
Bit Description
VCi Enable—R/W.
0 = VCi is disabled
31 1 = VCi is enabled
NOTE: This bit is not reset on D3HOT to D0 transition; however, it is reset by PLTRST#.
30:27 Reserved
VCi ID—R/W. This field assigns a VC ID to the VCi resource. This field is not used by
26:24
the PCH hardware, but it is R/W to avoid confusing software.
23:20 Reserved
Port Arbitration Select—RO. Hardwired to 0 since this field is not valid for endpoint
19:17
devices.
Load Port Arbitration Table—RO. Hardwired to 0 since this field is not valid for endpoint
16
devices.
15:8 Reserved
TC/VCi Map—R/W, RO. This field indicates the TCs that are mapped to the VCi
resource. Bit 0 is hardwired to 0 indicating that it cannot be mapped to VCi. Bits [7:1]
7:0
are implemented as R/W bits. This field is not used by the PCH hardware, but it is R/W
to avoid confusing software.
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Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.1.45 VCiSTS—VCi Resource Status Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 126h–127h Attribute: RO
Default Value: 0000h Size: 16 bits
Bit Description
15:2 Reserved
1 VCi Negotiation Pending—RO. Does not apply. Hardwired to 0.
Port Arbitration Table Status—RO. Hardwired to 0 since this field is not valid for
0
endpoint devices.
17.1.1.46 RCCAP—Root Complex Link Declaration Enhanced
Capability Header Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 130h–133h Attribute: RO
Default Value: 00010005h Size: 32 bits
Bit Description
31:20 Next Capability Offset—RO. Hardwired to 0 indicating this is the last capability.
19:16 Capability Version—RO. Hardwired to 1h.
15:0 PCI Express* Extended Capability ID—RO. Hardwired to 0005h.
17.1.1.47 ESD—Element Self Description Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 134h–137h Attribute: RO
Default Value: 0F000100h Size: 32 bits
Bit Description
Port Number—RO. Hardwired to 0Fh indicating that the Intel High Definition Audio
31:24
controller is assigned as Port #15d.
Component ID—RL. This field returns the value of the ESD.CID field of the chip
23:16 configuration section. ESD.CID is programmed by BIOS.
Locked when HDCTL.BCLD = 1.
Number of Link Entries—RO. The Intel High Definition Audio only connects to one
15:8
device, the PCH egress port. Therefore, this field reports a value of 1h.
7:4 Reserved
Element Type (ELTYP)—RO. The Intel High Definition Audio controller is an
3:0
integrated Root Complex Device. Therefore, the field reports a value of 0h.
Datasheet 773
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.1.48 L1DESC—Link 1 Description Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 140h–143h Attribute: RO
Default Value: 00000001h Size: 32 bits
Bit Description
Target Port Number—RO. The Intel High Definition Audio controller targets the PCH’s
31:24
Port 0.
Target Component ID—RO. This field returns the value of the ESD.CID field of the
23:16
chip configuration section. ESD.CID is programmed by BIOS.
15:2 Reserved
1 Link Type—RO. Hardwired to 0 indicating Type 0.
0 Link Valid—RO. Hardwired to 1.
17.1.1.49 L1ADDL—Link 1 Lower Address Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 148h–14Bh Attribute: RO
Default Value: See Register Description Size: 32 bits
Bit Description
Link 1 Lower Address—RO. Hardwired to match the RCBA register value in the PCI-
31:14
LPC bridge (D31:F0:F0h).
13:0 Reserved
17.1.1.50 L1ADDU—Link 1 Upper Address Register
(Intel® High Definition Audio Controller—D27:F0)
Address Offset: 14Ch–14Fh Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:0 Link 1 Upper Address—RO. Hardwired to 00000000h.
774 Datasheet
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2 Intel® High Definition Audio Memory Mapped
Configuration Registers
(Intel® High Definition Audio D27:F0)
The base memory location for these memory mapped configuration registers is
specified in the HdBAR register (D27:F0:offset 10h and D27:F0:offset 14h). The
individual registers are then accessible at HdBAR + Offset as indicated in Table 17-2.
These memory mapped registers must be accessed in byte, word, or DWord quantities.
Note: Address locations that are not shown should be treated as Reserved.
Table 17-2. Intel® High Definition Audio Memory Mapped Configuration Registers
Address Map (Intel® High Definition Audio D27:F0) (Sheet 1 of 4)
HdBAR +
Mnemonic Register Name Default Attribute
Offset
00h–01h GCAP Global Capabilities 4401h RO, R/WO
02h VMIN Minor Version 00h RO
03h VMAJ Major Version 01h RO
04h–05h OUTPAY Output Payload Capability 003Ch RO
06h–07h INPAY Input Payload Capability 001Dh RO
08h–0Bh GCTL Global Control 00000000h R/W
0Ch–0Dh WAKEEN Wake Enable 0000h R/W
0Eh–0Fh STATESTS State Change Status 0000h R/WC
10h–11h GSTS Global Status 0000h R/WC
12h-13h GCAP2 Global Capabilities 2 0001h R/WL
18h–19h OUTSTRMPAY Output Stream Payload Capability 0030h RO
1Ah–1Bh INSTRMPAY Input Stream Payload Capability 0018h RO
1Ch–1Fh — Reserved 00000000h RO
20h–23h INTCTL Interrupt Control 00000000h R/W
24h–27h INTSTS Interrupt Status 00000000h RO
30h–33h WALCLK Wall Clock Counter 00000000h RO
38h–3Bh SSYNC Stream Synchronization 00000000h R/W
40h–43h CORBLBASE CORB Lower Base Address 00000000h R/W, RO
44h–47h CORBUBASE CORB Upper Base Address 00000000h R/W
48h–49h CORBWP CORB Write Pointer 0000h R/W
4Ah–4Bh CORBRP CORB Read Pointer 0000h R/W, RO
4Ch CORBCTL CORB Control 00h R/W
4Dh CORBST CORB Status 00h R/WC
4Eh CORBSIZE CORB Size 42h RO
50h–53h RIRBLBASE RIRB Lower Base Address 00000000h R/W, RO
54h–57h RIRBUBASE RIRB Upper Base Address 00000000h R/W
58h–59h RIRBWP RIRB Write Pointer 0000h R/W, RO
5Ah–5Bh RINTCNT Response Interrupt Count 0000h R/W
Datasheet 775
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
Table 17-2. Intel® High Definition Audio Memory Mapped Configuration Registers
Address Map (Intel® High Definition Audio D27:F0) (Sheet 2 of 4)
HdBAR +
Mnemonic Register Name Default Attribute
Offset
5Ch RIRBCTL RIRB Control 00h R/W
5Dh RIRBSTS RIRB Status 00h R/WC
5Eh RIRBSIZE RIRB Size 42h RO
60h–63h IC Immediate Command 00000000h R/W
64h–67h IR Immediate Response 00000000h RO
R/W, R/
68h–69h ICS Immediate Command Status 0000h
WC
70h–73h DPLBASE DMA Position Lower Base Address 00000000h R/W, RO
74h–77h DPUBASE DMA Position Upper Base Address 00000000h R/W
80h–82h ISD0CTL Input Stream Descriptor Control 040000h R/W, RO
83h ISD0STS ISD0 Status 00h R/WC, RO
84h–87h ISD0LPIB ISD0 Link Position in Buffer 00000000h RO
88h–8Bh ISD0CBL ISD0 Cyclic Buffer Length 00000000h R/W
8Ch–8Dh ISD0LVI ISD0 Last Valid Index 0000h R/W
8Eh–8F ISD0FIFOW ISD0 FIFO Watermark 0004h R/W
90h–91h ISD0FIFOS ISD0 FIFO Size 0000h R/W
92h–93h ISD0FMT ISD0 Format 0000h R/W
ISD0 Buffer Descriptor List Pointer –
98h–9Bh ISD0BDPL 00000000h R/W, RO
Lower Base Address
ISD0 Buffer Description List Pointer –
9Ch–9Fh ISD0BDPU 00000000h R/W
Upper Base Address
Input Stream Descriptor 1(ISD1)
A0h–A2h ISD1CTL 040000h R/W, RO
Control
A3h ISD1STS ISD1 Status 00h R/WC, RO
A4h–A7h ISD1LPIB ISD1 Link Position in Buffer 00000000h RO
A8h–ABh ISD1CBL ISD1 Cyclic Buffer Length 00000000h R/W
ACh–ADh ISD1LVI ISD1 Last Valid Index 0000h R/W
AEh–AFh ISD1FIFOW ISD1 FIFO Watermark 0004h R/W
B0h–B1h ISD1FIFOS ISD1 FIFO Size 0000h R/W
B2h–B3h ISD1FMT ISD1 Format 0000h R/W
ISD1 Buffer Descriptor List Pointer –
B8h–BBh ISD1BDPL 00000000h R/W, RO
Lower Base Address
ISD1 Buffer Description List Pointer –
BCh–BFh ISD1BDPU 00000000h R/W
Upper Base Address
Input Stream Descriptor 2 (ISD2)
C0h–C2h ISD2CTL 040000h R/W, RO
Control
C3h ISD2STS ISD2 Status 00h R/WC, RO
C4h–C7h ISD2LPIB ISD2 Link Position in Buffer 00000000h RO
C8h–CBh ISD2CBL ISD2 Cyclic Buffer Length 00000000h R/W
776 Datasheet
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
Table 17-2. Intel® High Definition Audio Memory Mapped Configuration Registers
Address Map (Intel® High Definition Audio D27:F0) (Sheet 3 of 4)
HdBAR +
Mnemonic Register Name Default Attribute
Offset
CCh–CDh ISD2LVI ISD2 Last Valid Index 0000h R/W
CEh–CFh ISD1FIFOW ISD1 FIFO Watermark 0004h R/W
D0h–D1h ISD2FIFOS ISD2 FIFO Size 0000h R/W
D2h–D3h ISD2FMT ISD2 Format 0000h R/W
ISD2 Buffer Descriptor List Pointer –
D8h–dBh ISD2BDPL 00000000h R/W, RO
Lower Base Address
ISD2 Buffer Description List Pointer –
DCh–DFh ISD2BDPU 00000000h R/W
Upper Base Address
Input Stream Descriptor 3 (ISD3)
E0h–E2h ISD3CTL 040000h R/W, RO
Control
E3h ISD3STS ISD3 Status 00h R/WC, RO
E4h–E7h ISD3LPIB ISD3 Link Position in Buffer 00000000h RO
E8h–EBh ISD3CBL ISD3 Cyclic Buffer Length 00000000h R/W
ECh–EDh ISD3LVI ISD3 Last Valid Index 0000h R/W
EEh–EFh ISD3FIFOW ISD3 FIFO Watermark 0004h R/W
F0h–F1h ISD3FIFOS ISD3 FIFO Size 0000h R/W
F2h–F3h ISD3FMT ISD3 Format 0000h R/W
ISD3 Buffer Descriptor List Pointer –
F8h–FBh ISD3BDPL 00000000h R/W, RO
Lower Base Address
ISD3 Buffer Description List Pointer –
FCh–FFh ISD3BDPU 00000000h R/W
Upper Base Address
Output Stream Descriptor 0 (OSD0)
100h–102h OSD0CTL 040000h R/W, RO
Control
103h OSD0STS OSD0 Status 00h R/WC, RO
104h–107h OSD0LPIB OSD0 Link Position in Buffer 00000000h RO
108h–10Bh OSD0CBL OSD0 Cyclic Buffer Length 00000000h R/W
10Ch–10Dh OSD0LVI OSD0 Last Valid Index 0000h R/W
10Eh–10Fh OSD0FIFOW OSD0 FIFO Watermark 0004h R/W
110h–111h OSD0FIFOS OSD0 FIFO Size 0000h R/W
112–113h OSD0FMT OSD0 Format 0000h R/W
OSD0 Buffer Descriptor List Pointer –
118h–11Bh OSD0BDPL 00000000h R/W, RO
Lower Base Address
OSD0 Buffer Description List Pointer –
11Ch–11Fh OSD0BDPU 00000000h R/W
Upper Base Address
Output Stream Descriptor 1 (OSD1)
120h–122h OSD1CTL 040000h R/W, RO
Control
123h OSD1STS OSD1 Status 00h R/WC, RO
124h–127h OSD1LPIB OSD1 Link Position in Buffer 00000000h RO
128h–12Bh OSD1CBL OSD1 Cyclic Buffer Length 00000000h R/W
Datasheet 777
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
Table 17-2. Intel® High Definition Audio Memory Mapped Configuration Registers
Address Map (Intel® High Definition Audio D27:F0) (Sheet 4 of 4)
HdBAR +
Mnemonic Register Name Default Attribute
Offset
12Ch–12Dh OSD1LVI OSD1 Last Valid Index 0000h R/W
12Eh–12Fh OSD1FIFOW OSD1 FIFO Watermark 0004h R/W
130h–131h OSD1FIFOS OSD1 FIFO Size 0000h R/W
132h–133h OSD1FMT OSD1 Format 0000h R/W
OSD1 Buffer Descriptor List Pointer –
138h–13Bh OSD1BDPL 00000000h R/W, RO
Lower Base Address
OSD1 Buffer Description List Pointer –
13Ch–13Fh OSD1BDPU 00000000h R/W
Upper Base Address
Output Stream Descriptor 2 (OSD2)
140h–142h OSD2CTL 040000h R/W, RO
Control
143h OSD2STS OSD2 Status 00h R/WC, RO
144h–147h OSD2LPIB OSD2 Link Position in Buffer 00000000h RO
148h–14Bh OSD2CBL OSD2 Cyclic Buffer Length 00000000h R/W
14Ch–14Dh OSD2LVI OSD2 Last Valid Index 0000h R/W
14Eh–14Fh OSD2FIFOW OSD2 FIFO Watermark 0004h R/W
150h–151h OSD2FIFOS OSD2 FIFO Size 0000h R/W
152h–153h OSD2FMT OSD2 Format 0000h R/W
OSD2 Buffer Descriptor List Pointer –
158h–15Bh OSD2BDPL 00000000h R/W, RO
Lower Base Address
OSD2 Buffer Description List Pointer –
15Ch–15Fh OSD2BDPU 00000000h R/W
Upper Base Address
Output Stream Descriptor 3 (OSD3)
160h–162h OSD3CTL 040000h R/W, RO
Control
163h OSD3STS OSD3 Status 00h R/WC, RO
164h–167h OSD3LPIB OSD3 Link Position in Buffer 00000000h RO
168h–16Bh OSD3CBL OSD3 Cyclic Buffer Length 00000000h R/W
16Ch–16Dh OSD3LVI OSD3 Last Valid Index 0000h R/W
16Eh–16Fh OSD3FIFOW OSD3 FIFO Watermark 0004h R/W
170h–171h OSD3FIFOS OSD3 FIFO Size 0000h R/W
172h–173h OSD3FMT OSD3 Format 0000h R/W
OSD3 Buffer Descriptor List Pointer –
178h–17Bh OSD3BDPL 00000000h R/W, RO
Lower Base Address
OSD3 Buffer Description List Pointer –
17Ch–17Fh OSD3BDPU 00000000h R/W
Upper Base Address
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Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.1 GCAP—Global Capabilities Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 00h Attribute: RO, R/WO
Default Value: 4401h Size: 16 bits
Bit Description
Number of Output Stream Supported—R/WL. 0100b indicates that the PCH’s Intel
15:12 High Definition Audio controller supports 4 output streams.
Locked when HDCTL.BCLD = 1.
Number of Input Stream Supported—R/WL. 0100b indicates that the PCH’s Intel
11:8 High Definition Audio controller supports 4 input streams.
Locked when HDCTL.BCLD = 1.
Number of Bidirectional Stream Supported—RO. Hardwired to 0 indicating that the
7:3
PCH’s Intel High Definition Audio controller supports 0 bidirectional stream.
Number of Serial Data Out Signals—RO. Hardwired to 0 indicating that the PCH’s
2:1
Intel High Definition Audio controller supports 1 serial data output signal.
64-bit Address Supported—R/WL. 1b indicates that the PCH’s Intel High Definition
Audio controller supports 64-bit addressing for BDL addresses, data buffer addressees,
0
and command buffer addresses.
Locked when HDCTL.BCLD = 1.
17.1.2.2 VMIN—Minor Version Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 02h Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
Minor Version—RO. Hardwired to 0 indicating that the PCH supports minor revision
7:0
number 00h of the Intel High Definition Audio specification.
17.1.2.3 VMAJ—Major Version Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 03h Attribute: RO
Default Value: 01h Size: 8 bits
Bit Description
Major Version—RO. Hardwired to 01h indicating that the PCH supports major revision
7:0
number 1 of the Intel High Definition Audio specification.
Datasheet 779
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.4 OUTPAY—Output Payload Capability Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 04h Attribute: RO
Default Value: 003Ch Size: 16 bits
Bit Description
15:7 Reserved
Output Payload Capability—RO. Hardwired to 3Ch indicating 60 word payload.
This field indicates the total output payload available on the link. This does not include
bandwidth used for command and control. This measurement is in 16-bit word
quantities per 48 MHz frame. The default link clock of 24.000 MHz (the data is double
pumped) provides 1000 bits per frame, or 62.5 words in total. 40 bits are used for
6:0 command and control, leaving 60 words available for data payload.
00h = 0 word
01h = 1 word payload.
.....
FFh = 256 word payload.
17.1.2.5 INPAY—Input Payload Capability Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 06h Attribute: RO
Default Value: 001Dh Size: 16 bits
Bit Description
15:7 Reserved
Input Payload Capability—RO. Hardwired to 1Dh indicating 29 word payload.
This field indicates the total output payload available on the link. This does not include
bandwidth used for response. This measurement is in 16-bit word quantities per
48 MHz frame. The default link clock of 24.000 MHz provides 500 bits per frame, or
31.25 words in total. 36 bits are used for response, leaving 29 words available for data
6:0 payload.
00h = 0 word
01h = 1 word payload.
.....
FFh = 256 word payload.
780 Datasheet
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.6 GCTL—Global Control Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 08h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:9 Reserved
Accept Unsolicited Response Enable—R/W.
8 0 = Unsolicited responses from the codecs are not accepted.
1 = Unsolicited response from the codecs are accepted by the controller and placed
into the Response Input Ring Buffer.
7:2 Reserved
Flush Control—R/W. Writing a 1 to this bit initiates a flush. When the flush
completion is received by the controller, hardware sets the Flush Status bit and clears
this Flush Control bit. Before a flush cycle is initiated, the DMA Position Buffer must be
programmed with a valid memory address by software, but the DMA Position Buffer bit
1 0 needs not be set to enable the position reporting mechanism. Also, all streams must
be stopped (the associated RUN bit must be 0).
When the flush is initiated, the controller will flush the pipelines to memory to ensure
that the hardware is ready to transition to a D3 state. Setting this bit is not a critical
step in the power state transition if the content of the FIFOs is not critical.
Controller Reset #—R/W.
0 = Writing a 0 causes the Intel High Definition Audio controller to be reset. All state
machines, FIFOs, and non-resume well memory mapped configuration registers
(not PCI configuration registers) in the controller will be reset. The Intel High
Definition Audio link RESET# signal will be asserted, and all other link signals will
be driven to their default values. After the hardware has completed sequencing
into the reset state, it will report a 0 in this bit. Software must read a 0 from this
bit to verify the controller is in reset.
1 = Writing a 1 causes the controller to exit its reset state and de-assert the Intel High
Definition Audio link RESET# signal. Software is responsible for setting/clearing
this bit such that the minimum Intel High Definition Audio link RESET# signal
assertion pulse width specification is met. When the controller hardware is ready
to begin operation, it will report a 1 in this bit. Software must read a 1 from this
bit before accessing any controller registers. This bit defaults to a 0 after
0 Hardware reset, therefore, software needs to write a 1 to this bit to begin
operation.
NOTES:
1. The CORB/RIRB RUN bits and all stream RUN bits must be verified cleared to 0
before writing a 0 to this bit in order to assure a clean re-start.
2. When setting or clearing this bit, software must ensure that minimum link timing
requirements (minimum RESET# assertion time, and so on) are met.
3. When this bit is 0 indicating that the controller is in reset, writes to all Intel High
Definition Audio memory mapped registers are ignored as if the device is not
present. The only exception is this register itself. The Global Control register is
write-able as a DWord, Word, or Byte even when CRST# (this bit) is 0 if the byte
enable for the byte containing the CRST# bit (Byte Enable 0) is active. If Byte
Enable 0 is not active, writes to the Global Control register will be ignored when
CRST# is 0. When CRST# is 0, reads to Intel High Definition Audio memory
mapped registers will return their default value except for registers that are not
reset with PLTRST# or on a D3HOT to D0 transition.
Datasheet 781
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.7 WAKEEN—Wake Enable Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 0Ch Attribute: R/W
Default Value: 0000h Size: 16 bits
Function Level Reset: No
Bit Description
15:4 Reserved
SDIN Wake Enable Flags—R/W. These bits control which SDI signal(s) may generate
a wake event. A 1b in the bit mask indicates that the associated SDIN signal is enabled
to generate a wake.
Bit 0 is used for SDI[0]
Bit 1 is used for SDI[1]
3:0 Bit 2 is used for SDI[2]
Bit 3 is used for SDI[3]
NOTE: These bits are in the resume well and only cleared on a power on reset.
Software must not make assumptions about the reset state of these bits and
must set them appropriately.
17.1.2.8 STATESTS—State Change Status Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 0Eh Attribute: R/WC
Default Value: 0000h Size: 16 bits
Function Level Reset: No
Bit Description
15:4 Reserved
SDIN State Change Status Flags—R/WC. Flag bits that indicate which SDI signal(s)
received a state change event. The bits are cleared by writing 1s to them.
Bit 0 = SDI[0]
Bit 1 = SDI[1]
3:0 Bit 2 = SDI[2]
Bit 3 = SDI[3]
These bits are in the resume well and only cleared on a power on reset. Software must
not make assumptions about the reset state of these bits and must set them
appropriately.
782 Datasheet
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.9 GSTS—Global Status Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 10h Attribute: R/WC
Default Value: 0000h Size: 16 bits
Bit Description
15:2 Reserved
Flush Status—R/WC. This bit is set to 1 by hardware to indicate that the flush cycle
initiated when the Flush Control bit (HdBAR + 08h, bit 1) was set has completed.
1
Software must write a 1 to clear this bit before the next time the Flush Control bit is
set to clear the bit.
0 Reserved
17.1.2.10 GCAP2 Global Capabilities 2 Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 12h Attribute: R/WL
Default Value: 0001h Size: 16 bits
Bit Description
15:1 Reserved
Energy Efficient Audio Capability (EEAC)—R/WL. Indicates whether the energy
efficient audio with deeper buffering is supported or not.
0 0 = Not supported.
1 = Supported.
Locked when HDCTL.BCLD = 1.
17.1.2.11 OUTSTRMPAY—Output Stream Payload Capability
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 18h Attribute: RO
Default Value: 0030h Size: 16 bits
Bit Description
15:8 Reserved
Output Stream Payload Capability (OUTSTRMPAY)—RO. Indicates maximum
number of words per frame for any single output stream. This measurement is in 16 bit
word quantities per 48 kHz frame. 48 Words (96B) is the maximum supported,
therefore a value of 30h is reported in this register. Software must ensure that a format
which would cause more words per frame than indicated is not programmed into the
7:0 Output Stream Descriptor register.
00h = 0 words
01h = 1 word payload
…
FFh = 255h word payload
Datasheet 783
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.12 INSTRMPAY—Input Stream Payload Capability
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 1Ah Attribute: RO
Default Value: 0018h Size: 16 bits
Bit Description
15:8 Reserved
Input Stream Payload Capability (INSTRMPAY)—RO. Indicates maximum number
of words per frame for any single input stream. This measurement is in 16 bit word
quantities per 48 kHz frame. 24 Words (48B) is the maximum supported, therefore a
value of 18h is reported in this register. Software must ensure that a format which
would cause more words per frame than indicated is not programmed into the Input
7:0 Stream Descriptor register.
00h = 0 words
01h = 1 word payload
…
FFh = 255h word payload
17.1.2.13 INTCTL—Interrupt Control Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 20h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Global Interrupt Enable (GIE)—R/W. Global bit to enable device interrupt
generation.
1 = When set to 1, the Intel High Definition Audio function is enabled to generate an
31
interrupt. This control is in addition to any bits in the bus specific address space,
such as the Interrupt Enable bit in the PCI configuration space.
NOTE: This bit is not affected by the D3HOT to D0 transition.
Controller Interrupt Enable (CIE)—R/W. Enables the general interrupt for controller
functions.
1 = When set to 1, the controller generates an interrupt when the corresponding status
30
bit gets set due to a Response Interrupt, a Response Buffer Overrun, and State
Change events.
NOTE: This bit is not affected by the D3HOT to D0 transition.
29:8 Reserved
784 Datasheet
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
Bit Description
Stream Interrupt Enable (SIE)—R/W. When set to 1, the individual streams are
enabled to generate an interrupt when the corresponding status bits get set.
A stream interrupt will be caused as a result of a buffer with IOC = 1in the BDL entry
being completed, or as a result of a FIFO error (underrun or overrun) occurring. Control
over the generation of each of these sources is in the associated Stream Descriptor.
The streams are numbered and the SIE bits assigned sequentially, based on their order
in the register set.
7:0 Bit 0 = input stream 1
Bit 1 = input stream 2
Bit 2 = input stream 3
Bit 3 = input stream 4
Bit 4 = output stream 1
Bit 5 = output stream 2
Bit 6 = output stream 3
Bit 7 = output stream 4
17.1.2.14 INTSTS—Interrupt Status Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 24h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
Global Interrupt Status (GIS)—RO. This bit is an OR of all the interrupt status bits in
31 this register.
NOTE: This bit is not affected by the D3HOT to D0 transition.
Controller Interrupt Status (CIS)—RO. Status of general controller interrupt.
1 = Interrupt condition occurred due to a Response Interrupt, a Response Buffer
Overrun Interrupt, or a SDIN State Change event. The exact cause can be
determined by interrogating other registers. This bit is an OR of all of the stated
interrupt status bits for this register.
30
NOTES:
1. This bit is set regardless of the state of the corresponding interrupt enable bit,
but a hardware interrupt will not be generated unless the corresponding enable
bit is set.
2. This bit is not affected by the D3HOT to D0 transition.
29:8 Reserved
Stream Interrupt Status (SIS)—RO.
1 = Interrupt condition occurred on the corresponding stream. This bit is an OR of all of
the stream’s interrupt status bits.
NOTE: These bits are set regardless of the state of the corresponding interrupt enable
bits.
The streams are numbered and the SIE bits assigned sequentially, based on their order
in the register set.
7:0
Bit 0 = input stream 1
Bit 1 = input stream 2
Bit 2 = input stream 3
Bit 3 = input stream 4
Bit 4 = output stream 1
Bit 5 = output stream 2
Bit 6 = output stream 3
Bit 7 = output stream 4
Datasheet 785
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.15 WALCLK—Wall Clock Counter Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 30h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
Wall Clock Counter—RO. A 32-bit counter that is incremented on each link Bit Clock
period and rolls over from FFFF FFFFh to 0000 0000h. This counter will roll over to 0
31:0 with a period of approximately 179 seconds.
This counter is enabled while the Bit Clock bit is set to 1. Software uses this counter to
synchronize between multiple controllers. Will be reset on controller reset.
17.1.2.16 SSYNC—Stream Synchronization Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 38h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:8 Reserved
Stream Synchronization (SSYNC)—R/W. When set to 1, these bits block data from
being sent on or received from the link. Each bit controls the associated stream
descriptor (that is, bit 0 corresponds to the first stream descriptor, and so on)
To synchronously start a set of DMA engines, these bits are first set to 1. The RUN bits
for the associated stream descriptors are then set to 1 to start the DMA engines. When
all streams are ready (FIFORDY =1), the associated SSYNC bits can all be set to 0 at
the same time, and transmission or reception of bits to or from the link will begin
together at the start of the next full link frame.
To synchronously stop the streams, first these bits are set, and then the individual RUN
bits in the stream descriptor are cleared by software.
If synchronization is not desired, these bits may be left as 0, and the stream will simply
7:0 begin running normally when the stream’s RUN bit is set.
The streams are numbered and the SIE bits assigned sequentially, based on their order
in the register set.
Bit 0 = input stream 1
Bit 1 = input stream 2
Bit 2 = input stream 3
Bit 3 = input stream 4
Bit 4 = output stream 1
Bit 5= output stream 2
Bit 6= output stream 3
Bit 7= output stream 4
786 Datasheet
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.17 CORBLBASE—CORB Lower Base Address Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 40h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
CORB Lower Base Address—R/W. Lower address of the Command Output Ring
Buffer, allowing the CORB base address to be assigned on any 128-B boundary. This
31:7
register field must not be written when the DMA engine is running or the DMA transfer
may be corrupted.
CORB Lower Base Unimplemented Bits—RO. Hardwired to 0. This required the
6:0
CORB to be allocated with 128B granularity to allow for cache line fetch optimizations.
17.1.2.18 CORBUBASE—CORB Upper Base Address Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 44h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
CORB Upper Base Address—R/W. Upper 32 bits of the address of the Command
31:0 Output Ring buffer. This register field must not be written when the DMA engine is
running or the DMA transfer may be corrupted.
17.1.2.19 CORBWP—CORB Write Pointer Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 48h Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:8 Reserved
CORB Write Pointer—R/W. Software writes the last valid CORB entry offset into this
field in DWord granularity. The DMA engine fetches commands from the CORB until the
7:0
Read pointer matches the Write pointer. Supports 256 CORB entries (256x4B = 1KB).
This register field may be written when the DMA engine is running.
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Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.20 CORBRP—CORB Read Pointer Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 4Ah Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
CORB Read Pointer Reset—R/W. Software writes a 1 to this bit to reset the CORB
Read Pointer to 0 and clear any residual prefetched commands in the CORB hardware
buffer within the Intel High Definition Audio controller. The hardware will physically
update this bit to 1 when the CORB Pointer reset is complete. Software must read a 1
15
to verify that the reset completed correctly. Software must clear this bit back to 0 and
read back the 0 to verify that the clear completed correctly. The CORB DMA engine
must be stopped prior to resetting the Read Pointer or else DMA transfer may be
corrupted.
14:8 Reserved
CORB Read Pointer (CORBRP)—RO. Software reads this field to determine how
many commands it can write to the CORB without over-running. The value read
indicates the CORB Read Pointer offset in DWord granularity. The offset entry read from
7:0
this field has been successfully fetched by the DMA controller and may be over-written
by software. Supports 256 CORB entries (256 x 4B=1KB). This field may be read while
the DMA engine is running.
17.1.2.21 CORBCTL—CORB Control Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 4Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:2 Reserved
Enable CORB DMA Engine—R/W.
0 = DMA stop
1 1 = DMA run
After software writes a 0 to this bit, the hardware may not stop immediately. The
hardware will physically update the bit to 0 when the DMA engine is truly stopped.
Software must read a 0 from this bit to verify that the DMA engine is truly stopped.
CORB Memory Error Interrupt Enable—R/W.
0 If this bit is set, the controller will generate an interrupt if the CMEI status bit (HdBAR +
4Dh: bit 0) is set.
788 Datasheet
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.22 CORBST—CORB Status Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 4Dh Attribute: R/WC
Default Value: 00h Size: 8 bits
Bit Description
7:1 Reserved
CORB Memory Error Indication (CMEI)—R/WC.
1 = Controller detected an error in the path way between the controller and memory.
This may be an ECC bit error or any other type of detectable data error which
0 renders the command data fetched invalid.
Software can clear this bit by writing a 1 to it. However, this type of error leaves the
audio subsystem in an un-viable state and typically requires a controller reset by
writing a 0 to the Controller Reset # bit (HdBAR + 08h: bit 0).
17.1.2.23 CORBSIZE—CORB Size Register
Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 4Eh Attribute: RO
Default Value: 42h Size: 8 bits
Bit Description
CORB Size Capability—RO. Hardwired to 0100b indicating that the PCH only supports
7:4
a CORB size of 256 CORB entries (1024B)
3:2 Reserved
1:0 CORB Size—RO. Hardwired to 10b which sets the CORB size to 256 entries (1024B)
17.1.2.24 RIRBLBASE—RIRB Lower Base Address Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 50h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
RIRB Lower Base Address—R/W. Lower address of the Response Input Ring Buffer,
allowing the RIRB base address to be assigned on any 128-B boundary. This register
31:7
field must not be written when the DMA engine is running or the DMA transfer may be
corrupted.
RIRB Lower Base Unimplemented Bits—RO. Hardwired to 0. This required the RIRB to
6:0
be allocated with 128-B granularity to allow for cache line fetch optimizations.
Datasheet 789
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.25 RIRBUBASE—RIRB Upper Base Address Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 54h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
RIRB Upper Base Address—R/W. Upper 32 bits of the address of the Response Input
31:0 Ring Buffer. This register field must not be written when the DMA engine is running or
the DMA transfer may be corrupted.
17.1.2.26 RIRBWP—RIRB Write Pointer Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 58h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
RIRB Write Pointer Reset—R/W. Software writes a 1 to this bit to reset the RIRB
Write Pointer to 0. The RIRB DMA engine must be stopped prior to resetting the Write
15
Pointer or else DMA transfer may be corrupted.
This bit is always read as 0.
14:8 Reserved
RIRB Write Pointer (RIRBWP)—RO. Indicates the last valid RIRB entry written by
the DMA controller. Software reads this field to determine how many responses it can
read from the RIRB. The value read indicates the RIRB Write Pointer offset in 2 DWord
7:0
RIRB entry units (since each RIRB entry is 2 DWords long). Supports up to 256 RIRB
entries (256 x 8 B = 2 KB). This register field may be written when the DMA engine is
running.
17.1.2.27 RINTCNT—Response Interrupt Count Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 5Ah Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:8 Reserved
N Response Interrupt Count—R/W.
0000 0001b = 1 response sent to RIRB
...........
1111 1111b = 255 responses sent to RIRB
0000 0000b = 256 responses sent to RIRB
7:0 The DMA engine should be stopped when changing this field or else an interrupt may be
lost.
Each response occupies 2 DWords in the RIRB.
This is compared to the total number of responses that have been returned, as opposed
to the number of frames in which there were responses. If more than one codecs
responds in one frame, then the count is increased by the number of responses
received in the frame.
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Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.28 RIRBCTL—RIRB Control Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 5Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:3 Reserved
Response Overrun Interrupt Control—R/W. If this bit is set, the hardware will
2 generate an interrupt when the Response Overrun Interrupt Status bit (HdBAR + 5Dh:
bit 2) is set.
Enable RIRB DMA Engine—R/W.
0 = DMA stop
1 = DMA run
1
After software writes a 0 to this bit, the hardware may not stop immediately. The
hardware will physically update the bit to 0 when the DMA engine is truly stopped.
Software must read a 0 from this bit to verify that the DMA engine is truly stopped.
Response Interrupt Control—R/W.
0 = Disable Interrupt
0 1 = Generate an interrupt after N number of responses are sent to the RIRB buffer OR
when an empty Response slot is encountered on all SDI[x] inputs (whichever
occurs first). The N counter is reset when the interrupt is generated.
17.1.2.29 RIRBSTS—RIRB Status Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 5Dh Attribute: R/WC
Default Value: 00h Size: 8 bits
Bit Description
7:3 Reserved
Response Overrun Interrupt Status—R/WC.
1 = Software sets this bit to 1 when the RIRB DMA engine is not able to write the
incoming responses to memory before additional incoming responses overrun the
internal FIFO. When the overrun occurs, the hardware will drop the responses
2
which overrun the buffer. An interrupt may be generated if the Response Overrun
Interrupt Control bit is set. This status bit is set even if an interrupt is not enabled
for this event.
Software clears this bit by writing a 1 to it.
1 Reserved
Response Interrupt—R/WC.
1 = Hardware sets this bit to 1 when an interrupt has been generated after N number
of Responses are sent to the RIRB buffer OR when an empty Response slot is
0
encountered on all SDI[x] inputs (whichever occurs first). This status bit is set even
if an interrupt is not enabled for this event.
Software clears this bit by writing a 1 to it.
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Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.30 RIRBSIZE—RIRB Size Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 5Eh Attribute: RO
Default Value: 42h Size: 8 bits
Bit Description
RIRB Size Capability—RO. Hardwired to 0100b indicating that the PCH only supports
7:4
a RIRB size of 256 RIRB entries (2048B).
3:2 Reserved
1:0 RIRB Size—RO. Hardwired to 10b which sets the CORB size to 256 entries (2048B).
17.1.2.31 IC—Immediate Command Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 60h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Immediate Command Write—R/W. The command to be sent to the codec using the
Immediate Command mechanism is written to this register. The command stored in this
31:0
register is sent out over the link during the next available frame after a 1 is written to
the ICB bit (HdBAR + 68h: bit 0).
17.1.2.32 IR—Immediate Response Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 64h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
Immediate Response Read (IRR)—RO. This register contains the response received
from a codec resulting from a command sent using the Immediate Command
mechanism.
31:0
If multiple codecs responded in the same time, there is no assurance as to which
response will be latched. Therefore, broadcast-type commands must not be issued
using the Immediate Command mechanism.
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Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.33 ICS—Immediate Command Status Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 68h Attribute: R/W, R/WC
Default Value: 0000h Size: 16 bits
Bit Description
15:2 Reserved
Immediate Result Valid (IRV)—R/WC.
1 = Set to 1 by hardware when a new response is latched into the Immediate Response
register (HdBAR + 64). This is a status flag indicating that software may read the
1
response from the Immediate Response register.
Software must clear this bit by writing a 1 to it before issuing a new command so that
the software may determine when a new response has arrived.
Immediate Command Busy (ICB)—R/W. When this bit is read as 0, it indicates that
a new command may be issued using the Immediate Command mechanism. When this
bit transitions from a 0 to a 1 (using software writing a 1), the controller issues the
command currently stored in the Immediate Command register to the codec over the
link. When the corresponding response is latched into the Immediate Response register,
0 the controller hardware sets the IRV flag and clears the ICB bit back to 0. Software may
write this bit to a 0 if the bit fails to return to 0 after a reasonable time out period.
NOTE: An Immediate Command must not be issued while the CORB/RIRB mechanism
is operating, otherwise the responses conflict. This must be enforced by
software.
17.1.2.34 DPLBASE—DMA Position Lower Base Address Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 70h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
DMA Position Lower Base Address—R/W. Lower 32 bits of the DMA Position Buffer
Base Address. This register field must not be written when any DMA engine is running
31:7 or the DMA transfer may be corrupted. This same address is used by the Flush Control
and must be programmed with a valid value before the Flush Control bit
(HdBAR+08h:bit 1) is set.
DMA Position Lower Base Unimplemented bits—RO. Hardwired to 0 to force the 128-
6:1
byte buffer alignment for cache line write optimizations.
DMA Position Buffer Enable—R/W.
1 = Controller will write the DMA positions of each of the DMA engines to the buffer in
0
the main memory periodically (typically once per frame). Software can use this
value to know what data in memory is valid data.
Datasheet 793
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.35 DPUBASE—DMA Position Upper Base Address Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address: HdBAR + 74h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
DMA Position Upper Base Address—R/W. Upper 32 bits of the DMA Position Buffer
31:0 Base Address. This register field must not be written when any DMA engine is running
or the DMA transfer may be corrupted.
17.1.2.36 SDCTL—Stream Descriptor Control Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HdBAR + 80h Attribute: R/W, RO
Input Stream[1]: HdBAR + A0h
Input Stream[2]: HdBAR + C0h
Input Stream[3]: HdBAR + E0h
Output Stream[0]: HdBAR + 100h
Output Stream[1]: HdBAR + 120h
Output Stream[2]: HdBAR + 140h
Output Stream[3]: HdBAR + 160h
Default Value: 040000h Size: 24 bits
Bit Description
Stream Number—R/W. This value reflect the Tag associated with the data being
transferred on the link.
When data controlled by this descriptor is sent out over the link, it will have its stream
number encoded on the SYNC signal.
When an input stream is detected on any of the SDI signals that match this value, the
data samples are loaded into FIFO associated with this descriptor.
23:20 While a single SDI input may contain data from more than one stream number, two
different SDI inputs may not be configured with the same stream number.
0000 = Reserved
0001 = Stream 1
........
1110 = Stream 14
1111 = Stream 15
Bidirectional Direction Control—RO. This bit is only meaningful for bidirectional
19
streams; therefore, this bit is hardwired to 0.
Traffic Priority—RO. Hardwired to 1 indicating that all streams will use VC1 if it is
18
enabled through the PCI Express* registers.
Stripe Control—RO. This bit is only meaningful for input streams; therefore, this bit is
17:16
hardwired to 0.
15:5 Reserved
Descriptor Error Interrupt Enable—R/W.
4 0 = Disable
1 = An interrupt is generated when the Descriptor Error Status bit is set.
FIFO Error Interrupt Enable—R/W.
3 This bit controls whether the occurrence of a FIFO error (overrun for input or underrun
for output) will cause an interrupt or not. If this bit is not set, bit 3in the Status register
will be set, but the interrupt will not occur. Either way, the samples will be dropped.
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Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
Bit Description
Interrupt on Completion Enable—R/W.
2 This bit controls whether or not an interrupt occurs when a buffer completes with the
IOC bit set in its descriptor. If this bit is not set, bit 2 in the Status register will be set,
but the interrupt will not occur.
Stream Run (RUN)—R/W.
0 = DMA engine associated with this input stream will be disabled. The hardware will
report a 0 in this bit when the DMA engine is actually stopped. Software must read
a 0 from this bit before modifying related control registers or restarting the DMA
1 engine.
1 = DMA engine associated with this input stream will be enabled to transfer data from
the FIFO to the main memory. The SSYNC bit must also be cleared in order for the
DMA engine to run. For output streams, the cadence generator is reset whenever
the RUN bit is set.
Stream Reset (SRST)—R/W.
0 = Writing a 0 causes the corresponding stream to exit reset. When the stream
hardware is ready to begin operation, it will report a 0 in this bit. Software must
read a 0 from this bit before accessing any of the stream registers.
0 1 = Writing a 1 causes the corresponding stream to be reset. The Stream Descriptor
registers (except the SRST bit itself) and FIFOs for the corresponding stream are
reset. After the stream hardware has completed sequencing into the reset state, it
will report a 1 in this bit. Software must read a 1 from this bit to verify that the
stream is in reset. The RUN bit must be cleared before SRST is asserted.
Datasheet 795
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.37 SDSTS—Stream Descriptor Status Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HdBAR + 83h Attribute: R/WC, RO
Input Stream[1]: HdBAR + A3h
Input Stream[2]: HdBAR + C3h
Input Stream[3]: HdBAR + E3h
Output Stream[0]: HdBAR + 103h
Output Stream[1]: HdBAR + 123h
Output Stream[2]: HdBAR + 143h
Output Stream[3]: HdBAR + 163h
Default Value: 00h Size: 8 bits
Bit Description
7:6 Reserved
FIFO Ready (FIFORDY)—RO. For output streams, the controller hardware will set this
bit to 1 while the output DMA FIFO contains enough data to maintain the stream on the
5 link. This bit defaults to 0 on reset because the FIFO is cleared on a reset.
For input streams, the controller hardware will set this bit to 1 when a valid descriptor
is loaded and the engine is ready for the RUN bit to be set.
Descriptor Error—R/WC.
1 = A serious error occurred during the fetch of a descriptor. This could be a result of a
Master Abort, a parity or ECC error on the bus, or any other error which renders
the current Buffer Descriptor or Buffer Descriptor list useless. This error is treated
4 as a fatal stream error, as the stream cannot continue running. The RUN bit will be
cleared and the stream will stopped.
Software may attempt to restart the stream engine after addressing the cause of the
error and writing a 1 to this bit to clear it.
FIFO Error—R/WC.
1 = FIFO error occurred. This bit is set even if an interrupt is not enabled. The bit is
cleared by writing a 1 to it.
For an input stream, this indicates a FIFO overrun occurring while the RUN bit is set.
3 When this happens, the FIFO pointers do not increment and the incoming data is not
written into the FIFO, thereby being lost.
For an output stream, this indicates a FIFO underrun when there are still buffers to
send. The hardware should not transmit anything on the link for the associated stream
if there is not valid data to send.
Buffer Completion Interrupt Status—R/WC.
2 This bit is set to 1 by the hardware after the last sample of a buffer has been
processed, AND if the Interrupt on Completion bit is set in the command byte of the
buffer descriptor. It remains active until software clears it by writing a 1 to it.
1:0 Reserved
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Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.38 SDLPIB—Stream Descriptor Link Position in Buffer
Register (Intel® High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HdBAR + 84h Attribute: RO
Input Stream[1]: HdBAR + A4h
Input Stream[2]: HdBAR + C4h
Input Stream[3]: HdBAR + E4h
Output Stream[0]: HdBAR + 104h
Output Stream[1]: HdBAR + 124h
Output Stream[2]: HdBAR + 144h
Output Stream[3]: HdBAR + 164h
Default Value: 00000000h Size: 32 bits
Bit Description
Link Position in Buffer—RO. Indicates the number of bytes that have been received
31:0 off the link. This register will count from 0 to the value in the Cyclic Buffer Length
register and then wrap to 0.
17.1.2.39 SDCBL—Stream Descriptor Cyclic Buffer Length Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HdBAR + 88h Attribute: R/W
Input Stream[1]: HdBAR + A8h
Input Stream[2]: HdBAR + C8h
Input Stream[3]: HdBAR + E8h
Output Stream[0]: HdBAR + 108h
Output Stream[1]: HdBAR + 128h
Output Stream[2]: HdBAR + 148h
Output Stream[3]: HdBAR + 168h
Default Value: 00000000h Size: 32 bits
Bit Description
Cyclic Buffer Length—R/W. Indicates the number of bytes in the complete cyclic
buffer. This register represents an integer number of samples. Link Position in Buffer
will be reset when it reaches this value.
31:0 Software may only write to this register after Global Reset, Controller Reset, or Stream
Reset has occurred. This value should be only modified when the RUN bit is 0. Once the
RUN bit has been set to enable the engine, software must not write to this register until
after the next reset is asserted, or transfer may be corrupted.
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Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.40 SDLVI—Stream Descriptor Last Valid Index Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HdBAR + 8Ch Attribute: R/W
Input Stream[1]: HdBAR + ACh
Input Stream[2]: HdBAR + CCh
Input Stream[3]: HdBAR + ECh
Output Stream[0]: HdBAR + 10Ch
Output Stream[1]: HdBAR + 12Ch
Output Stream[2]: HdBAR + 14Ch
Output Stream[3]: HdBAR + 16Ch
Default Value: 0000h Size: 16 bits
Bit Description
15:8 Reserved
Last Valid Index—R/W. The value written to this register indicates the index for the
last valid Buffer Descriptor in BDL. After the controller has processed this descriptor, it
will wrap back to the first descriptor in the list and continue processing.
7:0
This field must be at least 1; that is, there must be at least 2 valid entries in the buffer
descriptor list before DMA operations can begin.
This value should only modified when the RUN bit is 0.
17.1.2.41 SDFIFOW—Stream Descriptor FIFO Watermark Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HdBAR + 8Eh Attribute:RO
Input Stream[1]: HdBAR + AEh
Input Stream[2]: HdBAR + CEh
Input Stream[3]: HdBAR + EEh
Output Stream[0]: HdBAR + 10Eh
Output Stream[1]: HdBAR + 12Eh
Output Stream[2]: HdBAR + 14Eh
Output Stream[3]: HdBAR + 16Eh
Default Value: 0004h Size: 16 bits
Bit Description
15:3 Reserved
FIFO Watermark (FIFOW)—RO. Indicates the minimum number of bytes
accumulated/free in the FIFO before the controller will start a fetch/eviction of data.
The HD Audio Controller hardwires the FIFO Watermark to either 32 B or 64 B based on
the number of bytes per frame for the configured input stream.
100 = 32 B (Default)
101 = 64 B
2:0
Others = Unsupported
NOTE: When the bit field is programmed to an unsupported size, the hardware sets
itself to the default value.
Software must read the bit field to test if the value is supported after setting the bit
field.
798 Datasheet
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.42 ISDFIFOS—Input Stream Descriptor FIFO Size Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HdBAR + 90h Attribute: RO
Input Stream[1]: HdBAR + B0h
Input Stream[2]: HdBAR + D0h
Input Stream[3]: HdBAR + F0h
Output Stream[0]: HdBAR + 110h
Output Stream[1]: HdBAR + 130h
Output Stream[2]: HdBAR + 150h
Output Stream[3]: HdBAR + 170h
Default Value: 0000h Size:16 bits
Bit Description
FIFO Size—RW. When GCAP2.EEACS = 0, indicates the maximum number of bytes
that could be evicted (for input) or fetched (for output) by the controller at one time.
This is the maximum number of bytes that may have been received into the HW buffer
but not yet transferred out, and is also the maximum possible value that the PICB
count will increase by at one time.
The FIFO size is calculated based on factors including the stream format programmed
in SDFMT register. As the default value is zero, SW must write to the respective SDFMT
15:0 register to kick of the FIFO size calculation, and read back to find out the HW allocated
FIFO size.
As the default value is zero, SW must write to the <I/O>SD<0:3>FMT register to kick
off the FIFO size calculation, and read back to find out the HW allocated FIFO size.
When GCAP2.EEACS = 1, this FIFOS value represent the minimum FIFO size HW
required to operate efficiently. Software can program FIFOL register to extend the
effective FIFO size in HW beyond this minimum value advertised. In this case, the
maximum number.
Datasheet 799
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.43 SDFMT—Stream Descriptor Format Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HdBAR + 92h Attribute: R/W
Input Stream[1]: HdBAR + B2h
Input Stream[2]: HdBAR + D2h
Input Stream[3]: HdBAR + F2h
Output Stream[0]: HdBAR + 112h
Output Stream[1]: HdBAR + 132h
Output Stream[2]: HdBAR + 152h
Output Stream[3]: HdBAR + 172h
Default Value: 0000h Size: 16 bits
Bit Description
15 Reserved
Sample Base Rate—R/W
14 0 = 48 kHz
1 = 44.1 kHz
Sample Base Rate Multiple—R/W
000 = 48 kHz, 44.1 kHz or less
001 = x2 (96 kHz, 88.2 kHz, 32 kHz)
13:11
010 = x3 (144 kHz)
011 = x4 (192 kHz, 176.4 kHz)
Others = Reserved.
Sample Base Rate Devisor—R/W.
000 = Divide by 1(48 kHz, 44.1 kHz)
001 = Divide by 2 (24 kHz, 22.05 kHz)
010 = Divide by 3 (16 kHz, 32 kHz)
10:8 011 = Divide by 4 (11.025 kHz)
100 = Divide by 5 (9.6 kHz)
101 = Divide by 6 (8 kHz)
110 = Divide by 7
111 = Divide by 8 (6 kHz)
7 Reserved
Bits per Sample (BITS)—R/W.
000 = 8 bits. The data will be packed in memory in 8-bit containers on 16-bit
boundaries
001 = 16 bits. The data will be packed in memory in 16-bit containers on 16-bit
boundaries
010 = 20 bits. The data will be packed in memory in 32-bit containers on 32-bit
6:4
boundaries
011 = 24 bits. The data will be packed in memory in 32-bit containers on 32-bit
boundaries
100 = 32 bits. The data will be packed in memory in 32-bit containers on 32-bit
boundaries
Others = Reserved.
Number of Channels (CHAN)—R/W. Indicates number of channels in each frame of the
stream.
0000 =1
3:0
0001 =2
........
1111 =16
800 Datasheet
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
17.1.2.44 SdBDPL—Stream Descriptor Buffer Descriptor List
Pointer Lower Base Address Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HdBAR + 98h Attribute: R/W,RO
Input Stream[1]: HdBAR + B8h
Input Stream[2]: HdBAR + D8h
Input Stream[3]: HdBAR + F8h
Output Stream[0]: HdBAR + 118h
Output Stream[1]: HdBAR + 138h
Output Stream[2]: HdBAR + 158h
Output Stream[3]: HdBAR + 178h
Default Value: 00000000h Size: 32 bits
Bit Description
Buffer Descriptor List Pointer Lower Base Address—R/W. Lower address of the
31:7 Buffer Descriptor List. This value should only be modified when the RUN bit is 0, or DMA
transfer may be corrupted.
6:0 Hardwired to 0 forcing alignment on 128-B boundaries.
17.1.2.45 SdBDPU—Stream Descriptor Buffer Descriptor List
Pointer Upper Base Address Register
(Intel® High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HdBAR + 9Ch Attribute:R/W
Input Stream[1]: HdBAR + BCh
Input Stream[2]: HdBAR + DCh
Input Stream[3]: HdBAR + FCh
Output Stream[0]: HdBAR + 11Ch
Output Stream[1]: HdBAR + 13Ch
Output Stream[2]: HdBAR + 15Ch
Output Stream[3]: HdBAR + 17Ch
Default Value: 00000000h Size: 32 bits
Bit Description
Buffer Descriptor List Pointer Upper Base Address—R/W. Upper 32-bit address of
31:0 the Buffer Descriptor List. This value should only be modified when the RUN bit is 0, or
DMA transfer may be corrupted.
§§
Datasheet 801
Integrated Intel® High Definition Audio (Intel® HD Audio) Controller Registers
802 Datasheet
SMBus Controller Registers (D31:F3)
18 SMBus Controller Registers
(D31:F3)
18.1 PCI Configuration Registers (SMBus—D31:F3)
Table 18-1. SMBus Controller PCI Register Address Map (SMBus—D31:F3)
Offset Mnemonic Register Name Default Attribute
00h–01h VID Vendor Identification 8086 RO
See register
02h–03h DID Device Identification RO
description
04h–05h PCICMD PCI Command 0000h R/W, RO
06h–07h PCISTS PCI Status 0280h RO
See register
08h RID Revision Identification RO
description
09h PI Programming Interface 00h RO
0Ah SCC Sub Class Code 05h RO
0Bh BCC Base Class Code 0Ch RO
Memory Base Address Register 0
10h SMBMBAR0 00000004h R/W, RO
(Bit 31:0)
Memory Based Address Register 1
14h SMBMBAR1 00000000h R/W
(Bit 63:32)
20h–23h SMB_BASE SMBus Base Address 00000001h R/W, RO
2Ch–2Dh SVID Subsystem Vendor Identification 0000h RO
2Eh–2Fh SID Subsystem Identification 0000h R/WO
3Ch INT_LN Interrupt Line 00h R/W
See register
3Dh INT_PN Interrupt Pin RO
description
40h HOSTC Host Configuration 00h R/W, R/WO
NOTE: Registers that are not shown should be treated as Reserved (See Section 9.2 for details).
18.1.1 VID—Vendor Identification Register (SMBus—D31:F3)
Address: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bits
Bit Description
15:0 Vendor ID—RO. This is a 16-bit value assigned to Intel
Datasheet 803
SMBus Controller Registers (D31:F3)
18.1.2 DID—Device Identification Register (SMBus—D31:F3)
Address: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bits
Bit Description
Device ID—RO. This is a 16-bit value assigned to the PCH SMBus controller. See
15:0
Section 1.3 for the value of the DID Register.
18.1.3 PCICMD—PCI Command Register (SMBus—D31:F3)
Address: 04h–05h Attributes: RO, R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved
Interrupt Disable—R/W.
10 0 = Enable
1 = Disables SMBus to assert its PIRQB# signal.
9 Fast Back to Back Enable (FBE)—RO. Hardwired to 0.
SERR# Enable (SERR_EN)—R/W.
8 0 = Enables SERR# generation.
1 = Disables SERR# generation.
7 Wait Cycle Control (WCC)—RO. Hardwired to 0.
Parity Error Response (PER)—R/W.
6 0 = Disable
1 = Sets Detected Parity Error bit (D31:F3:06, bit 15) when a parity error is detected.
5 VGA Palette Snoop (VPS)—RO. Hardwired to 0.
4 Postable Memory Write Enable (PMWE)—RO. Hardwired to 0.
3 Special Cycle Enable (SCE)—RO. Hardwired to 0.
2 Bus Master Enable (BME)—RO. Hardwired to 0.
Memory Space Enable (MSE)—R/W.
1 0 = Disables memory mapped config space.
1 = Enables memory mapped config space.
I/O Space Enable (IOSE)—R/W.
0 0 = Disable
1 = Enables access to the SMBus I/O space registers as defined by the Base Address
Register.
804 Datasheet
SMBus Controller Registers (D31:F3)
18.1.4 PCISTS—PCI Status Register (SMBus—D31:F3)
Address: 06h–07h Attributes: RO
Default Value: 0280h Size: 16 bits
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to
the bit has no effect.
Bit Description
Detected Parity Error (DPE)—R/WC.
15 0 = No parity error detected.
1 = Parity error detected.
Signaled System Error (SSE)—R/WC.
14 0 = No system error detected.
1 = System error detected.
13 Received Master Abort (RMA)—RO. Hardwired to 0.
12 Received Target Abort (RTA)—RO. Hardwired to 0.
11 Signaled Target Abort (STA)—RO. Hardwired to 0.
DEVSEL# Timing Status (DEVT)—RO. This 2-bit field defines the timing for DEVSEL#
10:9 assertion for positive decode.
01 = Medium timing.
8 Data Parity Error Detected (DPED)—RO. Hardwired to 0.
7 Fast Back to Back Capable (FB2BC)—RO. Hardwired to 1.
6 User Definable Features (UDF)—RO. Hardwired to 0.
5 66 MHz Capable (66MHZ_CAP)—RO. Hardwired to 0.
Capabilities List (CAP_LIST)—RO. Hardwired to 0 because there are no capability list
4
structures in this function
Interrupt Status (INTS)—RO. This bit indicates that an interrupt is pending. It is
3
independent from the state of the Interrupt Enable bit in the PCI Command register.
2:0 Reserved
18.1.5 RID—Revision Identification Register (SMBus—D31:F3)
Offset Address: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
Bit Description
Revision ID—RO. This field indicates the device specific revision identifier. See
7:0
Section 1.3 the value of the RID Register.
Datasheet 805
SMBus Controller Registers (D31:F3)
18.1.6 PI—Programming Interface Register (SMBus—D31:F3)
Offset Address: 09h Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
7:0 Reserved
18.1.7 SCC—Sub Class Code Register (SMBus—D31:F3)
Address Offset: 0Ah Attributes: RO
Default Value: 05h Size: 8 bits
Bit Description
Sub Class Code (SCC)—RO.
7:0
05h = SMBus serial controller
18.1.8 BCC—Base Class Code Register (SMBus—D31:F3)
Address Offset: 0Bh Attributes: RO
Default Value: 0Ch Size: 8 bits
Bit Description
Base Class Code (BCC)—RO.
7:0
0Ch = Serial controller.
18.1.9 SMBMBAR0—D31_F3_SMBus Memory Base Address 0
Register (SMBus—D31:F3)
Address Offset: 10–13h Attributes: R/W, RO
Default Value: 00000004h Size: 32 bits
Bit Description
Base Address—R/W. Provides the 32 byte system memory base address for the PCH
31:8
SMB logic.
7:4 Reserved
3 Prefetchable (PREF)—RO. Hardwired to 0. Indicates that SMBMBAR is not pre-fetchable.
Address Range (ADDRNG)—RO. Indicates that this SMBMBAR can be located
2:1
anywhere in 64 bit address space. Hardwired to 10b.
Memory Space Indicator—RO. This read-only bit always is 0, indicating that the SMB
0
logic is Memory mapped.
806 Datasheet
SMBus Controller Registers (D31:F3)
18.1.10 SMBMBAR1—D31_F3_SMBus Memory Base Address 1
Register (SMBus—D31:F3)
Address Offset: 14h–17h Attributes: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Base Address—R/W. Provides bits 63:32 system memory base address for the PCH
31:0
SMB logic.
18.1.11 SMB_BASE—SMBus Base Address Register
(SMBus—D31:F3)
Address Offset: 20–23h Attribute: R/W, RO
Default Value: 00000001h Size: 32-bits
Bit Description
31:16 Reserved—RO
Base Address—R/W. This field provides the 32-byte system I/O base address for the
15:5
PCH’s SMB logic.
4:1 Reserved—RO
0 IO Space Indicator—RO. Hardwired to 1 indicating that the SMB logic is I/O mapped.
18.1.12 SVID—Subsystem Vendor Identification Register
(SMBus—D31:F2/F4)
Address Offset: 2Ch–2Dh Attribute: RO
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Core
Bit Description
Subsystem Vendor ID (SVID)—RO. The SVID register, in combination with the
Subsystem ID (SID) register, enables the operating system (OS) to distinguish
subsystems from each other. The value returned by reads to this register is the same as
15:0
that which was written by BIOS into the IDE SVID register.
NOTE: Software can write to this register only once per core well reset. Writes should
be done as a single 16-bit cycle.
Datasheet 807
SMBus Controller Registers (D31:F3)
18.1.13 SID—Subsystem Identification Register
(SMBus—D31:F2/F4)
Address Offset: 2Eh–2Fh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Core
Bit Description
Subsystem ID (SID)—R/WO. The SID register, in combination with the SVID register,
enables the operating system (OS) to distinguish subsystems from each other. The
value returned by reads to this register is the same as that which was written by BIOS
15:0 into the IDE SID register.
NOTE: Software can write to this register only once per core well reset. Writes should
be done as a single 16-bit cycle.
18.1.14 INT_LN—Interrupt Line Register (SMBus—D31:F3)
Address Offset: 3Ch Attributes: R/W
Default Value: 00h Size: 8 bits
Bit Description
Interrupt Line (INT_LN)—R/W. This data is not used by the PCH. It is to
7:0 communicate to software the interrupt line that the interrupt pin is connected to
PIRQB#.
18.1.15 INT_PN—Interrupt Pin Register (SMBus—D31:F3)
Address Offset: 3Dh Attributes: RO
Default Value: See description Size: 8 bits
Bit Description
Interrupt PIN (INT_PN)—RO. This reflects the value of D31IP.SMIP in chipset
7:0
configuration space.
808 Datasheet
SMBus Controller Registers (D31:F3)
18.1.16 HOSTC—Host Configuration Register (SMBus—D31:F3)
Address Offset: 40h Attribute: R/W, R/WO
Default Value: 00h Size: 8 bits
Bit Description
7:5 Reserved
SPD Write Disable—R/WO.
0 = SPD write enabled.
1 = SPD write disabled. Writes to SMBus addresses 50h - 57h are disabled.
4 NOTE: This bit is R/WO and will be reset on PLTRST# assertion. This bit should be set
by BIOS to ‘1’. SW can only program this bit when both the START bit
(SMB_BASE + 02h, bit 6) and Host Busy bit (SMB_BASE + 00h, bit 0) are ‘0’;
otherwise the write may result in undefined behavior.
Soft SMBus Reset (SSRESET)—R/W.
3 0 = The HW will reset this bit to 0 when SMBus reset operation is completed.
1 = The SMBus state machine and logic in the PCH is reset.
I2C_EN—R/W.
0 = SMBus behavior.
2
1 = The PCH is enabled to communicate with I2C devices. This will change the
formatting of some commands.
SMB_SMI_EN—R/W.
0 = SMBus interrupts will not generate an SMI#.
1 1 = Any source of an SMB interrupt will instead be routed to generate an SMI#. Refer
to Section 5.22.4 (Interrupts / SMI#).
This bit needs to be set for SMBALERT# to be enabled.
SMBus Host Enable (HST_EN)—R/W.
0 = Disable the SMBus Host controller.
0 1 = Enable. The SMB Host controller interface is enabled to execute commands. The
INTREN bit (offset SMB_BASE + 02h, bit 0) needs to be enabled for the SMB Host
controller to interrupt or SMI#. The SMB Host controller will not respond to any
new requests until all interrupt requests have been cleared.
Datasheet 809
SMBus Controller Registers (D31:F3)
18.2 SMBus I/O and Memory Mapped I/O Registers
The SMBus registers (see Table 18-2) can be accessed through I/O BAR or Memory BAR
registers in PCI configuration space. The offsets are the same for both I/O and Memory
Mapped I/O registers.
Table 18-2. SMBus I/O and Memory Mapped I/O Register Address Map
SMB_BASE
Mnemonic Register Name Default Attribute
+ Offset
00h HST_STS Host Status 00h R/WC, RO
02h HST_CNT Host Control 00h R/W, WO
03h HST_CMD Host Command 00h R/W
04h XMIT_SLVA Transmit Slave Address 00h R/W
05h HST_D0 Host Data 0 00h R/W
06h HST_D1 Host Data 1 00h R/W
07h HOST_BLOCK_dB Host Block Data Byte 00h R/W
08h PEC Packet Error Check 00h R/W
09h RCV_SLVA Receive Slave Address 44h R/W
0Ah–0Bh SLV_DATA Receive Slave Data 0000h RO
0Ch AUX_STS Auxiliary Status 00h R/WC, RO
0Dh AUX_CTL Auxiliary Control 00h R/W
SMLink Pin Control (TCO See register
0Eh SMLINK_PIN_CTL R/W, RO
Compatible Mode) description
See register
0Fh SMBus_PIN_CTL SMBus Pin Control R/W, RO
description
10h SLV_STS Slave Status 00h R/WC
11h SLV_CMD Slave Command 00h R/W
14h NOTIFY_DADDR Notify Device Address 00h RO
16h NOTIFY_DLOW Notify Data Low Byte 00h RO
17h NOTIFY_DHIGH Notify Data High Byte 00h RO
810 Datasheet
SMBus Controller Registers (D31:F3)
18.2.1 HST_STS—Host Status Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 00h Attribute: R/WC, RO
Default Value: 00h Size: 8-bits
All status bits are set by hardware and cleared by the software writing a one to the
particular bit position. Writing a 0 to any bit position has no effect.
Bit Description
Byte Done Status (DS)—R/WC.
0 = Software can clear this by writing a 1 to it.
1 = Host controller received a byte (for Block Read commands) or if it has completed
transmission of a byte (for Block Write commands) when the 32-byte buffer is not
being used. This bit will be set, even on the last byte of the transfer. This bit is not
set when transmission is due to the LAN interface heartbeat.
This bit has no meaning for block transfers when the 32-byte buffer is enabled.
7 NOTE: When the last byte of a block message is received, the host controller will set
this bit. However, it will not immediately set the INTR bit (bit 1 in this register).
When the interrupt handler clears the DS bit, the message is considered
complete, and the host controller will then set the INTR bit (and generate
another interrupt). Thus, for a block message of n bytes, the PCH will generate
n+1 interrupts. The interrupt handler needs to be implemented to handle these
cases. When not using the 32 Byte Buffer, hardware will drive the SMBCLK signal
low when the DS bit is set until SW clears the bit. This includes the last byte of a
transfer. Software must clear the DS bit before it can clear the BUSY bit.
INUSE_STS—R/W. This bit is used as semaphore among various independent software
threads that may need to use the PCH’s SMBus logic, and has no other effect on
hardware.
6 0 = After a full PCI reset, a read to this bit returns a 0.
1 = After the first read, subsequent reads will return a 1. A write of a 1 to this bit will
reset the next read value to 0. Writing a 0 to this bit has no effect. Software can poll
this bit until it reads a 0, and will then own the usage of the host controller.
SMBALERT_STS—R/WC.
0 = Interrupt or SMI# was not generated by SMBALERT#. Software clears this bit by
writing a 1 to it.
5
1 = The source of the interrupt or SMI# was the SMBALERT# signal. This bit is only
cleared by software writing a 1 to the bit position or by RSMRST# going low.
If the signal is programmed as a GPIO, then this bit will never be set.
FAILED—R/WC.
4 0 = Software clears this bit by writing a 1 to it.
1 = The source of the interrupt or SMI# was a failed bus transaction. This bit is set in
response to the KILL bit being set to terminate the host transaction.
BUS_ERR—R/WC.
3 0 = Software clears this bit by writing a 1 to it.
1 = The source of the interrupt of SMI# was a transaction collision.
DEV_ERR—R/WC.
0 = Software clears this bit by writing a 1 to it. The PCH will then de-assert the interrupt
or SMI#.
2 1 = The source of the interrupt or SMI# was due to one of the following:
• Invalid Command Field,
• Unclaimed Cycle (host initiated),
• Host Device Time-out Error.
Datasheet 811
SMBus Controller Registers (D31:F3)
Bit Description
INTR—R/WC. This bit can only be set by termination of a command. INTR is not
dependent on the INTREN bit (offset SMB_BASE + 02h, bit 0) of the Host controller
register (offset 02h). It is only dependent on the termination of the command. If the
INTREN bit is not set, then the INTR bit will be set, although the interrupt will not be
1 generated. Software can poll the INTR bit in this non-interrupt case.
0 = Software clears this bit by writing a 1 to it. The PCH then de-asserts the interrupt or
SMI#.
1 = The source of the interrupt or SMI# was the successful completion of its last
command.
HOST_BUSY—R/WC.
0 = Cleared by the PCH when the current transaction is completed.
1 = Indicates that the PCH is running a command from the host interface. No SMB
registers should be accessed while this bit is set, except the BLOCK DATA BYTE
0
Register. The BLOCK DATA BYTE Register can be accessed when this bit is set only
when the SMB_CMD bits in the Host Control Register are programmed for Block
command or I2C Read command. This is necessary in order to check the DONE_STS
bit.
18.2.2 HST_CNT—Host Control Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 02h Attribute: R/W, WO
Default Value: 00h Size: 8-bits
Note: A read to this register will clear the byte pointer of the 32-byte buffer.
Bit Description
PEC_EN—R/W.
0 = SMBus host controller does not perform the transaction with the PEC phase
appended.
7 1 = Causes the host controller to perform the SMBus transaction with the Packet Error
Checking phase appended. For writes, the value of the PEC byte is transferred from
the PEC Register. For reads, the PEC byte is loaded in to the PEC Register. This bit
must be written prior to the write in which the START bit is set.
START—WO.
0 = This bit will always return 0 on reads. The HOST_BUSY bit in the Host Status
register (offset 00h) can be used to identify when the PCH has finished the
6
command.
1 = Writing a 1 to this bit initiates the command described in the SMB_CMD field. All
registers should be setup prior to writing a 1 to this bit position.
LAST_BYTE—WO. This bit is used for Block Read commands.
1 = Software sets this bit to indicate that the next byte will be the last byte to be
received for the block. This causes the PCH to send a NACK (instead of an ACK)
after receiving the last byte.
5
NOTE: Once the SECOND_TO_STS bit in TCO2_STS register (D31:F0, TCOBASE+6h,
bit 1) is set, the LAST_BYTE bit also gets set. While the SECOND_TO_STS bit is
set, the LAST_BYTE bit cannot be cleared. This prevents the PCH from running
some of the SMBus commands (Block Read/Write, I2C Read, Block I2C Write).
812 Datasheet
SMBus Controller Registers (D31:F3)
Bit Description
SMB_CMD—R/W. The bit encoding below indicates which command the PCH is to
perform. If enabled, the PCH will generate an interrupt or SMI# when the command
has completed If the value is for a non-supported or reserved command, the PCH will
set the device error (DEV_ERR) status bit (offset SMB_BASE + 00h, bit 2) and generate
an interrupt when the START bit is set. The PCH will perform no command, and will not
operate until DEV_ERR is cleared.
000 = Quick: The slave address and read/write value (bit 0) are stored in the transmit
slave address register.
001 = Byte: This command uses the transmit slave address and command registers.
Bit 0 of the slave address register determines if this is a read or write
command.
010 = Byte Data: This command uses the transmit slave address, command, and
DATA0 registers. Bit 0 of the slave address register determines if this is a read
or write command. If it is a read, the DATA0 register will contain the read data.
011 = Word Data: This command uses the transmit slave address, command, DATA0
and DATA1 registers. Bit 0 of the slave address register determines if this is a
read or write command. If it is a read, after the command completes, the
DATA0 and DATA1 registers will contain the read data.
100 = Process Call: This command uses the transmit slave address, command, DATA0
and DATA1 registers. Bit 0 of the slave address register determines if this is a
4:2 read or write command. After the command completes, the DATA0 and DATA1
registers will contain the read data.
101 = Block: This command uses the transmit slave address, command, DATA0
registers, and the Block Data Byte register. For block write, the count is stored
in the DATA0 register and indicates how many bytes of data will be transferred.
For block reads, the count is received and stored in the DATA0 register. Bit 0 of
the slave address register selects if this is a read or write command. For writes,
data is retrieved from the first n (where n is equal to the specified count)
addresses of the SRAM array. For reads, the data is stored in the Block Data
Byte register.
110 = I2C Read: This command uses the transmit slave address, command, DATA0,
DATA1 registers, and the Block Data Byte register. The read data is stored in
the Block Data Byte register. The PCH continues reading data until the NAK is
received.
111 = Block Process: This command uses the transmit slave address, command,
DATA0 and the Block Data Byte register. For block write, the count is stored in
the DATA0 register and indicates how many bytes of data will be transferred.
For block read, the count is received and stored in the DATA0 register. Bit 0 of
the slave address register always indicate a write command. For writes, data is
retrieved from the first m (where m is equal to the specified count) addresses
of the SRAM array. For reads, the data is stored in the Block Data Byte register.
NOTE: E32B bit in the Auxiliary Control register must be set for this command to work.
KILL—R/W.
0 = Normal SMBus host controller functionality.
1 1 = Kills the current host transaction taking place, sets the FAILED status bit, and
asserts the interrupt (or SMI#). This bit, once set, must be cleared by software to
allow the SMBus host controller to function normally.
INTREN—R/W.
0 0 = Disable.
1 = Enable the generation of an interrupt or SMI# upon the completion of the
command.
Datasheet 813
SMBus Controller Registers (D31:F3)
18.2.3 HST_CMD—Host Command Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 03h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
This 8-bit field is transmitted by the host controller in the command field of the SMBus
7:0
protocol during the execution of any command.
18.2.4 XMIT_SLVA—Transmit Slave Address Register
(SMBus—D31:F3)
Register Offset: SMB_BASE + 04h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is transmitted by the host controller in the slave address field of the
SMBus protocol.
Bit Description
7:1 Address—R/W. This field provides a 7-bit address of the targeted slave.
RW—R/W. Direction of the host transfer.
0 = Write
0 1 = Read
NOTE: Writes to SMBus addresses 50h - 57h are disabled depending on the setting of
bit 4 in HOSTC register (D31:F3:Offset 40h).
18.2.5 HST_D0—Host Data 0 Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 05h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Data0/Count—R/W. This field contains the 8-bit data sent in the DATA0 field of the
SMBus protocol. For block write commands, this register reflects the number of bytes to
7:0 transfer. This register should be programmed to a value between 1 and 32 for block
counts. A count of 0 or a count above 32 will result in unpredictable behavior. The host
controller does not check or log invalid block counts.
18.2.6 HST_D1—Host Data 1 Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 06h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Data1—R/W. This 8-bit register is transmitted in the DATA1 field of the SMBus protocol
7:0
during the execution of any command.
814 Datasheet
SMBus Controller Registers (D31:F3)
18.2.7 Host_BLOCK_dB—Host Block Data Byte Register
(SMBus—D31:F3)
Register Offset: SMB_BASE + 07h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Block Data (BDTA)—R/W. This is either a register, or a pointer into a 32-byte block
array, depending upon whether the E32B bit is set in the Auxiliary Control register.
When the E32B bit (offset SMB_BASE + 0Dh, bit 1) is cleared, this is a register
containing a byte of data to be sent on a block write or read from on a block read.
When the E32B bit is set, reads and writes to this register are used to access the 32-
byte block data storage array. An internal index pointer is used to address the array,
which is reset to 0 by reading the HCTL register (offset 02h). The index pointer then
increments automatically upon each access to this register. The transfer of block data
into (read) or out of (write) this storage array during an SMBus transaction always
starts at index address 0.
When the E2B bit is set, for writes, software will write up to 32-bytes to this register as
part of the setup for the command. After the Host controller has sent the Address,
Command, and Byte Count fields, it will send the bytes in the SRAM pointed to by this
register.
7:0
When the E2B bit is cleared for writes, software will place a single byte in this register.
After the host controller has sent the address, command, and byte count fields, it will
send the byte in this register. If there is more data to send, software will write the next
series of bytes to the SRAM pointed to by this register and clear the DONE_STS bit. The
controller will then send the next byte. During the time between the last byte being
transmitted to the next byte being transmitted, the controller will insert wait-states on
the interface.
When the E2B bit is set for reads, after receiving the byte count into the Data0 register,
the first series of data bytes go into the SRAM pointed to by this register. If the byte
count has been exhausted or the 32-byte SRAM has been filled, the controller will
generate an SMI# or interrupt (depending on configuration) and set the DONE_STS bit.
Software will then read the data. During the time between when the last byte is read
from the SRAM to when the DONE_STS bit is cleared, the controller will insert wait-
states on the interface.
18.2.8 PEC—Packet Error Check (PEC) Register
(SMBus—D31:F3)
Register Offset: SMB_BASE + 08h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
PEC_DATA—R/W. This 8-bit register is written with the 8-bit CRC value that is used as
the SMBus PEC data prior to a write transaction. For read transactions, the PEC data is
7:0 loaded from the SMBus into this register and is then read by software. Software must
ensure that the INUSE_STS bit is properly maintained to avoid having this field over-
written by a write transaction following a read transaction.
Datasheet 815
SMBus Controller Registers (D31:F3)
18.2.9 RCV_SLVA—Receive Slave Address Register
(SMBus—D31:F3)
Register Offset: SMB_BASE + 09h Attribute: R/W
Default Value: 44h Size: 8 bits
Lockable: No Power Well: Resume
Bit Description
7 Reserved
SLAVE_ADDR—R/W. This field is the slave address that the PCH decodes for read and
write cycles. the default is not 0, so the SMBus Slave Interface can respond even before
6:0
the processor comes up (or if the processor is dead). This register is cleared by
RSMRST#, but not by PLTRST#.
18.2.10 SLV_DATA—Receive Slave Data Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 0Ah–0Bh Attribute: RO
Default Value: 0000h Size: 16 bits
Lockable: No Power Well: Resume
This register contains the 16-bit data value written by the external SMBus master. The
processor can then read the value from this register. This register is reset by RSMRST#,
but not PLTRST#.
Bit Description
Data Message Byte 1 (DATA_MSG1)—RO. See Section 5.22.7 for a discussion of this
15:8
field.
Data Message Byte 0 (DATA_MSG0)—RO. See Section 5.22.7 for a discussion of
7:0
this field.
18.2.11 AUX_STS—Auxiliary Status Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 0Ch Attribute: R/WC, RO
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Resume
Bit Description
7:2 Reserved
SMBus TCO Mode (STCO)—RO. This bit reflects the strap setting of TCO compatible
mode versus Advanced TCO mode.
1
0 = The PCH is in the compatible TCO mode.
1 = The PCH is in the advanced TCO mode.
CRC Error (CRCE)—R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set if a received message contained a CRC error. When this bit is set, the
0 DERR bit of the host status register will also be set. This bit will be set by the
controller if a software abort occurs in the middle of the CRC portion of the cycle or
an abort happens after the PCH has received the final data bit transmitted by an
external slave.
816 Datasheet
SMBus Controller Registers (D31:F3)
18.2.12 AUX_CTL—Auxiliary Control Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 0Dh Attribute: R/W
Default Value: 00h Size: 8 bits
Lockable: No Power Well: Resume
Bit Description
7:2 Reserved
Enable 32-Byte Buffer (E32B)—R/W.
0 = Disable.
1 1 = Enable. When set, the Host Block Data register is a pointer into a 32-byte buffer, as
opposed to a single register. This enables the block commands to transfer or receive
up to 32-bytes before the PCH generates an interrupt.
Automatically Append CRC (AAC)—R/W.
0 = The PCH will Not automatically append the CRC.
0 1 = The PCH will automatically append the CRC. This bit must not be changed during
SMBus transactions or undetermined behavior will result. It should be programmed
only once during the lifetime of the function.
18.2.13 SMLINK_PIN_CTL—SMLink Pin Control Register
(SMBus—D31:F3)
Register Offset: SMB_BASE + 0Eh Attribute: R/W, RO
Default Value: See Description Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
This register is only applicable in the TCO compatible mode.
Bit Description
7:3 Reserved
SMLINK_CLK_CTL—R/W.
0 = The PCH will drive the SMLink0 pin low, independent of what the other SMLink logic
2 would otherwise indicate for the SMLink0 pin.
1 = The SMLink0 pin is not overdriven low. The other SMLink logic controls the state of
the pin. (Default)
SMLINK1_CUR_STS—RO. This read-only bit has a default value that is dependent on
an external signal level. This pin returns the value on the SMLink1 pin. This allows
1 software to read the current state of the pin.
0 = Low
1 = High
SMLINK0_CUR_STS—RO. This read-only bit has a default value that is dependent on
an external signal level. This pin returns the value on the SMLink0 pin. This allows
0 software to read the current state of the pin.
0 = Low
1 = High
Datasheet 817
SMBus Controller Registers (D31:F3)
18.2.14 SMBus_PIN_CTL—SMBus Pin Control Register
(SMBus—D31:F3)
Register Offset: SMB_BASE + 0Fh Attribute: R/W, RO
Default Value: See Description Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit Description
7:3 Reserved
SMBCLK_CTL—R/W.
1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of
2 the pin.
0 = The PCH drives the SMBCLK pin low, independent of what the other SMB logic
would otherwise indicate for the SMBCLK pin. (Default)
SMBDATA_CUR_STS—RO. This read-only bit has a default value that is dependent on
an external signal level. This pin returns the value on the SMBDATA pin. This allows
1 software to read the current state of the pin.
0 = Low
1 = High
SMBCLK_CUR_STS—RO. This read-only bit has a default value that is dependent on
an external signal level. This pin returns the value on the SMBCLK pin. This allows
0 software to read the current state of the pin.
0 = Low
1 = High
18.2.15 SLV_STS—Slave Status Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 10h Attribute: R/WC
Default Value: 00h Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
All bits in this register are implemented in the 64 kHz clock domain. Therefore,
software must poll this register until a write takes effect before assuming that a write
has completed internally.
Bit Description
7:1 Reserved
HOST_NOTIFY_STS—R/WC. The PCH sets this bit to a 1 when it has completely
received a successful Host Notify Command on the SMBus pins. Software reads this bit
to determine that the source of the interrupt or SMI# was the reception of the Host
Notify Command. Software clears this bit after reading any information needed from
0
the Notify address and data registers by writing a 1 to this bit. The PCH will allow the
Notify Address and Data registers to be over-written once this bit has been cleared.
When this bit is 1, the PCH will NACK the first byte (host address) of any new “Host
Notify” commands on the SMBus pins. Writing a 0 to this bit has no effect.
818 Datasheet
SMBus Controller Registers (D31:F3)
18.2.16 SLV_CMD—Slave Command Register (SMBus—D31:F3)
Register Offset: SMB_BASE + 11h Attribute: R/W
Default Value: 00h Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit Description
7:2 Reserved
SMBALERT_DIS—R/W.
0 = Allows the generation of the interrupt or SMI#.
1 = Software sets this bit to block the generation of the interrupt or SMI# due to the
2 SMBALERT# source. This bit is logically inverted and ANDed with the
SMBALERT_STS bit (offset SMB_BASE + 00h, bit 5). The resulting signal is
distributed to the SMI# and/or interrupt generation logic. This bit does not effect
the wake logic.
HOST_NOTIFY_WKEN—R/W. Software sets this bit to 1 to enable the reception of a
Host Notify command as a wake event. When enabled this event is “OR’d" in with the
other SMBus wake events and is reflected in the SMB_WAK_STS bit of the General
1
Purpose Event 0 Status register.
0 = Disable
1 = Enable
HOST_NOTIFY_INTREN—R/W. Software sets this bit to 1 to enable the generation of
interrupt or SMI# when HOST_NOTIFY_STS (offset SMB_BASE + 10h, bit 0) is 1. This
enable does not affect the setting of the HOST_NOTIFY_STS bit. When the interrupt is
generated, either PIRQB# or SMI# is generated, depending on the value of the
0 SMB_SMI_EN bit (D31:F3:40h, bit 1). If the HOST_NOTIFY_STS bit is set when this bit
is written to a 1, then the interrupt (or SMI#) will be generated. The interrupt (or
SMI#) is logically generated by AND’ing the STS and INTREN bits.
0 = Disable
1 = Enable
18.2.17 NOTIFY_DADDR—Notify Device Address Register
(SMBus—D31:F3)
Register Offset: SMB_BASE + 14h Attribute: RO
Default Value: 00h Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit Description
DEVICE_ADDRESS—RO. This field contains the 7-bit device address received during
the Host Notify protocol of the SMBus 2.0 Specification. Software should only consider
7:1
this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMB_BASE +10, bit 0) is set
to 1.
0 Reserved
Datasheet 819
SMBus Controller Registers (D31:F3)
18.2.18 NOTIFY_DLOW—Notify Data Low Byte Register
(SMBus—D31:F3)
Register Offset: SMB_BASE + 16h Attribute: RO
Default Value: 00h Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit Description
DATA_LOW_BYTE—RO. This field contains the first (low) byte of data received during
the Host Notify protocol of the SMBus 2.0 specification. Software should only consider
7:0
this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMB_BASE +10, bit 0) is set
to 1.
18.2.19 NOTIFY_DHIGH—Notify Data High Byte Register
(SMBus—D31:F3)
Register Offset: SMB_BASE + 17h Attribute: RO
Default Value: 00h Size: 8 bits
Note: This register is in the resume well and is reset by RSMRST#.
Bit Description
DATA_HIGH_BYTE—RO. This field contains the second (high) byte of data received
during the Host Notify protocol of the SMBus 2.0 specification. Software should only
7:0
consider this field valid when the HOST_NOTIFY_STS bit (D31:F3:SMB_BASE +10, bit
0) is set to 1.
§§
820 Datasheet
PCI Express* Configuration Registers
19 PCI Express* Configuration
Registers
19.1 PCI Express* Configuration Registers
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Note: This section assumes the default PCI Express Function Number-to-Root Port mapping is
used. Function numbers for a given root port are assignable through the Root Port
Function Number and Hide for PCI Express Root Ports register (RCBA+0404h).
Note: Register address locations that are not shown in Table 19-1 should be treated as
Reserved.
Table 19-1. PCI Express* Configuration Registers Address Map
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) (Sheet 1 of 3)
Function 0–7
Offset Mnemonic Register Name Attribute
Default
00h–01h VID Vendor Identification 8086h RO
See register
02h–03h DID Device Identification RO
description
04h–05h PCICMD PCI Command 0000h R/W, RO
06h–07h PCISTS PCI Status 0010h R/WC, RO
See register
08h RID Revision Identification RO
description
09h PI Programming Interface 00h RO
0Ah SCC Sub Class Code 04h RO
0Bh BCC Base Class Code 06h RO
0Ch CLS Cache Line Size 00h R/W
0Dh PLT Primary Latency Timer 00h RO
0Eh HEADTYP Header Type 81h RO
18h–1Ah BNUM Bus Number 000000h R/W
1Bh SLT Secondary Latency Timer 00h RO
1Ch–1Dh IOBL I/O Base and Limit 0000h R/W, RO
1Eh–1Fh SSTS Secondary Status Register 0000h R/WC
20h–23h MBL Memory Base and Limit 00000000h R/W
24h–27h PMBL Prefetchable Memory Base and Limit 00010001h R/W, RO
Prefetchable Memory Base Upper 32
28h–2Bh PMBU32 00000000h R/W
Bits
Prefetchable Memory Limit Upper 32
2Ch–2Fh PMLU32 00000000h R/W
Bits
34h CAPP Capabilities List Pointer 40h RO
See bit
3Ch–3Dh INTR Interrupt Information R/W, RO
description
3Eh–3Fh BCTRL Bridge Control Register 0000h R/W
Datasheet 821
PCI Express* Configuration Registers
Table 19-1. PCI Express* Configuration Registers Address Map
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) (Sheet 2 of 3)
Function 0–7
Offset Mnemonic Register Name Attribute
Default
40h–41h CLIST Capabilities List 8010h RO
42h–43h XCAP PCI Express* Capabilities 0042h R/WO, RO
44h–47h DCAP Device Capabilities 00008000h RO
48h–49h DCTL Device Control 0000h R/W, RO
4Ah–4Bh DSTS Device Status 0010h R/WC, RO
See bit
4Ch–4Fh LCAP Link Capabilities RO, R/WO
description
50h–51h LCTL Link Control 0000h R/W, RO
See bit
52h–53h LSTS Link Status RO
description
54h–57h SLCAP Slot Capabilities Register 00060060h R/WO, RO
58h–59h SLCTL Slot Control 0000h R/W, RO
5Ah–5Bh SLSTS Slot Status 0000h R/WC, RO
5Ch–5Dh RCTL Root Control 0000h R/W
60h–63h RSTS Root Status 00000000h R/WC, RO
64h–67h DCAP2 Device Capabilities 2 Register 00080816h R/WO,RO
68h–69h DCTL2 Device Control 2 Register 0000h R/W, RO
70h–71h LCTL2 Link Control 2 Register 0002h R/W
72h–73h LSTS2 Link Status 2 Register 0000h RO
80h–81h MID Message Signaled Interrupt Identifiers 9005h RO
Message Signaled Interrupt Message
82h–83h MC 0000h R/W, RO
Control
Message Signaled Interrupt Message
84h–87h MA 00000000h R/W
Address
Message Signaled Interrupt Message
88h–89h MD 0000h R/W
Data
90h–91h SVCAP Subsystem Vendor Capability A00Dh R/WO,RO
94h–97h SVID Subsystem Vendor Identification 00000000h R/WO
A0h–A1h PMCAP Power Management Capability 0001h RO
A2h–A3h PMC PCI Power Management Capability C803h RO
PCI Power Management Control and
A4h–A7h PMCS 00000000h R/W, RO
Status
D4h–D7h MPC2 Miscellaneous Port Configuration 2 00000800h R/W, RO
R/W, RO,
D8h–dBh MPC Miscellaneous Port Configuration 09110000h
R/WO
DCh–DFh SMSCS SMI/SCI Status Register 00000000h R/WC
E1h RPDCGEN Rort Port Dynamic Clock Gating Enable 00h R/W
ECh–EFh PECR3 PCI Express Configuration Register 3 00000000h R/W
See bit
104h–107h UES Uncorrectable Error Status R/WC, RO
description
108h–10Bh UEM Uncorrectable Error Mask 00000000h R/WO, RO
822 Datasheet
PCI Express* Configuration Registers
Table 19-1. PCI Express* Configuration Registers Address Map
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7) (Sheet 3 of 3)
Function 0–7
Offset Mnemonic Register Name Attribute
Default
10Ch–10Fh UEV Uncorrectable Error Severity 00060011h RO
110h–113h CES Correctable Error Status 00000000h R/WC
114h–117h CEM Correctable Error Mask 00002000h R/WO
Advanced Error Capabilities and
118h–11Bh AECC 00000000h RO
Control
130h–133h RES Root Error Status 00000000h R/WC, RO
320h–323h PECR2 PCI Express Configuration Register 2 0004B05Bh R/W
PCI Express Extended Test Mode See bit
324h–327h PEETM RO
Register description
330h–333h PEC1 PCI Express Configuration Register 1 28000016h RO, R/W
19.1.1 VID—Vendor Identification Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bits
Bit Description
15:0 Vendor ID—RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
19.1.2 DID—Device Identification Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 02h–03h Attribute: RO
Default Value: Port 1= Bit Description Size: 16 bits
Port 2= Bit Description
Port 3= Bit Description
Port 4= Bit Description
Port 5= Bit Description
Port 6= Bit Description
Port 7= Bit Description
Port 8= Bit Description
Bit Description
Device ID—RO. This is a 16-bit value assigned to the PCH’s PCI Express controller. See
15:0
Section 1.3 for the value of the DID Register.
Datasheet 823
PCI Express* Configuration Registers
19.1.3 PCICMD—PCI Command Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 04h–05h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved
Interrupt Disable—R/W. This disables pin-based INTx# interrupts on enabled Hot-Plug
and power management events. This bit has no effect on MSI operation.
0 = Internal INTx# messages are generated if there is an interrupt for Hot-Plug or
power management and MSI is not enabled.
10 1 = Internal INTx# messages will not be generated.
This bit does not affect interrupt forwarding from devices connected to the root port.
Assert_INTx and Deassert_INTx messages will still be forwarded to the internal
interrupt controllers if this bit is set.
9 Fast Back to Back Enable (FBE)—Reserved per the PCI Express* Base Specification.
SERR# Enable (SEE)—R/W.
8 0 = Disable.
1 = Enables the root port to generate an SERR# message when PSTS.SSE is set.
7 Wait Cycle Control (WCC)—Reserved per the PCI Express Base Specification.
Parity Error Response (PER)—R/W.
0 = Disable.
6
1 = Indicates that the device is capable of reporting parity errors as a master on the
backbone.
5 VGA Palette Snoop (VPS)—Reserved per the PCI Express* Base Specification.
Postable Memory Write Enable (PMWE)—Reserved per the PCI Express* Base
4
Specification.
3 Special Cycle Enable (SCE)—Reserved per the PCI Express* Base Specification.
Bus Master Enable (BME)—R/W.
0 = Disable. Memory and I/O requests received at a Root Port must be handled as
Unsupported Requests.
1 = Enable. Allows the root port to forward Memory and I/O Read/Write cycles onto the
2 backbone from a PCI Express* device.
NOTE: This bit does not affect forwarding of completions in either upstream or
downstream direction nor controls forwarding of requests other than memory or
I/O
Memory Space Enable (MSE)—R/W.
0 = Disable. Memory cycles within the range specified by the memory base and limit
1 registers are master aborted on the backbone.
1 = Enable. Allows memory cycles within the range specified by the memory base and
limit registers can be forwarded to the PCI Express device.
I/O Space Enable (IOSE)—R/W. This bit controls access to the I/O space registers.
0 = Disable. I/O cycles within the range specified by the I/O base and limit registers are
0 master aborted on the backbone.
1 = Enable. Allows I/O cycles within the range specified by the I/O base and limit
registers can be forwarded to the PCI Express device.
824 Datasheet
PCI Express* Configuration Registers
19.1.4 PCISTS—PCI Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 06h–07h Attribute: R/WC, RO
Default Value: 0010h Size: 16 bits
Bit Description
Detected Parity Error (DPE)—R/WC.
0 = No parity error detected.
15
1 = Set when the root port receives a command or data from the backbone with a
parity error. This is set even if PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is not set.
Signaled System Error (SSE)—R/WC.
14 0 = No system error signaled.
1 = Set when the root port signals a system error to the internal SERR# logic.
Received Master Abort (RMA)—R/WC.
0 = Root port has not received a completion with unsupported request status from the
13 backbone.
1 = Set when the root port receives a completion with unsupported request status from
the backbone.
Received Target Abort (RTA)—R/WC.
0 = Root port has not received a completion with completer abort from the backbone.
12
1 = Set when the root port receives a completion with completer abort from the
backbone.
Signaled Target Abort (STA)—R/WC.
11 0 = No target abort received.
1 = Set whenever the root port forwards a target abort received from the downstream
device onto the backbone.
DEVSEL# Timing Status (DEV_STS)—Reserved per the PCI Express* Base
10:9
Specification.
Master Data Parity Error Detected (DPED)—R/WC.
8 0 = No data parity error received.
1 = Set when the root port receives a completion with a data parity error on the
backbone and PCIMD.PER (D28:F0/F1/F2/F3:04, bit 6) is set.
7 Fast Back to Back Capable (FB2BC)—Reserved per the PCI Express* Base Specification.
6 Reserved
5 66 MHz Capable—Reserved per the PCI Express* Base Specification.
4 Capabilities List—RO. Hardwired to 1. Indicates the presence of a capabilities list.
Interrupt Status—RO. Indicates status of Hot-Plug and power management interrupts
on the root port that result in INTx# message generation.
0 = Interrupt is de-asserted.
3 1 = Interrupt is asserted.
This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the
state of PCICMD.Interrupt Disable bit (D28:F0/F1/F2/F3/F4/F5/F6/F7/F6/F7:04h:bit
10).
2:0 Reserved
Datasheet 825
PCI Express* Configuration Registers
19.1.5 RID—Revision Identification Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Offset Address: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
Bit Description
Revision ID—RO. This field indicates the device specific revision identifier. See
7:0
Section 1.3 for the value of the RID Register.
19.1.6 PI—Programming Interface Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 09h Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
Programming Interface—RO.
7:0
00h = No specific register level programming interface defined.
19.1.7 SCC—Sub Class Code Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 0Ah Attribute: RO
Default Value: 04h Size: 8 bits
Bit Description
Sub Class Code (SCC)—RO. This field is determined by bit 2 of the MPC register
(D28:F0-5:Offset D8h, bit 2).
7:0
04h = PCI-to-PCI bridge.
00h = Host Bridge.
19.1.8 BCC—Base Class Code Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 0Bh Attribute: RO
Default Value: 06h Size: 8 bits
Bit Description
Base Class Code (BCC)—RO.
7:0
06h = Indicates the device is a bridge device.
826 Datasheet
PCI Express* Configuration Registers
19.1.9 CLS—Cache Line Size Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 0Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Cache Line Size (CLS)—R/W. This is read/write but contains no functionality, per the
7:0
PCI Express* Base Specification.
19.1.10 PLT—Primary Latency Timer Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
7:3 Latency Count. Reserved per the PCI Express* Base Specification.
2:0 Reserved
19.1.11 HEADTYP—Header Type Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 0Eh Attribute: RO
Default Value: 81h Size: 8 bits
Bit Description
Multi-Function Device—RO.
7 0 = Single-function device.
1 = Multi-function device.
Configuration Layout—RO. This field is determined by bit 2 of the MPC register
(D28:F0-5:Offset D8h, bit 2).
6:0
00h = Indicates a Host Bridge.
01h = Indicates a PCI-to-PCI bridge.
Datasheet 827
PCI Express* Configuration Registers
19.1.12 BNUM—Bus Number Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 18–1Ah Attribute: R/W
Default Value: 000000h Size: 24 bits
Bit Description
Subordinate Bus Number (SBBN)—R/W. Indicates the highest PCI bus number
23:16
below the bridge.
15:8 Secondary Bus Number (SCBN)—R/W. Indicates the bus number the port.
7:0 Primary Bus Number (PBN)—R/W. Indicates the bus number of the backbone.
19.1.13 SLT—Secondary Latency Timer Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 1Bh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
Secondary Latency Timer—Reserved for a Root Port per the PCI Express* Base
7:0
Specification.
19.1.14 IOBL—I/O Base and Limit Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 1Ch–1Dh Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
I/O Limit Address (IOLA)—R/W. I/O Base bits corresponding to address lines 15:12
15:12
for 4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.
I/O Limit Address Capability (IOLC)—RO. Indicates that the bridge does not
11:8
support 32-bit I/O addressing.
I/O Base Address (IOBA)—R/W. I/O Base bits corresponding to address lines 15:12
7:4
for 4-KB alignment. Bits 11:0 are assumed to be padded to 000h.
I/O Base Address Capability (IOBC)—RO. Indicates that the bridge does not
3:0
support 32-bit I/O addressing.
828 Datasheet
PCI Express* Configuration Registers
19.1.15 SSTS—Secondary Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 1Eh–1Fh Attribute: R/WC
Default Value: 0000h Size: 16 bits
Bit Description
Detected Parity Error (DPE)—R/WC.
15 0 = No error.
1 = The port received a poisoned TLP.
Received System Error (RSE)—R/WC.
14 0 = No error.
1 = The port received an ERR_FATAL or ERR_NONFATAL message from the device.
Received Master Abort (RMA)—R/WC.
13 0 = Unsupported Request not received.
1 = The port received a completion with “Unsupported Request” status from the device.
Received Target Abort (RTA)—R/WC.
12 0 = Completion Abort not received.
1 = The port received a completion with “Completion Abort” status from the device.
Signaled Target Abort (STA)—R/WC.
11 0 = Completion Abort not sent.
1 = The port generated a completion with “Completion Abort” status to the device.
Secondary DEVSEL# Timing Status (SDTS): Reserved per PCI Express* Base
10:9
Specification.
Data Parity Error Detected (DPD)—R/WC.
0 = Conditions below did not occur.
1 = Set when the BCTRL.PERE (D28:FO/F1/F2/F3/F4/F5:3E: bit 0) is set, and either of
8
the following two conditions occurs:
•Port receives completion marked poisoned.
•Port poisons a write request to the secondary side.
Secondary Fast Back to Back Capable (SFBC): Reserved per PCI Express* Base
7
Specification.
6 Reserved
5 Secondary 66 MHz Capable (SC66): Reserved per PCI Express* Base Specification.
4:0 Reserved
Datasheet 829
PCI Express* Configuration Registers
19.1.16 MBL—Memory Base and Limit Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 20h–23h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Accesses that are within the ranges specified in this register will be sent to the attached
device if CMD.MSE (D28:F0~F7:04:bit 1) is set. Accesses from the attached device that
are outside the ranges specified will be forwarded to the backbone if CMD.BME
(D28:F0~F7:04:bit 2) is set. The comparison performed is MB AD[31:20] ML.
Bit Description
Memory Limit (ML)—R/W. These bits are compared with bits 31:20 of the incoming
31:20
address to determine the upper 1-MB aligned value of the range.
19:16 Reserved
Memory Base (MB)—R/W. These bits are compared with bits 31:20 of the incoming
15:4
address to determine the lower 1-MB aligned value of the range.
3:0 Reserved
19.1.17 PMBL—Prefetchable Memory Base and Limit Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 24h–27h Attribute: R/W, RO
Default Value: 00010001h Size: 32 bits
Accesses that are within the ranges specified in this register will be sent to the device if
CMD.MSE (D28:F0~F7;04, bit 1) is set. Accesses from the device that are outside the
ranges specified will be forwarded to the backbone if CMD.BME (D28:F0~F7;04, bit 2)
is set. The comparison performed is PMBU32:PMB AD[63:32]:AD[31:20]
PMLU32:PML.
Bit Description
Prefetchable Memory Limit (PML)—R/W. These bits are compared with bits 31:20 of
31:20
the incoming address to determine the upper 1-MB aligned value of the range.
19:16 64-bit Indicator (I64L)—RO. Indicates support for 64-bit addressing
Prefetchable Memory Base (PMB)—R/W. These bits are compared with bits 31:20 of
15:4
the incoming address to determine the lower 1-MB aligned value of the range.
3:0 64-bit Indicator (I64B)—RO. Indicates support for 64-bit addressing
830 Datasheet
PCI Express* Configuration Registers
19.1.18 PMBU32—Prefetchable Memory Base Upper 32 Bits
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 28h–2Bh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Prefetchable Memory Base Upper Portion (PMBU)—R/W. Upper 32-bits of the
31:0
prefetchable address base.
19.1.19 PMLU32—Prefetchable Memory Limit Upper 32 Bits
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 2Ch–2Fh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Prefetchable Memory Limit Upper Portion (PMLU)—R/W. Upper 32-bits of the
31:0
prefetchable address limit.
19.1.20 CAPP—Capabilities List Pointer Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 34h Attribute: RWO
Default Value: 40h Size: 8 bits
Bit Description
Capabilities Pointer (PTR)—RO. Indicates that the pointer for the first entry in the
7:0
capabilities list is at 40h in configuration space.
Datasheet 831
PCI Express* Configuration Registers
19.1.21 INTR—Interrupt Information Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 3Ch–3Dh Attribute: R/W, RO
Default Value: See bit description Size: 16 bits
Function Level Reset: No (Bits 7:0 only)
Bit Description
Interrupt Pin (IPIN)—RO. Indicates the interrupt pin driven by the root port. At
reset, this register takes on the following values that reflect the reset state of the
D28IP register in chipset config space:
Port Reset Value
1 D28IP.P1IP
2 D28IP.P2IP
15:8
3 D28IP.P3IP
4 D28IP.P4IP
5 D28IP.P5IP
6 D28IP.P6IP
7 D28IP.P7IP
8 D28IP.P8IP
NOTE: The value that is programmed into D28IP is always reflected in this register.
Interrupt Line (ILINE)—R/W. Default = 00h. Software written value to indicate which
7:0 interrupt line (vector) the interrupt is connected to. No hardware action is taken on this
register. These bits are not reset by FLR.
832 Datasheet
PCI Express* Configuration Registers
19.1.22 BCTRL—Bridge Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 3Eh–3Fh Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:12 Reserved
Discard Timer SERR# Enable (DTSE): Reserved per PCI Express* Base Specification,
11
Revision 1.0a
Discard Timer Status (DTS): Reserved per PCI Express* Base Specification, Revision
10
1.0a.
Secondary Discard Timer (SDT): Reserved per PCI Express* Base Specification,
9
Revision 1.0a.
Primary Discard Timer (PDT): Reserved per PCI Express* Base Specification, Revision
8
1.0a.
Fast Back to Back Enable (FBE): Reserved per PCI Express* Base Specification,
7
Revision 1.0a.
6 Secondary Bus Reset (SBR)—R/W. Triggers a hot reset on the PCI Express* port.
5 Master Abort Mode (MAM): Reserved per Express specification.
VGA 16-Bit Decode (V16)—R/W.
4 0 = VGA range is enabled.
1 = The I/O aliases of the VGA range (see BCTRL:VE definition below), are not enabled,
and only the base I/O ranges can be decoded.
VGA Enable (VE)—R/W.
0 = The ranges below will not be claimed off the backbone by the root port.
3 1 = The following ranges will be claimed off the backbone by the root port:
• Memory ranges A0000h-BFFFFh
• I/O ranges 3B0h – 3BBh and 3C0h – 3DFh, and all aliases of bits 15:10 in any combination of 1s
ISA Enable (IE)—R/W. This bit only applies to I/O addresses that are enabled by the
I/O Base and I/O Limit registers and are in the first 64 KB of PCI I/O space.
0 = The root port will not block any forwarding from the backbone as described below.
2
1 = The root port will block any forwarding from the backbone to the device of I/O
transactions addressing the last 768 bytes in each 1-KB block (offsets 100h to
3FFh).
SERR# Enable (SE)—R/W.
0 = The messages described below are not forwarded to the backbone.
1
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages received are forwarded to
the backbone.
Parity Error Response Enable (PERE)—R/W. When set,
0 = Poisoned write TLPs and completions indicating poisoned TLPs will not set the
0 SSTS.DPD (D28:F0/F1/F2/F3/F4/F5/F6/F7:1E, bit 8).
1 = Poisoned write TLPs and completions indicating poisoned TLPs will set the
SSTS.DPD (D28:F0/F1/F2/F3/F4/F5/F6/F7:1E, bit 8).
Datasheet 833
PCI Express* Configuration Registers
19.1.23 CLIST—Capabilities List Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 40–41h Attribute: R/WO, RO
Default Value: 8010h Size: 16 bits
Bit Description
Next Capability (NEXT)—RWO. Indicates the location of the next pointer. The default
value of this register is 80h, which points to the MSI Capability structure. Since this is a
15:8
RWO register, BIOS must write a value to this register, even if it is to re-write the
default value.
7:0 Capability ID (CID)—RO. Indicates this is a PCI Express* capability.
19.1.24 XCAP—PCI Express* Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 42h–43h Attribute: R/WO, RO
Default Value: 0042h Size: 16 bits
Bit Description
15:14 Reserved
Interrupt Message Number (IMN)—RO. The PCH does not have multiple MSI
13:9
interrupt numbers.
Slot Implemented (SI)—R/WO. Indicates whether the root port is connected to a
8 slot. Slot support is platform specific. BIOS programs this field, and it is maintained
until a platform reset.
7:4 Device / Port Type (DT)—RO. Indicates this is a PCI Express* root port.
3:0 Capability Version (CV)—RO. Indicates PCI Express 2.0.
834 Datasheet
PCI Express* Configuration Registers
19.1.25 DCAP—Device Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 44h–47h Attribute: R/WO, RO
Default Value: 00008000h Size: 32 bits
Bit Description
31:28 Reserved
27:26 Captured Slot Power Limit Scale (CSPS)—RO. Not supported.
25:18 Captured Slot Power Limit Value (CSPV)—RO. Not supported.
17:16 Reserved
Role Based Error Reporting (RBER)—RO. Indicates that this device implements the
15 functionality defined in the Error Reporting ECN as required by the PCI Express 2.0
specification.
14:12 Reserved
Endpoint L1 Acceptable Latency (E1AL)—RO. This field is reserved with a setting of
11:9
000b for devices other than Endpoints, per the PCI Express 2.0 Spec.
Endpoint L0 Acceptable Latency (E0AL)—RO. This field is reserved with a setting of
8:6
000b for devices other than Endpoints, per the PCI Express 2.0 Spec.
Extended Tag Field Supported (ETFS)—RO. Indicates that 8-bit tag fields are
5
supported.
4:3 Phantom Functions Supported (PFS)—RO. No phantom functions supported.
Max Payload Size Supported (MPS)—RWO. BIOS should write to this field during
system initialization. Only a maximum payload size of 128B is supported. Programming
2:0
this field to any value other than 000b (128B) will result in aliasing to 128B max
payload size.
Datasheet 835
PCI Express* Configuration Registers
19.1.26 DCTL—Device Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 48h–49h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15 Reserved
14:12 Max Read Request Size (MRRS)—RO. Hardwired to 0.
Enable No Snoop (ENS)—RO. Not supported. The root port will never issue non-
11
snoop requests.
Aux Power PM Enable (APME)—R/W. The OS will set this bit to 1 if the device
10
connected has detected aux power. It has no effect on the root port otherwise.
9 Phantom Functions Enable (PFE)—RO. Not supported.
8 Extended Tag Field Enable (ETFE)—RO. Not supported.
Max Payload Size (MPS)—R/W. The root port only supports 128B max payloads,
regardless of the programming of this field. Programming this field to any value other
7:5
than 000b (128B) will result in aliasing to 128B max payload size. BIOS should program
this field prior to enabling BME.
4 Enable Relaxed Ordering (ERO)—RO. Not supported.
Unsupported Request Reporting Enable (URE)—R/W.
0 = The root port will ignore unsupported request errors.
1 = Allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_COR to the Root Control
register when detecting an unmasked Unsupported Request (UR). An ERR_COR is
3
signaled when a unmasked Advisory Non-Fatal UR is received. An ERR_FATAL,
ERR_or NONFATAL, is sent to the Root Control Register when an uncorrectable non-
Advisory UR is received with the severity set by the Uncorrectable Error Severity
register.
Fatal Error Reporting Enable (FEE)—R/W.
0 = The root port will ignore fatal errors.
2 1 = Enables signaling of ERR_FATAL to the Root Control register due to internally
detected errors or error messages received across the link. Other bits also control
the full scope of related error reporting.
Non-Fatal Error Reporting Enable (NFE)—R/W.
0 = The root port will ignore non-fatal errors.
1 1 = Enables signaling of ERR_NONFATAL to the Root Control register due to internally
detected errors or error messages received across the link. Other bits also control
the full scope of related error reporting.
Correctable Error Reporting Enable (CEE)—R/W.
0 = The root port will ignore correctable errors.
0 1 = Enables signaling of ERR_CORR to the Root Control register due to internally
detected errors or error messages received across the link. Other bits also control
the full scope of related error reporting.
836 Datasheet
PCI Express* Configuration Registers
19.1.27 DSTS—Device Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 4Ah–4Bh Attribute: R/WC, RO
Default Value: 0010h Size: 16 bits
Bit Description
15:6 Reserved
Transactions Pending (TDP)—RO. This bit has no meaning for the root port since
5 only one transaction may be pending to the PCH, so a read of this bit cannot occur until
it has already returned to 0.
4 AUX Power Detected (APD)—RO. The root port contains AUX power for wakeup.
Unsupported Request Detected (URD)—R/WC. Indicates an unsupported request
3
was detected.
Fatal Error Detected (FED)—R/WC. Indicates a fatal error was detected.
0 = Fatal has not occurred.
2
1 = A fatal error occurred from a data link protocol error, link training error, buffer
overflow, or malformed TLP.
Non-Fatal Error Detected (NFED)—R/WC. Indicates a non-fatal error was detected.
1 0 = Non-fatal has not occurred.
1 = A non-fatal error occurred from a poisoned TLP, unexpected completions,
unsupported requests, completer abort, or completer timeout.
Correctable Error Detected (CED)—R/WC. Indicates a correctable error was
detected.
0 0 = Correctable has not occurred.
1 = The port received an internal correctable error from receiver errors / framing
errors, TLP CRC error, DLLP CRC error, replay num rollover, replay timeout.
Datasheet 837
PCI Express* Configuration Registers
19.1.28 LCAP—Link Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 4Ch–4Fh Attribute: R/WO, RO/V, RO
Default Value: See bit description Size: 32 bits
Bit Description
Port Number (PN)—RO/V. Indicates the port number for the root port. This value is
different for each implemented port:
Function Port # Value of PN Field
D28:F0 1 01h
D28:F1 2 02h
31:24 D28:F2 3 03h
D28:F3 4 04h
D28:F4 5 05h
D28:F5 6 06h
D28:F6 7 07h
D28:F7 8 08h
23:22 Reserved
Link Bandwidth Notification Capability (LBNC)—RO. Hardwired to 1b to indicate
21
that this port supports Link Bandwidth Notification status and interrupt mechanisms.
Link Active Reporting Capable (LARC)—RO. Hardwired to 1b to indicate that this
20 port supports the optional capability of reporting the DL_Active state of the Data Link
Control and Management State Machine.
19 Reserved
Clock Power Management (CPM)—RO.
18 0 = PCH root ports do not support the CLKREQ# mechanism.
1 = PCH root ports support the CLKREQ# mechanism.
L1 Exit Latency (EL1)—R/WO. Indicates an exit latency of 2us to 4us.
000b = Less than 1us
001b = 1 us to less than 2 us
010b = 2 us to less than 4 us
011b = 4 us to less than 8 us
100b = 8 us to less than 16 us
17:15
101b = 16 us to less than 32 us
110b = 32 us to 64 us
111b = more than 64 us
NOTE: If PXP PLL shutdown is enabled, BIOS should program this latency to
comprehend PLL lock latency.
838 Datasheet
PCI Express* Configuration Registers
Bit Description
L0s Exit Latency (EL0)—RO/V. Indicates an exit latency based upon common-clock
configuration.
LCLT.CCC Value of EL0 (these bits)
14:12
0 MPC.UCEL (D28:F0~F7:D8h:bits20:18)
1 MPC.CCEL (D28:F0~F7:D8h:bits17:15)
NOTE: LCLT.CCC is at D28:F0~F7:50h:bit 6.
Active State Power Management Support (APMS)—R/WO. Indicates what level of
active state link power management is supported on the root port.
NOTE: In a SKU where ASPM control is disabled, the default value of this field is hard
wired to 01b, regardless of any value the BIOS writes to this field. Otherwise,
the default value of this field is 11b.
Value Definition
11:10
00b Reserved
01b L0s Entry Supported
10b Reserved
11b Both L0s and L1 Entry Supported
Maximum Link Width (MLW)—RO/V.
These bits are set by the PCIEPCS1[1:0] soft strap in the PCHSTRP9 record.
NOTE: Support for 1 x2 or 1 x4 configuration on PCIe Port 1 is only available per
Section 5.1 guidelines.
000011 = 1 x4: Port 1 (x4)
000010 = Reserved
000001 = 1 x2 and 2 x1s: Port 1 (x2), Port 3 (x1) and Port 4 (x1)
9:4 000000 = 4 x1s: Port 1 (x1), Port 2 (x1), Port 3 (x1) and Port 4 (x1)
This bit is set by the PCIEPCS2[1:0] soft strap in the PCHSTRP9 record.
000011 = 1 x4: Port 5 (x4)
000010 = Reserved
000001 = 1 x2 and 2 x1s: Port 5 (x2), Port 7 (x1) and Port 8 (x1)
000000 = 4 x1s: Port 5 (x1), Port 6 (x1), Port 7 (x1) and Port 8 (x1)
Maximum Link Speed (MLS)—RO.
0001b = indicates the link speed is 2.5 Gb/s
0010b = 5.0 Gb/s and 2.5Gb/s link speeds supported
3:0
NOTE: These bits report a value of 0001b if Gen2 disable bit 14 is set in the MPC
register, else the value reported is 0010b
Datasheet 839
PCI Express* Configuration Registers
19.1.29 LCTL—Link Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 50h–51h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:10 Reserved
Hardware Autonomous Width Disable – RO. Hardware never attempts to change
9
the link width except when attempting to correct unreliable Link operation.
8 Reserved
Extended Synch (ES)—R/W.
7 0 = Extended synch disabled.
1 = Forces extended transmission of FTS ordered sets in FTS and extra TS2 at exit from
L1 prior to entering L0.
Common Clock Configuration (CCC)—R/W.
6 0 = The PCH and device are not using a common reference clock.
1 = The PCH and device are operating with a distributed common reference clock.
Retrain Link (RL)—R/W.
0 = This bit always returns 0 when read.
1 = The root port will train its downstream link.
NOTE: Software uses LSTS.LT (D28:F0/F1/F2/F3/F4/F5/F6/F7:52, bit 11) to check the
status of training.
5
NOTE: It is permitted to write 1b to this bit while simultaneously writing modified
values to other fields in this register. If the LTSSM is not already in Recovery or
Configuration, the resulting Link training must use the modified values. If the
LTSSM is already in Recovery or Configuration, the modified values are not
required to affect the Link training that is already in progress.
Link Disable (LD)—R/W.
4 0 = Link enabled.
1 = The root port will disable the link.
Read Completion Boundary Control (RCBC)—RO. Indicates the read completion
3
boundary is 64 bytes.
2 Reserved
Active State Link PM Control (APMC)—R/W. Indicates whether the root port should
enter L0s or L1 or both.
00 = Disabled
1:0
01 = L0s Entry Enabled
10 = L1 Entry Enabled
11 = L0s and L1 Entry Enabled
840 Datasheet
PCI Express* Configuration Registers
19.1.30 LSTS—Link Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 52h–53h Attribute: RO
Default Value: See bit description Size: 16 bits
Bit Description
15:14 Reserved
Data Link Layer Active (DLLA)—RO. Default value is 0b.
13 0 = Data Link Control and Management State Machine is not in the DL_Active state
1 = Data Link Control and Management State Machine is in the DL_Active state
Slot Clock Configuration (SCC)—RO. Set to 1b to indicate that the PCH uses the
12
same reference clock as on the platform and does not generate its own clock.
Link Training (LT)—RO. Default value is 0b.
11 0 = Link training completed.
1 = Link training is occurring.
10 Link Training Error (LTE)—RO. Not supported. Set value is 0b.
Negotiated Link Width (NLW)—RO. This field indicates the negotiated width of the
given PCI Express* link. The contents of this NLW field is undefined if the link has not
successfully trained.
Port # Possible Values
1 000001b, 000010b, 000100b
2 000001b
9:4 3 000001b, 000010b
4 000001b
5 000001b, 000010b, 000100b
6 000001b
7 000001b, 000010b
8 000001b
NOTE: 000001b = x1 link width, 000010b =x2 linkwidth, 000100b = x4 linkwidth
Link Speed (LS)—RO. This field indicates the negotiated Link speed of the given PCI
Express* link.
3:0
0001b = Link is 2.5 Gb/s
0010b = Link is 5.0 Gb/s
Datasheet 841
PCI Express* Configuration Registers
19.1.31 SLCAP—Slot Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 54h–57h Attribute: R/WO, RO
Default Value: 00060060h Size: 32 bits
Bit Description
Physical Slot Number (PSN)—R/WO. This is a value that is unique to the slot
31:19
number. BIOS sets this field and it remains set until a platform reset.
18:17 Reserved
Slot Power Limit Scale (SLS)—R/WO. Specifies the scale used for the slot power
16:15
limit value. BIOS sets this field and it remains set until a platform reset.
Slot Power Limit Value (SLV)—R/WO. Specifies the upper limit (in conjunction with
SLS value), on the upper limit on power supplied by the slot. The two values together
14:7
indicate the amount of power in watts allowed for the slot. BIOS sets this field and it
remains set until a platform reset.
Hot-Plug Capable (HPC)—R/WO.
6
1b = Indicates that Hot-Plug is supported.
Hot-Plug Surprise (HPS)—R/WO.
5
1b = Indicates the device may be removed from the slot without prior notification.
Power Indicator Present (PIP)—RO.
4
0b = Indicates that a power indicator LED is not present for this slot.
Attention Indicator Present (AIP)—RO.
3
0b = Indicates that an attention indicator LED is not present for this slot.
MRL Sensor Present (MSP)—RO.
2
0b = Indicates that an MRL sensor is not present.
Power Controller Present (PCP)—RO.
1
0b = Indicates that a power controller is not implemented for this slot.
Attention Button Present (ABP)—RO.
0
0b = Indicates that an attention button is not implemented for this slot.
842 Datasheet
PCI Express* Configuration Registers
19.1.32 SLCTL—Slot Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 58h–59h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:13 Reserved
Link Active Changed Enable (LACE)—R/W. When set, this field enables generation
12 of a Hot-Plug interrupt when the Data Link Layer Link Active field (D28:F0/F1/F2/F3/
F4/F5/F6/F7:52h:bit 13) is changed.
11 Reserved
Power Controller Control (PCC)—RO.This bit has no meaning for module based Hot-
10
Plug.
9:6 Reserved
Hot-Plug Interrupt Enable (HPE)—R/W.
5 0 = Hot-Plug interrupts based on Hot-Plug events is disabled.
1 = Enables generation of a Hot-Plug interrupt on enabled Hot-Plug events.
4 Reserved
Presence Detect Changed Enable (PDE)—R/W.
0 = Hot-Plug interrupts based on presence detect logic changes is disabled.
3
1 = Enables the generation of a Hot-Plug interrupt or wake message when the presence
detect logic changes state.
2:0 Reserved
Datasheet 843
PCI Express* Configuration Registers
19.1.33 SLSTS—Slot Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 5Ah–5Bh Attribute: R/WC, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:9 Reserved
Link Active State Changed (LASC)—R/WC.
1 = This bit is set when the value reported in Data Link Layer Link Active field of the
8 Link Status register (D28:F0/F1/F2/F3/F4/F5/F6/F7:52h:bit 13) is changed. In
response to a Data Link Layer State Changed event, software must read Data Link
Layer Link Active field of the Link Status register to determine if the link is active
before initiating configuration cycles to the hot plugged device.
7 Reserved
Presence Detect State (PDS)—RO. If XCAP.SI (D28:F0/F1/F2/F3/F4/F5/F6/
F7:42h:bit 8) is set (indicating that this root port spawns a slot), then this bit:
6 0 = Indicates the slot is empty.
1 = Indicates the slot has a device connected.
Otherwise, if XCAP.SI is cleared, this bit is always set (1).
5 MRL Sensor State (MS)—Reserved as the MRL sensor is not implemented.
4 Reserved
Presence Detect Changed (PDC)—R/WC.
3 0 = No change in the PDS bit.
1 = The PDS bit changed states.
2 MRL Sensor Changed (MSC)—Reserved as the MRL sensor is not implemented.
1 Power Fault Detected (PFD)—Reserved as a power controller is not implemented.
0 Reserved
844 Datasheet
PCI Express* Configuration Registers
19.1.34 RCTL—Root Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 5Ch–5Dh Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:4 Reserved
PME Interrupt Enable (PIE)—R/W.
0 = Interrupt generation disabled.
3 1 = Interrupt generation enabled when PCISTS.Inerrupt Status (D28:F0~F7:60h, bit
16) is in a set state (either due to a 0 to 1 transition, or due to this bit being set
with RSTS.IS already set).
System Error on Fatal Error Enable (SFE)—R/W.
0 = An SERR# will not be generated.
2 1 = An SERR# will be generated, assuming CMD.SEE (D28:F0~F7:04, bit 8) is set, if a
fatal error is reported by any of the devices in the hierarchy of this root port,
including fatal errors in this root port.
System Error on Non-Fatal Error Enable (SNE)—R/W.
0 = An SERR# will not be generated.
1 1 = An SERR# will be generated, assuming CMD.SEE (D28:F0~F7:04, bit 8) is set, if a
non-fatal error is reported by any of the devices in the hierarchy of this root port,
including non-fatal errors in this root port.
System Error on Correctable Error Enable (SCE)—R/W.
0 = An SERR# will not be generated.
0 1 = An SERR# will be generated, assuming CMD.SEE (D28:F0~F7:04, bit 8) if a
correctable error is reported by any of the devices in the hierarchy of this root port,
including correctable errors in this root port.
19.1.35 RSTS—Root Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 60h–63h Attribute: R/WC, RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:18 Reserved
PME Pending (PP)—RO.
17 0 = When the original PME is cleared by software, it will be set again, the requestor ID
will be updated, and this bit will be cleared.
1 = Indicates another PME is pending when the PME status bit is set.
PME Status (PS)—R/WC.
0 = PME was not asserted.
16
1 = Indicates that PME was asserted by the requestor ID in RID. Subsequent PMEs are
kept pending until this bit is cleared.
PME Requestor ID (RID)—RO. Indicates the PCI requestor ID of the last PME
15:0
requestor. Valid only when PS is set.
Datasheet 845
PCI Express* Configuration Registers
19.1.36 DCAP2—Device Capabilities 2 Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 64h–67h Attribute: RWO, RO
Default Value: 00080816h Size: 32 bits
Bit Description
31:12 Reserved
LTR Mechanism Supported (LTRMS)—RWO. A value of 1b
11
indicates support for the optional Latency Tolerance Reporting (LTR) mechanism.
10:5 Reserved
Completion Timeout Disable Supported (CTDS)—RO. A value of 1b
4
indicates support for the Completion Timeout Disable mechanism.
Completion Timeout Ranges Supported (CTRS) – RO. This field indicates device
support for the optional Completion Timeout programmability mechanism. This
3:0 mechanism allows system software to modify the Completion Timeout value.
This field is hardwired to support 10 ms to 250 ms and 250 ms to 4 s.
19.1.37 DCTL2—Device Control 2 Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 68h–69h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved
LTR Mechanism Enable (LTREN)—RW. A value of 1b enables support for the optional
10
Latency Tolerance Reporting (LTR) mechanism.
846 Datasheet
PCI Express* Configuration Registers
Bit Description
9:5 Reserved
Completion Timeout Disable (CTD)—R/W. When set to 1b, this bit disables the
Completion Timeout mechanism.
If there are outstanding requests when the bit is cleared, it is permitted but not
4
required for hardware to apply the completion timeout mechanism to the outstanding
requests. If this is done, it is permitted to base the start time for each request on either
the time this bit was cleared or the time each request was issued.
Completion Timeout Value (CTV)—R/W. In Devices that support Completion
Timeout programmability, this field allows system software to modify the Completion
Timeout value. This field is applicable to Root Ports, Endpoints that issue requests on
their own behalf, and PCI Express* to PCI/PCI-X Bridges that take ownership of
requests issued on PCI Express. For all other devices this field is reserved and must be
hardwired to 0000b.
A Device that does not support this optional capability must hardwire this field to 0000b
and is required to implement a timeout value in the range 50 us to 50 ms. Devices that
support Completion Timeout programmability must support the values given below,
corresponding to the programmability ranges indicated in the Completion Timeout
Values Supported field. The PCH targeted configurable ranges are listed below, along
with the range allowed by the PCI Express 2.0 specification.
Defined encodings:
0000b = Default range: 40 ms to 50 ms (specification range 50 us to 50 ms)
Values available if Range A (50 us to 10 ms) programmability range is supported:
3:0 0001b = 90 μs to 100 μs (specification range is 50 μs to 100 μs)
0010b = 9 ms to 10ms (specification range is 1 ms to 10 ms)
Values available if Range B (10 ms to 250 ms) programmability range is supported:
0101b = 40ms to 50ms (specification range is 16 ms to 55 ms)
0110b = 160ms to 170ms (specification range is 65 ms to 210 ms)
Values available if Range C (250 ms to 4s) programmability range is supported:
1001b = 400 ms to 500 ms (specification range is 260 ms to 900 ms)
1010b = 1.6 s to 1.7 s (specification range is 1 s to 3.5 s)
All other values are Reserved.
NOTE: Software is permitted to change the value in this field at any time. For requests
already pending when the Completion Timeout Value is changed, hardware is
permitted to use either the new or the old value for the outstanding requests,
and is permitted to base the start time for each request either on when this
value was changed or on when each request was issued.
Datasheet 847
PCI Express* Configuration Registers
19.1.38 LCTL2—Link Control 2 Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 70h–71h Attribute: R/W
Default Value: 0002h Size: 16 bits
Bit Description
15:13 Reserved
Compliance De-Emphasis (CD)—R/W.
This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due
to the Enter Compliance bit being 1b.
Encodings:
0 = -6 dB
12
1 = -3.5 dB
When the Link is operating at 2.5 GT/s, the setting of this bit has no effect.
The default value of this bit is 0b.
This bit is intended for debug, compliance testing purposes. System firmware and
software are allowed to modify this bit only during debug or compliance testing.
Compliance SOS (CSOS)—R/W.
When set to 1b, the LTSSM is required to send SKP Ordered Sets periodically in
11
between the (modified) compliance patterns.
The default value of this bit is 0b.
Enter Modified Compliance (EMC)—R/W.
When this bit is set to 1b, the device transmits Modified Compliance Pattern if the
LTSSM enters Polling.Compliance substrate. This register is intended for debug,
10
compliance testing purposes only and the system must ensure it is set to the default
value during normal operation.
The default value of this bit is 0b.
Transmit Margin (TM)—R/W. This field controls the value of the non-de-emphasized
voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM
Polling.Configuration substrate (see PCI Express Chapter 4 for details of how the
Transmitter voltage level is determined in various states).
Encodings:
000b: Normal operating range
001b: 800-1200 mV for full swing and 400-700 mV for half-swing
010b - (n-1): Values must be monotonic with a non-zero slope. The value of n must be
greater than 3 and less than 7. At least two of these must be below the
9:7 normal operating range of n: 200–400 mV for full-swing and 100–
200 mV for half-swing
n - 111b” Reserved
For a Multi-Function device associated with an Upstream Port, the field in Function 0 is
of type RWS, and only Function 0 controls the component‘s Link behavior. In all other
Functions of that device, this field is of type RsvdP.
Default value of this field is 000b.
Components that support only the 2.5 GT/s speed are permitted to hardwire this bit to
000b. This register is intended for debug, compliance testing purposes only and the
system must ensure it is set to the default value during normal operation.
848 Datasheet
PCI Express* Configuration Registers
Bit Description
Selectable De-emphasis (SD)—R/W.
When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis
for an Upstream component.
6 Encodings:
1b =3.5 dB
0b = 6 dB
When the Link is operating at 2.5 GT/s speed, the setting of this bit has no effect.
5 Reserved
Enter Compliance (EC)—R/W.
Software is permitted to force a Link to enter Compliance mode at the speed indicated
4
in the Target Link Speed field by setting this bit to 1b in both components on a Link and
then initiating a hot reset on the Link.
Target Link Speed (TLS)—R/W. This field sets an upper limit on Link operational
speed by restricting the values advertised by the upstream component in its training
sequences.
3:0
0001b = 2.5 GT/s Target Link Speed
0010b = 5.0 GT/s and 2.5 GT/s Target Link Speeds
All other values reserved.
19.1.39 LSTS2—Link Status 2 Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 72h–73h Attribute: RO
Default Value: 0000h Size: 16 bits
Bit Description
15:1 Reserved
Current De-emphasis Level (CDL)—RO.
When the Link is operating at 5 GT/s speed, this bit reflects the level of de-emphasis.
Encodings:
0
0 = -6 dB
1 = -3.5 dB
The value in this bit is undefined when the Link is operating at 2.5 GT/s speed.
19.1.40 MID—Message Signaled Interrupt Identifiers Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 80h–81h Attribute: RO
Default Value: 9005h Size: 16 bits
Bit Description
15:8 Next Pointer (NEXT)—RO. Indicates the location of the next pointer in the list.
7:0 Capability ID (CID)—RO. Capabilities ID indicates MSI.
Datasheet 849
PCI Express* Configuration Registers
19.1.41 MC—Message Signaled Interrupt Message Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 82–83h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:8 Reserved
7 64 Bit Address Capable (C64)—RO. Capable of generating a 32-bit message only.
Multiple Message Enable (MME)—R/W. These bits are R/W for software
6:4
compatibility, but only one message is ever sent by the root port.
3:1 Multiple Message Capable (MMC)—RO. Only one message is required.
MSI Enable (MSIE)—R/W.
0 = MSI is disabled.
1 = MSI is enabled and traditional interrupt pins are not used to generate interrupts.
0
NOTE: CMD.BME (D28:F0/F1/F2/F3/F4/F5/F6/F7:04h:bit 2) must be set for an MSI to
be generated. If CMD.BME is cleared, and this bit is set, no interrupts (not even
pin based) are generated.
19.1.42 MA—Message Signaled Interrupt Message Address
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 84h–87h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Address (ADDR)—R/W. Lower 32 bits of the system specified message address,
31:2
always DW aligned.
1:0 Reserved
850 Datasheet
PCI Express* Configuration Registers
19.1.43 MD—Message Signaled Interrupt Message Data Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 88h–89h Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
Data (DATA)—R/W. This 16-bit field is programmed by system software if MSI is
15:0 enabled. Its content is driven onto the lower word (PCI AD[15:0]) during the data
phase of the MSI memory write transaction.
19.1.44 SVCAP—Subsystem Vendor Capability Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 90h–91h Attribute: R/WO, RO
Default Value: A00Dh Size: 16 bits
Bit Description
Next Capability (NEXT)—R/WO. Indicates the location of the next pointer in the list.
15:8 As this register is RWO, BIOS must write a value to this register, even if it is to re-write
the default value.
Capability Identifier (CID)—RO. Value of 0Dh indicates this is a PCI bridge
7:0
subsystem vendor capability.
19.1.45 SVID—Subsystem Vendor Identification Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 94h–97h Attribute: R/WO
Default Value: 00000000h Size: 32 bits
Bit Description
Subsystem Identifier (SID)—R/WO. Indicates the subsystem as identified by the
31:16 vendor. This field is write once and is locked down until a bridge reset occurs (not the
PCI bus reset).
Subsystem Vendor Identifier (SVID)—R/WO. Indicates the manufacturer of the
15:0 subsystem. This field is write once and is locked down until a bridge reset occurs (not
the PCI bus reset).
Datasheet 851
PCI Express* Configuration Registers
19.1.46 PMCAP—Power Management Capability Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: A0h–A1h Attribute: RO
Default Value: 0001h Size: 16 bits
Bit Description
15:8 Next Capability (NEXT)—RO. Indicates this is the last item in the list.
Capability Identifier (CID)—RO. Value of 01h indicates this is a PCI power
7:0
management capability.
19.1.47 PMC—PCI Power Management Capabilities Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: A2h–A3h Attribute: RO
Default Value: C803h Size: 16 bits
Bit Description
PME_Support (PMES)—RO. Indicates PME# is supported for states D0, D3HOT and
D3COLD. The root port does not generate PME#, but reporting that it does is necessary
15:11
for some legacy operating systems to enable PME# in devices connected behind this
root port.
10 D2_Support (D2S)—RO. The D2 state is not supported.
9 D1_Support (D1S)—RO The D1 state is not supported.
Aux_Current (AC)—RO. Reports 375 mA maximum suspend well current required
8:6
when in the D3COLD state.
Device Specific Initialization (DSI)—RO.
5
1 = Indicates that no device-specific initialization is required.
4 Reserved
PME Clock (PMEC)—RO.
3
1 = Indicates that PCI clock is not required to generate PME#.
Version (VS)—RO. Indicates support for Revision 1.2 of the PCI Power Management
2:0
Specification.
852 Datasheet
PCI Express* Configuration Registers
19.1.48 PMCS—PCI Power Management Control and Status
Register (PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: A4h–A7h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:24 Reserved
Bus Power / Clock Control Enable (BPCE)—Reserved per PCI Express* Base
23
Specification, Revision 1.0a.
22 B2/B3 Support (B23S)—Reserved per PCI Express* Base Specification, Revision 1.0a.
21:16 Reserved
PME Status (PMES)—RO.
15
1 = Indicates a PME was received on the downstream link.
14:9 Reserved
PME Enable (PMEE)—R/W.
1 = Indicates PME is enabled. The root port takes no action on this bit, but it must be
8 R/W for some legacy operating systems to enable PME# on devices connected to
this root port.
This bit is sticky and resides in the resume well. The reset for this bit is RSMRST# which
is not asserted during a warm reset.
7:2 Reserved
Power State (PS)—R/W. This field is used both to determine the current power state
of the root port and to set a new power state. The values are:
00 = D0 state
11 = D3HOT state
1:0
NOTE: When in the D3HOT state, the controller’s configuration space is available, but
the I/O and memory spaces are not. Type 1 configuration cycles are also not
accepted. Interrupts are not required to be blocked as software will disable
interrupts prior to placing the port into D3HOT. If software attempts to write a
‘10’ or ‘01’ to these bits, the write will be ignored.
Datasheet 853
PCI Express* Configuration Registers
19.1.49 MPC2—Miscellaneous Port Configuration Register 2
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: D4h–D7h Attribute: R/W, RO
Default Value: 00000800h Size: 32 bits
Bit Description
31:5 Reserved
ASPM Control Override Enable (ASPMCOEN)—R/W.
1 = Root port will use the values in the ASPM Control Override registers
0 = Root port will use the ASPM Registers in the Link Control register.
4
NOTES:This register allows BIOS to control the root port ASPM settings instead of
the OS.
ASPM Control Override (ASPMO)—R/W. Provides BIOS control of whether root
port should enter L0s or L1 or both.
00 = Disabled
3:2
01 = L0s Entry Enabled
10 = L1 Entry Enabled
11 = L0s and L1 Entry Enabled.
EOI Forwarding Disable (EOIFD)—R/W. When set, EOI messages are not
claimed on the backbone by this port an will not be forwarded across the PCIe link.
1 0 = Broadcast EOI messages that are sent on the backbone are claimed by this
port and forwarded across the PCIe* link.
1 = Broadcast EOI messages are not claimed on the backbone by this port and will
not be forwarded across the PCIe Link.
L1 Completion Timeout Mode (LICTM)—R/W.
0 = PCI Express Specification Compliant. Completion timeout is disabled during
0 software initiated L1, and enabled during ASPM initiate L1.
1 = Completion timeout is enabled during L1, regardless of how L1 entry was
initiated.
854 Datasheet
PCI Express* Configuration Registers
19.1.50 MPC—Miscellaneous Port Configuration Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: D8h–dBh Attribute: R/W, RO, R/WO
Default Value: 09110000h Size: 32 bits
Bit Description
Power Management SCI Enable (PMCE)—R/W.
31 0 = SCI generation based on a power management event is disabled.
1 = Enables the root port to generate SCI whenever a power management event is
detected.
Hot-Plug SCI Enable (HPCE)—R/W.
30 0 = SCI generation based on a Hot-Plug event is disabled.
1 = Enables the root port to generate SCI whenever a Hot-Plug event is detected.
Link Hold Off (LHO)—R/W.
29
1 = Port will not take any TLP. This is used during loopback mode to fill up the
downstream queue.
Address Translator Enable (ATE)—R/W. This bit is used to enable address
translation using the AT bits in this register during loopback mode.
28
0 = Disable
1 = Enable
27 Reserved
Invalid Receive Bus Number Check Enable (IRBNCE)—R/W. When set, the receive
transaction layer will signal an error if the bus number of a Memory request does not
fall within the range between SCBN and SBBN. If this check is enabled and the request
26 is a memory write, it is treated as an Unsupported Request. If this check is enabled and
the request is a non-posted memory read request, the request is considered a
Malformed TLP and a fatal error.
Messages, I/O, Config, and Completions are never checked for valid bus number.
Invalid Receive Range Check Enable (IRRCE)—R/W. When set, the receive
transaction layer will treat the TLP as an Unsupported Request error if the address
range of a Memory request does not outside the range between prefetchable and non-
25 prefetchable base and limit.
Messages, I/O, Configuration, and Completions are never checked for valid address
ranges.
BME Receive Check Enable (BMERCE)—R/W. When set, the receive transaction
layer will treat the TLP as an Unsupported Request error if a memory read or write
24 request is received and the Bus Master Enable bit is not set.
Messages, I/O, Config, and Completions are never checked for BME.
23 Reserved
Detect Override (FORCEDET)—R/W.
22 0 = Normal operation. Detected output from AFE is sampled for presence detection.
1 = Override mode. Ignores AFE detect output and link training proceeds as if a device
were detected.
Flow Control During L1 Entry (FCDL1E)—R/W.
21 0 = No flow control update DLLPs sent during L1 Ack transmission.
1 = Flow control update DLLPs sent during L1 Ack transmission as required to meet the
30 s periodic flow control update.
Unique Clock Exit Latency (UCEL)—R/W. This value represents the L0s Exit Latency
20:18 for unique-clock configurations (LCTL.CCC = 0) (D28:F0/F1/F2/F3/F4/F5/F6/F7:Offset
50h:bit 6). It defaults to 512 ns to less than 1 µs, but may be overridden by BIOS.
Datasheet 855
PCI Express* Configuration Registers
Bit Description
Common Clock Exit Latency (CCEL)—R/W. This value represents the L0s Exit
Latency for common-clock configurations (LCTL.CCC = 1) (D28:F0/F1/F2/F3/F4/F5/F6/
17:15
F7:Offset 50h:bit 6). It defaults to 128 ns to less than 256 ns, but may be overridden
by BIOS.
PCIe Gen2 Speed Disable—R/W.
0 = PCIe supported data rate is defined as set through Supported Link Speed and
Target Link Speed settings.
14 1 = PCIe supported data rate is limited to 2.5 GT/s (Gen1). Supported Link Speed
register bits will reflect “0001b” when this bit is set.
When this bit is changed, link retrain needs to be performed for the change to be
effective.
13:8 Reserved
Port I/OxAPIC Enable (PAE)—R/W.
0 = Hole is disabled.
1 = A range is opened through the bridge for the following memory addresses:
Port # Address
1 FEC1_0000h – FEC1_7FFFh
2 FEC1_8000h – FEC1_FFFFh
3 FEC2_0000h – FEC2_7FFFh
7
4 FEC2_8000h – FEC2_FFFFh
5 FEC3_0000h – FEC3_7FFFh
6 FEC3_8000h – FEC3_FFFFh
7 FEC4_0000h – FEC4_7FFFh
8 FEC4_8000h – FEC4_FFFFh
6:3 Reserved
Bridge Type (BT)—R/WO. This register can be used to modify the Base Class and
Header Type fields from the default PCI-to-PCI bridge to a Host Bridge. Having the root
port appear as a Host Bridge is useful in some server configurations.
2 0 = The root port bridge type is a PCI-to-PCI Bridge, Header Sub-Class = 04h, and
Header Type = Type 1.
1 = The root port bridge type is a PCI-to-PCI Bridge, Header Sub-Class = 00h, and
Header Type = Type 0.
Hot-Plug SMI Enable (HPME)—R/W.
1 0 = SMI generation based on a Hot-Plug event is disabled.
1 = Enables the root port to generate SMI whenever a Hot-Plug event is detected.
Power Management SMI Enable (PMME)—R/W.
0 0 = SMI generation based on a power management event is disabled.
1 = Enables the root port to generate SMI whenever a power management event is
detected.
856 Datasheet
PCI Express* Configuration Registers
19.1.51 SMSCS—SMI/SCI Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: DCh–DFh Attribute: R/WC
Default Value: 00000000h Size: 32 bits
Bit Description
Power Management SCI Status (PMCS)—R/WC.
31 1 = PME control logic needs to generate an interrupt, and this interrupt has been
routed to generate an SCI.
Hot-Plug SCI Status (HPCS)—R/WC.
30 1 = Hot-Plug controller needs to generate an interrupt, and has this interrupt been
routed to generate an SCI.
29:5 Reserved
Hot-Plug Link Active State Changed SMI Status (HPLAS)—R/WC.
4 1 = SLSTS.LASC (D28:F0/F1/F2/F3/F4/F5/F6/F7:5Ah, bit 8) transitioned from 0-to-1,
and MPC.HPME (D28:F0/F1/F2/F3/F4/F5/F6/F7:D8h, bit 1) is set. When this bit is
set, an SMI# will be generated.
3:2 Reserved
Hot-Plug Presence Detect SMI Status (HPPDM)—R/WC.
1 1 = SLSTS.PDC (D28:F0/F1/F2/F3/F4/F5/F6/F7:5Ah, bit 3) transitioned from 0-to-1,
and MPC.HPME (D28:F0/F1/F2/F3/F4/F5/F6/F7:D8h, bit 1) is set. When this bit is
set, an SMI# will be generated.
Power Management SMI Status (PMMS)—R/WC.
0 1 = RSTS.PS (D28:F0/F1/F2/F3/F4/F5/F6/F7:60h, bit 16) transitioned from 0-to-1, and
MPC.PMME (D28:F0/F1/F2/F3/F4/F5/F6/F7:D8h, bit 1) is set.
19.1.52 RPDCGEN—Root Port Dynamic Clock Gating Enable
Register (PCI Express—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: E1h Attribute: R/W
Default Value: 00h Size: 8-bits
Bits Description
7:4 Reserved. RO
Shared Resource Dynamic Link Clock Gating Enable (SRDLCGEN)—R/W.
0 = Disables dynamic clock gating of the shared resource link clock domain.
3 1 = Enables dynamic clock gating on the root port shared resource link clock domain.
Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for
ports 5–8.
Shared Resource Dynamic Backbone Clock Gate Enable (SRdBCGEN)—R/W.
0 = Disables dynamic clock gating of the shared resource backbone clock domain.
1 = Enables dynamic clock gating on the root port shared resource backbone clock
2
domain.
Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for
ports 5–8.
Root Port Dynamic Link Clock Gate Enable (RPDLCGEN)—R/W.
1 0 = Disables dynamic clock gating of the root port link clock domain.
1 = Enables dynamic clock gating on the root port link clock domain.
Root Port Dynamic Backbone Clock Gate Enable (RPdBCGEN)—R/W.
0 0 = Disables dynamic clock gating of the root port backbone clock domain.
1 = Enables dynamic clock gating on the root port backbone clock domain.
Datasheet 857
PCI Express* Configuration Registers
19.1.53 PECR3—PCI Express* Configuration Register 3
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: ECh–EFh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:2 Reserved
Subtractive Decode Compatibility Device ID (SDCDID)—R/W.
0 = This function reports the device Device ID value assigned to the PCI Express
Root Ports. See Section 1.3 for the value of the DID Register.
1
1 = This function reports a Device ID of 244Eh for desktop or 2448h for mobile.
If subtractive decode (SDE) is enabled, having this bit as '0' allows the function to
present a Device ID that is recognized by the operating system.
Subtractive Decode Enable (SDE)—R/W.
0 = Subtractive decode is disabled this function and will only claim transactions
positively.
1 = This port will subtractively forward transactions across the PCIe link downstream
0
memory and I/O transactions that are not positively claimed any internal device
or bridge.
Software must ensure that only one PCH device is enabled for Subtractive decode at
a time.
858 Datasheet
PCI Express* Configuration Registers
19.1.54 UES—Uncorrectable Error Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 104h–107h Attribute: R/WC, RO
Default Value: 00000000000x0xxx0x0x0000000x0000b Size: 32 bits
This register maintains its state through a platform reset. It loses its state upon
suspend.
Bit Description
31:21 Reserved
Unsupported Request Error Status (URE)—R/WC. Indicates an unsupported
20
request was received.
19 ECRC Error Status (EE)—RO. ECRC is not supported.
18 Malformed TLP Status (MT)—R/WC. Indicates a malformed TLP was received.
17 Receiver Overflow Status (RO)—R/WC. Indicates a receiver overflow occurred.
Unexpected Completion Status (UC)—R/WC. Indicates an unexpected completion
16
was received.
15 Completion Abort Status (CA)—R/WC. Indicates a completer abort was received.
Completion Timeout Status (CT)—R/WC. Indicates a completion timed out. This bit
14 is set if Completion Timeout is enabled and a completion is not returned within the time
specified by the Completion TImeout Value
Flow Control Protocol Error Status (FCPE)—RO. Flow Control Protocol Errors not
13
supported.
12 Poisoned TLP Status (PT)—R/WC. Indicates a poisoned TLP was received.
11:5 Reserved
Data Link Protocol Error Status (DLPE)—R/WC. Indicates a data link protocol error
4
occurred.
3:1 Reserved
0 Training Error Status (TE)—RO. Training Errors not supported.
Datasheet 859
PCI Express* Configuration Registers
19.1.55 UEM—Uncorrectable Error Mask Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 108h–10Bh Attribute: R/WO, RO
Default Value: 00000000h Size: 32 bits
When set, the corresponding error in the UES register is masked, and the logged error
will cause no action. When cleared, the corresponding error is enabled.
Bit Description
31:21 Reserved
Unsupported Request Error Mask (URE)—R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
20 enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
masked.
19 ECRC Error Mask (EE)—RO. ECRC is not supported.
Malformed TLP Mask (MT)—R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
18 enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
masked.
Receiver Overflow Mask (RO)—R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
17 enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
masked.
Unexpected Completion Mask (UC)—R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
16 enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
masked.
Completion Abort Mask (CA)—R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
15 enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
masked.
Completion Timeout Mask (CT)—R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
14 enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
masked.
Flow Control Protocol Error Mask (FCPE)—RO. Flow Control Protocol Errors not
13
supported.
Poisoned TLP Mask (PT)—R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
12 enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
masked.
11:5 Reserved
Data Link Protocol Error Mask (DLPE)—R/WO.
0 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
4 enabled.
1 = The corresponding error in the UES register (D28:F0/F1/F2/F3/F4/F5/F6/F7:144) is
masked.
3:1 Reserved
0 Training Error Mask (TE)—RO. Training Errors not supported
860 Datasheet
PCI Express* Configuration Registers
19.1.56 UEV—Uncorrectable Error Severity Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 10Ch–10Fh Attribute: RO, R/W
Default Value: 00060011h Size: 32 bits
Bit Description
31:21 Reserved
Unsupported Request Error Severity (URE)—R/W.
20 0 = Error considered non-fatal. (Default)
1 = Error is fatal.
19 ECRC Error Severity (EE)—RO. ECRC is not supported.
Malformed TLP Severity (MT)—R/W.
18 0 = Error considered non-fatal.
1 = Error is fatal. (Default)
Receiver Overflow Severity (RO)—R/W.
17 0 = Error considered non-fatal.
1 = Error is fatal. (Default)
16 Reserved
Completion Abort Severity (CA)—R/W.
15 0 = Error considered non-fatal. (Default)
1 = Error is fatal.
14 Reserved
Flow Control Protocol Error Severity (FCPE)—RO. Flow Control Protocol Errors not
13
supported.
Poisoned TLP Severity (PT)—R/W.
12 0 = Error considered non-fatal. (Default)
1 = Error is fatal.
11:5 Reserved
Data Link Protocol Error Severity (DLPE)—R/W.
4 0 = Error considered non-fatal.
1 = Error is fatal. (Default)
3:1 Reserved
0 Training Error Severity (TE)—R/W. TE is not supported.
Datasheet 861
PCI Express* Configuration Registers
19.1.57 CES—Correctable Error Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 110h–113h Attribute: R/WC
Default Value: 00000000h Size: 32 bits
Bit Description
31:14 Reserved
Advisory Non-Fatal Error Status (ANFES)—R/WC.
13 0 = Advisory Non-Fatal Error did not occur.
1 = Advisory Non-Fatal Error did occur.
12 Replay Timer Timeout Status (RTT)—R/WC. Indicates the replay timer timed out.
11:9 Reserved
Replay Number Rollover Status (RNR)—R/WC. Indicates the replay number rolled
8
over.
7 Bad DLLP Status (BD)—R/WC. Indicates a bad DLLP was received.
6 Bad TLP Status (BT)—R/WC. Indicates a bad TLP was received.
5:1 Reserved
0 Receiver Error Status (RE)—R/WC. Indicates a receiver error occurred.
19.1.58 CEM—Correctable Error Mask Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 114h–117h Attribute: R/WO
Default Value: 00002000h Size: 32 bits
When set, the corresponding error in the CES register is masked, and the logged error
will cause no action. When cleared, the corresponding error is enabled.
Bit Description
31:14 Reserved
Advisory Non-Fatal Error Mask (ANFEM)—R/WO.
0 = Does not mask Advisory Non-Fatal errors.
1 = Masks Advisory Non-Fatal errors from (a) signaling ERR_COR to the device control
register and (b) updating the Uncorrectable Error Status register.
13
This register is set by default to enable compatibility with software that does not
comprehend Role-Based Error Reporting.
NOTE: The correctable error detected bit in device status register is set whenever the
Advisory Non-Fatal error is detected, independent of this mask bit.
12 Replay Timer Timeout Mask (RTT)—R/WO. Mask for replay timer timeout.
11:9 Reserved
8 Replay Number Rollover Mask (RNR)—R/WO. Mask for replay number rollover.
7 Bad DLLP Mask (BD)—R/WO. Mask for bad DLLP reception.
6 Bad TLP Mask (BT)—R/WO. Mask for bad TLP reception.
5:1 Reserved
0 Receiver Error Mask (RE)—R/WO. Mask for receiver errors.
862 Datasheet
PCI Express* Configuration Registers
19.1.59 AECC—Advanced Error Capabilities and Control Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 118h–11Bh Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:9 Reserved
8 ECRC Check Enable (ECE)—RO. ECRC is not supported.
7 ECRC Check Capable (ECC)—RO. ECRC is not supported.
6 ECRC Generation Enable (EGE)—RO. ECRC is not supported.
5 ECRC Generation Capable (EGC)—RO. ECRC is not supported.
First Error Pointer (FEP)—RO. Identifies the bit position of the last error reported in the
4:0
Uncorrectable Error Status Register.
19.1.60 RES—Root Error Status Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 130h–133h Attribute: R/WC, RO
Default Value: 00000000h Size: 32 bits
Bit Description
Advanced Error Interrupt Message Number (AEMN)—RO. There is only one error
31:27
interrupt allocated.
26:7 Reserved
Fatal Error Messages Received (FEMR)—RO. Set when one or more Fatal
6
Uncorrectable Error Messages have been received.
Non-Fatal Error Messages Received (NFEMR)—RO. Set when one or more Non-
5
Fatal Uncorrectable error messages have been received
First Uncorrectable Fatal (FUF)—RO. Set when the first Uncorrectable Error
4
message received is for a fatal error.
Multiple ERR_FATAL/NONFATAL Received (MENR)—RO. For the PCH, only one
3
error will be captured.
ERR_FATAL/NONFATAL Received (ENR)—R/WC.
2 0 = No error message received.
1 = Either a fatal or a non-fatal error message is received.
Multiple ERR_COR Received (MCR)—RO. For the PCH, only one error will be
1
captured.
ERR_COR Received (CR)—R/WC.
0 0 = No error message received.
1 = A correctable error message is received.
Datasheet 863
PCI Express* Configuration Registers
19.1.61 PECR2—PCI Express* Configuration Register 2
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 320–323h Attribute: R/W
Default Value: 0004B05Bh Size: 32 bits
Bit Description
31:20 Reserved
21 PECR2 Field 1—R/W. BIOS must set this bit to 1b.
20:0 Reserved
19.1.62 PEETM—PCI Express* Extended Test Mode Register
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 324h–327h Attribute: RO
Default Value: See Description Size: 32 bits
Bit Description
31:5 Reserved
Lane Reversal (LR)—RO.
This register reads the setting of the PCIELR1 soft strap for port 1 and the PCIELR2 soft
strap for port 5.
0 = No Lane reversal (default).
1 = PCI Express lanes 0-3 (register in port 1) or lanes 4-7 (register in port 5) are
4 reversed.
NOTES:
1. The port configuration straps must be set such that Port 1 or Port 5 is configured
as a x4 port using lanes 0–3, or 4–7 when Lane Reversal is enabled. x2 lane
reversal is not supported.
2. This register is only valid on port 1 (for ports 1–4) or port 5 (for ports 5–8).
3 Reserved
Scrambler Bypass Mode (BAU)—R/W.
0 = Normal operation. Scrambler and descrambler are used.
1 = Bypasses the data scrambler in the transmit direction and the data de-scrambler in
2 the receive direction.
NOTE: This functionality intended for debug/testing only.
NOTE: If bypassing scrambler with the PCH root port 1 in x4 configuration, each PCH
root port must have this bit set.
1:0 Reserved
19.1.63 PEC1—PCI Express* Configuration Register 1
(PCI Express*—D28:F0/F1/F2/F3/F4/F5/F6/F7)
Address Offset: 330h–333h Attribute: RO, R/W
Default Value: 28000016h Size: 32 bits
Bit Description
31:8 Reserved
7:0 PEC1 Field 1—R/W. BIOS must program this field to 40h.
§§
864 Datasheet
High Precision Event Timer Registers
20 High Precision Event Timer
Registers
The timer registers are memory-mapped in a non-indexed scheme. This allows the
processor to directly access each register without having to use an index register. The
timer register space is 1024 bytes. The registers are generally aligned on 64-bit
boundaries to simplify implementation with IA64 processors. There are four possible
memory address ranges beginning at 1) FED0_0000h, 2) FED0_1000h, 3)
FED0_2000h, 4) FED0_3000h. The choice of address range will be selected by
configuration bits in the High Precision Timer Configuration Register (Chipset Config
Registers:Offset 3404h).
Behavioral Rules:
1. Software must not attempt to read or write across register boundaries. For
example, a 32-bit access should be to offset x0h, x4h, x8h, or xCh. 32-bit accesses
should not be to 01h, 02h, 03h, 05h, 06h, 07h, 09h, 0Ah, 0Bh, 0Dh, 0Eh, or 0Fh.
Any accesses to these offsets will result in an unexpected behavior, and may result
in a master abort. However, these accesses should not result in system hangs. 64-
bit accesses can only be to x0h and must not cross 64-bit boundaries.
2. Software should not write to Read Only registers.
3. Software should not expect any particular or consistent value when reading
reserved registers or bits.
20.1 Memory Mapped Registers
Table 20-1. Memory-Mapped Register Address Map (Sheet 1 of 2)
Offset Mnemonic Register Default Attribute
General Capabilities and 0429B17F80
000h–007h GCAP_ID RO
Identification 86A201h
008h–00Fh — Reserved — —
0000000000
010h–017h GEN_CONF General Configuration R/W
000000h
018h–01Fh — Reserved — —
0000000000
020h–027h GINTR_STA General Interrupt Status R/WC
000000h
028h–0EFh — Reserved — —
0F0h–0F7h MAIN_CNT Main Counter Value N/A R/W
0F8h–0FFh — Reserved — —
Timer 0 Configuration and
100h–107h TIM0_CONF N/A R/W, RO
Capabilities
108h–10Fh TIM0_COMP Timer 0 Comparator Value N/A R/W
110h–11Fh — Reserved — —
Timer 1 Configuration and
120h–127h TIM1_CONF N/A R/W, RO
Capabilities
Datasheet 865
High Precision Event Timer Registers
Table 20-1. Memory-Mapped Register Address Map (Sheet 2 of 2)
Offset Mnemonic Register Default Attribute
128h–12Fh TIM1_COMP Timer 1 Comparator Value N/A R/W
130h–13Fh — Reserved — —
Timer 2 Configuration and
140h–147h TIM2_CONF N/A R/W, RO
Capabilities
148h–14Fh TIM2_COMP Timer 2 Comparator Value N/A R/W
150h–15Fh — Reserved — —
Timer 3 Configuration and
160h–167h TIM3_CONG N/A R/W, RO
Capabilities
168h–16Fh TIM3_COMP Timer 3 Comparator Value N/A R/W
Timer 4 Configuration and
180h–187h TIM4_CONG N/A R/W, RO
Capabilities
188h–18Fh TIM4_COMP Timer 4 Comparator Value N/A R/W
190h–19Fh — Reserved — —
Timer 5 Configuration and
1A0h–1A7h TIM5_CONG N/A R/W, RO
Capabilities
1A8h–1AFh TIM5_COMP Timer 5 Comparator Value N/A R/W
1B0h–1BFh — Reserved — —
Timer 6 Configuration and
1C0h–1C7h TIM6_CONG N/A R/W, RO
Capabilities
1C8h–1CFh TIM6_COMP Timer 6 Comparator Value N/A R/W
1D0h–1DFh — Reserved — —
Timer 7 Configuration and
1E0h–1E7h TIM7_CONG N/A R/W, RO
Capabilities
1E8h–1EFh TIM7_COMP Timer 7 Comparator Value N/A R/W
1F0h–19Fh — Reserved — —
200h–3FFh — Reserved — —
NOTES:
1. Reads to reserved registers or bits will return a value of 0.
2. Software must not attempt locks to the memory-mapped I/O ranges for High Precision
Event Timers. If attempted, the lock is not honored, which means potential deadlock
conditions may occur.
866 Datasheet
High Precision Event Timer Registers
20.1.1 GCAP_ID—General Capabilities and Identification Register
Address Offset: 00h Attribute: RO
Default Value: 0429B17F8086A201h Size: 64 bits
Bit Description
Main Counter Tick Period (COUNTER_CLK_PER_CAP)—RO. This field indicates the
period at which the counter increments in femptoseconds (10^-15 seconds). This will
63:32
return 0429B17Fh when read. This indicates a period of 69841279 fs
(69.841279 ns).
31:16 Vendor ID Capability (VENDOR_ID_CAP)—RO. This is a 16-bit value assigned to Intel.
Legacy Replacement Rout Capable (LEG_RT_CAP)—RO. Hardwired to 1. Legacy
15
Replacement Interrupt Rout option is supported.
14 Reserved. This bit returns 0 when read.
Counter Size Capability (COUNT_SIZE_CAP)—RO. Hardwired to 1. Counter is 64-bit
13
wide.
Number of Timer Capability (NUM_TIM_CAP)—RO. This field indicates the number of
12:8 timers in this block.
07h = Eight timers.
Revision Identification (REV_ID)—RO. This indicates which revision of the function is
7:0
implemented. Default value will be 01h.
20.1.2 GEN_CONF—General Configuration Register
Address Offset: 010h Attribute: R/W
Default Value: 00000000 00000000h Size: 64 bits
Bit Description
63:2 Reserved. These bits return 0 when read.
Legacy Replacement Rout (LEG_RT_CNF)—R/W. If the ENABLE_CNF bit and the
LEG_RT_CNF bit are both set, then the interrupts will be routed as follows:
• Timer 0 is routed to IRQ0 in 8259 or IRQ2 in the I/O APIC
• Timer 1 is routed to IRQ8 in 8259 or IRQ8 in the I/O APIC
• Timer 2-n is routed as per the routing in the timer n config registers.
1 • If the Legacy Replacement Rout bit is set, the individual routing bits for Timers 0 and 1 (APIC)
will have no impact.
• If the Legacy Replacement Rout bit is not set, the individual routing bits for each of the timers
are used.
• This bit will default to 0. BIOS can set it to 1 to enable the legacy replacement routing, or 0 to
disable the legacy replacement routing.
Overall Enable (ENABLE_CNF)—R/W. This bit must be set to enable any of the
timers to generate interrupts. If this bit is 0, then the main counter will halt (will not
increment) and no interrupts will be caused by any of these timers. For level-triggered
interrupts, if an interrupt is pending when the ENABLE_CNF bit is changed from 1 to 0,
0
the interrupt status indications (in the various Txx_INT_STS bits) will not be cleared.
Software must write to the Txx_INT_STS bits to clear the interrupts.
NOTE: This bit will default to 0. BIOS can set it to 1 or 0.
Datasheet 867
High Precision Event Timer Registers
20.1.3 GINTR_STA—General Interrupt Status Register
Address Offset: 020h Attribute: R/WC
Default Value: 00000000 00000000h Size: 64 bits
.
Bit Description
63:8 Reserved. These bits will return 0 when read.
7 Timer 7 Interrupt Active (T07_INT_STS)—R/WC. Same functionality as Timer 0.
6 Timer 6 Interrupt Active (T06_INT_STS)—R/WC. Same functionality as Timer 0.
5 Timer 5 Interrupt Active (T05_INT_STS)—R/WC. Same functionality as Timer 0.
4 Timer 4 Interrupt Active (T04_INT_STS)—R/WC. Same functionality as Timer 0.
3 Timer 3 Interrupt Active (T03_INT_STS)—R/WC. Same functionality as Timer 0.
2 Timer 2 Interrupt Active (T02_INT_STS)—R/WC. Same functionality as Timer 0.
1 Timer 1 Interrupt Active (T01_INT_STS)—R/WC. Same functionality as Timer 0.
Timer 0 Interrupt Active (T00_INT_STS)—R/WC. The functionality of this bit
depends on whether the edge or level-triggered mode is used for this timer.
(default = 0)
If set to level-triggered mode:
This bit will be set by hardware if the corresponding timer interrupt is active. Once
the bit is set, it can be cleared by software writing a 1 to the same bit position.
0 Writes of 0 to this bit will have no effect.
If set to edge-triggered mode:
This bit should be ignored by software. Software should always write 0 to this bit.
NOTE: Defaults to 0. In edge triggered mode, this bit will always read as 0 and writes
will have no effect.
20.1.4 MAIN_CNT—Main Counter Value Register
Address Offset: 0F0h Attribute: R/W
Default Value: N/A Size: 64 bits
.
Bit Description
Counter Value (COUNTER_VAL[63:0])—R/W. Reads return the current value of the
counter. Writes load the new value to the counter.
NOTES:
1. Writes to this register should only be done while the counter is halted.
2. Reads to this register return the current value of the main counter.
3. 32-bit counters will always return 0 for the upper 32-bits of this register.
63:0 4. If 32-bit software attempts to read a 64-bit counter, it should first halt the counter.
Since this delays the interrupts for all of the timers, this should be done only if the
consequences are understood. It is strongly recommended that 32-bit software only
operate the timer in 32-bit mode.
5. Reads to this register are monotonic. No two consecutive reads return the same
value. The second of two reads always returns a larger value (unless the timer has
rolled over to 0).
868 Datasheet
High Precision Event Timer Registers
20.1.5 TIMn_CONF—Timer n Configuration and Capabilities
Register
Address Offset: Timer 0: 100–107h Attribute: RO, R/W
Timer 1: 120–127h
Timer 2: 140–147h
Timer 3: 160–167h
Timer 4: 180–187h
Timer 5: 1A0–1A7h
Timer 6: 1C0–1C7h
Timer 7: 1E0–1E7h
Default Value: N/A Size: 64 bit
Note: The letter n can be 0, 1, 2, 3, 4, 5, 6, or 7 referring to Timer 0, 1, 2, 3, 4, 5, 6, or 7.
Bit Description
63:56 Reserved. These bits will return 0 when read.
Timer Interrupt Rout Capability (TIMERn_INT_ROUT_CAP)—RO.
Timer 0, 1:Bits 52, 53, 54, and 55 in this field (corresponding to IRQ 20, 21, 22, and
23) have a value of 1. Writes will have no effect.
Timer 2:Bits 43, 52, 53, 54, and 55 in this field (corresponding to IRQ 11, 20, 21, 22,
and 23) have a value of 1. Writes will have no effect.
55:52, Timer 3:Bits 44, 52, 53, 54, and 55 in this field (corresponding to IRQ 11, 20, 21, 22,
44,43 and 23) have a value of 1. Writes will have no effect.
Timer 4, 5, 6, 7:This field is always 0 as interrupts from these timers can only be
delivered using direct processor interrupt messages.
NOTE: If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared
with any other devices to ensure the proper operation of HPET #2.
NOTE: If IRQ 12 is used for HPET #3, software should ensure IRQ 12 is not shared
with any other devices to ensure the proper operation of HPET #3.
51:45,
Reserved. These bits return 0 when read.
42:16
Timer n Processor Message Interrupt Delivery (Tn_PROCMSG_INT_DEL_CAP)—RO.
15 This bit is always read as ‘1’, since the PCH HPET implementation supports the direct
processor interrupt delivery.
Timer n Processor Message Interrupt Enable (Tn_PROCMSG_EN_CNF)—R/W
/ RO. If the Tn_PROCMSG_INT_DEL_CAP bit is set for this timer, then the software
can set the Tn_PROCMSG_EN_CNF bit to force the interrupts to be delivered directly
as processor messages, rather than using the 8259 or I/O (x) APIC. In this case, the
14 Tn_INT_ROUT_CNF field in this register will be ignored. The Tn_PROCMSG_ROUT
register will be used instead.
Timer 0, 1, 2, 3 Specific: This bit is a read/write bit.
Timer 4, 5, 6, 7 Specific: This bit is always Read Only ‘1’ as interrupt from these
timers can only be delivered using direct processor interrupt messages.
Datasheet 869
High Precision Event Timer Registers
Bit Description
Timer n Interrupt Rout (Tn_INT_ROUT_CNF)—R/W / RO. This 5-bit field
indicates the routing for the interrupt to the 8259 or I/O (x) APIC. Software writes to
this field to select which interrupt in the 8259 or I/O (x) will be used for this timer’s
interrupt. If the value is not supported by this particular timer, then the value read
back will not match what is written. The software must only write valid values.
Timer 4, 5, 6, 7: This field is Read Only and reads will return 0.
NOTES:
1. If the interrupt is handled using the 8259, only interrupts 0–15 are applicable and
valid. Software must not program any value other than 0–15 in this field.
2. If the Legacy Replacement Rout bit is set, then Timers 0 and 1 will have a
13:9 different routing, and this bit field has no effect for those two timers.
3. Timer 0,1: Software is responsible to make sure it programs a valid value (20, 21,
22, or 23) for this field. The PCH logic does not check the validity of the value
written.
4. Timer 2: Software is responsible to make sure it programs a valid value (11, 20,
21, 22, or 23) for this field. The PCH logic does not check the validity of the value
written.
5. Timer 3: Software is responsible to make sure it programs a valid value (12, 20,
21, 22, or 23) for this field. The PCH logic does not check the validity of the value
written.
6. Timers 4, 5, 6, 7: This field is always Read Only 0 as interrupts from these timers
can only be delivered using direct processor interrupt messages.
Timer n 32-bit Mode (TIMERn_32MODE_CNF)—R/W or RO. Software can set this
bit to force a 64-bit timer to behave as a 32-bit timer.
Timer 0:Bit is read/write (default to 0). 0 = 64 bit; 1 = 32 bit
Timers 1, 2, 3, 4, 5, 6, 7:Hardwired to 0. Writes have no effect (since these seven
8 timers are 32-bits).
NOTE: When this bit is set to 1, the hardware counter will do a 32-bit operation on
comparator match and rollovers; thus, the upper 32-bit of the Timer 0
Comparator Value register is ignored. The upper 32-bit of the main counter is
not involved in any rollover from lower 32-bit of the main counter and
becomes all zeros.
7 Reserved. This bit returns 0 when read.
Timer n Value Set (TIMERn_VAL_SET_CNF)—R/W. Software uses this bit only for
Timer 0 if it has been set to periodic mode. By writing this bit to a 1, the software is
then allowed to directly set the timer’s accumulator. Software does not have to write
this bit back to 1 (it automatically clears).
6 Software should not write a 1 to this bit position if the timer is set to non-periodic
mode.
NOTE: This bit will return 0 when read. Writes will only have an effect for Timer 0 if it
is set to periodic mode. Writes will have no effect for Timers 1, 2, 3, 4, 5, 6,
7.
Timer n Size (TIMERn_SIZE_CAP)—RO. This read only field indicates the size of
the timer.
5
Timer 0:Value is 1 (64-bits).
Timers 1, 2, 3, 4, 5, 6, 7: Value is 0 (32-bits).
Periodic Interrupt Capable (TIMERn_PER_INT_CAP)—RO. If this bit is 1, the
hardware supports a periodic mode for this timer’s interrupt.
4
Timer 0: Hardwired to 1 (supports the periodic interrupt).
Timers 1, 2, 3, 4, 5, 6, 7: Hardwired to 0 (does not support periodic interrupt).
Timer n Type (TIMERn_TYPE_CNF)—R/W or RO.
Timer 0:Bit is read/write. 0 = Disable timer to generate periodic interrupt; 1 =
3
Enable timer to generate a periodic interrupt.
Timers 1, 2, 3, 4, 5, 6, 7: Hardwired to 0. Writes have no affect.
870 Datasheet
High Precision Event Timer Registers
Bit Description
Timer n Interrupt Enable (TIMERn_INT_ENB_CNF)—R/W. This bit must be set
to enable timer n to cause an interrupt when it times out.
2 0 = Disable (Default). The timer can still count and generate appropriate status bits,
but will not cause an interrupt.
1 = Enable.
Timer Interrupt Type (TIMERn_INT_TYPE_CNF)—R/W.
0 = The timer interrupt is edge triggered. This means that an edge-type interrupt is
generated. If another interrupt occurs, another edge will be generated.
1 = The timer interrupt is level triggered. This means that a level-triggered interrupt
1
is generated. The interrupt will be held active until it is cleared by writing to the
bit in the General Interrupt Status Register. If another interrupt occurs before the
interrupt is cleared, the interrupt will remain active.
Timer 4, 5, 6, 7: This bit is Read Only, and will return 0 when read
0 Reserved. These bits will return 0 when read.
NOTE: Reads or writes to unimplemented timers should not be attempted. Read from any
unimplemented registers will return an undetermined value.
Datasheet 871
High Precision Event Timer Registers
20.1.6 TIMn_COMP—Timer n Comparator Value Register
Address Offset: Timer 0: 108h–10Fh,
Timer 1: 128h–12Fh,
Timer 2: 148h–14Fh,
Timer 3: 168h–16Fh,
Timer 4: 188h–18Fh,
Timer 5: 1A8h–1AFh,
Timer 6: 1C8h–1CFh,
Timer 7: 1E8h–1EFh
Attribute: R/W
Default Value: N/A Size: 64 bit
Bit Description
Timer Compare Value—R/W. Reads to this register return the current value of the
comparator
If Timer n is configured to non-periodic mode:
Writes to this register load the value against which the main counter should be
compared for this timer.
• When the main counter equals the value last written to this register, the corresponding
interrupt can be generated (if so enabled).
• The value in this register does not change based on the interrupt being generated.
If Timer 0 is configured to periodic mode:
• When the main counter equals the value last written to this register, the corresponding
interrupt can be generated (if so enabled).
• After the main counter equals the value in this register, the value in this register is increased
by the value last written to the register.
63:0
For example, if the value written to the register is 00000123h, then
1. An interrupt will be generated when the main counter reaches 00000123h.
2. The value in this register will then be adjusted by the hardware to 00000246h.
3. Another interrupt will be generated when the main counter reaches 00000246h
4. The value in this register will then be adjusted by the hardware to 00000369h
• As each periodic interrupt occurs, the value in this register will increment. When the
incremented value is greater than the maximum value possible for this register (FFFFFFFFh
for a 32-bit timer or FFFFFFFFFFFFFFFFh for a 64-bit timer), the value will wrap around
through 0. For example, if the current value in a 32-bit timer is FFFF0000h and the last value
written to this register is 20000h, then after the next interrupt the value will change to
00010000h
Default value for each timer is all 1s for the bits that are implemented. For example,
a 32-bit timer has a default value of 00000000FFFFFFFFh. A 64-bit timer has a
default value of FFFFFFFFFFFFFFFFh.
872 Datasheet
High Precision Event Timer Registers
20.1.7 TIMERn_PROCMSG_ROUT—Timer n Processor Message
Interrupt Rout Register
Address Offset: Timer 0: 110–117h, Attribute: R/W
Timer 1: 130–137h,
Timer 2: 150–157h,
Timer 3: 170–177h,
Timer 4: 190–197h,
Timer 5: 1B0–1B7h,
Timer 6: 1D0–1D7h,
Timer 7: 1F0–1F7h,
Default Value: N/A Size: 64 bit
Note: The letter n can be 0, 1, 2, 3, 4, 5, 6, or 7 referring to Timer 0, 1, 2, 3, 4, 5, 6, or 7.
Software can access the various bytes in this register using 32-bit or 64-bit accesses.
32-bit accesses can be done to offset 1x0h or 1x4h. 64-bit accesses can be done to
1x0h. 32-bit accesses must not be done to offsets 1x1h, 1x2h, 1x3h, 1x5h, 1x6h, or
1x7h.
Bit Description
Tn_PROCMSG_INT_ADDR—R/W. Software sets this 32-bit field to indicate the
63:32
location that the direct processor interrupt message should be written.
Tn_PROCMSG_INT_VAL—R/W. Software sets this 32-bit field to indicate that value
31:0
that is written during the direct processor interrupt message.
§§
Datasheet 873
High Precision Event Timer Registers
874 Datasheet
Serial Peripheral Interface (SPI)
21 Serial Peripheral Interface
(SPI)
The Serial Peripheral Interface resides in memory mapped space. This function contains
registers that allow for the setup and programming of devices that reside on the SPI
interface.
Note: All registers in this function (including memory-mapped registers) must be addressable
in byte, word, and DWord quantities. The software must always make register accesses
on natural boundaries (that is, DWord accesses must be on DWord boundaries; word
accesses on word boundaries, and so on) In addition, the memory-mapped register
space must not be accessed with the LOCK semantic exclusive-access mechanism. If
software attempts exclusive-access mechanisms to the SPI memory-mapped space,
the results are undefined.
21.1 Serial Peripheral Interface Memory Mapped
Configuration Registers
The SPI Host Interface registers are memory-mapped in the RCRB (Root Complex
Register Block) Chipset Register Space with a base address (SPIBAR) of 3800h and are
located within the range of 3800h to 39FFh. The address for RCRB are in the RCBA
Register (see Section 12.1.40). The individual registers are then accessible at SPIBAR
+ Offset as indicated in the following table.
These memory mapped registers must be accessed in byte, word, or DWord quantities.
Table 21-1. Serial Peripheral Interface (SPI) Register Address Map
(SPI Memory Mapped Configuration Registers) (Sheet 1 of 2)
SPIBAR +
Mnemonic Register Name Default
Offset
00h–03h BFPR BIOS Flash Primary Region 00000000h
04h–05h HSFS Hardware Sequencing Flash Status 0000h
06h–07h HSFC Hardware Sequencing Flash Control 0000h
08h–0Bh FADDR Flash Address 00000000h
0Ch–0Fh — Reserved 00000000h
10h–13h FDATA0 Flash Data 0 00000000h
14h–4Fh FDATAN Flash Data N 00000000h
50h–53h FRAP Flash Region Access Permissions 00000202h
54h–57h FREG0 Flash Region 0 00000000h
58h–5Bh FREG1 Flash Region 1 00000000h
5Ch–5Fh FREG2 Flash Region 2 00000000h
60h–63h FREG3 Flash Region 3 00000000h
64h–67h FREG4 Flash Region 4 00000000h
67h–73h — Reserved for Future Flash Regions
74h–77h PR0 Flash Protected Range 0 00000000h
Datasheet 875
Serial Peripheral Interface (SPI)
Table 21-1. Serial Peripheral Interface (SPI) Register Address Map
(SPI Memory Mapped Configuration Registers) (Sheet 2 of 2)
SPIBAR +
Mnemonic Register Name Default
Offset
78h–7Bh PR1 Flash Protected Range 1 00000000h
7Ch–7Fh PR2 Flash Protected Range 2 00000000h
80h–83h PR3 Flash Protected Range 3 00000000h
84h–87h PR4 Flash Protected Range 4 00000000h
88h–8Fh — Reserved —
90h SSFS Software Sequencing Flash Status 00h
91h–93h SSFC Software Sequencing Flash Control 0000h
94h–95h PREOP Prefix Opcode Configuration 0000h
96h–97h OPTYPE Opcode Type Configuration 0000h
0000000000000
98h–9Fh OPMENU Opcode Menu Configuration
000h
A0h BBAR BIOS Base Address Configuration 00000000h
B0h–B3h FDOC Flash Descriptor Observability Control 00000000h
B4h–B7h FDOD Flash Descriptor Observability Data 00000000h
B8h–C3h — Reserved —
C0h–C3h AFC Additional Flash Control 00000000h
Host Lower Vendor Specific Component
C4h–C7h LVSCC 00000000h
Capabilities
Host Upper Vendor Specific Component
C8h–C11h UVSCC 00000000h
Capabilities
D0h–D3h FPB Flash Partition Boundary 00000000h
F0h–F3h SRDL Soft Reset Data Lock 00000000h
F4h–F7h SRDC Soft Reset Data Control 00000000h
F8h–FBh SRD Soft Reset Data 00000000h
876 Datasheet
Serial Peripheral Interface (SPI)
21.1.1 BFPR –BIOS Flash Primary Region Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 00h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
Bit Description
31:29 Reserved
BIOS Flash Primary Region Limit (PRL)—RO. This specifies address bits 24:12 for
the Primary Region Limit.
28:16
The value in this register loaded from the contents in the Flash
Descriptor.FLREG1.Region Limit
15:13 Reserved
BIOS Flash Primary Region Base (PRB)—RO. This specifies address bits 24:12 for
the Primary Region Base
12:0
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Base
21.1.2 HSFS—Hardware Sequencing Flash Status Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 04h Attribute: RO, R/WC, R/W
Default Value: 0000h Size: 16 bits
Bit Description
Flash Configuration Lock-Down (FLOCKDN)—R/W/L. When set to 1, those Flash
Program Registers that are locked down by this FLOCKDN bit cannot be written. Once
15
set to 1, this bit can only be cleared by a hardware reset due to a global reset or host
partition reset in an Intel ME enabled system.
Flash Descriptor Valid (FDV)—RO. This bit is set to a 1 if the Flash Controller read
the correct Flash Descriptor Signature.
14 If the Flash Descriptor Valid bit is not 1, software cannot use the Hardware Sequencing
registers, but must use the software sequencing registers. Any attempt to use the
Hardware Sequencing registers will result in the FCERR bit being set.
Flash Descriptor Override Pin Strap Status (FDOPSS)—RO. This bit indicates the
condition of the Flash Descriptor Security Override / Intel ME Debug Mode pin strap.
13 0 = The Flash Descriptor Security Override / Intel ME Debug Mode strap is set using
external pull-up on HDA_SDO
1 = No override
12:6 Reserved
SPI Cycle In Progress (SCIP)—RO. Hardware sets this bit when software sets the
Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit
remains set until the cycle completes on the SPI interface. Hardware automatically sets
and clears this bit so that software can determine when read data is valid and/or when
5
it is safe to begin programming the next command. Software must only program the
next command when this bit is 0.
NOTE: This field is only applicable when in Descriptor mode and Hardware sequencing
is being used.
Datasheet 877
Serial Peripheral Interface (SPI)
Bit Description
Block/Sector Erase Size (BERASE)—RO. This field identifies the erasable sector size
for all Flash components.
Valid Bit Settings:
00 = 256 Byte
01 = 4 K Byte
10 = 8 K Byte
4:3 11 = 64 K Byte
If the FLA is less than FPBA, then this field reflects the value in the LVSCC.LBES
register.
If the FLA is greater or equal to FPBA, then this field reflects the value in the
UVSCC.UBES register.
NOTE: This field is only applicable when in Descriptor mode and Hardware sequencing
is being used.
Access Error Log (AEL)—R/W/C. Hardware sets this bit to a 1 when an attempt was
made to access the BIOS region using the direct access method or an access to the
BIOS Program Registers that violated the security restrictions. This bit is simply a log of
2
an access security violation. This bit is cleared by software writing a 1.
NOTE: This field is only applicable when in Descriptor mode and Hardware sequencing
is being used.
Flash Cycle Error (FCERR)—R/W/C. Hardware sets this bit to 1 when an program
register access is blocked to the FLASH due to one of the protection policies or when
any of the programmed cycle registers is written while a programmed access is already
in progress. This bit remains asserted until cleared by software writing a 1 or until
1 hardware reset occurs due to a global reset or host partition reset in an Intel ME
enabled system. Software must clear this bit before setting the FLASH Cycle GO bit in
this register.
NOTE: This field is only applicable when in Descriptor mode and Hardware sequencing
is being used.
Flash Cycle Done (FDONE)—R/W/C. The PCH sets this bit to 1 when the SPI Cycle
completes after software previously set the FGO bit. This bit remains asserted until
cleared by software writing a 1 or hardware reset due to a global reset or host partition
reset in an Intel ME enabled system. When this bit is set and the SPI SMI# Enable bit is
0 set, an internal signal is asserted to the SMI# generation block. Software must make
sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed
access.
NOTE: This field is only applicable when in Descriptor mode and Hardware sequencing
is being used.
878 Datasheet
Serial Peripheral Interface (SPI)
21.1.3 HSFC—Hardware Sequencing Flash Control Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 06h Attribute: R/W, R/WS
Default Value: 0000h Size: 16 bits
Note: This register is only applicable when SPI device is in descriptor mode.
Bit Description
Flash SPI SMI# Enable (FSMIE)—R/W. When set to 1, the SPI asserts an SMI#
15
request whenever the Flash Cycle Done bit is 1.
14 Reserved
Flash Data Byte Count (FdBC)—R/W. This field specifies the number of bytes to shift
in or out during the data portion of the SPI cycle. The contents of this register are 0s
13:8 based with 0b representing 1 byte and 111111b representing 64 bytes. The number of
bytes transferred is the value of this field plus 1.
This field is ignored for the Block Erase command.
7:3 Reserved
FLASH Cycle (FCYCLE)—R/W. This field defines the Flash SPI cycle type generated to
the FLASH when the FGO bit is set as defined below:
00 = Read (1 up to 64 bytes by setting FdBC)
2:1
01 = Reserved
10 = Write (1 up to 64 bytes by setting FdBC)
11 = Block Erase
Flash Cycle Go (FGO)—R/W/S. A write to this register with a 1 in this bit initiates a
request to the Flash SPI Arbiter to start a cycle. This register is cleared by hardware
when the cycle is granted by the SPI arbiter to run the cycle on the SPI bus. When the
cycle is complete, the FDONE bit is set.
Software is forbidden to write to any register in the HSFLCTL register between the FGO
0 bit getting set and the FDONE bit being cleared. Any attempt to violate this rule will be
ignored by hardware.
Hardware allows other bits in this register to be programmed for the same transaction
when writing this bit to 1. This saves an additional memory write.
This bit always returns 0 on reads.
21.1.4 FADDR—Flash Address Register
(SPI Memory Mapped Configuration Registers)
Memory Address:SPIBAR + 08h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:25 Reserved
Flash Linear Address (FLA)—R/W. The FLA is the starting byte linear address of a
SPI Read or Write cycle or an address within a Block for the Block Erase command. The
24:0 Flash Linear Address must fall within a region for which BIOS has access permissions.
Hardware must convert the FLA into a Flash Physical Address (FPA) before running this
cycle on the SPI bus.
Datasheet 879
Serial Peripheral Interface (SPI)
21.1.5 FDATA0—Flash Data 0 Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 10h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Flash Data 0 (FD0)—R/W. This field is shifted out as the SPI Data on the Master-Out
Slave-In Data pin during the data portion of the SPI cycle.
This register also shifts in the data from the Master-In Slave-Out pin into this register
during the data portion of the SPI cycle.
The data is always shifted starting with the least significant byte, msb to lsb, followed
31:0 by the next least significant byte, msb to lsb, and so on. Specifically, the shift order on
SPI in terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-…8-23-22-…16-
31…24 Bit 24 is the last bit shifted out/in. There are no alignment assumptions; byte 0
always represents the value specified by the cycle address.
The data in this register may be modified by the hardware during any programmed SPI
transaction. Direct Memory Reads do not modify the contents of this register.
21.1.6 FDATAN—Flash Data [N] Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 14h Attribute: R/W
SPIBAR + 18h
SPIBAR + 1Ch
SPIBAR + 20h
SPIBAR + 24h
SPIBAR + 28h
SPIBAR + 2Ch
SPIBAR + 30h
SPIBAR + 34h
SPIBAR + 38h
SPIBAR + 3Ch
SPIBAR + 40h
SPIBAR + 44h
SPIBAR + 48h
SPIBAR + 4Ch
Default Value: 00000000h Size: 32 bits
Bit Description
Flash Data N (FD[N])—R/W. Similar definition as Flash Data 0. However, this register
31:0
does not begin shifting until FD[N-1] has completely shifted in/out.
880 Datasheet
Serial Peripheral Interface (SPI)
21.1.7 FRAP—Flash Regions Access Permissions Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 50h Attribute: RO, R/W
Default Value: 00000202h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
Bit Description
BIOS Master Write Access Grant (BMWAG)—R/W. Each bit [31:29] corresponds to
Master[7:0]. BIOS can grant one or more masters write access to the BIOS region 1
overriding the permissions in the Flash Descriptor.
31:24
Master[1] is Host processor/BIOS, Master[2] is Intel Management Engine, Master[3] is
Host processor/GbE. Master[0] and Master[7:4] are reserved.
The contents of this register are locked by the FLOCKDN bit.
BIOS Master Read Access Grant (BMRAG)—R/W. Each bit [28:16] corresponds to
Master[7:0]. BIOS can grant one or more masters read access to the BIOS region 1
overriding the read permissions in the Flash Descriptor.
23:16
Master[1] is Host processor/BIOS, Master[2] is Intel Management Engine, Master[3] is
Host processor/GbE. Master[0] and Master[7:4] are reserved.
The contents of this register are locked by the FLOCKDN bit
BIOS Region Write Access (BRWA)—RO. Each bit [15:8] corresponds to Regions
[7:0]. If the bit is set, this master can erase and write that particular region through
register accesses.
15:8 The contents of this register are that of the Flash Descriptor. Flash Master 1 Master
Region Write Access OR a particular master has granted BIOS write permissions in their
Master Write Access Grant register or the Flash Descriptor Security Override strap is
set.
BIOS Region Read Access (BRRA)—RO. Each bit [7:0] corresponds to Regions
[7:0]. If the bit is set, this master can read that particular region through register
accesses.
7:0 The contents of this register are that of the Flash Descriptor.Flash Master 1.Master
Region Write Access OR a particular master has granted BIOS read permissions in their
Master Read Access Grant register or the Flash Descriptor Security Override strap is
set.
Datasheet 881
Serial Peripheral Interface (SPI)
21.1.8 FREG0—Flash Region 0 (Flash Descriptor) Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 54h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
Bit Description
31:29 Reserved
Region Limit (RL)—RO. This specifies address bits 24:12 for the Region 0 Limit.
28:16 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG0.Region Limit.
15:13 Reserved
Region Base (RB) / Flash Descriptor Base Address Region (FdBAR)—RO. This
specifies address bits 24:12 for the Region 0 Base
12:0
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG0.Region Base.
21.1.9 FREG1—Flash Region 1 (BIOS Descriptor) Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 58h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
Bit Description
31:29 Reserved
Region Limit (RL)—RO. This specifies address bits 24:12 for the Region 1 Limit.
28:16 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Limit.
15:13 Reserved
Region Base (RB)—RO. This specifies address bits 24:12 for the Region 1 Base
12:0 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Base.
882 Datasheet
Serial Peripheral Interface (SPI)
21.1.10 FREG2—Flash Region 2 (Intel® ME) Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 5Ch Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
Bit Description
31:29 Reserved
Region Limit (RL)—RO. This specifies address bits 24:12 for the Region 2 Limit.
28:16 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Limit.
15:13 Reserved
Region Base (RB)—RO. This specifies address bits 24:12 for the Region 2 Base
12:0 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Base
21.1.11 FREG3—Flash Region 3 (GbE) Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 60h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
Bit Description
31:29 Reserved
Region Limit (RL)—RO. This specifies address bits 24:12 for the Region 3 Limit.
28:16 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG3.Region Limit.
15:13 Reserved
Region Base (RB)—RO. This specifies address bits 24:12 for the Region 3 Base
12:0 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG3.Region Base
Datasheet 883
Serial Peripheral Interface (SPI)
21.1.12 FREG4—Flash Region 4 (Platform Data) Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 64h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
Bit Description
31:29 Reserved
Region Limit (RL)—RO. This specifies address bits 24:12 for the Region 4 Limit.
28:16 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG4.Region Limit.
15:13 Reserved
Region Base (RB)—RO. This specifies address bits 24:12 for the Region 4 Base
12:0 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG4.Region Base.
21.1.13 PR0—Protected Range 0 Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 74h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: This register can not be written when the FLOCKDN bit is set to 1.
Bit Description
Write Protection Enable—R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that writes and erases directed to addresses between
31
them (inclusive) must be blocked by hardware. The base and limit fields are ignored
when this bit is cleared.
30:29 Reserved
Protected Range Limit—R/W. This field corresponds to FLA address bits 24:12 and
specifies the upper limit of the protected range. Address bits 11:0 are assumed to be
28:16
FFFh for the limit comparison. Any address greater than the value programmed in this
field is unaffected by this protected range.
Read Protection Enable—R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that read directed to addresses between them
15
(inclusive) must be blocked by hardware. The base and limit fields are ignored when
this bit is cleared.
14:13 Reserved
Protected Range Base—R/W. This field corresponds to FLA address bits 24:12 and
specifies the lower base of the protected range. Address bits 11:0 are assumed to be
12:0
000h for the base comparison. Any address less than the value programmed in this
field is unaffected by this protected range.
884 Datasheet
Serial Peripheral Interface (SPI)
21.1.14 PR1—Protected Range 1 Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 78h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: This register can not be written when the FLOCKDN bit is set to 1.
Bit Description
Write Protection Enable—R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that writes and erases directed to addresses between
31
them (inclusive) must be blocked by hardware. The base and limit fields are ignored
when this bit is cleared.
30:29 Reserved
Protected Range Limit—R/W. This field corresponds to FLA address bits 24:12 and
specifies the upper limit of the protected range. Address bits 11:0 are assumed to be
28:16
FFFh for the limit comparison. Any address greater than the value programmed in this
field is unaffected by this protected range.
Read Protection Enable—R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that read directed to addresses between them
15
(inclusive) must be blocked by hardware. The base and limit fields are ignored when
this bit is cleared.
14:13 Reserved
Protected Range Base—R/W. This field corresponds to FLA address bits 24:12 and
specifies the lower base of the protected range. Address bits 11:0 are assumed to be
12:0
000h for the base comparison. Any address less than the value programmed in this
field is unaffected by this protected range.
21.1.15 PR2—Protected Range 2 Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 7Ch Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: This register can not be written when the FLOCKDN bit is set to 1.
Bit Description
Write Protection Enable—R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that writes and erases directed to addresses between
31
them (inclusive) must be blocked by hardware. The base and limit fields are ignored
when this bit is cleared.
30:29 Reserved
Protected Range Limit—R/W. This field corresponds to FLA address bits 24:12 and
specifies the upper limit of the protected range. Address bits 11:0 are assumed to be
28:16
FFFh for the limit comparison. Any address greater than the value programmed in this
field is unaffected by this protected range.
Read Protection Enable—R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that read directed to addresses between them
15
(inclusive) must be blocked by hardware. The base and limit fields are ignored when
this bit is cleared.
14:13 Reserved
Protected Range Base—R/W. This field corresponds to FLA address bits 24:12 and
specifies the lower base of the protected range. Address bits 11:0 are assumed to be
12:0
000h for the base comparison. Any address less than the value programmed in this
field is unaffected by this protected range.
Datasheet 885
Serial Peripheral Interface (SPI)
21.1.16 PR3—Protected Range 3 Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 80h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: This register can not be written when the FLOCKDN bit is set to 1.
Bit Description
Write Protection Enable—R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that writes and erases directed to addresses between
31
them (inclusive) must be blocked by hardware. The base and limit fields are ignored
when this bit is cleared.
30:29 Reserved
Protected Range Limit—R/W. This field corresponds to FLA address bits 24:12 and
specifies the upper limit of the protected range. Address bits 11:0 are assumed to be
28:16
FFFh for the limit comparison. Any address greater than the value programmed in this
field is unaffected by this protected range.
Read Protection Enable—R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that read directed to addresses between them
15
(inclusive) must be blocked by hardware. The base and limit fields are ignored when
this bit is cleared.
14:13 Reserved
Protected Range Base—R/W. This field corresponds to FLA address bits 24:12 and
specifies the lower base of the protected range. Address bits 11:0 are assumed to be
12:0
000h for the base comparison. Any address less than the value programmed in this
field is unaffected by this protected range.
21.1.17 PR4—Protected Range 4 Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 84h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: This register can not be written when the FLOCKDN bit is set to 1.
Bit Description
Write Protection Enable—R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that writes and erases directed to addresses between
31
them (inclusive) must be blocked by hardware. The base and limit fields are ignored
when this bit is cleared.
30:29 Reserved
Protected Range Limit—R/W. This field corresponds to FLA address bits 24:12 and
specifies the upper limit of the protected range. Address bits 11:0 are assumed to be
28:16
FFFh for the limit comparison. Any address greater than the value programmed in this
field is unaffected by this protected range.
Read Protection Enable—R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that read directed to addresses between them
15
(inclusive) must be blocked by hardware. The base and limit fields are ignored when this
bit is cleared.
14:13 Reserved
Protected Range Base—R/W. This field corresponds to FLA address bits 24:12 and
specifies the lower base of the protected range. Address bits 11:0 are assumed to be
12:0
000h for the base comparison. Any address less than the value programmed in this field
is unaffected by this protected range.
886 Datasheet
Serial Peripheral Interface (SPI)
21.1.18 SSFS—Software Sequencing Flash Status Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 90h Attribute: RO, R/WC
Default Value: 00h Size: 8 bits
Note: The Software Sequencing control and status registers are reserved if the hardware
sequencing control and status registers are used.
Bit Description
7:5 Reserved
Access Error Log (AEL)—RO. This bit reflects the value of the Hardware Sequencing
4
Status AEL register.
Flash Cycle Error (FCERR)—R/WC. Hardware sets this bit to 1 when a programmed
access is blocked from running on the SPI interface due to one of the protection policies
or when any of the programmed cycle registers is written while a programmed access is
3
already in progress. This bit remains asserted until cleared by software writing a 1 or
hardware reset due to a global reset or host partition reset in an Intel ME enabled
system.
Cycle Done Status—R/WC. The PCH sets this bit to 1 when the SPI Cycle completes
(that is, SCIP bit is 0) after software sets the GO bit. This bit remains asserted until
cleared by software writing a 1 or hardware reset due to a global reset or host partition
2 reset in an Intel ME enabled system. When this bit is set and the SPI SMI# Enable bit is
set, an internal signal is asserted to the SMI# generation block. Software must make
sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed
access.
1 Reserved
SPI Cycle In Progress (SCIP)—RO. Hardware sets this bit when software sets the
SPI Cycle Go bit in the Command register. This bit remains set until the cycle completes
0 on the SPI interface. Hardware automatically sets and clears this bit so that software
can determine when read data is valid and/or when it is safe to begin programming the
next command. Software must only program the next command when this bit is 0.
Datasheet 887
Serial Peripheral Interface (SPI)
21.1.19 SSFC—Software Sequencing Flash Control Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 91h Attribute: R/W
Default Value: F80000h Size: 24 bits
Bit Description
23:19 Reserved – BIOS must set this field to ‘11111’b
SPI Cycle Frequency (SCF)—R/W. This register sets frequency to use for all SPI
software sequencing cycles (write, erase, fast read, read status, and so on) except
for the read cycle which always run at 20 MHz.
000 = 20 MHz
18:16
001 = 33 MHz
100 = 50 MHz
All other values reserved.
This register is locked when the SPI Configuration Lock-Down bit is set.
SPI SMI# Enable (SME)—R/W. When set to 1, the SPI asserts an SMI# request
15
whenever the Cycle Done Status bit is 1.
Data Cycle (DS)—R/W. When set to 1, there is data that corresponds to this
14 transaction. When 0, no data is delivered for this cycle, and the dBC and data fields
themselves are don’t cares.
Data Byte Count (dBC)—R/W. This field specifies the number of bytes to shift in or
out during the data portion of the SPI cycle. The valid settings (in decimal) are any
13:8 value from 0 to 63. The number of bytes transferred is the value of this field plus 1.
When this field is 00_0000b, there is 1 byte to transfer and that 11_1111b means
there are 64 bytes to transfer.
7 Reserved
Cycle Opcode Pointer (COP)—R/W. This field selects one of the programmed
6:4 opcodes in the Opcode Menu to be used as the SPI Command/Opcode. In the case
of an Atomic Cycle Sequence, this determines the second command.
Sequence Prefix Opcode Pointer (SPOP)—R/W. This field selects one of the two
programmed prefix opcodes for use when performing an Atomic Cycle Sequence. A
3 value of 0 points to the opcode in the least significant byte of the Prefix Opcodes
register. By making this programmable, the PCH supports flash devices that have
different opcodes for enabling writes to the data space versus status register.
Atomic Cycle Sequence (ACS)—R/W. When set to 1 along with the SCGO
assertion, the PCH will execute a sequence of commands on the SPI interface
without allowing the LAN component to arbitrate and interleave cycles. The
sequence is composed of:
2 • Atomic Sequence Prefix Command (8-bit opcode only)
• Primary Command specified below by software (can include address and data)
• Polling the Flash Status Register (opcode 05h) until bit 0 becomes 0b.
The SPI Cycle in Progress bit remains set and the Cycle Done Status bit remains
unset until the Busy bit in the Flash Status Register returns 0.
SPI Cycle Go (SCGO)—R/WS. This bit always returns 0 on reads. However, a write
to this register with a 1 in this bit starts the SPI cycle defined by the other bits of
this register. The “SPI Cycle in Progress” (SCIP) bit gets set by this action. Hardware
1
must ignore writes to this bit while the Cycle In Progress bit is set.
Hardware allows other bits in this register to be programmed for the same
transaction when writing this bit to 1. This saves an additional memory write.
0 Reserved
888 Datasheet
Serial Peripheral Interface (SPI)
21.1.20 PREOP—Prefix Opcode Configuration Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 94h Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
Prefix Opcode 1—R/W. Software programs an SPI opcode into this field that is
15:8
permitted to run as the first command in an atomic cycle sequence.
Prefix Opcode 0—R/W. Software programs an SPI opcode into this field that is
7:0
permitted to run as the first command in an atomic cycle sequence.
NOTE: This register is not writable when the Flash Configuration Lock-Down bit (SPIBAR +
04h:15) is set.
21.1.21 OPTYPE—Opcode Type Configuration Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 96h Attribute: R/W
Default Value: 0000h Size: 16 bits
Entries in this register correspond to the entries in the Opcode Menu Configuration
register.
Note: The definition below only provides write protection for opcodes that have addresses
associated with them. Therefore, any erase or write opcodes that do not use an address
should be avoided (for example, “Chip Erase” and “Auto-Address Increment Byte
Program”)
Bit Description
15:14 Opcode Type 7—R/W. See the description for bits 1:0
13:12 Opcode Type 6—R/W. See the description for bits 1:0
11:10 Opcode Type 5—R/W. See the description for bits 1:0
9:8 Opcode Type 4—R/W. See the description for bits 1:0
7:6 Opcode Type 3—R/W. See the description for bits 1:0
5:4 Opcode Type 2—R/W. See the description for bits 1:0
3:2 Opcode Type 1—R/W. See the description for bits 1:0
Opcode Type 0—R/W. This field specifies information about the corresponding Opcode
0. This information allows the hardware to 1) know whether to use the address field
and 2) provide BIOS and Shared Flash protection capabilities. The encoding of the two
bits is:
1:0 00 = No address associated with this Opcode; Read cycle type
01 = No address associated with this Opcode; Write cycle type
10 = Address required; Read cycle type
11 = Address required; Write cycle type
NOTE: This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR + 00h:15)
is set.
Datasheet 889
Serial Peripheral Interface (SPI)
21.1.22 OPMENU—Opcode Menu Configuration Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + 98h Attribute: R/W
Default Value: 0000000000000000h Size: 64 bits
Eight entries are available in this register to give BIOS a sufficient set of commands for
communicating with the flash device, while also restricting what malicious software can
do. This keeps the hardware flexible enough to operate with a wide variety of SPI
devices.
Note: It is recommended that BIOS avoid programming Write Enable opcodes in this menu.
Malicious software could then perform writes and erases to the SPI flash without using
the atomic cycle mechanism. This could cause functional failures in a shared flash
environment. Write Enable opcodes should only be programmed in the Prefix Opcodes.
Bit Description
63:56 Allowable Opcode 7—R/W. See the description for bits 7:0
55:48 Allowable Opcode 6—R/W. See the description for bits 7:0
47:40 Allowable Opcode 5—R/W. See the description for bits 7:0
39:32 Allowable Opcode 4—R/W. See the description for bits 7:0
31:24 Allowable Opcode 3—R/W. See the description for bits 7:0
23:16 Allowable Opcode 2—R/W. See the description for bits 7:0
15:8 Allowable Opcode 1—R/W. See the description for bits 7:0
Allowable Opcode 0—R/W. Software programs an SPI opcode into this field for use
7:0
when initiating SPI commands through the Control Register.
This register is not writable when the SPI Configuration Lock-Down bit (SPIBAR +
00h:15) is set.
21.1.23 BBAR—BIOS Base Address Configuration Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + A0h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Eight entries are available in this register to give BIOS a sufficient set of commands for
communicating with the flash device, while also restricting what malicious software can
do. This keeps the hardware flexible enough to operate with a wide variety of SPI
devices.
Bit Description
31:24 Reserved
Bottom of System Flash—R/W. This field determines the bottom of the System BIOS.
The PCH will not run programmed commands nor memory reads whose address field is
less than this value. this field corresponds to bits 23:8 of the 3-byte address; bits 7:0
are assumed to be 00h for this vector when comparing to a potential SPI address.
23:8 NOTE: The SPI host controller prevents any programmed cycle using the address
register with an address less than the value in this register. Some flash devices
specify that the Read ID command must have an address of 0000h or 0001h. If
this command must be supported with these devices, it must be performed with
the BIOS BAR.
7:0 Reserved
890 Datasheet
Serial Peripheral Interface (SPI)
21.1.24 FDOC—Flash Descriptor Observability Control Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + B0h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: This register that can be used to observe the contents of the Flash Descriptor that is
stored in the PCH Flash Controller. This register is only applicable when SPI device is in
descriptor mode.
Bit Description
31:15 Reserved
Flash Descriptor Section Select (FDSS)—R/W. Selects which section within the
loaded Flash Descriptor to observe.
000 = Flash Signature and Descriptor Map
14:12 001 = Component
010 = Region
011 = Master
111 = Reserved
Flash Descriptor Section Index (FDSI)—R/W. Selects the DW offset within the Flash
11:2
Descriptor Section to observe.
1:0 Reserved
21.1.25 FDOD—Flash Descriptor Observability Data Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + B4h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register that can be used to observe the contents of the Flash Descriptor that is
stored in the PCH Flash Controller.
Bit Description
Flash Descriptor Section Data (FDSD)—RO. Returns the DW of data to observe as
31:0
selected in the Flash Descriptor Observability Control.
Datasheet 891
Serial Peripheral Interface (SPI)
21.1.26 AFC—Additional Flash Control Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + C0h Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits.
Bit Description
31:3 Reserved
Flash Controller Interface Dynamic Clock Gating Enable—R/W.
0 = Flash Controller Interface Dynamic Clock Gating is Disabled
2:1
1 = Flash Controller Interface Dynamic Clock Gating is Enabled
Other configurations are Reserved.
Flash Controller Core Dynamic Clock Gating Enable—R/W.
0 0 = Flash Controller Core Dynamic Clock Gating is Disabled
1 = Flash Controller Core Dynamic Clock Gating is Enabled
21.1.27 LVSCC—Host Lower Vendor Specific Component
Capabilities Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + C4h Attribute: RO, R/WL
Default Value: 00000000h Size: 32 bits
Note: All attributes described in LVSCC must apply to all flash space below the FPBA, even if
it spans between two separate flash parts. This register is only applicable when SPI
device is in descriptor mode.
Bit Description
31:24 Reserved
Vendor Component Lock (LVCL)—R/W. This register locks itself when set.
23 0 = The lock bit is not set
1 = The Vendor Component Lock bit is set.
NOTE: This bit applies to both UVSCC and LVSCC registers.
22:16 Reserved
Lower Erase Opcode (LEO)—R/W. This register is programmed with the Flash erase
15:8 instruction opcode required by the vendor’s Flash component.
This register is locked by the Vendor Component Lock (LVCL) bit.
7:5 Reserved
Write Enable on Write Status (LWEWS)—R/W. This register is locked by the Vendor
Component Lock (LVCL) bit.
0 = No automatic write of 00h will be made to the SPI flash’s status register)
1 = A write of 00h to the SPI flash’s status register will be sent on EVERY write and
erase to the SPI flash. 06h 01h 00h is the opcode sequence used to unlock the
Status register.
4
NOTES:
1. This bit should not be set to 1 if there are non-volatile bits in the SPI flash’s
status register. This may lead to premature flash wear out.
2. This is not an atomic sequence. If the SPI component’s status register is non-
volatile, then BIOS should issue an atomic software sequence cycle to unlock the
flash part.
3. Bit 3 and bit 4 should NOT be both set to 1.
892 Datasheet
Serial Peripheral Interface (SPI)
Bit Description
Lower Write Status Required (LWSR)—R/W. This register is locked by the Vendor
Component Lock (LVCL) bit.
0 = No automatic write of 00h will be made to the SPI flash’s status register)
1 = A write of 00h to the SPI flash’s status register will be sent on EVERY write and
erase to the SPI flash. 50h 01h 00h is the opcode sequence used to unlock the
Status register.
3
NOTES:
1. This bit should not be set to 1 if there are non volatile bits in the SPI flash’s
status register. This may lead to premature flash wear out.
2. This is not an atomic sequence. If the SPI component’s status register is non-
volatile, then BIOS should issue an atomic software sequence cycle to unlock the
flash part.
3. Bit 3 and bit 4 should NOT be both set to 1.
Lower Write Granularity (LWG)—R/W. This register is locked by the Vendor
Component Lock (LVCL) bit.
0 = 1 Byte
1 = 64 Byte
2 NOTES:
1. If more than one Flash component exists, this field must be set to the lowest
common write granularity of the different Flash components.
2. If using 64 B write, BIOS must ensure that multiple byte writes do not occur over
256 B boundaries. This will lead to corruption as the write will wrap around the
page boundary on the SPI flash part. This is a a feature page writable SPI flash.
Lower Block/Sector Erase Size (LBES)—R/W. This field identifies the erasable sector
size for all Flash components.
00 = 256 Byte
01 = 4 KB
10 = 8 KB
1:0
11 = 64 KB
This register is locked by the Vendor Component Lock (LVCL) bit.
Hardware takes no action based on the value of this register. The contents of this
register are to be used only by software and can be read in the HSFSTS.BERASE register
in both the BIOS and the GbE program registers if FLA is less than FPBA.
Datasheet 893
Serial Peripheral Interface (SPI)
21.1.28 UVSCC—Host Upper Vendor Specific Component
Capabilities Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + C8h Attribute: RO, R/WL
Default Value: 00000000h Size: 32 bits
Note: All attributes described in UVSCC must apply to all flash space equal to or above the
FPBA, even if it spans between two separate flash parts. This register is only applicable
when SPI device is in descriptor mode.
Note: To prevent this register from being modified you must use LVSCC.VCL bit.
Bit Description
31:16 Reserved
Upper Erase Opcode (UEO)—R/W. This register is programmed with the Flash erase
15:8 instruction opcode required by the vendor’s Flash component.
This register is locked by the Vendor Component Lock (UVCL) bit.
7:5 Reserved
Write Enable on Write Status (UWEWS)—R/W. This register is locked by the Vendor
Component Lock (UVCL) bit.
0 = No automatic write of 00h will be made to the SPI flash’s status register)
1 = A write of 00h to the SPI flash’s status register will be sent on EVERY write and
erase to the SPI flash. 06h 01h 00h is the opcode sequence used to unlock the
Status register.
4 NOTES:
1. This bit should not be set to 1 if there are non volatile bits in the SPI flash’s status
register. This may lead to premature flash wear out.
2. This is not an atomic sequence. If the SPI component’s status register is non-
volatile, then BIOS should issue an atomic software sequence cycle to unlock the
flash part.
3. Bit 3 and bit 4 should NOT be both set to 1.
Upper Write Status Required (UWSR)—R/W. This register is locked by the Vendor
Component Lock (UVCL) bit.
0 = No automatic write of 00h will be made to the SPI flash’s status register)
1 = A write of 00h to the SPI flash’s status register will be sent on EVERY write and
erase to the SPI flash. 50h 01h 00h is the opcode sequence used to unlock the
Status register.
3 NOTES:
1. This bit should not be set to ‘1’ if there are non volatile bits in the SPI flash’s status
register. This may lead to premature flash wear out.
2. This is not an atomic sequence. If the SPI component’s status register is non-
volatile, then BIOS should issue an atomic software sequence cycle to unlock the
flash part.
3. Bit 3 and bit 4 should NOT be both set to 1.
Upper Write Granularity (UWG)—R/W. This register is locked by the Vendor
Component Lock (UVCL) bit.
0 = 1 Byte
1 = 64 Byte
2 NOTES:
1. If more than one Flash component exists, this field must be set to the lowest
common write granularity of the different Flash components.
2. If using 64 B write, BIOS must ensure that multiple byte writes do not occur over
256 B boundaries. This will lead to corruption as the write will wrap around the page
boundary on the SPI flash part. This is a a feature page writable SPI flash.
894 Datasheet
Serial Peripheral Interface (SPI)
Bit Description
Upper Block/Sector Erase Size (UBES)—R/W. This field identifies the erasable
sector size for all Flash components.
Valid Bit Settings:
00 = 256 Byte
01 = 4 KB
1:0 10 = 8 KB
11 = 64 KB
This register is locked by the Vendor Component Lock (UVCL) bit.
Hardware takes no action based on the value of this register. The contents of this
register are to be used only by software and can be read in the HSFSTS.BERASE
register in both the BIOS and the GbE program registers if FLA is greater or equal to
FPBA.
21.1.29 FPB—Flash Partition Boundary Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + D0h Attribute: RO
Default Value: 00000000h Size: 32 bits
Note: This register is only applicable when SPI device is in descriptor mode.
Bit Description
31:13 Reserved
Flash Partition Boundary Address (FPBA)—RO. This register reflects the value of
12:0
Flash Descriptor Component FPBA field.
21.1.30 SRDL—Soft Reset Data Lock Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + F0h Attribute: R/WL
Default Value: 00000000h Size: 32 bits
Bit Description
31:1 Reserved
Set_Stap Lock (SSL)—R/WL.
0 = The SRDL (this register), SRDC (SPIBAR+F4h), and SRD (SPIBAR+F4h) registers
are writeable.
0
1 = The SRDL (this register), SRDC (SPIBAR+F4h), and SRD (SPIBAR+F4h) registers
are locked.
NOTE: That this bit is reset to ‘0’ on CF9h resets.
Datasheet 895
Serial Peripheral Interface (SPI)
21.1.31 SRDC—Soft Reset Data Control Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + F4h Attribute: R/WL
Default Value: 00000000h Size: 32 bits
Bit Description
31:1 Reserved
Soft Reset Data Select (SRDS)—R/WL.
0 = The Set_Strap data sends the default processor configuration data.
0 1 = The Set_Strap message bits come from the Set_Strap Msg Data register.
NOTES:
1. This bit is reset by the RSMRST# or when the Resume well loses power.
2. This bit is locked by the SSL bit (SPIBAR+F0h:bit 0).
21.1.32 SRD—Soft Reset Data Register
(SPI Memory Mapped Configuration Registers)
Memory Address: SPIBAR + F8h Attribute: R/WL
Default Value: 00000000h Size: 32 bits
Bit Description
31:14 Reserved
Set_Stap Data (SSD)—R/WL.
NOTES:
13:0
1. These bits are reset by the RSMRST#, or when the Resume well loses power.
2. These bits are locked by the SSL bit (SPIBAR+F0h:bit 0).
21.2 Flash Descriptor Records
The following sections describe the data structure of the Flash Descriptor on the SPI
device. These are not registers within the PCH.
21.3 OEM Section
Memory Address: F00h Default Value: Size: 256 Bytes
256 Bytes are reserved at the top of the Flash Descriptor for use by the OEM. The
information stored by the OEM can only be written during the manufacturing process as
the Flash Descriptor read/write permissions must be set to Read Only when the
computer leaves the manufacturing floor. The PCH Flash controller does not read this
information. FFh is suggested to reduce programming time.
896 Datasheet
Serial Peripheral Interface (SPI)
21.4 GbE SPI Flash Program Registers
The GbE Flash registers are memory-mapped with a base address MBARB found in the
GbE LAN register chapter Device 25: Function 0: Offset 14h. The individual registers
are then accessible at MBARB + Offset as indicated in the following table.
These memory mapped registers must be accessed in byte, word, or DWord quantities.
Note: These register are only applicable when SPI flash is used in descriptor mode.
Table 21-2. Gigabit LAN SPI Flash Program Register Address Map
(GbE LAN Memory Mapped Configuration Registers)
MBARB +
Mnemonic Register Name Default Attribute
Offset
00h–03h GLFPR Gigabit LAN Flash Primary Region 00000000h RO
RO, R/WC,
04h–05h HSFS Hardware Sequencing Flash Status 0000h
R/W
06h–07h HSFC Hardware Sequencing Flash Control 0000h R/W, R/WS
08h–0Bh FADDR Flash Address 00000000h R/W
0Ch–0Fh — Reserved 00000000h
10h–13h FDATA0 Flash Data 0 00000000h R/W
14h–4Fh — Reserved 00000000h
50h–53h FRAP Flash Region Access Permissions 00000000h RO, R/W
54h–57h FREG0 Flash Region 0 00000000h RO
58h–5Bh FREG1 Flash Region 1 00000000h RO
5Ch–5F FREG2 Flash Region 2 00000000h RO
60h–63h FREG3 Flash Region 3 00000000h RO
64h–73h — Reserved for Future Flash Regions
74h–77h PR0 Flash Protected Range 0 00000000h R/W
78h–7Bh PR1 Flash Protected Range 1 00000000h R/W
7Ch–8Fh — Reserved
90h SSFS Software Sequencing Flash Status 00h RO, R/WC
91h–93h SSFC Software Sequencing Flash Control 000000h R/W
94h–95h PREOP Prefix Opcode Configuration 0000h R/W
96h–97h OPTYPE Opcode Type Configuration 0000h R/W
0000000000
98h–9Fh OPMENU Opcode Menu Configuration R/W
000000h
A0h–DFh — Reserved
Datasheet 897
Serial Peripheral Interface (SPI)
21.4.1 GLFPR –Gigabit LAN Flash Primary Region Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 00h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:29 Reserved
GbE Flash Primary Region Limit (PRL)—RO. This specifies address bits 24:12 for
the Primary Region Limit.
28:16
The value in this register loaded from the contents in the Flash
Descriptor.FLREG3.Region Limit
15:13 Reserved
GbE Flash Primary Region Base (PRB)—RO. This specifies address bits 24:12 for
the Primary Region Base
12:0
The value in this register is loaded from the contents in the Flash
Descriptor.FLREG3.Region Base
21.4.2 HSFS—Hardware Sequencing Flash Status Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 04h Attribute: RO, R/WC, R/W
Default Value: 0000h Size: 16 bits
Bit Description
Flash Configuration Lock-Down (FLOCKDN)—R/W. When set to 1, those Flash
Program Registers that are locked down by this FLOCKDN bit cannot be written. Once
15
set to 1, this bit can only be cleared by a hardware reset due to a global reset or host
partition reset in an Intel ME enabled system.
Flash Descriptor Valid (FDV)—RO. This bit is set to a 1 if the Flash Controller read
the correct Flash Descriptor Signature.
14 If the Flash Descriptor Valid bit is not 1, software cannot use the Hardware Sequencing
registers, but must use the software sequencing registers. Any attempt to use the
Hardware Sequencing registers will result in the FCERR bit being set.
Flash Descriptor Override Pin Strap Status (FDOPSS)—RO. This bit indicates the
condition of the Flash Descriptor Security Override / Intel ME Debug Mode pin strap.
13 0 = The Flash Descriptor Security Override / Intel ME Debug Mode strap is set using
external pull-up on HDA_SDO
1 = No override
12:6 Reserved
SPI Cycle In Progress (SCIP)—RO. Hardware sets this bit when software sets the
Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash Control register. This bit
remains set until the cycle completes on the SPI interface. Hardware automatically sets
5
and clears this bit so that software can determine when read data is valid and/or when
it is safe to begin programming the next command. Software must only program the
next command when this bit is 0.
898 Datasheet
Serial Peripheral Interface (SPI)
Bit Description
Block/Sector Erase Size (BERASE)—RO. This field identifies the erasable sector size
for all Flash components.
00 = 256 Byte
01 = 4 K Byte
10 = 8 K Byte
4:3
11 = 64 K Byte
If the Flash Linear Address is less than FPBA then this field reflects the value in the
LVSCC.LBES register.
If the Flash Linear Address is greater or equal to FPBA then this field reflects the value
in the UVSCC.UBES register.
Access Error Log (AEL)—R/W/C. Hardware sets this bit to a 1 when an attempt was
made to access the BIOS region using the direct access method or an access to the
2
BIOS Program Registers that violated the security restrictions. This bit is simply a log of
an access security violation. This bit is cleared by software writing a 1.
Flash Cycle Error (FCERR)—R/W/C. Hardware sets this bit to 1 when an program
register access is blocked to the FLASH due to one of the protection policies or when
any of the programmed cycle registers is written while a programmed access is already
1 in progress. This bit remains asserted until cleared by software writing a 1 or until
hardware reset occurs due to a global reset or host partition reset in an Intel ME
enabled system. Software must clear this bit before setting the FLASH Cycle GO bit in
this register.
Flash Cycle Done (FDONE)—R/W/C. The PCH sets this bit to 1 when the SPI Cycle
completes after software previously set the FGO bit. This bit remains asserted until
cleared by software writing a 1 or hardware reset due to a global reset or host partition
0 reset in an Intel ME enabled system. When this bit is set and the SPI SMI# Enable bit is
set, an internal signal is asserted to the SMI# generation block. Software must make
sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed
access.
Datasheet 899
Serial Peripheral Interface (SPI)
21.4.3 HSFC—Hardware Sequencing Flash Control Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 06h Attribute: R/W, R/WS
Default Value: 0000h Size: 16 bits
Bit Description
15:10 Reserved
Flash Data Byte Count (FdBC)—R/W. This field specifies the number of bytes to shift
in or out during the data portion of the SPI cycle. The contents of this register are 0s
9:8 based with 0b representing 1 byte and 11b representing 4 bytes. The number of bytes
transferred is the value of this field plus 1.
This field is ignored for the Block Erase command.
7:3 Reserved
FLASH Cycle (FCYCLE)—R/W. This field defines the Flash SPI cycle type generated to
the FLASH when the FGO bit is set as defined below:
00 = Read (1 up to 4 bytes by setting FdBC)
2:1
01 = Reserved
10 = Write (1 up to 4 bytes by setting FdBC)
11 = Block Erase
Flash Cycle Go (FGO)—R/W/S. A write to this register with a 1 in this bit initiates a
request to the Flash SPI Arbiter to start a cycle. This register is cleared by hardware
when the cycle is granted by the SPI arbiter to run the cycle on the SPI bus. When the
cycle is complete, the FDONE bit is set.
Software is forbidden to write to any register in the HSFLCTL register between the FGO
0
bit getting set and the FDONE bit being cleared. Any attempt to violate this rule will be
ignored by hardware.
Hardware allows other bits in this register to be programmed for the same transaction
when writing this bit to 1. This saves an additional memory write.
This bit always returns 0 on reads.
21.4.4 FADDR—Flash Address Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 08h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:25 Reserved
Flash Linear Address (FLA)—R/W. The FLA is the starting byte linear address of a
24:0 SPI Read or Write cycle or an address within a Block for the Block Erase command. The
Flash Linear Address must fall within a region for which BIOS has access permissions.
900 Datasheet
Serial Peripheral Interface (SPI)
21.4.5 FDATA0—Flash Data 0 Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 10h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Flash Data 0 (FD0)—R/W. This field is shifted out as the SPI Data on the Master-Out
Slave-In Data pin during the data portion of the SPI cycle.
This register also shifts in the data from the Master-In Slave-Out pin into this register
during the data portion of the SPI cycle.
The data is always shifted starting with the least significant byte, msb to lsb, followed
31:0 by the next least significant byte, msb to lsb, and so on. Specifically, the shift order on
SPI in terms of bits within this register is: 7-6-5-4-3-2-1-0-15-14-13-…8-23-22-…16-
31…24 Bit 24 is the last bit shifted out/in. There are no alignment assumptions; byte 0
always represents the value specified by the cycle address.
The data in this register may be modified by the hardware during any programmed SPI
transaction. Direct Memory Reads do not modify the contents of this register.
21.4.6 FRAP—Flash Regions Access Permissions Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 50h Attribute: RO, R/W
Default Value: 00000808h Size: 32 bits
Bit Description
31:28 Reserved
GbE Master Write Access Grant (GMWAG)—R/W. Each bit 27:25 corresponds to
Master[3:1]. GbE can grant one or more masters write access to the GbE region 3
overriding the permissions in the Flash Descriptor.
27:25
Master[1] is Host Processor/BIOS, Master[2] is Intel Management Engine, Master[3] is
Host processor/GbE.
The contents of this register are locked by the FLOCKDN bit.
24:20 Reserved
GbE Master Read Access Grant (GMRAG)—R/W. Each bit 19:17 corresponds to
Master[3:1]. GbE can grant one or more masters read access to the GbE region 3
overriding the read permissions in the Flash Descriptor.
19:17
Master[1] is Host processor/BIOS, Master[2] is Intel Management Engine, Master[3] is
GbE.
The contents of this register are locked by the FLOCKDN bit
16:12 Reserved
GbE Region Write Access (GRWA)—RO. Each bit 11:8 corresponds to Regions 3:0.
If the bit is set, this master can erase and write that particular region through register
accesses.
11:8 The contents of this register are that of the Flash Descriptor. Flash Master 3.Master
Region Write Access OR a particular master has granted GbE write permissions in their
Master Write Access Grant register OR the Flash Descriptor Security Override strap is
set.
7:4 Reserved
GbE Region Read Access (GRRA)—RO. Each bit 3:0 corresponds to Regions 3:0. If
the bit is set, this master can read that particular region through register accesses.
3:0 The contents of this register are that of the Flash Descriptor. Flash Master 3.Master
Region Write Access OR a particular master has granted GbE read permissions in their
Master Read Access Grant register.
Datasheet 901
Serial Peripheral Interface (SPI)
21.4.7 FREG0—Flash Region 0 (Flash Descriptor) Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 54h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:29 Reserved
Region Limit (RL)—RO. This specifies address bits 24:12 for the Region 0 Limit.
28:16 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG0.Region Limit.
15:13 Reserved
Region Base (RB)—RO. This specifies address bits 24:12 for the Region 0 Base
12:0 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG0.Region Base.
21.4.8 FREG1—Flash Region 1 (BIOS Descriptor) Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 58h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:29 Reserved
Region Limit (RL)—RO. This specifies address bits 24:12 for the Region 1 Limit.
28:16 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Limit.
15:13 Reserved
Region Base (RB)—RO. This specifies address bits 24:12 for the Region 1 Base
12:0 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG1.Region Base.
21.4.9 FREG2—Flash Region 2 (Intel® ME) Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 5Ch Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:29 Reserved
Region Limit (RL)—RO. This specifies address bits 24:12 for the Region 2 Limit.
28:16 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Limit.
15:13 Reserved
Region Base (RB)—RO. This specifies address bits 24:12 for the Region 2 Base
12:0 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG2.Region Base.
902 Datasheet
Serial Peripheral Interface (SPI)
21.4.10 FREG3—Flash Region 3 (GbE) Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 60h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:29 Reserved
Region Limit (RL)—RO. This specifies address bits 24:12 for the Region 3 Limit.
28:16 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG3.Region Limit.
15:13 Reserved
Region Base (RB)—RO. This specifies address bits 24:12 for the Region 3 Base
12:0 The value in this register is loaded from the contents in the Flash
Descriptor.FLREG3.Region Base.
21.4.11 PR0—Protected Range 0 Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 74h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: This register can not be written when the FLOCKDN bit is set to 1.
Bit Description
Write Protection Enable—R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that writes and erases directed to addresses between
31
them (inclusive) must be blocked by hardware. The base and limit fields are ignored
when this bit is cleared.
30:29 Reserved
Protected Range Limit—R/W. This field corresponds to FLA address bits 24:12 and
specifies the upper limit of the protected range. Address bits 11:0 are assumed to be
28:16
FFFh for the limit comparison. Any address greater than the value programmed in this
field is unaffected by this protected range.
Read Protection Enable—R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that read directed to addresses between them
15
(inclusive) must be blocked by hardware. The base and limit fields are ignored when
this bit is cleared.
14:13 Reserved
Protected Range Base—R/W. This field corresponds to FLA address bits 24:12 and
specifies the lower base of the protected range. Address bits 11:0 are assumed to be
12:0
000h for the base comparison. Any address less than the value programmed in this
field is unaffected by this protected range.
Datasheet 903
Serial Peripheral Interface (SPI)
21.4.12 PR1—Protected Range 1 Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 78h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Note: This register can not be written when the FLOCKDN bit is set to 1.
Bit Description
Write Protection Enable—R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that writes and erases directed to addresses between
31
them (inclusive) must be blocked by hardware. The base and limit fields are ignored
when this bit is cleared.
30:29 Reserved
Protected Range Limit—R/W. This field corresponds to FLA address bits 24:12 and
specifies the upper limit of the protected range. Address bits 11:0 are assumed to be
28:16
FFFh for the limit comparison. Any address greater than the value programmed in this
field is unaffected by this protected range.
Read Protection Enable—R/W. When set, this bit indicates that the Base and Limit
fields in this register are valid and that read directed to addresses between them
15
(inclusive) must be blocked by hardware. The base and limit fields are ignored when
this bit is cleared.
14:13 Reserved
Protected Range Base—R/W. This field corresponds to FLA address bits 24:12 and
specifies the lower base of the protected range. Address bits 11:0 are assumed to be
12:0
000h for the base comparison. Any address less than the value programmed in this
field is unaffected by this protected range.
904 Datasheet
Serial Peripheral Interface (SPI)
21.4.13 SSFS—Software Sequencing Flash Status Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 90h Attribute: RO, R/WC
Default Value: 00h Size: 8 bits
Note: The Software Sequencing control and status registers are reserved if the hardware
sequencing control and status registers are used.
Bit Description
7:5 Reserved
Access Error Log (AEL)—RO. This bit reflects the value of the Hardware Sequencing
4
Status AEL register.
Flash Cycle Error (FCERR)—R/WC. Hardware sets this bit to 1 when a programmed
access is blocked from running on the SPI interface due to one of the protection policies
or when any of the programmed cycle registers is written while a programmed access is
3
already in progress. This bit remains asserted until cleared by software writing a 1 or
hardware reset due to a global reset or host partition reset in an Intel ME enabled
system.
Cycle Done Status—R/WC. The PCH sets this bit to 1 when the SPI Cycle completes
(that is, SCIP bit is 0) after software sets the GO bit. This bit remains asserted until
cleared by software writing a 1 or hardware reset due to a global reset or host partition
2 reset in an Intel ME enabled system. When this bit is set and the SPI SMI# Enable bit is
set, an internal signal is asserted to the SMI# generation block. Software must make
sure this bit is cleared prior to enabling the SPI SMI# assertion for a new programmed
access.
1 Reserved
SPI Cycle In Progress (SCIP)—RO. Hardware sets this bit when software sets the
SPI Cycle Go bit in the Command register. This bit remains set until the cycle completes
0 on the SPI interface. Hardware automatically sets and clears this bit so that software
can determine when read data is valid and/or when it is safe to begin programming the
next command. Software must only program the next command when this bit is 0.
Datasheet 905
Serial Peripheral Interface (SPI)
21.4.14 SSFC—Software Sequencing Flash Control Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 91h Attribute: R/W
Default Value: 000000h Size: 24 bits
Bit Description
23:19 Reserved
SPI Cycle Frequency (SCF)—R/W. This register sets frequency to use for all SPI
software sequencing cycles (write, erase, fast read, read status, and so on) except for
the read cycle which always run at 20 MHz.
18:16 000 = 20 MHz
001 = 33 MHz
All other values = Reserved.
This register is locked when the SPI Configuration Lock-Down bit is set.
15 Reserved
Data Cycle (DS)—R/W. When set to 1, there is data that corresponds to this
14 transaction. When 0, no data is delivered for this cycle, and the dBC and data fields
themselves are don’t cares.
Data Byte Count (dBC)—R/W. This field specifies the number of bytes to shift in or
out during the data portion of the SPI cycle. The valid settings (in decimal) are any
13:8 value from 0 to 3. The number of bytes transferred is the value of this field plus 1.
When this field is 00b, then there is 1 byte to transfer and that 11b means there are 4
bytes to transfer.
7 Reserved
Cycle Opcode Pointer (COP)—R/W. This field selects one of the programmed
6:4 opcodes in the Opcode Menu to be used as the SPI Command/Opcode. In the case of an
Atomic Cycle Sequence, this determines the second command.
Sequence Prefix Opcode Pointer (SPOP)—R/W. This field selects one of the two
programmed prefix opcodes for use when performing an Atomic Cycle Sequence. A
3 value of 0 points to the opcode in the least significant byte of the Prefix Opcodes
register. By making this programmable, the PCH supports flash devices that have
different opcodes for enabling writes to the data space versus status register.
Atomic Cycle Sequence (ACS)—R/W. When set to 1 along with the SCGO assertion,
the PCH will execute a sequence of commands on the SPI interface without allowing the
LAN component to arbitrate and interleave cycles. The sequence is composed of:
• Atomic Sequence Prefix Command (8-bit opcode only)
2
• Primary Command specified below by software (can include address and data)
• Polling the Flash Status Register (opcode 05h) until bit 0 becomes 0b.
The SPI Cycle in Progress bit remains set and the Cycle Done Status bit remains unset
until the Busy bit in the Flash Status Register returns 0.
SPI Cycle Go (SCGO)—R/WS. This bit always returns 0 on reads. However, a write to
this register with a ‘1’ in this bit starts the SPI cycle defined by the other bits of this
register. The “SPI Cycle in Progress” (SCIP) bit gets set by this action. Hardware must
1
ignore writes to this bit while the Cycle In Progress bit is set.
Hardware allows other bits in this register to be programmed for the same transaction
when writing this bit to 1. This saves an additional memory write.
0 Reserved
906 Datasheet
Serial Peripheral Interface (SPI)
21.4.15 PREOP—Prefix Opcode Configuration Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 94h Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
Prefix Opcode 1—R/W. Software programs an SPI opcode into this field that is
15:8
permitted to run as the first command in an atomic cycle sequence.
Prefix Opcode 0—R/W. Software programs an SPI opcode into this field that is
7:0
permitted to run as the first command in an atomic cycle sequence.
NOTE: This register is not writable when the SPI Configuration Lock-Down bit (MBARB + 00h:15)
is set.
21.4.16 OPTYPE—Opcode Type Configuration Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 96h Attribute: R/W
Default Value: 0000h Size: 16 bits
Entries in this register correspond to the entries in the Opcode Menu Configuration
register.
Note: The definition below only provides write protection for opcodes that have addresses
associated with them. Therefore, any erase or write opcodes that do not use an address
should be avoided (for example, “Chip Erase” and “Auto-Address Increment Byte
Program”).
Bit Description
15:14 Opcode Type 7—R/W. See the description for bits 1:0
13:12 Opcode Type 6—R/W. See the description for bits 1:0
11:10 Opcode Type 5—R/W. See the description for bits 1:0
9:8 Opcode Type 4—R/W. See the description for bits 1:0
7:6 Opcode Type 3—R/W. See the description for bits 1:0
5:4 Opcode Type 2—R/W. See the description for bits 1:0
3:2 Opcode Type 1—R/W. See the description for bits 1:0
Opcode Type 0—R/W. This field specifies information about the corresponding Opcode
0. This information allows the hardware to 1) know whether to use the address field
and 2) provide BIOS and Shared Flash protection capabilities. The encoding of the two
bits is:
1:0 00 = No address associated with this Opcode; Read cycle type
01 = No address associated with this Opcode; Write cycle type
10 = Address required; Read cycle type
11 = Address required; Write cycle type
NOTE: This register is not writable when the SPI Configuration Lock-Down bit (MBARB + 00h:15)
is set.
Datasheet 907
Serial Peripheral Interface (SPI)
21.4.17 OPMENU—Opcode Menu Configuration Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 98h Attribute: R/W
Default Value: 0000000000000000h Size: 64 bits
Eight entries are available in this register to give GbE a sufficient set of commands for
communicating with the flash device, while also restricting what malicious software can
do. This keeps the hardware flexible enough to operate with a wide variety of SPI
devices.
Note: It is recommended that GbE avoid programming Write Enable opcodes in this menu.
Malicious software could then perform writes and erases to the SPI flash without using
the atomic cycle mechanism. This could cause functional failures in a shared flash
environment. Write Enable opcodes should only be programmed in the Prefix Opcodes.
Bit Description
63:56 Allowable Opcode 7—R/W. See the description for bits 7:0
55:48 Allowable Opcode 6—R/W. See the description for bits 7:0
47:40 Allowable Opcode 5—R/W. See the description for bits 7:0
39:32 Allowable Opcode 4—R/W. See the description for bits 7:0
31:24 Allowable Opcode 3—R/W. See the description for bits 7:0
23:16 Allowable Opcode 2—R/W. See the description for bits 7:0
15:8 Allowable Opcode 1—R/W. See the description for bits 7:0
Allowable Opcode 0—R/W. Software programs an SPI opcode into this field for use
7:0
when initiating SPI commands through the Control Register.
This register is not writable when the SPI Configuration Lock-Down bit (MBARB +
00h:15) is set.
§§
908 Datasheet
Thermal Sensor Registers (D31:F6)
22 Thermal Sensor Registers
(D31:F6)
22.1 PCI Bus Configuration Registers
Table 22-1. Thermal Sensor Register Address Map
Offset Mnemonic Register Name Default Attribute
00h–01h VID Vendor Identification 8086h RO
02h–03h DID Device Identification 3A32h RO
04h–05h CMD Command Register 0000h R/W, RO
06h–07h STS Device Status 0010h R/WC, RO
08h RID Revision ID 00h RO
09h PI Programming Interface 00h RO
0Ah SCC Sub Class Code 80h RO
0Bh BCC Base Class Code 11h RO
0Ch CLS Cache Line Size 00h RO
0Dh LT Latency Timer 00h RO
0Eh HTYPE Header Type 00h RO
10h–13h TBAR Thermal Base Address 00000004h R/W, RO
14h–17h TBARH Thermal Base Address High DWord 00000000h RO
2Ch–2Dh SVID Subsystem Vendor Identifier 0000h R/WO
2Eh–2Fh SID Subsystem Identifier 0000h R/WO
34h CAP_PTR Capabilities Pointer 50h RO
3Ch INTLN Interrupt Line 00h R/W
See
3Dh INTPN Interrupt Pin RO
Description
40h–43h TBARB BIOS Assigned Thermal Base Address 00000004h R/W, RO
BIOS Assigned Thermal Base High
44h–47h TBARBH 00000000h R/W
DWord
50h–51h PID PCI Power Management Capability ID 0001h RO
52h–53h PC Power Management Capabilities 0023h RO
54h–57h PCS Power Management Control and Status 0008h R/W, RO
Datasheet 909
Thermal Sensor Registers (D31:F6)
22.1.1 VID—Vendor Identification Register
Offset Address: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bit
Lockable: No Power Well: Core
Bit Description
15:0 Vendor ID—RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
22.1.2 DID—Device Identification Register
Offset Address: 02h–03h Attribute: RO
Default Value: 3A32h Size: 16 bits
Bit Description
15:0 Device ID (DID)—RO. Indicates the device number assigned by the SIG.
22.1.3 CMD—Command Register
Address Offset: 04h–05h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved
Interrupt Disable (ID)—R/W. Enables the device to assert an INTx#.
10 0 = When cleared, the INTx# signal may be asserted.
1 = When set, the Thermal logic’s INTx# signal will be de-asserted.
9 FBE (Fast Back to Back Enable)—RO. Hardwired to 0.
8 SEN (SERR Enable)—RO. Hardwired to 0.
7 WCC (Wait Cycle Control)—RO. Hardwired to 0.
6 PER (Parity Error Response)—RO. Hardwired to 0.
5 VPS (VGA Palette Snoop)—RO. Hardwired to 0.
4 MWI (Memory Write and Invalidate Enable)—RO. Hardwired to 0.
3 SCE (Special Cycle Enable)—RO. Hardwired to 0.
BME (Bus Master Enable)—R/W.
2 0 = Function disabled as bus master.
1 = Function enabled as bus master.
Memory Space Enable (MSE)—R/W.
1 0 = Disable
1 = Enable. Enables memory space accesses to the Thermal registers.
IOS (I/O Space)—RO. The Thermal logic does not implement I/O Space; therefore,
0
this bit is hardwired to 0.
910 Datasheet
Thermal Sensor Registers (D31:F6)
22.1.4 STS—Status Register
Address Offset: 06h–07h Attribute: R/WC, RO
Default Value: 0010h Size: 16 bits
Bit Description
Detected Parity Error (DPE)—R/WC. This bit is set whenever a parity error is seen
15 on the internal interface for this function, regardless of the setting of bit 6 in the
command register. Software clears this bit by writing a 1 to this bit location.
14 SERR# Status (SERRS)—RO. Hardwired to 0.
13 Received Master Abort (RMA)—RO. Hardwired to 0.
12 Received Target Abort (RTA)—RO. Hardwired to 0.
11 Signaled Target-Abort (STA)—RO. Hardwired to 0.
10:9 DEVSEL# Timing Status (DEVT)—RO. Hardwired to 0.
8 Master Data Parity Error (MDPE)—RO. Hardwired to 0.
7 Fast Back to Back Capable (FBC)—RO. Hardwired to 0.
6 Reserved
5 66 MHz Capable (C66)—RO. Hardwired to 0.
Capabilities List Exists (CLIST)—RO. Indicates that the controller contains a
4 capabilities pointer list. The first item is pointed to by looking at configuration offset
34h.
Interrupt Status (IS)—RO. Reflects the state of the INTx# signal at the input of the
enable/disable circuit. This bit is a 1 when the INTx# is asserted. This bit is a 0 after
3
the interrupt is cleared (independent of the state of the Interrupt Disable bit in the
command register).
2:0 Reserved
22.1.5 RID—Revision Identification Register
Address Offset: 08h Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
7:0 Revision ID (RID)—RO. This field indicates the device specific revision identifier.
22.1.6 PI—Programming Interface Register
Address Offset: 09h Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
Programming Interface (PI)—RO. The PCH Thermal logic has no standard
7:0
programming interface.
Datasheet 911
Thermal Sensor Registers (D31:F6)
22.1.7 SCC—Sub Class Code Register
Address Offset: 0Ah Attribute: RO
Default Value: 80h Size: 8 bits
Bit Description
7:0 Sub Class Code (SCC)—RO. Value assigned to the PCH Thermal logic.
22.1.8 BCC—Base Class Code Register
Address Offset: 0Bh Attribute: RO
Default Value: 11h Size: 8 bits
Bit Description
7:0 Base Class Code (BCC)—RO. Value assigned to the PCH Thermal logic.
22.1.9 CLS—Cache Line Size Register
Address Offset: 0Ch Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
7:0 Cache Line Size (CLS)—RO. Does not apply to PCI Bus Target-only devices.
22.1.10 LT—Latency Timer Register
Address Offset: 0Dh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
7:0 Latency Timer (LT)—RO. Does not apply to PCI Bus Target-only devices.
22.1.11 HTYPE—Header Type Register
Address Offset: 0Eh Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
Multi-Function Device (MFD)—RO. This bit is 0 because a multi-function device only
7 needs to be marked as such in Function 0, and the Thermal registers are not in
Function 0.
6:0 Header Type (HTYPE)—RO. Implements Type 0 Configuration header.
912 Datasheet
Thermal Sensor Registers (D31:F6)
22.1.12 TBAR—Thermal Base Register
Address Offset: 10h–13h Attribute: R/W, RO
Default Value: 00000004h Size: 32 bits
This BAR creates 4K bytes of memory space to signify the base address of Thermal
memory mapped configuration registers. This memory space is active when the
Command (CMD) register Memory Space Enable (MSE) bit is set and either
TBAR[31:12] or TBARH are programmed to a non-zero address. This BAR is owned by
the Operating System, and allows the OS to locate the Thermal registers in system
memory space.
Bit Description
Thermal Base Address (TBA)—R/W. This field provides the base address for the
31:12 Thermal logic memory mapped configuration registers. 4 KB bytes are requested by
hardwiring bits 11:4 to 0s.
11:4 Reserved
3 Prefetchable (PREF)—RO. Indicates that this BAR is NOT pre-fetchable.
Address Range (ADDRNG)—RO. Indicates that this BAR can be located anywhere in
2:1
64 bit address space.
0 Space Type (SPTYP)—RO. Indicates that this BAR is located in memory space.
22.1.13 TBARH—Thermal Base High DWord Register
Address Offset: 14h–17h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
This BAR extension holds the high 32 bits of the 64 bit TBAR. In conjunction with TBAR,
it creates 4 KB of memory space to signify the base address of Thermal memory
mapped configuration registers.
Bit Description
31:0 Thermal Base Address High (TBAH)—R/W. TBAR bits 61:32.
22.1.14 SVID—Subsystem Vendor ID Register
Address Offset: 2Ch–2Dh Attribute: R/WO
Default Value: 0000h Size: 16 bits
This register should be implemented for any function that could be instantiated more
than once in a given system. The SVID register, in combination with the Subsystem ID
register, enables the operating environment to distinguish one subsystem from the
other(s).
Software (BIOS) will write the value to this register. After that, the value can be read,
but writes to the register will have no effect. The write to this register should be
combined with the write to the SID to create one 32-bit write. This register is not
affected by D3HOT to D0 reset.
Bit Description
15:0 SVID (SVID)—R/WO. These R/WO bits have no PCH functionality.
Datasheet 913
Thermal Sensor Registers (D31:F6)
22.1.15 SID—Subsystem ID Register
Address Offset: 2Eh–2Fh Attribute: R/WO
Default Value: 0000h Size: 16 bits
This register should be implemented for any function that could be instantiated more
than once in a given system. The SID register, in combination with the Subsystem
Vendor ID register make it possible for the operating environment to distinguish one
subsystem from the other(s).
Software (BIOS) will write the value to this register. After that, the value can be read,
but writes to the register will have no effect. The write to this register should be
combined with the write to the SVID to create one 32-bit write. This register is not
affected by D3HOT to D0 reset.
Bit Description
15:0 SID (SAID)—R/WO. These R/WO bits have no PCH functionality.
22.1.16 CAP_PTR—Capabilities Pointer Register
Address Offset: 34h Attribute: RO
Default Value: 50h Size: 8 bits
Bit Description
Capability Pointer (CP)—RO. Indicates that the first capability pointer offset is offset
7:0
50h (Power Management Capability).
22.1.17 INTLN—Interrupt Line Register
Address Offset: 3Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Interrupt Line—R/W. PCH hardware does not use this field directly. It is used to
7:0
communicate to software the interrupt line that the interrupt pin is connected to.
22.1.18 INTPN—Interrupt Pin Register
Address Offset: 3Dh Attribute: RO
Default Value: See description Size: 8 bits
Bit Description
7:4 Reserved
Interrupt Pin—RO. This reflects the value of the Device 31 interrupt pin bits 27:24
3:0
(TTIP) in chipset configuration space.
914 Datasheet
Thermal Sensor Registers (D31:F6)
22.1.19 TBARB—BIOS Assigned Thermal Base Address Register
Address Offset: 40h–43h Attribute: R/W, RO
Default Value: 00000004h Size: 32 bits
This BAR creates 4 KB of memory space to signify the base address of Thermal memory
mapped configuration registers. This memory space is active when TBARB.SPTYPEN is
asserted. This BAR is owned by the BIOS, and allows the BIOS to locate the Thermal
registers in system memory space. If both TBAR and TBARB are programmed, then the
OS and BIOS each have their own independent “view” of the Thermal registers, and
must use the TSIU register to denote Thermal registers ownership/availability.
Bit Description
Thermal Base Address (TBA)—R/W. This field provides the base address for the
31:12 Thermal logic memory mapped configuration registers. 4K B bytes are requested by
hardwiring bits 11:4 to 0s.
11:4 Reserved
3 Prefetchable (PREF)—RO. Indicates that this BAR is NOT pre-fetchable.
Address Range (ADDRNG)—RO. Indicates that this BAR can be located anywhere in
2:1
64 bit address space.
Space Type Enable (SPTYPEN)—R/W.
0 0 = Disable.
1 = Enable. When set to 1b by software, enables the decode of this memory BAR.
22.1.20 TBARBH—BIOS Assigned Thermal Base High
DWord Register
Address Offset: 44h–47h Attribute: R/W
Default Value: 00000000h Size: 32 bits
This BAR extension holds the high 32 bits of the 64 bit TBARB.
Bit Description
31:0 Thermal Base Address High (TBAH)—R/W. TBAR bits 61:32.
22.1.21 PID—PCI Power Management Capability ID Register
Address Offset: 50h–51h Attribute: RO
Default Value: 0001h Size: 16 bits
Bit Description
Next Capability (NEXT)—RO. Indicates that this is the last capability structure in the
15:8
list.
7:0 Cap ID (CAP)—RO. Indicates that this pointer is a PCI power management capability
Datasheet 915
Thermal Sensor Registers (D31:F6)
22.1.22 PC—Power Management Capabilities Register
Address Offset: 52h–53h Attribute: RO
Default Value: 0023h Size: 16 bits
Bit Description
15:11 PME_Support—RO. Indicates PME# is not supported
10 D2_Support—RO. The D2 state is not supported.
9 D1_Support—RO. The D1 state is not supported.
Aux_Current—RO. PME# from D3COLD state is not supported, therefore this field is
8:6
000b.
Device Specific Initialization (DSI)—RO. Indicates that device-specific initialization
5
is required.
4 Reserved
3 PME Clock (PMEC)—RO. Does not apply. Hardwired to 0.
Version (VS)—RO. Indicates support for Revision 1.2 of the PCI Power Management
2:0
Specification.
22.1.23 PCS—Power Management Control And Status Register
Address Offset: 54h–57h Attribute: R/W, RO
Default Value: 0008h Size: 32 bits
Bit Description
31:24 Data—RO. Does not apply. Hardwired to 0s.
23 Bus Power/Clock Control Enable (BPCCE)—RO. Hardwired to 0.
22 B2/B3 Support (B23)—RO. Does not apply. Hardwired to 0.
21:16 Reserved
PME Status (PMES)—RO. This bit is always 0, since this PCI Function does not
15
generate PME#.
14:9 Reserved
PME Enable (PMEE)—RO. This bit is always zero, since this PCI Function does not
8
generate PME#.
7:4 Reserved
No Soft Reset—RO. When set 1, this bit indicates that devices transitioning from
D3HOT to D0 because of PowerState commands do not perform an internal reset.
3 Configuration context is preserved. Upon transition from D3HOT to D0 initialized state,
no additional operating system intervention is required to preserve Configuration
Context beyond writing the PowerState bits.
2 Reserved
Power State (PS)—R/W. This field is used both to determine the current power state
of the Thermal controller and to set a new power state. The values are:
00 = D0 state
11 = D3HOT state
1:0 If software attempts to write a value of 10b or 01b in to this field, the write operation
must complete normally; however, the data is discarded and no state change occurs.
When in the D3HOT states, the Thermal controller’s configuration space is available, but
the I/O and memory spaces are not. Additionally, interrupts are blocked.
When software changes this value from the D3HOT state to the D0 state, no internal
warm (soft) reset is generated.
916 Datasheet
Thermal Sensor Registers (D31:F6)
22.2 Thermal Memory Mapped Configuration Registers
(Thermal Sensor – D31:F26)
The base memory for these thermal memory mapped configuration registers is
specified in the TBARB (D31:F6:Offset 40h) register. The individual registers are then
accessible at TBARB + Offset.
All registers in Table 22-2 are located in the Core Well.
Table 22-2. Thermal Memory Mapped Configuration Register Address Map
Offset Mnemonic Register Name Default Attribute
00h–01h TEMP Temperature 0000h RO
04h TSC Thermal Sensor Control 00h RO, R/W
RO, R/W,
06h TSS Thermal Sensor Status 00h
R/WC
08h TSEL Thermal Sensor Enable and Lock 00h RO, R/W
Thermal Sensor Report Enable
0Ah TSREL 00h RO, R/W
and Lock
0Ch TSMIC Thermal Sensor SMI Control 00h RO, R/W
10h–11h CTT Catastrophic Trip Point 01FFh RO, R/W
14h–15h TAHV Thermal Alert High Value 0000h RO, R/W
18h–19h TALV Thermal Alert Low Value 0000h RO, R/W
40h–43h TL Throttle Levels 00000000h RO, R/W
60h–61h PHL PCH Hot Level 0000h RO, R/W
62h PHLC PHL Control 00h RO, R/W
RO, R/W,
80h TAS Thermal Alert Status 00h
R/WC
82h TSPIEN PCI Interrupt Event Enables 00h RO, R/W
84h TSGPEN General Purpose Event Enables 00h RO, R/W
22.2.1 TEMP—Temperature Register
Offset Address: TBARB+00h Attribute: RO
Default Value: 0000h Size: 16 bit
Bit Description
15:9 Reserved
TS Reading (TSR)—RO. The die temperature with resolution of 1/2 degree C and an
8:0
offset of -50 °C. Thus, a reading of 0x121 is 94.5C.
Datasheet 917
Thermal Sensor Registers (D31:F6)
22.2.2 TSC—Thermal Sensor Control Register
Offset Address: TBARB+04h Attribute: RO, R/W
Default Value: 00h Size: 8 bit
This register controls the operation of the thermal sensor.
Bit Description
Policy Lock-Down Bit—R/W. When written to 1, this bit prevents any more writes to
7
the register (offset 04h) and to CTT (offset 10h)
6:1 Reserved
Catastrophic Power-Down Enable—R/W. When set to 1, the power management
logic (PMC) transitions to the S5 state when a catastrophic temperature is detected by
the sensor. The transition to the S5 state must be unconditional (like the Power Button
0
Override Function). The thermal sensor and response logic is in the core/main power
well; therefore, detection of a catastrophic temperature is limited to times when this
well is powered and out of reset.
22.2.3 TSS—Thermal Sensor Status Register
Offset Address: TBARB+06h Attribute: RO, R/W
Default Value: 00h Size: 8 bit
This register provides statuses of the thermal sensor.
Bit Description
7:5 Reserved
Thermal Sensor Dynamic Shutdown Status (TSDSS)—RO. This bit indicates the
status of the thermal sensor circuit when TSEL.ETS=1.
4
1 = thermal sensor is fully operational
0 = thermal sensor is in a dynamic shutdown state
GPE Status (GPES)—R/WC. Set when GPE is enabled for a trip event. Software must
write a ‘1’ to this bit to clear the GPE status. GPE can be configured to cause an SMI or
3
SCI.
As long as this bit is set, the GPE indication to the global GPE logic is asserted.
SMI Status (SMIS)—R/WC. Set when SMI is enabled for a trip event. Software must
2 write a ‘1’ to this bit to clear the SMI status.
As long as this bit is set, the SMI indication to the global SMI logic is asserted.
1:0 Reserved
918 Datasheet
Thermal Sensor Registers (D31:F6)
22.2.4 TSEL—Thermal Sensor Enable and Lock Register
Offset Address: TBARB+08h Attribute: RO, R/W
Default Value: 00h Size: 8 bit
This register controls the operation of the thermal sensor.
Bit Description
Policy Lock-Down Bit—R/W. When written to 1, this bit prevents any more writes to
7
this register.
6:1 Reserved
Enable TS (ETS)—R/W.
1 = Enables the thermal sensor. Until this bit is set, no thermometer readings or trip
events will occur. If SW reads the TEMP register before the sensor is enabled, it
will read 0x0. The value of this bit is sent to the thermal sensor. NOTE: if the
0 sensor is running and valid temperatures have been captured in TEMP and then
ETS is cleared, TEMP will retain its old value. Clearing ETS does not force TEMP to
0x00.
0 = Disables the sensor.
22.2.5 TSREL—Thermal Sensor Reporting Enable and Lock
Register
Offset Address: TBARB+0Ah Attribute: RO, R/W
Default Value: 00h Size: 8 bit
Bit Description
Policy Lock-Down Bit—R/W. When written to 1, this bit prevents anymore writes to
7
this register.
6:1 Reserved
Enable SMBus Temperature Reporting—R/W.
1 = Enables the reporting of the PCH temperature to the SMBus and PMC. This must
also be set if ME needs access to the PCH temperature. Once enabled this bit
0 should not be cleared by software. If it is cleared then the EC may get an
undefined value. Software has no need to dynamically disable and then re-enable
this bit.
0 = Disables temperature reporting.
22.2.6 TSMIC—Thermal Sensor SMI Control Register
Offset Address: TBARB+0Ch Attribute: RO, R/W
Default Value: 00h Size: 8 bit
Bit Description
Policy Lock-Down Bit—R/W. When written to 1, this bit prevents anymore writes to
7
this register.
6:1 Reserved
SMI Enable on Alert Thermal Sensor Trip—R/W.
1 = Enables SMI# assertions on alert thermal sensor events for either low-to-high or
0
high-to-low events. Both edges are enabled by this one bit.
0 = Disables SMI# assertions for alert thermal events.
Datasheet 919
Thermal Sensor Registers (D31:F6)
22.2.7 CTT—Catastrophic Trip Point Register
Offset Address: TBARB+10h Attribute: RO, R/W
Default Value: 01FFh Size: 16 bit
Bit Description
15:9 Reserved
Catastrophic Temperature TRIP (CTRIP)—R/W. When the current temperature
reading is greater than or equal to the value in this register, a catastrophic trip event
8:0
is signaled.
This register is locked by TSC[7]
22.2.8 TAHV—Thermal Alert High Value Register
Offset Address: TBARB+14h Attribute: RO, R/W
Default Value: 0000h Size: 16 bit
Bit Description
15:9 Reserved
Alert High (AH)—R/W. Sets the high value for the alert indication. See the later
section for usage.
8:0
NOTE: It is illegal for SW to program AH to a value less than TALV.AL.
This register is not lockable, so that SW can change the values during runtime.
22.2.9 TALV—Thermal Alert Low Value Register
Offset Address: TBARB+18h Attribute: R/W, RO
Default Value: 0000h Size: 16 bit
Bit Description
15:9 Reserved
Alert Low (AL)—R/W. Sets the low value for the alert indication. See the later section
8:0 for usage.
This register is not lockable, so that SW can change the values during runtime.
920 Datasheet
Thermal Sensor Registers (D31:F6)
22.2.10 TL—Throttle Levels Register
Offset Address: TBARB+40h Attribute: RO, R/W
Default Value: 00000000h Size: 32 bit
Bit Description
TT.Lock – R/W. When set to ‘1’, this entire register (TL) is locked and remains locked
31
until the next platform reset.
TT.State13 Enable (TT13EN) – R/W. When set to ‘1’ and the programmed GPIO pin
30
is a ‘1’, then PMSync state 13 will force at least T2 state.
TT Enable (TTEN) – R/W. When set the thermal throttling states are enabled. At
reset, BIOS must set bits 28:0 and then do a separate write to set bit 29 to enable
throttling. SW may set bit 31 at the same time it sets bit 29 if it wishes to lock the
register. If SW wishes to change the values of 28:0, it must first clear the TTEN bit,
then change the values in 28:0; and then re-enable TTEN. It is legal to set bits 31, 30
and 29 with the same write.
29
This bit must not be set by SW until SW has already enabled the thermal
sensor(TSEL.ETS =’1’).
If TTEN is written to ‘0’, after having been enabled, then the PCH may stay in the
throttling state it was in at the moment TTEN is disabled. There is no intent that the
sensor be enabled for a while and then disabled and left off. It may be disabled
temporarily while changing the register values, but it should not be left in the disabled
state.
T2 Level (T2L) – R/W. When TTEN = 1 AND TSE = ‘1’ AND (T2L >= TSR[8:0] > T1L),
then the system is in T2 state.
When TTEN = 1 AND TSE = ‘1’ AND (TSR[8:0] > T2L), then the system is in T3 state.
28:20
NOTE: The T3 condition overrides PMSync[13] and forces the system to T3 if both
cases are true.
SW NOTE:T2L must be programmed to a value greater than T1L if TTEN=’1’
19 Reserved
T1 Level (T1L) – R/W. When TTEN = 1 AND TSE = 1 AND (T1L >= TSR[8:0] > T0L),
then the system is in T1 state.
18:10
SW NOTE:T1L must be programmed to a value greater than T0L if TTEN=’1’
9 Reserved
T0 Level (T0L) – R/W. When TEMP.TSR[8:0] <= T0L OR TT.Enable is ‘0’ OR TSE 0’,
8:0
then the system is in T0 state.
Datasheet 921
Thermal Sensor Registers (D31:F6)
22.2.11 PHL—PCH Hot Level Register
Offset Address: TBARB+60h Attribute: RO, R/W
Default Value: 0000h Size: 16 bit
Bit Description
PHL Enable (PHLE) – R/W. When set and the current temperature reading, TSR, is
15
greater than PHLL, then the TEMP_ALERT# pin will be asserted (active low).
14:9 Reserved
8:0 PHL Level (PHLL) – R/W. Temperature value used for TEMP_ALERT# pin.
22.2.12 PHLC—PHL Control Register
Offset Address: TBARB+62h Attribute: RO, R/W
Default Value: 00h Size: 8 bit
Bit Description
7:1 Reserved
0 PHL Lock – R/W. When written to a ‘1’, then both PHL and PHLC are locked
22.2.13 TAS—Thermal Alert Status Register
Offset Address: TBARB+80h Attribute: RO, R/W
Default Value: 00h Size: 8 bit
Bit Description
7:2 Reserved
Alert High-to-Low Event (AHLE)—R/WC.
1 = Indicates that a Hot Thermal Sensor trip event occurred based on a lower to
1 higher temperature transition thru the trip point.
0 = No trip for this event
Software must write a 1 to clear this status bit.
Alert Low-to-High Event (ALHE)—R/WC.
1 = Indicates that an Aux Thermal Sensor trip event occurred based on a lower to
higher temperature transition thru the trip point.
0 = No trip for this event
0
Software must write a 1 to clear this status bit.
NOTE: AHLE will not be set until there has been one occurrence of a Low to High event
(ALHE must have been set once). This prevents the case where the system
power up at a reasonably high temperature and starts to cool off while booting
and causing an interrupt before there is SW loaded to handle it.
922 Datasheet
Thermal Sensor Registers (D31:F6)
22.2.14 TSPIEN—PCI Interrupt Event Enables Register
Offset Address: TBARB+82h Attribute: RO, R/W
Default Value: 00h Size: 8 bit
Bit Description
7:2 Reserved
Alert High-to-Low Enable—R/W. When set to 1, the thermal sensor logic asserts the
Thermal logic PCI INTx signal when the corresponding status bit is set in the Thermal
1
Error Status register. When cleared, the corresponding status bit does not result in PCI
INTx.
0 Alert Low-to-High Enable—R/W. See the description for bit 1
22.2.15 TSGPEN—General Purpose Event Enables Register
Offset Address: TBARB+84h Attribute: RO, R/W
Default Value: 00h Size: 8 bit
Bit Description
7:2 Reserved
Alert High-to-Low Enable—R/W. When set to 1, the thermal sensor logic asserts its
General Purpose Event signal to the GPE block when the corresponding status bit is set
1
in the Thermal Error Status register. When cleared, the corresponding status bit does
not result in the GPE signal assertion.
Alert Low-to-High Enable—R/W. See the description for bit 1.
§§
Datasheet 923
Thermal Sensor Registers (D31:F6)
924 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23 Intel® Management Engine
(Intel® ME) Subsystem
Registers (D22:F[3:0])
23.1 First Intel® Management Engine Interface
(Intel® MEI) Configuration Registers
(Intel® MEI 1—D22:F0)
23.1.1 PCI Configuration Registers (Intel® MEI 1—D22:F0)
/
Table 23-1. Intel® MEI 1 Configuration Registers Address Map
(Intel® MEI 1—D22:F0) (Sheet 1 of 2)
Offset Mnemonic Register Name Default Attribute
00h–01h VID Vendor Identification 8086h RO
See register
02h–03h DID Device Identification RO
description
04h–05h PCICMD PCI Command 0000h R/W, RO
06h–07h PCISTS PCI Status 0010h RO
See
08h RID Revision Identification register RO
description
09h–0Bh CC Class Code 078000h RO
0Eh HTYPE Header Type 80h RO
000000000
10h–17h MEI0_MBAR Intel MEI 1 MMIO Base Address R/W, RO
0000004h
2Ch–2Dh SVID Subsystem Vendor ID 0000h R/WO
2Eh–2Fh SID Subsystem ID 0000h R/WO
34h CAPP Capabilities List Pointer 50h RO
3Ch–3Dh INTR Interrupt Information 0100h R/W, RO
40h–43h HFS Host Firmware Status 00000000h RO
44h–47h ME_UMA Management Engine UMA Register 10000000h RO
48h–4Bh GMES General Intel ME Status 00000000h RO
4Ch–4Fh H_GS Host General Status 00000000h R/W
50h–51h PID PCI Power Management Capability ID 8C01h RO
52h–53h PC PCI Power Management Capabilities C803h RO
PCI Power Management Control and R/WC,
54h–55h PMCS 0008h
Status R/W, RO
60h-63h GMES2 General Intel ME Status 2 00000000h RO
64h-67h GMES3 General Intel ME Status 3 00000000h RO
68h-6Bh GMES4 General Intel ME Status 4 00000000h RO
Datasheet 925
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
Table 23-1. Intel® MEI 1 Configuration Registers Address Map
(Intel® MEI 1—D22:F0) (Sheet 2 of 2)
Offset Mnemonic Register Name Default Attribute
6Ch-6Fh GMES5 General Intel ME Status 5 00000000h RO
70h-73h H_GS2 Host General Status 2 00000000h RW
74h-77h H_GS3 Host General Status 3 00000000h RW
8Ch–8Dh MID Message Signaled Interrupt Identifiers 0005h RO
Message Signaled Interrupt Message
8Eh–8Fh MC 0080h R/W, RO
Control
Message Signaled Interrupt Message
90h–93h MA 00000000h R/W, RO
Address
Message Signaled Interrupt Upper
94h–97h MUA 00000000h R/W
Address
98h–99h MD Message Signaled Interrupt Message Data 0000h R/W
A0h HIDM Intel MEI Interrupt Delivery Mode 00h R/W
BCh–BFh HERES Intel MEI Extended Register Status 40000000h RO
C0h–DFh HER[1:8] Intel MEI Extended Register DW[1:8] 00000000h RO
23.1.1.1 VID—Vendor Identification Register
(Intel® MEI 1—D22:F0)
Address Offset: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bits
Bit Description
15:0 Vendor ID (VID)—RO. This is a 16-bit value assigned to Intel.
23.1.1.2 DID—Device Identification Register
(Intel® MEI 1—D22:F0)
Address Offset: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bits
Bit Description
Device ID (DID)—RO. This is a 16-bit value assigned to the Intel Management Engine
15:0
Interface controller. See Section 1.3 for the value of the DID Register.
926 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.1.1.3 PCICMD—PCI Command Register
(Intel® MEI 1—D22:F0)
Address Offset: 04h–05h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved
Interrupt Disable (ID)—R/W. Disables this device from generating PCI line based
10
interrupts. This bit does not have any effect on MSI operation.
9:3 Reserved
Bus Master Enable (BME)—R/W.
Controls the Intel MEI host controller's ability to act as a system memory master for
data transfers. When this bit is cleared, Intel ME bus master activity stops and any
active DMA engines return to an idle condition. This bit is made visible to firmware
through the H_PCI_CSR register, and changes to this bit may be configured by the
2 H_PCI_CSR register to generate an Intel ME MSI. When this bit is 0, Intel MEI is
blocked from generating MSI to the host processor.
NOTE: This bit does not block Intel MEI accesses to Intel ME UMA; that is, writes or
reads to the host and Intel ME circular buffers through the read window and
write window registers still cause Intel ME backbone transactions to Intel ME
UMA.
Memory Space Enable (MSE)—R/W. Controls access to the Intel ME memory mapped
register space.
1 0 = Disable. Memory cycles within the range specified by the memory base and limit
registers are master aborted.
1 = Enable. Allows memory cycles within the range specified by the memory base and
limit registers accepted.
0 Reserved
23.1.1.4 PCISTS—PCI Status Register
(Intel® MEI 1—D22:F0)
Address Offset: 06h–07h Attribute: RO
Default Value: 0010h Size: 16 bits
Bit Description
15:5 Reserved
4 Capabilities List (CL)—RO. Indicates the presence of a capabilities list, hardwired to 1.
Interrupt Status (IS)—RO. Indicates the interrupt status of the device.
3 0 = Interrupt is de-asserted.
1 = Interrupt is asserted.
2:0 Reserved
Datasheet 927
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.1.1.5 RID—Revision Identification Register
(Intel® MEI 1—D22:F0)
Offset Address: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
Bit Description
Revision ID—RO. This field indicates the device specific revision identifier. See
7:0
Section 1.3 for the value of the RID Register.
23.1.1.6 CC—Class Code Register
(Intel® MEI 1—D22:F0)
Address Offset: 09h–0Bh Attribute: RO
Default Value: 078000h Size: 24 bits
Bit Description
23:16 Base Class Code (BCC)—RO. Indicates the base class code of the Intel MEI device.
15:8 Sub Class Code (SCC)—RO. Indicates the sub class code of the Intel MEI device.
Programming Interface (PI)—RO. Indicates the programming interface of the Intel
7:0
MEI device.
23.1.1.7 HTYPE—Header Type Register
(Intel® MEI 1—D22:F0)
Address Offset: 0Eh Attribute: RO
Default Value: 80h Size: 8 bits
Bit Description
Multi-Function Device (MFD)—RO. Indicates the Intel MEI host controller is part of
7
a multifunction device.
6:0 Header Layout (HL)—RO. Indicates that the Intel MEI uses a target device layout.
23.1.1.8 MEI0_MBAR—Intel® MEI 1 MMIO Base Address
(Intel® MEI 1—D22:F0)
Address Offset: 10h–17h Attribute: R/W, RO
Default Value: 0000000000000004h Size: 64 bits
This register allocates space for the MEI0 memory mapped registers.
Bit Description
Base Address (BA)—R/W. Software programs this field with the base address of this
63:4
region.
3 Prefetchable Memory (PM)—RO. Indicates that this range is not pre-fetchable.
Type (TP)—RO. Set to 10b to indicate that this range can be mapped anywhere in 64-
2:1
bit address space.
Resource Type Indicator (RTE)—RO. Indicates a request for register memory
0
space.
928 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.1.1.9 SVID—Subsystem Vendor ID Register
(Intel® MEI 1—D22:F0)
Address Offset: 2Ch–2Dh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Bit Description
Subsystem Vendor ID (SSVID)—R/WO. Indicates the sub-system vendor identifier.
This field should be programmed by BIOS during boot-up. Once written, this register
15:0
becomes Read Only. This field can only be cleared by PLTRST#.
NOTE: Register must be written as a Word write or as a DWord write with SID register.
23.1.1.10 SID—Subsystem ID Register
(Intel® MEI 1—D22:F0)
Address Offset: 2Eh–2Fh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Bit Description
Subsystem ID (SSID)—R/WO. Indicates the sub-system identifier. This field should
be programmed by BIOS during boot-up. Once written, this register becomes Read
15:0 Only. This field can only be cleared by PLTRST#.
NOTE: Register must be written as a Word write or as a DWord write with SVID
register.
23.1.1.11 CAPP—Capabilities List Pointer Register
(Intel® MEI 1—D22:F0)
Address Offset: 34h Attribute: RO
Default Value: 50h Size: 8 bits
Bit Description
Capabilities Pointer (PTR)—RO. Indicates that the pointer for the first entry in the
7:0
capabilities list is at 50h in configuration space.
23.1.1.12 INTR—Interrupt Information Register
(Intel® MEI 1—D22:F0)
Address Offset: 3Ch–3Dh Attribute: R/W, RO
Default Value: 0100h Size: 16 bits
Bit Description
Interrupt Pin (IPIN)—RO. This indicates the interrupt pin the Intel MEI host
15:8 controller uses. A value of 1h/2h/3h/4h indicates that this function implements legacy
interrupt on INTA/INTB/INTC/INTD, respectively.
Interrupt Line (ILINE)—R/W. Software written value to indicate which interrupt line
7:0
(vector) the interrupt is connected to. No hardware action is taken on this register.
Datasheet 929
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.1.1.13 HFS—Host Firmware Status Register
(Intel® MEI 1—D22:F0)
Address Offset: 40h–43h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
Host Firmware Status (HFS)—RO. This register field is used by Firmware to reflect
31:0
the operating environment to the host.
23.1.1.14 ME_UMA—Intel® Management Engine UMA Register
(Intel® MEI 1—D22:F0)
Address Offset: 44h–47h Attribute: RO
Default Value: 80000000h Size: 32 bits
Bit Description
Reserved—RO. Hardwired to 1. Can be used by host software to discover that this
31
register is valid.
30:7 Reserved
Intel ME UMA Size Valid—RO. This bit indicates that FW has written to the MUSZ
16
field.
15:6 Reserved
Intel ME UMA Size (MUSZ)—RO. This field reflect Intel ME Firmware’s desired size of
Intel ME UMA memory region. This field is set by Intel ME firmware prior to core power
bring up allowing BIOS to initialize memory.
000000b = 0 MB, No memory allocated to Intel ME UMA
000001b = 1 MB
5:0
000010b = 2 MB
000100b = 4 MB
001000b = 8 MB
010000b = 16 MB
100000b = 32 MB
23.1.1.15 GMES—General Intel® ME Status Register
(Intel® MEI 1—D22:F0)
Address Offset: 48h–4Bh Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:0 General Intel ME Status (ME_GS)—RO. This field is populated by Intel ME.
930 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.1.1.16 H_GS—Host General Status Register
(Intel® MEI 1—D22:F0)
Address Offset: 4Ch–4Fh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Host General Status(H_GS)—R/W. General Status of Host, this field is not used by
31:0
Hardware
23.1.1.17 PID—PCI Power Management Capability ID Register
(Intel® MEI 1—D22:F0)
Address Offset: 50h–51h Attribute: RO
Default Value: 8C01h Size: 16 bits
Bit Description
15:8 Next Capability (NEXT)—RO. Value of 8Ch indicates the location of the next pointer.
Capability ID (CID)—RO. Indicates the linked list item is a PCI Power Management
7:0
Register.
23.1.1.18 PC—PCI Power Management Capabilities Register
(Intel® MEI 1—D22:F0)
Address Offset: 52h–53h Attribute: RO
Default Value: C803h Size: 16 bits
Bit Description
PME_Support (PSUP)—RO. This five-bit field indicates the power states in which the
15:11 function may assert PME#. Intel MEI can assert PME# from any D-state except D1 or
D2 which are not supported by Intel MEI.
10:9 Reserved
Aux_Current (AC)—RO. Reports the maximum Suspend well current required when in
8:6
the D3cold state. Value of 00b is reported.
Device Specific Initialization (DSI)—RO. Indicates whether device-specific
5
initialization is required.
4 Reserved
3 PME Clock (PMEC)—RO. Indicates that PCI clock is not required to generate PME#.
Version (VS)—RO. Hardwired to 011b to indicate support for Revision 1.2 of the PCI
2:0
Power Management Specification.
Datasheet 931
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.1.1.19 PMCS—PCI Power Management Control and Status
Register (Intel® MEI 1—D22:F0)
Address Offset: 54h–55h Attribute: R/WC, R/W, RO
Default Value: 0008h Size: 16 bits
Bit Description
PME Status (PMES)—R/WC. Bit is set by Intel ME Firmware. Host software clears bit
15 by writing ‘1’ to bit.
This bit is reset when CL_RST# asserted.
14:9 Reserved
PME Enable (PMEE)—R/W. This bit is read/write and is under the control of host SW.
It does not directly have an effect on PME events. However, this bit is shadowed so Intel
8 ME FW can monitor it. Intel ME FW will not cause the PMES bit to transition to 1 while
the PMEE bit is 0, indicating that host SW had disabled PME.
This bit is reset when PLTRST# asserted.
7:4 Reserved
No_Soft_Reset (NSR)—RO. This bit indicates that when the Intel MEI host controller
3 is transitioning from D3hot to D0 due to a power state command, it does not perform an
internal reset. Configuration context is preserved.
2 Reserved
Power State (PS)—R/W. This field is used both to determine the current power state
of the Intel MEI host controller and to set a new power state. The values are:
00 = D0 state (default)
1:0 11 = D3hot state
The D1 and D2 states are not supported for the Intel MEI host controller. When in the
D3hot state, the Intel ME’s configuration space is available, but the register memory
spaces are not. Additionally, interrupts are blocked.
23.1.1.20 GMES2—General Intel® ME Status Register 2
(Intel® MEI 1—D22:F0)
Address Offset: 60h–63h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:0 General Intel ME Status 2 (ME_GS 2)—RO. This field is populated by Intel ME.
23.1.1.21 GMES3—General Intel® ME Status Register 3
(Intel® MEI 1—D22:F0)
Address Offset: 64h–67h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:0 General Intel ME Status 3 (ME_GS 3)—RO. This field is populated by Intel ME.
932 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.1.1.22 GMES4—General Intel® ME Status Register 4
(Intel® MEI 1—D22:F0)
Address Offset: 68h–6Bh Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:0 General Intel ME Status 4 (ME_GS 4)—RO. This field is populated by Intel ME.
23.1.1.23 GMES5—General Intel® ME Status Register 5
(Intel® MEI 1—D22:F0)
Address Offset: 6Ch–6Fh Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:0 General Intel ME Status 5 (ME_GS 5)—RO. This field is populated by Intel ME.
23.1.1.24 H_GS2—Host General Status Register 2
(Intel® MEI 1—D22:F0)
Address Offset: 70h–73h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Host General Status 2 (H_GS 2)—R/W. General Status of Host, this field is not used
31:0
by Hardware
23.1.1.25 H_GS3—Host General Status Register 3
(Intel® MEI 1—D22:F0)
Address Offset: 74h–77h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Host General Status 3( H_GS3)—R/W. General Status of Host, this field is not used
31:0
by Hardware
23.1.1.26 MID—Message Signaled Interrupt Identifiers Register
(Intel® MEI 1—D22:F0)
Address Offset: 8Ch-8Dh Attribute: RO
Default Value: 0005h Size: 16 bits
Bit Description
15:8 Next Pointer (NEXT)—RO. Value of 00h indicates that this is the last item in the list.
7:0 Capability ID (CID)—RO. Capabilities ID indicates MSI.
Datasheet 933
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.1.1.27 MC—Message Signaled Interrupt Message Control Register
(Intel® MEI 1—D22:F0)
Address Offset: 8Eh–8Fh Attribute: R/W, RO
Default Value: 0080h Size: 16 bits
Bit Description
15:8 Reserved
64 Bit Address Capable (C64)—RO. Specifies that function is capable of generating
7
64-bit messages.
6:1 Reserved
MSI Enable (MSIE)—R/W. If set, MSI is enabled and traditional interrupt pins are not
0
used to generate interrupts.
23.1.1.28 MA—Message Signaled Interrupt Message Address Register
(Intel® MEI 1—D22:F0)
Address Offset: 90h–93h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
Address (ADDR)—R/W. Lower 32 bits of the system specified message address,
31:2
always DW aligned.
1:0 Reserved
23.1.1.29 MUA—Message Signaled Interrupt Upper Address Register
(Intel® MEI 1—D22:F0)
Address Offset: 94h–97h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Upper Address (UADDR)—R/W. Upper 32 bits of the system specified message
31:0
address, always DW aligned.
23.1.1.30 MD—Message Signaled Interrupt Message Data Register
(Intel® MEI 1—D22:F0)
Address Offset: 98h–99h Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
Data (DATA)—R/W. This 16-bit field is programmed by system software if MSI is
15:0 enabled. Its content is driven during the data phase of the MSI memory write
transaction.
934 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.1.1.31 HIDM—MEI Interrupt Delivery Mode Register
(Intel® MEI 1—D22:F0)
Address Offset: A0h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:2 Reserved
Intel MEI Interrupt Delivery Mode (HIDM)—R/W. These bits control what type of
interrupt the Intel MEI will send the host. They are interpreted as follows:
1:0 00 = Generate Legacy or MSI interrupt
01 = Generate SCI
10 = Generate SMI
23.1.1.32 HERES—Intel® MEI Extend Register Status
(Intel® MEI 1—D22:F0)
Address Offset: BCh–BFh Attribute: RO
Default Value: 40000000h Size: 32 bits
Bit Description
Extend Register Valid (ERV)—RO. Set by firmware after all firmware has been
31 loaded. If ERA field is SHA-1, the result of the extend operation is in HER:5-1. If ERA
field is SHA-256, the result of the extend operation is in HER:8-1.
Extend Feature Present (EFP)—RO. This bit is hardwired to 1 to allow driver
30 software to easily detect the chipset supports the Extend Register FW measurement
feature.
29:4 Reserved
Extend Register Algorithm (ERA)—RO. This field indicates the hash algorithm used
in the FW measurement extend operations. Encodings are:
3:0 0h = SHA-1
2h = SHA-256
Other values = Reserved.
Datasheet 935
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.1.1.33 HERX—Intel® MEI Extend Register DWX
(Intel® MEI 1—D22:F0)
Address Offset: HER1: C0h–C3h Attribute: RO
HER2: C4h–C7h
HER3: C8h–CBh
HER4: CCh–CFh
HER5: D0h–D3h
HER6: D4h–D7h
HER7: D8h–dBh
HER8: DCh–DFh
Default Value: 00000000h Size: 32 bits
Bit Description
Extend Register DWX (ERDWX)—RO. Xth DWord result of the extend operation.
31:0
NOTE: Extend Operation is HER[5:1] if using SHA-1. If using SHA-256 then Extend
Operation is HER[8:1]
23.1.2 MEI0_MBAR—Intel® MEI 1 MMIO Registers
These MMIO registers are accessible starting at the Intel MEI 1 MMIO Base Address
(MEI0_MBAR) which gets programmed into D22:F0:Offset 10–17h. These registers are
reset by PLTRST# unless otherwise noted.
Table 23-2. Intel® MEI 1 MMIO Register Address Map
MEI0_MBAR+
Mnemonic Register Name Default Attribute
Offset
00–03h H_CB_WW Host Circular Buffer Write Window 00000000h W
RO, R/W,
04h–07h H_CSR Host Control Status 02000000h
R/WC
Intel ME Circular Buffer Read
08h–0Bh ME_CB_RW FFFFFFFFh RO
Window
Intel ME Control Status Host
0Ch–0Fh ME_CSR_HA 02000000h RO
Access
23.1.2.1 H_CB_WW—Host Circular Buffer Write Window Register
(Intel® MEI 1 MMIO Register)
Address Offset: MEI0_MBAR + 00h Attribute: W
Default Value: 00000000h Size: 32 bits
Bit Description
Host Circular Buffer Write Window Field (H_CB_WWF). This bit field is for host to
write into its circular buffer. The host's circular buffer is located at the Intel ME
subsystem address specified in the Host CB Base Address register. This field is write
31:0
only, reads will return arbitrary data. Writes to this register will increment the H_CBWP
as long as ME_RDY is 1. When ME_RDY is 0, writes to this register have no effect and
are not delivered to the H_CB, nor is H_CBWP incriminated.
936 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.1.2.2 H_CSR—Host Control Status Register
(Intel® MEI 1 MMIO Register)
Address Offset: MEI0_MBAR + 04h Attribute: RO, R/W, R/WC
Default Value: 02000000h Size: 32 bits
Bit Description
Host Circular Buffer Depth (H_CBD)—RO. This field indicates the maximum number
of 32 bit entries available in the host circular buffer (H_CB). Host software uses this
field along with the H_CBRP and H_CBWP fields to calculate the number of valid entries
in the H_CB to read or # of entries available for write.
31:24
This field is implemented with a "1-hot" scheme. Only one bit will be set to a "1" at a
time. Each bit position represents the value n of a buffer depth of (2^n). For example,
when bit# 1 is 1, the buffer depth is 2; when bit#2 is 1, the buffer depth is 4, and so
on. The allowed buffer depth values are 2, 4, 8, 16, 32, 64 and 128.
23:16 Host CB Write Pointer (H_CBWP)—RO. Points to next location in the H_CB for host
to write the data. Software uses this field along with H_CBRP and H_CBD fields to
calculate the number of valid entries in the H_CB to read or number of entries available
for write.
15:8 Host CB Read Pointer (H_CBRP)—RO. Points to next location in the H_CB where a
valid data is available for embedded controller to read. Software uses this field along
with H_CBWR and H_CBD fields to calculate the number of valid entries in the host CB
to read or number of entries available for write.
7:5 Reserved
NOTE: For writes to this register, these bits shall be written as 000b.
4 Host Reset (H_RST)—R/W. Setting this bit to 1 will initiate a Intel MEI reset sequence
to get the circular buffers into a known good state for host and Intel ME
communication. When this bit transitions from 0 to 1, hardware will clear the H_RDY
and ME_RDY bits.
3 Host Ready (H_RDY)—R/W. This bit indicates that the host is ready to process
messages.
2 Host Interrupt Generate (H_IG)—R/W. Once message(s) are written into its CB, the
host sets this bit to one for the HW to set the ME_IS bit in the ME_CSR and to generate
an interrupt message to Intel ME. HW will send the interrupt message to Intel ME only
if the ME_IE is enabled. HW then clears this bit to 0.
1 Host Interrupt Status (H_IS)—R/WC. Hardware sets this bit to 1 when ME_IG bit is
set to 1. Host clears this bit to 0 by writing a 1 to this bit position. H_IE has no effect on
this bit.
0 Host Interrupt Enable (H_IE)—R/W. Host sets this bit to 1 to enable the host
interrupt (INTR# or MSI) to be asserted when H_IS is set to 1.
Datasheet 937
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.1.2.3 ME_CB_RW—Intel® ME Circular Buffer Read Window Register
(Intel® MEI 1 MMIO Register)
Address Offset: MEI0_MBAR + 08h Attribute: RO
Default Value: FFFFFFFFh Size: 32 bits
Bit Description
Intel ME Circular Buffer Read Window Field (ME_CB_RWF). This bit field is for
host to read from the Intel ME Circular Buffer. The Intel ME circular buffer is located at
the Intel ME subsystem address specified in the Intel ME CB Base Address register. This
31:0
field is read only, writes have no effect. Reads to this register will increment the
ME_CBRP as long as ME_RDY is 1. When ME_RDY is 0, reads to this register have no
effect, all 1s are returned, and ME_CBRP is not incremented.
23.1.2.4 ME_CSR_HA—Intel® ME Control Status Host Access Register
(Intel® MEI 1 MMIO Register)
Address Offset: MEI0_MBAR + 0Ch Attribute: RO
Default Value: 02000000h Size: 32 bits
Bit Description
Intel ME Circular Buffer Depth Host Read Access (ME_CBD_HRA).
31:24
Host read only access to ME_CBD.
Intel ME CB Write Pointer Host Read Access (ME_CBWP_HRA).
23:16
Host read only access to ME_CBWP.
Intel ME CB Read Pointer Host Read Access (ME_CBRP_HRA).
15:8
Host read only access to ME_CBRP.
7:5 Reserved
Intel ME Reset Host Read Access (ME_RST_HRA).
4
Host read access to ME_RST.
Intel ME Ready Host Read Access (ME_RDY_HRA):
3
Host read access to ME_RDY.
Intel ME Interrupt Generate Host Read Access (ME_IG_HRA).
2
Host read only access to ME_IG.
Intel ME Interrupt Status Host Read Access (ME_IS_HRA).
1
Host read only access to ME_IS.
Intel ME Interrupt Enable Host Read Access (ME_IE_HRA).
0
Host read only access to ME_IE.
938 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.2 Second Intel® Management Engine Interface
(Intel® MEI 2) Configuration Registers
(Intel® MEI 2—D22:F1)
23.2.1 PCI Configuration Registers (Intel® MEI 2—D22:F2)
Table 23-3. Intel® MEI 2 Configuration Registers Address Map
(Intel® MEI 2—D22:F1) (Sheet 1 of 2)
Offset Mnemonic Register Name Default Attribute
00h–01h VID Vendor Identification 8086h RO
See register
02h–03h DID Device Identification RO
description
04h–05h PCICMD PCI Command 0000h R/W, RO
06h–07h PCISTS PCI Status 0010h RO
See register
08h RID Revision Identification RO
description
09h–0Bh CC Class Code 078000h RO
0Eh HTYPE Header Type 80h RO
00000000000
10h–17h MEI1_MBAR Intel MEI 2 MMIO Base Address R/W, RO
00004h
2Ch–2Dh SVID Subsystem Vendor ID 0000h R/WO
2Eh–2Fh SID Subsystem ID 0000h R/WO
34h CAPP Capabilities List Pointer 50h RO
3Ch–3Dh INTR Interrupt Information 0200h R/W, RO
40h–43h HFS Host Firmware Status 00000000h RO
48h–4Bh GMES General Intel ME Status 00000000h RO
4Ch–4Fh H_GS Host General Status 00000000h R/W
PCI Power Management Capability
50h–51h PID 8C01h RO
ID
PCI Power Management
52h–53h PC C803h RO
Capabilities
PCI Power Management Control R/WC, R/W,
54h–55h PMCS 0008h
and Status RO
60h–63h GMES2 General Intel ME Status 2 00000000h RO
64h–67h GMES3 General Intel ME Status 3 00000000h RO
68h–6Bh GMES4 General Intel ME Status 4 00000000h RO
6Ch–6Fh GMES5 General Intel ME Status 5 00000000h RO
70h–73h H_GS2 Host General Status 2 00000000h RW
74h–77h H_GS3 Host General Status 3 00000000h RW
Message Signaled Interrupt
8Ch–8Dh MID 0005h RO
Identifiers
Datasheet 939
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
Table 23-3. Intel® MEI 2 Configuration Registers Address Map
(Intel® MEI 2—D22:F1) (Sheet 2 of 2)
Offset Mnemonic Register Name Default Attribute
Message Signaled Interrupt
8Eh–8Fh MC 0080h R/W, RO
Message Control
Message Signaled Interrupt
90h–93h MA 00000000h R/W, RO
Message Address
Message Signaled Interrupt Upper
94h–97h MUA 00000000h R/W
Address
Message Signaled Interrupt
98h–99h MD 0000h R/W
Message Data
A0h HIDM Intel MEI Interrupt Delivery Mode 00h R/W
Intel MEI Extended Register
BC–BFh HERES 40000000h RO
Status
Intel MEI Extended Register
C0–DFh HER[1:8] 00000000h RO
DW[1:8]
23.2.1.1 VID—Vendor Identification Register
(Intel® MEI 2—D22:F1)
Address Offset: 00h–01h Attribute: RO
Default Value: 8086h Size: 16 bits
Bit Description
15:0 Vendor ID (VID)—RO. This is a 16-bit value assigned to Intel.
23.2.1.2 DID—Device Identification Register
(Intel® MEI 2—D22:F1)
Address Offset: 02h–03h Attribute: RO
Default Value: See bit description Size: 16 bits
Bit Description
Device ID (DID)—RO. This is a 16-bit value assigned to the Intel Management Engine
15:0
Interface controller. See Section 1.3 for the value of the DID Register.
940 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.2.1.3 PCICMD—PCI Command Register
(Intel® MEI 2—D22:F1)
Address Offset: 04h–05h Attribute: R/W, RO
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved
Interrupt Disable (ID)—R/W. Disables this device from generating PCI line based
10
interrupts. This bit does not have any effect on MSI operation.
9:3 Reserved
Bus Master Enable (BME)—R/W. Controls the Intel MEI host controller's ability to act
as a system memory master for data transfers. When this bit is cleared, Intel MEI bus
master activity stops and any active DMA engines return to an idle condition. This bit is
made visible to firmware through the H_PCI_CSR register, and changes to this bit may
be configured by the H_PCI_CSR register to generate an Intel ME MSI. When this bit is
2 0, Intel MEI is blocked from generating MSI to the host processor.
NOTE: This bit does not block Intel MEI accesses to Intel ME UMA; that is, writes or
reads to the host and Intel ME circular buffers through the read window and
write window registers still cause Intel ME backbone transactions to Intel ME
UMA.
Memory Space Enable (MSE)—R/W. Controls access to the Intel ME memory mapped
register space.
0 = Disable. Memory cycles within the range specified by the memory base and limit
1
registers are master aborted.
1 = Enable. Allows memory cycles within the range specified by the memory base and
limit registers accepted.
0 Reserved
23.2.1.4 PCISTS—PCI Status Register
(Intel® MEI 2—D22:F1)
Address Offset: 06h–07h Attribute: RO
Default Value: 0010h Size: 16 bits
Bit Description
15:5 Reserved
4 Capabilities List (CL)—RO. Indicates the presence of a capabilities list, hardwired to 1.
Interrupt Status—RO. Indicates the interrupt status of the device.
3 0 = Interrupt is de-asserted.
1 = Interrupt is asserted.
2:0 Reserved
Datasheet 941
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.2.1.5 RID—Revision Identification Register
(Intel® MEI 2—D22:F1)
Offset Address: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
Bit Description
Revision ID—RO. This field indicates the device specific revision identifier. See
7:0
Section 1.3 for the value of the RID Register.
23.2.1.6 CC—Class Code Register
(Intel® MEI 2—D22:F1)
Address Offset: 09h–0Bh Attribute: RO
Default Value: 078000h Size: 24 bits
Bit Description
23:16 Base Class Code (BCC)—RO. Indicates the base class code of the Intel MEI device.
15:8 Sub Class Code (SCC)—RO. Indicates the sub class code of the Intel MEI device.
Programming Interface (PI)—RO. Indicates the programming interface of the Intel
7:0
MEI device.
23.2.1.7 HTYPE—Header Type Register
(Intel® MEI 2—D22:F1)
Address Offset: 0Eh Attribute: RO
Default Value: 80h Size: 8 bits
Bit Description
Multi-Function Device (MFD)—RO. Indicates the Intel MEI host controller is part of a
7
multifunction device.
6:0 Header Layout (HL)—RO. Indicates that the Intel MEI uses a target device layout.
942 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.2.1.8 MEI1_MBAR—Intel MEI 2 MMIO Base Address
(Intel® MEI 2—D22:F1)
Address Offset: 10h–17h Attribute: R/W, RO
Default Value: 0000000000000004h Size: 64 bits
This register allocates space for the Intel MEI memory mapped registers.
Bit Description
Base Address (BA)—R/W. Software programs this field with the base address of this
63:4
region.
3 Prefetchable Memory (PM)—RO. Indicates that this range is not pre-fetchable.
Type (TP)—RO. Set to 10b to indicate that this range can be mapped anywhere in 64-
2:1
bit address space.
Resource Type Indicator (RTE)—RO. Indicates a request for register memory
0
space.
23.2.1.9 SVID—Subsystem Vendor ID Register
(Intel® MEI 2—D22:F1)
Address Offset: 2Ch–2Dh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Bit Description
Subsystem Vendor ID (SSVID)—R/WO. Indicates the sub-system vendor identifier.
This field should be programmed by BIOS during boot-up. Once written, this register
15:0
becomes Read Only. This field can only be cleared by PLTRST#.
NOTE: Register must be written as a Word write or as a DWord write with SID register.
23.2.1.10 SID—Subsystem ID Register
(Intel® MEI 2—D22:F1)
Address Offset: 2Eh–2Fh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Bit Description
Subsystem ID (SSID)—R/WO. Indicates the sub-system identifier. This field should
be programmed by BIOS during boot-up. Once written, this register becomes Read
Only. This field can only be cleared by PLTRST#.
15:0
NOTE: Register must be written as a Word write or as a DWord write with SVID
register.
Datasheet 943
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.2.1.11 CAPP—Capabilities List Pointer Register
(Intel® MEI 2—D22:F1)
Address Offset: 34h Attribute: RO
Default Value: 50h Size: 8 bits
Bit Description
Capabilities Pointer (PTR)—RO. Indicates that the pointer for the first entry in the
7:0
capabilities list is at 50h in configuration space.
23.2.1.12 INTR—Interrupt Information Register
(Intel® MEI 2—D22:F1)
Address Offset: 3Ch–3Dh Attribute: R/W, RO
Default Value: 0200h Size: 16 bits
Bit Description
Interrupt Pin (IPIN)—RO. This field indicates the interrupt pin the Intel MEI host
15:8 controller uses. A value of 1h/2h/3h/4h indicates that this function implements legacy
interrupt on INTA/INTB/INTC/INTD, respectively.
Interrupt Line (ILINE)—R/W. Software written value to indicate which interrupt line
7:0
(vector) the interrupt is connected to. No hardware action is taken on this register.
23.2.1.13 HFS—Host Firmware Status Register
(Intel® MEI 2—D22:F1)
Address Offset: 40h–43h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
Host Firmware Status (HFS)—RO. This register field is used by Firmware to reflect
31:0
the operating environment to the host.
23.2.1.14 GMES—General Intel® ME Status Register
(Intel® MEI 2—D22:F1)
Address Offset: 48h–4Bh Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:0 General Intel ME Status (ME_GS)—RO. This field is populated by Intel ME.
944 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.2.1.15 H_GS—Host General Status Register
(Intel® MEI 2—D22:F1)
Address Offset: 4Ch–4Fh Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Host General Status (H_GS)—R/W. General Status of Host, this field is not used by
31:0
Hardware
23.2.1.16 PID—PCI Power Management Capability ID Register
(Intel® MEI 2—D22:F1)
Address Offset: 50h–51h Attribute: RO
Default Value: 8C01h Size: 16 bits
Bit Description
15:8 Next Capability (NEXT)—RO. Value of 8Ch indicates the location of the next pointer.
Capability ID (CID)—RO. Indicates the linked list item is a PCI Power Management
7:0
Register.
23.2.1.17 PC—PCI Power Management Capabilities Register
(Intel® MEI 2—D22:F1)
Address Offset: 52h–53h Attribute: RO
Default Value: C803h Size: 16 bits
Bit Description
PME_Support (PSUP)—RO. This five-bit field indicates the power states in which the
15:11 function may assert PME#. Intel MEI can assert PME# from any D-state except D1 or
D2 which are not supported by Intel MEI.
10:9 Reserved
Aux_Current (AC)—RO. Reports the maximum Suspend well current required when in
8:6
the D3cold state. Value of 00b is reported.
Device Specific Initialization (DSI)—RO. Indicates whether device-specific
5
initialization is required.
4 Reserved
3 PME Clock (PMEC)—RO. Indicates that PCI clock is not required to generate PME#.
Version (VS)—RO. Hardwired to 011b to indicate support for Revision 1.2 of the PCI
2:0
Power Management Specification.
Datasheet 945
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.2.1.18 PMCS—PCI Power Management Control and Status
Register (Intel® MEI 2—D22:F1)
Address Offset: 54h–55h Attribute: R/WC, R/W, RO
Default Value: 0008h Size: 16 bits
Bit Description
PME Status (PMES)—R/WC. Bit is set by Intel ME Firmware. Host software clears bit
15 by writing 1 to bit.
This bit is reset when CL_RST# is asserted.
14:9 Reserved
PME Enable (PMEE)—R/W. This bit is read/write and is under the control of host SW.
It does not directly have an effect on PME events. However, this bit is shadowed so Intel
8 ME FW can monitor it. Intel ME FW will not cause the PMES bit to transition to 1 while
the PMEE bit is 0, indicating that host SW had disabled PME.
This bit is reset when PLTRST# asserted.
7:4 Reserved
No_Soft_Reset (NSR)—RO. This bit indicates that when the Intel MEI host controller
3 is transitioning from D3hot to D0 due to a power state command, it does not perform an
internal reset. Configuration context is preserved.
2 Reserved
Power State (PS)—R/W. This field is used both to determine the current power state
of the Intel MEI host controller and to set a new power state. The values are:
00 = D0 state (default)
1:0 11 = D3hot state
The D1 and D2 states are not supported for the Intel MEI host controller. When in the
D3hot state, the Intel ME’s configuration space is available, but the register memory
spaces are not. Additionally, interrupts are blocked.
23.2.1.19 GMES2—General Intel® ME Status Register 2
(Intel® MEI 2—D22:F1)
Address Offset: 60h–63h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:0 General Intel ME Status 2 (ME_GS 2)—RO. This field is populated by Intel ME.
23.2.1.20 GMES3—General Intel® ME Status Register 3
(Intel® MEI 2—D22:F1)
Address Offset: 64h–67h Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:0 General Intel ME Status 3 (ME_GS 3)—RO. This field is populated by Intel ME.
946 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.2.1.21 GMES4—General Intel® ME Status Register 4
(Intel® MEI 2—D22:F1)
Address Offset: 68h–6Bh Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:0 General Intel ME Status 4 (ME_GS 4)—RO. This field is populated by Intel ME.
23.2.1.22 GMES5—General Intel® ME Status Register 5
(Intel® MEI 2—D22:F1)
Address Offset: 6Ch–6Fh Attribute: RO
Default Value: 00000000h Size: 32 bits
Bit Description
31:0 General Intel ME Status 5 (ME_GS 5)—RO. This field is populated by Intel ME.
23.2.1.23 H_GS2—Host General Status Register 2
(Intel® MEI 2—D22:F1)
Address Offset: 70h–73h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Host General Status 2 (H_GS 2)—R/W. General Status of Host, this field is not used
31:0
by Hardware
23.2.1.24 H_GS3—Host General Status Register 3
(Intel® MEI 2—D22:F1)
Address Offset: 74h–77h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Host General Status 3 (H_GS3)—R/W. General Status of Host, this field is not used
31:0
by Hardware
23.2.1.25 MID—Message Signaled Interrupt Identifiers Register
(Intel® MEI 2—D22:F1)
Address Offset: 8Ch-8Dh Attribute: RO
Default Value: 0005h Size: 16 bits
Bit Description
15:8 Next Pointer (NEXT)—RO. Value of 00h indicates that this is the last item in the list.
7:0 Capability ID (CID)—RO. Capabilities ID indicates MSI.
Datasheet 947
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.2.1.26 MC—Message Signaled Interrupt Message Control Register
(Intel® MEI 2—D22:F1)
Address Offset: 8Eh–8Fh Attribute: R/W, RO
Default Value: 0080h Size: 16 bits
Bit Description
15:8 Reserved
64 Bit Address Capable (C64)—RO. Specifies that function is capable of generating
7
64-bit messages.
6:1 Reserved
MSI Enable (MSIE)—R/W. If set, MSI is enabled and traditional interrupt pins are not
0
used to generate interrupts.
23.2.1.27 MA—Message Signaled Interrupt Message Address Register
(Intel® MEI 2—D22:F1)
Address Offset: 90h–93h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
Address (ADDR)—R/W. Lower 32 bits of the system specified message address,
31:2
always DW aligned.
1:0 Reserved
23.2.1.28 MUA—Message Signaled Interrupt Upper Address Register
(Intel® MEI 2—D22:F1)
Address Offset: 94h–97h Attribute: R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Upper Address (UADDR)—R/W. Upper 32 bits of the system specified message
31:0
address, always DW aligned.
948 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.2.1.29 MD—Message Signaled Interrupt Message Data Register
(Intel® MEI 2—D22:F1)
Address Offset: 98h–99h Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
Data (DATA)—R/W. This 16-bit field is programmed by system software if MSI is
15:0 enabled. Its content is driven during the data phase of the MSI memory write
transaction.
23.2.1.30 HIDM—Intel® MEI Interrupt Delivery Mode Register
(Intel® MEI 2—D22:F1)
Address Offset: A0h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:2 Reserved
Intel MEI Interrupt Delivery Mode (HIDM)—R/W. These bits control what type of
interrupt the Intel MEI will send the host. They are interpreted as follows:
1:0 00 = Generate Legacy or MSI interrupt
01 = Generate SCI
10 = Generate SMI
23.2.1.31 HERES—Intel® MEI Extend Register Status
(Intel® MEI 2—D22:F1)
Address Offset: BCh–BFh Attribute: RO
Default Value: 40000000h Size: 32 bits
Bit Description
Extend Register Valid (ERV)—RO. Set by firmware after all firmware has been
31 loaded. If ERA field is SHA-1, the result of the extend operation is in HER:5-1. If ERA
field is SHA-256, the result of the extend operation is in HER:8-1.
Extend Feature Present (EFP)—RO. This bit is hardwired to 1 to allow driver
30 software to easily detect the chipset supports the Extend Register FW measurement
feature.
29:4 Reserved
Extend Register Algorithm (ERA)—RO. This field indicates the hash algorithm used
in the FW measurement extend operations. Encodings are:
3:0 0h = SHA-1
2h = SHA-256
Other values = Reserved
Datasheet 949
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.2.1.32 HERX—Intel® MEI Extend Register DWX
(Intel® MEI 2—D22:F1)
Address Offset: HER1: C0h–C3h Attribute: RO
HER2: C4h–C7h
HER3: C8h–CBh
HER4: CCh–CFh
HER5: D0h–D3h
HER6: D4h–D7h
HER7: D8h–dBh
HER8: DCh–DFh
Default Value: 00000000h Size: 32 bits
Bit Description
Extend Register DWX (ERDWX)—RO.
Xth DWord result of the extend operation.
31:0
NOTE: Extend Operation is HER[5:1] if using SHA-1. If using SHA-256, then Extend
Operation is HER[8:1].
23.2.2 MEI1_MBAR—Intel® MEI 2 MMIO Registers
These MMIO registers are accessible starting at the Intel MEI 2 MMIO Base Address
(MEI1_MBAR) which gets programmed into D22:F1:Offset 10–17h. These registers are
reset by PLTRST# unless otherwise noted.
Table 23-4. Intel® MEI 2 MMIO Register Address Map
MEI1_MBAR
Mnemonic Register Name Default Attribute
+ Offset
00–03h H_CB_WW Host Circular Buffer Write Window 00000000h W
R/W,
04h–07h H_CSR Host Control Status 02000000h
R/WC, RO
08h–0Bh ME_CB_RW Intel ME Circular Buffer Read Window FFFFFFFFh RO
0Ch–0Fh ME_CSR_HA Intel ME Control Status Host Access 02000000h RO
23.2.2.1 H_CB_WW—Host Circular Buffer Write Window
(Intel® MEI 2 MMIO Register)
Address Offset: MEI1_MBAR + 00h Attribute: W
Default Value: 00000000h Size: 32 bits
Bit Description
Host Circular Buffer Write Window Field (H_CB_WWF)—W. This bit field is for
host to write into its circular buffer. The host's circular buffer is located at the Intel ME
subsystem address specified in the Host CB Base Address register. This field is write
31:0
only; reads will return arbitrary data. Writes to this register will increment the H_CBWP
as long as ME_RDY is 1. When ME_RDY is 0, writes to this register have no effect and
are not delivered to the H_CB, nor is H_CBWP incremented.
950 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.2.2.2 H_CSR—Host Control Status Register
(Intel® MEI 2 MMIO Register)
Address Offset: MEI1_MBAR + 04h Attribute: RO, R/W, R/WC
Default Value: 02000000h Size: 32 bits
Bit Description
Host Circular Buffer Depth (H_CBD)—RO. This field indicates the maximum number
of 32 bit entries available in the host circular buffer (H_CB). Host software uses this
field along with the H_CBRP and H_CBWP fields to calculate the number of valid entries
in the H_CB to read or # of entries available for write.
31:24
This field is implemented with a "1-hot" scheme. Only one bit will be set to a "1" at a
time. Each bit position represents the value n of a buffer depth of (2^n). For example,
when bit# 1 is 1, the buffer depth is 2; when bit#2 is 1, the buffer depth is 4, and so
on. The allowed buffer depth values are 2, 4, 8, 16, 32, 64 and 128.
23:16 Host CB Write Pointer (H_CBWP)—RO. Points to next location in the H_CB for host
to write the data. Software uses this field along with H_CBRP and H_CBD fields to
calculate the number of valid entries in the H_CB to read or number of entries available
for write.
15:8 Host CB Read Pointer (H_CBRP)—RO. Points to next location in the H_CB where a
valid data is available for embedded controller to read. Software uses this field along
with H_CBWR and H_CBD fields to calculate the number of valid entries in the host CB
to read or number of entries available for write.
7:5 Reserved
NOTE: For writes to this register, these bits shall be written as 000b.
4 Host Reset (H_RST)—R/W. Setting this bit to 1 will initiate a Intel MEI reset sequence
to get the circular buffers into a known good state for host and Intel ME
communication. When this bit transitions from 0 to 1, hardware will clear the H_RDY
and ME_RDY bits.
3 Host Ready (H_RDY)—R/W. This bit indicates that the host is ready to process
messages.
2 Host Interrupt Generate (H_IG)—R/W. Once message(s) are written into its CB, the
host sets this bit to one for the HW to set the ME_IS bit in the ME_CSR and to generate
an interrupt message to Intel ME. HW will send the interrupt message to Intel ME only
if the ME_IE is enabled. HW then clears this bit to 0.
1 Host Interrupt Status (H_IS)—R/WC. Hardware sets this bit to 1 when ME_IG bit is
set to 1. Host clears this bit to 0 by writing a 1 to this bit position. H_IE has no effect on
this bit.
0 Host Interrupt Enable (H_IE)—R/W. Host sets this bit to 1 to enable the host
interrupt (INTR# or MSI) to be asserted when H_IS is set to 1.
Datasheet 951
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.2.2.3 ME_CB_RW—Intel® ME Circular Buffer Read Window Register
(Intel® MEI 2 MMIO Register)
Address Offset: MEI1_MBAR + 08h Attribute: RO
Default Value: FFFFFFFFh Size: 32 bits
Bit Description
Intel ME Circular Buffer Read Window Field (ME_CB_RWF). This bit field is for
host to read from the Intel ME Circular Buffer. The Intel ME's circular buffer is located at
the Intel ME subsystem address specified in the Intel ME CB Base Address register. This
31:0
field is read only, writes have no effect. Reads to this register will increment the
ME_CBRP as long as ME_RDY is 1. When ME_RDY is 0, reads to this register have no
effect, all 1s are returned, and ME_CBRP is not incremented.
23.2.2.4 ME_CSR_HA—Intel® ME Control Status Host Access Register
(Intel® MEI 2 MMIO Register)
Address Offset: MEI1_MBAR + 0Ch Attribute: RO
Default Value: 02000000h Size: 32 bits
Bit Description
Intel ME Circular Buffer Depth Host Read Access (ME_CBD_HRA).
31:24
Host read only access to ME_CBD.
Intel ME CB Write Pointer Host Read Access (ME_CBWP_HRA).
23:16
Host read only access to ME_CBWP.
Intel ME CB Read Pointer Host Read Access (ME_CBRP_HRA).
15:8
Host read only access to ME_CBRP.
7:5 Reserved
Intel ME Reset Host Read Access (ME_RST_HRA).
4
Host read access to ME_RST.
Intel ME Ready Host Read Access (ME_RDY_HRA).
3
Host read access to ME_RDY.
Intel ME Interrupt Generate Host Read Access (ME_IG_HRA).
2
Host read only access to ME_IG.
Intel ME Interrupt Status Host Read Access (ME_IS_HRA).
1
Host read only access to ME_IS.
Intel ME Interrupt Enable Host Read Access (ME_IE_HRA).
0
Host read only access to ME_IE.
952 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3 IDE Redirect IDER Registers (IDER—D22:F2)
23.3.1 PCI Configuration Registers (IDER—D22:F2)
Table 23-5. IDE Redirect Function IDER Register Address Map
Address Register Default
Register Name Attribute
Offset Symbol Value
00h–01h VID Vendor Identification 8086h RO
See register
02h–03h DID Device Identification RO
description
04h–05h PCICMD PCI Command 0000h RO, R/W
06h–07h PCISTS PCI Status 00B0h RO
See register
08h RID Revision ID RO
description
09h–0Bh CC Class Codes 010185h RO
0Ch CLS Cache Line Size 00h RO
10h–13h PCMdBA Primary Command Block IO Bar 00000001h RO, R/W
14h–17h PCTLBA Primary Control Block Base Address 00000001h RO, R/W
18h–1Bh SCMdBA Secondary Command Block Base Address 00000001h RO, R/W
1Ch–1Fh SCTLBA Secondary Control Block base Address 00000001h RO, R/W
20h–23h LBAR Legacy Bus Master Base Address 00000001h RO, R/W
2Ch–2Dh SVID Subsystem Vendor ID 0000h R/WO
2Eh–2Fh SID Subsystem ID 8086h R/WO
34h CAPP Capabilities Pointer C8h RO
3Ch–3Dh INTR Interrupt Information 0300h R/W, RO
C8h–C9h PID PCI Power Management Capability ID D001h RO
CAh–CBh PC PCI Power Management Capabilities 0023h RO
PCI Power Management Control and RO, R/W,
CCh–CFh PMCS 00000000h
Status RO/V
D0h–D1h MID Message Signaled Interrupt Capability ID 0005h RO
Message Signaled Interrupt Message
D2h–D3h MC 0080h RO, R/W
Control
Message Signaled Interrupt Message
D4h–D7h MA 00000000h R/W, RO
Address
Message Signaled Interrupt Message
D8h–dBh MAU 00000000h RO, R/W
Upper Address
DC–DDh MD Message Signaled Interrupt Message Data 0000h R/W
Datasheet 953
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.1.1 VID—Vendor Identification Register (IDER—D22:F2)
Address Offset: 00–01h Attribute: RO
Default Value: 8086h Size: 16 bits
Bit Description
15:0 Vendor ID (VID)—RO. This is a 16-bit value assigned by Intel.
23.3.1.2 DID—Device Identification Register (IDER—D22:F2)
Address Offset: 02–03h Attribute: RO
Default Value: See bit description Size: 16 bits
Bit Description
Device ID (DID)—RO. This is a 16-bit value assigned to the PCH IDER controller.
15:0
See Section 1.3 for the value of the DID Register.
23.3.1.3 PCICMD—PCI Command Register (IDER—D22:F2)
Address Offset: 04–05h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved
Interrupt Disable (ID)—R/W. This disables pin-based INTx# interrupts. This bit
has no effect on MSI operation. When set, internal INTx# messages will not be
10
generated. When cleared, internal INTx# messages are generated if there is an
interrupt and MSI is not enabled.
9:3 Reserved
Bus Master Enable (BME)—RO. This bit controls the PT function's ability to act as a
2 master for data transfers. This bit does not impact the generation of completions for
split transaction commands.
Memory Space Enable (MSE)—RO. PT function does not contain target memory
1
space.
I/O Space enable (IOSE)—RO. This bit controls access to the PT function's target
0
I/O space.
954 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.1.4 PCISTS—PCI Device Status Register (IDER—D22:F2)
Address Offset: 06–07h Attribute: RO
Default Value: 00B0h Size: 16 bits
Bit Description
15:11 Reserved
DEVSEL# Timing Status (DEVT)—RO. This bit controls the device select time for
10:9
the PT function's PCI interface.
8:5 Reserved
Capabilities List (CL)—RO. This bit indicates that there is a capabilities pointer
4
implemented in the device.
Interrupt Status (IS)—RO. This bit reflects the state of the interrupt in the
3 function. Setting of the Interrupt Disable bit to 1 has no affect on this bit. Only when
this bit is a 1 and ID bit is 0 is the INTc interrupt asserted to the Host.
2:0 Reserved
23.3.1.5 RID—Revision Identification Register (IDER—D22:F2)
Address Offset: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
Bit Description
Revision ID—RO. This field indicates the device specific revision identifier. See
7:0
Section 1.3 for the value of the RID Register.
23.3.1.6 CC—Class Codes Register (IDER—D22:F2)
Address Offset: 09–0Bh Attribute: RO
Default Value: 010185h Size: 24 bits
Bit Description
Base Class Code (BCC)—RO This field indicates the base class code of the IDER
23:16
host controller device.
Sub Class Code (SCC)—RO This field indicates the sub class code of the IDER host
15:8
controller device.
Programming Interface (PI)—RO This field indicates the programming interface of
7:0
the IDER host controller device.
23.3.1.7 CLS—Cache Line Size Register (IDER—D22:F2)
Address Offset: 0Ch Attribute: RO
Default Value: 00h Size: 8 bits
Bit Description
7:0 Cache Line Size (CLS)—RO. All writes to system memory are Memory Writes.
Datasheet 955
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.1.8 PCMdBA—Primary Command Block IO Bar
Register (IDER—D22:F2)
Address Offset: 10–13h Attribute: RO, R/W
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
Base Address (BAR)—R/W Base Address of the BAR0 I/O space (8 consecutive I/O
15:3
locations).
2:1 Reserved
0 Resource Type Indicator (RTE)—RO. This bit indicates a request for I/O space.
23.3.1.9 PCTLBA—Primary Control Block Base Address
Register (IDER—D22:F2)
Address Offset: 14–17h Attribute: RO, R/W
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
Base Address (BAR)—R/W. Base Address of the BAR1 I/O space (4 consecutive I/O
15:2
locations)
1 Reserved
0 Resource Type Indicator (RTE)—RO. This bit indicates a request for I/O space
23.3.1.10 SCMdBA—Secondary Command Block Base Address
Register (IDER—D22:F2)
Address Offset: 18–1Bh Attribute: RO, R/W
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
Base Address (BAR)—R/W. Base Address of the I/O space (8 consecutive I/O
15:3
locations).
2:1 Reserved
0 Resource Type Indicator (RTE)—RO. This bit indicates a request for I/O space.
956 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.1.11 SCTLBA—Secondary Control Block base Address
Register (IDER—D22:F2)
Address Offset: 1C–1Fh Attribute: RO, R/W
Default Value: 00000001h1 Size: 32 bits
Bit Description
31:16 Reserved
Base Address (BAR)—R/W. Base Address of the I/O space (4 consecutive I/O
15:2
locations).
1 Reserved
0 Resource Type Indicator (RTE)—RO. This bit indicates a request for I/O space.
23.3.1.12 LBAR—Legacy Bus Master Base Address Register
(IDER—D22:F2)
Address Offset: 20–23h Attribute: RO, R/W
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
Base Address (BA)—R/W. Base Address of the I/O space (16 consecutive I/O
15:4
locations).
3:1 Reserved
0 Resource Type Indicator (RTE)—RO. This bit indicates a request for I/O space.
23.3.1.13 SVID—Subsystem Vendor ID Register (IDER—D22:F2)
Address Offset: 2Ch–2Dh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Bit Description
Subsystem Vendor ID (SSVID)—R/WO. Indicates the sub-system vendor identifier.
This field should be programmed by BIOS during boot-up. Once written, this register
15:0
becomes Read Only. This field can only be cleared by PLTRST#.
NOTE: Register must be written as a DWord write with SID register.
23.3.1.14 SID—Subsystem ID Register (IDER—D22:F2)
Address Offset: 2Eh–2Fh Attribute: R/WO
Default Value: 8086h Size: 16 bits
Bit Description
Subsystem ID (SSID)—R/WO. Indicates the sub-system identifier. This field should
be programmed by BIOS during boot-up. Once written, this register becomes Read
15:0
Only. This field can only be cleared by PLTRST#.
NOTE: Register must be written as a DWord write with SVID register.
Datasheet 957
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.1.15 CAPP—Capabilities List Pointer Register
(IDER—D22:F2)
Address Offset: 34h Attribute: RO
Default Value: C8h Size: 8 bits
Bit Description
Capability Pointer (CP)—R/WO. This field indicates that the first capability pointer
7:0
is offset C8h (the power management capability).
23.3.1.16 INTR—Interrupt Information Register
(IDER—D22:F2)
Address Offset: 3C–3Dh Attribute: R/W, RO
Default Value: 0300h Size: 16 bits
Bit Description
Interrupt Pin (IPIN)—RO. A value of 1h/2h/3h/4h indicates that this function
implements legacy interrupt on INTA/INTB/INTC/INTD, respectively
15:8
Function Value INTx
(2 IDE) 03h INTC
Interrupt Line (ILINE)—R/W. The value written in this register indicates which
input of the system interrupt controller, the device's interrupt pin is connected to.
7:0
This value is used by the OS and the device driver, and has no affect on the
hardware.
23.3.1.17 PID—PCI Power Management Capability ID Register
(IDER—D22:F2)
Address Offset: C8–C9h Attribute: RO
Default Value: D001h Size: 16 bits
Bit Description
15:8 Next Capability (NEXT)—RO. Its value of D0h points to the MSI capability.
7:0 Cap ID (CID)—RO. This field indicates that this pointer is a PCI power management.
958 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.1.18 PC—PCI Power Management Capabilities Register
(IDER—D22:F2)
Address Offset: CA–CBh Attribute: RO
Default Value: 0023h Size: 16 bits
Bit Description
PME_Support (PSUP)—RO. This five-bit field indicates the power states in which
15:11 the function may assert PME#. IDER can assert PME# from any D-state except D1 or
D2 which are not supported by IDER.
10:9 Reserved
Aux_Current (AC)—RO. Reports the maximum Suspend well current required when
8:6
in the D3cold state. Value of 000b is reported.
Device Specific Initialization (DSI)—RO. Indicates whether device-specific
5
initialization is required.
4 Reserved
3 PME Clock (PMEC)—RO. Indicates that PCI clock is not required to generate PME#.
Version (VS)—RO. Hardwired to 011b to indicate support for Revision 1.2 of the PCI
2:0
Power Management Specification.
23.3.1.19 PMCS—PCI Power Management Control and Status
Register (IDER—D22:F2)
Address Offset: CC–CFh Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:4 Reserved
No Soft Reset (NSR)—RO.
0 = Devices do perform an internal reset upon transitioning from D3hot to D0 using
software control of the PowerState bits. Configuration Context is lost when
performing the soft reset. Upon transition from the D3hot to the D0 state, full re-
3 initialization sequence is needed to return the device to D0 Initialized.
1 = Devices do not perform an internal reset upon transitioning from D3hot to D0.
Configuration Context is preserved. Upon transition from the D3hot to the D0
Initialized state, no additional operating system intervention is required to
preserve Configuration Context beyond writing the PowerState bits.
2 Reserved
Power State (PS)—R/W. This field is used both to determine the current power
state of the PT function and to set a new power state. The values are:
00 = D0 state
1:0 11 = D3HOT state
When in the D3HOT state, the controller's configuration space is available, but the I/O
and memory spaces are not. Additionally, interrupts are blocked. If software attempts
to write a '10' or '01' to these bits, the write will be ignored.
Datasheet 959
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.1.20 MID—Message Signaled Interrupt Capability ID
Register (IDER—D22:F2)
Address Offset: D0–D1h Attribute: RO
Default Value: 0005h Size: 16 bits
Bit Description
Next Pointer (NEXT)—RO. This value indicates this is the last item in the
15:8
capabilities list.
Capability ID (CID)—RO. The Capabilities ID value indicates device is capable of
7:0
generating an MSI.
23.3.1.21 MC—Message Signaled Interrupt Message Control
Register (IDER—D22:F2)
Address Offset: D2–D3h Attribute: RO, R/W
Default Value: 0080h Size: 16 bits
Bit Description
15:8 Reserved
64 Bit Address Capable (C64)—RO. Capable of generating 64-bit and 32-bit
7
messages.
Multiple Message Enable (MME)—R/W. These bits are R/W for software
6:4
compatibility, but only one message is ever sent by the PT function.
3:1 Multiple Message Capable (MMC)—RO. Only one message is required.
MSI Enable (MSIE)—R/W. If set, MSI is enabled and traditional interrupt pins are
0
not used to generate interrupts.
23.3.1.22 MA—Message Signaled Interrupt Message Address
Register (IDER—D22:F2)
Address Offset: D4–D7h Attribute: R/W, RO
Default Value: 00000000h Size: 32 bits
Bit Description
Address (ADDR)—R/W. This field contains the Lower 32 bits of the system specified
31:2
message address, always DWord aligned
1:0 Reserved
23.3.1.23 MAU—Message Signaled Interrupt Message Upper
Address Register (IDER—D22:F2)
Address Offset: D8–dBh Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:4 Reserved
Address (ADDR)—R/W. This field contains the Upper 4 bits of the system specified
3:0
message address.
960 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.1.24 MD—Message Signaled Interrupt Message Data
Register (IDER—D22:F2)
Address Offset: DC–DDh Attribute: R/W
Default Value: 0000h Size: 16 bits
Bit Description
Data (DATA)—R/W. This content is driven onto the lower word of the data bus of the
15:0
MSI memory write transaction.
23.3.2 IDER BAR0 Registers
Table 23-6. IDER BAR0 Register Address Map (Sheet 1 of 2)
Address Register Default
Register Name Attribute
Offset Symbol Value
0h IDEDATA IDE Data Register 00h R/W
1h IDEERD1 IDE Error Register DEV1 00h R/W
1h IDEERD0 IDE Error Register DEV0 00h R/W
1h IDEFR IDE Features Register 00h R/W
2h IDESCIR IDE Sector Count In Register 00h R/W
IDE Sector Count Out Register
2h IDESCOR1 00h R/W
Device 1
IDE Sector Count Out Register
2h IDESCOR0 00h R/W
Device 0
IDE Sector Number Out Register
3h IDESNOR0 00h R/W
Device 0
IDE Sector Number Out Register
3h IDESNOR1 00h R/W
Device 1
3h IDESNIR IDE Sector Number In Register 00h R/W
4h IDECLIR IDE Cylinder Low In Register 00h R/W
IDE Cylinder Low Out Register
4h IDCLOR1 00h R/W
Device 1
IDE Cylinder Low Out Register
4h IDCLOR0 00h R/W
Device 0
IDE Cylinder High Out Register
5h IDCHOR0 00h R/W
Device 0
IDE Cylinder High Out Register
5h IDCHOR1 00h R/W
Device 1
5h IDECHIR IDE Cylinder High In Register 00h R/W
6h IDEDHIR IDE Drive/Head In Register 00h R/W
IDE Drive Head Out Register Device
6h IDDHOR1 00h R/W
1
IDE Drive Head Out Register Device
6h IDDHOR0 00h R/W
0
Datasheet 961
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
Table 23-6. IDER BAR0 Register Address Map (Sheet 2 of 2)
Address Register Default
Register Name Attribute
Offset Symbol Value
7h IDESD0R IDE Status Device 0 Register 80h R/W
7h IDESD1R IDE Status Device 1 Register 80h R/W
7h IDECR IDE Command Register 00h R/W
23.3.2.1 IDEDATA—IDE Data Register (IDER—D22:F2)
Address Offset: 0h Attribute: R/W
Default Value: 00h Size: 8 bits
The IDE data interface is a special interface that is implemented in the HW. This data
interface is mapped to I/O space from the host and takes read and write cycles from
the host targeting master or slave device.
Writes from host to this register result in the data being written to Intel ME memory.
Reads from host to this register result in the data being fetched from Intel ME memory.
Data is typically written/ read in WORDs. Intel ME FW must enable hardware to allow it
to accept Host initiated Read/ Write cycles, else the cycles are dropped.
Bit Description
IDE Data Register (IDEDR)—R/W. Data Register implements the data interface for
7:0 IDE. All writes and reads to this register translate into one or more corresponding
write/reads to Intel ME memory.
23.3.2.2 IDEERD1—IDE Error Register DEV1
(IDER—D22:F2)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Error register of the command block of the IDE function.
The register is read only by the HOST interface when DEV = 1 (slave device).
Bit Description
IDE Error Data (IDEED)—R/W. Drive reflects its error/ diagnostic code to the host
7:0
using this register at different times.
962 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.2.3 IDEERD0—IDE Error Register DEV0
(IDER—D22:F2)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Error register of the command block of the IDE function.
The register is read only by the HOST interface when DEV = 0 (master device).
Bit Description
IDE Error Data (IDEED)—R/W. Drive reflects its error/ diagnostic code to the host
7:0
using this register at different times.
23.3.2.4 IDEFR—IDE Features Register
(IDER—D22:F2)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Feature register of the command block of the IDE
function. This register can be written only by the Host.
When the HOST reads the same address, it reads the Error register of Device 0 or
Device 1 depending on the device_select bit (bit 4 of the drive/head register).
Bit Description
7:0 IDE Feature Data (IDEFD)—R/W. IDE drive specific data written by the Host
23.3.2.5 IDESCIR—IDE Sector Count In Register
(IDER—D22:F2)
Address Offset: 02h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Sector Count register of the command block of the IDE
function. This register can be written only by the Host. When host writes to this
register, all 3 registers (IDESCIR, IDESCOR0, IDESCOR1) are updated with the written
value.
A host read to this register address reads the IDE Sector Count Out Register IDESCOR0
if DEV=0 or IDESCOR1 if DEV=1
Bit Description
IDE Sector Count Data (IDESCD)—R/W. Host writes the number of sectors to be
7:0
read or written.
Datasheet 963
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.2.6 IDESCOR1—IDE Sector Count Out Register Device 1
Register (IDER—D22:F2)
Address Offset: 02h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read by the HOST interface if DEV = 1. Intel ME Firmware writes to this
register at the end of a command of the selected device.
When the host writes to this address, the IDE Sector Count In Register (IDESCIR), this
register is updated.
Bit Description
IDE Sector Count Out Dev1 (ISCOD1)—R/W. Sector Count register for Slave
7:0
Device (that is, Device 1)
23.3.2.7 IDESCOR0—IDE Sector Count Out Register Device
0 Register (IDER—D22:F2)
Address Offset: 02h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read by the HOST interface if DEV = 0. Intel ME Firmware writes to this
register at the end of a command of the selected device.
When the host writes to this address, the IDE Sector Count In Register (IDESCIR), this
register is updated.
Bit Description
IDE Sector Count Out Dev0 (ISCOD0)—R/W. Sector Count register for Master
7:0
Device (that is, Device 0).
23.3.2.8 IDESNOR0—IDE Sector Number Out Register
Device 0 Register (IDER—D22:F2)
Address Offset: 03h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read by the Host if DEV = 0. Intel ME Firmware writes to this register at
the end of a command of the selected device.
When the host writes to the IDE Sector Number In Register (IDESNIR), this register is
updated with that value.
Bit Description
IDE Sector Number Out DEV 0 (IDESNO0)—R/W. Sector Number Out register for
7:0
Master device.
964 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.2.9 IDESNOR1—IDE Sector Number Out Register
Device 1 Register (IDER—D22:F2)
Address Offset: 03h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read by the Host if DEV = 1. Intel ME Firmware writes to this register at
the end of a command of the selected device.
When the host writes to the IDE Sector Number In Register (IDESNIR), this register is
updated with that value.
Bit Description
IDE Sector Number Out DEV 1 (IDESNO1)—R/W. Sector Number Out register for
7:0
Slave device.
23.3.2.10 IDESNIR—IDE Sector Number In Register (IDER—D22:F2)
Address Offset: 03h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Sector Number register of the command block of the IDE
function. The register can be written only by the Host. When host writes to this register,
all 3 registers (IDESNIR, IDESNOR0, IDESNOR1) are updated with the written value.
Host read to this register address reads the IDE Sector Number Out Register
IDESNOR0 if DEV=0 or IDESNOR1 if DEV=1.
Bit Description
IDE Sector Number Data (IDESND)—R/W. This register contains the number of
7:0
the first sector to be transferred.
23.3.2.11 IDECLIR—IDE Cylinder Low In Register (IDER—D22:F2)
Address Offset: 04h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Cylinder Low register of the command block of the IDE
function. The register can be written only by the Host. When host writes to this register,
all 3 registers (IDECLIR, IDECLOR0, IDECLOR1) are updated with the written value.
Host read to this register address reads the IDE Cylinder Low Out Register IDECLOR0 if
DEV=0 or IDECLOR1 if DEV=1.
Bit Description
IDE Cylinder Low Data (IDECLD)—R/W. Cylinder Low register of the command
7:0
block of the IDE function.
Datasheet 965
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.2.12 IDCLOR1—IDE Cylinder Low Out Register Device 1
Register (IDER—D22:F2)
Address Offset: 04h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read by the Host if DEV = 1. Intel ME Firmware writes to this register at
the end of a command of the selected device. When the host writes to the IDE Cylinder
Low In Register (IDECLIR), this register is updated with that value.
Bit Description
IDE Cylinder Low Out DEV 1. (IDECLO1)—R/W. Cylinder Low Out Register for
7:0
Slave Device.
23.3.2.13 IDCLOR0—IDE Cylinder Low Out Register Device 0
Register (IDER—D22:F2)
Address Offset: 04h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read by the Host if DEV = 0. Intel ME Firmware writes to this register at
the end of a command of the selected device. When the host writes to the IDE Cylinder
Low In Register (IDECLIR), this register is updated with that value.
Bit Description
IDE Cylinder Low Out DEV 0. (IDECLO0)—R/W. Cylinder Low Out Register for
7:0
Master Device.
23.3.2.14 IDCHOR0—IDE Cylinder High Out Register Device 0
Register (IDER—D22:F2)
Address Offset: 05h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read by the Host if DEVice = 0. Intel ME Firmware writes to this register
at the end of a command of the selected device. When the host writes to the IDE
Cylinder High In Register (IDECHIR), this register is updated with that value.
Bit Description
IDE Cylinder High Out DEV 0 (IDECHO0)—R/W. Cylinder High out register for
7:0
Master device.
966 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.2.15 IDCHOR1—IDE Cylinder High Out Register Device 1
Register (IDER—D22:F2)
Address Offset: 05h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read by the Host if Device = 1. Intel ME Firmware writes to this register
at the end of a command of the selected device. When the host writes to the IDE
Cylinder High In Register (IDECHIR), this register is updated with that value.
Bit Description
IDE Cylinder High Out DEV 1 (IDECHO1)—R/W. Cylinder High out register for
7:0
Slave device.
23.3.2.16 IDECHIR—IDE Cylinder High In Register
(IDER—D22:F2)
Address Offset: 05h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Cylinder High register of the command block of the IDE
function. The register can be written only by the Host. When host writes to this register,
all 3 registers (IDECHIR, IDECHOR0, IDECHOR1) are updated with the written value.
Host read to this register address reads the IDE Cylinder High Out Register IDECHOR0
if DEV=0 or IDECHOR1 if DEV=1.
Bit Description
IDE Cylinder High Data (IDECHD)—R/W. Cylinder High data register for IDE
7:0
command block.
23.3.2.17 IDEDHIR—IDE Drive/Head In Register
(IDER—D22:F2)
Address Offset: 06h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Drive/Head register of the command block of the IDE. The
register can be written only by the Host. When host writes to this register, all 3
registers (IDEDHIR, IDEDHOR0, IDEDHOR1) are updated with the written value.
Host read to this register address reads the IDE Drive/Head Out Register (IDEDHOR0)
if DEV=0 or IDEDHOR1 if DEV=1.
Bit 4 of this register is the DEV (master/slave) bit. This bit is cleared by hardware on
IDE software reset (S_RST toggles to '1') in addition to Host system reset and D3->D0
transition of the function.
Bit Description
IDE Drive/Head Data (IDEDHD)—R/W. Register defines the drive number, head
7:0
number and addressing mode.
Datasheet 967
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.2.18 IDDHOR1—IDE Drive Head Out Register Device 1
Register (IDER—D22:F2)
Address Offset: 06h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read only by the Host. Host read to this Drive/head In register address
reads the IDE Drive/Head Out Register (IDEDHOR0) if DEV=1
Bit 4 of this register is the DEV (master/slave) bit. This bit is cleared by hardware on
IDE software reset (S_RST toggles to '1') in addition to the Host system reset and D3
to D0 transition of the IDE function.
When the host writes to this address, it updates the value of the IDEDHIR register.
Bit Description
IDE Drive Head Out DEV 1 (IDEDHO1)—R/W. Drive/Head Out register of Slave
7:0
device.
23.3.2.19 IDDHOR0—IDE Drive Head Out Register Device 0
Register (IDER—D22:F2)
Address Offset: 06h Attribute: R/W
Default Value: 00h Size: 8 bits
This register is read only by the Host. Host read to this Drive/head In register address
reads the IDE Drive/Head Out Register (IDEDHOR0) if DEV=0.
Bit 4 of this register is the DEV (master/slave) bit. This bit is cleared by hardware on
IDE software reset (S_RST toggles to 1) in addition to the Host system reset and D3 to
D0 transition of the IDE function.
When the host writes to this address, it updates the value of the IDEDHIR register.
Bit Description
IDE Drive Head Out DEV 0 (IDEDHO0)—R/W. Drive/Head Out register of Master
7:0
device.
968 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.2.20 IDESD0R—IDE Status Device 0 Register
(IDER—D22:F2)
Address Offset: 07h Attribute: R/W
Default Value: 80h Size: 8 bits
This register implements the status register of the Master device (DEV = 0). The
register is read only by the Host. Host read of this register clears the Master device's
interrupt.
When the HOST writes to the same address it writes to the command register
The bits description is for ATA mode.
Bit Description
Busy (BSY)—R/W. This bit is set by HW when the IDECR is being written and
DEV=0, or when SRST bit is asserted by Host or host system reset or D3-to-D0
7 transition of the IDE function.
This bit is cleared by FW write of 0.
6 Drive Ready (DRDY)—R/W. When set, this bit indicates drive is ready for command.
5 Drive Fault (DF)—R/W. Indicates Error on the drive.
Drive Seek Complete (DSC)—R/W. Indicates Heads are positioned over the desired
4
cylinder.
Data Request (DRQ)—R/W. Set when, the drive wants to exchange data with the
3
Host using the data register.
Corrected Data (CORR)—R/W. When set, this bit indicates a correctable read error
2
has occurred.
Index (IDX)—R/W. This bit is set once per rotation of the medium when the index
1
mark passes under the read/write head.
Error (ERR)—R/W. When set, this bit indicates an error occurred in the process of
0 executing the previous command. The Error Register of the selected device contains
the error information.
Datasheet 969
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.2.21 IDESD1R—IDE Status Device 1 Register
(IDER—D22:F2)
Address Offset: 07h Attribute: R/W
Default Value: 80h Size: 8 bits
This register implements the status register of the slave device (DEV = 1). The register
is read only by the Host. Host read of this register clears the slave device's interrupt.
When the HOST writes to the same address it writes to the command register.
The bits description is for ATA mode.
Bit Description
Busy (BSY)—R/W. This bit is set by hardware when the IDECR is being written and
DEV=0, or when SRST bit is asserted by the Host or host system reset or D3-to-D0
7 transition of the IDE function.
This bit is cleared by FW write of 0.
6 Drive Ready (DRDY)—R/W. When set, indicates drive is ready for command.
5 Drive Fault (DF)—R/W. Indicates Error on the drive.
Drive Seek Complete (DSC)—R/W. Indicates Heads are positioned over the desired
4
cylinder.
Data Request (DRQ)—R/W. Set when the drive wants to exchange data with the
3
Host using the data register.
Corrected Data (CORR)—R/W. When set indicates a correctable read error has
2
occurred.
Index (IDX)—R/W. This bit is set once per rotation of the medium when the index
1
mark passes under the read/write head.
Error (ERR)—R/W. When set, this bit indicates an error occurred in the process of
0 executing the previous command. The Error Register of the selected device contains
the error information
23.3.2.22 IDECR—IDE Command Register (IDER—D22:F2)
Address Offset: 07h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the Command register of the command block of the IDE
function. The register can be written only by the Host.
When the HOST reads the same address it reads the Status register DEV0 if DEV=0 or
Status Register DEV1 if DEV=1 (Drive/Head register bit [4]).
Bit Description
IDE Command Data (IDECD)—R/W. Host sends the commands (read/ write, and
7:0
so on) to the drive using this register.
970 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.3 IDER BAR1 Registers
Table 23-7. IDER BAR1 Register Address Map
Address Register Default
Register Name Attribute
Offset Symbol Value
2h IDDCR IDE Device Control Register 00h RO, WO
2h IDASR IDE Alternate status Register 00h RO
23.3.3.1 IDDCR—IDE Device Control Register (IDER—D22:F2)
Address Offset: 2h Attribute: WO
Default Value: 00h Size: 8 bits
This register implements the Device Control register of the Control block of the IDE
function. The register is Write only by the Host.
When the HOST reads to the same address it reads the Alternate Status register.
Bit Description
7:3 Reserved
Software reset (S_RST)—WO. When this bit is set by the Host, it forces a reset to
2
the device.
Host interrupt Disable (nIEN)—WO. When set, this bit disables hardware from
1
sending interrupt to the Host.
0 Reserved
23.3.3.2 IDASR—IDE Alternate Status Register (IDER—D22:F2)
Address Offset: 2h Attribute: RO
Default Value: 00h Size: 8 bits
This register implements the Alternate Status register of the Control block of the IDE
function. The register is a mirror register to the status register in the command block.
Reading this register by the HOST does not clear the IDE interrupt of the DEV selected
device
Host read of this register when DEV=0 (Master), Host gets the mirrored data of
IDESD0R register.
Host read of this register when DEV=1 (Slave), host gets the mirrored data of IDESD1R
register.
Bit Description
IDE Alternate Status Register (IDEASR)—RO. This field mirrors the value of the
7:0
DEV0/ DEV1 status register, depending on the state of the DEV bit on Host reads.
Datasheet 971
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.4 IDER BAR4 Registers
Table 23-8. IDER BAR4 Register Address Map
Address Register Default
Register Name Attribute
Offset Symbol Value
IDE Primary Bus Master Command
0h IDEPBMCR 00h RO, R/W
Register
IDE Primary Bus Master Device
1h IDEPBMDS0R 00h R/W
Specific 0 Register
IDE Primary Bus Master Status
2h IDEPBMSR 80h RO, R/W
Register
IDE Primary Bus Master Device
3h IDEPBMDS1R 00h R/W
Specific 1 Register
IDE Primary Bus Master Descriptor
4h IDEPBMDTPR0 00h R/W
Table Pointer Register Byte 0
IDE Primary Bus Master Descriptor
5h IDEPBMDTPR1 00h R/W
Table Pointer Register Byte 1
IDE Primary Bus Master Descriptor
6h IDEPBMDTPR2 00h R/W
Table Pointer Register Byte 2
IDE Primary Bus Master Descriptor
7h IDEPBMDTPR3 00h R/W
Table Pointer Register Byte 3
IDE Secondary Bus Master Command
8h IDESBMCR 00h RO, R/W
Register
IDE Secondary Bus Master Device
9h IDESBMDS0R 00h R/W
Specific 0 Register
IDE Secondary Bus Master Status
Ah IDESBMSR 00h R/W, RO
Register
IDE Secondary Bus Master Device
Bh IDESBMDS1R 00h R/W
Specific 1 Register
IDE Secondary Bus Master Descriptor
Ch IDESBMDTPR0 00h R/W
Table Pointer Register Byte 0
IDE Secondary Bus Master Descriptor
Dh IDESBMDTPR1 00h R/W
Table Pointer Register Byte 1
IDE Secondary Bus Master Descriptor
Eh IDESBMDTPR2 00h R/W
Table Pointer Register Byte 2
IDE Secondary Bus Master Descriptor
Fh IDESBMDTPR3 00h R/W
Table Pointer Register Byte 3
972 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.4.1 IDEPBMCR—IDE Primary Bus Master Command
Register (IDER—D22:F2)
Address Offset: 00h Attribute: RO, R/W
Default Value: 00h Size: 8 bits
This register implements the bus master command register of the primary channel. The
register is programmed by the Host.
Bit Description
7:4 Reserved
Read Write Command (RWC)—R/W. This bit sets the direction of bus master
transfer.
3 0 = Reads are performed from system memory
1 = Writes are performed to System Memory.
This bit should not be changed when the bus master function is active.
2:1 Reserved
Start/Stop Bus Master (SSBM)—R/W. This bit gates the bus master operation of
IDE function when 0. Writing 1 enables the bus master operation. Bus master
operation can be halted by writing a 0 to this bit. Operation cannot be stopped and
0
resumed.
This bit is cleared after data transfer is complete as indicated by either the BMIA bit
or the INT bit of the Bus Master status register is set or both are set.
23.3.4.2 IDEPBMDS0R—IDE Primary Bus Master Device
Specific 0 Register (IDER—D22:F2)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:0 Device Specific Data0 (DSD0)—R/W. Device Specific
Datasheet 973
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.4.3 IDEPBMSR—IDE Primary Bus Master Status
Register (IDER—D22:F2)
Address Offset: 02h Attribute: RO, R/W
Default Value: 80h Size: 8 bits
Bit Description
Simplex Only (SO)—RO. Value indicates whether both Bus Master Channels can be
operated at the same time or not.
7
0 = Both can be operated independently
1 = Only one can be operated at a time.
Drive 1 DMA Capable (D1DC)—R/W. This bit is read/write by the host (not write 1
6
clear).
Drive 0 DMA Capable (D0DC)—R/W. This bit is read/write by the host (not write 1
5
clear).
4:3 Reserved
Interrupt (INT)—R/W. This bit is set by the hardware when it detects a positive
2 transition in the interrupt logic (refer to IDE host interrupt generation diagram).The
hardware will clear this bit when the Host SW writes 1 to it.
Error (ER)—R/W. Bit is typically set by FW. Hardware will clear this bit when the Host
1
SW writes 1 to it.
Bus Master IDE Active (BMIA)—RO. This bit is set by hardware when SSBM
register is set to 1 by the Host. When the bus master operation ends (for the whole
0
command) this bit is cleared by firmware. This bit is not cleared when the HOST
writes 1 to it.
23.3.4.4 IDEPBMDS1R—IDE Primary Bus Master Device
Specific 1 Register (IDER—D22:F2)
Address Offset: 03h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:0 Device Specific Data1 (DSD1)—R/W. Device Specific Data.
23.3.4.5 IDEPBMDTPR0—IDE Primary Bus Master Descriptor
Table Pointer Byte 0 Register (IDER—D22:F2)
Address Offset: 04h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Descriptor Table Pointer Byte 0 (DTPB0)—R/W. This register implements the
Byte 0 (1 of 4 bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
7:0
master operation of the primary channel. This register is read/write by the HOST
interface.
974 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.4.6 IDEPBMDTPR1—IDE Primary Bus Master Descriptor
Table Pointer Byte 1 Register (IDER—D22:F2)
Address Offset: 05h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Descriptor Table Pointer Byte 1 (DTPB1)—R/W. This register implements the
7:0 Byte 1 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the primary channel. This register is programmed by the Host.
23.3.4.7 IDEPBMDTPR2—IDE Primary Bus Master Descriptor
Table Pointer Byte 2 Register (IDER—D22:F2)
Address Offset: 06h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Descriptor Table Pointer Byte 2 (DTPB2)—R/W. This register implements the
7:0 Byte 2 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the primary channel. This register is programmed by the Host.
23.3.4.8 IDEPBMDTPR3—IDE Primary Bus Master Descriptor
Table Pointer Byte 3 Register (IDER—D22:F2)
Address Offset: 07h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Descriptor Table Pointer Byte 3 (DTPB3)—R/W. This register implements the
7:0 Byte 3 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the primary channel. This register is programmed by the Host.
Datasheet 975
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.4.9 IDESBMCR—IDE Secondary Bus Master Command
Register (IDER—D22:F2)
Address Offset: 08h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
7:4 Reserved
Read Write Command (RWC)—R/W. This bit sets the direction of bus master
transfer. When 0, Reads are performed from system memory; when 1, writes are
3
performed to System Memory. This bit should not be changed when the bus master
function is active.
2:1 Reserved
Start/Stop Bus Master (SSBM)—R/W. This bit gates the bus master operation of
IDE function when zero.
Writing 1 enables the bus master operation. Bus master operation can be halted by
0
writing a 0 to this bit. Operation cannot be stopped and resumed.
This bit is cleared after data transfer is complete as indicated by either the BMIA bit
or the INT bit of the Bus Master status register is set or both are set.
23.3.4.10 IDESBMDS0R—IDE Secondary Bus Master Device
Specific 0 Register (IDER—D22:F2)
Address Offset: 09h Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Device Specific Data0 (DSD0)—R/W. This register implements the bus master
7:0 Device Specific 1 register of the secondary channel. This register is programmed by
the Host.
976 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.4.11 IDESBMSR—IDE Secondary Bus Master Status
Register (IDER—D22:F2)
Address Offset: 0Ah Attribute: R/W, RO
Default Value: 80h Size: 8 bits
Bit Description
Simplex Only (SO)—R/W. This bit indicates whether both Bus Master Channels can
be operated at the same time or not.
7
0 = Both can be operated independently
1 = Only one can be operated at a time.
6 Drive 1 DMA Capable (D1DC)—R/W. This bit is read/write by the host.
5 Drive 0 DMA Capable (D0DC)—R/W. This bit is read/write by the host.
4:0 Reserved
23.3.4.12 IDESBMDS1R—IDE Secondary Bus Master Device
Specific 1 Register (IDER—D22:F2)
Address Offset: 0Bh Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Device Specific Data1 (DSD1)—R/W. This register implements the bus master
7:0 Device Specific 1 register of the secondary channel. This register is programmed by
the Host for device specific data if any.
23.3.4.13 IDESBMDTPR0—IDE Secondary Bus Master Descriptor
Table Pointer Byte 0 Register (IDER—D22:F2)
Address Offset: 0Ch Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Descriptor Table Pointer Byte 0 (DTPB0)—R/W. This register implements the
Byte 0 (1 of 4 bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
7:0
master operation of the secondary channel. This register is read/write by the HOST
interface.
Datasheet 977
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.3.4.14 IDESBMDTPR1—IDE Secondary Bus Master Descriptor
Table Pointer Byte 1 Register (IDER—D22:F2)
Address Offset: 0Dh Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Descriptor Table Pointer Byte 1 (DTPB1)—R/W. This register implements the
7:0 Byte 1 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the secondary channel. This register is programmed by the Host.
23.3.4.15 IDESBMDTPR2—IDE Secondary Bus Master Descriptor
Table Pointer Byte 2 Register (IDER—D22:F2)
Address Offset: 0Eh Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Descriptor Table Pointer Byte 2 (DTPB2)—R/W. This register implements the
7:0 Byte 2 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the secondary channel. This register is programmed by the Host.
23.3.4.16 IDESBMDTPR3—IDE Secondary Bus Master Descriptor
Table Pointer Byte 3 Register (IDER—D22:F2)
Address Offset: 0Fh Attribute: R/W
Default Value: 00h Size: 8 bits
Bit Description
Descriptor Table Pointer Byte 3 (DTPB3)—R/W. This register implements the
7:0 Byte 3 (of four bytes) of the descriptor table Pointer (four I/O byte addresses) for bus
master operation of the secondary channel. This register is programmed by the Host.
978 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.4 Serial Port for Remote Keyboard and Text (KT)
Redirection (KT—D22:F3)
23.4.1 PCI Configuration Registers (KT—D22:F3)
Table 23-9. Serial Port for Remote Keyboard and Text (KT) Redirection Register
Address Map
Address Register Default
Register Name Attribute
Offset Symbol Value
00h–01h VID Vendor Identification 8086h RO
See Register
02h–03h DID Device Identification RO
description
04h–05h CMD Command Register 0000h RO, R/W
06h–07h STS Device Status 00B0h RO
See Register
08h RID Revision ID RO
description
09h–0Bh CC Class Codes 070002h RO
0Ch CLS Cache Line Size 00h RO
10h–13h KTIBA KT IO Block Base Address 00000001h RO, R/W
14h–17h KTMBA KT Memory Block Base Address 00000000h RO, R/W
2Ch–2Dh SVID Subsystem Vendor ID 0000h R/WO
2Eh–2Fh SID Subsystem ID 8086h R/WO
34h CAP Capabilities Pointer C8h RO
3Ch–3Dh INTR Interrupt Information 0200h R/W, RO
C8h–C9h PID PCI Power Management Capability ID D001h RO
CAh–CBh PC PCI Power Management Capabilities 0023h RO
Message Signaled Interrupt Capability
D0h–D1h MID 0005h RO
ID
Message Signaled Interrupt Message
D2h–D3h MC 0080h RO, R/W
Control
Message Signaled Interrupt Message
D4h–D7h MA 00000000h RO, R/W
Address
Message Signaled Interrupt Message
D8h–dBh MAU 00000000h RO, R/W
Upper Address
Message Signaled Interrupt Message
DCh–DDh MD 0000h R/W
Data
Datasheet 979
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.4.1.1 VID—Vendor Identification Register (KT—D22:F3)
Address Offset: 00–01h Attribute: RO
Default Value: 8086h Size: 16 bits
Bit Description
15:0 Vendor ID (VID)—RO. This is a 16-bit value assigned by Intel.
23.4.1.2 DID—Device Identification Register (KT—D22:F3)
Address Offset: 02–03h Attribute: RO
Default Value: See bit description Size: 16 bits
Bit Description
Device ID (DID)—RO. This is a 16-bit value assigned to the PCH KT controller. See
15:0
Section 1.3 for the value of the DID Register.
23.4.1.3 CMD—Command Register (KT—D22:F3)
Address Offset: 04–05h Attribute: RO, R/W
Default Value: 0000h Size: 16 bits
Bit Description
15:11 Reserved
Interrupt Disable (ID)—R/W. This bit disables pin-based INTx# interrupts. This bit
has no effect on MSI operation.
10 1 = Internal INTx# messages will not be generated.
0 = Internal INTx# messages are generated if there is an interrupt and MSI is not
enabled.
9:3 Reserved
Bus Master Enable (BME)—R/W. This bit controls the KT function's ability to act as
a master for data transfers. This bit does not impact the generation of completions
2
for split transaction commands. For KT, the only bus mastering activity is MSI
generation.
Memory Space Enable (MSE)—R/W. This bit controls Access to the PT function's
1
target memory space.
I/O Space enable (IOSE)—R/W. This bit controls access to the PT function's target
0
I/O space.
980 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.4.1.4 STS—Device Status Register (KT—D22:F3)
Address Offset: 06–07h Attribute: RO
Default Value: 00B0h Size: 16 bits
Bit Description
15:11 Reserved
DEVSEL# Timing Status (DEVT)—RO. This field controls the device select time for
10:9
the PT function's PCI interface.
8:5 Reserved
Capabilities List (CL)—RO. This bit indicates that there is a capabilities pointer
4
implemented in the device.
Interrupt Status (IS)—RO. This bit reflects the state of the interrupt in the function.
3 Setting of the Interrupt Disable bit to 1 has no affect on this bit. Only when this bit is
a 1 and ID bit is 0 is the INTB interrupt asserted to the Host.
2:0 Reserved
23.4.1.5 RID—Revision ID Register (KT—D22:F3)
Address Offset: 08h Attribute: RO
Default Value: See bit description Size: 8 bits
Bit Description
Revision ID—RO. This field indicates the device specific revision identifier. See
7:0
Section 1.3 for the value of the RID Register.
23.4.1.6 CC—Class Codes Register (KT—D22:F3)
Address Offset: 09–0Bh Attribute: RO
Default Value: 070002h Size: 24 bits
Bit Description
Base Class Code (BCC)—RO This field indicates the base class code of the KT host
23:16
controller device.
Sub Class Code (SCC)—RO This field indicates the sub class code of the KT host
15:8
controller device.
Programming Interface (PI)—RO This field indicates the programming interface of
7:0
the KT host controller device.
Datasheet 981
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.4.1.7 CLS—Cache Line Size Register (KT—D22:F3)
Address Offset: 0Ch Attribute: RO
Default Value: 00h Size: 8 bits
This register defines the system cache line size in DWord increments. Mandatory for
master which use the Memory-Write and Invalidate command.
Bit Description
7:0 Cache Line Size (CLS)—RO. All writes to system memory are Memory Writes.
23.4.1.8 KTIBA—KT IO Block Base Address Register
(KT—D22:F3)
Address Offset: 10–13h Attribute: RO, R/W
Default Value: 00000001h Size: 32 bits
Bit Description
31:16 Reserved
Base Address (BAR)—R/W. This field provides the base address of the I/O space (8
15:3
consecutive I/O locations).
2:1 Reserved
0 Resource Type Indicator (RTE)—RO. This bit indicates a request for I/O space
23.4.1.9 KTMBA—KT Memory Block Base Address Register
(KT—D22:F3)
Address Offset: 14–17h Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
Bit Description
Base Address (BAR)—R/W. This field provides the base address for Memory
31:12
Mapped I,O BAR. Bits 31:12 correspond to address signals 31:12.
11:4 Reserved
3 Prefetchable (PF)—RO. This bit indicates that this range is not pre-fetchable.
Type (TP)—RO. This field indicates that this range can be mapped anywhere in 32-
2:1
bit address space.
Resource Type Indicator (RTE)—RO. This bit indicates a request for register
0
memory space.
982 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.4.1.10 SVID—Subsystem Vendor ID Register (KT—D22:F3)
Address Offset: 2Ch–2Dh Attribute: R/WO
Default Value: 0000h Size: 16 bits
Bit Description
Subsystem Vendor ID (SSVID)—R/WO. Indicates the sub-system vendor identifier.
This field should be programmed by BIOS during boot-up. Once written, this register
15:0 becomes Read Only. This field can only be cleared by PLTRST#.
NOTE: Register must be written as a DWord write with SID register.
23.4.1.11 SID—Subsystem ID Register (KT—D22:F3)
Address Offset: 2Eh–2Fh Attribute: R/WO
Default Value: 8086h Size: 16 bits
Bit Description
Subsystem ID (SSID)—R/WO. Indicates the sub-system identifier. This field should
be programmed by BIOS during boot-up. Once written, this register becomes Read
15:0 Only. This field can only be cleared by PLTRST#.
NOTE: Register must be written as a DWord write with SVID register.
23.4.1.12 CAP—Capabilities Pointer Register (KT—D22:F3)
Address Offset: 34h Attribute: RO
Default Value: C8h Size: 8 bits
This optional register is used to point to a linked list of new capabilities implemented by
the device.
Bit Description
Capability Pointer (CP)—RO. This field indicates that the first capability pointer is
7:0
offset C8h (the power management capability).
23.4.1.13 INTR—Interrupt Information Register (KT—D22:F3)
Address Offset: 3C–3Dh Attribute: R/W, RO
Default Value: 0200h Size: 16 bits
Bit Description
Interrupt Pin (IPIN)—RO. A value of 1h/2h/3h/4h indicates that this function
implements legacy interrupt on INTA/INTB/INTC/INTD, respectively
15:8
FunctionValueINTx
(3 KT/Serial Port)02hINTB
Interrupt Line (ILINE)—R/W. The value written in this register tells which input of
7:0 the system interrupt controller, the device's interrupt pin is connected to. This value
is used by the OS and the device driver, and has no affect on the hardware.
Datasheet 983
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.4.1.14 PID—PCI Power Management Capability ID Register
(KT—D22:F3)
Address Offset: C8–C9h Attribute: RO
Default Value: D001h Size: 16 bits
Bit Description
15:8 Next Capability (NEXT)—RO. A value of D0h points to the MSI capability.
7:0 Cap ID (CID)—RO. This field indicates that this pointer is a PCI power management.
23.4.1.15 PC—PCI Power Management Capabilities ID Register
(KT—D22:F3)
Address Offset: CA–CBh Attribute: RO
Default Value: 0023h Size: 16 bits
Bit Description
15:11 PME Support (PME)—RO.This field indicates no PME# in the PT function.
10:6 Reserved
Device Specific Initialization (DSI)—RO. This bit indicates that no device-specific
5
initialization is required.
4 Reserved
PME Clock (PMEC)—RO. This bit indicates that PCI clock is not required to generate
3
PME#
Version (VS)—RO. This field indicates support for the PCI Power Management
2:0
Specification, Revision 1.2.
984 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.4.1.16 MID—Message Signaled Interrupt Capability ID
Register (KT—D22:F3)
Address Offset: D0–D1h Attribute: RO
Default Value: 0005h Size: 16 bits
Message Signaled Interrupt is a feature that allows the device/function to generate an
interrupt to the host by performing a DWord memory write to a system specified
address with system specified data. This register is used to identify and configure an
MSI capable device.
Bit Description
15:8 Next Pointer (NEXT)—RO. This value indicates this is the last item in the list.
Capability ID (CID)—RO. This field value of Capabilities ID indicates device is
7:0
capable of generating MSI.
23.4.1.17 MC—Message Signaled Interrupt Message Control
Register (KT—D22:F3)
Address Offset: D2–D3h Attribute: RO, R/W
Default Value: 0080h Size: 16 bits
Bit Description
15:8 Reserved
64 Bit Address Capable (C64)—RO. Capable of generating 64-bit and 32-bit
7
messages.
Multiple Message Enable (MME)—R/W.These bits are R/W for software
6:4
compatibility, but only one message is ever sent by the PT function.
3:1 Multiple Message Capable (MMC)—RO. Only one message is required.
MSI Enable (MSIE)—R/W. If set, MSI is enabled and traditional interrupt pins are
0
not used to generate interrupts.
23.4.1.18 MA—Message Signaled Interrupt Message Address
Register (KT—D22:F3)
Address Offset: D4–D7h Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
This register specifies the DWord aligned address programmed by system software for
sending MSI.
Bit Description
Address (ADDR)—R/W. Lower 32 bits of the system specified message address,
31:2
always DWord aligned.
1:0 Reserved
Datasheet 985
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.4.1.19 MAU—Message Signaled Interrupt Message Upper
Address Register (KT—D22:F3)
Address Offset: D8–dBh Attribute: RO, R/W
Default Value: 00000000h Size: 32 bits
Bit Description
31:4 Reserved
3:0 Address (ADDR)—R/W. Upper 4 bits of the system specified message address.
23.4.1.20 MD—Message Signaled Interrupt Message Data
Register (KT—D22:F3)
Address Offset: DC–DDh Attribute: R/W
Default Value: 0000h Size: 16 bits
This 16-bit field is programmed by system software if MSI is enabled
Bit Description
Data (DATA)—R/W. This MSI data is driven onto the lower word of the data bus of
15:0
the MSI memory write transaction.
23.4.2 KT IO/Memory Mapped Device Registers
Table 23-10. KT IO/Memory Mapped Device Register Address Map
Address Register Default
Register Name Attribute
Offset Symbol Value
0h KTRxBR KT Receive Buffer Register 00h RO
0h KTTHR KT Transmit Holding Register 00h WO
0h KTDLLR KT Divisor Latch LSB Register 00h R/W
1h KTIER KT Interrupt Enable register 00h R/W, RO
1h KTDLMR KT Divisor Latch MSB Register 00h R/W
2h KTIIR KT Interrupt Identification register 00h RO
2h KTFCR KT FIFO Control register 00h WO
3h KTLCR KT Line Control register 03h R/W
4h KTMCR KT Modem Control register 00h RO, R/W
5h KTLSR KT Line Status register 00h RO
6h KTMSR KT Modem Status register 00h RO
986 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.4.2.1 KTRxBR—KT Receive Buffer Register (KT—D22:F3)
Address Offset: 00h Attribute: RO
Default Value: 00h Size: 8 bits
This implements the KT Receiver Data register. Host access to this address, depends on
the state of the DLAB bit (KTLCR[7]). It must be 0 to access the KTRxBR.
RxBR:
Host reads this register when FW provides it the receive data in non-FIFO mode. In
FIFO mode, host reads to this register translate into a read from Intel ME memory (RBR
FIFO).
Bit Description
Receiver Buffer Register (RBR)—RO. Implements the Data register of the Serial
7:0
Interface. If the Host does a read, it reads from the Receive Data Buffer.
23.4.2.2 KTTHR—KT Transmit Holding Register (KT—D22:F3)
Address Offset: 00h Attribute: RO
Default Value: 00h Size: 8 bits
This implements the KT Transmit Data register. Host access to this address, depends on
the state of the DLAB bit (KTLCR[7]). It must be 0 to access the KTTHR.
THR:
When host wants to transmit data in the non-FIFO mode, it writes to this register. In
FIFO mode, writes by host to this address cause the data byte to be written by
hardware to Intel ME memory (THR FIFO).
Bit Description
Transmit Holding Register (THR)—WO. Implements the Transmit Data register of
7:0 the Serial Interface. If the Host does a write, it writes to the Transmit Holding
Register.
23.4.2.3 KTDLLR—KT Divisor Latch LSB Register (KT—D22:F3)
Address Offset: 00h Attribute: R/W
Default Value: 00h Size: 8 bits
This register implements the KT DLL register. Host can Read/Write to this register only
when the DLAB bit (KTLCR[7]) is 1. When this bit is 0, Host accesses the KTTHR or the
KTRBR depending on Read or Write.
This is the standard Serial Port Divisor Latch register. This register is only for software
compatibility and does not affect performance of the hardware.
Bit Description
7:0 Divisor Latch LSB (DLL)—R/W. Implements the DLL register of the Serial Interface.
Datasheet 987
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.4.2.4 KTIER—KT Interrupt Enable Register (KT—D22:F3)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
This implements the KT Interrupt Enable register. Host access to this address, depends
on the state of the DLAB bit (KTLCR[7]). It must be "0" to access this register. The bits
enable specific events to interrupt the Host.
Bit Description
7:4 Reserved
MSR (IER2)—R/W. When set, this bit enables bits in the Modem Status register to
3
cause an interrupt to the host.
LSR (IER1)—R/W.When set, this bit enables bits in the Receiver Line Status Register
2
to cause an Interrupt to the Host.
THR (IER1)—R/W. When set, this bit enables an interrupt to be sent to the Host
1
when the transmit Holding register is empty.
DR (IER0)—R/W. When set, the Received Data Ready (or Receive FIFO Timeout)
0
interrupts are enabled to be sent to Host.
23.4.2.5 KTDLMR—KT Divisor Latch MSB Register (KT—D22:F3)
Address Offset: 01h Attribute: R/W
Default Value: 00h Size: 8 bits
Host can Read/Write to this register only when the DLAB bit (KTLCR[7]) is 1. When this
bit is 0, Host accesses the KTIER.
This is the standard Serial interface's Divisor Latch register's MSB. This register is only
for SW compatibility and does not affect performance of the hardware.
Bit Description
Divisor Latch MSB (DLM)—R/W. Implements the Divisor Latch MSB register of the
7:0
Serial Interface.
988 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.4.2.6 KTIIR—KT Interrupt Identification Register
(KT—D22:F3)
Address Offset: 02h Attribute: RO
Default Value: 00h Size: 8 bits
The KT IIR register prioritizes the interrupts from the function into 4 levels and records
them in the IIR_STAT field of the register. When Host accesses the IIR, hardware
freezes all interrupts and provides the priority to the Host. Hardware continues to
monitor the interrupts but does not change its current indication until the Host read is
over. Table in the Host Interrupt Generation section shows the contents.
Bit Description
FIFO Enable (FIEN1)—RO. This bit is connected by hardware to bit 0 in the FCR
7
register.
FIFO Enable (FIEN0)—RO. This bit is connected by hardware to bit 0 in the FCR
6
register.
5:4 Reserved
IIR STATUS (IIRSTS)—RO. These bits are asserted by the hardware according to
3:1
the source of the interrupt and the priority level.
Interrupt Status (INTSTS)—RO.
0 0 = Pending interrupt to Host
1 = No pending interrupt to Host
23.4.2.7 KTFCR—KT FIFO Control Register (KT—D22:F3)
Address Offset: 02h Attribute: WO
Default Value: 00h Size: 8 bits
When Host writes to this address, it writes to the KTFCR. The FIFO control Register of
the serial interface is used to enable the FIFOs, set the receiver FIFO trigger level and
clear FIFOs under the direction of the Host.
When Host reads from this address, it reads the KTIIR.
Bit Description
Receiver Trigger Level (RTL)—WO. Trigger level in bytes for the RCV FIFO. Once
the trigger level number of bytes is reached, an interrupt is sent to the Host.
00 = 01
7:6
01 = 04
10 = 08
11 = 14
5:3 Reserved
XMT FIFO Clear (XFIC)—WO. When the Host writes one to this bit, the hardware
2
will clear the XMT FIFO. This bit is self-cleared by hardware.
RCV FIFO Clear (RFIC)—WO. When the Host writes one to this bit, the hardware
1
will clear the RCV FIFO. This bit is self-cleared by hardware.
FIFO Enable (FIE)—WO.When set, this bit indicates that the KT interface is working
0 in FIFO node. When this bit value is changed the RCV and XMT FIFO are cleared by
hardware.
Datasheet 989
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.4.2.8 KTLCR—KT Line Control Register (KT—D22:F3)
Address Offset: 03h Attribute: R/W
Default Value: 03h Size: 8 bits
The line control register specifies the format of the asynchronous data communications
exchange and sets the DLAB bit. Most bits in this register have no affect on hardware
and are only used by the FW.
Bit Description
Divisor Latch Address Bit (DLAB)—R/W. This bit is set when the Host wants to
read/write the Divisor Latch LSB and MSB Registers. This bit is cleared when the Host
7
wants to access the Receive Buffer Register or the Transmit Holding Register or the
Interrupt Enable Register.
6 Break Control (BC)—R/W. This bit has no affect on hardware.
5:4 Parity Bit Mode (PBM)—R/W. This bit has no affect on hardware.
3 Parity Enable (PE)—R/W.This bit has no affect on hardware.
2 Stop Bit Select (SBS)—R/W. This bit has no affect on hardware.
1:0 Word Select Byte (WSB)—R/W. This bit has no affect on hardware.
23.4.2.9 KTMCR—KT Modem Control Register (KT—D22:F3)
Address Offset: 04h Attribute: R/W
Default Value: 00h Size: 8 bits
The Modem Control Register controls the interface with the modem. Since the FW
emulates the modem, the Host communicates to the FW using this register. Register
has impact on hardware when the Loopback mode is on.
Bit Description
7:5 Reserved
Loop Back Mode (LBM)—R/W. When set by the Host, this bit indicates that the
4 serial port is in loop Back mode. This means that the data that is transmitted by the
host should be received. Helps in debug of the interface.
Output 2 (OUT2)—R/W. This bit has no affect on hardware in normal mode. In loop
3 back mode the value of this bit is written by hardware to the Modem Status Register
bit 7.
Output 1 (OUT1)—R/W. This bit has no affect on hardware in normal mode. In loop
2 back mode the value of this bit is written by hardware to Modem Status Register bit
6.
Request to Send Out (RTSO)—R/W. This bit has no affect on hardware in normal
1 mode. In loopback mode, the value of this bit is written by hardware to Modem Status
Register bit 4.
Data Terminal Ready Out (DRTO)—R/W. This bit has no affect on hardware in
0 normal mode. In loopback mode, the value in this bit is written by hardware to
Modem Status Register Bit 5.
990 Datasheet
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.4.2.10 KTLSR—KT Line Status Register (KT—D22:F3)
Address Offset: 05h Attribute: WO
Default Value: 00h Size: 8 bits
This register provides status information of the data transfer to the Host. Error
indication, and so on are provided by the HW/FW to the host using this register.
Bit Description
RX FIFO Error (RXFER)—RO. This bit is cleared in non FIFO mode. This bit is
7
connected to BI bit in FIFO mode.
Transmit Shift Register Empty (TEMT)—RO. This bit is connected by HW to bit 5
6
(THRE) of this register.
Transmit Holding Register Empty (THRE)—RO. This bit is always set when the
mode (FIFO/Non-FIFO) is changed by the Host. This bit is active only when the THR
operation is enabled by the FW. This bit has acts differently in the different modes:
Non FIFO: This bit is cleared by hardware when the Host writes to the THR registers
5
and set by hardware when the FW reads the THR register.
FIFO mode: This bit is set by hardware when the THR FIFO is empty, and cleared by
hardware when the THR FIFO is not empty.
This bit is reset on Host system reset or D3->D0 transition.
Break Interrupt (BI)—RO. This bit is cleared by hardware when the LSR register is
4
being read by the Host.
3:2 Reserved
Overrun Error (OE): This bit is cleared by hardware when the LSR register is being
1 read by the Host. The FW typically sets this bit, but it is cleared by hardware when
the host reads the LSR.
Data Ready (DR)—RO.
Non-FIFO Mode: This bit is set when the FW writes to the RBR register and cleared
by hardware when the RBR register is being Read by the Host.
0
FIFO Mode: This bit is set by hardware when the RBR FIFO is not empty and cleared
by hardware when the RBR FIFO is empty.
This bit is reset on Host System Reset or D3->D0 transition.
Datasheet 991
Intel® Management Engine (Intel® ME) Subsystem Registers (D22:F[3:0])
23.4.2.11 KTMSR—KT Modem Status Register (KT—D22:F3)
Address Offset: 06h Attribute: RO
Default Value: 00h Size: 8 bits
The functionality of the Modem is emulated by the FW. This register provides the status
of the current state of the control lines from the modem.
Bit Description
Data Carrier Detect (DCD)—RO. In Loop Back mode this bit is connected by
7
hardware to the value of MCR bit 3.
Ring Indicator (RI)—RO. In Loop Back mode this bit is connected by hardware to
6
the value of MCR bit 2.
Data Set Ready (DSR)—RO. In Loop Back mode this bit is connected by hardware
5
to the value of MCR bit 0.
Clear To Send (CTS)—RO. In Loop Back mode this bit is connected by hardware to
4
the value of MCR bit 1.
Delta Data Carrier Detect (DDCD)—RO. This bit is set when bit 7 is changed. This
3
bit is cleared by hardware when the MSR register is being read by the HOST driver.
Trailing Edge of Read Detector (TERI)—RO. This bit is set when bit 6 is changed
2 from 1 to 0. This bit is cleared by hardware when the MSR register is being read by
the Host driver.
Delta Data Set Ready (DDSR)—RO. This bit is set when bit 5 is changed. This bit is
1
cleared by hardware when the MSR register is being read by the Host driver.
Delta Clear To Send (DCTS)—RO. This bit is set when bit 4 is changed. This bit is
0
cleared by hardware when the MSR register is being read by the Host driver.
§§
992 Datasheet
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