MICROPROCESSOR

Prof. (Dr.) Umakanta Nanda

Department of ECE
VIT-AP
[email protected]
8086

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Software Model of the 8086 Microprocessors

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8086 Registers General Purpose Index
AH AL
BP
AX

SP
BH BL
BX
SI

CH CL
DI
CX

DH DL
DX Segment

CS

Status and Control SS

Flags DS

IP ES

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General Purpose Registers

AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register

• Normally used for storing temporary results

• Each of the registers is 16 bits wide (AX, BX, CX, DX)
• Can be accessed as either 16 or 8 bits AX, AH, AL
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General Purpose Registers
• AX
– Accumulator Register
– Preferred register to use in arithmetic, logic and data
transfer instructions because it generates the shortest
Machine Language Code
– Must be used in multiplication and division operations
– Must also be used in I/O operations

• BX
– Base Register
– Also serves as an address register

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General Purpose Registers
• CX
– Count register
– Used as a loop counter
– Used in shift and rotate operations

• DX
– Data register
– Used in multiplication and division
– Also used in I/O operations

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 Pointer and Index Registers

• All 16 bits wide, L/H bytes separately are not accessible

• Used as memory pointers

• Example: MOV AH, [SI]
• Move the byte stored in memory location whose address is contained in
register SI to register AH

• IP is not under direct control of the programmer

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Flag Register

Overflow Carry
Direction Parity

Interrupt enable Auxiliary Carry

Trap Zero
6 are status flags
Sign
3 are control flag
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8086 Programmer’s Model
ES Extra Segment
CS Code Segment
BIU registers
(20 bit adder) SS Stack Segment
DS Data Segment
IP Instruction Pointer

EU registers AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS

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The Stack
• The stack is used for temporary storage of information
such as data or addresses.

• When a CALL is executed, the 8086 automatically PUSHes

the current value of CS and IP onto the stack.

• Other registers can also be pushed

• Before return from the subroutine, POP instructions can

be used to pop values back from the stack into the
corresponding registers.

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The Stack

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What is an Instruction Set?
• The complete collection of instructions that are understood by a CPU
• Machine Code
• Binary
• Usually represented by programmer as assembly codes
Elements of an Instruction
• Operation code (Op code)
• Do this
• Source Operand reference
• To this
• Result Operand reference
• Put the answer here
• Next Instruction Reference
• When you have done that, do this...
Instruction Cycle State Diagram
Instruction Representation
• In machine code each instruction has a unique bit pattern
• For human consumption (well, programmers anyway) a symbolic
representation is used
• e.g. ADD, SUB, LOAD
• Operands can also be represented in this way
• ADD A,B
Simple Instruction Format
Instruction Types
• Data processing
• Data storage (main memory)
• Data movement (I/O)
• Program flow control
Number of Addresses (a)
• 3 addresses
• Operand 1, Operand 2, Result
• a = b + c;
• May be a forth - next instruction (usually implicit)
• Not common
• Needs very long words to hold everything
Number of Addresses (b)
• 2 addresses
• One address doubles as operand and result
• a=a+b
• Reduces length of instruction
• Requires some extra work
• Temporary storage to hold some results
Number of Addresses (c)
• 1 address
• Implicit second address
• Usually a register (accumulator)
• Common on early machines
Number of Addresses (d)
• 0 (zero) addresses
• All addresses implicit
• Uses a stack
• e.g. push a
• push b
• add
• pop c

• c=a+b
INSTRUCTION SET

Prof. (Dr.) Umakanta Nanda

Department of ECE
VIT-AP
[email protected]
 Instruction Representation

• In machine code each instruction has a unique bit

pattern
• For human consumption (well, programmers
anyway) a symbolic representation is used
– e.g. ADD, SUB, LOAD
• Operands can also be represented in this way
– ADD A,B
Simple Instruction Format
 Instruction Types

• Data processing
• Data storage (main memory)
• Data movement (I/O)
• Program flow control
 Number of Addresses (a)

• 3 addresses
– Operand 1, Operand 2, Result
– a = b + c;
– May be a forth - next instruction (usually implicit)
– Not common
– Needs very long words to hold everything
 Number of Addresses (b)

• 2 addresses
– One address doubles as operand and result
–a = a + b
– Reduces length of instruction
– Requires some extra work
• Temporary storage to hold some results
 Number of Addresses (c)

• 1 address
– Implicit second address
– Usually a register (accumulator)
– Common on early machines
8086 Microprocessor Instruction Set

8086 supports 6 types of instructions.

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logical Instructions

4. String manipulation Instructions

5. Process Control Instructions

6. Control Transfer Instructions

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8086 Microprocessor
Instruction Set

1. Data Transfer Instructions

Instructions that are used to transfer data/ address in to

registers, memory locations and I/O ports.

Generally involve two operands: Source operand and

Destination operand of the same size.

Source: Register or a memory location or an immediate data

Destination : Register or a memory location.

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory

and a 16-bit data can be moved to 16-bit register/ memory.

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8086 Microprocessor
Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

MOV reg2/ mem, reg1/ mem

MOV reg2, reg1 (reg2)  (reg1)

MOV mem, reg1 (mem)  (reg1)
MOV reg2, mem (reg2)  (mem)

MOV reg/ mem, data

MOV reg, data (reg)  data

MOV mem, data (mem)  data

XCHG reg2/ mem, reg1

XCHG reg2, reg1 (reg2)  (reg1)

XCHG mem, reg1 (mem)  (reg1)

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8086 Microprocessor
Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

PUSH reg16/ mem

PUSH reg16 (SP)  (SP) – 2

MA S = (SS) x 1016 + SP
(MA S ; MA S + 1)  (reg16)

PUSH mem (SP)  (SP) – 2

MA S = (SS) x 1016 + SP
(MA S ; MA S + 1)  (mem)

POP reg16/ mem

POP reg16 MA S = (SS) x 1016 + SP

(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2

POP mem MA S = (SS) x 1016 + SP

(mem)  (MA S ; MA S + 1)
(SP)  (SP) + 2
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8086 Microprocessor
Instruction Set

1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

IN A, [DX] OUT [DX], A

IN AL, [DX] PORTaddr = (DX) OUT [DX], AL PORTaddr = (DX)

(AL)  (PORT) (PORT)  (AL)

IN AX, [DX] PORTaddr = (DX) OUT [DX], AX PORTaddr = (DX)

(AX)  (PORT) (PORT)  (AX)

IN A, addr8 OUT addr8, A

IN AL, addr8 (AL)  (addr8) OUT addr8, AL (addr8)  (AL)

IN AX, addr8 (AX)  (addr8) OUT addr8, AX (addr8)  (AX)

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8086 Microprocessor
Instruction Set

Condition of Flag

1. Data Transfer Instructions

MOV, XCHG, PUSH, POP, IN, OUT …
These instructions do not affect any flag

2. Arithmetic Instructions
ADD, ADC, SUB, SBB, CMP…
Affects CF, ZF, SF, OF, PF, AF.
INC, DEC
Affects ZF, SF, OF, PF, AF
MUL, IMUL, DIV, IDIV
Affects CF, OF

3. Logical Instructions
AND, OR, XOR, TEST, SHR, SHL, RCR, RCL
Affects CF, ZF, SF, OF, PF, AF

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8086 Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADD reg2/ mem, reg1/mem

ADD reg2, reg1 (reg2)  (reg1) + (reg2)

ADD reg2, mem (reg2)  (reg2) + (mem)
ADD mem, reg1 (mem)  (mem)+(reg1)

ADD reg/mem, data

ADD reg, data (reg)  (reg)+ data

ADD mem, data (mem)  (mem)+data

ADD A, data

ADD AL, data8 (AL)  (AL) + data8

ADD AX, data16 (AX)  (AX) +data16

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8086 Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADC reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2)  (reg1) + (reg2)+CF

ADC reg2, mem (reg2)  (reg2) + (mem)+CF
ADC mem, reg1 (mem)  (mem)+(reg1)+CF

ADC reg/mem, data

ADC reg, data (reg)  (reg)+ data+CF

ADC mem, data (mem)  (mem)+data+CF

ADC A, data

ADC AL, data8 (AL)  (AL) + data8+CF

ADC AX, data16 (AX)  (AX) +data16+CF

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8086 Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SUB reg2/ mem, reg1/mem

SUB reg2, reg1 (reg2)  (reg2) - (reg1)

SUB reg2, mem (reg2)  (reg2) - (mem)
SUB mem, reg1 (mem)  (mem) - (reg1)

SUB reg/mem, data

SUB reg, data (reg)  (reg) - data

SUB mem, data (mem)  (mem) - data

SUB A, data

SUB AL, data8 (AL)  (AL) - data8

SUB AX, data16 (AX)  (AX) - data16

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8086 Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SBB reg2/ mem, reg1/mem

SBB reg2, reg1 (reg2)  (reg2) - (reg1) - CF

SBB reg2, mem (reg2)  (reg2) - (mem)- CF
SBB mem, reg1 (mem)  (mem) - (reg1) –CF

SBB reg/mem, data

SBB reg, data (reg)  (reg) – data - CF

SBB mem, data (mem)  (mem) - data - CF

SBB A, data

SBB AL, data8 (AL)  (AL) - data8 - CF

SBB AX, data16 (AX)  (AX) - data16 - CF

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8086 Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

INC reg/ mem

INC reg8 (reg8)  (reg8) + 1

INC reg16 (reg16)  (reg16) + 1

INC mem (mem)  (mem) + 1

DEC reg/ mem

DEC reg8 (reg8)  (reg8) - 1

DEC reg16 (reg16)  (reg16) - 1

DEC mem (mem)  (mem) - 1

After DEC instruction we can use any JMP (Cond. Or Non-conditional) incase of loop

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8086 Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

MUL reg/ mem

MUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

MUL mem For byte : (AX)  (AL) x (mem8)

IMUL reg/ mem

IMUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

IMUL mem For byte : (AX)  (AX) x (mem8)

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8086 Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

DIV reg/ mem

DIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  Remainder

For 16-bit :- 8-bit :

DIV mem (AL)  (AX) :- (mem8) Quotient
(AH)  Remainder

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8086 Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

IDIV reg/ mem

IDIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  Remainder

For 16-bit :- 8-bit :

IDIV mem (AL)  (AX) :- (mem8) Quotient
(AH)  Remainder

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8086 Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg2/mem, reg1/ mem

CMP reg2, reg1 Modify flags  (reg2) – (reg1)

If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0

CMP reg2, mem Modify flags  (reg2) – (mem)

If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0

CMP mem, reg1 Modify flags  (mem) – (reg1)

If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0

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8086 Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg/mem, data

CMP reg, data Modify flags  (reg) – (data)

If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0

CMP mem, data Modify flags  (mem) – (data)

If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0

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8086 Microprocessor Instruction Set

2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP A, data

CMP AL, data8 Modify flags  (AL) – data8

If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0

CMP AX, data16 Modify flags  (AX) – data16

If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0

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SUM OF N CONSECUTIVE NUMBERS

MOV SI, 2000H SI = 2000H

MOV CL, [SI] CL = 03H

MOV AL, 00H AL = 00H

MOV BL, 01H BL = 01H

LOOP ADD AL, BL AL = 01H

INC BL BL = 02H

DEC CL CL = 02H

JNZ LOOP
MOV DI, 2002H
MOV [DI], AX
HLT
8086 Microprocessor Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

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8086 Microprocessor
Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

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8086 Microprocessor Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

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8086 Microprocessor Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

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8086 Microprocessor Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

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8086 Microprocessor Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

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8086 Microprocessor Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

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8086 Microprocessor Instruction Set

3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, ROL …

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8086 Microprocessor Instruction Set

4. String Manipulation Instructions

 String : Sequence of bytes or words

 8086 instruction set includes instruction for string movement, comparison,

scan, load and store.

 REP instruction prefix : used to repeat execution of string instructions

 String instructions end with S or SB or SW.

S represents string, SB string byte and SW string word.

 Offset or effective address of the source operand is stored in SI register and

that of the destination operand is stored in DI register.

 Depending on the status of DF, SI and DI registers are automatically

updated.

 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.

 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.

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8086 Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

MOVS

MOVSB MA = (DS) x 1016 + (SI)

MAE = (ES) x 1016 + (DI)

(MAE)  (MA)

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1

If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

MOVSW MA = (DS) x 1016 + (SI)

MAE = (ES) x 1016 + (DI)

(MAE ; MAE + 1)  (MA; MA + 1)

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2

If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2

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 8086 Microprocessor
Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
REP Example:
REPZ/ REPE While CX  0 and ZF = 1, repeat execution of MOVSB
string instruction and REP MOVSB
(Repeat string instruction (CX)  (CX) – 1
until ZF = 0)
MOVSW
REP MOVSW
REPNZ/ REPNE While CX  0 and ZF = 0, repeat execution of
string instruction and
(Repeat string instruction (CX)  (CX) - 1
until ZF = 1)

In the example, the first form copies a single byte from the source string, at address DS:SI, to the destination string, at
address ES:DI, then increments (or decrements, if the Direction flag is set) both SI and DI.

The second form performs this operation and then decrements CX; if CX is not zero, the operation is repeated.
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8086 Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, LODS, STOS

Compare two string byte or string word

CMPS

CMPSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

Modify flags  (MA) - (MAE)

If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0

If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
CMPSW If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0

For byte operation

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1
If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

For word operation

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2
If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2

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8086 Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Load string byte in to AL or string word in to AX

LODS

LODSB MA = (DS) x 1610 + (SI)

(AL)  (MA)

If DF = 0, then (SI)  (SI) + 1

If DF = 1, then (SI)  (SI) – 1

LODSW MA = (DS) x 1610 + (SI)

(AX)  (MA ; MA + 1)

If DF = 0, then (SI)  (SI) + 2

If DF = 1, then (SI)  (SI) – 2

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8086 Microprocessor Instruction Set

4. String Manipulation Instructions

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Store byte from AL or word from AX in to string

STOS

STOSB MAE = (ES) x 1610 + (DI)

(MAE)  (AL)

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

STOSW MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1 )  (AX)

If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2

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8086 Microprocessor Instruction Set

5. Processor Control Instructions

Mnemonics Explanation
STC Set CF  1

CLC Clear CF  0

CMC Complement carry CF  CF/

STD Set direction flag DF  1

CLD Clear direction flag DF  0

STI Set interrupt enable flag IF  1

CLI Clear interrupt enable flag IF  0

NOP No operation

HLT Halt after interrupt is set

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8086 Microprocessor Instruction Set

6. Control Transfer Instructions

Transfer the control to a specific destination or target instruction

Do not affect flags

 8086 Unconditional transfers

Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine

RET Return from subroutine

JMP reg/ mem/ disp8/ disp16 Unconditional jump

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8086 Microprocessor Instruction Set

6. Control Transfer Instructions

Checks flags

If conditions are true, the program control is

transferred to the new memory location in the same
segment by modifying the content of IP

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8086 Microprocessor Instruction Set

6. Control Transfer Instructions

Name Alternate name Name Alternate name

JE disp8 JZ disp8 JE disp8 JZ disp8
Jump if equal Jump if result is 0 Jump if equal Jump if result is 0

JNE disp8 JNZ disp8 JNE disp8 JNZ disp8

Jump if not equal Jump if not zero Jump if not equal Jump if not zero
JG disp8 JNLE disp8 JA disp8 JNBE disp8
Jump if greater Jump if not less or Jump if above Jump if not below
equal or equal
JGE disp8 JNL disp8 JAE disp8 JNB disp8
Jump if greater Jump if not less Jump if above or Jump if not below
than or equal equal
JL disp8 JNGE disp8 JB disp8 JNAE disp8
Jump if less than Jump if not Jump if below Jump if not above
greater than or or equal
equal
JLE disp8 JNG disp8 JBE disp8 JNA disp8
Jump if less than Jump if not Jump if below or Jump if not above
or equal greater equal 44
8086 Microprocessor Instruction Set

6. Control Transfer Instructions

 8086 conditional branch instructions affecting individual flags

Mnemonics Explanation

JC disp8 Jump if CF = 1

JNC disp8 Jump if CF = 0

JP disp8 Jump if PF = 1

JNP disp8 Jump if PF = 0

JO disp8 Jump if OF = 1

JNO disp8 Jump if OF = 0

JS disp8 Jump if SF = 1

JNS disp8 Jump if SF = 0

JZ disp8 Jump if result is zero, i.e, Z = 1

JNZ disp8 Jump if result is not zero, i.e, Z = 1

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Branch Instruction
Nested Procedure Calls
Addressing modes
Dr. Umakanta Nanda
Dept. of ECE
VIT-AP
Addressing modes
Addressing mode is the way of locating the data or operands, the types of
operands used and the way they are accessed for executing an instruction.
Based on the flow of instructions, the instructions in 8086 can be categorized as
1. Sequential control flow instructions
2. Control transfer instructions
Sequential control flow are the instructions in which after execution, the control
is transferred to the next instruction appearing immediately after it in the
program.
Eg. Arithmetic instructions, logical, data transfer, and processor control
instructions.
Control transfer instructions transfer their control to some predefined address
after their execution. Eg. INT, CALL, RET, and JUMP instructions.
Addressing modes

1. Register addressing mode 1. Intrasegment direct addressing mode

2. Immediate addressing mode 2. Intrasegment indirect addressing mode
3. Direct addressing mode 3. Intersegment direct addressing mode
4. Register indirect addressing mode
4. Intersegment indirect addressing mode
5. Register relative addressing mode
6. Indexed addressing mode
7. Based indexed addressing mode
8. Relative based indexed addressing
mode
Sequential Control flow modes
1. Register addressing mode
2. Immediate addressing mode
3. Direct addressing mode
4. Register indirect addressing mode
5. Register relative addressing mode
6. Indexed addressing mode
7. Based indexed addressing mode
8. Relative based indexed addressing mode
Register addressing mode
In this mode, both the operands are specified by registers.
Eg. MOV AX, BX
All the registers can be used in this mode.
Both the source and destination registers should be of the same size
Immediate addressing mode
In this mode, the source operand is specified as immediate data byte
or word and the destination is either a register or a memory location.
Eg. MOV AL, 22H; MOV BX, 3456H
All the registers can be used in this mode.
Both the source and destination registers should be of the same size
A segment to segment movement of data is not allowed
Direct addressing mode
In this mode, the source is a memory location and the destination is a
register.
Eg. MOV AL, [1234H]; MOV BX, [5000H]
Here, a 16-bit memory address i.e. the offset address is directly
specified in the instruction as a part of it.
The content of the physical address which is formed from the offset
address is the source data.
Register in-Direct addressing mode
Register indirect addressing mode allows data to be addressed at any
memory location using the offset registers: BP, BX, DI or SI
DS is the default segment when the registers BX, DI or SI are used.
SS is the default segment when the register BP is used.
Eg. MOV AX, [BX]
Register relative addressing mode
In this mode, the data in a segment of memory are addressed by
adding an 8-bit or 16-bit displacement to the contents of a base
register (BX or BP) or an index register (SI or DI).
ES and DS are the default segments when the registers BX, DI or SI
are used.
SS is the default segment when the register BP is used.
Eg. MOV AX, 1000H [BX]
Indexed addressing mode
In this mode, the offset address of the operand is stored in one of the
index registers like SI or DI.
ES and DS are the default segments for DI or SI are used.
Eg. MOV AX, [SI]
Based-Indexed addressing mode
In this mode, one base register (BX or BP) and one index register (SI
or DI) are used to indirectly address memory.
The effective address is formed by adding contents of a base register
to the contents of the index register.
Eg. MOV AX, [BX] [DI]
Relative Based-Indexed addressing mode
It is similar to the based indexed mode, but it adds a displacement
along with the base register and index register to form the memory
address
The effective address is formed by adding the 8-bit or 16-bit
displacement with the addition result of the base register and the
index register.
Eg. MOV AX, 2000H [BX] [DI]
Control transfer instruction modes

1. Intrasegment direct addressing mode

2. Intrasegment indirect addressing mode
3. Intersegment direct addressing mode
4. Intersegment indirect addressing mode

If the address location to which the control is to be transferred lies

in a different segment other than the current one, the mode is
called intersegment mode.
If the destination lies in the same segment, the mode is called
intrasegment mode
Intrasegment direct mode
In this mode, the effective branch address to which the control is to
be transferred lies in the same segment in which the control transfer
instruction lies and it appears directly in the instruction as an
immediate displacement value.
The effective branch address is the sum of an 8-bit or 16-bit
displacement in the current contents of IP.
Eg. JMP [02] ( Eff. offset Addr = [IP] + [02] )
Intrasegment indirect mode
In this mode, the effective branch address is the contents of the register or
memory location that is accessed using any one of the data addressing
modes.
The contents of the IP will be replaced by the effective branch address
Eg. JMP BX
In this instruction, the control is jumped to an address specified by the 16-
bit register.
The value of BX is copied into IP with CS value unchanged.
Then the physical address of the next instruction is obtained using the
current contents of CS and new values of IP
Intersegment direct mode
This addressing mode is used to provide means of branching from
one segment to another segment.
Eg. JMP 2000H: 3000H
i.e. the JMP instruction loads CS with 2000H and loads IP with 3000H
Intersegment indirect mode
This addressing mode replaces the contents of the IP and CS with the
contents of two consecutive words in memory that are addressed
using indirect addressing.
Eg. JMP [5000H] or JMP [BX or SI or DI]
i.e. the contents of [5000H] and [5000H+1] in DS is loaded into IP
and loads the contents of [5000H+2] and [5000H+3] in DS into CS.
Searching the existence of a certain data in a
given data array
Assumptions:
• Input data (number to be searched and array elements) are stored in data memory starting from
1200H offset.
• To store the output, a memory location 1400H offset will be used.

MEMORY DATA IN MEMORY DATA OUT

ADDRESS (offset) ADDRESS (offset)
1200 AB96 1400 1206
1202 89CD = AB96
1204 4EDF = AB96
1206 AB96 = AB96
Input number to be searched
1208 91C7
120A D6A0 Match found

Elements of the array

FLOW CHART
IF
START AX=[SI] YES
?
Initialize SI to 1200 memory
location NO

Data of SI moved to AX IF
NO CX=00
?
Counter CX is assigned by 05
yes
YES

0000 is assigned to SI
Increment SI by 02 times

compare the content contents of SI moved

of AX with [SI] to 1400 memory location

STOP
PROGRAM
Memory address level mnemonics
1000 MOV SI, 1200
MOV AX, [SI]
MOV CX, 05
GG12 INC SI
INC SI
CMP AX, [SI]
JE SS
JMP GG12
MOV SI, 0000
SS MOV [1400], SI
HLT
To separate odd and even numbers in a given
data array
Address Program Explanation
MOV CL, 06 Set counter in CL register
MOV SI, 1600 Set source index as 1600
MOV DI, 1500 Set Destination index as memory address 1500
Loop1: LODSB Load data from source memory
DEC CL Decrement the count
ROR AL, 01 Rotate AL once to right
JNB Loop1 If bit is zero Jump to Loop1
ROL AL,01 Rotate AL once to left
MOV [DI], AL Move result to Destination
INC DI Increment Destination index
CMP CL, 00H Compare CL to 00H
JNE Loop1 Jump if not equal to Loop1
HLT Stop the program

WAP to count the number of odd and even numbers in a given set of data array
Similarly write a program to separate –ve numbers from +ve numbers in a given set of data
CONVERSION OF BCD TO HEXADECIMAL
Write a program to sort a 8 bit data array in ascending order. The array consists of 5
numbers starting from location 3000H:4000H.
MOV AX,3000H
MOV DS,AX
MOV CH, 04H
L3: MOV CL,04H
MOV SI, 4000H
L2: MOV AL, [SI]
MOV AH, [SI+01H]
CMP AL, AH
JC L1
JZ L1
MOV [SI+1], AL
MOV [SI], AH
L1: INC SI
DEC CL
JNZ L2
DEC CH
JNZ L3
HLT
 Program to check a number for bit wise palindrome. If
palindrome place FFH at 2500H or place 00H at 2500H
DATA SEGMENT
X DW 0FFFFH
MSG1 DB 10,13,'NUMBER IS PALINDROME$'
MSG2 DB 10,13,'NUMBER IS NOT PALINDROME$'
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START: MOV AX,DATA ;Load the Data to AX. MOV AX, [2300H]
MOV DS,AX ;Move the Data AX to DS.
MOV AX,X ;Move DW to AX.
MOV CL,10H ;Initialize the counter 10.
MOV CL,10H ;Initialize the counter 10. UP: ROR AX,1 ;Rotate right one time.
UP: ROR AX,1 ;Rotate right one time. RCL DX,1 ;Rotate left with carry one time.
RCL DX,1 ;Rotate left with carry one time. DEC CL
LOOP UP ;Loop the process.
CMP AX,DX ;Compare AX and DX. JNZ UP ;Loop the process.
JNZ DOWN ;If no zero go to DOWN label. CMP AX,DX ;Compare AX and DX.
LEA DX,MSG1 ;Declare as a PALINDROME. JNZ DOWN ;If no zero go to DOWN label.
MOV AH,09H
INT 21H
MOV [2500H], FFH ;Declare as a PALINDROME.
JMP EXIT ;Jump to EXIT label. JMP EXIT ;Jump to EXIT label.
DOWN: LEA DX,MSG2 ; Declare as not a PALINDROME DOWN: MOV [2500H], 00H ; Declare as not a PALINDROME
MOV AH,09H EXIT: HLT
INT 21H
EXIT:MOV AH,4CH
INT 21H
CODE ENDS
END START
WAP to reverse a string of 100 bytes using stack. Check whether the
string is palindrome or not. If it is palindrome display FFH on a display
unit whose address is 64H else display 00H.
MOV SI, 2300H MOV SI, 2300H
MOV DI, 2500H MOV DI, 2500H
MOV CL, 64H MOV CL, 64H
L1: MOV AL, [SI] CLD
PUSH AL REPZ CMPSB
JNZ L3
INC SI
MOV AL, FFH
DEC CL OUT 64H
JNZ L1 JMP Exit
MOV CL, 64H L3: MOV AL, 00H
L2: POP AL OUT 64H
MOV [DI], AL Exit: HLT
INC DI
DEC CL
JNZ L2
ALP to find the Sum of cubes of an array of size 10
by using 8086.
MOV SI,0200 H
MOV DI,0220H
MOV CL,0AH
MOV AX,0000 H
MOV [DI],AX
Up: MOV AL,[SI]
MOV BL,AL
MUL AL
MUL BL
ADD [DI],AX
INC SI
DEC CL
JNZ Up
HLT
Program to get the square root of a number
M0V AX, [0500H] move the data from offset 500 to register AX
MOV CX, 0000H move 0000 to register CX
MOV BX, FFFFH move FFFF to register BX
L1: ADD BX, 0002H add BX and 02
INC CX increment the content of CX by 1
SUB AX, BX subtract contents of AX with BX
JNZ L1 jump to address 040A if zero flag(ZF) is 0
MOV [600], CX store the contents of CX to offset 600
HLT end the program
Write a program to get Factorial of 10 numbers stored from the starting
location 4000H:1000H. The results should be stored in 4000H:2000H
MOV AX,4000H
MOV DS, AX
MOV SI,1000H
MOV DI, 2000H
Mov CL,0AH
MOV AL, 01H
Next:MOV BL,[SI]
LOOK:MUL BL
DEC BL
JNZ LOOK
MOV [DI], AL
INC SI
INC DI
LOOP NEXT
HLT
Write an ALP to convert binary number to gray code

Start

Initialize SI to 1200 memory location

Move contents of SI to AX and BX

Shift contents of BX to one bit right

Perform XOR operation on AX and BX

Move contents of AX to
1400 memory location

Stop
Program
MOV SI, 1200

MOV AX, [SI]

MOV BX, [SI]

SHR BX, 01

XOR AX, BX

MOV [1400], AX

HLT
Flowchart Start

Initialize SI to 1200 memory location

Move contents of SI to AX and BX

Shift contents of BX to one bit right

Perform XOR operation on AX and BX

Compare contents of BX with 0000

No If equal
?
Yes
Move contents of AX to
Stop
1400 memory location
Program
Mnemonics
MOV SI, 1200
MOV AX, [ SI ]
MOV BX, [ SI ]
LOOP 1 SHR BX, 01
XOR AX, BX
CMP BX, 0000
JE LOOP 2
JMP LOOP 1
LOOP 2 MOV [ 1400 ], AX
HLT
Program to find Greatest common divisor (GCD) of
given numbers
MOV SI, 2300H ;Store Offset address 2300h in SI
MOV DI, 2400H ;Store offset address 2400h in DI
MOV AX, [SI] ;Move the first number to AX.
MOV BX, [SI+1] ;Move the second number to BX.
UP: CMP AX, BX ;Compare the two numbers.
JE EXIT ;If equal, go to EXIT label.
JB EXCG ;If first number is below than second, go to EXCG label.
UP1: MOV DX,0000H ;Initialize the DX.
DIV BX ;Divide the first number by second number.
CMP DX,0000H ;Compare remainder is zero or not.
JE EXIT ;If zero, jump to EXIT label.
MOV AX,DX ;If non-zero, move remainder to AX.
JMP UP ;Jump to UP label.
EXCG: XCHG AX,BX ;Exchange the remainder and quotient.
JMP UP1 ;Jump to UP1.
EXIT: MOV [DI], BX ;Store the result in DI.
HLT ; Stop
Program to find least common multiple (LCM) of a
given numbers
MOV SI, 2300H ;Store Offset address 2300h in SI
MOV DI, 2400H ;Store offset address 2400h in DI
MOV DX,0000H ;Initialize the DX
MOV AX,[SI] ;Move the first number to AX
MOV BX,[SI+2] ;Move the second number to AX
UP: PUSH AX ;Store the quotient/first number STACK
PUSH DX ;Store the remainder STACK
DIV BX ;Divide the first number by second number
CMP DX,0000H ;Compare the remainder.
JE EXIT ;If remainder is zero, go to EXIT label
POP DX ;If remainder is non-zero, ;Retrieve the remainder from stack
POP AX ;Retrieve the quotient from stack
ADD AX,[SI] ;Add first number with AX
JNC DOWN ;If no carry jump to DOWN label
INC DX ;Increment DX
DOWN: JMP UP ;Jump to Up label
EXIT: MOV [DI], AX ;If remainder is zero, store the value of LCM at destination
HLT ;Stop
Some important programs
• Program to count logical 1’s and 0’s in a given data
• Program for getting square of array of numbers
• Program to find LCM of a given numbers
• Program to find GCD of a given numbers
• Program to check a number is Bit wise palindrome or not
• Program to check a 16 bit number is Nibble wise palindrome or not
• Program to reverse a string
• Program to search for a character in a string
INTERRUPT
Bus arbitration for I/O devices
Data transfer techniques
 The Purpose of Interrupts
I/O Organizations can be of 3 different types
1. Programmed I/O (Polling/Daisy chain)
2. Interrupt driven I/O
3. DMA
• Interrupts are useful when interfacing I/O devices with low data-transfer rates, like a keyboard or a mouse, in
which case polling the device wastes valuable processing time
• The peripheral interrupts the normal application execution, requesting to send or receive data.
• The processor jumps to a special program called Interrupt Service Routine to service the peripheral
• After the processor services the peripheral, the execution of the interrupted program continues.

Main Program Main Program Main Program Main Program

Printer Interrupt Modem Interrupt Modem Interrupt

3
Interrupts
• Interrupt Types
• Hardware Interrupts: External event
• Software Interrupts: Internal event (Software generated)
• Maskable and non-maskable interrupts
• Vectored and non vectored interrupts
• Interrupt priority
• Interrupt Vectors and Interrupt Handlers
• Interrupt Controllers

4
BASIC INTERRUPT TERMINOLOGY
• Interrupt pins: Set of pins used in hardware interrupts
• Interrupt Service Routine (ISR) or Interrupt handler: code used for
handling a specific interrupt
• Interrupt priority: In systems with more than one interrupt inputs, some
interrupts have a higher priority than other
• They are serviced first if multiple interrupts are triggered simultaneously
• Interrupt vector: Code loaded on the bus by the interrupting device that
contains the Address (segment and offset) of specific interrupt service
routine
• Interrupt Masking: Ignoring (disabling) an interrupt
• Non-Maskable Interrupt: Interrupt that cannot be ignored (power-down)
5
Interrupt processing flow Main program

Interrupt N
Req

Accept N
Interrupt

Get interrupt
vector

Jump to ISR
Save PC

Load PC

6
Hardware Interrupts – Interrupt pins and timing
• x86 Interrupt Pins
• INTR: Interrupt Request. Activated by a peripheral device to interrupt the processor.
• Level triggered. Activated with a logic 1.
• /INTA: Interrupt Acknowledge. Activated by the processor to inform the interrupting device the the
interrupt request (INTR) is accepted.
• Level triggered. Activated with a logic 0.
• NMI: Non-Maskable Interrupt. Used for major system faults such as power failures.
• Edge triggered. Activated with a positive edge (0 to 1) transition.
• Must remain at logic 1, until it is accepted by the processor.
• Before the 0 to 1 transition, NMI must be at logic 0 for at least 2 clock cycles.
• No need for interrupt acknowledgement.

INTR

INTA΄

D7-D0 Vector

7
Interrupt Vectors
• The processor uses the interrupt vector to determine the address of the ISR of the
interrupting device.
• In the 8088/8086 processor as well as in the 80386/80486/Pentium processors operating
in Real Mode (16-bit operation), the interrupt vector is a pointer to the Interrupt Vector
Table.
• The Interrupt Vector Table occupies the address range from 00000H to 003FFH (the
first 1024 bytes in the memory map).
• Each entry in the Interrupt Vector Table is 4 bytes long:
• The first two represent the offset address and the last two the segment address
of the ISR.
• The first 5 vectors are reserved by Intel to be used by the processor.
• The vectors 5 to 255 are free to be used by the user.

8
Interrupt Vector Table

9
Interrupt Vector - Example
•Draw a circuit diagram to show how a device with interrupt vector
4CH can be connected on an 8088 microprocessor system.
•Answer:
• The peripheral device activates the INTR line
• The processor responds by activating the INTA signal
• The NAND gate enables the 74LS244 octal buffer
• the number 4CH appears on the data bus
• The processor reads the data bus to get the interrupt vector
D7

Peripheral
Device
8088 System

D0

A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
E2 INTR
LS244
E1
I7 I6 I5 I4 I3 I2 I1 I0
A19 +5V
INTA
4C = 0 1 0 0 1 1 0 0
INTR

10
Interrupt Vector Table – Real Mode (16-bit) Example
•Using the Interrupt Vector Table shown below, determine the
address of the ISR of a device with interrupt vector 42H.
•Answer: Address in table = 4 X 42H = 108H
• (Multiply by 4 since each entry is 4 bytes)
• Offset Low = [108] = 2A, Offset High = [109] = 33
• Segment Low = [10A] = 3C, Segment High = [10B] = 4A
• Address = 4A3C:332A = 4A3C0 + 332A = 4D6EAH
0 1 2 3 4 5 6 7 8 9 A B C D E F
00000 3C 22 10 38 6F 13 2C 2A 33 22 21 67 EE F1 32 25
00010 11 3C 32 88 90 16 44 32 14 30 42 58 30 36 34 66
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
00100 4A 33 3C 4A AA 1A 1B A2 2A 33 3C 4A AA 1A 3E 77
00110 C1 58 4E C1 4F 11 66 F4 C5 58 4E 20 4F 11 F0 F4
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
00250 00 10 10 20 3F 26 33 3C 20 26 20 C1 3F 10 28 32
00260 20 4E 00 10 50 88 22 38 10 5A 38 10 4C 55 14 54
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
003E0 3A 10 45 2F 4E 33 6F 90 3A 44 37 43 3A 54 54 7F
11
003F0 22 3C 80 01 3C 4F 4E 88 22 3C 50 21 49 3F F4 65
Interrupt Vector Table – Real Mode (16-bit) Example
•Write a sequence of instructions that initialize vector 40H to point to the ISR “isr40”.
•Answer: Address in table = 4 X 40 = 100H
• Set ds to 0 since the Interrupt Vector Table begins at 00000H
• Get the offset address of the ISR using the Offset directive
• and store it in the addresses 100H and 101H
• Get the segment address of the ISR using the Segment directive
• and store it in the addresses 102H and 103H
push ax Save registers in the stack
push ds
mov ax,0
Set ds to 0 to point to the interrupt vector table
mov ds,ax
mov ax,offset isr40 Get the offset address of the ISR and store
mov [0100h],ax it in the address 0100h (4X40 = 100h)
mov ax,segment isr40 Get the segment address of the ISR
mov [0102h],ax and store it in the address 0102h
pop ds
Restore registers from the stack
pop ax
12
Interrupt Masking
• The processor can inhibit certain types of interrupts by use of a
special interrupt mask bit.
• This mask bit is part of the flags/condition code register, or a special
interrupt register.
• If this bit is clear, and an interrupt request occurs on the Interrupt
Request input, it is ignored.
• NMI cannot be masked

13
S/W Interrupt Processing
• Save state
• Disable interrupts for the duration of the ISR or allow it to be interrupted
too?
• Save program counter/Instruction Pointer
• Save flags
• Save register values?
• Jump to interrupt service routine
• Location obtained by interrupt vector
• Process interrupt
• Restore state
• Load PC/IP, flags, registers etc.

14
H/W Interrupt Processing
• External interface sends an interrupt signal, to the Interrupt Request (INTR) pin, (or an internal interrupt
occurs.)
• The CPU finishes the present instruction (for a hardware interrupt) and checks the INTR pin.
• If IF=0 the processor ignores the interrupt, else sends Interrupt Acknowledge (INTA) to hardware interface.
• The interrupt type N is sent to the Central Processor Unit (CPU) via the Data bus from the hardware
interface.
• The contents of the flag registers are pushed onto the stack.
• Both the interrupt (IF – FR bit 9) and (TF – FR bit 8) flags are cleared. This disables the INTR pin and the
trap or single-step feature.
• The contents of the code segment register (CS) are pushed onto the Stack.
• The contents of the instruction pointer (IP) are pushed onto the Stack.
• The interrupt vector contents are fetched, from (4 x N) and then placed into the IP and from (4 x N +2) into
the CS so that the next instruction executes at the interrupt service procedure addressed by the interrupt
vector.
• While returning from the interrupt-service routine by the Interrupt Return (IRET) instruction, the IP, CS and
Flag registers are popped from the Stack and return to their state prior to the interrupt.

15
The Intel x86 Interrupt Software Instructions
• All x86 processors provide the following instructions related to
interrupts:
• INT nn: Interrupt. Run the ISR pointed by vector nn.
• INT 0 is reserved for the Divide Error
• INT 1 is reserved for Single Step operation
• INT 2 is reserved for the NMI pin
• INT 3 is reserved for setting a Breakpoint
• INT 4 is reserved for Overflow (Same as the INTO (Interrupt on overflow)
instruction.
• CLI: Clear Interrupt Flag. IF is set to 0, thus interrupts are disabled.
• STI: Set Interrupt Flag. IF is set to 1, thus interrupts are enabled.
• IRET: Return from interrupt. This is the last instruction in the ISR (Real
Mode only). It pops from the stack the Flag register, the IP and the CS.
• After returning from an ISR the interrupts are enabled, since the initial value of
the flag register is poped from the stack.

16
Divide-By-Zero Interrupt-Type 0:
The 8086 will automatically do a type 0 interrupt if the result of a DIV operation or an IDIV operation is too large to fit in the destination
register. For a type 0 interrupt, the 8086 pushes the flag register on the stack, resets IF and TF and pushes the return addresses on the stack.

Single Step Interrupt-Type 1:

The use of single step execution feature is found in some of the monitor & debugger programs. When we tell a system to single step by
making TF=1, it will execute one instruction and stop. We can then examine the contents of registers and memory locations.

In other words, when in single step mode a system will stop after it executes each instruction and wait for further direction from user. The
8086 trap flag and type 1 interrupt response make it quite easy to implement a single step feature direction.

Non-maskable Interrupt-Type 2:
The 8086 will automatically do a type 2 interrupt response when it receives a low to high transition on its NMI pin. When it does a type 2
interrupt, the 8086 will push the flags on the stack, reset TF and IF, and push the CS value and the IP value for the next instruction on the
stack. It will then get the CS value for the start of the type 2 interrupt service procedure from address 0000AH and the IP value for the start
of the procedure from address 00008H. Needed to save the program data or processor status in case of power failure.

Breakpoint Interrupt-Type 3:
The type 3 interrupt is produced by execution of the INT3 instruction. The main use of the type 3 interrupt is to implement a breakpoint
function in a system. Whenever we insert a breakpoint, the system executes the instructions up to the breakpoint and then goes to the
breakpoint procedure.

Overflow Interrupt-Type4:
The 8086 overflow flag will be set if the signed result of an arithmetic operation on two signed numbers is too large to be represented in the
destination register or memory location.

Example: If we add the 8 bit signed number 01101100 and the 8 bit signed number 010111101, the result will be 10111101. This would be
the correct result if we were adding unsigned binary numbers, but it is not the correct signed result.
Intel 82C59A Interrupt Controller
• To allow the 8086 to handle a variety of devices and priority structures, it is
usually configured with an external interrupt arbiter, the 82C59A
• External devices are connected to the 82C59A, which in turn connects to
the 8086
• It accepts interrupt requests from attached modules, determines which
interrupt has the highest priority, and then signals the processor by raising
the INTR line
• The processor acknowledges via the INTA line.
• This prompts the 82C59A to place the appropriate vector information on
the data bus.
• The processor can then proceed to process the interrupt and to
communicate directly with the I/O module to read or write data
Programmable 82C59A
The 82C59A is programmable. The 8386 determines the priority
scheme to be used by setting a control word in the 82C59A.
The following interrupt modes are possible:
Fully nested: The interrupt requests are ordered in priority from 0
(IR0) through 7 (IR7)
Rotating: In some applications a number of interrupting devices are
of equal priority. In this mode a device, after being serviced, receives
the lowest priority in the group.
Special mask: This allows the processor to inhibit interrupts from
certain devices
Necessary materials to read for Interrupts
• Stallings book chapter: Input / Output (Chapter 7)
• Other materials will be provided in VTOP
Control Unit Operation
Prof. (Dr.) Umakanta Nanda
Department of ECE
VIT-AP
[email protected]
Micro-Operations
• A computer executes a program
• Fetch/execute cycle
• Each cycle has a number of steps called as micro-operations
• Each step does very little called atomic operation of CPU
Constituent Elements of
Program Execution
Fetch - 4 Registers
• Memory Address Register (MAR)
• Connected to address bus
• Specifies address for read or write op
• Memory Buffer Register (MBR)
• Connected to data bus
• Holds data to write or last data read
• Program Counter (PC)
• Holds address of next instruction to be fetched
• Instruction Register (IR)
• Holds last instruction fetched
Fetch Sequence
• Address of next instruction is in PC
• Address (MAR) is placed on address bus
• Control unit issues READ command
• Result (data from memory) appears on data
bus
• Data from data bus copied into MBR
• PC = PC+1 (in parallel with data fetch from
memory)
• Data (instruction) moved from MBR to IR
• MBR is now free for further data fetches
Fetch Sequence (symbolic)
• t1: MAR <- (PC)
• t2: MBR <- (memory)
PC <- (PC) +1
• t3: IR <- (MBR)
(tx = time unit/clock cycle)
or
• t1: MAR <- (PC)
• t2: MBR <- (memory)
• t3: PC <- (PC) +1
IR <- (MBR)
Rules for Clock Cycle Grouping
• Proper sequence must be followed
• MAR <- (PC) must precede MBR <- (memory)
• Conflicts must be avoided
• Must not read & write same register at same time
• MBR <- (memory) & IR <- (MBR) must not be in same cycle
• Also: PC <- (PC) +1 involves addition
• Use ALU
• May need additional micro-operations
 Indirect Cycle

• MAR <- (IR(address)) - address field of IR

• MBR <- (memory)
• IR(address) <- (MBR(address))

• MBR contains an address

• IR is now in same state as if direct
addressing had been used
 Interrupt Cycle
• t1: MBR <-(PC)
• t2: MAR <- save-address (Address where the content
of current PC will be stored)
• PC <- Interrupt service routine-address
• t3: memory <- (MBR) (Content of MBR ie. Previous PC
will be stored in Mem)
• This is a minimum
• May be additional micro-ops to get addresses
• N.B. saving context is done by interrupt handler routine, not
micro-ops
Execute Cycle (ADD)
• Different for each instruction
• e.g. ADD R1,X - add the contents of location X to Register 1 , result in
R1
• t1: MAR <- (IRaddress)
• t2: MBR <- (memory)
• t3: R1 <- R1 + (MBR)
• Note no overlap of micro-operations
Execute Cycle (ISZ)
• ISZ X - increment and skip if zero
• t1: MAR <- (IRaddress)
• t2: MBR <- (memory)
• t3: MBR <- (MBR) + 1
• t4: memory <- (MBR)
• if (MBR) == 0 then PC <- (PC) + 1
• Notes:
• if is a single micro-operation
• Micro-operations done during t4
Execute Cycle (BSA)

• BSA X - Branch and save address

• Address of instruction following BSA is saved in X
• Execution continues from X+1
• t1: MAR <- (IRaddress)
• MBR <- (PC)
• t2: PC <- (IRaddress)
• memory <- (MBR)
• t3: PC <- (PC) + 1
Instruction Cycle
• Each phase decomposed into sequence of elementary micro-operations
• E.g. fetch, indirect, and interrupt cycles
• Execute cycle
• One sequence of micro-operations for each opcode
• Need to tie sequences together
• Assume new 2-bit register
• Instruction cycle code (ICC) designates which part of cycle processor is in
• 00: Fetch
• 01: Indirect
• 10: Execute
• 11: Interrupt
Flowchart for Instruction Cycle

01
Functional Requirements
• Define basic elements of processor
• Describe micro-operations processor performs
• Determine functions control unit must perform
Basic Elements of Processor
• ALU
• Registers
• Internal data paths
• External data paths
• Control Unit
Types of Micro-operation
• Transfer data between registers
• Transfer data from register to external
• Transfer data from external to register
• Perform arithmetic or logical ops
Functions of Control Unit
• Sequencing
• Causing the CPU to step through a series of micro-operations
• Execution
• Causing the performance of each micro-op
• This is done using Control Signals
Control Signals-Input
• Clock
• One micro-instruction (or set of parallel micro-instructions) per clock cycle
• Instruction register
• Op-code for current instruction
• Determines which micro-instructions are performed
• Flags
• State of CPU
• Results of previous operations
• From control bus
• Interrupts
• Acknowledgements
Model of Control Unit
Control Signals - output
• Within CPU
• Cause data movement
• Activate specific functions
• Via control bus
• To memory
• To I/O modules
Example Control Signal Sequence - Fetch
• MAR <- (PC)
• Control unit activates signal to open gates between PC and MAR
• MBR <- (memory)
• Open gates between MAR and address bus
• Memory read control signal
• Open gates between data bus and MBR
Data Paths and Control Signals
Micro operations and control signals

For simplicity, the data

and control paths for
incrementing the PC and
for loading the fixed
addresses into the PC and
MAR are not shown.
 Memory
CPU Address Content

PC FFFFH MAR 6FFFH

7000H
7001H
7002H

ALU 7003H
7004H
7005H
IR FFFFH MBR FFFFH 7006H
7007H
7008H
Control Unit 7009H

Rd Wr
Implementation of
Control Unit
Prof. (Dr.) Umakanta Nanda
Department of ECE
VIT-AP
[email protected]
Control unit implementation
Implementation of Control unit is broadly of two types
• Hardwired implementation (RISC)
• Microprogrammed implementation (CISC)
Hardwired Implementation
Control unit inputs
• Flags and control bus
• Each bit means something
• Instruction register
• Op-code causes different control signals for each different instruction
• Unique logic for each op-code
• Decoder takes encoded input and produces single output
• n binary inputs and 2n outputs
• Clock
• Repetitive sequence of pulses
• Useful for measuring duration of micro-ops
• Must be long enough to allow signal propagation
• Different control signals at different times within instruction cycle
• Need a counter with different control signals for t1, t2 etc.
Control Unit with Decoded Inputs

How to implement ???

4:16 DECODER
 Hardwired control unit methods
State table method:
T-States I1 I2 I3 ---- In
T1 C11 C12 C13 --- C1n
T2 C21 C22 C23 --- C2n
--- --- --- --- --- ---
Tm Cm1 Cm2 Cm3 --- Cmn
 Hardwired Control Unit Logic
• For each control signal, to derive a Boolean expression of that signal
as a function of the inputs
• Let us consider a single control signal, C5, which causes data to be
read from the external data bus into the MBR
• Let us define two new control signals, P and Q, that have the
following interpretation:
PQ = 00 Fetch Cycle
PQ = 11 Interrupt Cycle
PQ = 10 Execute Cycle
PQ = 01 Indirect Cycle
 State table Logic Example
• Then C5 can be defined as:

• That is, the control signal C5 will be asserted

during the second time unit of both the fetch
and indirect cycles.
• This is not complete
• C5 is also needed during the execute cycle. For
our simple example, let us assume that there
are only three instructions that read from
memory: LDA, ADD and AND. Now we can
define C5 as
PQ = 00 Fetch Cycle
PQ = 11 Interrupt Cycle
• Is it that simple? PQ = 10 Execute Cycle
PQ = 01 Indirect Cycle
• No. In a modern complex processor, the
number of Boolean equations needed to define Hence an efficient and simpler approach, known as Flow
the control unit is very large. chart/ delay element method is usually used
•Referring to the figures above, depict the control signals required for the execution cycle of LOAD 200 and
STORE 300. [5]
•Express the Boolean expression for each of the control signals. [5]
•Implement the Boolean expressions for each of the control signals using minimum number of gates. [5]
Flow chart/ Delay element method:
Start

C1

C2

C3

Is
x=0
Y N
?

C4 C5

C6

End
Sequence counter method
Micro-programmed Control unit
implementation
Prof. (Dr.) Umakanta Nanda
Department of ECE
VIT-AP
[email protected]
Wilkes’ Design for Micro programmed CU
Actual Microprogrammed control unit