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Solution For All Important Questions of Module 3 Introduction To Electronics Engineering PDF

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89 views

Solution For All Important Questions of Module 3 Introduction To Electronics Engineering PDF

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keerthan050604
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© © All Rights Reserved
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®
Sri Sai Vidya Vikas Shikshana Samithi
SAI VIDYA INSTITUTE OF TECHNOLOGY
Approved by AICTE, New Delhi, Affiliated to VTU, Recognized by Govt.
of Karnataka.Accredited by NBA, New Delhi (CSE, ECE, ISE, MECH &
CIVIL), NAAC – “A” Grade
DEPARTMENT OF ELECTRONICS & COMMUNICATION
ENGINEERING
RAJANUKUNTE, BENGALURU – 560 064, KARNATAKA
Phone: 080-28468191/96/97/98 * E-mail: [email protected] * URL
www.saividya.ac.in

Course Name: Introduction to Course Code: AY:2022-2023


Electronics Engineering 22ESC143

Course Coordinator: Dr. Chaya B M Scheme: 2022 Batch: 2022

Boolean Algebra and Logic Gates

Axiomatic Definition of Boolean Algebra

Dr. Chaya.B.M, Associate Professor, Dept. of ECE SVIT, Bangalore

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Dr. Chaya.B.M, Associate Professor, Dept. of ECE SVIT, Bangalore

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Two Valued Boolean Algebra

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Basic Theorems and Properties of Boolean Algebra

Proof of Theorems:

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DeMorgan’s Theorem

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Operator Precedence:

Boolean Functions:

Truth Table

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Equivalent Logics

Algebraic Manipulation

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Minimization of Boolean Function

Complement of a Function

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Minterms and Maxterms

Canonical Form: Sum of Minterms

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Canonical Form: Product of Maxterms

Minterm Expansion

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Maxterm Expansion

Canonical Form Conversion

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Conversion Example

Standard Forms

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Non Standard Forms

Other Logic Operations

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Digital Logic Gates

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Extension to Multiple Inputs

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Multiple –input NOR/NAND

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Multiple –input XOR/XNOR

Combinational Logic:
A combinational Logic consists of input variables, logic gates and output variables. The logic
gates accepts signals from the inputs and generate signals to the outputs. This process
transforms binary information from the given input data to the required output data.

A block diagram of a combinational circuit is shown in the figure above. The n input binary
variables come from an eternal source, the m output variables go to an external destination.

For n input variables , there are 2𝑛 possible combinations of binary input values. For each
possible input combination, there is one and only one possible output combination. A
combinational circuit can be described by m Boolean functions, one for each output variable.
Each output function is expressed in terms of the n input variables.

Dr. Chaya.B.M, Associate Professor, Dept. of ECE SVIT, Bangalore

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Design Procedure:

The design of combinational circuit starts from the verbal outline of a problem and ends in a
logic circuit diagram.

The procedure involves the following steps:

1. The problem is stated.


2. The number of available input variables and required output variables is determined.
3. The input and output variables are assigned letter symbols.
4. The truth table that defines the required relationships between inputs and outputs are
defined.
5. The simplified Boolean function for each output is obtained.
6. The logic diagram is drawn.

Adders

Digital computers perform a variety of information processing tasks. Among the basic
functions encountered are the various arithmetic operation.
The most common basic arithmetic operation is the addition of two binary digits.

Half Adder:
The half adder circuit has two inputs: A and B, which add two input digits and generates a carry
and a sum.
The Half Adder adds two binary digits where the input bits are termed as augend and addend
and the result will be two outputs one is the sum and the other is carry. To perform the sum
operation, XOR is applied to both the inputs, and AND gate is applied to both inputs to produce
carry.

The truth table is shown below:

The simplified sum of products expressions are:

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Various implementation of a half adder:

Full Adder:

A full adder is a combinational circuit that forms the arithmetic sum of the three input bits. It
consists of three inputs and two outputs.
The Truth Table of the full adder is as follows:

Dr. Chaya.B.M, Associate Professor, Dept. of ECE SVIT, Bangalore

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The implementation uses the following Boolean expressions:

First Form:

Second Form: The full adder Expression after reduction can also be written as:

Dr. Chaya.B.M, Associate Professor, Dept. of ECE SVIT, Bangalore

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Third Form: The full adder Expression can also be written as: (After reduction)

Design Full adder circuit using two Half adder and one OR gate.

Solution: Considering the Full adder expressions:

Dr. Chaya.B.M, Associate Professor, Dept. of ECE SVIT, Bangalore

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A full adder can be implemented with two half adders and one OR gate as shown in the
figure. The S from the second half adder is the exclusive OR-gate of z and the output of the
first half adder giving:

Dr. Chaya.B.M, Associate Professor, Dept. of ECE SVIT, Bangalore

Availaible at VTU HUB (Android App)

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