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VEMU INSTITUTE OF TECHNOLOGY

P.KOTHA KOTA
CHITTOOR

LINEAR AND DIGITAL

IC APPLICATIONS

Prepared by:
Mrs. S.LEELALA LAKSHMI ,Professor,HOD

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Course Contents

◼ Unit 1 - Operational Amplifier

◼ Unit 2 - OP-Amp,IC555 & IC565 Applications

◼ Unit 3 - Active filters and other Ic’s

◼ Unit 4 - Voltage regulators and converts

◼ Unit 5 - Cmos logic,Combinational circuits

Sequential Logic IC’s & Memories

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Unit 1- Integrated Circuits

◼ What is an Integrated Circuit?

◼ Where do you use an Integrated Circuit?

◼ Why do you prefer an Integrated Circuit to the circuits

made by interconnecting discrete components?

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Def: The “Integrated Circuit “ or IC is a miniature,

low cost electronic circuit consisting of active and
passive components that are irreparably joined
together on a single crystal chip of silicon.

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Applications of an Integrated Circuit

◼ Communication

◼ Control

◼ Instrumentation

◼ Computer

◼ Electronics

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Advantages
:
◼ Small size

◼ Low cost

◼ Less weight

◼ Low supply voltages

◼ Low power consumption

◼ Highly reliable

◼ Matched devices

◼ Fast speed

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Classification

◼ Digital ICs
◼ Linear ICs
Integrated circuits

Monolithic circuits Thick Hybrid circuits

&Thin film

Bipolar Uni polar

Pn junction Dielectric JFET

MOSFET
isolation isolation

Classification of ICs

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Chip size and

Complexity
◼ Invention of Transistor (Ge) - 1947
◼ Development of Silicon - 1955-1959

◼ Silicon Planar Technology - 1959

◼ First ICs, SSI (3- 30gates/chip) - 1960

◼ MSI ( 30-300 gates/chip) - 1965-1970

◼ LSI ( 300-3000 gates/chip) -1970-1975

◼ VLSI (More than 3k gates/chip) - 1975
◼ ULSI (more than one million active devices are integrated on single
chip)

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SSI MSI LSI VLSI ULSI

< 100 active 100-1000 1000- >100000 Over 1

devices active 100000 active million
devices active devices active
devices devices
Integrated BJT’s and MOSFETS 8bit, 16bit Pentium
resistors, Enhanced Microproces Microproces
diodes & MOSFETS sors sors
BJT’s

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Selection of IC
Type Package Criteria
Metal can 1. Heat dissipation is important
package 2. For high power applications like power
amplifiers, voltage regulators etc.

DIP 1. For experimental or bread boarding

purposes as easy to mount
2.If bending or soldering of the leads is
not required
3. Suitable for printed circuit boards as
lead spacing is more
Flat pack 1. More reliability is required
2. Light in weight
3. Suited for airborne applications

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Factors affecting selection of IC

package
◼ Relative cost

◼ Reliability

◼ Weight of the package

◼ Ease of fabrication

◼ Power to be dissipated

◼ Need of external heat sink

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Temperature
Ranges

1. Military temperature range : -55o C to +125o C (-55o C to +85o C)

2. Industrial temperature range : -20o C to +85o C (-40o C to +85o C )

3. Commercial temperature range: 0o C to +70o C (0o C to +75o C )

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Operational Amplifier

The operational amplifier (Op-Amp) is a multi-

terminal device which internally is quite
complex.

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Operational
Amplifier
An “Operational amplifier” is a direct coupled high-gain
amplifier usually consisting of one or more differential
amplifiers and usually followed by a level translator and
output stage.

The operational amplifier is a versatile device that can be

used to amplify dc as well as ac input signals and was
originally designed for computing such mathematical
functions as addition, subtraction, multiplication and
integration.
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Basic Information of Op-Amp

Op-amps have five basic terminals, that is, two input

terminals, one output terminal and two power supply
terminals.

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Package
s

The metal can (TO) The Flat Package

Package

The Dual-in-Line (DIP)

Package
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Basic Information of an Op-amp

contd…

Power supply connection:

The power supply voltage may range from about + 5V to

+ 22V.
The common terminal of the V+ and V- sources is
connected to a reference point or ground.

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Manufacturer’s Designation for Linear ICs

◼ Fairchild - µA, µAF

◼ National Semiconductor - LM,LH,LF,TBA

◼ Motorola - MC,MFC

◼ RCA - CA,CD

◼ Texas Instruments - SN

◼ Signetics - N/S,NE/SE

◼ Burr- Brown - BB

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Fairchild’s original µA741 is also manufactured by

other manufactures as follows

◼ National Semiconductor - LM741

- MC1741
◼ Motorola

◼ RCA - CA3741

- SN52741
◼ Texas Instruments
- N5741
◼ Signetics

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◼ 741 Military grade op-amp

◼ 741C Commercial grade op-amp

◼ 741A Improved version of 741

◼ 741E Improved version of 741C

◼ 741S Military grade op-amp with higher slew rate

◼ 741SC Commercial grade op-amp with higher slew rate

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Differential Amplifier
V0 =Ad (V1 – V2 )

Ad =20 log10 (Ad ) in dB

Vc =
(V1 + V2 )
2
CMRR= ρ = | |A
d

Ac

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Characteristics and performance parameters

of Op-amp

◼ Input offset Voltage

◼ Input offset current

◼ Input bias current

◼ Differential input resistance

◼ Input capacitance

◼ Open loop voltage gain

◼ CMRR

◼ Output voltage swing

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Characteristics and performance

parameters of Op-
amp
◼ Output resistance

◼ Offset adjustment range

◼ Input Voltage range

◼ Power supply rejection ratio

◼ Power consumption

◼ Slew rate

◼ Gain – Bandwidth product

◼ Equivalent input noise voltage and current

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Characteristics and performance

parameters of Op-
amp
◼ Average temperature coefficient of offset parameters

◼ Output offset voltage

◼ Supply current

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1. Input Offset
Voltage

The differential voltage that must be applied between the

two input terminals of an op-amp, to make the output
voltage zero.

It is denoted as Vios

For op-amp 741C the input offset voltage is 6mV

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2. Input offset current

The algebraic difference between the currents flowing into

the two input terminals of the op-amp

It is denoted as Iios = | Ib1 – Ib2|

For op-amp 741C the input offset current is 200nA

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3. Input bias current

The average value of the two currents flowing

into the op-amp input terminals

It is expressed mathematically as

I b1 + I b 2
2

For 741C the maximum value of Ib is 500nA

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4. Differential Input Resistance

It is the equivalent resistance measured at either the

inverting or non-inverting input terminal with the other
input terminal grounded

It is denoted as Ri

For 741C it is of the order of 2MΩ

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5. Input capacitance

It is the equivalent capacitance measured at either the

inverting or non- inverting input terminal with the other
input terminal grounded.

It is denoted as Ci

For 741C it is of the 1-4 pF

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6. Open loop Voltage

gain
It is the ratio of output voltage to the differential input
voltage, when op-amp is in open loop configuration,
without any feedback. It is also called as large signal

voltage gain

It is denoted asAOL AOL=Vo / Vd

For 741C it is typically 200,000

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7. CMRR

It is the ratio of differential voltage gain Ad to common mode

voltage gain Ac

CMRR = Ad /Ac

Ad is open loop voltage gain AOL and Ac = VOC /Vc

For op-amp 741C CMRR is 90 dB

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8. Output Voltage
swing
The op-amp output voltage gets saturated at +Vcc and –
VEE and it cannot produce output voltage more than +Vcc
and –VEE. Practically voltages +Vsat and –Vsat are
slightly less than +Vcc and –VEE .

For op-amp 741C the saturation voltages are + 13V for supply voltages + 15V

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9. Output Resistance

It is the equivalent resistance measured between the output

terminal of the op-amp and ground

It is denoted as Ro

For op-amp 741 it is 75Ω

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10. Offset voltage adjustment

range
The range for which input offset voltage can be adjusted
using the potentiometer so as to reduce output to zero

For op-amp 741C it is + 15mV

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11. Input Voltage

range
It is the range of common mode voltages which can be
applied for which op-amp functions properly and given
offset specifications apply for the op-amp

For + 15V supply voltages, the input voltage range is +13V

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12. Power supply rejection ratio

PSRR is defined as the ratio of the change in input offset

voltage due to the change in supply voltage producing it,
keeping the other power supply voltage constant. It is
also called as power supply sensitivity (PSV)

PSRR= (Δvios / ΔVcc)|constant VEE PSRR= (Δvios / ΔVEE)|constant Vcc

The typical value of PSRR for op-amp 741C is 30µV/V

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13. Power
Consumption
It is the amount of quiescent power to be consumed by op-
amp with zero input voltage, for its proper functioning

It is denoted as Pc

For 741C it is 85mW

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14. Slew rate

It is defined as the maximum rate of change of output
voltage with time. The slew rate is specified in V/µsec

Slew rate = S = dVo / dt |max

It is specified by the op-amp in unity gain condition.

The slew rate is caused due to limited charging rate of the
compensation capacitor and current limiting and saturation of the
internal stages of op-amp, when a high frequency large amplitude
signal is applied.

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Slew rate

It is given by dVc /dt = I/C

For large charging rate, the capacitor should be small or

the current should be large.
S = Imax / C

For 741 IC the charging current is 15 µA and

the internal capacitor is 30 pF. S= 0.5V/ µsec

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Slew rate equation

dVo = Vm ω cosωt
Vs = Vm sinωt
dt
Vo = Vm sinωt
dVo
S =slew rate =
dt max

S = Vm ω = 2 π f Vm
For distortion free output, the
S = 2 π f Vm V / sec maximum allowable input
frequency fm can be obtained as
This is also called full
S
power bandwidth of the f m =
2 V m
op-amp
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15. Gain – Bandwidth

product

It is the bandwidth of op-amp when voltage

gain is unity (1).It is denoted as GB.

The GB is also called unity gain bandwidth

(UGB) or closed loop bandwidth

It is about 1MHz for op-amp 741C

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16. Equivalent Input Noise Voltage and

Current
The noise is expressed as a power density
Thus equivalent noise voltage is expressed as V2 /Hz
while the equivalent noise current is expressed as A2

/Hz

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17. Average temperature coefficient of offset parameters

The average rate of change of input offset voltage per unit

change in temperature is called average temperature coefficient of
input offset voltage or input offset voltage drift

It is measured in µV/oC. For 741 C it is 0.5 µV/oC

The average rate of change of input offset current per unit

change in temperature is called average temperature coefficient of
input offset current or input offset current drift

It is measured in nA/oC or pA/oC . For 741 C it is 12 pA/oC

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18. Output offset voltage ( Voos

)
The output offset voltage is the dc voltage present at the
output terminals when both the input terminals are
grounded.

It is denoted as Voos

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Factors affecting parameters of Op-amp

Supply Frequency Temperature

Voltage

1. Voltage gain 1. Input offset current

1. Voltage gain
2. Input resistance 2. Input offset voltage
2. Output Voltage
swing 3. Output resistance 3. Input bias current

3. Input voltage range 4. CMRR 4. Power consumption

4. Power consumption 5. Input noise voltage 5. Gain-Bandwidth

product
5. Input offset current 6. Input noise current
6. Slew rate
7. Input resistance

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Parameter consideration for

various applications
For A.C. applications For D.C. applications
Input resistance Input resistance
Output resistance Output resistance
Open loop voltage gain Open loop voltage gain
Slew rate Input offset voltage
Output voltage swing Input offset current
Gain- bandwidth product Input offset voltage and current
drifts
Input noise voltage and current

Input offset voltage and current

drifts

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Absolute Maximum Ratings of Op-

amp
◼ Maximum power dissipation: This is the maximum
power which can be dissipated, in the internal stages of
the op-amp in the form of heat

◼ Operating temperature range: As specified in the data

sheet, op-amp can work satisfactorily, over the operating
temperature range, as required for the given application

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Absolute Maximum Ratings of Op-

amp
◼ Maximum supply voltage: This is the maximum d.c.
supply voltage which can be applied to the op-amp

◼ Maximum differential input voltage: This rating gives

the maximum value of difference between the two input
voltages, applied to the two input terminals of the op-
amp

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Absolute Maximum Ratings of Op-

amp
◼ Maximum common mode input voltage: This is the
maximum value of the input voltage which can be
simultaneously applied to the two input terminals

◼ Storage temperature range: This gives the temperature

range over which the op-amp can be stored safely.

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Op-amp characteristics
dependent on the power
supply voltages
◼ Absolute maximum power supply voltage

◼ Absolute maximum differential input voltages

◼ Absolute maximum common mode input voltage

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Ideal Op-amp:

1.An ideal op-amp draws nocurrent at both the input

terminalsI.e. I1 = I2 = 0. Thus its inputimpedance is infinite.
Any sourcecan drive it and there is no loading

2. The gain of an ideal op-amp is infinite, hence the

on the driver stage
differential input Vd = V1 – V2 is essentially zero for the
finite output voltage Vo

3. The output voltage Vo is independent of the current

drawn from the output terminals. Thus its output
impedance is zero and hence output can drive an infinite
number of other circuits
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The Ideal Operational

Amplifier
◼ Open loop voltage gain AOL =∞

◼ Input Impedance Ri =∞

◼ Output Impedance Ro =0

◼ Bandwidth BW =∞

◼ Zero offset (Vo = 0 when V1 = V2 = 0) Vios =0

◼ CMRR ρ =∞
◼ Slew rate S =∞

◼ No effect of temperature
◼ Power supply rejection ratio PSRR = 0

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Ideal Voltage transfer

curve

+Vsat
AOL = ∞

-Vd +Vd
0
+Vsat ≈ +Vcc
-Vsat

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Practical voltage transfer

curve
1. If Vd is
greater than corresponding to b,
the output
 attains +Vsat

2. If Vd is
less than corresponding to a, the
output attains

–Vsat
3. Thus range a-b is input range for which output varies

linearily with the input. But AOL is very high,

practically this range is very small

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Equivalent circuit of practical op-

amp

AOL = Large signal open loop voltage gain

Vd = Difference voltage V1 – V2
V1 = Non-inverting input voltage with respect to ground

V2 = Inverting input voltage with respect to ground

Ri = Input resistance of op-amp

Ro = Output resistance of op-amp

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Transient Response Rise time

When the output of the op-amp is suddenly changing like

pulse type, then the rise time of the response depends on
the cut-off frequency fH of the op-amp. Such a rise time is
called cut-off frequency limited rise time or transient
response rise time ( tr )

0 .3 5
tr =
fH

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Op-amp
Characteristics

◼ DC Characteristics
Input bias current Input offset current Input

offset voltage Thermal drift

◼ AC Characteristics
Slew rate Frequency response

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DC Characteristics Thermal Drift

The op-amp parameters input offset

voltage Vios and input offset current

Iios are not constants but vary with

the factors

1. Temperature

2. Supply Voltage changes

3. Time

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Thermal Voltage Drift

It is defined as the average rate of change of input offset voltage per

unit change in temperature. It is also called as input offset
voltage drift

 V io s
Input offset voltage drift =
T

∆Vios = change in input offset voltage

∆T = Change in temperature

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It is expressed in μV/0 c. The drift is not constant and it is

 not uniform over specified operating temperature

range. The value of input offset voltage may increase or
decrease with the increasing temperature
2 Slope can be of
either polarities Input Offset Voltage Drift
Vios
in 1
mv
0
-1

-2
TA , ambient
temp in oc
-55
-25 0 25 50 75
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Input bias current drift

It is defined as the average rate of change of input bias
current per unit change in temperature

Thermal drift in input bias current = Ib

T
It is measured in nA/oC or pA/oc. These parameters vary
randomly with temperature. i.e. they may be positive in
one temperature range and negative in another

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Input bias current drift

100

80
Ib in
nA 60
40
TA ambient temp.
20
in oC

-55
-25 0 25 50 75

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Input Offset current drift

It is defined as the average rate of change of input offset

current per unit change in temperature

Iios
Thermal drift in input offset current =
T

It is measured in nA/oC or pA/oc. These parameters vary randomly with

temperature. i.e. they may be positive in one temperature range and negative in
another

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Input Offset current Drift

2 Slope can be of
either polarities
Iios in
nA 1

0
-1

-2
TA , ambient
temp in oc
-55
-25 0 25 50 75

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AC
Characteristics
Frequency Response
Ideally, an op-amp should have an infinite bandwidth but practically op-
amp gain decreases at higher frequencies. Such a gain reduction
with respect to frequency is called as roll off.

The plot showing the variations in magnitude and phase

angle of the gain due to the change in frequency is called
frequency response of the op-amp

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When the gain in decibels, phase angle in degrees are

plotted against logarithmic scale of frequency, the plot is
called Bode Plot

The manner in which the gain of the op-amp changes with

variation in frequency is known as the magnitude plot.

The manner in which the phase shift changes with variation

in frequency is known as the phase-angle plot.

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Obtaining the frequency

response
To obtain the frequency response , consider the high frequency model
of the op-amp with capacitor C at the output, taking into account the
capacitive effect present
Where
AOL
AOL ( f ) = AOL(f) = open loop voltage gain as a
1+ j2fRoC function of frequency
AOL = Gain of the op-amp at 0Hz F =
AOL
AOL ( f ) = operating frequency
f)
1 + j( Fo = Break frequency or cutoff
fo frequency of op-amp

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For a given op-amp and selected value of C, the frequency fo is constant.

The above equation can be written in the polar form as

AOL
AOL ( f ) =
2
 f 
1+  
 fo 

 f 
AOL ( f ) = ( f ) = − tan   −1
 f0 

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Frequency Response of an op-amp

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The following observations can be made from the frequency response of an

op-amp
i)The open loop gain AOL is almost constant from 0 Hz to the break
frequency fo .
ii) At f=fo , the gain is 3dB down from its value at 0Hz . Hence the frequency

fo is also called as -3dB frequency. It is also know as corner frequency

iii) After f=fo , the gain AOL (f) decreases at a rate of 20 dB/decade or
6dB/octave. As the gain decreases, slope of the magnitude plot is -
20dB/decade or -6dB/octave, after f=fo .

iv)At a certain frequency, the gain reduces to 0dB. This means

20log|AOL | is
0dB i.e. |AOL | =1. Such a frequency is called gain cross-over frequency or
unity gain bandwidth (UGB). It is also called closed loop bandwidth.
UGB is the gain bandwidth product only if an op-amp has a single breakover
frequency, before AOL (f) dB is zero.
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For an op-amp with single break frequency

fo , after fo the gain bandwidth product is
constant equal to UGB
UGB=AOL fo
UGB is also called gain bandwidth product and denoted as ft Thus
ft is the product of gain of op-amp and bandwidth.

The break frequency is nothing but a corner frequency fo . Atthis

frequency, slope of the magnitude plot changes. The op-amp for
which there is only once change in the slope of the magnitude plot,
is called single break frequency op-amp.

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For a single break frequency we can also write

UGB= Af ff

Af = closed loop voltage gain Ff =

bandwidth with feedback

v) The phase angle of an op-amp with

single break frequency varies between 00 to 900 . The maximum possible
phase shift is -900 , i.e. output voltage lags input voltage by 900 when
phase shift is maximum
o= UGB /AOL
F
vi)At a corner frequency f=fo , the phase shift is -450.

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The modes of using an op-

amp
◼ Open Loop : (The output assumes one of the two
possible output states, that is +Vsat or – Vsat and the
amplifier acts as a switch only).

◼ Closed Loop: ( The utility of an op-amp can be greatly

increased by providing negative feed back. The output in
this case is not driven into saturation and the circuit
behaves in a linear manner).

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Open loop configuration of op-

amp

◼ The voltage transfer curve indicates the inability of op-

amp to work as a linear small signal amplifier in the open
loop mode

◼ Such an open loop behaviour of the op-amp finds some

rare applications like voltage comparator, zero crossing
detector etc.

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Open loop op-amp

configurations
◼ The configuration in which output depends on input, but output has
no effect on the input is called open loop configuration.

◼ No feed back from output to input is used in such configuration.

◼ The opamp works as high gain amplifier

◼ The op-amp can be used in three modes in open loop
configuration they are

1. Differential amplifier

2. Inverting amplifier

3. Non inverting amplifier

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Differential Amplifier

The amplifier which amplifies the difference between the two input
voltages is called differential amplifier.

V o= AOLVd = AOL (V1 −V2 ) = AOL (Vin1 −Vin 2 )

Key point: For very small Vd , output gets driven into saturation due to high AOL ,
hence this application is applicable for very small range of differential input
voltage.
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Inverting Amplifier

The amplifier in which the output is inverted i.e. having 180o

phase shift with respect to the input is called an inverting
amplifier

Vo = -AOL Vin2

Keypoint: The negative sign indicates that there is phase shift of 180o between
input and output i.e. output is inverted with respect to input.

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Non-inverting Amplifier

The amplifier in which the output is amplified without any

phase shift in between input and output is called non
inverting amplifier

Vo =AOL Vin1

Keypoint: The positive output shows that input and output are in phase and
input is amplified AOL times to get the output.

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Why op-amp is generally not used in

open loop
mode?
As open loop gain of op-amp is very large, very small input
voltage drives the op-amp voltage to the saturation level.
Thus in open loop configuration, the output is at its
positive saturation voltage (+Vsat ) or negative saturation
voltage (-Vsat ) depending on which input V1 or V2 is more
than the other. For a.c. input voltages, output may
switch between positive and negative saturation voltages

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This indicates the inability of op-amp to work as a linear small signal

amplifier in the open loop mode. Hence the op-amp in open loop
configuration is not used for the linear applications
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General purpose op-amp

741
The IC 741 is high performance monolithic op-amp IC. It is
available in 8pin, 10pin or 14pin configuration. It can
operate over a temperature of -550 C to 1250 C.

Features:
i) No frequency compensation required
ii) Short circuit protection provided
iii) Offset Voltage null capability
iv) Large common mode and differential voltage range
v) No latch up

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Internal schematic of 741 op-amp

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The 8pin DIP package of IC 741

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Realistic simplifying assumptions

◼ Zero input current: The current drawn by either of the

input terminals (inverting and non-inverting) is zero

◼ Virtual ground :This means the differential input voltage

Vd between the non-inverting and inverting terminals is
essentially zero. (The voltage at the non inverting input
terminal of an op-amp can be realistically assumed to be
equal to the voltage at the inverting input terminal

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Closed loop operation of op-

amp:

The utility of the op-amp can be increased considerably by

operating in closed loop mode. The closed loop
operation is possible with the help of feedback. The
feedback allows to feed some part of the output back to
the input terminals. In the linear applications, the op-
amp is always used with negative feedback. The
negative feedback helps in controlling gain, which
otherwise drives the op-amp out of its linear range, even
for a small noise voltage at the input terminals
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Unit - II

 Applications of OP-Amp

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Ideal Inverting Amplifier

1. The output is inverted with respect to input, which is indicated by minus
sign.
2. The voltage gain is independent of open loop gain of the op-amp, which is
assumed to be large.

3. The voltage gain depends on the ratio of the two resistances.

Hence selecting Rf and R1 , the required value of gain can be easily
obtained.

4. If Rf > R1,, the gain is greater than 1 If Rf < R1,, the gain is less than 1

If Rf = R1, the gain is unity

Thus the output voltage can be greater than, less than or equal to the input
voltage in magnitude
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5. If the ratio of Rf and R1 is K which is other than one, the

circuit is called scale changer while for Rf/R1 =1 it is called
phase inverter.

6. The closed loop gain is denoted as AVF or ACL i.e. gain with feedback

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Ideal Non-inverting Amplifier

1. The voltage gain is always greater than one

2. The voltage gain is positive indicating that for a.c. input, the output
and input are in phase while for d.c. input, the output polarity is
same as that of input
3. The voltage gain is independent of open loop gain of op-amp, but
depends only on the two resistance values
4. The desired voltage gain can be obtained by selecting proper
values of Rf and R1

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Comparison of the ideal inverting and

non- inverting op-amp
Ideal Inverting amplifier Ideal non-inverting amplifier

1. Voltage gain=-Rf/R1 1. Voltage gain=1+Rf/R1

2. The output is inverted with 2. No phase shift between input

respect to input and output

3. The voltage gain can be 3. The voltage gain is always

adjusted as greater than, equal to greater than one
or less than one

4. The input impedance is R1 4. The input impedance is very

large
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Practical Inverting Amplifier

AOL R f
Closed Loop Voltage gain = ACL = −
R1 + R f + R1 AOL

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Practical Non-Inverting Amplifier

ACL A (R + R )
Closed Loop Voltage gain = = OL 1 f

R1 + R f + R1AOL

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Instrumentation Amplifier

In a number of industrial and consumer

applications, the measurement of physical quantities
is usually done with the help of transducers. The output
of transducer has to be amplified So that it can
drive the indicator or display system. This function is
performed by an instrumentation amplifier

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Sample Ans Hold Circuit

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Definition: The Sample and Hold circui t is an electronic circuit which

creates the samples of voltage given to it as input, and after that, it
holds these samples for the definite time. The time during
which sample and hold circuit generates the sample of the input
signal is called sampling time.

▪ Sample and Hold Circuit takes samples from the analog input
signal and hold them for particular period of time and then
outputs the sampled part of input signal. This circuit is only useful
for sampling few microseconds of input signal. A Sample and
Hold circuit consist of switching devices, capacitor and an
operational amplifier.

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Log and Antilog Amplifer

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 A logarithmic amplifier, or a log amplifier, is an electronic

circuit that produces an output that is proportional to the
logarithm of the applied input. This section discusses about
the op-amp based logarithmic amplifier in detail.
 In the antilog amplifier, the input signal is at the inverting
pin of the operational amplifier, which passes through a
diode. As observed in the circuit shown above, the negative
feedback is achieved by connecting the output to the
inverting input terminal.

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Instrumentation Amplifier

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Features of instrumentation amplifier

1. high gain accuracy
2. high CMRR
3. high gain stability with low temperature co-
efficient
4. low dc offset
5. low output impedance

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AC AMPLIFIER

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Differentiator

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Integrato
r

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Differential amplifier
This circuit amplifies only the difference between
the two inputs. In this circuit there are two
resistors labeled R IN Which means that their
values are equal. The differential amplifier
amplifies the difference of two inputs while the
differentiator amplifies the slope of an input

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Summer

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Comparat
or
A comparator is a circuit which compares
a signal voltage applied at one input of an
op- amp with a known reference voltage at
the other input. It is an open loop op - amp
with output + Vsat

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Comparat
or

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Applications of
comparator
1. Zero crossing detector
2. Window detector
3. Time marker generator
4. Phase detector

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Schmitt trigger

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Multivibrator Circuit:

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Triangle Square Wave generator:

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UNIT –III

◼ Active filters
◼ Timer and phase locked loops

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Filter
Filter is a frequency selective circuit that passes
signal of specified Band of frequencies and attenuates
the signals of frequencies outside the band

Type of Filter

1. Passive filters
2. Active filters

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Passive filters
Passive filters works well for high frequencies.
But at audio frequencies, the inductors become
problematic, as they become large, heavy and
expensive.For low frequency applications, more number
of turns of wire must be used which in turn adds to the
series resistance degrading inductor’s performance ie,
low Q, resulting in high power dissipation

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Active filters

Active filters used op- amp as the active

element and resistors and capacitors as passive
elements. By enclosing a capacitor in the feed back loop
, inductor less active filters can be obtained

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some commonly used active

filters
1. Low pass filter
2. High pass filter
3. Band pass filter
4. Band reject filter
5. All pass filter

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Active Filters

◼ Active filters use op-amp(s) and RC components.

◼ Advantages over passive filters:
 op-amp(s) provide gain and overcome circuit losses
 increase input impedance to minimize circuit loading
 higher output power
 sharp cutoff characteristics can be produced simply
and efficiently without bulky inductors
◼ Single-chip universal filters (e.g. switched-capacitor
ones) are available that can be configured for any type of
filter or response.

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Review of Filter Types & Responses

◼ 4 major types of filters: low-pass, high-pass, band pass,

and band-reject or band-stop
◼ 0 dB attenuation in the passband (usually)
◼3 dB attenuation at the critical or cutoff frequency, fc (for
Butterworth filter)
◼ Roll-off at 20 dB/dec (or 6 dB/oct) per pole outside
the passband (# of poles = # of reactive elements).
Attenuation at any frequency, f, is:
 
atten.(dB) at f = log f x atten.(dB) at f
 fc 
dec

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Review of Filters (cont’d)

◼ Bandwidth of a filter: BW = fcu - fcl

◼ Phase shift: 45o/pole at fc; 90o/pole at >> fc
◼ 4 types of filter responses are commonly used:
 Butterworth - maximally flat in passband; highly non-
linear phase response with frequecny
 Bessel - gentle roll-off; linear phase shift with freq.
 Chebyshev - steep initial roll-off with ripples in
passband
 Cauer (or elliptic) - steepest roll-off of the four types
but has ripples in the passband and in the stopband

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Frequency Response of Filters

A(dB) A(dB) A(dB)
LPF HPF BPF

Pass-
band
f f f
fc fc fcl fcu
A(dB) A(dB)
Butterworth
BRF
Chebyshev
Bessel
f
fcl fcu f

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Unity-Gain Low-Pass Filter Circuits

2-pole 3-pole

4-pole

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Design Procedure for Unity-Gain LPF

 Determine/select number of poles required.

 Calculate the frequency scaling constant, Kf = 2f
 Divide normalized C values (from table) by Kf to obtain
frequency-scaled C values.
 Select a desired value for one of the frequency-
scaled Cvalues and calculate the impedance scaling
factor: = frequency − scaled C value
Kx
desired C value
 Divide all frequency-scaled C values by
Kx
 Set R = Kx 
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An
Example
Design a unity-gain LP Butterworth filter with a critical
frequency of 5 kHz and an attenuation of at least 38 dB
at 15 kHz.
The attenuation at 15 kHz is 38 dB
 the attenuation at 1 decade (50 kHz) = 79.64 dB.
We require a filter with a roll-off of at least 4 poles.
Kf = 31,416 rad/s. Let’s pick C1 = 0.01 F (or 10
nF).Then C2 = 8.54 nF, C3 = 24.15 nF, and C4 = 3.53 nF.
Pick standard values of 8.2 nF, 22 nF, and 3.3 nF. Kx =
3,444
Make all R = 3.6 k (standard value)

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Unity-Gain High-Pass Filter Circuits

2-pole 3-pole

4-pole

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Design Procedure for Unity-Gain HPF

◼ The same procedure as for LP filters is used except for

step #3, the normalized C value of 1 F is divided by Kf.
Then pick a desired value for C, such as 0.001 F to 0.1
F, to calculate Kx. (Note that all capacitors have the
same value).
◼ For step #6, multiply all normalized R values (from table)
by Kx.
E.g. Design a unity-gain Butterworth HPF with a critical
frequency of 1 kHz, and a roll-off of 55 dB/dec. (Ans.: C
= 0.01 F, R1 = 4.49 k, R2 = 11.43 k, R3 = 78.64 k.;
pick standard values of 4.3 k, 11 k, and 75 k).

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Equal-Component Filter Design

2-pole LPF 2-pole HPF

Same value R & same value C Av for # of poles is given in
are used in a table and
filter. is the same for
Select C A = RF +1LP and HP
(e.g. 0.01 F), then: filter devsign.
RI
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Exampl
e
Design an equal-component LPF with a critical
frequency of 3 kHz and a roll-off of 20 dB/oct.

Minimum # of poles = 4
Choose C = 0.01 F;  R = 5.3 k
From table, Av1 = 1.1523, and Av2 = 2.2346.
Choose RI1 = RI2 = 10 k; then RF1 = 1.5 k, and
RF2 =
12.3 k .
Select standard values: 5.1 k, 1.5 k, and 12 k.
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Bandpass and Band-Rejection Filter

Attenuation (dB)

Attenuation (dB)
BPF BRF

f f
fcl fctr fcu fcl fctr fcu
The quality factor, Q, of a filter is given by: f
Q = ctr
where BW = fcu - fcl and BW
fctr = fcu fcl

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More On Bandpass Filter

If BW and f are given, then:
A broadbandcentre
BPF can be obtained by combining a LPF and

a HPF: BW 2 BW BW 2 BW
fcl = + f ctr2 − ; fcu = + f ctr2 +
4 2 4 2

> 1.
The Q of this filter is usually

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Broadband Band-Reject
Filter
A LPF and a HPF can also be combined to give abroadband
BRF:

2-pole band-reject filter

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Narrow-band Bandpass Filter

BW = fctr = 1
Q
C1 = C2 = C2 R1
R2 = 2 CR1
R1
R3 =
2Q2 −1

R3 can be adjusted or trimmed

1 1+ R1
fctr = to change f ctrwithout affecting
2 R3 the BW. Note that
2 R1 Q < 1.
C
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Narrow-band Band-Reject
Filter
Easily obtained by combining the inverting output of a
narrow-band BRF and the original signal:

The equations for R1, R2, R3, C1, and C2 are the same as before.
RI = RF for unity gain and is often chosen to be >> R1.
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TRIANGULAR WAVE
GENERATOR

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555 IC
The 555 timer is an integrated circuit
specifically designed to perform signal
generation and timing functions.

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Features of 555 Timer Basic blocks

1. It has two basic operating modes: monostable

and astable
2. It is available in three packages. 8 pin metal can ,
8 pin dip, 14 pin dip.
3. It has very high temperature stability

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Applications of 555 Timer

1. astable multivibrator
.
2. monostable multivibrator
3. Missing pulse detector
4. Linear ramp generator
5. Frequency divider
6. Pulse width modulation
7. FSK generator
8. Pulse position modulator
9. Schmitt trigger

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Astable multivibrator

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Astable multivibrator

. When the voltage on the capacitor

reaches (2/3)Vcc, a switch is closed at pin 7 and the
capacitor is discharged to (1/3)Vcc, at which time the
switch is opened and the cycle starts over

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Monostable multivibrator

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Voltage controlled
oscillator
A voltage controlled oscillator is an
oscillator circuit in which the frequency of
oscillations can be controlled by an externally
applied voltage

The features of 566 VCO

1. Wide supply voltage range(10- 24V)

2. Very linear modulation characteristics
3. High temperature stability

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Monolithic pll Ic:

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Advantages of Monolith:

 The Advantages of using monoliths Monolithic

applications are a natural way for an application to evolve.
Most applications start out with a single objective or a
small number of related objectives. Over time, features are
added to the application to support business needs.
• It is generally used in multimedia, communication and in
many other applications. There are two different types of
PLL’s – linear and nonlinear. The nonlinear is difficult and
complicated to design in the real world, but the linear
control theory is well modeled in analog PLL’s.

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UNIT - IV

◼ DATA CONVERTETRS
◼ VOLTAGE CONVERTS

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Classification of ADCs
1. Direct type ADC.
2. Integrating type ADC

Direct type ADCs

1. Flash (comparator) type converter
2. Counter type converter
3. Tracking or servo converter.
4. Successive approximation
type converter

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Integrating type
converters
An ADC converter that perform conversion
in an indirect manner by first changing the
analog I/P signal to a linear function of time or
frequency and then to a digital code is known as
integrating type A/D converter

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Weighted Resistor DAC:

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R-2R Ladder DAC:

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Inverted R-2R Ladder DAC:

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Parral type comparator:

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Successive Approximation:

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ADC and Dual slope DAC:

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Counter type ADC:

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INTRODUCTION TO VOLTAGE
REGULATORS

◼ A voltage regulator is designed to

automatically maintain a constant voltage
level. A voltage regulator may be a simple
"feed-forward" design or may include
negative feedback control loops. It may use
an electromechanical mechanism, or
electronic components.

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IC Voltage Regulators:

◼ There are basically two kinds of IC voltage

regulators:
 Multipin type, e.g. LM723C
 3-pin type, e.g. 78/79XX
◼ Multipin regulators are less popular but they provide
the greatest flexibility and produce the highest
quality voltage regulation
◼ 3-pin types make regulator circuit design simple

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Multipin IC Voltage
Regulator
◼ The LM723 has an
equivalent circuit that
contains most of the parts
of the op-amp voltage
regulator discussed
earlier.
◼ It has an internal voltage
reference, error amplifier,
pass transistor, and
current limiter all in one
IC package.
LM 723C Schematic
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LM723 Voltage
Regulator
◼ Can be either 14-pin DIP or 10-pin TO-100 can
◼ May be used for either +ve or -ve, variable or fixed
regulated voltage output
◼ Using the internal reference (7.15 V), it can operate as a
high-voltage regulator with output from 7.15 V to about
37 V, or as a low-voltage regulator from 2 V to 7.15 V
◼ Max. output current with heat sink is 150 mA
◼ Dropout voltage is 3 V (i.e. VCC > Vo(max) + 3)

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LM723 in High-Voltage
Configuration
Design equations:
V (R + R )
Vo = ref 1 2

R2

R3 =
R1R2 Rsens = 0.7
R1 + R2 I max
Choose R1 + R2 = 10
k,
External pass transistor and and Cc = 100 pF.
current sensing added. To make Vo variable,
replace R1 with a pot.
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LM723 in Low-Voltage
Configuration
I L(max) = R 4 Vo + 0.7(R 4 + R 5 )
R 5 R sen s

I sho rt
= 0.7(R + R ) 4 5

RR 5 sen s

0.7Vo
R sens =
I short (Vo + 0.7) − 0.7I L(max)

With external pass transistor Under foldback condition:

and foldback current limiting
Vo ' = 0.7R L (R 4 + R 5 )
V =
RV 2 ref
R 5 R sens − R 4R L
R +R
o
1 2

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Three-Terminal Fixed Voltage Regulators

◼ Less flexible, but simple to use

◼ Come in standard TO-3 (20 W) or TO-220 (15 W)
transistor packages
◼78/79XX series regulators are commonly available with
5, 6, 8, 12, 15, 18, or 24 V output
◼ Max. output current with heat sink is 1 A
◼ Built-in thermal shutdown protection
◼ 3-V dropout voltage; max. input of 37 V
◼Regulators with lower dropout, higher in/output, and
better regulation are available.

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Basic Circuits With 78/79XX Regulators

◼ Both the 78XX and 79XX regulators can be used to

provide +ve or -ve output voltages
◼ C1 and C2 are generally optional. C1 is used to cancel
any inductance present, and C2 improves the transient
response. If used, they should preferably be either 1 F
tantalum type or 0.1 F mica type capacitors.
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Dual-Polarity Output with

78/79XX
Regulators

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78XX Regulator with Pass Transistor

◼ Q1 starts to conduct when

VR2 = 0.7 V.
◼ R2 is typically chosen so
that max. IR2 is 0.1 A.
◼Power dissipation of Q1 is
P = (Vi - Vo)IL.
◼ Q2 is for current limiting
protection. It conducts
R1 = 0.7 R2 = 0.7 when VR1 = 0.7 V.
Imax I R2 ◼ Q2 must be able to pass
max. 1 A; but note that
max. VCE2 is only 1.4 V.
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78XX Floating Regulator

◼ It is used to obtain an
output > the Vreg
value up to a max.of
37 V.
◼ R1 is chosen so that
R1  0.1
Vreg/IQ, where I is
+   the
Vo = Vreg 
V 
+ I Q R2
reg

 R1 

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3-Terminal Variable
Regulator
◼ The floating regulator could be made into a variable
regulator by replacing R2 with a pot. However, there are
several disadvantages:
 Minimum output voltage is Vreg instead of 0 V.
 IQ is relatively large and varies from chip to chip.
Power dissipation in R2 can in some cases be quite
large resulting in bulky and expensive equipment.
◼ A variety of 3-terminal variable regulators are available,
e.g. LM317 (for +ve output) or LM 337 (for -ve output).

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Basic LM317 Variable Regulator Circuits

(a) (b)
Circuit with capacitors Circuit with protective
to improve performance diodes
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Notes on Basic LM317 Circuits

◼ The function of C1 and C2 is similar to those used in

the 78/79XX fixed regulators.
◼ C3 is used to improve ripple rejection.
◼Protective diodes in circuit (b) are required for high-
current/high-voltage applications.
+ V 
where Vref = 1.25 V, and Iadj is
Vo = Vref  ref + I adj  R2 the current flowing into the adj.
 R1  terminal (typically 50 A).
R (V −V )
R1 = Vref /IL(min), where I L(min) is
R2 = 1 o ref
Vref + IadjR1 typically 10 mA.

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LM317 Regulator Circuits

Circuit with pass transistor Circuit to give 0V min.

and current limiting output voltage

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UNIT-V

▪ Digital Logic families

▪ CMOS Logic
▪ Combinational circuits
▪ Sequnitional circuits

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Overview

• Integration, Moore’s law

• Early families (DL, RTL)
• TTL
• Evolution of TTL family
• ECL
• CMOS family and its evolution
• Overview

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Integration Levels
• Gate/transistor ratio is roughly 1/10
– SSI < 12 gates/chip
– MSI < 100 gates/chip
– LSI …1K gates/chip
– VLSI …10K gates/chip
– ULSI …100K gates/chip
– GSI …1Meg gates/chip

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Moore’s law
• A prediction made by Moore (a co-founder of Intel) in
1965: “… a number of transistors to double every 2
years.”

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In the beginning…
Diode Logic (DL)
•simplest; does not
scale =
•NOT not possible
(need an active
eRleesmisetnotr)-
Transistor Logic (RTL)
•replace diode switch
with a transistor switch
•can be cascaded =

•large power draw

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was…
Diode-Transistor Logic (DTL)
•essentially diode logic with transistor
amplification
•reduced power consumption
•faster than RTL

DL AND gate Saturating inverter

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Logic families: V levels

VOH(min) – The minimum voltage level at an output in the logical “1” state under
defined load conditions
VOL(max) – The maximum voltage level at an output in the logical “0” state under
defined load conditions
VIH(min) – The minimum voltage required at an input to be recognized as “1”
logical state
VIL(max) – The maximum voltage required at an input that still will be recognized
as “0” logical state

VOH VIH VOL VIL

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Logic families: I requirements

IOH – Current flowing into an output in the logical “1” state under specified load
conditions
IOL – Current flowing into an output in the logical “0” state under specified load
conditions
IIH – Current flowing into an input when a specified HI level is applied to that
input IIL – Current flowing into an input when a specified LO level is applied to
that input

IOH IIH IOL IIL

VOH VIH VOL VIL

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Logic families: fanout

Fanout: the maximum number of logic inputs (of the
same logic family) that an output can drive reliably

IOH ) IOL
DC fanout = min( ,
IIH IL I

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Logic families: propagation delay

TPD,HL TPD,LH

TPD,HL – input-to-output
propagation delay from HI
to LO output TPD,LH – input-
to-output propagation delay
from LO to HI output

Speed-power
product: TPD  Pavg
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Logic families: noise margin

HI state noise margin:
VNH = VOH(min) – VIH(min)

LO state noise margin:

VNL = VIL(max) – VOL(max)

Noise margin:
VN = min(VNH,VNL)
VNH

VNL

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TTL
Bipolar Transistor-Transistor Logic (TTL)
•first introduced by in 1964 (Texas Instruments)
•TTL has shaped digital technology in many ways
•Standard TTL family (e.g. 7400) is obsolete
•Newer TTL families still used (e.g. 74ALS00)

Distinct features
• Multi-emitter transistors
•Totem-pole transistor
arrangement
•Open LTspice example:
TTL NAND… 2-input NAND
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TTL evolution
Schottky series (74LS00) TTL
•A major slowdown factor in BJTs is due to
transistors going in/out of saturation
•Shottky diode has a lower forward bias (0.25V)
•When BC junction would become forward biased,
the Schottky diode bypasses the current
preventing the transistor from going into saturation

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TTL family evolution

Legacy: don’t use in Widely used today

new designs

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ECL
Emitter-Coupled Logic (ECL)
•PROS: Fastest logic family available (~1ns)
•CONS: low noise margin and high power
dissipation
•Operated in emitter coupled geometry (recall
differential amplifier or emitter-follower),
transistors are biased and operate near their Q-
point (never near saturation!)
• Logic levels. “0”: –1.7V. “1”: –0.8V
•Such strange logic levels require extra effort
when interfacing to TTL/CMOS logic families.
•Open LTspice example: ECL inverter…
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CMOS
Complimentary MOS (CMOS)
• Other variants: NMOS, PMOS (obsolete)
• Very low static power consumption
• Scaling capabilities (large integration all MOS)
• Full swing: rail-to-rail output
• Things to watch out for:
– don’t leave inputs floating (in TTL these will
float
to HI, in CMOS you get undefined behaviour)
–susceptible to electrostatic damage (finger of
death)

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Life-cycle

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Combinational
Circuits

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Outline

◼ Boolean Algebra
◼ Decoder
◼ Encoder
◼ MUX

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History: Computer and

the Rationalist

◼ Modern research issues in AI are formed and

evolve through a combination of historical,
social and cultural pressures.
◼ The rationalist tradition had an early
proponent in Plato, and was continued on
through the writings of Pascal, Descates, and
Liebniz
◼ For the rationalist, the external world is
reconstructed through the clear and distinct
ideas of a mathematics

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History: Development of
Formal Logic

◼ The goal of creating a formal language for

thought also appears in the work of George
Boole, another 19th century mathematician
whose work must be included in the roots of AI
◼ The importance of Boole’s accomplishment is in
the extraordinary power and simplicity of the
system he devised: Three Operations

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Three Operations

◼ three basic Boolean operations can be

defined arithmetically as follows.
 x‫ר‬y=xy
 x‫ש‬y=x + y − xy
¬x=1 − x

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Boolean function and logic

diagram

• Boolean algebra: Deals with binary

variables and logic operations operating
on those variables.

• Logic diagram: Composed of graphic

symbols for logic gates. A simple circuit
sketch that represents inputs and outputs
of Boolean functions.

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Basic Identities of Boolean Algebra

(1) x + 0 =x
(2) x ·0=0
(3) x + 1 =1
(4) x·1=1
(5) x + x = x
(6) x · x = x
(7)x + x’ = x
(8) x · x’ =0
(9) x + y = y + x
(10)xy = yx
(11) x + ( y + z ) = ( x + y ) + z
(12)x (yz) = (xy) z
(13)x ( y + z ) = xy + xz
(14) x + yz = ( x + y )( x + z)
(15) ( x + y )’ = x’y’
(16) ( xy )’ = x’ + y’
(17) (x’)’ = x

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Gate
s
◼ Refer to the hardware to implement Boolean operators.

◼ The most basic gates are

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Boolean function and truth

table

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Outline

◼ Boolean Algebra
◼ Decoder
◼ Encoder
◼ MUX

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Decod
er
 Accepts a value and decodes it
◼ Output corresponds to value of n inputs

 Consists of:
◼ Inputs (n)
◼ Outputs (2n , numbered from 0 → 2n -1)

◼ Selectors / Enable (active high or active low)

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The truth table of 2-to-4

Decoder

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2-to-4
Decoder

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2-to-4
Decoder

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The truth table of 3-to-8

Decoder
A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1
0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1
1 1 0 1

1 1 1 1

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3-to-8
Decoder

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3-to-8 Decoder with

Enable

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Decoder
Expansion
◼ Decoder expansion
 Combine two or more small decoders with
enable inputs to form a larger decoder

 3-to-8-line decoder constructed from two 2-to-

4- line decoders
◼ The MSB is connected to the enable inputs
◼ if A2=0, upper is enabled; if A2=1, lower is
enabled.

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Decoder
Expansion

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Combining two 2-4 decoders to form

one 3-8 decoder using enable switch
es

The highest bit is used for the enabl

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How about 4-16

decoder
◼ Use how many 3-8 decoder?
◼ Use how many 2-4 decoder?

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Outline

◼ Boolean Algebra
◼ Decoder
◼ Encoder
◼ Mux

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Encoders

◼ Perform the inverse operation of a

decoder
 2n (or less) input lines and n output lines

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Encoders

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Encoders with OR gates

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Encoders

◼ Perform the inverse operation of a decoder

 2n (or less) input lines and n output lines

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Priority Encoder

 Accepts multiple values and encodes them

◼ Works when more than one input is active

 Consists of:
◼ Inputs (2n)

◼ Outputs
 when more than one output is active, sets
output to correspond to highest input
 V (indicates whether any of the inputs are
active)
◼ Selectors / Enable (active high or active low)

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D3 D2 D1 D0 A1 A0 V
0 0 0 0 x X 0
0 0 0 1 0 0 1
0 0 1 0 0 1 1
0 0 1 1 0 1 1
0 1 0 0 1 0 1
0 1 0 1 1 0 1
0 1 1 0 1 0 1
0 1 1 1 1 0 1
1 0 0 0 1 1 1
1 0 0 1 1 1 1
1 0 1 0 1 1 1
1 0 1 1 1 1 1
1 1 0 0 1 1 1
1 1 0 1 1 1 1
1 1 1 0 1 1 1
1 1 1 1 1 1 1

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Priority Encoder

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Outline

◼ Boolean Algebra
◼ Decoder
◼ Encoder
◼ Mux

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Multiplexer (MUX)

A multiplexer can use addressing bits to

select one of several input bits to be the
output.

A selector chooses a single data input and

passes it to the MUX output
 It has one output selected at a time.

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Function table with enable

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4 to 1 line multiplexer

4 to 1 line
multiplexer
S1 S0 F
2n MUX to 1 0 0 I0
n for this MUX is 2 0 1 I1
1 0 I2
This means 2 1 1 I3
selection lines s 0
and s1
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Multiplexer (MUX)

 Consists of:
◼ Inputs (multiple) = 2n
◼ Output (single)

◼ Selectors (# depends on # of inputs) = n

◼ Enable (active high or active low)

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Multiplexers versus decoders

•A Multiplexer uses n binary select bits to choose from a

maximum of 2n unique input lines.

•Decoders have 2^n number of output lines while

multiplexers have only one output line.

•The output of the multiplexer is the data input whose index is

specified by the n bit code.

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Multiplexer Versus Decoder

I3

I2

I1

I
0
S1

S
0 2-to-4 Decoder
4-to-1 Multiplexer
Note that the multiplexer has an extra OR gate.A1 andA0 are the two inputs
in decoder. There are four inputs plus two selecs in multiplexer.
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Cascading multiplexers
Using three 2-1 MUX
to make one 4-1 MUX

S1 S0 F
0 0 I0
0 1 I1
1 0 I2
1 1 I3

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Example: Construct an
8-to-1 multiplexer using I0
2-to-1 multiplexers. I1

S2 S1 S0 F
I2
0 0 0 I0
I3
2-1
F
0 0 1 I1 MUX

0 1 0 I2
S E

I4
0 1 1 I3 S2 E

I5
1 0 0 I4
1 0 1 I5
1 1 0 I6
I6
1 1 1 I7 I7

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Example : Construct 8-to-1 multiplexer using one 2-to-1 multiplexer and

two 4-to-1 multiplexers

S2 S1 S0 X
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

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Quadruple 2-to-1 Line Multiplexer

Used to supply four bits to the

output. In this case two inputs four
bits each.
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Quadruple 2-to-1 Line

Multiplexer

E S Y
(Enable) (Select) (Output)
0 X All 0’s

1 0 A

1 1 B

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UNIT-5
Sequential Circuits

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Combinational
Logic

◼ Combinational Logic:
 Outputdepends only on current input
 Has no memory

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Sequential Logic

◼ Sequential Logic:
 Output depends not only on current input but
also on past input values, e.g., design a
counter
Need some type of memory to remember the
past input values

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Sequential Circuits

Circuits that we Information Storing

have learned Circuits
so far

Timed “States”

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Sequential Logic:
Concept

◼ Sequential Logic circuits remember past

inputs and past circuit state.
◼Outputs from the system are
“fed back” as new inputs
 With gate delay and wire delay
◼ The storage elements are circuits that are
capable of storing binary information:
memory.
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Synchronous vs. Asynchronous

There are two types of sequential circuits:

◼Synchronous sequential circuit: circuit output
changes only at some discrete instants of time.
This type of circuits achieves synchronization by
using a timing signal called the clock.
◼Asynchronous sequential circuit: circuit output
can change at any time (clockless).

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Clock
Period
F F
F Combinational F
Circuit

F
F

Smallest clock period = largest combinational

circuit delay between any two directly
connected FF, subjected to impact of FF
setup time.

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SR Latch (NAND version)

0 S’ S’ R’ Q Q’
Q 1
0 0
0 1 1 0 Set
1 0
Q’ 0
1 R’ 1 1

X Y NAND
00 1
01 1
10 1
11 0

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SR Latch (NAND version)

1 S’ S’ R’ Q Q’
Q 1
0 0
0 1 1 0 Set
1 0
Q’ 0
1 R’ 1 1 1 0 Hold

X Y NAND
00 1
01 1
10 1
11 0

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SR Latch (NAND version)

1 S’ S’ R’ Q Q’
Q 0
0 0
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
0 R’ 1 1 1 0 Hold

X Y NAND
00 1
01 1
10 1
11 0

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SR Latch (NAND version)

1 S’ S’ R’ Q Q’
Q 0
0 0
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
1 R’ 1 1 1 0 Hold
0 1 Hold
X Y NAND
00 1
01 1
10 1
11 0

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SR Latch (NAND version)

0 S’ S’ R’ Q Q’
Q 1
0 0 1 1 Disallowed
0 1 1 0 Set
1 0 1 1 Reset
Q’ 1
0 R’ 1 1 2 0 Hold
0 1 Hold
X Y NAND
00 1
01 1
10 1
11 0

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D Latch
◼One way to eliminate the undesirable
indeterminate state in the RS flip flop is to
ensure that inputs S and R are never 1
simultaneously. This is done in the D latch:

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D Latch with Transmission Gates

PJF - 235 2015/7/4 Sequential Circuits

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Flip-Flops

◼ Latches are “transparent” (= any change

on the inputs is seen at the outputs
immediately when C=1).
◼ This causes synchronization problems.
◼ Solution: use latches to create flip-flops
that can respond (update) only on specific
times (instead of any time).
◼ Types: RS flip-flop and D flip-flop
PJF - 236 2015/7/4 Sequential Circuits
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D Flip-Flop

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Characteristic Tables

◼ Defines the logical properties of a flip-flop

(such as a truth table does for a logic gate).
◼ Q(t) – present state at time t
◼ Q(t+1) – next state at time t+1

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D Flip-Flop Timing Parameters

Setup time

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Shift register:

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Sequential Circuit Analysis

◼ Analysis: Consists of obtaining a suitable description

that demonstrates the time sequence of inputs, outputs,
and states.
◼ Logic diagram: Boolean gates, flip-flops (of any kind),
and appropriate interconnections.
◼ The logic diagram is derived from any of the following:
 Boolean Equations (FF-Inputs, Outputs)
 State Table
 State Diagram

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Example

◼ Input: x(t) Function?

x
◼ Output: y(t) D Q A

◼ State: (A(t), B(t)) C Q A

◼ What is the Output

D Q B
◼ What is the Next State
Function? CP C Q

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Example (continued)
◼ Boolean equations
for the functions: x
D Q A
 A(t+1) = A(t)x(t) A’
C Q
+ B(t)x(t) Next State

 B(t+1) = A’(t)x(t)
 y(t) = x’(t)(B(t) + A(t)) D Q B

CP C Q'

Output

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State Table Characteristics

◼State table – a multiple variable table with the
following four sections:
 Present State – the values of the state variables for each
allowed state.
 Input – the input combinations allowed.
 Next-state – the value of the state at time (t+1) based on the
present state and the input.
 Output – the value of the output as a function of the present
state and (sometimes) the input.
◼ From the viewpoint of a truth table:
 the inputs are Input, Present State
 and the outputs are Output, Next State

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State
Diagrams
◼ The sequential circuit function can be represented in
graphical form as a state diagram with the following
components:
 A circle with the state name in it for each state
 A directed arc from the Present State to the Next State for each
state transition
 A label on each directed arc with the Input values which causes
the state transition, and
 A label:
◼ On each circle with the output value produced, or
◼ On each directed arc with the output value produced.

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Example: State
Diagram
s,x=0/y=0 x=0/y=1 x=1/y=0
◼ Diagram gets
confusing for AB
large circuits 00 x=0/y=1 1 0
◼ For small circuit x=1/y=0
usually easier to x=1/y=0
understand than x=0/y=1
the state table
01 11
x=1/y=0

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MEMORY

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Memory

◼ Sequential circuits all depend upon the presence of memory.

 A flip-flop can store one bit of information.
 A register can store a single “word,” typically 32 or 64 bits.

◼ Memory allows us to store even larger amounts of data.

 Read Only Memory (ROM)
 Random Access Memory (RAM)
◼ Static RAM (SRAM)

◼ Dynamic RAM (DRAM)

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Address Data
Picture of Memory 00000000
00000001
◼You can think of memory as being one big array of
0000000
data. 2
 The address serves as an array index. .
 Each address refers to one word of data. .
.
◼ You can read or modify the data at any given
.
memory address, just like you can read or modify
.
the contents of an array at any given index.
.
.
. Word
.
.
FFFFFFF
D
FFFFFFFE
FFFFFFFF

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Memory Signal Types

◼ Memory signals fall into three groups
 Address bus - selects one of memory locations
 Data bus
◼ Read: the selected location’s stored data is put on the data bus

◼ Write (RAM): The data on the data bus is stored into the selected
location
 Control signals - specifies what the memory is to do
◼ Control signals are usually active low

◼ Most common signals are:

 CS: Chip Select; must be active to do anything

 OE: Output Enable; active to read data

 WR: Write; active to write data

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Memory Address, Location and size

 All bits in location are read/written together

 Cannot manipulate single bits in a location
◼ For k address signals, there are 2k locations in memory device
◼ Each location contains an n bit word
◼ Memory size is specified as
 #loc x bits per location
◼ 224 x 16 RAM - 224 = 16M words, each 16 bits long

◼ 24 address lines, 16 data lines

 #bits
◼ The total storage capacity is 224 x 16 = 228 bits

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Size matters!
◼ Memory sizes are usually specified in numbers of bytes (1 byte= 8 bits).
◼ The 228-bit memory on the previous page translates into:

228 bits / 8 bits per byte = 225 bytes

◼ With the abbreviations below, this is equivalent to 32 megabytes.

Prefix Base 2 Base 10

K Kilo 2 = 1,024
10
10 = 1,000
3

M Mega 220 = 1,048,576 106 = 1,000,000

G Giga 230 = 1,073,741,824 109 = 1,000,000,000

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Read-only memory (ROM)

2k x n ROM • Non-volatile
k – If un-powered, its content retains
ADRS Data n
Out
• Read-only
CS – normal operation cannot change
OE contents
• k-bit ADRS specifies the address or location to read from
• A Chip Select, CS, enables or disables the RAM
• An Output Enable, OE, turns on or off tri-state output buffers
• Data Out will be the n-bit value stored at ADRS

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ROM PROGRAMMING

 Programmed ROM (PROM): contents loaded at the factory

◼ hardwired - can’t be changed

◼ embedded mass-produced systems

 OTP (One Time Programmable): Programmed by user

 UVPROM: reusable, erased by UV light
 EEPROM: Electrically erasable; clears entire blocks with single
operation

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ROM Usage
◼ ROMs are useful for holding data that never changes.

 Arithmetic circuits might use tables to speed up computations of logarithms

or divisions.
Many computers use a ROM to store important programs that should not be
modified, such as the system BIOS.
 Application programs of embedded systems,PDAs, game machines, cell
phones, vending machines, etc., are stored in ROMs

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ROM Structure

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32Kx8 ROM

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Typical commercial EEPROMs

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Microprocessor EPROM
application

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ROM Timing

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Memories and functions

Address Data
◼ ROMs are actually combinational devices, not A2A1 A0 V2V1V0
sequential ones! 000 000
001 100
 You can store arbitrary data into a ROM, so
010 110
the same address will always contain the 011 100
same data. 100 101
101 000
 You can think of a ROM as a combinational 110 011
circuit that takes an address as input, and 111 011

produces some data as the output.

◼ A ROM table is basically just a truth table.

 The table shows what data is stored at each
ROM address.
 You can generate that data combinationally,
using the address as the input.

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Logic-in-ROM Example

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Reading RAM
• 50 MHz CPU – 20 ns clock cycle time
• Memory access time= 65 ns
• Maximum time from the application of the address to the
appearance of the data at the Data Output

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WRITING RAM

2k x n memory
k ADDRESS DATA n
IN/OUT
RD/WR’
CS

 Enable the chip by setting CS = 1.

 Select the write operation, by setting RD/WR’ = 0.
 Send the desired address to the ADRS input.
 Send the word to store to the DATA IN/OUT.

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WRITING RAM

• 50 MHz CPU – 20 ns clock cycle time

• Write cycle time= 75 ns
• Maximum time from the application of the address to the
completion of all internal memory operations to store a word

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Static memory
◼ How can you implement the memory chip?
◼ There are many different kinds of RAM.
 We’ll start off discussing static memory, which is most commonly used in
caches and video cards.
 Later we mention a little about dynamic memory, which forms the bulk of a
computer’s main memory.
◼ Static memory is modeled using one latch for each bit of storage.

◼ Why use latches instead of flip flops?

 A latch can be made with only two NAND or two NOR gates, but a flip-
flop requires at least twice that much hardware.
 In general, smaller is faster, cheaper and requires less power.
 The tradeoff is that getting the timing exactly right is a pain.

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RAM Cell with SR Latch

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RAM Bit Slice Model

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8x2 RAM Using a 4x4 RAM Cell Array

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SRAM Devices

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Dynamic memory
◼ Dynamic memory is built with capacitors.
 A stored charge on the capacitor represents a logical 1.
 No charge represents a logic 0.

◼ However, capacitors lose their charge after a few milliseconds. The memory
requires constant refreshing to recharge the capacitors. (That’s what’s
“dynamic” about it.)

◼ Dynamic RAMs tend to be physically smaller than static RAMs.

 A single bit of data can be stored with just one capacitor and one
transistor, while static RAM cells typically require 4-6 transistors.
 This means dynamic RAM is cheaper and denser—more bits can be
stored in the same physical area.

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DRAM Cell

• DRAM cell: One transistor and one capacitor

• 1/0 = capacitor charged/discharged
• SRAM cell: Six transistors – Costs 3 times more (cell complexity)
• Cost per bit is less for DRAM – reason for why large memories are
DRAMs

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DRAM Bit Slice

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DRAM Including Refresh

Logic

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