Participant Guide AXI: Transactions

1 AXI: Transactions

Slide 21-1:
111740**slide

2020.1
111740!*note

This module describes the different types of AXI transactions.

After completing this module, you will be able to:
■ Identify the different types of AXI transactions

Slide 21-2:

Memory-Map AXI Channels

111741**slide

■ Read address
channel

■ Read data
channel

■ Write address
channel

■ Write data channel

■ Write response channel

— Non-posted write model: there will always be a write response

■ Other signals are present to indicate when the information on the

channel is valid, etc.
111741!*note

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The AXI interface has separate and independent read and write channels
that can be used simultaneously.
Each channel has its own address and data buses.
Both channels are non-posted; that is, there is always a response. In the
read case, the response is simply the read data coming back. For a write,
a separate response bus acknowledges data delivery.
Summary of the five AXI channels:
■ Read address channel
■ Read data channel
■ Write address channel
■ Write data channel
■ Write response channel
Slide 21-3:

AXI Interface: Handshaking

111742**slide

■ AXI uses a valid/ready

handshake acknowledge

■ Each channel has its own valid/ Inserting Wait States

ready
— Address (read/write)
— Data (read/write)
— Response (write only)

■ Flexible signaling functionality

— Inserting wait states Always Ready
— Always ready
— Same cycle acknowledge

Same Cycle Acknowledge

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111742!*note

It is up to the master to assert the valid signal and the slave to assert the
ready signals for all channels except the read data channel, where the
slave asserts valid to indicate that it is returning data.
The agent that asserts ready determines the flexibility as seen in the
three waveform options.
This ready/valid acknowledge protocol provides masters and slaves the
flexibility to pull wait states to prevent data overrun and starvation
situations.
Slide 21-4:

AXI Interface: Memory-Map Read

111743**slide

■ Two channels
— Address
— Data

■ Up to 256
transfer data AXI – Burst Read
phase

■ Selectable data
transfer size

■ See notes for

signal detail of
each channel
111743!*note

The AXI4 read interface allows for data phase transfer up to 256 beats as
opposed to 16 beats that were supported for AXI3. AXI-Lite has identical
timing except that there is no support for data bursts - that is, there is
only one beat.
Some signal features may not be required for all types of transfers,
depending on user requirements and capabilities.
Read Address Channel
■ ARID[3:0] – Master read address ID. This signal is the identification
tag for the read address group of signals.

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■ ARADDR[31:0] – Master read address. The read address bus gives the
initial address of a read burst transaction. Only the start address of the
burst is provided and the control signals that are issued alongside the
address detail how the address is calculated for the remaining
transfers in the burst.
■ ARLEN[7:0] – Master burst length. The burst length gives the exact
number of transfers in a burst. This information determines the
number of data transfers associated with the address.
■ ARSIZE[2:0] – Master burst size. This signal indicates the size of each
transfer in the burst.
■ ARBURST[1:0] – Master burst type. The burst type, coupled with the
size information, details how the address for each transfer within the
burst is calculated.
■ ARLOCK[1:0] – Master lock type. This signal provides additional
information about the atomic characteristics of the transfer.
■ ARCACHE[3:0] – Master cache type. This signal provides additional
information about the cacheable characteristics of the transfer.
■ ARPROT[2:0] – Master protection type. This signal provides protection
unit information for the transaction.
■ ARVALID – Master read address valid. This signal indicates, when
HIGH, that the read address and control information is valid and will
remain stable until the address acknowledge signal, ARREADY, is high.
1 = address and control information valid. 0 = address and control
information not valid.
■ ARREADY – Slave read address ready. This signal indicates that the
slave is ready to accept an address and associated control signals: 1 =
slave ready; 0 = slave not ready.
Read Data Channel
■ RID[3:0] – Slave read ID tag. This signal is the ID tag of the read data
group of signals. The RID value is generated by the slave and must
match the ARID value of the read transaction to which it is responding.
■ RDATA[31:0] – Slave read data. The read data bus can be 8, 16, 32,
64, 128, 256, 512, or 1024 bits wide (the PL limits this to a maximum
width of 256).
■ RRESP[1:0] – Slave read response. This signal indicates the status of
the read transfer. The allowable responses are OKAY, EXOKAY,
SLVERR, and DECERR.
■ RLAST – Slave read last. This signal indicates the last transfer in a
read burst.
■ RVALID – Slave read valid. This signal indicates that the required read
data is available and the read transfer can complete: 1 = read data
available; 0 = read data not available.

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 Participant Guide AXI: Transactions

■ RREADY – Master read ready. This signal indicates that the master can
accept the read data and response information: 1= master ready; 0 =
master not ready.
Slide 21-5:

AXI Interface: Memory-Map Write

111744**slide

■ Three channels
— Address
— Data
— Response

■ Up to 256 transfer
data phase
AXI – Burst Write
■ Selectable data
transfer size

■ See notes for signal

detail of each
channel
111744!*note

The AXI4 write interface allows for data phase transfer up to 256 beats as
opposed to 16 beats that were supported for AXI3. AXI-Lite has identical
timing except that there is no support for data bursts - that is, there is
only one beat.
Some signal features may not be required for all types of transfers,
depending on user requirements and capabilities.
Write Address Channel
■ AWID[3:0] – Master write address ID. This signal is the identification
tag for the write address group of signals.
■ AWADDR[31:0] – Master write address. The write address bus gives
the address of the first transfer in a write burst transaction. The
associated control signals are used to determine the addresses of the
remaining transfers in the burst.
■ AWLEN[3:0] – Master burst length. The burst length gives the exact
number of transfers in a burst. This information determines the
number of data transfers associated with the address.

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■ AWSIZE[2:0] – Master burst size. This signal indicates the size of each
transfer in the burst. Byte lane strobes indicate exactly which byte
lanes to update.

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Participant Guide AXI: Transactions

■ AWBURST[1:0] – Master burst type. The burst type, coupled with the
size information, details how the address for each transfer within the
burst is calculated.
■ AWLOCK[1:0] – Master lock type. This signal provides additional
information about the atomic characteristics of the transfer.
■ AWCACHE[3:0] – Master cache type. This signal indicates the
bufferable, cacheable, write-through, write-back, and allocate
attributes of the transaction.
■ AWPROT[2:0] – Master protection type. This signal indicates the
normal, privileged, or secure protection level of the transaction and
whether the transaction is a data access or an instruction access.
■ AWVALID – Master write address valid. This signal indicates that valid
write address and control information are available: 1 = address and
control information available; 0 = address and control information not
available. The address and control information remain stable until the
address acknowledge signal, AWREADY, goes HIGH.
■ AWREADY – Slave write address ready. This signal indicates that the
slave is ready to accept an address and associated control signals: 1 =
slave ready; 0 = slave not ready.
Write Data Channel
■ WID[3:0] – Master write ID tag. This signal is the ID tag of the write
data transfer. The WID value must match the AWID value of the write
transaction.
■ WDATA[31:0] – Master write data. The write data bus can be 8, 16,
32, 64, 128, 256, 512, or 1024 bits wide (the PL limits this to a
maximum width of 256).
■ WSTRB[3:0] – Master write strobes. This signal indicates which byte
lanes to update in memory. There is one write strobe for each eight
bits of the write data bus. Therefore, WSTRB[n] corresponds to
WDATA[(8 × n) + 7:(8 × n)].
■ WLAST – Master write last. This signal indicates the last transfer in a
write burst.
■ WVALID – Master write valid. This signal indicates that valid write data
and strobes are available: 1 = write data and strobes available; 0 =
write data and strobes not available.
■ WREADY – Slave write ready. This signal indicates that the slave can
accept the write data: 1 = slave ready; 0 = slave not ready.
Write Response Channel
■ BID[3:0] – Slave response ID. The identification tag of the write
response. The BID value must match the AWID value of the write
transaction to which the slave is responding.

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■ BRESP[1:0] – Slave write response. This signal indicates the status of

the write transaction. The allowable responses are OKAY, EXOKAY,
SLVERR, and DECERR.
■ BVALID – Slave write response valid. This signal indicates that a valid
write response is available: 1 = write response available; 0 = write
response not available.
■ BREADY – Master response ready. This signal indicates that the
master can accept the response information. 1 = master ready. 0 =
master not ready.
Slide 21-6:

AXI Interface: Streaming

111759**slide

■ Data moves in a single direction, from a master to a slave

— Simplex communication: master-to-slave
— Dual direction would be dual simplex; individual channels, for
example

■ Data only
— No address channel
— Minimum control
— Unlimited burst length
— Sideband signals optionally used to condition data
— Contents of data stream interpreted by slave

111759!*note

Data flowing across the streaming connection may be in packet format or

not. The handshaking signals may provide packet start/end information or
the data itself may contain special characters to mark the beginning and
end of a packet. The important point here is that both master and slave
must have prior knowledge of data format. Just to drive the point home,
the use of hardware signaling is optional and may be used if the designer
deems it necessary or useful, or it may be completely disregarded.

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AXI streaming does not have an address phase; all transactions go to the
same place. Also note that the direction is always from master to slave.
AXI streaming is very similar to the MicroBlaze™ processor fast simplex
link (FSL) except that there is no requirement that a processor be
involved.
Note that the AXI-Stream signals are less numerous than for AXI4 or AXI4-
Lite, as only a single channel is required. In many instances, not all of the
signals are required for a given application.

The following stream terms are used:

■ Transfer: A single transfer of data across an AXI4-Stream interface. A
single transfer is defined by a single TVALID, TREADY handshake.
■ Packet: A group of bytes that are transported together across an AXI4-
Stream interface. A packet is similar to an AXI4 burst. A packet can
consist of a single transfer or multiple transfers. Infrastructure
components can use packets to deal more efficiently with a stream in
packet-sized groups.
■ Frame: The highest level of byte grouping in an AXI4-Stream interface.
A frame contains an integer number of packets. A frame can be a very
large number of bytes; an entire video frame buffer, for example.
■ Data stream: The transport of data from one source to one
destination. A data stream can be:
— A series of individual byte transfers

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— A series of byte transfers grouped together in packets

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Slide 21-7:

AXI Interface: Streaming Write

111748**slide

■ Only write data

channel exists
— Side-band
signals are
indicated
when data is
valid and
when device is
ready

■ Other side-band
signals may be
used for other
needs
— As required by
the design
Thi
111748!*note

This example illustrates how TLAST might be used to indicate the type of
data being sent. Consider streaming data conveying a frame of
information (such as video or audio). How can the device know where the
frame begins or ends? Here, TLAST helps the receiving device determine
how to interpret the incoming data.
Consider a stream of single-channel sensor data that a device is
averaging and thresholding. In such a case, TLAST would not matter, as
all the data is treated the same and there is no start or finish to the
packet-less information.

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Capture Your Notes Here

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