Journal of Integrated Circuits and Systems, vol. 18, n.

2, 2023

Multiplexer Based Error Efficient Fixed-Width Adder Tree Design for Signal
Processing Applications
Rashmi Seethur1, Deeksha Sudarshan2, Vaibhavi Naik3, Tushar Masur4, and Shreedhar H K5
1,2,3,4
Rashmi Seethur, Deeksha Sudarshan, Vaibhavi Naik and Tushar Masur, Electronics and Communication Engineering
Department, PES University, Bangalore, India
5
Shreedhar H K, Electronics and Communication Engineering Department, GAT, Bangalore, India
Email: [email protected]

Abstract— In copious mixed media applications, humans cannot including logic, architecture, and algorithm [5]. The
necessarily discern error free or erroneous outputs, owing to the approximation computing paradigm is exclusive to a few
small range of perception abilities. Crucial information can still be hardware implementations of DSP blocks. Hardware, software,
obtained from marginally inexact outputs. Leveraging this, many and memory storage all fall under the umbrella of approximate
algorithms such as Digital Signal Processing (DSP), Discrete computing. Research on approximate hardware
Cosine Transform (DCT), Motion Compensation (MC) use implementations are mostly concentrated on arithmetic and
approximate calculations while still maintaining appreciable logic circuits. Since addition and multiplication are often
computation accuracy. When data processing algorithms are
carried out in microprocessors and digital signal processors,
taken into consideration, adders play an important role in the
adders and multipliers have drawn a lot of interest in the field
arithmetic module by managing the power and area utilization of
of approximate arithmetic circuits. This has led to an increased
the system. A fixed-width adder tree design for approximate
calculations is proposed, that uses the trade-off between area and usage of low-power and area-efficient methodologies. To
accuracy as the base for analysis. Our design uses 12.42%, 18.17% support this, signal processing systems are realized on fixed-
and 5.05% lesser area compared to the full width adder tree, FX- point VLSI applications. This paper talks about approximation
AT-PT and FX-AT-DT respectively. Additionally, when compared adders, which are created by inserting errors into an exact adder.
to FX-AT-DT, TFX-AT and ITFX-AT, the proposed design has an There are essentially two different types of approximate adders:
improved Maximum Error Distance (MED) of (33.33%, 29.03%), static approximate adders (SAAs) and dynamic approximate
(63.64%, 65.63%) and (38.46%, 35.29%) for N = 8, 16 respectively. adders (DAAs) as discussed in [2]. When compared to an
To cope with the inaccuracy caused by truncation, the proposed accurate adder, a SAA's fixed approximation feature ensures
design employs mux-based radix-4 addition coupled with bias certain savings in design metrics and may output either a correct
estimation. Further, to examine the error performance we have sum or an approximation with the desired precision in a single
incorporated the proposed design and a few other existing designs clock cycle. While a DAA may compute an exact or
into the Walsh-Hadamard Transform (WHT), to process images approximate total upon request using single or more clock
with different metrics and compare the Peak Signal to Noise Ratio cycles, approximation is changeable in a DAA. DAAs also
(PSNR) of the images. It was observed that the proposed design contain an additional Error Detection and Correction logic
showed significant improvement in the PSNR score when (EDCL) which in some cases proves to be an overhead and to
compared to ITFX-AT and maintains a score similar to that of FX-
by-pass this we can simply make use of the SAA. Typically, a
AT-PT.
SAA is divided into two sections: a precise section where
Index Terms - Full width, Fixed width, Adder Tree (AT),
addition is performed accurately, and an imprecise section
approximate AT where addition is performed incorrectly or inexactly. The exact
component receives more significant adder input bits, whereas
the imprecise section receives less important adder input bits.
I. INTRODUCTION The accurate portion therefore has more importance than the
imprecise portion. Using approximate adders, desired adder-
Artificial intelligence, big data analytics, data mining, machine tree structures can be designed for various applications. Adder-
learning, multimedia processing, cloud computing, Internet of trees are routinely used in matrix-vector multiplication and
Things, etc. are examples of exhaustive computation parallel designs of inner product computation. Implementing
technologies that routinely deal with a data flood, making approximate adder-tree designs in computation intensive
correct computing approaches expensive in terms of time and applications prove to be profitable as a significant decrease in
resources. In these situations, computation that produces metrics such as area, power and error performance can be
answers that are only roughly, inaccurately, or imprecisely right observed when compared to conventional or full-width adder-
might be more practical and cost-effective. For instance, in tree structures. Fixed-width adder-tree (AT) design is often
image processing applications minor deviation in the quality of derived from full-width adder-tree design by implementing
the image is not necessarily captured by the human eye [9]. This direct or post truncation. The full-width AT (FL-AT) generates
provides us with some latitude to do erroneous or a (w + p) bit output for N input vector, where N is the total
approximative calculations. This flexibility allows us to number of inputs, w is the number of bits for each input, and p
develop low-power systems at many design abstraction levels, = log2N, which determines the number of stages in the adder

Digital Object Identifier 10.29292/jics.v18i2.691

 Rashmi et al.: Error Efficient MT-FX-AT for Signal Processing Applications

tree. In direct truncation, the least significant bit of the output

from each adder is truncated after computation at each stage.
Whereas, in post truncation, the least significant bit of the final
output from the entire adder tree is truncated. However, these
approximations may not hold good for a wide range of
applications. In the recent past, several approximate designs
have been proposed to achieve efficient arithmetic computation
[6]. As we play around with truncation at different levels, the
error induced becomes significantly high and computation
Fig.1 (a) Full width adder tree (FL-AT) N=8 and w=8 (b) Fixed width post
accuracy may vary. [1] Investigated the Fixed Width AT using truncated adder tree (FX-AT-PT) N=8 and w=8
bias estimation aspects. Using the bias estimation, the
maximum error distance of adder tree is improved to 13 with an
area optimized by 40% compared to full width adder tree. [2]
Provides a comparative analysis of different gate-level SAAs,
suitable for both FPGA and ASIC type implementations, was
performed from the perspective of error and design metrics.
Different state of art approximate adders is compared, and it is
observed that [7] is better in terms of area and [8] is preferred
in terms of accuracy of result. [3] This paper discusses transistor
level adder optimizations. To perform switch level arithmetic Fig.2 Input bit matrix of adder tree for N=8 and w=8 y0 and y1 represent the
design mirror design concepts are explored. [1] uses type 1 2 3 output of FL-AT and FX-AT-PT
and 4 of [3] to compare his proposed design with existing state B. FX-AT-PT (Fixed-Width Post-Truncated Adder-Tree)
of art. Previous works [1] have reported the Maximum Error
In the post truncation method, the adder tree will provide
Distance of 13 and with area improvement of 29% compared to
precise addition of the inputs, similar to the full width adder tree.
FX-AT-PT. In our work a multiplexer-based design is
Although in the penultimate stage, the data will be divided into
proposed, to achieve a maximum error distance of 8 for N = 8,
two parts, namely MSP (Most Significant Part) and LSP (Least
16 irrespective of the word length (w). The rest of the paper is
Significant Part) as shown in Fig.1(b). The size of LSP is decided
organized as follows, Section II deals with existing adder tree
with the help of log2N. The MSP is given to an exact adder to get
designs and their comparisons based on different metrics.
the accurate output, whereas the LSP is processed through a “C”
Section III discusses about the proposed Adder Tree design.
block to provide Cin to the last adder block, in order to reduce the
Section IV deals with hardware and time complexity
error distance. The tree will have ceil of log2N stages. The output
performance study for image processing applications. Section
of the first stage is w+1 bits, the output of the second stage is w+2
V deals with conclusion and future scope.
bits so on as observed by Fig.2. The function of the “C” block is
as follows:
II. EXISTING ADDER TREE DESIGNS a = {a2, a1, a0} (1)
In order to obtain a distinct outcome when compared to the b = {b2, b1, b0} (2)
proposed design, we have chosen five divergent existing adder c1 = a0 ∙ b0 (3)
tree designs and performed comparative analysis against key c2 = a1 ∙ c1 + b1 ∙ c1 + a1 ∙ b1 (4)
metrics such as area, power, delay and error performance. For r = a2 ∙ c2 + b2 ∙ c2 + a2 ∙ b2 (5)
the sake of conformity, all architectures were designed using This method gives a maximum error distance of 7 which is
Cadence NC-simulator tools using the saed90nm typical library considered as the minimum error encountered in adder tree
with built in constraint. design as per state-of-the-art. For the sake of comparison, the area
of this AT is considered as upper ceiling and its maximum error
A. Full Width Adder Tree distance is considered as minimum ceiling for upcoming AT
The full width adder tree is a conventional tree which design comparison.
provides an accurate summation of N inputs, and each input of
size w bits. Multiple full width adders are used in all the stages C. FX-AT-DT (Fixed-Width 1-bit Direct-Truncated Adder-
and the number of stages depends on N. For instance, we have Tree)
provided 8 inputs, each of size 8 bits. As full width adders are In the Direct truncation method, the adder tree will perform
used at each stage the output bit size increments by 1. As precise addition of the inputs, but the Least Significant Bit (LSB)
depicted by Fig.1(a), for 8 inputs, the tree will have 3 stages, of the output at each stage will be truncated/ignored/neglected,
which is determined by log2N. Therefore, as shown by Fig.2 the without affecting the remaining bits. This results in the size of
final output is the total of N and the number of stages, i.e., 8 + final output to be same as w, as depicted by Fig.3. Let us consider
3 = 11 bits, which is same as w+log2N. The accuracy of this full N inputs each of w bits in size, and let p be the number of stages,
width adder tree is 100%, since all bits are added, along with required to compute final output of AT. The output from the first
their carry bits generated in all the stages. stage will be w+1 bits, but as the LSB is truncated, input vector
Journal of Integrated Circuits and Systems, vol. 18, n. 2, 2023

size to the subsequent stage will remain as w bits. This

computation method is followed until the final stage. At the final
stage, we append p zeros to LSB to maintain the size of final
answer, which is w+p bits. FX-AT-DT method achieves 20% in
area efficiency at the cost of 23% increased MED.

Fig.4 Input bit matrix of TFX-AT for N=8 and w=8 with constant bias of 4

Fig.3 Fixed Width 1-bit direct truncation adder tree (FX-AT-DT) with N=8 and
w=8

D. TFX-AT (Truncated Fixed-Width Adder-Tree)

In TFX-AT [1], the data is divided into two parts, MSP (Most
Significant Part) and LSP (Least Significant Part). The LSP size
depends on p = log2N, where N is the number of inputs. In TFX-
AT, the LSP is truncated at the input stage and there is a
constant bias, carry in “Cin =1”, provided to the first stage of
the tree to compensate for the significant error incurred due to
truncation. This can be understood by Fig.5. For N input data, Fig.5 Truncated Fixed width adder tree (TFX-AT) with N=8 and w=8 with LSP
w-log2N bit MSP is added precisely. The final number of stages (3-bit truncation)
required to compute for N inputs will be ceil of log2N. The final
output of the tree will again be w bits. Input bit matrix is shown
in Fig.4.
For the 8 inputs of 8 bits each, the maximum error distance of
the truncated tree adder is 56 which can be reduced to 28 by
adding bias input of (4=8/2) in the first stage of the adder tree.
The mathematical approach used to compute fixed bias in adder
tree is given by Equation 6.
𝑌 = 𝑀𝑆𝑃 + 𝐿𝑆𝑃 (6)
Where Y = Final output of adder tree
MSP = Most Significant Part used for precise addition
LSP = Least Significant part which is truncated
To compensate the error due to truncation the LSP part is
replaced by fixed bias estimation. Each number in LSP matrix
Fig.6 Improved Truncated Fixed width adder tree (ITFX-AT) with N=8 and
is binary occurring with the probability of ½. The output y is w=8
expressed as
𝑌 = 𝑀𝑆𝑃 + 2 𝜎 (7) E. ITFX-AT (Improved Truncated Fixed-Width Adder-Tree)
Where 2 𝜎 is LSP term and 𝜎 is estimated bias. If all p =log2N In ITFX-AT [1], the data is divided into two parts, MSP
are considered for truncation, then w×p LSP matrix is estimated (Most Significant Part) and LSP (Least Significant Part). The
as LSP size depends on the formula log2N, where N is the number
E[LSP] = N ∑ ( )2 (8) of inputs. Depending on the number of LSP bits considered for
w = number of bits in input, p = LSP bits considered for truncation, accuracy of adder tree will be configured. Here in
truncation as discussed in [4]. ITFX-AT among three bits of LSP, higher significant 1-bit (σ
E[LSP] = 2 (1 − 2 ) ≅ 2 (9) major) is computed precisely whereas lower two bits of LSP (σ
TFX-AT shows a 42.37% improvement in area when compared to minor) bits are truncated. Further to improve accuracy, fixed
FX-AT-PT. But compromises in terms of MED by 68.18% when bias estimation is added in to the first stage of adder tree. MSP
compared to FX-AT-PT. is added accurately like that of TFX-AT. Higher significant bit
of LSP is also added precisely using A* and A blocks in the tree
stages. In this design the accuracy of the tree improved by
 Rashmi et al.: Error Efficient MT-FX-AT for Signal Processing Applications

46.15% compared to TFX-AT at the cost of 24.7% area number of bits analyzed by LSP block in the tree is given by
overhead. The design of TFX-AT fixed width adder tree with log2N, where N is the number of inputs. In proposed design the
N=8 and w=8 is depicted in Fig. 6. The details of A and A* LSP is further divided into σ major and σ minor as shown in
blocks are shown in Fig. 7. Here A* stage is used in first stage Fig. 10. σ major is the 2 higher order bits of the LSP and
of the tree design to incorporate 1-bit accurate addition with remaining least significant bit of LSP comprise the σ minor
bias added for error correction. A block is added in subsequent which needs to be truncated in the proposed design. The σ
stages to perform 1-bit exact addition to improve error major bits are used to generate the fixed bias in the LSP stage
performance parameter of the AT. Implementation of the fixed of the tree by computing radix-4 addition. For N inputs each of
bias can be understood by Table.1. Figure 8 shows the input bit w bits, the MSP comprise of w-log2N bits and LSP comprise of
matrix. log2N bits. The σ major is passed through “AXA*” block in first
stage and “AXA” block in the subsequent stage. AXA* block
performs precise radix-4 addition with 1-bit fixed bias. Whereas
AXA block does only accurate radix 4 addition with minimum
area requirements. AXA* block comprises of two 2:1
multiplexer, XOR, OR and XNOR gates and AXA block
comprises of two 2:1 multiplexer, two XOR and AND gates as
depicted in Fig.11. The least significant bit of the input is
Fig.7 A* block for 1-bit accurate arithmetic with bias estimation and A block truncated. The design analysis of AXA and AXA* block is
for the subsequent stages detailed in Table 2.
For MT-FX-AT to estimate the bias of Least significant bit
Table.1 Fixed bias implementation for A* and A block
(truncated part) of LSP, the estimation equation is given by
Fixed A B S CO E[LSP]=N ∑ ( )2 (12)
Bias
0 0 0 0 0
W=number of bits of each input, p-1= LSP bits considered for
0 0 1 1 0 A truncation, expressed as
0 1 0 1 0 block E[LSP]= 2 (1 − 2 )≅ 2 (13)
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1 A*
1 1 0 0 1 block
1 1 1 1 1

Fig.8 Input bit matrix of ITFX-AT for N=8 and W=8 with constant bias of 4 Fig.9 Proposed MT-FX-AT design

For ITFX-AT to estimate the bias of last two bits (truncated

part) of LSP, the estimation equation is given by
E[LSP]=N ∑ ( )2 (10)
W=number of bits in input p-1= LSP bits considered for
truncation
E[LSP]= 2 (1 − 2 )≅ 2 (11)

III. PROPOSED MULTIPLEXER BASED FIXED WIDTH ADDER

TREE DESIGN (MT-FX-AT)
In MT-FX-AT design, the data is divided into two parts, Fig.10 Input bit matrix of proposed MT-FX-AT for N=8 and W=8 with constant
bias of 1
MSP (Most Significant Part) and LSP (Least Significant Part).
The MSP is computed using the traditional full-width adders
without truncation. The LSP is computed by using AXA* and
AXA block in the first and second stage of the tree as depicted
in Fig. 9, where AXA stands for approximate addition. The
Journal of Integrated Circuits and Systems, vol. 18, n. 2, 2023

AXA* fixed width adder trees such as FX-AT-PT, FX-AT-DT, TFX-

AT and ITFX-AT are analyzed and compared for its error
performance with the proposed MT-FX-AT. All the designs are
validated using Verilog and tested using saed90nm typical
C block library. For N = 8, 16, and w = 8, 12, 16 the test-bench produced
10,000 sets of randomly generated test inputs.
Compared to Full Width AT, fixed width AT are prone to errors
due to truncation of bits and therefore it is essential to keep a
check on the errors by examining the error performance
metrics. The most classic error measurements for an
approximate arithmetic design includes Maximum Error
AXA Distance (MED), Average Error Distance (AED) and Average
Accuracy (AAC). [10].
MED is calculated by taking the maximum of the absolute value
of the difference between the output of the full-width AT and
the output of the fixed-width AT. It is given by:
𝑚𝑎𝑥 𝑎𝑏𝑠(𝑦 − 𝑦 ) (14)
where yO is the output of the full-width AT and yi is the output
of the fixed-width AT.
AED is calculated by taking the average of the absolute value
of the difference between the output of the full-width AT and
the output of the fixed-width AT. It is given by:
Fig.11 AXA* block for radix-4 addition with 1-bit fixed bias and AXA block
for only radix-4 addition 𝑎𝑣𝑔 𝑎𝑏𝑠(𝑦 − 𝑦 ) (15)
where yO is the output of the full-width AT and yi is the output
Table.2 Truth table analysis of AXA block of proposed Adder tree design of the fixed-width AT.
A2 B2 A1 B1 S1 C1 X S2 Cout
0 0 0 0 0 0 0 0 0 AAC is calculated by first taking the difference between the
0 0 0 1 1 0 0 0 0 output of the Full Width AT yO and the absolute ED, where ED
0 0 1 0 1 0 0 0 0 is the difference between the approximate and accurate sum
0 0 1 1 0 1 0 1 0 and then this is divided by yO . Average of this taken for all the
0 1 0 0 0 0 1 1 0
0 1 0 1 1 0 1 1 0 10,000 samples. Finally, the percentage value is calculated by
0 1 1 0 1 0 1 1 0 multiplying the average results by 100. AAC is given by:
0 1 1 1 0 1 1 0 1 ( )
1 0 0 0 0 0 1 1 0 𝑎𝑣𝑔 1− × 100 (16)
1 0 0 1 1 0 1 1 0
1 0 1 0 1 0 1 1 0 Predominantly the error metrics are mostly dependent on the
1 0 1 1 0 1 1 0 1 number of the inputs (i.e., value of N) rather than the size of the
1 1 0 0 0 0 0 0 1
inputs. Table 4 shows the error performance metrics of all state-
1 1 0 1 1 0 0 0 1
1 1 1 0 1 0 0 0 1 of-the-art fixed width and proposed fixed width AT for N = 8,16
1 1 1 1 0 1 0 1 1 and w = 8,12,16. For N = 8, MT-FX-AT has the lowest AED
and FX-AT-PT has the lowest MED when compared to other
IV . RESULTS AND DISCUSSIONS designs. The proposed design also aims to maintain a uniform
Full-width AT, which involves more logic complexity than MED with change in w. Taking AAC into consideration MT-
fixed-width AT, precisely calculates the result. However, fixed FX-AT has the highest percentage and therefore this proves to
width AT generates some inaccurate output by improving have an acceptable tradeoff whilst maintaining good accuracy.
performance metrics of the tree design. It is crucial to examine B. Analyzing and Comparing Synthesized Results
the hardware complexity and error performance metrics of All the six designs were simulated and synthesized on
designed fixed width adder tree, by doing so the approximate Cadence using the SAED 90nm typical cell library. The metrics
adder-tree structure for a desired application can be picked with being compared are area and power and are discussed in Table
ease. 5. Proposed MX-FX-AT has a 18.17% and 5.05% decrease in
A. Analyzing and Comparing Different Error Measurements area when compared to FX-AT-PT and FX-AT-DT
respectively, while maintaining the MED close to that of FX-
Different error performance metrics are compared and AT-PT. When compared to TFX-AT and ITFX-AT, area of the
analyzed for, the proposed fixed-width AT design (MT-FX- proposed MX-FX-AT has a 41.99% and 16.24% increase but
AT). Conventional Full Width adder tree and state-of-the-art MED has a 63.64% and 38.46% improvement, respectively.
 Rashmi et al.: Error Efficient MT-FX-AT for Signal Processing Applications

C. Studying Signal Processing Applications Using

Approximate Arithmetic Structures
Additions and multiplications make up the majority of
multimedia DSP algorithms. Multiplications are equivalent to
shifts and additions. As a result, adders may be seen as the
fundamental building blocks for various algorithms. The
majority of DSP algorithms used in multimedia systems have
Original Image
intrinsic fault tolerance, which is an interesting trait. So, minor
mistakes in intermediate outputs might not significantly affect
the ultimate output quality. We concentrate on image
processing and describe the outcomes of this algorithm by
employing our approximate adder tree structures. To prevent a
significant decline in output quality, we solely apply
approximation in the LSPs.
We have considered an 8-point Walsh-Hadamard transform
FX-AT-PT ITFX-AT MT-FX-AT
(WHT) for processing the images on MATLAB. The original PSNR = 73.4 PSNR = 65.4 PSNR = 70.25
full width adders in WHT algorithm are replaced with existing
and proposed fixed width adder tree.
We have examined three digital images as shown in Fig.12,
with a spatial resolution of 512X512. PSNR was evaluated to
determine the quality of the reconstructed images. The PSNR
ratio is used to measure how robust the signal is in comparison
to noise or distortion in an image. Less visual distortion or a
better reconstructed image is indicated by a high PSNR score
Original Image
and it is measured in terms of decibels. Image processing was
carried out, where an original image was translated into a matrix
of size 1×262144, which was then processed by forward and
inverse Walsh-Hadamard transform (WHT).
WHT is calculated using the formula:
𝑦 = ∑ 𝑥 × 𝑊𝐴𝐿(𝑛, 𝑖) (17)
y is the output vector returned by WHT, N is the number of
FX-AT-PT ITFX-AT MT-FX-AT
inputs to the adder tree and n and i represents the rows and PSNR = 90.23 PSNR = 81.35 PSNR = 86.24
columns of the unitary Walsh matrix. x is a matrix that contains
the pixel values of the input image. Fig.12 Three different sets of digital images and their PSNR scores (in dB)
obtained using various FX-AT
The proposed design achieves an improved PSNR score when
compared to the ITFX-AT and also maintains a very similar
score as that of FX-AT-PT. The scores are detailed in Table 3. V. CONCLUSION
The innate error tolerance of signal processing applications
was exploited in this study to create a fixed width adder tree to
trade off performance and error metrics. The impact on output
quality was relatively negligible when the inaccuracies caused
by these approximations were represented at a high level in
WHT. The proposed design incorporates multiplexers to
compute the approximations in 𝜎 . A bias estimation
Original Image approach is made use of to compensate and maintain minimal
error, induced due to truncation of data.
Proposed design has a 18.17% and 5.05% decrease in area
when compared to FX-AT-PT and FX-AT-DT respectively,
while maintaining the MED close to that of FX-AT-PT.
When compared to TFX-AT and ITFX-AT, area of the
proposed MX-FX-AT has a 41.99% and 16.24% increase but
MED has a 63.64% and 38.46% improvement, respectively.
FX-AT-PT ITFX-AT MT-FX-AT
Moreover, the designed adder tree maintains constant MED
PSNR = 83.04 PSNR = 79.0 PSNR = 81.7
irrespective of word length for N=8,16 which is more
Journal of Integrated Circuits and Systems, vol. 18, n. 2, 2023

demanding for high word length data application.

Additionally, WHT was implemented for three different digital
images using the proposed design and the PSNR score of
proposed MT-FX-AT was relatively higher when compared to
the PSNR score of ITFX-AT.
Our approach of using multiplexers aids in sustaining nominal
error and this trait proves to be essential for different variants
of signal processing applications.

Table.4 Error analysis

WORD LENGTH w=8 WORD LENGTH w=12 WORD LENGTH w=16
DESIGNS N
AED MED AAC (%) AED MED AAC (%) AED MED AAC (%)
FULL WIDTH 8 0 0 100 0 0 100 0 0 100
[1] 16 0 0 100 0 0 100 0 0 100
8 3.50 7 99.66 3.50 7 99.98 3.50 7 99.98
FX-AT-PT [1]
16 7.30 15 99.64 7.50 15 99.97 7.50 15 99.99
8 6.00 12 99.42 6.00 12 99.96 6.10 12 99.99
FX-AT-DT [1]
16 16.00 31 99.21 16.00 31 99.95 16.10 31 99.99
8 6.00 22 99.41 6.20 26 99.96 6.10 26 99.99
TFX-AT [1]
16 16.30 64 99.20 16.10 76 99.95 16.10 71 99.99
8 3.40 13 99.67 3.40 15 99.98 3.40 15 99.99
ITFX-AT [1]
16 8.70 34 99.57 8.60 40 99.97 8.70 40 99.99
PROPOSED 8 2.98* 8 99.89 2.99 8 99.87 2.99 8 99.92
MT-FX-AT 16 7.90 22 99.83 7.92 22 99.91 7.92 22 99.97

Table.5 Area power analysis

WORD LENGTH w=8 WORD LENGTH w=12 WORD LENGTH w=16
DESIGNS N
AREA POWER AREA POWER AREA POWER
FULL WIDTH 8 1610 257 2539 283 3476 295
[1] 16 3261 232 5135 376 7200 537
8 1723 275 2717 295 4008 367
FX-AT-PT [1]
16 3489 363 5394 391 7902 568
8 1485 225 2342 241 3455 246
FX-AT-DT [1]
16 3028 372 4937 735 6734 1256
8 993 146 1287 193 1725 207
TFX-AT [1]
16 2438 171 3858 278 5255 396
8 1213 183 2035 283 2807 310
ITFX-AT [1]
16 2540 251 4306 313 5903 455
PROPOSED 8 1410* 225 2253 248 3172 255
MT-FX-AT 16 2855 207 4525 338 6265 497
* It can be observed that the proposed MT-FX-AT has a significantly lesser error rate when compared to TFX-AT and ITFX-AT
and hence the proposed design shows a trade-off in area and power. As the aim is to achieve high accuracy.
Table.3 Comparison of PSNR scores (dB)
Image 2: Image 3:
DESIGNS Image 1: Lady
House Pepper

FX-AT-PT 83.4 73.4 90.23

ITFX-AT 79.0 65.4 81.35

PROPOSED
81.7 70.25 86.24
MT-FX-AT
Journal of Integrated Circuits and Systems, vol. 18, n. 2, 2023

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