Synthesis

Synthesis is the process of converting RTL (Register Transfer Level) code (i.e.., Verilog format) to
optimized Gate level netlist to the targeted technology by meeting area, timing and power
constraints.

Synthesis = Translation + logic Optimization + Mapping

Types of synthesis
There are 2 types of synthesis techniques which are in use to convert RTL code to gatelevel netlist:

Logic synthesis

Physical aware synthesis

Some popular tools for synthesis are:

Genus - Cadence

Design Compiler - Synopsys

Now a days most of the companies are moving to Fusion Compiler (Synosys) instead of Design
Compiler

Goals of synthesis is
To get a gate-level netlist with minimum dealy ( speed ,perfomance ),minimum area (number of
gate , ragister ) ,minimum power.

Inserting Clock gates

Logic optimization

Inserting DFT logic

Logic Equivalence between RTL and Netlist should be maintained.

 Synthesis flow

Input required for synthesis:

High-Level Design Description (HDL) (Verilog, VHDL)/ RTL code

Design Exchange Format (DEF file)

Physical Library (LEF)

Timing Library (.lib):

Unified Power Format (.upf):

Standard Design Constraints (.sdc)

Output of synthesis:
Netlist

SDC

Reports

Inputs :

High-Level Description: A hardware description of the design, typically written in a hardware

description language (HDL) like Verilog or VHDL. This description captures the intended
functionality of the digital circuit.

Constraints: Timing constraints, area constraints, power constraints, and other design
requirements that define the desired performance and characteristics of the final design.

Library Information: Information about the standard cell library that contains predefined logic
gates and their associated characteristics, such as delay, power consumption, and area.

Mapping :

Technology Mapping: The generic gate-level representation is mapped onto the specific cells
available in the target standard cell library. This involves selecting appropriate gates to implement
the design's logic and interconnections.

Optimization Stages:

Logical Optimization: The logic is optimized to improve performance, reduce power consumption,
and minimize area usage. Techniques like Boolean logic optimization, constant propagation, and
common subexpression elimination are employed.

Timing Optimization: Timing constraints are taken into account to ensure that signal propagation
delays meet the desired timing targets. This may involve inserting buffers or performing other
transformations to achieve balanced and well-timed circuits.

Area Optimization: Techniques are applied to minimize the physical area occupied by the design,
which is important for efficient chip utilization.
DFT insertion

DFT is Design For testability. This technique is used to check whether manufacturing process has
added any defects in the chip. DFT insertion means inserting an additional logic to improve the
testability of the internal nodes of the desig.

Scan insertion while synthesis/before synthesis/after synthesis

Scan insertion can be done at three different stages in the design flow:

In general, scan insertion during synthesis is the best approach for most designs.

During synthesis: This is the most common approach, as it allows the scan insertion tool to
optimize the scan chains for performance and area.

Before synthesis: This approach is less common, but it can be used to improve the testability of the
design before any optimizations are performed.

After synthesis: This approach is the least common, as it is the most disruptive to the design flow.
However, it can be used to add scan to a design that was not originally designed for testability.

Synthesis Inputs
Synthesis inputs are the various pieces of information and data required by a synthesis tool to
perform the process of converting a high-level hardware description of a digital circuit into a gate-
level netlist.

HDL (hardware description language): These files contain the functional and behavioral
description of the digital circuit at a high level. They define how the circuit should behave and
operate.

Design Exchange Format (DEF file): The Design Exchange (DEF) file is an ASCII representation of
physical information of the design. DEF contains Property definition, Die area, Row definition,
Physical cell definition, STD cell definition, special net, regular nets, port, blockages, module
constraints etc.

Physical Library (LEF): The Physical Library or Library exchange format (LEF) is an ASCII
representation of the abstract of the standard cells. It contains all the physical information about
the cells (Technology and Macro cells) and nets. It also contains the Layer definitions, VIA’s
definitions, SITE definitions, Metal capacitance definitions, Macro cell definitions, macro cell
dimensions, Layout of pins, Blockages information, DRC information given by foundry etc. There
are basically two types of LEF: Tech LEF: Technology LEF file contains all the details about the Metal
layer information (Type, Direction, Pitch, Offset, Area, Width, Resistance, Capacitance, Edge
Capacitance, Thickness, Antenna Model, Antenna Ratio, etc.), Via Definition (Type, Spacing, Width,
Enclosure, Antenna model, Antenna Ratio etc.) , Site Info, Resistance, Capacitance, Edge Capacitance,
Antenna information, etc. Macro LEF: Macro/Cell LEF contains all the information about the
standard cell physical information, Macro cell physical information (Class, Origin, Symmetry, Site,
Pin Direction, etc.), Pin location etc.

Timing Library (.lib): The timing library (.lib) is an ASCII representation of the Timing, Power and
Area associated with the standard cells. delay calculation happens based on input transition (Slew)
and the output capacitance (Load).

Unified Power Format (.upf): The Unified Power Format (.upf) is an IEEE standard which is used
to define the power and related aspects of multi voltage design. UPF contains supply set definition,
power domain definition, power switch definition, retention cell definition, level shifter cell
definition and other low power related definition.

Standard Design Constraints (.sdc): Standard design constraints or Synopsys design constraints
contain the timing and power related constraints which control design w.r.t to the spec.

Incremental Optimization

After scan insertion one more optimization has to be done which will be same as optimization.

Generate Output

Optimized gate level netlist, SDC, DEF (info for scan connection between flops in the design), report

UPF

UPF stands for "Unified Power Format" and it is a standard format used in the field of electronic
design automation (EDA) to describe and control power intent in integrated circuit (IC) designs.

Liberty Timing File (LIB)

lib contains the standard cell information, but only the timing information of the cells. This is used
during the synthesis and STA phases.

In .lib file following unit attributes are present

Time unit

Voltage unit

Current unit

Leakage power unit

Capacitive load unit

Library Exchange Format (LEF)

LEF file has the physical information of the std. cells

Design Exchange Format (DEF)

DEF file contains the design-specific information of a circuit and is a representation of the design at
any point during the layout process.

Link library

A link library is a collection of cells that are used to describe the function of mapped cells prior to
optimization. The link library is typically used to provide cells that are not available in the target
library, such as RAMs, ROMs, and macros. The link library can contain cells from any technology
library, but it is typically recommended to use the same technology library for the target library and
the link library.

Target library

the technology library you want to map to during synthesis. Target library is used for technology
mapping. All the combo (AND, NAND, NOT, etc) and the sequential (SDFF, DFF, etc) are mapped to
equivalent gates from the target. Synthesis is about converting RTL to gates.
Can we do synthesis without giving timing constraints?

Yes, it is possible to do synthesis without giving timing constraints. However, the resulting design
may not meet the timing requirements of the design.

Clock Tree Synthesis (CTS) is the technique of balancing the clock delay to all clock inputs by
inserting buffers/inverters along the clock routes of an ASIC design.