EDA Tools

Lab 08: Pre-layout verification tools (Formality)

Objective
Learn how to use Formality to detect unexpected differences that may have been introduced into a design
during development.

Introduction

The purpose of Formality is to detect unexpected differences that may have been introduced into a design
during development.

In Formality the following concepts are used:

Reference design: This design is the golden design, the standard against which Formality tests
for equivalence.
Implementation design: This design is the changed design. It is the design whose accuracy you
want to prove. For example, a newly synthesized design is an
implementation of the source RTL design.

To start Formality, enter the following command at the terminal:

% fm_shell
fm_shell (setup)>

The fm_shell command starts the Formality shell environment. From here, start the graphical user interface
(GUI) as follows:

fm_shell (setup)> start_gui

When Formality is invoked, begin in the setup mode. The setup indicates the mode that currently in when
using commands. The modes are setup, match, and verify.

This laboratory work includes the following sections:

0. Guidance (Load Automated Setup File)
1. Reference (Specify the Reference Design)
2. Implementation (Specify the Implementation Design)
3. Set up (Set Up the Design)
4. Match (Match Compare Points)
5. Verify (Verify the Designs)
6. Debug.

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Laboratory tasks

0. Guidance (Load Automated Setup File)

Before specifying the reference and implementation designs, an automated setup file (.svf) can be optionally
loaded into Formality. The automated setup file helps Formality process design changes caused by other
tools used in the design flow. Formality uses this file to assist the compare point matching and verification
process. For each automated setup file that is loaded, Formality processes the content and stores the
information for use during the name-based compare point matching period.

If Formality is given the result of DC, then work in the pre_lay directory, and if Formality is given the result
of ICC, then work in the post_lay directory. This lab shows an example where Formality works with the
result of ICC. To run Formality, which works with the result of DC is similar to this lab steps.

Start Formality graphical user interface (GUI) from work directory, which is located in post_lay directory.
To start it, enter:

% fm_shell -gui

This opens the Formality top-level GUI window (Fig. 1).

Fig.1. The Main Window of Formality GUI

Use the script, created to carry out complex commands. There is a script in scripts directory, which is
located in post_lay directory. The name of this script is script.tcl, which sources using the following
command:
Formality(verify)> source ../scripts/script.tcl

Now understand Formality's general sections.

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1. Reference (Specify the Reference Design)

Specifying the reference design involves reading in design files, optionally reading in technology libraries,
and setting the top-level design.

The reference design is the design against which the transformed (implementation) design is compared.
The reference design is the RTL source file named johnson.v file. Click Open and Load this file (Fig 2).

Fig.2. Set up DC gate level Source

Source the DB file. Select ./ref/db_nldm/ saed14rvt_tt0p8v25c.db file click Open and Load this file (Fig. 3).

Fig.3. Set up .db file.

Set Top Design of reference. Select Library WORK, choose a design johnson and Set and click Set Top
button (Fig 4).

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 Fig.4. Set Top

2. Implementation (Specify the Implementation Design)

The procedure for specifying the implementation design is identical to that for specifying the reference
design. The implementation design is the gate level netlist after Design Compiler named this source file
johnson.v file. Click Open and Load this file (Fig. 5).

Fig.5. Set up ICC gate level Verilog

Source the DB file. Select ./ref/db_nldm/ saed14rvt_tt0p8v25c.db file. Click Open and Load this file (Fig.
6).

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 Fig.6. Set gate .db file

Set Top Design of implementation. Select Library WORK, choose a design johnson and Set and click Set
Top button and Load this file.

3. Set up (Set Up the Design)

To Set up the design, click 3.set up (Fig.7 and Fig.8).

Fig.7. Set Up the Design window

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 Fig.8. After Set Up the Design

4. Match (Match Compare Points)

Match compare points is the process by which Formality segments the reference and
implementation designs into logical units, called logic cones.

To match compare points between johnson.v and johnson.v (after ICC II), do the following:
In Main Window click 4. Match for match compare points.

Fig.9. Match compare points

As seen from the massage shown in Fig.9, there are 0 unmatched compare points.

5. Verify (Verify the Designs)

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When verify command is used, Formality attempts to prove design equivalence
between an implementation design and a reference design. This section describes how to
verify a design or a single compare point as well as how to perform traditional hierarchical
verification.
On the main toolbar, click the Verify tab, then click Verify.

Fig.10. Verify the design

Verifying process completed successfully.

6. Debug

During debugging, the exact points in the designs that exhibit the difference in functionality and then fix
them must be found (Fig. 11).

Fig.11. Debugging the design

Formality is able to simultaneously display reference and implementation Verilog views and mark
differences and /or similarities (Fig. 12).

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 Fig.12(a). Implementation Verilog
Fig. 12(b). Reference Verilog

Besides, Formality can display schematic view and highlight reference object on it (Fig. 13).

Fig.13. View Reference Object in schematic

Output results of the design are stored in ../.location/results/ directory.

To exit Formality, write exit in the command line.

Formality (verify)> exit

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