Lecture 4:

Simple Digital
Circuits
Outline
n Nonideal Transistor Behavior
Channel Length Modulation
n
n Leakage
n Subthreshold Leakage

n Gate Leakage

n Junction Leakage

n Simple Digital Circuits

4: Nonideal Transistor Theory 2

Channel Length Modulation
n Reverse-biased p-n junctions form a depletion
region
n Region between n and p with no carriers
V V
GND DD DD

n Width of depletion Ld region grows with reverse

Source Gate Drain
Depletion Region

bias Width: L d

n Leff = L – Ld n L n
+ Leff +

n Shorter Leff gives more current p GND bulk Si

n Ids
increases with Vds
n Even in saturation

4: Nonideal Transistor Theory 3

Chan Length Mod I-V


( − Vt ) (1 + lVds )
2
I ds = V gs
2

◼ l = channel length modulation coefficient

◼ not feature size
◼ Empirically fit to I-V characteristics

4: Nonideal Transistor Theory 4

Ideal vs. Simulated nMOS I-V Plot
n 65 nm IBM process, VDD = 1.0 V
Ids ( A)

Simulated
Vgs = 1.0
Ideal
1200
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts

1000
Ion = 747 mA @
Channel length modulation: V = V = V
gs ds DD
Saturation current increases
800 with Vds Vgs = 1.0

Vgs = 0.8
600
Velocity saturation & Mobility degradation:
Vgs = 0.8
Saturation current increases less than
400 quadratically with Vgs

Vgs = 0.6
200 Vgs = 0.6
Vgs = 0.4
0 Vds
0 0.2 0.4 0.6 0.8 1

4: Nonideal Transistor Theory 5

ON and OFF Current
Ids ( A)
1000

n Ion = Ids @ Vgs = Vds = VDD 800

Ion = 747 mA @
Vgs = Vds = VDD

Vgs = 1.0

n Saturation 600

Vgs = 0.8

400

Vgs = 0.6
200

Vgs = 0.4

0 Vds
0 0.2 0.4 0.6 0.8 1

n Ioff = Ids @ Vgs = 0, Vds = VDD

n Cutoff

4: Nonideal Transistor Theory 6

Leakage
n What about current in cutoff?
n Simulated results
n What differs?
n Current doesn’t
go to 0 in cutoff

4: Nonideal Transistor Theory 7

 Leakage Sources
n Subthreshold conduction
n Transistors can’t abruptly turn ON or OFF
n Dominant source in contemporary transistors

n Gate leakage
n Tunneling through ultrathin gate dielectric
n Carriers tunnel thorough very thin gate oxides
n Negligible for older processes (tox > 20 Å)
n Critically important at 65 nm and below (tox ≈ 10.5 Å)

n Junction leakage
n Reverse-biased PN junction diode current

Gate leakage

p+ n+ n+ p+ p+ n+

n well
4: Nonideal Transistor Theory p substrate
8
Temperature Sensitivity
◼ Increasing temperature
◼ Reduces mobility
◼ Reduces Vt
◼ ION decreases with temperature
◼ IOFF increases with temperature
I ds

increasing
temperature

Vgs

4: Nonideal Transistor Theory 9

VLSI Design

Circuits & Layout

Power Supply Voltage
n GND = 0 V
n In 1980’s, VDD = 5V
n VDD has decreased in modern processes
n High VDD would damage modern tiny
transistors
n Lower VDD saves power

n VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,

n Effective power supply voltage can be lower
due
to IR drop across the power grid.
Transistors as Switches
n In Digital circuits, MOS transistors are
electrically controlled switches
n Voltage at gate controls path from source to
drain g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d
pMOS g OFF
ON
s s s
CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0

ON Y is pulled low by the

turned on NMOS

A Y Device. Hence
NMOS is the pull-
down device.
GND
CMOS Inverter

A Y VDD Y is pulled high by

0 1 the turned on PMOS
Device. Hence PMOS

1 0 ON is the pull-up device.

A=0 Y=1

OFF
A Y
GND
CMOS NAND Gate
A B Y
0 0 1 ON ON
0 1 Y=1
1 0
A=0 OFF
1 1
B=0 OFF
CMOS NAND Gate
A B Y
0 0 1 OFF ON
0 1 1 Y=1
1 0
A=0 OFF
1 1
B=1 ON
CMOS NAND Gate
A B Y
0 0 1 ON OFF
0 1 1 Y=1
1 0 1
A=1 ON
1 1
B=0 OFF
CMOS NAND Gate
A B Y
0 0 1 OFF OFF
0 1 1 Y=0
1 0 1
A=1 ON
1 1 0
B=1 ON
CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y
3-input NAND Gate
n Y is pulled low if ALL inputs are 1
n Y is pulled high if ANY input is 0

Y
A
B
C
Complementary CMOS
n Complementary CMOS logic gates
n nMOS pull-down network
n pMOS pull-up network pMOS
pull-up

n a.k.a. static CMOS

network
inputs
output

nMOS
pull-down
network

Pull-up OFF Pull-up ON

Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)
 Series and Parallel
a a a a a
0 0 1 1
g1
g2
0 1 0 1
b b b b b
(a) OFF OFF OFF ON

n nMOS: 1 = ON a
0
a
0
a
1
a
1
a

g1

n pMOS: 0 = ON g2
b
0
b
1
b
0
b
1
b

n Series: both must be ON (b) ON OFF OFF OFF

n Parallel: either can be ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF
 Conduction Complement
n Complementary CMOS gates always produce 0 or 1

n Ex: NAND gate

n Series nMOS: Y=0 when both inputs are 1
n Thus Y=1 when either input is 0
n Requires parallel pMOS Y
A
B
n Rule of Conduction Complements
n Pull-up network is complement of pull-down
n Parallel -> series, series -> parallel
Compound Gates
n Compound gates can do any inverting function
n Ex: AND-AND-OR-INV (AOI22) Y ( A B) (C D)
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)
Example: O3AI
n
Y ( A B C) D
Example: O3AI
n
Y ( A B C) D

A
B
C D
Y
D
A B C
Pass Transistors
n Transistors can be used as switches
g

s d

s d
Pass Transistors
n Transistors can be used as switches
g g=0 Input g = 1 Output
s d 0 strong 0
s d
g=1 g=1
s d 1 degraded 1

g g=0 Input Output

g=0
s d 0 degraded 0
s d
g=1
g=0
s d strong 1
Signal Strength
n Strength of signal
n How close it approximates ideal voltage source
n VDD and GND rails are strongest 1 and 0
n nMOS pass strong 0
n But degraded or weak 1
n pMOS pass strong 1
n But degraded or weak 0
n Thus NMOS are best for pull-down network
n Thus PMOS are best for pull-up network
Transmission Gates
n Pass transistors produce degraded outputs
n Transmission gates pass both 0 and 1 well
Transmission Gates
n Pass transistors produce degraded outputs
n Transmission gates pass both 0 and 1 well

Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb
Tristates
n Tristate buffer produces Z when not enabled

EN

EN A Y A Y
0 0 Z
0 1 Z EN
1 0 0
1 1 1 A Y

EN
Multiplexers
n 2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 D0 0
0 X 1 Y
D1 1
1 0 X
1 1 X
Multiplexers
n 2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1 Y
D1 1
1 0 X 0
1 1 X 1
Gate-Level Mux Design
nY SD1 SD0 (too many transistors)
n How many transistors are needed?
Gate-Level Mux Design
nY SD1 SD0 (too many transistors)
n How many transistors are needed? 20
D1
S Y
D0

D1 4 2
S 4 2 Y
D0 4 2
2
Transmission Gate Mux
n Nonrestoring mux uses two transmission
gates
Transmission Gate Mux
n Nonrestoring mux uses two transmission
gates
n Only 4 transistors
S

D0
S Y
D1

S
 Inverting Mux
n Inverting multiplexer
n Use compound AOI22
n Or pair of tristate inverters
n Essentially the same thing

n Noninverting multiplexer adds an inverter

D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1
4:1 Multiplexer
n 4:1 mux chooses one of 4 inputs using two
selects
4:1 Multiplexer
n 4:1 mux chooses one of 4 inputs using two
selects
n Two levels of 2:1 muxes
n Or four tristates S1S0 S1S0 S1S0 S1S0

D0
S0 S1

D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1

D3