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VLSI lab manual 2021-22

Vlsi design (Alva's Institute of Engineering and Technology)

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fAlva’s Institute of Engineering & Technology

Shobhavana Campus, Mijar, Moodbidri, D.K-574225

Department of Electronics & Communication

Engineering

Academic Year 2021-22

VLSI LABORATORY: 18ECL77

NAME: …………………………………………………………..…………

USN:…………………………………………………………….…………..

SEM / SECTION:………………………BATCH NO.:………..………..

Prepared by

Department of Electronics & Communication Engineering

Alva’s Institute of Engineering & Technology

Shobhavana Campus, Mijar, Moodbidri, D.K-
574225 Phone: 08258-262725, Fax:
08258262726

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Vision of the Institute

“Transformative education by pursuing excellence in engineering and Management
through enhancing skills to meet the evolving needs of the community”

Mission of the Institute

 To bestow quality technical education to imbibe knowledge, creativity and ethos
to students community.
 To include the best engineering practices through transformative education.
 To develop a knowledgeable individual for a dynamic industrial scenario.
 To include research, entrepreneurial skills and human values in order to cater
the needs of the society.

Vision of the Department

Centre of Excellence to empower the young minds in the field of Electronics and
Communication engineering with research focus and skill development through
Transformative Education catering to the needs of the Society.

Mission of the Department

 To create Learning Environment to enable the Students for Excellence in the

field of Electronics and Communication Engineering.

 To Empower the Students with necessary Skills for Solving the Complex

Technological Problems.
 To Inculcate Research Culture among Teaching-Learning Group by guiding

them towards Research Activities to bridge the gap between Industry and
Academia.
 By Imbibing the Students with Human Values and Ethics through

Transformative Education and make them Socially Responsible Professionals.

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Program EDUCATIONAL OBJECTIVES

The graduates of Electronics & Communication Engineering will be able to

PEO 1: Apply Mathematical, Scientific and Engineering skills for solving problems in the area of

Electronics and Communication Engineering.

PEO 2: Expose to Emerging Technologies and excel in Industries/Higher studies/Research.

PEO 3: Apply analytical skills in the area of Electronics and Communication Engineering to become
competent and Employable.
PEO 4: Inculcate professional ethics, human values, team work for solving engineering problems and
contribute to societal needs.

Program Specific Outcomes

PSO 1: Understand and apply the principles of Electronics and Communication Engineering
in various domains of Analog and Digital systems.

PSO2: Design and implement systems using the concepts of Electronics, signal processing,
Embedded systems and Semiconductor Technology.

PSO 3: Apply modern hardware and software tools to analyse and solve engineering
problems.

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PROGRAMME OUTCOMES
Our graduates will be able to

1. Apply the knowledge of mathematics, science, engineering fundamentals, and an

engineering specialization to the solution of complex engineering problems.
2. Identify, formulate, review research literature, and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.
3. Design solutions for complex engineering problems and design system components or
processes that meet the specified needs with appropriate consideration for the public
health and safety, and the cultural, societal, and environmental considerations.
4. Use research-based knowledge and research methods including design of experiments,
analysis and interpretation of data, and synthesis of the information to provide valid
conclusions.
5. Create, select, and apply appropriate techniques, resources, and modern engineering
and IT tools including prediction and modeling to complex engineering activities with
an understanding of the limitations.
6. Apply reasoning informed by the contextual knowledge to assess societal, health, safety,
legal and cultural issues and the consequent responsibilities relevant to the professional
engineering practice.
7. Understand the impact of the professional engineering solutions in societal and
environmental contexts, and demonstrate the knowledge of, and need for sustainable
development.
8. Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
9. Function effectively as an individual, and as a member or leader in diverse teams, and in
multidisciplinary settings.
10. Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and
receive clear instructions.
11. Demonstrate knowledge and understanding of the engineering and management
principles and apply these to one’s own work, as a member and leader in a team, to
manage projects and in multidisciplinary environments.
12. Recognize the need for, and have the preparation and ability to engage in independent
and life-long learning in the broadest context of technological change.

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Course Outcomes
Students will be able to:

Design and simulate combinational and sequential digital circuits using

18ECL77.1 Verilog HDL.

18ECL77.2 Understand the synthesis process of digital circuits using EDA tool

Perform ASIC design 昀氀ow and understand the process of synthesis,

18ECL77.3 synthesis constraints and evaluating the synthesis reports to obtain
optimum gate level net list.

Design and simulate basic CMOS circuits like inverter, common source
18ECL77.4
ampli昀椀er and di昀昀erential ampli昀椀ers.

18ECL77.5 Perform RTL-GDSII 昀氀ow and understand the stages in ASIC design.

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CO’s – PO’s –Mapping

Academic Year: 2021-22

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
COs
18ECL77.1 3 3 3 3 3 3

18ECL77.2 3 3 3 3

18ECL77.3 3 3 3 3

18ECL77.4 3 3 3 3 3 3

18ECL77.5 3 3 3 3 3

SUM 12 6 6 6 15 9 9 15

AVERAGE 3 3 3 3 3 3 3 3

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CONTENTS

# Topic. Page No
Syllabus
Rules & Guidelines for conducting Lab-Work
Cycle of experiments
Part A – Analog Design 1-5
1. Inverter 6-30
2. NAND
3. Common source amplifier
4. Op-amp

Part – B Digital Design

1. 4-bit up/down Asynchronous reset counter

2. 4 bit Adder
3. UART
4. 32 bit ALU
5. Flip flop - D, SR, JK
Viva questions

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VLSI LABORATORY
SEMESTER – VII
[As per Choice Based Credit System (CBCS) Scheme]
Laboratory Code 18ECL77 CIE Marks 40
Number of Lecture 02Hr Tutorial (Instructions)
SEE Marks 60
Hours/Week + 02 Hours Laboratory
RBT Level L1, L2, L3 Exam Hours 03
CREDITS – 02
Course objectives: This course will enable students to:
• Design, model, simulate and verify CMOS digital circuits
• Design layouts and perform physical verification of CMOS digital circuits
• Perform ASIC design flow and understand the process of synthesis, synthesis constraints and
evaluating the synthesis reports to obtain optimum gate level netlist
• Perform RTL-GDSII flow and understand the stages in ASIC design
Experiments can be conducted using any of the following or equivalent design tools:
Cadence/Synopsis/Mentor Graphics/Microwind
Laboratory Experiments:
Part -A
Analog Design
Use any VLSI design tools to carry out the experiments, use library files and technology files below
180 nm.
1. a).Capture the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths of
inverter with Wn = Wp, Wn = 2Wp, Wn = Wp/2 and length at selected technology. Carry out the
following:
i. Set the input signal to a pulse with rise time, fall time of lns and pulse width of l0ns and time period
of 20ns and plot the input voltage and output voltage of designed inverter?
ii. From the simulation results compute tpHL, tpLH and td for all three geometrical settings of width?
iii. Tabulate the results of delay and find the best geometry for minimum delay for CMOS inverter?
1. b) Draw layout of inverter with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC and
LVS, extract parasitic and perform post layout simulations, compare the results with pre-layout
simulations. Record the observations.
2. a) Capture the schematic of 2-input CMOS NAND gate having similar delay as that of CMOS inverter
computed in experiment 1. Verify the functionality of NAND gate and also find out the delay td for
all four possible combinations of input vectors. Table the results. Increase the drive strength to 2X
and 4X and tabulate the results.
2. b) Draw layout of NAND with Wp/Wn = 40/20, use optimum layout methods. Verify for DRC and LVS,
extract parasitic and perform post layout simulations, compare the results with pre-layout
simulations. Record the observations.
3.a) Capture schematic of Common Source Amplifier with PMOS Current Mirror Load and find its transient
response and AC response? Measures the Unity Gain Bandwidth (UGB), amplification factor by
varying transistor geometries, study the impact of variation in width to UGB.
3. b) Draw layout of common source amplifier, use optimum layout methods. Verify for DRC and LVS,
extract parasitic and perform post layout simulations, compare the results with pre-layout
simulations. Record the observations.

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4.a) Capture schematic of two-stage operational amplifier and measure the following:
i UGB
ii. dB bandwidth
iii. Gain margin and phase margin with and without coupling capacitance
iv. Use the op-amp in the inverting and non-inverting configuration and verify its functionality
v. Study the UGB, 3dB bandwidth, gain and power requirement in op-amp by varying the stage
wise transistor geometries and record the observations.
4. b) Draw layout of two-stage operational amplifier with minimum transistor width set to 3 to 300(in180/
90/45nm technology), choose appropriate transistor geometries as per the results obtained in 4.a.
Use optimum layout methods. Verify for DRC and LVS, extract parasitic and perform post layout
simulations, compare the results with pre-layout simulations. Record the observations.
Part - B
Digital Design
Carry out the experiments using semicustom design flow or ASIC design flow, use technology
library 180/90/45nm and below
Note: The experiments can also be carried out using FPGA design flow, it is required to set appropriate
constraints in FPGA advanced synthesis option.
1.Write verilog code for 4-bit up/down asynchronous reset counter and carry out the following:
a. Verify the functionality using test bench
b. Synthesize the design by setting area and timing constraint. Obtain the gate level netlist find the
critical path and maximum frequency of operation. Record the area requirement in terms of
number of cells required and properties of each cell in terms of driving strength, power and area
requirement.
c. Perform the above for 32-bit up/down counter and identify the critical path, delay of critical path,
and maximum frequency of operation, total number of cells required and total area.
2. Write verilog code for 4-bit adder and verify its functionality using test bench. Synthesize the
design by setting proper constraints and obtain the net list. From the report generated identify critical
path, maximum delay, total number of cells, power requirement and total area required. Change the
constraints and obtain optimum synthesis results.
3. Write verilog code for UART and carry out the following:
a.Perform functional verification using test bench
b. Synthesize the design targeting suitable library and by setting area and timing constraints
c. For various constrains set, tabulate the area, power and delay for the synthesized netlist
d. Identify the critical path and set the constraints to obtain optimum gate level netlist with suitable
constraints
4.Write verilog code for 32-bit ALU supporting four logical and four arithmetic operations, use case
statement and if statement for ALU behavioral modeling.
a.Perform functional verification using test bench
b. Synthesize the design targeting suitable library by setting area and timing constraints
d. For various constrains set, tabulate the area, power and delay for the synthesized netlist
e. Identify the critical path and set the constraints to obtain optimum gate level netlist with suitable
constraints
Compare the synthesis results of ALU modeled using IF and CASE statements.
5. Write verilog code for Latch and Flip-flop, Synthesize the design and compare the synthesis report (D,
SR, JK).
6. For the synthesized netlist carry out the following for any two above experiments:
a.Floor planning (automatic), identify the placement of pads
b. Placement and Routing, record the parameters such as no. of layers used for routing, flip method
for placement of standard cells, placement of standard cells, routes of power and ground, and
routing of standard cells

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c. Physical verification and record the LVS and DRC reports

d. Perform Back annotation and verify the functionality of the design

e. Generate GDSII and record the number of masks and its color composition

Course Outcomes: On the completion of this laboratory course, the students will be able to:
1. Design and simulate combinational and sequential digital circuits using Verilog HDL
2. Understand the Synthesis process of digital circuits using EDA tool.
3. Perform ASIC design flow and understand the process of synthesis, synthesis constraints and
evaluating the synthesis reports to obtain optimum gate level net list
4. Design and simulate basic CMOS circuits like inverter, common source amplifier and differential
amplifiers.
5. Perform RTL-GDSII flow and understand the stages in ASIC design

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Rules & Guidelines for conducting Lab-Work

 Conduct yourself in a responsible manner at all times in the laboratory. Don’t talk aloud
or crack jokes in lab.
 A lab coat should be worn during laboratory experiments. Dress properly during a
laboratory activity. Long hair, dangling jewellery and loose or baggy clothing are a
hazard in the laboratory.
 Observe good housekeeping practices. Replace the materials in proper place after work to
keep the lab area tidy.
 Do not wander around the room, distract other students, startle other students or interfere
with the laboratory experiments of others.
 Do not eat food, drink beverages or chew gum in the laboratory and do not use laboratory
glassware as containers for food or beverages.
 Students are not allowed to touch any equipment or other materials in the laboratory
area until you are instructed by Faculty or Instructor.
 Before starting Laboratory work follow all written and verbal instructions carefully. If
you do not understand a direction or part of a procedure, ASK YOUR CONCERNED
FACULTY BEFORE PROCEEDING WITH THE ACTIVITY.
 If you do not understand how to use a piece of equipment, ASK THE FACULTY &
INSTRUCTOR FOR HELP!
 Perform only those experiments authorized by your Faculty. Carefully follow all
instructions, both written and oral.
 Students are not allowed to work in Laboratory alone or without presence of the
Faculty or Instructor.
 Any failure / break-down of equipment must be reported to the Instructor.
 Protect yourself from getting electric shock.
 Without Fail bring the observation book, record and Manual for each Lab session.
 Compulsory fill the lab test form before coming to lab.
 Ensure that safety devices are adequate, appropriate and in good working order.

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DO's
 Be on time to LAB sessions.
 Do wear ID card and follow dress code.
 Do log off the computers when you leave the LAB.
 Do ask for assistance if you need help.
 Do keep your voice low when speaking to others in the LAB.
 Do ask for assistance in downloading any software.
 Do make suggestions as to how we can improve the LAB.
 In case of any hardware related problem, ask LAB in charge for solution.
 If you are the last one leaving the LAB, make sure that the staff in charge of the
LAB is informed to close the LAB.
 Do keep the LAB as clean as possible.

DONT'S
 Do not use mobile phone inside the LAB.
 Don’t do anything that can make the LAB dirty (like eating, throwing waste papers etc).
 Do not carry any external devices without permission.
 Don’t move the chairs of the LAB.
 Don’t interchange any part of one computer with another.
 Don’t leave the computers of the LAB turned on while leaving the LAB.
 Do not install or download any software or modify or delete any system files on any LAB.
 Do not damage, remove, or disconnect any labels, parts, cables, or equipment.
 Don’t attempt to bypass the computer security system.
 Do not read or modify other user’s file.
 If you leave the lab, do not leave your personal belongings unattended. We are not
responsible for any theft.

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SAFETY MEASURES IN LABORATORY

1. Do not run inside the Computer Lab.
2. Take a note of all the exits in the room, and also take note of the location of
fire extinguishers in the room for the sake of fire safety.
3. Keep bags and coats in the designated area, as they can cause people to trip if they
are simply lying around the room.
4. Try not to type continuously for extremely long periods.
5. Look away from the screen once in a while to give your eyes a rest.
6. Do not touch any exposed wires or sockets.
7. Avoid making loud noises and speaking loudly.
8. Do not attempt to open any machines, and do not touch the backs of machines when
they are switched on.
9. Do not spill water or any other liquid on the machine, in order to maintain
electrical safety.
10. Do not bring any food or drinks near the machine.

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CYCLE – I

1. Inverter
2. NAND
3. 4-bit up/down Asynchronous reset counter
4. 4 bit Adder
CYCLE – II

5. Common source amplifier

6. UART

7. 32 bit ALU

CYCLE – III

8. Op-amp

9. Flip flop - D, SR, JK

LAB INTERNAL

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Alva’s Ins琀椀tute of Engineering & Technology

Shobhavana Campus, Mijar, Moodbidri, D.K-574225

Department of Electronics and Communication Engineering

Internal Test Sheet

Name of the Student

USN 4AL

Semester / Section

Lab Name / Lab Code

Staff Incharges
Sl No. Name of the Staff Signature
1
2
3

Total Marks: 20

# Parameter Maximum Marks

1 Write-up 4
2 Conduction 8
3 Viva 4
4 Record 2
5 Attendance 2
Name of the Experiment /
# 1 2 3 4 5 Total
Program
T-1

T-2

T-3
Average Marks Scored

Signature of Valuator with date

1.
2. Marks
3. Obtained Max
Marks HOD

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Lab Wise Test Score Sheet

Date of A R C V T
# Name of the Experiment
Conduction (2M) (2M) (4M) (2M) (10M)

1. Inverter

2. NAND

3. Common source amplifier

4. Op-amp

4-bit up/down Asynchronous reset

5. counter

6. 4 bit Adder

7. UART

8. 32 bit ALU

9. Flip flop - D, SR, JK

Unit
Test 1
Unit
Test 2

TOTAL

Staff 1 Signature

Staff 2 Signature

HOD

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VLSI Lab Manual 18ECEL77

PART – A ANALOG DESIGN

PROCEDURE FOR ANALOG DESIGN

CUSTOM IC DESIGN FLOW

Speci昀椀ca琀椀ons

Schema琀椀c entry

Circuit simula琀椀on

Layout

Design rule check

Layout versus schema琀椀c

Parasi琀椀c RC extrac琀椀on

Back
annota琀椀on

GDS-II to foundry

AIET, Dept. of ECE 1

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VLSI Lab Manual 18ECEL77

INITIAL PROCEDURES:

1. After logging in, right click and

open terminal. cd ..

cd cadence_db

2. Get into the c shell by typing

the command csh

3. Run the shellscript by typing the

command source /home/install/cshrc

4. Check system is connected to LAN

Mount -a

5. Move inside the respective directory using the cd

command cd cadence

6. Invoke the analog design tool by using the command

virtuoso

After the virtuoso console opens up, maximize it. The linux terminal can be minimized.

7. In the virtuoso console, create your own library by following the steps –

File→New→Library

AIET, Dept. of ECE 2

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VLSI Lab Manual 18ECEL77

8. In the “New Library” window that opens up, fill in your library name (e.g.: Design2),
and then click on the option –

Attach to an existing technology library

9. A selection box named “Attach Library to Technology Library” will open. Select
“gpdk180” and click on OK.

AIET, Dept. of ECE 3

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VLSI Lab Manual 18ECL77

I. STEPS FOR DESIGN ENTRY:

1. In the virtuoso console, select the following –

File → New → Cellview

2. In the “New File” form that opens, browse for your library name, and in front of the Cell,
fill in the name of the schematic that is going to be entered (e.g.: inverter). Later, click
on OK.

3. A new design window opens, in which the schematic has to be entered.

AIET, Dept. of ECE 4

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VLSI Lab Manual 18ECL77

4. After the schematic entry, a symbol for the schematic has to be created in the
schematic editor window, by selecting the following –

Create → Cellview → From Cellview

During these steps, one more editor window will open up for the symbol entry.
The symbol generation procedures will be elaborated while describing the
experiments.
5. After symbol creation, both the editor windows can be closed. Now for the test circuit,
a new Cellview has to be created in the virtuoso console. Again, the detailed
procedures for the test circuit are elaborated while discussing the respective
experiments.

II. STEPS FOR SIMULATION AND LAYOUT:

The test circuit has to be simulated by launching ADE-L in the schematic editor window, and then
by choosing the respective analyses in ADE. The three main analyses that are performed are
transient, dc and ac. With output plotted in Y-axis, the details of these analyses are summarized
below –

Type of analysis X-axis Observation

Transient Time Waveform
DC Input Transfer characteristics
AC Frequency Bandwidth

After the circuit verification, the layout for the schematic has to be prepared using Layout-XL,
and the same has to be physically verified. The detailed procedures are explained with the
experiments.

AIET, Dept. of ECE 5

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VLSI Lab Manual 18ECL77

1. INVERTER
AIM
:
To simulate the schematic of the CMOS inverter, and then to perform the physical verification for
the layout of the same.

TOOL REQUIRED :
Cadence Tool

THEORY:
The inverter is universally accepted as the most basic logic gate doing a Boolean operation on a
single input variable. Fig.1 depicts the symbol, truth table and a general structure of a CMOS
inverter. As shown, the simple structure consists of a combination of an pMOS transistor at the
top and a nMOS transistor at the bottom.

Fig.1: Symbol, circuit structure and

truth table of a CMOS inverter

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–

semiconductor. The words "complementary-symmetry" refer to the fact that the typical digital
design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal
oxide semiconductor field effect transistors (MOSFETs) for logic functions. Two important
characteristics of CMOS devices are high noise immunity and low static power consumption.
Significant power is only drawn

AIET, Dept. of ECE 6

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VLSI Lab Manual 18ECL77

while the transistors in the CMOS device are switching between on and off states. Consequently,
CMOS devices do not produce as much waste heat as other forms of logic, for example transistor-
transistor logic (TTL) or NMOS logic, which uses all n-channel devices without p-channel
devices.

PROCEDURE :
The three initial steps before simulation are: schematic entry, symbol entry and test circuit entry.
The procedures are as detailed below –

I. DESIGN ENTRY:

1. In the schematic editor window, for the addition of instances, press “i”. This will open the
“Add Instance” window. In that window, browse for the library gpdk180, select the cell
pmos and then select the view symbol. Click on close.

2. The properties of the selected instance are displayed in the “Add Instance” window.
There is no need to modify any properties for this particular experiment. Click on Hide.

AIET, Dept. of ECE 7

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VLSI Lab Manual 18ECL77

3. The pmos symbol will move along with the cursor. Place it in the top mid-position, left-
click and then press Esc.

4. Similarly place nmos device, and then press Esc.

AIET, Dept. of ECE 8

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VLSI Lab Manual 18ECL77

5. Now, press “w” for placing wire, click on the respective nodes and connect them
through wire. Place the input and output wires as well. Complete the substrate
connections also.

6. After pressing Esc, press “p” for adding pins to the schematic diagram. In the “Add
Pin” window, enter the name of the pin (e.g.: in), and ensure its direction as input.

7. Click on Hide, and place the pin at the input. Later press Esc.

AIET, Dept. of ECE 9

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VLSI Lab Manual 18ECL77

8. Similarly, place the output pin with name “out” and direction output.

9. Complete the schematic by placing the instances “vdd” and “gnd”, which are in the
analogLib
library. Finally, click on “check & save” icon and observe the errors in the virtuoso console.

AIET, Dept. of ECE 10

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VLSI Lab Manual 18ECL77

In the schematic window, the errors will be highlighted with yellow boxes. Move those
boxes, correct the errors, and click on “check & save”. Correct all the errors that are
reported.

10. After the schematic entry is finished, a symbol for the design has to be created. For
this purpose, click on Create and follow the procedure –

Create → Cellview → From Cellview

The name comes by default, along with the other options. Click on OK.

AIET, Dept. of ECE 11

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VLSI Lab Manual 18ECL77

11. Another window opens, which shows the input and output pin configurations. Click on OK.

12. A symbol editor window opens up with the default symbol.

13. The default symbol can be deleted and the symbol as per our convention can
be created. For this purpose, click on the green colored edge of the symbol. Now the color
of the

AIET, Dept. of ECE 12

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VLSI Lab Manual 18ECL77

selected part changes into magenta. Press Delete and click again on the edge. The default
green box gets deleted, and a new symbol can be created. Now press Esc to come out of
the delete mode.

14. On the pulldown menu, Select Create → Shape → Line and click on the editor window.
Use the mouse to create the shape of a triangle. Alternatively, you can select Create →
Shape → Polygon as well. Use “right click” for making the line slant.

AIET, Dept. of ECE 13

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VLSI Lab Manual 18ECL77

15. After the triangle is complete, select Create → Shape → Circle, and then bring the cursor
in front of the triangle, and click once. Release the finger and move the mouse. After the
circle is generated, click once again to place it.

16. Now, click on the output wire and drag it in front of the circle. Similarly, join the output
pin to the wire. Later, select Create → Selection box and click on Automatic. The tool will
adjust the selection box around the created symbol automatically. You can similarly select
and drag the port names to the respective places. Finally, “check & save” and observe the
errors.

17. After the schematic and symbol entries, both the editor windows can be closed. Now
for creating a test circuit, create a new cellview from the virtuoso console, and give the
name as “inverter_test”. When the editor window opens, press “i”, browse for your library
and select the inverter symbol which was created earlier. Place it in the middle of the
screen.

To ensure that the symbol is loaded correctly, you can click on the symbol and then
press “Shift E”. The schematic editor will move one level down, and the inverter’s
circuit entered

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earlier will be displayed on the screen. To come back to the symbol, press “Ctrl E”;
the symbol will be displayed back. Press Esc to unselect the symbol.

18. Place wires at the input and output, and place an output pin as well. These wires are
needed during simulation, to plot the voltage waveforms.

19. Press “i”, browse analogLib library and select “vpulse” and its symbol.

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20. In the property window, enter Voltage1 as 0 and Voltage2 as 1.8. Similarly enter
Period as 40n and Pulse width as 20n, without the space in between. No need to enter the
units; they appear automatically. Place the “vpulse” at the input wire. Connect “gnd” at the
other end.

21. Similarly, browse for the instance “vdc”, and enter its DC voltage as 1.8.

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22. Place “vdc” at the front, and connect “vdd” and “gnd” accordingly. Finally “check &
save”. The test circuit is complete now, and ready to be simulated.

Note: The library gpdk180 contains the technology dependent components (180nm), and the
library
analogLib contains the technology independent components.

Whenever a component needs to be selected, place the cursor on the component and click on it.
The selected component’s boundary turns into magenta color. Now the properties of the
component can be verified by pressing “q”, after which the property window opens.

To zoom a particular portion of the screen, right click, hold, and move the mouse. A yellow
colored boundary will be drawn on the screen. When the finger is released, the highlighted portion
gets zoomed. To come back to the original screen, press “f”. Alternatively, “Ctrl Z” and “Shift Z”
can be used, to zoom in and zoom out.

After the symbol is entered, Shift and E can be used together to move one level down, to view the
schematic diagram. Later, Ctrl and E can be used together to move one level up, to the symbol.

The hot key functions that are used during design entry are summarized as follows –

Hot key Function

i Instance
w Wire
p Pin
m Stretch
q Property
r Rotate
u Undo
c Copy
f Fit to screen
Esc Exit

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II. SIMULATION:

1. In the test circuit’s editor window, click on Launch → ADE L. A new window will open.

2. Click on Analyses → Choose. A new window will open, in which select “tran”. Fill the
stop time as 100n, and select liberal. Later, click on Apply.

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3. Now select “dc” on the Choosing Analyses window, and click on Save DC Operating
Point. Click on the Component Parameter. A Select Component option will pop up.

4. Double click on Select Component. The ADE window gets minimized, and the schematic
is shown. Click on the component “vpulse”. In the new window that opens up, click on the
top most parameter dc and then click on OK.

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5. Ensure that the component name and parameter name are updated. Now in the Sweep
range, enter 0 and 1.8 in the Start and Stop options respectively. Later, click on Apply.

6. In the ADE window, ensure that the Analyses fields are updated for tran and dc.

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7. Now to select the stimulus and response points, in the ADE window, click on Outputs →
To be plotted → Select on Schematic. In the schematic window, click on input and
output wires. These wires will become dotted lines when selected. Later, press Esc.

8. In the ADE window, check that the Outputs fields are updated. Now click on Simulation
→ Netlist and Run. The waveform window will open and the simulation results are
displayed. Transient response is displayed on the left side and DC response on the right.
Click on the transient response waveform and then click on the fourth icon at the top (Strip
chart mode). The input and output waveforms are displayed separately. You can “right
click” on each waveform, and then edit the properties of the display such as color and
appearance. Similarly, the transfer characteristics can be observed at the right hand side.

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III. LAYOUT:

1. For preparing the layout of the inverter, all the other windows can be closed, except for the
virtuoso console. In the console, open the schematic of the inverter and click on Launch
→ Layout XL. In the Startup Option, click on OK.

2. In the New File option, the tool selects the view as layout by default. Click on OK.

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3. The tool opens the LSW and the Layout suite.

4. Maximize the layout suite and click on Connectivity → Generate → All from Source. A
Generate Layout window will open, with default attributes. Click on OK.

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5. The layout suite displays a cyan colored box in the first quadrant, which is the Photo-
Resist boundary. In addition, in the fourth quadrant, the default layouts of pmos and nmos
transistors are displayed, along with four blue squares, which are the nodes - vdd, gnd,
input & output.

6. Press “Shift F” to see all the layers within the default layout. Hold the “right click” and
move the mouse to zoom a selected portion, and observe the layout carefully. The color
details are – Orange border: n-well, Red border: p-diffusion’s boundary, Yellow
border: n-diffusion’s boundary, Green: diffusion, Rose: polysilicon, Yellow square:
contact cut, Blue: metal1.

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7. Click on the pmos device and drag it into the PR boundary. The layout can be moved
either vertically or horizontally, not diagonally. During this movement, the tool keeps
displaying the connections of the terminals with the nodes. After placing the pmos device,
place the nmos device below it. If the space is insufficient, the PR boundary can be
enlarged, through the top and the right edges. For this purpose, press “s” and click on the
edge of the PR boundary. (“s”
is for stretch, in the layout suite). The selected edge will turn into magenta color. Now
release the finger and move the mouse till the desired area, and click again. Later, press
Esc.

8. After placing the devices, zoom the space in between the transistors. In the LSW, select
Poly. Now in the layout suite, press “p”, place the mouse at the middle of the gate’s
lower contact of pmos device, and click once. (“p” is for path, in the layout suite). Release
the finger and move the mouse downwards. The poly path will move along with the
mouse. Move the mouse until the gate area of the nmos device gets overlapped. Bring the
cursor exactly to the middle of the path and double click. The poly path between the gates
gets realized. The area can be zoomed further, and the devices can be moved, for the exact
overlapping of the poly layers.

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9. In the LSW, select Metal1. Using the same procedure, draw the paths for “vdd” at the top
and “gnd” at the bottom. Later, using the same metal path, connect the source of pmos
device to “vdd” and that of nmos device to “gnd”. Finally, connect both the drains for the
output path.

10. Now move to the fourth quadrant where the four blue squares are displayed. Click on one
of them; it will turn into magenta color. Press “q”, and then click on Connectivity, to see
its properties. If it is vdd, drag it and place it on the upper metal path. Later, place the gnd
on the lower path; similarly, place the output pin. Now, place the input pin in front of the
poly and connect through a poly path.

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11. Now, for connecting the input metal pin to the poly path, a via needs to be placed. Hence,
in the layout suite click Create → Via. In the Via Definition pull-down menu, select the
via M1_POLY1. Click on Hide, and place the via on the input pin. Press Esc.

12. Similarly, for the substrate connections, select the via M1_NWELL and place it touching
the n-well, and connect it to “vdd” through a metal path. Later, place the via M1_PSUB on
the “vss” path, for the substrate connection of nmos device; the Black background itself
indicates the p-substrate. (p-device resides on n-well and n-device resides directly on p-
substrate).

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13. As the layout is now complete, its verification can be performed. In the layout suite, click
on Assura → Run DRC. Give the run name as “inverter” and verify the output. If there
are errors, the tool will highlight those areas in White color. The errors will be displayed
in the ELW, and the location of each error can be known, by selecting the error in ELW,
and then clicking on the arrow mark available in ELW. Correct those errors and rerun
DRC.

14. After the DRC check, click on Assura → Run LVS, and verify the output. Correct the
errors.

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15. After the LVS check, click on Assura → Run RCX. Click OK on the form that appears.

16. After the RCX is run, the output is saved in your library as av_extracted. In the virtuoso
console, open the “inverter” file with view as av_extracted, and observe the output. The
layout can be enlarged and the parasitic components can be observed. Each components
value can be checked, by selecting the component and pressing “q”.

If the parasitic component values are beyond the limits, then the layout can be optimized in the
layout suite, for the reduction of the parasitic component values; later on, the layout can be back-
annotated with the existing parasitic components, and simulation can be performed, for verifying
the output.

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RESULT:
a. The schematic for the inverter is drawn and verified the following: DC Analysis,
Transient Analysis
b. The Layout for the inverter is drawn and verified the DRC, LVS, RC Extraction.

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2. TWO INPUT CMOS NAND GATE

AIM:
To simulate the schematic of the common source amplifier, and then to perform the physical
verification for the layout of the same.

TOOL REQUIRED:
Cadence Tool

THEORY:

The NAND gate or “Not AND” gate is the combination of two basic logic gates, the AND gate and the NOT
gate connected in series. The NAND gate and NOR gate can be called the universal gates since the
combination of these gates can be used to accomplish any of the basic operations. Hence, NAND gate and
NOR gate combination can produce an inverter, an OR gate or an AND gate.

The output of a NAND gate is high when either of the inputs is high or if both the inputs are low. In other
words, the output is always high and goes low only when both the inputs are high. The logic NAND function
is given by the Boolean expression Y ¿ AB . Here A, B are the inputs and Y is the output.
The Boolean expression given for a NAND gate is that of logical addition and it is opposite to AND gate.
The Boolean expression is given by a single dot (.) with an over line over the expression to show the NOT or
the logical negation of the NAND gate.
CIRCUIT DIAGRAM :

1. Circuit diagram in schematic entry

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2. Design entry for the test circuit

Library name Cellview name Properties/Comments

myDesignLib nand Symbol

analogLib Vdc (V0, V1,V2) V1 = 0; V2 = 1.8
analogLib gnd

3. Test circuit

4. Output waveform

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5. Layout:

6. Extracted wave

RESULT:

• The schematic for the operational amplifier is drawn and verified

the following: DC Analysis, AC Analysis and Transient Analysis.
• The Layout for the operational amplifier is drawn and verified
the DRC, LVS, RC Extraction.

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3. COMMON SOURCE AMPLIFIER

AIM :
To simulate the schematic of the common source amplifier, and then to perform the physical
verification for the layout of the same.

TOOL REQUIRED :
Cadence Tool

THEORY:
In electronics, a common-source amplifier is one of three basic single-stage field-effect transistor
(FET) amplifier topologies, typically used as a voltage or transconductance amplifier. The easiest
way to tell if a FET is common source, common drain, or common gate is to examine where
the signal enters and leaves. The remaining terminal is what is known as "common". In this
example, the signal enters the gate, and exits the drain. The only terminal remaining is the source.
This is a common-source FET circuit. The analogous bipolar junction transistor circuit is the
common-emitter amplifier.

The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a

voltage amplifier. (See classification of amplifiers). As a transconductance amplifier, the
input voltage is seen as modulating the current going to the load. As a voltage amplifier, input
voltage modulates the amount of current flowing through the FET, changing the voltage
across the output resistance according to Ohm's law. However, the FET device's output
resistance typically is not high enough for a reasonable transconductance amplifier (ideally
infinite), nor low enough for a decent voltage amplifier (ideally zero). Another major drawback is
the amplifier's limited high-frequency response.

CIRCUIT DIAGRAM :
Vdd

Vbias

Vout

Vi
n
Vss

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1. Circuit diagram in schematic entry

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2. Design entry for the test circuit

Library name Cellview name Properties/Comments

myDesignLib cs_amplifier Symbol
analogLib vsin Define pulse specification as AC
Magnitude=1; DC Voltage=0; Offset
Voltage=0; Amplitude=5m; Frequency=1K
analogLib vdd,vss,gnd vdd=2.5; vss= -2.5; vbias= -2.5

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3.Output Waveform

RESULT:
a. The schematic for the common source amplifier is drawn and verified the following:
DC Analysis, DC Analysis, Transient Analysis.
b. The Layout for the common source amplifier is drawn and verified the DRC,
LVS, RC Extraction.

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4. OPERATIONAL AMPLIFIER

To simulate the schematic of the operational amplifier, and then to perform the physical
verification for the layout of the same.

TOOL REQUIRED:
Cadence Tool

THEORY:
An operational amplifier (often op-amp or opamp) is a DC-coupled high-gain electronic voltage
amplifier with a differential input and, usually, a single-ended output. In this configuration, an op-
amp produces an output potential (relative to circuit ground) that is typically hundreds of thousands
of times larger than the potential difference between its input terminals. Operational amplifiers had
their origins in analog computers, where they were used to perform mathematical operations in
many linear, non-linear and frequency- dependent circuits. The popularity of the op-amp as a
building block in analog circuits is due to its versatility. Due to negative feedback, the
characteristics of an op-amp circuit, its gain, input and output impedance, bandwidth etc. are
determined by external components and have little dependence on temperature coefficients or
manufacturing variations in the op-amp itself.
Op-amps are among the most widely used electronic devices today, being used in a vast array of
consumer, industrial, and scientific devices. Many standard IC op-amps cost only a few cents in
moderate production volume; however some integrated or hybrid operational amplifiers with
special performance specifications may cost over $100 US in small quantities. Op-amps may be
packaged as components, or used as elements of more complex integrated circuits. The op-amp is
one type of differential amplifier.
The amplifier's differential inputs consist of a non-inverting input (+) with voltage V+ and an
inverting input (–) with voltage V−; ideally the op-amp amplifies only the difference in voltage
between the two, which is called the differential input voltage. The output voltage of
the op-amp Vout is given by the equation: Vout = AOL(V+ - V-)

where AOL is the open-loop gain of the amplifier (the term "open-loop" refers to the absence of a
feedback loop from the output to the input).

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CIRCUIT DIAGRAM :

7. Circuit diagram in schematic entry

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8. Design entry for the test circuit

Library name Cellview name Properties/Comments

myDesignLib Diff_amplifier Symbol

analogLib Vsin Define Pulse specifications
AC Magnitude=1; DC Voltage=0;
Offset Voltage=0; Amplitude=5m;
Frequency=1K
analogLib vdd,vss,gnd vdd=2.5; vss= -2.5;

analogLib Idc Dc current = 30u

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9. Test circuit

10. Output waveform

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RESULT:
• The schematic for the operational amplifier is drawn and verified
the following: DC Analysis, AC Analysis, Transient Analysis.
• The Layout for the operational amplifier is drawn and verified
the DRC, LVS, RC Extraction.

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PART- A: DIGITAL DESIGN

ASIC DIGITAL DESIGN FLOW

Note:
1. Verify system date, time and LAN connection.
2. Verify the connection between server and client using IP address of the server.
Ex: ping 192.168.40.100

Tools used for ASIC Flow:

1. INCISIVE - Used for Functional Simulation

2. GENUS - Used for Synthesis and pre-Layout Timing Analysis
3. INNOVUS - Used for Physical Design

Getting Started :

1. Make sure the Licensing Server is switched ON and the client is connected to server.”
2. Open the “counter” directory and make a right click to “Open in Terminal”.
3. To open the tools to be used, type in the command “csh” (Press Enter) followed by “source
/home/install/cshrc” <Or the path of tools whichever is applicable>.
4. A welcome string “Welcome to Cadence Tool Suite” appears indicating terminal
ready to invoke Cadence Tools available for you.

Module 1: Creating an RTL Code

In order to create an RTL Code, you can open a text editor and type in your Verilog code
or VHDL Code.

1. In the terminal, type in “gedit <filename>.v [OR] <filename>.vhdl”. The file extensions
depends on the type of RTL Code you write as shown.

2. Similarly, using same command, Test Bench also could be written as shown below.

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1) Write verilog code for 16-bit up/down synchronous counter and verify its
functionality using test bench

Test Bench for the Up-Down Counter

Module 2: Functional Simulation

1. To perform Functional Simulation, “Incisive” tool is to be used.

2. In your terminal, type the command “nclaunch -new” to open the tool.

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3. Select “Multiple Step”. And then select “Create cds.lib”

Note : The ‘-new’ switch is used only for the first time the design is being run. For the next
time on wards, the command to be used could be ‘nclaunch’ only.

4. Save the cds.lib file. It is a tool file that holds the design location information for easy
access by the tool.

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5. Based on the Libraries available and the type of RTL Code written, one of the three shown
above is to be selected. Cadence tool suite provides default gpdk libraries. Here, counter
RTL is of Verilog Format and hence third option is selected.
6. A new pop-up “nclaunch” opens which will contain all the .v and .vhdl files as per the
cds.lib file created.
7. Functional Simulation using Cadence runs in 3 stages:
➔ Compilation of Verilog/VHDL Code and/or Test Bench
➔ Elaboration of the Code & Test Bench Compiled
➔ Simulating the Test Bench or Top Module[in absence of Test Bench]

8. A set of tools are shown in the nclaunch window which refer to VHDL Compiler, Verilog
Compiler, Elaborator, Simulator corresponding from Left To Right.
9. Select the .v or .vhdl files to be compiled and launch Compiler. On successful completion
of compilation, on the Right hand Side, the modules appear under “Worklib” .
10. Select the Module under Worklib and “Launch Elaborator” . On successful
completion of Elaboration, “Snapshots” are generated.
11. Select the Test Bench under snapshots and “Launch Simulator” .
12. The above steps are depicted under following snapshosts.

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The Design Browser pops-up and The Test Bench Module name can be seen on the left and
the Pin list on the right when selected. For Simulation, The number of Pins / Ports to be
simulated can be selected.

Make a right click on the selected and Select “Send to Waveform Window”.

In the waveform window, we can see different ports in the design. Now click on the Run

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simulation key to start the simulation. Use the ‘pause’ key to interrupt or stop the
simulation. Use different options like zoom in, zoom out etc to analyze the plot.

Module 3: Synthesis
Inputs for Synthesis:
1. RTL Code (.v or .vhdl)
2. Chip Level SDC (System Design Constraints)
3. Liberty Files (.lib)
Expected Outputs of Synthesis :
1. Gate Level Netlist
2. Block Level Netlist
3. Timing, Area, Power reports

Synthesis is a 3-stage process which converts Virtual RTL Logic into Physical Gates in order
to give a Physical Shape to the design through Physical Design.

Synthesis runs in following stages:

* Translation - RTL Codes are compiled

* Elaboration / Mapping - Pieces of Logic are replaced with
corresponding Gates from Libraries with same Functionality
* Optimization - Tool tries to reduce cell count without affecting
the functionality

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To run the synthesis, the following script can be used.

Chip Level SDC is as follows :

Close out all INCISIVE windows and in the same terminal type in the following
command to run Synthesis.
genus -f rc_script.tcl

The tcl [Tool Command Language] script runs executing each command one after the
other.
A window of Genus GUI pops – up with the top hier cell on the le昀琀 top. Make a
right click and select Schema琀椀c Viewer → In Main.

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The Gate level Circuit that implements the RTL Logic can be seen and analysed.

As from the script, Block Level SDC, Gate Level Netlist, Timing, Power and Area reports are
generated which are readable.

The Timing report gives the path with Worst timing.

The area report gives Cell count and Total area occupied by them.
The total power consumed by those cells are given in Power report.

Module 4: Physical Design

Mandatory Inputs for PD:

1. Gate Level Netlist [Output of Synthesis]

2. Block Level SDC [Output of Synthesis]
3. Liberty Files (.lib)
4. LEF Files (Layer Exchange Format)

Expected Outputs from PD:

1. GDS II File (Graphical Data Stream for Information Interchange – Feed In for
Fabrication Unit).

Close out all windows relating to Genus and in the terminal, type the command

innovus (Press Enter)

For Innovus tool, a GUI opens and also the terminal enters into innovus command
prompt where in the tool commands can be entered.

Physical Design involves 5 stages as following:

After Importing Design,

* Floor Planning
* Power Planning
* Placement
* CTS (Clock Tree Synthesis)
* Routing
*
Module 4.1: Importing Design
To Import Design, all the Mandatory Inputs are to be loaded and this can be done using

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script files named with .globals and .view/.tcl

Globals File to import design using Mandatory Inputs

The Globals file reads in the LEF’s and Gate Level Netlist and .view file implicitly.

The .view file reads Liberty Files and Block Level SDC to create various PVT Corners for
analysis.
In the terminal command prompt, type the commands as shown. The design is imported
and “Core Area” is calculated by tool and shown on GUI.

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The Horizontal Lines on the GUI across the Core Area are alternative VDD and VSS tracks
and Standard Cell Placement Rows.

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Module 4.2: Floorplan

Steps under Floorplan :

1. Aspect Ratio [Ratio of Vertical Height to Horizontal Width of Core]

2. Core Utilisation [The total Core Area % to be used for Floor Planning]
3. Channel Spacing between Core Boundary to IO Boundary

Select Floorplan → Specify Floorplan to modify/add concerned values to the above Factors.

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On adding/modifying the concerned values, the core area is also modified.

The Yellow patch on the Left Bottom are the group of “Unassigned pins” which are to be
placed along the IO Boundary along with the Standard Cells [Gates].

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Module 4.3: Power Planning

Steps under Power Planning:
1. Connect Global Net Connects
2. Adding Power Rings
3. Adding Power Strings
4. Special Route

During the stage of Importing Design, under the Globals file, Two command lines state the
names of Power and Ground Nets.

However, in order to Current flow through these Power nets, they are to converge at a
point, preferably a common net connected to a Pin.

Under Connect Global Net Connects, we create two pins, one for VDD and one for VSS
connecting them to corresponding Global Nets as mentioned in Globals file.

Select Power → Connect Global Nets.. to create “Pin” and “Connect to Global Net” as
shown and use “Add to list”.

Click on “Apply” to direct the tool in enforcing the Pins and Net connects to Design and
then Close the window.

In order to Tap in Power from a distant Power supply, Wider Nets and Parallel connections

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improve efficiency. Moreover, the cells that would be placed inside the core area are
expected to have shorter Nets for lower resistance.

Hence Power Rings [Around Core Boundary] and Power Stripes [Across Core Boundary]
are added which satisfies the above conditions.

Select Power → Power Planning → Add Rings to add Power rings ‘around Core
Boundary’.

* Select the Nets from Browse option OR Directly type in the Global Net Names separated by a
space being Case and Spelling Senstive.
* Select the Highest Metals marked ‘H’ [Horizontal] for Top and Bottom and Metals marked
‘V’ [Vertical] for Right and Bottom. This is because Highest metals have Highest Widths and
thus Lowest Resistance.
* Click on Update after the selection and “Set Offset : Center in Channel” in order to get the
Minimum Width and Minimum Spacing of the corresponding Metals and then Click “OK”.

* Similarly, Power Stripes are added using similar content to that of Power Rings.

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Factors to be considered under Power Stripes :

* Nets
* Metal and It’s Direction
* Width and Spacing [Updated]
* Set to Set Distance = ( Minimum Width of Metal + Min. Spacing ) x 2

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On adding Power Stripes, The Power mesh setup is complete as shown. However, There are
no Vias that could connect Metal 9 or Metal 8 directly with Metal 1 [VDD or VSS of
Standard Cells are generally made up of Metal 1].

The connection between the Highest and Lowest Metals is done through Stacking of Vias
done using “Special Route”.

To perform Special Route, Select Route → Special Route → Add Nets → OK.

After the Special Route is complete, all the Standard Cell Rows turn to the Color coded
for Metal 1 as shown below.

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The complete Power Planning process makes sure Every Standard Cell receives enough
power to operate smoothly.

Module 4.4.1 : Pre - Placement

* After Power Planning, a few Physical Cells are added namely, End Caps and Well
Taps.
* End Caps : They are Physical Cells which are added to the Left and Right Core
Boundaries acting as blockages to avoid Standard Cells from moving out of boundary.
* Well Taps : They act like Shunt Resistance to avoid Latch Up effects.

1. To add End Caps, Select Place → Physical Cell → Add End Caps and “Select” the FILL’s
from the available list. Higher Fills have Higher Widths. As shown Below, The End Caps are added
below your Power Mesh.

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2. To add Well Taps, Select Place → Physical Cell → Add Well Tap → Select → FillX
[X → Strength of Fill = 1,2,4 etc] → Distance Interval [Could be given in range of
30-45u] → OK

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Module 4.5: Placement

1. The Placement stage deals with Placing of Standard Cells as well as Pins.
2. Select Place → Place Standard Cell → Run Full Placement → Mode → Enable
‘Place I/O Pins’ → OK → OK .

All the Standard Cells and Pins are placed as per the communication between them, i.e.,
Two communicating Cells are placed as close as possible so that shorter Net lengths can be
used for connections as Shorter Net Lengths enable Better Timing Results.

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Placed Design

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Standard Cells Placed

You can toggle the Layer Visibility from the list on the Right.

Report Generation and Optimization :

➔ Timing Report :

To generate Timing Report, Timing → Report Timing → Design Stage – PreCTS

➔ Analysis Type – Setup → OK

The Timing report Summary can be seen on the Terminal.

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➔ Area Report :

To generate Area Report, Switch to the Terminal and type the command ,

report_area to see the Cell Count and Area Occupied.

➔ Power report :

To generate Power Report, In the Terminal type the command

report_power to see the Power Consumption numbers.

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Design Optimization :
To optimize the Design, Select ECO → Optimize Design → Design Stage [PreCTS] →
Optimization Type – Setup → OK

This step Optimizes your design in terms of Timing, Area and Power.

You can Generate Timing, Area, Power in similar way as above report Post – Optimization
to compare the Reports.

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Module 4.6: Clock Tree Synthesis

The CTS Stage is meant to build a Clock Distribution Network such that every Register
(Flip Flop) acquires Clock at the same time (Atleast Approximately) to keep them in proper
communication.

A Script can be used to Build the Clock Tree as follows :

Source the Script as shown in the above snapshot through the Terminal and then Select
Clock → CCOpt Clock Tree Debugger → OK to build and view clock tree.

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The Red Boxes are the Clock Pins of various Flip Flops in the Design while Yellow
Pentagon on the top represents Clock Source.

The Clock Tree is built with Clock Buffers and Clock Inverters added to boost up the Clock
Signal.

Report Generation and Design Optimization:

CTS Stage adds real clock into the Design and hence “Hold” Analysis also becomes
prominent. Hence, Optimizations can be done for both Setup & Hold, Timing Reports
are to be Generated for Setup and Hold Individually.

Setup Timing Analysis :

Hold Timing Analysis:

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For Area and Power Report Generation,

report_area & report_power commands can be used.

Design Optimizations:

Module 4.7: Routing

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* All the net connections shown in the GUI till CTS are only based on the Logical
connectivity.
* These connections are to be replaced with real Metals avoiding Opens, Shorts,
Signal Integrity [Cross Talks], Antenna Violations etc.
To run Routing, Select Route → Nano Route → Route and enable Timing Driven and SI
Driven for Design Physical Efficiency and Reliability.

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Report Generation and Design Optimization:

Setup Report:

Hold Report:

Area and Power Reports:

Use the commands report_area and report_power for Area and Power Reports
respectively.

Design Optimization:

Enter the above shown command in the Terminal in order to run the Design Optimization
first Post-Route.

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The Report generation is same as shown prior to Design Optimization.

Saving Database:

1. Saving Design => File → Save Design → Data Type : Innovus →

<DesignName>.enc → OK

2. Saving Netlist => File → Save → Netlist → <NetlistName>.v → OK

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It is recommended to save Netlist and Design at every stage.

To restore a Design Data Base, type source <DesignName>.enc in the terminal.

3. Saving GDS => File → Save → GDS/OASIS → <FileName>.gds → OK

The GDS File is a Binary Format File which is not Readable and is fed to the
Fabrication unit with data of various layers used depicted in terms of Geometrical
Shapes.

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2) Write verilog code for 4-bit up/down asynchronous reset counter and verify
its functionality using test bench

Verilog Code
module up_down_counter( clk, reset,up_down, counter );
input clk;
input reset;
input up_down;
output [3:0] counter;
reg [3:0] counter_up_down;

always @(posedge clk or posedge reset)

begin
if(reset)
counter_up_down <=4'h0;
else if(~up_down)
counter_up_down <= counter_up_down + 4'h1;
else
counter_up_down <= counter_up_down - 4'h1;
end
assign counter = counter_up_down;
endmodule

Test Bench Code

module updowncounter_testbench();
reg clk, reset,up_down;
wire [3:0] counter;

up_down_counter dut(clk, reset,up_down, counter);

initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
up_down=0;
#20;
reset=0;
#180;
up_down=1;
end
endmodule

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3) Write verilog code for 4-bit adder and verify its functionality using test
bench.

Verilog Code
module fulladd(input [3:0]a,input[3:0]b, input c_in,
output reg c_out, output reg[3:0]sum);
always@(a or b or c_in)
begin
{c_out,sum} = a+b+c_in;
end
endmodule

Test Bench code

module tb_fulladd;
reg [3:0]a;
reg [3:0]b;
reg c_in;
wire [3:0] sum;
integer i;
fulladd fa0(.a(a), .b(b), .c_in(c_in), .c_out(c_out), .sum(sum));

initial begin
a<=0;
b<=0;
c_in<=0;

$monitor("a=0x%0h, b=0x%0h, c_in=0x%0h, c_out=0x%0h, sum=0x%0h", a, b, c_in, c_out, sum);

for(i=0;i<5;i=i+1) begin
#10
a<=$random;
b<=$random;
c_in<=$random;
end
end
endmodule

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4) Write verilog code for UART and carry out the following verify its
functionality using test bench.

a) Functional Verification using Test Bench

Source Code – Transmitter:

// This code contains the UART Transmitter. This transmitter is able

// to transmit 8 bits of serial data, one start bit, one stop bit,
// and no parity bit. When transmit is complete o_Tx_done will be
// driven high for one clock cycle.
// Set Parameter CLKS_PER_BIT as follows:
// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 25 MHz Clock, 115200 baud UART
// (25000000)/(115200) = 217

module UART_TX
#(parameter CLKS_PER_BIT = 217)
(
input i_Clock,
input i_TX_DV,
input [7:0] i_TX_Byte,
output o_TX_Active,
output reg o_TX_Serial,
output o_TX_Done
);
parameter IDLE = 3'b000;
parameter TX_START_BIT = 3'b001;
parameter TX_DATA_BITS = 3'b010;
parameter TX_STOP_BIT = 3'b011;
parameter CLEANUP = 3'b100;

reg [2:0] r_SM_Main = 0;

reg [7:0] r_Clock_Count = 0;
reg [2:0] r_Bit_Index = 0;
reg [7:0] r_TX_Data = 0;
reg r_TX_Done = 0;
reg r_TX_Active = 0;

always @(posedge i_Clock)

begin

case (r_SM_Main)
IDLE :
begin
o_TX_Serial <= 1'b1; // Drive Line High for Idle
r_TX_Done <= 1'b0;

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r_Clock_Count <= 0;
r_Bit_Index <= 0;
if (i_TX_DV == 1'b1)
begin
r_TX_Active <= 1'b1;
r_TX_Data <= i_TX_Byte;
r_SM_Main <= TX_START_BIT;
end
else
r_SM_Main <= IDLE;
end // case: IDLE

// Send out Start Bit. Start bit = 0

TX_START_BIT :
begin
o_TX_Serial <= 1'b0;

// Wait CLKS_PER_BIT-1 clock cycles for start bit to finish

if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_START_BIT;
end
else
begin
r_Clock_Count <= 0;
r_SM_Main <= TX_DATA_BITS;
end
end // case: TX_START_BIT

// Wait CLKS_PER_BIT-1 clock cycles for data bits to finish

TX_DATA_BITS :

begin
o_TX_Serial <= r_TX_Data[r_Bit_Index];

if (r_Clock_Count < CLKS_PER_BIT-1)

begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;

if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= TX_DATA_BITS;

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end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= TX_STOP_BIT;
end
end
end // case: TX_DATA_BITS

// Send out Stop bit. Stop bit = 1

TX_STOP_BIT :
begin
o_TX_Serial <= 1'b1;

// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish

if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_STOP_BIT;
end
else
begin
r_TX_Done <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= CLEANUP;
r_TX_Active <= 1'b0;
end
end // case: TX_STOP_BIT
// Stay here 1 clock
CLEANUP :
begin
r_TX_Done <= 1'b1;
r_SM_Main <= IDLE;
end
default :
r_SM_Main <= IDLE;
endcase
end
assign o_TX_Active = r_TX_Active;

assign o_TX_Done = r_TX_Done;

endmodule

Source Code – Receiver:

// This file contains the UART Receiver. This receiver is able to

// receive 8 bits of serial data, one start bit, one stop bit,
// and no parity bit. When receive is complete o_rx_dv will be
// driven high for one clock cycle.

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//
// Set Parameter CLKS_PER_BIT as follows:
// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 25 MHz Clock, 115200 baud UART
// (25000000)/(115200) = 217
module UART_RX
#(parameter CLKS_PER_BIT = 217)
(
input i_Clock,
input i_RX_Serial,
output o_RX_DV,
output [7:0] o_RX_Byte
);

parameter IDLE = 3'b000;

parameter RX_START_BIT = 3'b001;
parameter RX_DATA_BITS = 3'b010;
parameter RX_STOP_BIT = 3'b011;
parameter CLEANUP = 3'b100;

reg [7:0] r_Clock_Count = 0;

reg [2:0] r_Bit_Index = 0; //8 bits total
reg [7:0] r_RX_Byte = 0;
reg r_RX_DV = 0;
reg [2:0] r_SM_Main = 0;

// Purpose: Control RX state machine

always @(posedge i_Clock)
begin

case (r_SM_Main)
IDLE :
begin
r_RX_DV <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;

if (i_RX_Serial == 1'b0) // Start bit detected

r_SM_Main <= RX_START_BIT;
else
r_SM_Main <= IDLE;
end

// Check middle of start bit to make sure it's still low

RX_START_BIT :
begin
if (r_Clock_Count == (CLKS_PER_BIT-1)/2)
begin
if (i_RX_Serial == 1'b0)
begin
r_Clock_Count <= 0; // reset counter, found the middle

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r_SM_Main <= RX_DATA_BITS;

end
else
r_SM_Main <= IDLE;
end
else
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_START_BIT;
end
end // case: RX_START_BIT
// Wait CLKS_PER_BIT-1 clock cycles to sample serial data
RX_DATA_BITS :
begin
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
r_RX_Byte[r_Bit_Index] <= i_RX_Serial;

// Check if we have received all bits

if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= RX_DATA_BITS;
end

else
begin
r_Bit_Index <= 0;
r_SM_Main <= RX_STOP_BIT;
end
end
end // case: RX_DATA_BITS

// Receive Stop bit. Stop bit = 1

RX_STOP_BIT :
begin
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_STOP_BIT;
end
else
begin
r_RX_DV <= 1'b1;

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r_Clock_Count <= 0;
r_SM_Main <= CLEANUP;
end
end // case: RX_STOP_BIT

// Stay here 1 clock

CLEANUP :
begin
r_SM_Main <= IDLE;
r_RX_DV <= 1'b0;
end

default :
r_SM_Main <= IDLE;

endcase
end

assign o_RX_DV = r_RX_DV;

assign o_RX_Byte = r_RX_Byte;

endmodule // UART_RX

Test bench :

// This testbench will exercise the UART RX.

// It sends out byte 0x37, and ensures the RX receives it correctly.

`timescale 1ns/10ps
`include "uart_tx.v"
`include "uart_rx.v"
module UART_TB ();
// Testbench uses a 25 MHz clock
// Want to interface to 115200 baud UART
// 25000000 / 115200 = 217 Clocks Per Bit.

parameter c_CLOCK_PERIOD_NS = 40;

parameter c_CLKS_PER_BIT = 217;
parameter c_BIT_PERIOD = 8600;

reg r_Clock = 0;
reg r_TX_DV = 0;
wire w_TX_Active, w_UART_Line;
wire w_TX_Serial;
reg [7:0] r_TX_Byte = 0;
wire [7:0] w_RX_Byte;
UART_RX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_RX_Inst
(.i_Clock(r_Clock),
.i_RX_Serial(w_UART_Line),
.o_RX_DV(w_RX_DV),

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.o_RX_Byte(w_RX_Byte)
);

UART_TX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_TX_Inst

(.i_Clock(r_Clock),
.i_TX_DV(r_TX_DV),
.i_TX_Byte(r_TX_Byte),
.o_TX_Active(w_TX_Active),
.o_TX_Serial(w_TX_Serial),
.o_TX_Done()
);
// Keeps the UART Receive input high (default) when

// UART transmitter is not active

assign w_UART_Line = w_TX_Active ? w_TX_Serial : 1'b1;

always
#(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;

34
// Main Testing:
initial
begin
// Tell UART to send a command (exercise TX)
@(posedge r_Clock);
@(posedge r_Clock);
r_TX_DV <= 1'b1;
r_TX_Byte <= 8'h3F;
@(posedge r_Clock);
r_TX_DV <= 1'b0;
end
endmodule

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5) Write verilog code for 32-bit ALU supporting four logical and four arithmetic
operations, use case statement and if statement for ALU behavioral
modeling.

OPCODE ALU Operation

1 A+B
2 A-B
3 A Complement
4 A*B
5 A AND B
6 A OR B
7 A NAND B
8 A XOR B

Verilog code

module alu (out,a,b,en,op);

input [31:0] a, b;
input en;
input [2:0] op;
output reg [32:0] out;
always @ (a,b,en,op)

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if(en==0)
out=33'bz;
else
case(op)
3'd0 :out=a+b;
3'd1 :out=a-b;
3'd2 :out=a+1;
3'd3 :out=a-1;
3'd4 :out=a;
3'd5 :out=~a;
3'd6 :out=a|b;
3'd7 :out=a&b;
endcase
endmodule

Test Bench code

module alu_tb;
reg [31:0] a,b;
reg en;
reg [2:0] op;
wire [32:0] out;
alu a1(out,a,b,en,op);
initial
begin
en=0;
a=48;
b=33;
#20 en=1;
op=0;
#10 op=1;
#10 op=2;
#10 op=3;
#10 op=4;
#10 op=5;
#10 op=6;
#10 op=7;
#10 op=3'bx;
#10 op=3'bz;
#10 en=0;
end
initial
$monitor($time, "en=%b,input a=%b,b=%b,opcode=%b,output=%b",en,a,b,op,out);
endmodule

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6) Write the verilog code for the following Flip flop circuits and their
Test Bench for verification

a. SR Flip flop

Symbol and Truth Table:

Verilog Code
module
SR_ff(q,qbar,s,r,clk);
output q,qbar;
inputclk,s,r; reg tq;
always @(posedge clk or tq) begin
if (s == 1'b0 && r == 1'b0) tq <= tq;
else if (s == 1'b0 && r == 1'b1)
tq <= 1'b0;
else if (s == 1'b1 && r == 1'b0)
tq <= 1'b1;
else if (s == 1'b1 && r == 1'b1)
tq <= 1'bx;
end

assign q = tq;
assign qbar = ~tq;
initial

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$monitor($time, " input s=%b,r=%b,clk=%b,q=%b,qbar=%b",s,r,clk,q,qbar);

endmodule

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Test Bench Code

module SR_ff_test;
reg clk,s,r;
wire q,qbar;
wire s1,r1,clk1;
assign s1=s;
assign r1=r;
assign clk1=clk;

SR_ff sr1(q,qbar,s,r,clk);
initial
clk = 1'b0;
always
#10 clk = ~clk;
initial
begin
s = 1'b0; r = 1'b0;
#30 s = 1'b1;
#29 s = 1'b0;
#1 r = 1'b1;
#30 s = 1'b1;
#30 r = 1'b0;
#20 s = 1'b0;
#19 s = 1'b1;
#200 s = 1'b1; r = 1'b1;
#50 s = 1'b0; r = 1'b0;
#50 s = 1'b1; r = 1'b0;
#10 ;
end
always
#5 $display($time," clk=%b s=%b r=%b ",clk,s,r);
initia
l
#500$finish;
specify
$setup(s1, posedge clk1, 2);
$setup(r1, posedge clk1, 2);
$hold(posedge clk1, s1, 2);
$hold(posedge clk1, r1, 2);

endspeciy
iiiiiiendmodule

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VLSI Lab Manual 18ECL77

b. D flip fop

Symbol and Truth Table:

Verilog Code
module
d_ff(q,clk,n_rst,din);
output q;
input clk,din,n_rst; reg q;
always @(posedge clk or negedge n_rst)
begin
if(!n_rst)
q <= 1'b0;
else
q <= din;
end
endmodule

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Test Bench Code

module d_ff_test;
reg clk, din, n_rst;
wire q, d1, clk1;
d_ff df1 (q, clk, n_rst, din);
assign d1=din;
assign clk1=clk;
initial
clk = 1'b0;
always
#10 clk = ~clk;
initial
begin
din = 1'b0;
n_rst = 1'b1;
#20 n_rst = 1'b0;
#10 din = 1'b1;
#20 n_rst = 1'b1;
#18 din = 1'b0;
#1 din = 1'b1;
#20 din = 1'b0;
#10 ;
end
always
#5 $display ($time," clk=%b din=%b q=%b", clk, din, q);
initial
#100 $finish;
specify
$setup(d1, posedge clk1, 2);
$hold(posedge clk1, d1, 2);

$width(negedge d1, 2);

endspecify
endmodule

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VLSI Lab Manual 18ECL77

c) JK- Flip-Flop
Verilog Code

module jk_ff(q,qbar,clk,rst,j,k);
input clk,rst,j,k;
output q,qbar;
reg q,tq;
always @(posedge clk or negedge rst)
begin
if (!rst)
begin
q <= 1'b0;
tq <= 1'b0;
end
else
begin
if (j == 1'b1 && k == 1'b0)
q<=j;
else if (j == 1'b0 && k == 1'b1)
q <= 1'b0;
else if (j == 1'b1 && k == 1'b1)
begin
tq <= ~tq;
q <= tq;
end
end
end
assign qbar = ~q;
endmodule

Test Bench Code

module jk_ff_test;
reg clk,rst,j,k;
wire q,qbar;
wire clk1,j1,k1;
jk_ff inst1(q,qbar,clk,rst,j,k);
assign clk1=clk;
assign j1=j;
assign k1=k;
initial
clk = 1'b0;
always
#10 clk = ~clk;
initial
begin
j = 1'b0;
k = 1'b0;
rst = 1'b0;
#30 rst = 1'b1;
#60 j = 1'b0;k = 1'b1;
#30 j = 1'b1;k = 1'b0;
#10 j = 1'b0;k = 1'b1;
#20 j = 1'b1;k = 1'b1;

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VLSI Lab Manual 18ECL77

#40 j = 1'b1;k = 1'b0;

#5 j = 1'b0;

#20 j = 1'b1;
#50 rst = 1'b0;
#10 ;
end
always
#5 $display($time," clk=%b j=%b k=%b ",clk,j,k);
initial
#300 $finish;
specify
$setup(j1, posedge clk1, 2);
$setup(k1, posedge clk1, 2);
$hold(posedge clk1, j1, 2);
$hold(posedge clk1, k1, 2);
endspecify
endmodule

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VLSI Lab Manual 18ECL77

Viva Questions:
1. What are MOSFET’s?
2. What is the difference between MOSFET and BJT?
3. What are the types of MOSFET?
4. What is the difference between depletion mode and enhancement mode MOSFET’s?
5. What is rise time and fall time?
6. What is pinch off voltage?
7. In which region the MOSFET is used as a switch?
8. Which parameter defines the transfer characteristics?
9. Why MOSFET’s are mainly used for low power applications?
10. How MOSFET is turned off?
11. What are the merits of MOSFET?
12. What are demerits of MOSFET?
13. What are the applications of MOSFET?
14. Why is NAND gate preferred over NOR gate for fabrication?
15. Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
16. What are set up time & hold time constraints? What do they signify?
17. Explain Clock Skew?
18. What is Body Effect?
19. Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
20. Why PMOS and NMOS are sized equally in a Transmission Gates?
21. What happens when the PMOS and NMOS are interchanged with one
another in an inverter?
22. Why are PMOS transistor networks generally used to produce high signals,
while NMOS networks are used to product low signals?
23. What are the differences between SIMULATION and SYNTHESIS
24. Why does the present VLSI circuits use MOSFETs instead of BJTs?
25. Why does the present VLSI circuits use MOSFETs instead of BJTs?
26. What is threshold voltage?
27. What does it mean "the channel is pinched off"?
28. Explain the three regions of operation of a MOSFET.
29. What is channel-length modulation?
30. Explain depletion region.
31. What is body effect?
32. Give various factors on which threshold voltage depends.
33. Give the Cross-sectional diagram of the CMOS.
34. Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
35. What happens when the PMOS and NMOS are interchanged with one
another in an inverter?
36. Why are PMOS transistor networks generally used to produce high signals,
while NMOS networks are used to product low signals?
37. What is Latch Up? Explain Latch Up with cross section of a CMOS
Inverter. How do you avoid Latch Up?
38. Difference between Synchronous and Asynchronous reset.

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39. What is DRC ?

40. What is LVS ?
41. What is RCX ?
42. What are the differences between SIMULATION and SYNTHESIS?
43. What is a counter?
44. What are the differences between flipflop and latch?
45. How can you convert JK flipflop into Jk?
46. What are different types of adders?
47. Give the excitation table for JK flipflop?
48. Give the excitation table for SR flipflop?
49. Give the excitation table for D flipflop?
50. Give the excitation table for T flipflop?
51. What is the race around condition?
52. What is an amplifier?
53. What is an op-amp?
54. What is differential amplifier?
55. What is elaboration?
56. What is transient analysis?
57. What is DC analysis?
58. What is AC analysis?

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