Scribd
Upload
61 views13 pages

ARM Prog Model 3 Arithmetic

Uploaded by

Arther Traver
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
61 views13 pages

ARM Prog Model 3 Arithmetic

Uploaded by

Arther Traver
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 13

ARM Cortex-M4 Programming Model

Arithmetic Instructions
References:
Textbook Chapter 4, Chapter 9.1 – 9.2
“ARM Cortex-M Users Manual”, Chapter 3

1
CPU instruction types
 Data movement operations (Chapter 5)
 memory-to-register and register-to-memory
 includes different memory “addressing” options
 “memory” includes peripheral function registers
 register-to-register
 constant-to-register (or to memory in some CPUs)
 Arithmetic operations (Text – Chapter 4.1 – 4.5, Chapter 9.1-9.2)
 add/subtract/multiply/divide
 multi-precision operations (more than 32 bits)
 Logical operations (Text – Chapter 4.4 – 4.6)
 and/or/exclusive-or/complement (between operand bits)
 shift/rotate
 bit test/set/reset
 Flow control operations (Text – Chapter 6)
 branch to a location (conditionally or unconditionally)
 branch to a subroutine/function
 return from a subroutine/function

2
ARM arithmetic instructions
 ADD{S}: [Rd] <= Op1 + Op2
 SUB{S}: [Rd] <= Op1 – Op2
 RSB{S} (reverse subtract): [Rd] <= Op2 – Op1
Why would we need RSB if we have SUB? (Op2 options?)

 ADD/SUB/RSB performed only on 32-bit operands


 ADDS/SUBS/RSBS also set Z/N/C/V flags
 What if we have 8-bit or 16-bit data?
(Flags would not reflect 8 or 16-bit results)
 CPU cannot distinguish between signed and unsigned data
 One 32-bit binary adder circuit in the ALU
 SUB/RSB performed via 2’s complement arithmetic (whether data are
signed or unsigned)

3
Addition Summary
Let the 32-bit result R be the result of the 32-bit addition X+M.
 N bit is set
 if unsigned result is above 231-1 or
 if signed result is negative.
 N = R31
 Z bit is set if result is zero
 V bit is set after a signed addition if result is incorrect

 if signed result < -231 or signed result > 231-1

 V = X 31 & M 31 & R31 | X 31 & M 31 & R31

 C bit is set after an unsigned addition if result is incorrect


 if unsigned result is above 232-1

 C = X 31 & M 31 | M 31 & R31 | R31 & X 31

Bard, Gerstlauer,
Valvano, Yerraballi
Subtraction Summary
Let the 32-bit result R be the result of the 32-bit subtraction X-M

 N bit is set
 if unsigned result is above 231-1 or
 if signed result is negative.
 N = R31
 Z bit is set if result is zero
 V bit is set after a signed subtraction if result is incorrect (overflow)

 Signed result < -231 or signed result > 231-1

 V = X 31 & M 31 & R31 | X 31 & M 31 & R31

 C bit is clear after an unsigned subtraction if result is incorrect (overflow)

 if unsigned result < 0 (unsigned X < unsigned M => “borrow” condition)

 C = X 31 & M 31 | M 31 & R31 | R31 & X 31


Bard, Gerstlauer,
Valvano, Yerraballi
Checking for overflow
 Signed operands:
ADDS r3,r2,r1 ; r3 = r2 + r1
BVS Error ; branch if V flag set (overflow)
SUBS r3,r2,r1 ; r3 = r2 + r1
BVS Error ; branch if V flag set (overflow)
 Unsigned operands:
ADDS r3,r2,r1 ; r3 = r2 + r1
BCS Error ; branch if C flag set (carry = overflow)
SUBS r3,r2,r1 ; r3 = r2 + r1
BCC Error ; branch if C flag clear (borrow = overflow)

6
ARM multiply instructions
 Product of 32-bit operands can be up to 64 bits long
 Worst case unsigned product (product of max 32-bit values)
(232-1) × (232-1) = 264 – 233 + 1
0xFFFFFFFF × 0xFFFFFFFF = 0xFFFFFFFE00000001
 Worst case signed products:
 Positive × Positive
(231-1) × (231-1) = +262 – 232 + 1
0x7FFFFFFF × 0x7FFFFFFF = 0x3FFFFFFF00000001
 Negative × Negative
(-231) × (-231) = +262
0x80000000 × 0x80000000 = 0x4000000000000000
 Positive × Negative
(231-1) × (-231) = -262 + 231
0x7FFFFFFF × 0x80000000 = 0xC000000080000000

7
All results can be represented with 64 bits (no “overflows”)
ARM multiply instructions
[Rd] <= Op1 × Op2

 MUL Rd, Rm, Rn or MUL Rm,Rn


 Saves least-significant 32 bits of the product in Rd
 Valid result for both signed and unsigned operands
 No immediate form for Op2

 MULS Rm,Rs
 MUL updates N and Z flags (C and V are unaffected)
 Restricted to form Rm,Rs and to registers R0-R7

 UMULL/SMULL RdLo, RdHi, Rm, Rs


 Unsigned (UMULL) and Signed (SMULL) “Long Multiply”
 64-bit product P63-P0 put into two registers:
[RdHi] <= P63-P32 , [RdLo] <= P31-P0
8  No condition flags set
ARM divide instructions
 SDIV Rd, Rn, Rm (signed)
 UDIV Rd, Rn, Rm (unsigned)
 Integer division: Rd = Rn÷Rm (= Rn/Rm)
 Can also use form “Rn, Rm”: Rn = Rn÷Rm
 Result is truncated (rounded toward 0)
 Result = “quotient”, with “remainder” discarded
 Condition flags are unaffected

9
Example: C assignment statements

 C: x = (a + b) - c;
 Assembler:
LDR r4,=a ; get address for a
LDR r0,[r4] ; get value of a
LDR r4,=b ; get address for b, reusing r4
LDR r1,[r4] ; get value of b
ADD r3,r0,r1 ; compute a+b
LDR r4,=c ; get address for c
LDR r2,[r4] ; get value of c
SUB r3,r3,r2 ; complete computation of x
LDR r4,=x ; get address for x
STR r3,[r4] ; store value of x

10
Example: C assignment

 C: y = a*(b+c);
 Assembler:
LDR r4,=b ; get address for b
LDR r0,[r4] ; get value of b
LDR r4,=c ; get address for c
LDR r1,[r4] ; get value of c
ADD r2,r0,r1 ; compute partial result
LDR r4,=a ; get address for a
LDR r0,[r4] ; get value of a
MUL r2,r2,r0 ; compute final value for y
LDR r4,=y ; get address for y
STR r2,[r4] ; store y

11
Multi-precision arithmetic
 What if we need arithmetic for numbers > 32 bits?
 Consider addition/subtraction of decimal numbers:
53 Carry 10 from 1st to 2nd column
+ 29 (1 added to 2nd column)
82

53 Borrow 10 from 2nd to 1st column


- 29 (1 subtracted from 2nd column)
24
 CPU: add/subtract 32-bit parts of #s, with carry/borrow between parts
ADC (add with carry): [Rd] <= Op1 + Op2 + C
SBC (subtract with carry*): [Rd] <= Op1 – Op2 + (C – 1)
RSC (reverse subtract with carry*): [Rd] <= OP2 – Op1 + (C – 1)
* C=0 indicates “borrow” for subtraction
 Examples: (in class)
12
ARM multiply/accumulate instructions
 MLA : multiply with accumulate (32-bit result)
MLA Rd,Rm,Rs,Rn : [Rd] <= Rn + (Rm x Rs)
 MLS : multiply and subtract (32-bit result)
MLS Rd,Rm,Rs,Rn : [Rd] <= Rn - (Rm x Rs)

 UMLAL (unsigned)/SMLAL (signed)


 Multiply with accumulate, long (64-bit result)
UMLAL RdLo, RdHi, Rm, Rs :
[RdHi:RdLo] <= RdHi:RdLo + (Rm x Rs)

13 Example (in class) – DSP algorithm

You might also like