MAHARANA PRATAP GROUP OF INSTITUTIONS

KOTHI MANDHANA, KANPUR

(Approved by AICTE, New Delhi and Affiliated to Dr.AKTU, Lucknow)

Digital Notes

[Department of Computer Application]

Subject Name : OPERATING SYSTEM

Subject Code : KCA203

Course : MCA

Branch : -

Semester : IInd

Prepared by : Mr. Avanish Kumar dixit

 Memory Management
Memory Management is the process of controlling and coordinating computer memory, assigning portions known as blocks
to various running programs to optimize the overall performance of the system.
It is the most important function of an operating system that manages primary memory. It helps processes to move back and
forward between the main memory and execution disk. It helps OS to keep track of every memory location, irrespective of
whether it is allocated to some process or it remains free.
 It allows you to check how much memory needs to be allocated to processes that decide which processor should get
memory at what time.
 Tracks whenever inventory gets freed or unallocated. According to it will update the status.
 It allocates the space to application routines.
 It also make sure that these applications do not interfere with each other.
 Helps protect different processes from each other
 It places the programs in memory so that memory is utilized to its full extent.
Fixed Partitioning
The earliest and one of the simplest technique which can be used to load more than one processes into the main memory is
Fixed partitioning or Contiguous memory allocation.
In this technique, the main memory is divided into partitions of equal or different sizes. The operating system always resides in
the first partition while the other partitions can be used to store user processes. The memory is assigned to the processes in
contiguous way.
In fixed partitioning,
 The partitions cannot overlap.
 A process must be contiguously present in a partition for the execution.
There are various cons of using this technique.
1. Internal Fragmentation
If the size of the process is lesser then the total size of the partition then some size of the partition get wasted and remain
unused. This is wastage of the memory and called internal fragmentation.
As shown in the image below, the 4 MB partition is used to load only 3 MB process and the remaining 1 MB got wasted.
2. External Fragmentation
The total unused space of various partitions cannot be used to load the processes even though there is space available but not in
the contiguous form.
As shown in the image below, the remaining 1 MB space of each partition cannot be used as a unit to store a 4 MB process.
Despite of the fact that the sufficient space is available to load the process, process will not be loaded.
3. Limitation on the size of the process
If the process size is larger than the size of maximum sized partition then that process cannot be loaded into the memory.
Therefore, a limitation can be imposed on the process size that is it cannot be larger than the size of the largest partition.
4. Degree of multiprogramming is less
By Degree of multi programming, we simply mean the maximum number of processes that can be loaded into the memory at
the same time. In fixed partitioning, the degree of multiprogramming is fixed and very less due to the fact that the size of the
partition cannot be varied according to the size of processes.
Contiguous Memory Allocation-
 In contiguous memory allocation, a process can be stored only in a contiguous fashion.
 There are two popular techniques used for contiguous memory allocation-
Static Partitioning-
 Static partitioning is a fixed size partitioning scheme.
 In this technique, main memory is pre-divided into fixed size partitions.
 The size of each partition is fixed and can not be changed.
 Each partition is allowed to store only one process.
Algorithms for Partition Allocation- Popular algorithms used for allocating the partitions to the arriving processes are-

1. First Fit Algorithm-

 This algorithm starts scanning the partitions serially from the starting.
 When an empty partition that is big enough to store the process is found, it is allocated to the process.
 Obviously, the partition size has to be greater than or at least equal to the process size.

2. Best Fit Algorithm-

 This algorithm first scans all the empty partitions.
 It then allocates the smallest size partition to the process.

3. Worst Fit Algorithm-

 This algorithm first scans all the empty partitions.

 It then allocates the largest size partition to the process.

Important Points-
 Point-01: For static partitioning,
a) Best Fit Algorithm works best.
b) This is because space left after the allocation inside the partition is of very small size.
c) Thus, internal fragmentation is least.

 Point-02:For static partitioning,

a) Worst Fit Algorithm works worst.
b) This is because space left after the allocation inside the partition is of very large size.
c) Thus, internal fragmentation is maximum.
Fragmentation

Internal Fragmentation

 It occurs when the space is left inside the partition after allocating the partition to a
process.
 This space is called as internally fragmented space.
 This space can not be allocated to any other process.
 This is because only static partitioning allows to store only one process in each partition.
 Internal Fragmentation occurs only in static partitioning.

External Fragmentation

 It occurs when the total amount of empty space required to store the process is available in
the main memory.
  But because the space is not contiguous, so the process can not be stored.

Translating Logical Address into Physical Address-

 CPU always generates a logical address.

 A physical address is needed to access the main memory.
Following steps are followed to translate logical address into physical address-
Step-01:

 The translation scheme uses two registers that are under the control of operating system.
 During context switching, the values corresponding to the process being loaded are set in the registers.

These two registers are-

 Relocation Register
 Limit Register

 Relocation Register stores the base address or starting address of the process in the main memory.
 Limit Register stores the size or length of the process.

Step-02:

 CPU generates a logical address containing the address of the instruction that it wants to read.

Step-03:

 The logical address generated by the CPU is compared with the limit of the process.
 Now, two cases are possible-

Case-01: Generated Address >= Limit

 If address is found to be greater than or equal to the limit, a trap is generated.

 This helps to prevent unauthorized access.

Case-02: Generated Address < Limit

 The address must always lie in the range [0, limit-1].

 If address is found to be smaller than the limit, then the request is treated as a valid request.
 Then, generated address is added with the base address of the process.
 The result obtained after addition is the address of the memory location storing the required word.

Diagram-

The following diagram illustrates the above steps of translating logical address into physical address-
Advantages-The advantages of static partitioning are-
 It is simple and easy to implement.
 It supports multiprogramming since multiple processes can be stored inside the main memory.
 Only one memory access is required which reduces the access time.

Disadvantages-The disadvantages of static partitioning are-

 It suffers from both internal fragmentation and external fragmentation.
 It utilizes memory inefficiently.
 The degree of multiprogramming is limited equal to number of partitions.
 There is a limitation on the size of process since processes with size greater than the size of largest partition can’t be
stored and executed.

Dynamic Partitioning
 Dynamic partitioning is a variable size partitioning scheme.
 It performs the allocation dynamically.
 When a process arrives, a partition of size equal to the size of process is created.
 Then, that partition is allocated to the process.

Partition Allocation Algorithms-

 The processes arrive and leave the main memory.
 As a result, holes of different size are created in the main memory.
 These holes are allocated to the processes that arrive in future.
Partition allocation algorithms are used to decide which hole should be allocated to the arrived process.

Popular partition allocation algorithms are-

 First Fit Algorithm
 Best Fit Algorithm
 Worst Fit Algorithm
Important Points-

Point-01: For dynamic partitioning,

 Worst Fit Algorithm works best.
 This is because space left after allocation inside the partition is of large size.
 There is a high probability that this space might suit the requirement of arriving processes.
Point-02:
For dynamic partitioning,
 Best Fit Algorithm works worst.
 This is because space left after allocation inside the partition is of very small size.
 There is a low probability that this space might suit the requirement of arriving processes.
Translating Logical Address into Physical Address-
The following diagram illustrates the steps of translating logical address into physical address-
Advantages- The advantages of dynamic partitioning are-
 It does not suffer from internal fragmentation.
 Degree of multiprogramming is dynamic.
 There is no limitation on the size of processes.

Disadvantages- The disadvantages of dynamic partitioning are-

 It suffers from external fragmentation.
 Allocation and deallocation of memory is complex.
Non-Contiguous Memory Allocation-
 Non-contiguous memory allocation is a memory allocation technique.
 It allows to store parts of a single process in a non-contiguous fashion.
 Thus, different parts of the same process can be stored at different places in the main memory.
Techniques-There are two popular techniques used for non-contiguous memory allocation-

Paging-

 Paging is a fixed size partitioning scheme.

 In paging, secondary memory and main memory are divided into equal fixed size partitions.
 The partitions of secondary memory are called as pages.
 The partitions of main memory are called as frames.

 Each process is divided into parts where size of each part is same as page size.
  The size of the last part may be less than the page size.
 The pages of process are stored in the frames of main memory depending upon their availability.

Example-

 Consider a process is divided into 4 pages P 0, P1, P2 and P3.

 Depending upon the availability, these pages may be stored in the main memory frames in a non-contiguous fashion
as shown-

Translating Logical Address into Physical Address-

 CPU always generates a logical address.

 A physical address is needed to access the main memory.

Following steps are followed to translate logical address into physical address-
Step-01: CPU generates a logical address consisting of two parts-
 Page Number
 Page Offset

 Page Number specifies the specific page of the process from which CPU wants to read the data.
 Page Offset specifies the specific word on the page that CPU wants to read.

Step-02:For the page number generated by the CPU,

 Page Table provides the corresponding frame number (base address of the frame) where that page is stored in the
main memory.
Step-03:

 The frame number combined with the page offset forms the required physical address.

 Frame number specifies the specific frame where the required page is stored.
 Page Offset specifies the specific word that has to be read from that page.
Diagram-

The following diagram illustrates the above steps of translating logical address into physical address-

Advantages-The advantages of paging are-

 It allows to store parts of a single process in a non-contiguous fashion.
 It solves the problem of external fragmentation.

Disadvantages- The disadvantages of paging are-

 It suffers from internal fragmentation.
 There is an overhead of maintaining a page table for each process.
 The time taken to fetch the instruction increases since now two memory accesses are required.

Page Table-

 Page table is a data structure.

 It maps the page number referenced by the CPU to the frame number where that page is stored.

Characteristics-
 Page table is stored in the main memory.
 Number of entries in a page table = Number of pages in which the process is divided.
 Page Table Base Register (PTBR) contains the base address of page table.
 Each process has its own independent page table.

Working-
  Page Table Base Register (PTBR) provides the base address of the page table.
 The base address of the page table is added with the page number referenced by the CPU.
 It gives the entry of the page table containing the frame number where the referenced page is stored.

Page Table Entry-

 A page table entry contains several information about the page.
 The information contained in the page table entry varies from operating system to operating system.
 The most important information in a page table entry is frame number.
In general, each entry of a page table contains the following information-

1. Frame Number-

 Frame number specifies the frame where the page is stored in the main memory.
 The number of bits in frame number depends on the number of frames in the main memory.

2. Present / Absent Bit-

 This bit is also sometimes called as valid / invalid bit.

 This bit specifies whether that page is present in the main memory or not.
 If the page is not present in the main memory, then this bit is set to 0 otherwise set to 1.

NOTE
 If the required page is not present in the main memory, then it is called as Page Fault.
 A page fault requires page initialization.
 The required page has to be initialized (fetched) from the secondary memory and brought into the main memory.

3. Protection Bit-

 This bit is also sometimes called as “Read / Write bit“.

 This bit is concerned with the page protection.
 It specifies the permission to perform read and write operation on the page.
 If only read operation is allowed to be performed and no writing is allowed, then this bit is set to 0.
 If both read and write operation are allowed to be performed, then this bit is set to 1.

4. Reference Bit-

 Reference bit specifies whether that page has been referenced in the last clock cycle or not.
 If the page has been referenced recently, then this bit is set to 1 otherwise set to 0.

NOTE
 Reference bit is useful for page replacement policy.
 A page that has not been referenced recently is considered a good candidate for page
replacement in LRU page replacement policy.

5. Caching Enabled / Disabled-

 This bit enables or disables the caching of page.

 Whenever freshness in the data is required, then caching is disabled using this bit.
 If caching of the page is disabled, then this bit is set to 1 otherwise set to 0.
6. Dirty Bit-

 This bit is also sometimes called as “Modified bit“.

 This bit specifies whether that page has been modified or not.
 If the page has been modified, then this bit is set to 1 otherwise set to 0.

NOTE
In case the page is modified,
 Before replacing the modified page with some other page, it has to be written back in the secondary
memory to avoid losing the data.
 Dirty bit helps to avoid unnecessary writes.
 This is because if the page is not modified, then it can be directly replaced by another page without any
need of writing it back to the disk.

Important Formulas-

The following list of formulas is very useful for solving the numerical problems based on paging.

For Main Memory-

 Physical Address Space = Size of main memory

 Size of main memory = Total number of frames x Page size
 Frame size = Page size
 If number of frames in main memory = 2 X, then number of bits in frame number = X bits
 If Page size = 2X Bytes, then number of bits in page offset = X bits
 If size of main memory = 2X Bytes, then number of bits in physical address = X bits

For Process-

 Virtual Address Space = Size of process

 Number of pages the process is divided = Process size / Page size
 If process size = 2X bytes, then number of bits in virtual address space = X bits

For Page Table-

 Size of page table = Number of entries in page table x Page table entry size
 Number of entries in pages table = Number of pages the process is divided
 Page table entry size = Number of bits in frame number + Number of bits used for optional fields if any

NOTE-
 In general, if the given address consists of ‘n’ bits, then using ‘n’ bits, 2 n locations are possible.
 Then, size of memory = 2n x Size of one location.
 If the memory is byte-addressable, then size of one location = 1 byte.
 Thus, size of memory = 2n bytes.
 If the memory is word-addressable where 1 word = m bytes, then size of one location = m bytes.
 Thus, size of memory = 2n x m bytes.
PRACTICE PROBLEMS BASED ON PAGING AND PAGE TABLE-
Problem-01: Calculate the size of memory if its address consists of 22 bits and the memory is 2-byte addressable.
Solution-
We have-
 Number of locations possible with 22 bits = 2 22 locations
 It is given that the size of one location = 2 bytes
Thus, Size of memory
= 222 x 2 bytes
= 223 bytes
= 8 MB

Problem-02 Calculate the number of bits required in the address for memory having size of 16 GB. Assume the memory is 4-
byte addressable.
Solution-
Let ‘n’ number of bits are required. Then, Size of memory = 2 n x 4 bytes.
Since, the given memory has size of 16 GB, so we have-
2n x 4 bytes = 16 GB
2n x 4 = 16 G
2n x 22 = 234
2n = 232
∴ n = 32 bits

Problem-03: Consider a system with byte-addressable memory, 32 bit logical addresses, 4 kilobyte page size and page table
entries of 4 bytes each. The size of the page table in the system in megabytes is _____.
1. 2
2. 4
3. 8
4. 16

Solution-Given-
 Number of bits in logical address = 32 bits
 Page size = 4KB
 Page table entry size = 4 bytes
Process Size-
Number of bits in logical address = 32 bits
Thus,
Process size
= 232 B
= 4 GB
Number of Entries in Page Table-
Number of pages the process is divided
= Process size / Page size
= 4 GB / 4 KB
= 220 pages
Thus,
Number of entries in page table = 220 entries
Page Table Size-
Page table size
= Number of entries in page table x Page table entry size
= 220 x 4 bytes
= 4 MB
Thus, Option (B) is correct.
Problem-04: Consider a machine with 64 MB physical memory and a 32 bit virtual address space. If the page size is 4 KB,
what is the approximate size of the page table?
1. 16 MB
2. 8 MB
3. 2 MB
4. 24 MB
Solution-Given-
 Size of main memory = 64 MB
 Number of bits in virtual address space = 32 bits
 Page size = 4 KB
We will consider that the memory is byte addressable.
Number of Bits in Physical Address-
Size of main memory
= 64 MB
= 226 B
Thus, Number of bits in physical address = 26 bits
Number of Frames in Main Memory-
Number of frames in main memory
= Size of main memory / Frame size
= 64 MB / 4 KB
= 226 B / 212 B
= 214
Thus, Number of bits in frame number = 14 bits
Number of Bits in Page Offset-
We have,
Page size
= 4 KB
= 212 B
Thus, Number of bits in page offset = 12 bits
So, Physical address is-

Process Size-
Number of bits in virtual address space = 32 bits
Thus,
Process size
= 232 B
= 4 GB
Number of Entries in Page Table-
Number of pages the process is divided
= Process size / Page size
= 4 GB / 4 KB
= 220 pages
Thus, Number of entries in page table = 220 entries
Page Table Size-
Page table size
= Number of entries in page table x Page table entry size
= Number of entries in page table x Number of bits in frame number
= 220 x 14 bits
= 220 x 16 bits (Approximating 14 bits ≈ 16 bits)
= 220 x 2 bytes
= 2 MB Thus, Option (C) is correct.
Problem-05:In a virtual memory system, size of virtual address is 32-bit, size of physical address is 30-bit, page size is 4
Kbyte and size of each page table entry is 32-bit. The main memory is byte addressable. Which one of the following is the
maximum number of bits that can be used for storing protection and other information in each page table entry?
1. 2
2. 10
3. 12
4. 14
Solution-Given-
 Number of bits in virtual address = 32 bits
 Number of bits in physical address = 30 bits
 Page size = 4 KB
 Page table entry size = 32 bits

Size of Main Memory-

Number of bits in physical address = 30 bits
Thus,
Size of main memory
= 230 B
= 1 GB
Number of Frames in Main Memory-
Number of frames in main memory
= Size of main memory / Frame size
= 1 GB / 4 KB
= 230 B / 212 B
= 218
Thus, Number of bits in frame number = 18 bits
Number of Bits used for Storing other Information-
Maximum number of bits that can be used for storing protection and other information
= Page table entry size – Number of bits in frame number
= 32 bits – 18 bits
= 14 bits
Thus, Option (D) is correct.
Overhead in Paging-
In paging scheme, there are mainly two overheads-
1. Overhead of Page Tables-
 Paging requires each process to maintain a page table.
 So, there is an overhead of maintaining a page table for each process.
2. Overhead of Wasting Pages-
 There is an overhead of wasting last page of each process if it is not completely filled.
 On an average, half page is wasted for each process.
Thus,
Total overhead for one process= Size of its page table + (Page size / 2)
Optimal Page Size-
Optimal page size is the page size that minimizes the total overhead.
It is given as-

Also Read- Important Formulas Of Paging

Proof-

Total overhead due to one process

= Size of its page table + (Page size / 2)
= Number of entries x Page table entry size + (Page size / 2)
= Number of pages the process is divided x Page table entry size + (Page size / 2)
= (Process size / Page size) x Page table entry size + (Page size / 2)
Now,
For minimum overhead,

Keeping process size and page table entry size as constant, differentiating overhead with respect to page size, we get-

This page size minimizes the total overhead.

PRACTICE PROBLEMS BASED ON OPTIMAL PAGE SIZE-

Problem-01:
In a paging scheme, virtual address space is 4 KB and page table entry size is 8 bytes. What should be the optimal page size?

Solution-
Given-
 Virtual address space = Process size = 4 KB
 Page table entry size = 8 bytes
We know-
Optimal page size
= (2 x Process size x Page table entry size)1/2
= (2 x 4 KB x 8 bytes)1/2
= (216 bytes x bytes)1/2
= 28 bytes
= 256 bytes
Thus, Optimal page size = 256 bytes.

Problem-02:
In a paging scheme, virtual address space is 16 MB and page table entry size is 2 bytes. What should be the optimal page size?
Solution-
Given-
 Virtual address space = Process size = 16 MB
 Page table entry size = 2 bytes

We know-
Optimal page size
= (2 x Process size x Page table entry size)1/2
= (2 x 16 MB x 2 bytes)1/2
= (226 bytes x bytes)1/2
= 213 bytes
= 8 KB
Thus, Optimal page size = 8 KB.
Problem-03: In a paging scheme, virtual address space is 256 GB and page table entry size is 32 bytes. What should be the
optimal page size?
Solution-
 Virtual address space = Process size = 256 GB
 Page table entry size = 32 bytes
Optimal page size
= (2 x Process size x Page table entry size)1/2
= (2 x 256 GB x 32 bytes)1/2
= (244 bytes x bytes)1/2
= 222 bytes
= 4 MB
Thus, Optimal page size = 4 MB.

PRACTICE PROBLEMS BASED ON PAGING IN OS-

Problem-01:Consider a single level paging scheme. The virtual address space is 4 MB and page size is 4 KB. What is the
maximum page table entry size possible such that the entire page table fits well in one page?
Solution-
For page table, to fit well in one page, we must have-
Page table size <= Page size
Number of Pages of Process-
Number of pages the process is divided
= Process size / Page size
= 4 MB / 4 KB
= 210 pages
Page Table Size-
Let page table entry size = B bytes
Now,
Page table size
= Number of entries in the page table x Page table entry size
= Number of pages the process is divided x Page table entry size
= 210 x B bytes
Now,
According to the above condition, we must have-
210 x B bytes <= 4 KB
210 x B <= 212
B <= 4
Thus, maximum page table entry size possible = 4 bytes.
Problem-02:
Consider a single level paging scheme. The virtual address space is 4 GB and page size is 128 KB. What is the maximum page
table entry size possible such that the entire page table fits well in one page?
Solution-
For page table, to fit well in one page, we must have-
Page table size <= Page size
Number of Pages of Process-
Number of pages the process is divided
= Process size / Page size
= 4 GB / 128 KB
= 232 B / 217 B
= 215 pages
Page Table Size-
Let page table entry size = B bytes
Now,
Page table size
= Number of entries in the page table x Page table entry size
= Number of pages the process is divided x Page table entry size
= 215 x B bytes
Now,
 According to the above condition, we must have-
215 x B bytes <= 128 KB
215 x B <= 217
B <= 4
Thus, maximum page table entry size possible = 4 bytes.

Problem-03:Consider a single level paging scheme. The virtual address space is 128 TB and page size is 32 MB. What is the
maximum page table entry size possible such that the entire page table fits well in one page?
Solution-
For page table, to fit well in one page, we must have-
Page table size <= Page size
Number of Pages of Process-
Number of pages the process is divided
= Process size / Page size
= 128 TB / 32 MB
= 247 B / 225 B
= 222 pages
Page Table Size-
Let page table entry size = B bytes
Now,
Page table size
= Number of entries in the page table x Page table entry size
= Number of pages the process is divided x Page table entry size
= 222 x B bytes
Now,
According to the above condition, we must have-
222 x B bytes <= 32 MB
222 x B <= 225
B <= 8
Thus, maximum page table entry size possible = 8 bytes.

Problem-04:

Consider a single level paging scheme. The virtual address space is 256 MB and page table entry size is 4 bytes. What is the
minimum page size possible such that the entire page table fits well in one page?

Solution-

For page table, to fit well in one page, we must have-

Page table size <= Page size

Let page size = B bytes.

Number of Pages of Process-

Number of pages the process is divided

= Process size / Page size
= 256 MB / B bytes
= 228 / B

Page Table Size-

Page table size

= Number of entries in the page table x Page table entry size
= Number of pages the process is divided x Page table entry size
= (228 / B) x 4 bytes
= (230 / B) bytes

Now,
According to the above condition, we must have-
(230 / B) bytes <= B bytes
B2 >= 230
B >= 215
Thus, minimum page size possible = 215 bytes or 32 KB.

Problem-05:

Consider a single level paging scheme. The virtual address space is 512 KB and page table entry size is 2 bytes. What is the
minimum page size possible such that the entire page table fits well in one page?

Solution-

For page table, to fit well in one page, we must have-

Page table size <= Page size

Let page size = B bytes.

Number of Pages of Process-

Number of pages the process is divided

= Process size / Page size
= 512 KB / B bytes
= 219 / B

Page Table Size-

Page table size

= Number of entries in the page table x Page table entry size
= Number of pages the process is divided x Page table entry size
= (219 / B) x 2 bytes
= (220 / B) bytes

Now,
According to the above condition, we must have-
(220 / B) bytes <= B bytes
B2 >= 220
B >= 210
Thus, minimum page size possible = 210 bytes or 1 KB.
Problem-06: Consider a single level paging scheme. The virtual address space is 16 GB and page table entry size is 4 bytes.
What is the minimum page size possible such that the entire page table fits well in one page?
Solution-For page table, to fit well in one page, we must have-
Page table size <= Page size
Let page size = B bytes.
Number of Pages of Process-
Number of pages the process is divided
= Process size / Page size
= 16 GB / B bytes
= 234 / B
Page Table Size-
Page table size
= Number of entries in the page table x Page table entry size
= Number of pages the process is divided x Page table entry size
= (234 / B) x 4 bytes
= (236 / B) bytes
Now, According to the above condition, we must have-
(236 / B) bytes <= B bytes
B2 >= 236
B >= 218
Thus, minimum page size possible = 218 bytes or 256 KB.
Translation Lookaside Buffer-
  Translation Lookaside Buffer (TLB) is a solution that tries to reduce the effective access time.
 Being a hardware, the access time of TLB is very less as compared to the main memory.
Structure- Translation Lookaside Buffer (TLB) consists of two columns-
 Page Number
 Frame Number

Translating Logical Address into Physical Address-

In a paging scheme using TLB,
The logical address generated by the CPU is translated into the physical address using following steps-
Step-01:CPU generates a logical address consisting of two parts-
 Page Number
 Page Offset
Step-02:
 TLB is checked to see if it contains an entry for the referenced page number.
 The referenced page number is compared with the TLB entries all at once.
Now, two cases are possible-
Case-01: If there is a TLB hit-
 If TLB contains an entry for the referenced page number, a TLB hit occurs.
 In this case, TLB entry is used to get the corresponding frame number for the referenced page number.
Case-02: If there is a TLB miss-
 If TLB does not contain an entry for the referenced page number, a TLB miss occurs.
 In this case, page table is used to get the corresponding frame number for the referenced page number.
 Then, TLB is updated with the page number and frame number for future references.
Step-03:
 After the frame number is obtained, it is combined with the page offset to generate the physical address.
 Then, physical address is used to read the required word from the main memory.
NOTE- In the above discussion, we have assumed that no Page Fault occurs.
Diagram-
Flowchart-

The following flowchart illustrates the above steps of translating logical address into physical address-

Important Points-
Point-01:
 Unlike page table, there exists only one TLB in the system.
 So, whenever context switching occurs, the entire content of TLB is flushed and deleted.
 TLB is then again updated with the currently running process.
Point-02:
When a new process gets scheduled-
 Initially, TLB is empty. So, TLB misses are frequent.
 With every access from the page table, TLB is updated.
 After some time, TLB hits increases and TLB misses reduces.
Point-03:
 The time taken to update TLB after getting the frame number from the page table is negligible.
 Also, TLB is updated in parallel while fetching the word from the main memory.
Advantages-The advantages of using TLB are-
 TLB reduces the effective access time.
 Only one memory access is required when TLB hit occurs.
Disadvantages-A major disadvantage of using TLB is-
 After some time of running the process, when TLB hits increases and process starts to run smoothly, a context
switching occurs.
 The entire content of the TLB is flushed.
 Then, TLB is again updated with the currently running process.
This happens again and again.
Other disadvantages are-
 TLB can hold the data of only one process at a time.
 When context switches occur frequently, the performance of TLB degrades due to low hit ratio.
 As it is a special hardware, it involves additional cost.
Effective Access Time
In a single level paging using TLB, the effective access time is given as-

This formula is valid only when there is single level paging and there are no page faults.

PRACTICE PROBLEMS BASED ON TRANSLATION LOOKASIDE BUFFER-

Problem-01:
A paging scheme uses a Translation Lookaside buffer (TLB). A TLB access takes 10 ns and a main memory access takes 50
ns. What is the effective access time (in ns) if the TLB hit ratio is 90% and there is no page fault?
1. 54
2. 60
3. 65
4. 75
Solution-Given-
 TLB access time = 10 ns
 Main memory access time = 50 ns
 TLB Hit ratio = 90% = 0.9

Calculating TLB Miss Ratio-

TLB Miss ratio
= 1 – TLB Hit ratio
= 1 – 0.9
= 0.1
Calculating Effective Access Time-
Substituting values in the above formula, we get-
Effective Access Time
= 0.9 x { 10 ns + 50 ns } + 0.1 x { 10 ns + 2 x 50 ns }
= 0.9 x 60 ns + 0.1 x 110 ns
= 54 ns + 11 ns
= 65 ns
Thus, Option (C) is correct.
Problem-02:A paging scheme uses a Translation Lookaside buffer (TLB). The effective memory access takes 160 ns and a
main memory access takes 100 ns. What is the TLB access time (in ns) if the TLB hit ratio is 60% and there is no page fault?
1. 54
2. 60
3. 20
4. 75
Solution-Given-
 Effective access time = 160 ns
 Main memory access time = 100 ns
 TLB Hit ratio = 60% = 0.6
Calculating TLB Miss Ratio-
TLB Miss ratio
= 1 – TLB Hit ratio
= 1 – 0.6
= 0.4
Calculating TLB Access Time-
Let TLB access time = T ns.
Substituting values in the above formula, we get-
160 ns = 0.6 x { T + 100 ns } + 0.4 x { T + 2 x 100 ns }
160 = 0.6 x T + 60 + 0.4 x T + 80
160 = T + 140
T = 160 – 140
T = 20

Thus, Option (C) is correct.

Multilevel Paging-

Multilevel paging is a paging scheme where there exists a hierarchy of page tables.

Need –The need for multilevel paging arises when-

 The size of page table is greater than the frame size.
 As a result, the page table can not be stored in a single frame in main memory.
Working-
In multilevel paging,
 The page table having size greater than the frame size is divided into several parts.
 The size of each part is same as frame size except possibly the last part.
 The pages of page table are then stored in different frames of the main memory.
 To keep track of the frames storing the pages of the divided page table, another page table is maintained.
 As a result, the hierarchy of page tables get generated.
 Multilevel paging is done till the level is reached where the entire page table can be stored in a single frame.
Illustration of Multilevel Paging-
Consider a system using paging scheme where-
 Logical Address Space = 4 GB
 Physical Address Space = 16 TB
 Page size = 4 KB
Now, let us find how many levels of page table will be required.
Number of Bits in Physical Address-

Size of main memory

= Physical Address Space
= 16 TB
= 244 B
Thus, Number of bits in physical address = 44 bits
Number of Frames in Main Memory-
Number of frames in main memory
= Size of main memory / Frame size
= 16 TB / 4 KB
= 232 frames
Thus, Number of bits in frame number = 32 bits
Number of Bits in Page Offset-
We have,
Page size
= 4 KB
= 212 B
 Thus, Number of bits in page offset = 12 bits
Alternatively,
Number of bits in page offset
= Number of bits in physical address – Number of bits in frame number
= 44 bits – 32 bits
= 12 bits

So, Physical address is-

Number of Pages of Process-

Number of pages the process is divided

= Process size / Page size
= 4 GB / 4 KB
= 220 pages

Inner Page Table Size-

Inner page table keeps track of the frames storing the pages of process.
Inner Page table size
= Number of entries in inner page table x Page table entry size
= Number of pages the process is divided x Number of bits in frame number
= 220 x 32 bits
= 220 x 4 bytes
= 4 MB

Now, we can observe-

 The size of inner page table is greater than the frame size (4 KB).
 Thus, inner page table can not be stored in a single frame.
 So, inner page table has to be divided into pages.

Number of Pages of Inner Page Table-

Number of pages the inner page table is divided

= Inner page table size / Page size
= 4 MB / 4 KB
= 210 pages

Now, these 210 pages of inner page table are stored in different frames of the main memory.

Number of Page Table Entries in One Page of Inner Page Table-

Number of page table entries in one page of inner page table

= Page size / Page table entry size
= Page size / Number of bits in frame number
= 4 KB / 32 bits
= 4 KB / 4 B
= 210
 Number of Bits Required to Search an Entry in One Page of Inner Page Table-

One page of inner page table contains 210 entries.

Thus,
Number of bits required to search a particular entry in one page of inner page table = 10 bits

Outer Page Table Size-

Outer page table is required to keep track of the frames storing the pages of inner page table.
Outer Page table size
= Number of entries in outer page table x Page table entry size
= Number of pages the inner page table is divided x Number of bits in frame number

= 210 x 32 bits
= 210 x 4 bytes
= 4 KB

Now, we can observe-

 The size of outer page table is same as frame size (4 KB).
 Thus, outer page table can be stored in a single frame.
 So, for given system, we will have two levels of page table.
 Page Table Base Register (PTBR) will store the base address of the outer page table.

Number of Bits Required to Search an Entry in Outer Page Table-

Outer page table contains 210 entries.

Thus,
Number of bits required to search a particular entry in outer page table = 10 bits

The paging system will look like as shown below-

 PRACTICE PROBLEM BASED ON MULTILEVEL PAGING-

Problem-

Consider a system using multilevel paging scheme. The page size is 16 KB. The memory is byte addressable and virtual
address is 48 bits long. The page table entry size is 4 bytes.
Find-
1. How many levels of page table will be required?
2. Give the divided physical address and virtual address.

Solution-

Given-
 Virtual Address = 48 bits
 Page size = 16 KB
 Page table entry size = 4 bytes

Number of Bits in Frame Number-

We have,
Page table entry size
= 4 bytes
= 32 bits
Thus, Number of bits in frame number = 32 bits

Number of Frames in Main Memory-

We have, Number of bits in frame number = 32 bits

Thus,
Number of frames in main memory
= 232 frames

Size of Main Memory-

Size of main memory

= Total number of frames x Frame size
= 232 x 16 KB
= 246 B
= 64 TB
Thus, Number of bits in physical address = 46 bits

Number of Bits in Page Offset-

We have,
Page size
= 16 KB
= 214 B
Thus, Number of bits in page offset = 14 bits

Alternatively,
Number of bits in page offset
= Number of bits in physical address – Number of bits in frame number
= 46 bits – 32 bits
= 14 bits

Process Size-

Number of bits in virtual address = 48 bits

Thus,
Process size
 = 248 bytes
= 256 TB

Number of Pages of Process-

Number of pages the process is divided

= Process size / Page size
= 256 TB / 16 KB
= 248 B / 214 B
= 234 pages

Inner Page Table Size-

Inner page table keeps track of the frames storing the pages of process.
Inner Page table size
= Number of entries in inner page table x Page table entry size
= Number of pages the process is divided x Page table entry size
= 234 x 4 bytes
= 236 bytes
= 64 GB

Now, we can observe-

 The size of inner page table is greater than the frame size (4 KB).
 Thus, inner page table can not be stored in a single frame.
 So, inner page table has to be divided into pages.

Number of Pages of Inner Page Table-

Number of pages the inner page table is divided

= Inner page table size / Page size
= 64 GB / 16 KB
= 236 B / 214 B
= 222 pages

Now, these 222 pages of inner page table are stored in different frames of the main memory.

Number of Page Table Entries in One Page of Inner Page Table-

Number of page table entries in one page of inner page table

= Page size / Page table entry size
= 16 KB / 4 B
= 212 entries

Number of Bits Required to Search an Entry in One Page of Inner Page Table-

One page of inner page table contains 212 entries.

Thus,
Number of bits required to search a particular entry in one page of inner page table = 12 bits

Outer Page Table-1 Size-

Outer page table-1 is required to keep track of the frames storing the pages of inner page table.
Outer Page table-1 size
= Number of entries in outer page table-1 x Page table entry size
= Number of pages the inner page table is divided x Page table entry size
= 222 x 4 bytes
= 16 MB

Now, we can observe-

 The size of outer page table-1 is greater than the frame size (4 KB).
 Thus, outer page table-1 can not be stored in a single frame.
 So, outer page table-1 has to be divided into pages.

Number of Pages of Outer Page Table-1

Number of pages the outer page table-1 is divided

= Outer page table-1 size / Page size
= 16 MB / 16 KB
= 210 pages

Now, these 210 pages of outer page table-1 are stored in different frames of the main memory.

Number of Page Table Entries in One Page of Outer Page Table-1

Number of page table entries in one page of outer page table-1

= Page size / Page table entry size
= 16 KB / 4 B
= 212 entries

Number of Bits Required to Search an Entry in One Page of Outer Page Table-1

One page of outer page table-1 contains 212 entries.

Thus,
Number of bits required to search a particular entry in one page of outer page table-1 = 12 bits

Outer Page Table-2 Size-

Outer page table-2 is required to keep track of the frames storing the pages of outer page table-1.
Outer Page table-2 size
= Number of entries in outer page table-2 x Page table entry size
= Number of pages the outer page table-1 is divided x Page table entry size
= 210 x 4 bytes
= 4 KB

Now, we can observe-

 The size of outer page table-2 is less than the frame size (16 KB).
 Thus, outer page table-2 can be stored in a single frame.
 In fact, outer page table-2 will not completely occupy one frame and some space will remain vacant.
 So, for given system, we will have three levels of page table.
 Page Table Base Register (PTBR) will store the base address of the outer page table-2.

Number of Bits Required to Search an Entry in Outer Page Table-2

Outer page table-2 contains 210 entries.

Thus,
Number of bits required to search a particular entry in outer page table-2 = 10 bits

The paging system will look like as shown below-

 Important Points-

 At any level, the page table entry size of any page table will always be same because each entry points to the frame number.
 When there is only one level of paging, there is only one page table whose size is less than or equal to page size.
 All the page tables are completely filled except possibly the last page.

Problem-01:

Consider a system using multilevel paging scheme. The page size is 1 MB. The memory is byte addressable and virtual address
is 64 bits long. The page table entry size is 4 bytes.
Find-
1. How many levels of page table will be required?
2. Give the divided physical address and virtual address.

Solution-

Given-
 Virtual Address = 64 bits
 Page size = 1 MB
 Page table entry size = 4 bytes

Number of Bits in Frame Number-

We have,
Page table entry size
= 4 bytes
= 32 bits
Thus, Number of bits in frame number = 32 bits

Number of Frames in Main Memory-

We have, Number of bits in frame number = 32 bits

Thus,
Number of frames in main memory
= 232 frames

Size of Main Memory-

Size of main memory

= Total number of frames x Frame size
= 232 x 1 MB
= 252 B
Thus, Number of bits in physical address = 52 bits
 Number of Bits in Page Offset-

We have,
Page size
= 1 MB
= 220 B
Thus, Number of bits in page offset = 20 bits

Alternatively,
Number of bits in page offset
= Number of bits in physical address – Number of bits in frame number
= 52 bits – 32 bits
= 20 bits

Process Size-

Number of bits in virtual address = 64 bits

Thus,
Process size
= 264 bytes

Number of Pages of Process-

Number of pages the process is divided

= Process size / Page size
= 264 B / 1 MB
= 264 B / 220 B
= 244 pages

Inner Page Table Size-

Inner page table keeps track of the frames storing the pages of process.
Inner page table size
= Number of entries in inner page table x Page table entry size
= Number of pages the process is divided x Page table entry size
= 244 x 4 bytes
= 246 bytes

Now, we can observe-

 The size of inner page table is greater than the frame size (1 MB).
 Thus, inner page table can not be stored in a single frame.
 So, inner page table has to be divided into pages.

Number of Pages of Inner Page Table-

Number of pages the inner page table is divided

= Inner page table size / Page size
= 246 B / 1 MB
= 246 B / 220 B
= 226 pages

Now, these 226 pages of inner page table are stored in different frames of the main memory.

Number of Page Table Entries in One Page of Inner Page Table-

Number of page table entries in one page of inner page table

= Page size / Page table entry size
= 1 MB / 4 B
= 220 B / 22 B
 = 218 entries

Number of Bits Required to Search an Entry in One Page of Inner Page Table-

One page of inner page table contains 218 entries.

Thus,
Number of bits required to search a particular entry in one page of inner page table = 18 bits

Outer Page Table-1 Size-

Outer page table-1 is required to keep track of the frames storing the pages of inner page table.
Outer page table-1 size
= Number of entries in outer page table-1 x Page table entry size
= Number of pages the inner page table is divided x Page table entry size
= 226 x 4 bytes
= 228 bytes
= 256 MB

Now, we can observe-

 The size of outer page table-1 is greater than the frame size (1 MB).
 Thus, outer page table-1 can not be stored in a single frame.
 So, outer page table-1 has to be divided into pages.

Number of Pages of Outer Page Table-1

Number of pages the outer page table-1 is divided

= Outer page table-1 size / Page size
= 256 MB / 1 MB
= 256 pages

Now, these 256 pages of outer page table-1 are stored in different frames of the main memory.

Number of Page Table Entries in One Page of Outer Page Table-1

Number of page table entries in one page of outer page table-1

= Page size / Page table entry size
= 1 MB / 4 B
= 220 B / 22 B
= 218 entries

Number of Bits Required to Search an Entry in One Page of Outer Page Table-1

One page of outer page table-1 contains 218 entries.

Thus,
Number of bits required to search a particular entry in one page of outer page table-1 = 18 bits

Outer Page Table-2 Size-

Outer page table-2 is required to keep track of the frames storing the pages of outer page table-1.
Outer page table-2 size
= Number of entries in outer page table-2 x Page table entry size
= Number of pages the outer page table-1 is divided x Page table entry size
= 256 x 4 bytes
= 1 KB
Now, we can observe-
 The size of outer page table-2 is less than the frame size (16 KB).
 Thus, outer page table-2 can be stored in a single frame.
 In fact, outer page table-2 will not completely occupy one frame and some space will remain vacant.
 So, for given system, we will have three levels of page table.
 Page Table Base Register (PTBR) will store the base address of the outer page table-2.
 Number of Bits Required to Search an Entry in Outer Page Table-2
Outer page table-2 contains 256 = 28 entries.
Thus,
Number of bits required to search a particular entry in outer page table-2 = 8 bits

The paging system will look like as shown below-

Problem-02:Consider a system using multilevel paging scheme. The page size is 1 GB. The memory is byte addressable and
virtual address is 72 bits long. The page table entry size is 4 bytes.
Find-
1. How many levels of page table will be required?
2. Give the divided physical address and virtual address.

Solution Given-
 Virtual Address = 72 bits
 Page size = 1 GB
 Page table entry size = 4 bytes
Number of Bits in Frame Number
We have,
Page table entry size
= 4 bytes
= 32 bits
Thus, Number of bits in frame number = 32 bits
Number of Frames in Main Memory-
We have, Number of bits in frame number = 32 bits
Thus,
Number of frames in main memory
= 232 frames
Size of Main Memory-
Size of main memory
= Total number of frames x Frame size
= 232 x 1 GB
= 262 B
Thus, Number of bits in physical address = 62 bits
Number of Bits in Page Offset
We have,
Page size
= 1 GB
= 230 B
Thus, Number of bits in page offset = 30 bits
Alternatively,
Number of bits in page offset
= Number of bits in physical address – Number of bits in frame number
= 62 bits – 32 bits
= 30 bits
Process Size-
Number of bits in virtual address = 72 bits
Thus,
Process size
= 272 bytes
Number of Pages of Process-
Number of pages the process is divided
= Process size / Page size
= 272 B / 1 GB
= 272 B / 230 B
= 242 pages
Inner Page Table Size-
Inner page table keeps track of the frames storing the pages of process.
Inner page table size
= Number of entries in inner page table x Page table entry size
= Number of pages the process is divided x Page table entry size
= 242 x 4 bytes
= 244 bytes
Now, we can observe-
 The size of inner page table is greater than the frame size (1 GB).
 Thus, inner page table can not be stored in a single frame.
 So, inner page table has to be divided into pages.
Number of Pages of Inner Page Table-
Number of pages the inner page table is divided
= Inner page table size / Page size
= 244 B / 1 GB
= 244 B / 230 B
= 214 pages

Now, these 214 pages of inner page table are stored in different frames of the main memory.
Number of Page Table Entries in One Page of Inner Page Table-
Number of page table entries in one page of inner page table
= Page size / Page table entry size
= 1 GB / 4 B
= 230 B / 22 B
= 228 entries
Number of Bits Required to Search an Entry in One Page of Inner Page Table-
One page of inner page table contains 228 entries.
Thus,
Number of bits required to search a particular entry in one page of inner page table = 28 bits
Outer Page Table Size-
Outer page table is required to keep track of the frames storing the pages of inner page table.
Outer page table size
= Number of entries in outer page table x Page table entry size
= Number of pages the inner page table is divided x Page table entry size
= 214 x 4 bytes
= 216 bytes
= 64 KB
Now, we can observe-
 The size of outer page table is less than the frame size (1 GB).
 Thus, outer page table can be stored in a single frame.
 In fact, outer page table will not completely occupy one frame and some space will remain vacant.
 So, for given system, we will have two levels of page table.
 Page Table Base Register (PTBR) will store the base address of the outer page table.
Number of Bits Required to Search an Entry in Outer Page Table-
Outer page table contains 214 entries.
Thus, Number of bits required to search a particular entry in outer page table = 14 bits
The paging system will look like as shown below-
Problem-03:Consider a system using multilevel paging scheme. The page size is 256 MB. The memory is byte addressable
and virtual address is 72 bits long. The page table entry size is 4 bytes.
Find-
 How many levels of page table will be required?
 Give the divided physical address and virtual address.
Solution Given-
 Virtual Address = 72 bits
 Page size = 256 MB
 Page table entry size = 4 bytes

Number of Bits in Frame Number-

We have,
Page table entry size
= 4 bytes
= 32 bits
Thus, Number of bits in frame number = 32 bits
Number of Frames in Main Memory-
We have, Number of bits in frame number = 32 bits
Thus,
Number of frames in main memory
= 232 frames
Size of Main Memory-
Size of main memory
= Total number of frames x Frame size
= 232 x 256 MB
= 260 B
Thus, Number of bits in physical address = 60 bits
Number of Bits in Page Offset
We have,
Page size
= 256 MB
= 228 B
Thus, Number of bits in page offset = 28 bits
Alternatively,
Number of bits in page offset
= Number of bits in physical address – Number of bits in frame number
= 60 bits – 32 bits
= 28 bits
Process Size-
Number of bits in virtual address = 72 bits
Thus,
Process size
= 272 bytes
Number of Pages of Process-
Number of pages the process is divided
= Process size / Page size
= 272 B / 256 MB
= 272 B / 228 B
= 244 pages
Inner Page Table Size-
Inner page table keeps track of the frames storing the pages of process.
Inner page table size
= Number of entries in inner page table x Page table entry size
= Number of pages the process is divided x Page table entry size
= 244 x 4 bytes
= 246 bytes
Now, we can observe-
 The size of inner page table is greater than the frame size (256 MB).
 Thus, inner page table can not be stored in a single frame.
 So, inner page table has to be divided into pages.
Number of Pages of Inner Page Table
Number of pages the inner page table is divided
= Inner page table size / Page size
= 246 B / 256 MB
= 246 B / 228 B
= 218 pages
Now, these 218 pages of inner page table are stored in different frames of the main memory.
Number of Page Table Entries in One Page of Inner Page Table-
Number of page table entries in one page of inner page table
= Page size / Page table entry size
= 256 MB / 4 B
= 228 B / 22 B
= 226 entries
Number of Bits Required to Search an Entry in One Page of Inner Page Table-
One page of inner page table contains 226 entries.
Thus,
Number of bits required to search a particular entry in one page of inner page table = 26 bits
Outer Page Table Size
Outer page table is required to keep track of the frames storing the pages of inner page table.
Outer page table size
= Number of entries in outer page table x Page table entry size
= Number of pages the inner page table is divided x Page table entry size
= 218 x 4 bytes
= 220 bytes
= 1 MB
Now, we can observe-
 The size of outer page table is less than the frame size (256 MB).
 Thus, outer page table can be stored in a single frame.
 In fact, outer page table will not completely occupy one frame and some space will remain vacant.
 So, for given system, we will have two levels of page table.
 Page Table Base Register (PTBR) will store the base address of the outer page table.
Number of Bits Required to Search an Entry in Outer Page Table-
Outer page table contains 218 entries.
Thus,Number of bits required to search a particular entry in outer page table = 18 bits
The paging system will look like as shown below-
Problem-04:Consider a system using multilevel paging scheme. The page size is 16 MB. The memory is byte addressable and
virtual address is 72 bits long. The page table entry size is 4 bytes.
Find-
 How many levels of page table will be required?
 Give the divided physical address and virtual address.

Solution-Given-
 Virtual Address = 72 bits
 Page size = 16 MB
 Page table entry size = 4 bytes
Number of Bits in Frame Number-
We have,
Page table entry size
= 4 bytes
= 32 bits
Thus, Number of bits in frame number = 32 bits
Number of Frames in Main Memory-
We have, Number of bits in frame number = 32 bits
Thus,
Number of frames in main memory
= 232 frames

Size of Main Memory

Size of main memory
= Total number of frames x Frame size
= 232 x 16 MB
= 256 B
Thus, Number of bits in physical address = 56 bits
Number of Bits in Page Offset-
We have,
Page size
= 16 MB
= 224 B
Thus, Number of bits in page offset = 24 bits
Alternatively,
Number of bits in page offset
= Number of bits in physical address – Number of bits in frame number
= 56 bits – 32 bits
= 24 bits
Process Size-
Number of bits in virtual address = 72 bits
Thus,
Process size
= 272 bytes
Number of Pages of Process-
Number of pages the process is divided
= Process size / Page size
= 272 B / 16 MB
= 272 B / 224 B
= 248 pages
Inner Page Table Size
Inner page table keeps track of the frames storing the pages of process.
Inner page table size
= Number of entries in inner page table x Page table entry size
= Number of pages the process is divided x Page table entry size
= 248 x 4 bytes
= 250 bytes
Now, we can observe-
 The size of inner page table is greater than the frame size (16 MB).
 Thus, inner page table can not be stored in a single frame.
 So, inner page table has to be divided into pages.
Number of Pages of Inner Page Table-
Number of pages the inner page table is divided
= Inner page table size / Page size
= 250 B / 16 MB
= 250 B / 224 B
= 226 pages
Now, these 226 pages of inner page table are stored in different frames of the main memory.
Number of Page Table Entries in One Page of Inner Page Table-
Number of page table entries in one page of inner page table
= Page size / Page table entry size
= 16 MB / 4 B
= 224 B / 22 B
= 222 entries
Number of Bits Required to Search an Entry in One Page of Inner Page Table-
One page of inner page table contains 222 entries.
Thus, Number of bits required to search a particular entry in one page of inner page table = 22 bits
Outer Page Table-1 Size-
Outer page table-1 is required to keep track of the frames storing the pages of inner page table.
Outer page table-1 size
= Number of entries in outer page table-1 x Page table entry size
= Number of pages the inner page table is divided x Page table entry size
= 226 x 4 bytes
= 228 bytes
= 256 MB
Now, we can observe-
 The size of outer page table-1 is greater than the frame size (16 MB).
 Thus, outer page table-1 can not be stored in a single frame.
 So, outer page table-1 has to be divided into pages.
Number of Pages of Outer Page Table-1
Number of pages the outer page table-1 is divided
= Outer page table-1 size / Page size
= 256 MB / 16 MB
= 16 pages
Now, these 16 pages of outer page table-1 are stored in different frames of the main memory.
Number of Page Table Entries in One Page of Outer Page Table-1
Number of page table entries in one page of outer page table-1
= Page size / Page table entry size
= 16 MB / 4 B
= 224 B / 22 B
= 222 entries
Number of Bits Required to Search an Entry in One Page of Outer Page Table-1
One page of outer page table-1 contains 222 entries.
Thus,
Number of bits required to search a particular entry in one page of outer page table-1 = 22 bits
Outer Page Table-2 Size-
Outer page table-2 is required to keep track of the frames storing the pages of outer page table-1.
Outer page table-2 size
= Number of entries in outer page table-2 x Page table entry size
= Number of pages the outer page table-1 is divided x Page table entry size
= 16 x 4 bytes
= 64 bytes
Now, we can observe-
 The size of outer page table-2 is less than the frame size (16 MB).
 Thus, outer page table-2 can be stored in a single frame.
 In fact, outer page table-2 will not completely occupy one frame and some space will remain vacant.
 So, for given system, we will have three levels of page table.
 Page Table Base Register (PTBR) will store the base address of the outer page table-2.
Number of Bits Required to Search an Entry in Outer Page Table-2
Outer page table-2 contains 16 = 24 entries.
Thus,
Number of bits required to search a particular entry in outer page table-2 = 4 bits
Page Fault-
 When a page referenced by the CPU is not found in the main memory, it is called as a page fault.
 When a page fault occurs, the required page has to be fetched from the secondary memory into the main memory.
Translating Logical Address into Physical Address-
In a paging scheme using TLB with possibility of page fault,
The logical address generated by the CPU is translated into the physical address using the following steps-
Step-01:
CPU generates a logical address consisting of two parts-
 Page Number
 Page Offset
Step-02:
 TLB is checked to see if it contains an entry for the referenced page number.
 The referenced page number is compared with the TLB entries all at once.
Now, two cases are possible-
Case-01: If there is a TLB hit-
 If TLB contains an entry for the referenced page number, a TLB hit occurs.
 In this case, TLB entry is used to get the frame number for the referenced page number.
Case-02: If there is a TLB miss-

 If TLB does not contain an entry for the referenced page number, a TLB miss occurs.
 In this case, page table is used to get the frame number for the referenced page number.
 The valid / invalid bit of the page table entry indicates whether the referenced page is present in the main memory or
not.
 Now, two cases are possible-
Case-01: If Valid / Invalid Bit is Set to 1-
 If valid / invalid bit is set to 1, it indicates that the page is present in the main memory.
 Then, page table is used to get the frame number for the referenced page number.
 Then, TLB is updated with the page number and its frame number for future references.
Case-02: If Valid / Invalid Bit is Set to 0-
 If valid / invalid bit is set to 0, it indicates that the page is not present in the main memory.
 A page fault occurs.
 The occurrence of page fault calls the page fault interrupt which executes the page fault handling routine.
Page Fault Handling Routine-
The following sequence of events take place-
 The currently running process is stopped and context switching occurs.
 The referenced page is copied from the secondary memory to the main memory.
 If the main memory is already full, a page is replaced to create a room for the referenced page.
 After copying the referenced page successfully in the main memory, the page table is updated.
 When the execution of process is resumed, step-02 repeats.
Step-03:
 After the frame number is obtained, it is combined with the page offset to generate the physical address.
 Then, physical address is used to read the required word from the main memory.
Flowchart-
The following flowchart illustrates the above steps of translating logical address into physical address-

Page Fault Service Time-

 The time taken by the page fault handling routine to service the page fault is called as page fault service time.
 Page fault service time is much greater than main memory access time.
 It increases the effective access time.
Page Replacement-
Page replacement is a process of swapping out an existing page from the frame of a main memory and replacing it
with the required page.
Page replacement is required when-
 All the frames of main memory are already occupied.
 Thus, a page has to be replaced to create a room for the required page.

Page Replacement Algorithms-

Page replacement algorithms help to decide which page must be swapped out from the main memory to create a room for the
incoming page.
Various page replacement algorithms are-
 FIFO Page Replacement Algorithm
 LIFO Page Replacement Algorithm
 LRU Page Replacement Algorithm
 Optimal Page Replacement Algorithm
 Random Page Replacement Algorithm
 A good page replacement algorithm is one that minimizes the number of page faults.
FIFO Page Replacement Algorithm-
 As the name suggests, this algorithm works on the principle of “First in First out“.
 It replaces the oldest page that has been present in the main memory for the longest time.
 It is implemented by keeping track of all the pages in a queue.
LIFO Page Replacement Algorithm-
 As the name suggests, this algorithm works on the principle of “Last in First out“.
 It replaces the newest page that arrived at last in the main memory.
 It is implemented by keeping track of all the pages in a stack.

NOTE Only frame is used for page replacement during entire procedure after all the frames get occupied.

LRU Page Replacement Algorithm-

 As the name suggests, this algorithm works on the principle of “Least Recently Used“.
 It replaces the page that has not been referred by the CPU for the longest time.
Optimal Page Replacement Algorithm-
 This algorithm replaces the page that will not be referred by the CPU in future for the longest time.
 It is practically impossible to implement this algorithm.
 This is because the pages that will not be used in future for the longest time can not be predicted.
 However, it is the best known algorithm and gives the least number of page faults.
 Hence, it is used as a performance measure criterion for other algorithms.
Random Page Replacement Algorithm-
 As the name suggests, this algorithm randomly replaces any page.
 So, this algorithm may behave like any other algorithm like FIFO, LIFO, LRU, Optimal etc.
PRACTICE PROBLEMS BASED ON PAGE REPLACEMENT ALGORITHMS-
Problem-01:A system uses 3 page frames for storing process pages in main memory. It uses the First in First out (FIFO) page
replacement policy. Assume that all the page frames are initially empty. What is the total number of page faults that will occur
while processing the page reference string given below-
4 , 7, 6, 1, 7, 6, 1, 2, 7, 2
Also calculate the hit ratio and miss ratio.
Solution-
Total number of references = 10
From here,
Total number of page faults occurred = 6
Calculating Hit ratio-
Total number of page hits
= Total number of references – Total number of page misses or page faults
= 10 – 6
=4
Thus, Hit ratio
= Total number of page hits / Total number of references
= 4 / 10
= 0.4 or 40%
Calculating Miss ratio-
Total number of page misses or page faults = 6
Thus, Miss ratio
= Total number of page misses / Total number of references
= 6 / 10
= 0.6 or 60%
Alternatively,
Miss ratio
= 1 – Hit ratio
= 1 – 0.4
= 0.6 or 60%
Problem-02:A system uses 3 page frames for storing process pages in main memory. It uses the Least Recently Used (LRU)
page replacement policy. Assume that all the page frames are initially empty. What is the total number of page faults that will
occur while processing the page reference string given below-
4 , 7, 6, 1, 7, 6, 1, 2, 7, 2
Also calculate the hit ratio and miss ratio.
Solution- Total number of references = 10

From here,
Total number of page faults occurred = 6
In the similar manner as above-
 Hit ratio = 0.4 or 40%
 Miss ratio = 0.6 or 60%
Problem-03:A system uses 3 page frames for storing process pages in main memory. It uses the Optimal page replacement
policy. Assume that all the page frames are initially empty. What is the total number of page faults that will occur while
processing the page reference string given below-
4 , 7, 6, 1, 7, 6, 1, 2, 7, 2
Also calculate the hit ratio and miss ratio.
Solution-
Total number of references = 10
 From here,
Total number of page faults occurred = 5
In the similar manner as above-
 Hit ratio = 0.5 or 50%
 Miss ratio = 0.5 or 50%
Belady’s Anomaly-
Belady’s Anomaly is the phenomenon of increasing the number of page faults on increasing the number of frames in main
memory.
Following page replacement algorithms suffer from Belady’s Anomaly-
 FIFO Page Replacement Algorithm
 Random Page Replacement Algorithm
 Second Chance Algorithm
NOTE-In the above discussion,
 “Algorithms suffer from Belady’s Anomaly” does not mean that always the number of page faults will increase on
increasing the number of frames in main memory.
 This unusual behavior is observed only sometimes.
Reason Behind Belady’s Anomaly-
 An algorithm suffers from Belady’s Anomaly if and only if it does not follow stack property.
 Algorithms that follow stack property are called as stack based algorithms.
 Stack based algorithms do not suffer from Belady’s Anomaly.
 This is because these algorithms assign priority to a page for replacement that is independent of the number of frames
in the main memory.
Examples-Following page replacement algorithms are stack based algorithms-
1. LRU Page Replacement Algorithm
2. Optimal Page Replacement Algorithm
Hence, they do not suffer from Belady’s Anomaly.
Stack Property-
Consider-
 Initially, we had ‘m’ number of frames in the main memory.
 Now, the number of frames in the main memory is increased to ‘m+1’.
According to stack property-
 At each stage, the set of pages that were present in the main memory when number of frames is ‘m’ will be
compulsorily present in the corresponding stages in main memory when the number of frames is increased to ‘m+1’.
The following illustrations explain it clearly.
Illustration-01: For Optimal Page Replacement Algorithm-
Consider the reference string is-
0, 1, 2, 3, 0, 1, 4, 0, 1, 2, 3, 4
Now, observe the following two cases-
Case-01: When frame size = 3

Number of page faults = 7

Case-02: When frame size = 4

Number of page faults = 6
From here, we can observe-
 At all the stages in case-02, main memory compulsorily contains the set of pages that are present in the corresponding
stages in case-01.
 Thus, optimal page replacement algorithm follows the stack property.
 Hence, it does not suffer from Belady’s Anomaly.
 As a proof, number of page faults decrease when the number of frames is increased from 3 to 4.
Illustration-02: For LRU Page Replacement Algorithm-
Consider the reference string is-
0, 1, 2, 3, 0, 1, 4, 0, 1, 2, 3, 4
Now, observe the following two cases-
Case-01: When frame size = 3

Number of page faults = 10

Case-02: When frame size = 4

Number of page faults = 8

From here, we can observe-
 At all the stages in case-02, main memory compulsorily contains the set of pages that are present in the corresponding
stages in case-01.
 Thus, LRU page replacement algorithm follows the stack property.
 Hence, it does not suffer from Belady’s Anomaly.
 As a proof, number of page faults decrease when the number of frames is increased from 3 to 4.

Illustration-03: For FIFO Page Replacement Algorithm-

Consider the reference string is-
0, 1, 2, 3, 0, 1, 4, 0, 1, 2, 3, 4
Now, observe the following two cases-
Case-01: When frame size = 3
Number of page faults = 9
Case-02: When frame size = 4

Number of page faults = 10

From here, we can observe-
 At stage-07 and stage-08 in case-02, main memory does not contain the set of pages that are present in the
corresponding stages in case-01.
 Thus, FIFO page replacement algorithm does not follow the stack property.
 Hence, it suffers from Belady’s Anomaly.
 As a proof, number of page faults increase when the number of frames is increased from 3 to 4.
NOTE In the above illustration,
 FIFO Page Replacement Algorithm suffers from Belady’s Anomaly.
 It would be wrong to say that “FIFO Page Replacement Algorithm always suffer from Belady’s Anomaly”.
Segmentation-
 Like Paging, Segmentation is another non-contiguous memory allocation technique.
 In segmentation, process is not divided blindly into fixed size pages.
 Rather, the process is divided into modules for better visualization.
Characteristics-
 Segmentation is a variable size partitioning scheme.
 In segmentation, secondary memory and main memory are divided into partitions of unequal size.
 The size of partitions depend on the length of modules.
 The partitions of secondary memory are called as segments.

Example-

Consider a program is divided into 5 segments as-

 Segment Table-
 Segment table is a table that stores the information about each segment of the process.
 It has two columns.
 First column stores the size or length of the segment.
 Second column stores the base address or starting address of the segment in the main memory.
 Segment table is stored as a separate segment in the main memory.
 Segment table base register (STBR) stores the base address of the segment table.
For the above illustration, consider the segment table is-

Here,
 Limit indicates the length or size of the segment.
 Base indicates the base address or starting address of the segment in the main memory.
In accordance to the above segment table, the segments are stored in the main memory as-

Translating Logical Address into Physical Address-

 CPU always generates a logical address.
 A physical address is needed to access the main memory.
Following steps are followed to translate logical address into physical address-
Step-01: CPU generates a logical address consisting of two parts-
 Segment Number
 Segment Offset
  Segment Number specifies the specific segment of the process from which CPU wants to read the data.
 Segment Offset specifies the specific word in the segment that CPU wants to read.
Step-02:
 For the generated segment number, corresponding entry is located in the segment table.
 Then, segment offset is compared with the limit (size) of the segment.
Now, two cases are possible-
Case-01: Segment Offset >= Limit
 If segment offset is found to be greater than or equal to the limit, a trap is generated.
Case-02: Segment Offset < Limit
 If segment offset is found to be smaller than the limit, then request is treated as a valid request.
 The segment offset must always lie in the range [0, limit-1],
 Then, segment offset is added with the base address of the segment.
 The result obtained after addition is the address of the memory location storing the required word.
Diagram-The following diagram illustrates the above steps of translating logical address into physical address-

Advantages-The advantages of segmentation are-

 It allows to divide the program into modules which provides better visualization.
 Segment table consumes less space as compared to Page Table in paging.
 It solves the problem of internal fragmentation.

Disadvantages-The disadvantages of segmentation are-

 There is an overhead of maintaining a segment table for each process.
 The time taken to fetch the instruction increases since now two memory accesses are required.
 Segments of unequal size are not suited for swapping.
 It suffers from external fragmentation as the free space gets broken down into smaller pieces with the processes being
loaded and removed from the main memory.
PRACTICE PROBLEM BASED ON SEGMENTATION-
Problem-Consider the following segment table-

Segment
Base Length
No.

0 1219 700

1 2300 14

2 90 100

3 1327 580

4 1952 96

Which of the following logical address will produce trap addressing error?
1. 0, 430
2. 1, 11
3. 2, 100
4. 3, 425
5. 4, 95
Calculate the physical address if no trap is produced.
Solution-
In a segmentation scheme, the generated logical address consists of two parts-
 Segment Number
 Segment Offset
We know-
 Segment Offset must always lie in the range [0, limit-1].
 If segment offset becomes greater than or equal to the limit of segment, then trap addressing error is produced.
Option-A: 0, 430- Here,
 Segment Number = 0
 Segment Offset = 430
We have,
 In the segment table, limit of segment-0 is 700.
 Thus, segment offset must always lie in the range = [0, 700-1] = [0, 699]
Now,
 Since generated segment offset lies in the above range, so request generated is valid.
 Therefore, no trap will be produced.
 Physical Address = 1219 + 430 = 1649
Option-B: 1, 11-
Here,
 Segment Number = 1
 Segment Offset = 11
We have,
 In the segment table, limit of segment-1 is 14.
 Thus, segment offset must always lie in the range = [0, 14-1] = [0, 13]
Now,
 Since generated segment offset lies in the above range, so request generated is valid.
 Therefore, no trap will be produced.
 Physical Address = 2300 + 11 = 2311
Option-C: 2, 100-
Here,
 Segment Number = 2
 Segment Offset = 100
We have,
 In the segment table, limit of segment-2 is 100.
  Thus, segment offset must always lie in the range = [0, 100-1] = [0, 99]
Now,
 Since generated segment offset does not lie in the above range, so request generated is invalid.
 Therefore, trap will be produced.
Option-D: 3, 425-
Here,
 Segment Number = 3
 Segment Offset = 425
We have,
 In the segment table, limit of segment-3 is 580.
 Thus, segment offset must always lie in the range = [0, 580-1] = [0, 579]
 Now,
 Since generated segment offset lies in the above range, so request generated is valid.
 Therefore, no trap will be produced.
 Physical Address = 1327 + 425 = 1752
Option-E: 4, 95-
Here,
 Segment Number = 4
 Segment Offset = 95
We have,
 In the segment table, limit of segment-4 is 96.
 Thus, segment offset must always lie in the range = [0, 96-1] = [0, 95]
Now,
 Since generated segment offset lies in the above range, so request generated is valid.
 Therefore, no trap will be produced.
 Physical Address = 1952 + 95 = 2047
Thus, Option-(C) is correct.
Segmented Paging-

Segmented paging is a scheme that implements the combination of segmentation and paging.
Working-
In segmented paging,
 Process is first divided into segments and then each segment is divided into pages.
 These pages are then stored in the frames of main memory.
 A page table exists for each segment that keeps track of the frames storing the pages of that segment.
 Each page table occupies one frame in the main memory.
 Number of entries in the page table of a segment = Number of pages that segment is divided.
 A segment table exists that keeps track of the frames storing the page tables of segments.
 Number of entries in the segment table of a process = Number of segments that process is divided.
 The base address of the segment table is stored in the segment table base register.
Translating Logical Address into Physical Address-
 CPU always generates a logical address.
 A physical address is needed to access the main memory.
Following steps are followed to translate logical address into physical address-
Step-01:
CPU generates a logical address consisting of three parts-
 Segment Number
 Page Number
 Page Offset
  Segment Number specifies the specific segment from which CPU wants to reads the data.
 Page Number specifies the specific page of that segment from which CPU wants to read the data.
 Page Offset specifies the specific word on that page that CPU wants to read.
Step-02:
 For the generated segment number, corresponding entry is located in the segment table.
 Segment table provides the frame number of the frame storing the page table of the referred segment.
 The frame containing the page table is located.
Step-03:
 For the generated page number, corresponding entry is located in the page table.
 Page table provides the frame number of the frame storing the required page of the referred segment.
 The frame containing the required page is located.
Step-04:
 The frame number combined with the page offset forms the required physical address.
 For the generated page offset, corresponding word is located in the page and read.

Diagram-

The following diagram illustrates the above steps of translating logical address into physical address-

Advantages-The advantages of segmented paging are-

 Segment table contains only one entry corresponding to each segment.
 It reduces memory usage.
 The size of Page Table is limited by the segment size.
 It solves the problem of external fragmentation.
Disadvantages-
The disadvantages of segmented paging are-
 Segmented paging suffers from internal fragmentation.
 The complexity level is much higher as compared to paging.