2010 9th IEEE/IAS International Conference on Industry Applications

- INDUSCON 2010 -

A High Voltage Gain Sepic Converter Based on

Three-State Switching Cell
Levy F. Costa(1), René P. T. Bascopé(1), Grover V. T. Bascopé(2), Gean J. M. Sousa(1), Ronny G. A. Cacau(1)
(1)
Energy Processing and Control Group-GPEC, Electrical Engineering Department, Federal University of Ceará
Cx Postal 6001 - Campus do Pici, 60455-700, Fortaleza - CE - Brazil
E-mail: [email protected], [email protected]
(2)
Huawei Technologies Sweden AB
Skalholtsgatan 9-11, Box: 54, SE- 164 94 Kista, Sweden
[email protected]

D1
L1 C1 D1 L1 +
Abstract - This paper presents a high voltage gain DC-DC
+ - + Vo
converter. The proposed converter is based on the Sepic topology C2 R0
Vi S1 L2 C2 R0 Vo Vi S1
using the three-state switching cell. This converter is suitable for - C1
-

applications with a high voltage gain between the input and the L2 - +

output, as well as, UPS and renewable energy system. Another (a)
b (b)
important feature of this converter is the lower blocking voltage b

across the controlled switches compared to similar circuits, which D3 D4

D2 D1 C2
T1 L2 +
allows the utilization of MOSFETs switches with lower conduction c
c

resistances RDS(on). Principles of operation, theoretical analysis S2 S3 L1

Ro Vo
S2 S1
and design example of the proposed converter as well as Vi
-
experimental results for a 1kW prototype are presented in this a
a
C1
work. (c) (d) (e)
Fig. 1. Procedure to obtain the Sepic converter with three-state switching cell.

I. INTRODUCTION to elevate the input voltage up to the required output voltage

When the application desires high voltage gain, as to step level. This idea was adequate only for the development of low
the low batteries voltage (12Vdc – 48Vdc) up to feed a voltage power converters, since many switches with high voltage stress
source inverter (300Vdc – 400Vdc), the classical topologies are and many capacitors are necessary.
not a good choice. This application are very common in UPS, The proposed converter is a Sepic (single ended primary
renewable energy, and others system where to store energy is inductor converter) based on the three-state commutation cell
necessary. An alternative might be the utilization of converters [8-11]. Fig. 1 shows how to obtain the Sepic converter with the
in cascade, but this solution achieves a low efficiency, due to three-state switching cell from the conventional Sepic
the amount of power processing stages. To overcome this converter. To simplify, the inductors L1 and L2 from Fig. 1 (e)
disadvantage some solutions using step-up converters capable can be magnetically coupled, using only one core. To provide
of operating with high voltage gain ratio were proposed in the high voltage gain was added to the converter a voltage doubler
literature. rectifier using two diodes and two capacitors. Fig. 2 shows the
Thus, in [1,2] several clamp-mode coupled-inductor boost proposed topology. As advantages, it can be emphasized that
converters operating with the advantages of high voltage gain the input current is non-pulsating with low ripple; the input
ratio and half output voltage stress across the switches were inductor operates within the double of the switching frequency
presented. The disadvantages observed in these converters, allowing weight and volume reduction.
were their pulsating input current and high currents stress
through the clamping capacitors.
Following the brief revision, in [3-5] were proposed several
converters with high static gain, all based on boost-flyback.
They are similar to the topologies proposed in [1,2]. They
present the following advantage: the voltage stress across the
switches is low and naturally clamped by the output filter
capacitor. As disadvantages, it can be indicated that the input
current is pulsating; therefore, a LC input filter is necessary to
get continuous current on the input voltage source.
Finally, in [6,7], switching capacitor techniques were used
Fig. 2. Proposed converter.

978-1-4244-8010-4/10/$26.00 ©2010 IEEE

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DO CEARA. Downloaded on September 13,2023 at 14:12:12 UTC from IEEE Xplore. Restrictions apply.
 It can be also observed that the voltage stress across the in the inductors in the third stage, as well as the energy from the
switches is lower than a half of the output voltage. The lower voltage source are transferred to the filter capacitors C2 and C4.
voltage across the switches, allows the utilization of low The capacitor C1 stores energy provided by the inductor L1.
on-resistance MOSFETs, improving therefore the efficiency. This stage is represented by the circuit shown in Fig. 3.d.
As disadvantage, the converter does not operate appropriately
for duty cycle lower than 0.5, due to magnetic induction
problems of the transformer.

II. PRINCIPLE OF OPERATION

The converter shown in Fig. 2 is composed by the following
devices: voltage source Vi, inductors L1 and L2, transformer T1,
controlled switches S1 and S2, rectifier diodes D1, D2, D3 and D4,
transference capacitor C1, filter capacitors C2, C3, C4, and load
resistor RO.
A. Principle of Operation
a) First stage
In order to explain the principle of operation of this
converter, it is analyzed in continuous conduction mode (CCM)
operating with a duty cycle value of the switches higher than
0.5. For this purpose, the semiconductors and magnetic
elements are considered ideals.
During one commutation period of the converter operation,
it presents four operating stages or intervals that are described
as follows:
First Stage (t0, t1): The switches S1 and S2 are turned-on.
The energy is stored in the inductor L1 fed by the input voltage
source and in the inductor L2 fed by the capacitor C1. In this
stage, there is no energy transference to the load. This stage, b) Second stage
represented in Fig. 3.a finishes when switch S1 is turned-off.
The correspondent differential equations during this stage are
given by (1) and (2).
di
L1 ⋅ L1 − Vi = 0 (1)
dt
di
L2 ⋅ L 2 − VC1 = 0 (2)
dt
Second Stage (t1, t2): In this stage the switch S2 remains
turned-on. The voltage across switch S1 is equal to the voltage
across capacitor C1 plus the voltage across capacitor C2. The
diodes D1 and D3 are directly biased. The energy stored in the
inductors in the first stage, as well as the energy from the c) Third stage
voltage source are transferred to the filter capacitors C2 and C3.
The capacitor C1 stores energy provided by the inductor L1. The
interval results in circuit shown in Fig. 3.b. The differential
equations representing this stage are given by (3) and (4).
di Vi
L1 ⋅ L1 + − Vi = 0 (3)
dt 2 ⋅ (1 − D )
di Vi
L2 ⋅ L 2 + − VC1 = 0 (4)
dt 2 ⋅ (1 − D )
Third Stage (t2, t3): This stage is similar to the first one,
where switches S1 and S2 are turned-on, and the energy is stored
in the inductors L1 and L2. It is finished when switch S2 is d) Fourth stage
turned-off. This stage is represented by the circuit shown in Fig.
3.c. Fig. 3. Operation stages shown topologically.
Fourth Stage (t3, t4): During this stage, the switch S1
remains turned-on. The voltage across switch S2 is equal to the
voltage across the capacitor C1 plus the voltage across capacitor
C2. The diodes D2 and D4 are directly biased. The energy stored

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DO CEARA. Downloaded on September 13,2023 at 14:12:12 UTC from IEEE Xplore. Restrictions apply.
 B. Inductor Design
Using the expressions (1), (5) and the time interval during
the first stage, the current ripple on the inductor is equal to
( 2 D − 1) ⋅ (1 − D ) ⋅ Vo
ΔI L1 = (6)
2 ⋅ f s ⋅ (n + D)
In (6), ΔIL1 is the current ripple on the inductor L1, and fs is
the switching frequency of the converter.
Rearranging the terms in (6), the normalized current ripple
on the inductor is given by
2 ⋅ ΔI L1 ⋅ L1 ⋅ f s (2 D − 1) ⋅ (1 − D )
ΔI L1 = = (7)
Vo (n + D)
Fig. 6 is obtained using (7), and shows the normalized
current ripple on the inductor as a function of the duty cycle.
0.2

0.15
n=0

0.1

n=1
0.05 n=2

n=3
Fig.4. Theoretical waveforms of the converter. 0
0.5 0.6 0.7 0.8 0.9 1
D
III. THEORETICAL ANALYSIS Fig. 6. Normalized ripple current on the inductor L1.

A. Output Characteristic It is possible to conclude that the maximum current ripple on

the inductor occurs when n equal to zero and the duty cycle is
The output-input voltage ratio, named as static gain of the 0.7. In this condition the normalized current ripple is 0.171.
converter, is given by (5). The corresponding curve of this When n is equal to zero, means that the high gain circuit
equation, taking the transformer turns ratio as parameter are composed by the diodes D3, D4, the capacitors C3, C4 and the
shown in Fig. 5. secondary S1 of the transformer shown in Fig. 2 do not exist. For
V n+D a given value to the current ripple, it is possible to obtain the
GV = o = (5)
Vi 1 − D inductor value using
In (5), Vo is the output voltage, Vi is the input voltage, n is Vo
L1 = . (8)
the transformer turn ratio, and D is the duty cycle. 16 ⋅ f s ⋅ (n + 0.7) ⋅ ΔI L1

30
The voltage across the capacitor C1 is equal to voltage of the
input source, then the inductors L1 and L2 are under the same
condition. The inductance of the inductor L2 is obtained using
25
(9).
Vo
20 L2 = (9)
16 ⋅ f s ⋅ (n + 0.7) ⋅ ΔI L1
n=4
Gv

15 C. Transformer Design
n=3
The high frequency transformer must be designed according
10 n=2
to the amount of processed power given by
n=1
( 2a + 1) Po
5 Pp = (10)
n=0 (1 + a ) 2
0 In (10), Pp is the power processed by the transformer, and, Po
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
D is the output power of the converter.
Fig. 5. Static gain of the converter.

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DO CEARA. Downloaded on September 13,2023 at 14:12:12 UTC from IEEE Xplore. Restrictions apply.
 D. Output Capacitors Design The maximum reverse voltage across the diodes D1, D2, D3,
and D4 are given by (16) and (17), respectively.
Considering the output voltage ripple small, the normalized
average voltages across the capacitors C2, C3 e C4 are described V
VD1 = VD2 == i (16)
by (11) and (12). In Fig. 7 is shown the normalized voltage 1− D
curve using (11), corresponding to the capacitor C2, and in Fig.8
n ⋅ Vi
are shown the normalized voltage curves given by (12), VD4 = VD3 == (17)
corresponding to the capacitors C3 and C4. 1− D
VC 2 D
VC 2 = = (11) IV. EXPERIMENTAL RESULTS
Vi 1− D
A. Specifications
VC3 VC3 n 1
VC3 = VC 4 = = = ⋅ (12) In order to verify the operation and evaluate the
Vi Vi 2 1− D
performance of the proposed boost converter using three-state
10 commutation cell, a prototype with the following specifications
was assembled and tested.
8 Vi = 42 − 54VDC Input voltage range
6 Po = 1kW Output power
Vo = 400V Output voltage
4
f s = 25kHz Switching frequency
2
The assumed parameters are: the maximum boost inductor
0
current ripple is ΔI L = 0.15 I i max , the transformer turns ratio is
0.4 0.5 0.6 0.7 0.8 0.9 1
D n = N S / N P = 2.15 , the maximum fixed duty cycle of the
Fig. 7. Normalized voltage across capacitor C2. switches is Dmax = 0.70 to minimum input voltage, and the
10 output voltage ripple is ΔVo=0.15Vo.
B. Design Example
8

n=4
The inductances are obtained according to (8) and (9).
6
n=3 Substituting values in it is equal to
n=2 400
4
L1 = L2 = = 90.0 μH
n=1 16 ⋅ 25000 ⋅ ( 2.15 + 0.7) ⋅ 3.88
2
The transformer of the converter was built using the
0 push-pull DC-DC converter guidelines, for power given by
0.5 0.6 0.7 0.8 0.9 1
D (10). Thus,
Fig. 8. Normalized average voltage across capacitors C3 and C4.
(2 ⋅ 2.15 + 1) 1000
PP = ⋅ = 841.6W
The capacitance of each capacitor can be calculated using ( 2.15 + 1) 2
the expressions (13) and (14),
The capacitances of the output filter capacitors were
(1 − D ) ⋅ Po calculated using (13) and (14). Substituting values, they are
C2 ≥ (13)
2 ⋅ f s ⋅ ΔVo ⋅ Vi ⋅ ( n + D ) obtained as
(1 − 0.7) ⋅ 1000
(1 − D ) ⋅ Po C2 ≥ = 833nF
C3 = C4 ≥ (14) 2 ⋅ 25000 ⋅ 60 ⋅ 42 ⋅ (2.15 + 0.7)
f s ⋅ ΔV o ⋅ Vi ⋅ ( n + D )
(1 − 0.7) ⋅ 1000
In (13) and (14), ΔVo is the total output voltage ripple. C3 = C4 ≥ = 1.67 μF
25000 ⋅ 60 ⋅ 42 ⋅ (2.15 + 0.7)
E. Maximum Voltage across the Switches S1 and S2
The voltage across such capacitors must be higher than the
The maximum normalized voltage across switches S1 and values calculated using (11) and (12). Thus,
S2, without considering overshoots due to layout inductances, is 42
given by (15). VC 2 = = 140V
(1 − 0.7)
VS1 VS2 1
VS1 = VS2 = = = (15) 2.15 42
Vi Vi (1 − D ) VC3 = VC 4 = = 150 .5V
2 (1 − 0.7)
F. Reverse Voltage across the Diodes D1, D2, D3, and D4 The breakdown voltage of the controlled switches must be
higher than the value obtained using (15). Thus,

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DO CEARA. Downloaded on September 13,2023 at 14:12:12 UTC from IEEE Xplore. Restrictions apply.
 42
VS1 = VS2 = = 140V .
(1 − 0.7)
The maximum reverse voltage of the rectifier diodes must
be higher than the values calculated from (16) and (17). Thus,
42
VD1 = VD2 == = 140V
(1 − 0.7)
2.15 ⋅ 42
VD4 = VD3 == = 301V
(1 − 0.7)
The components used to assemble the prototype are listed in
Table I.
Fig. 9. Measured gate-to-source voltages VGS1 and VGs2, current through the
TABLE I. PROTOTYPE COMPONENTS inductor L1 and current through the inductor L2 (10A/div.; 20V/div.; 20V/div.;
2.5A/div.; 10us/div.)
Diodes D1, D2 30CTH03
Diodes D3, D4 30TH 06
L1=L2 =90μH
NEE-55/28/21 (Thornton Ipec)
Inductor L1, L2 NL1= 23 turns (33x26AWG)
NL1= 23 turns (3x26AWG)
δ=1.31mm (gap)
Output Filter Capacitors C1, C2, C3, C4 2.2μF / 400V
Switches S1, S2 IFRP90N20D
NEE-55/28/21 (Thornton Ipec)
High Frequency Transformer Np1=Np2=10 turns (17x25AWG)
Ns1=22 turns (8x25AWG)

C. Experimental Waveforms and Curves

Fig. 10. Measured gate-to-source voltages VGS1 and VGs2, drain-to-source
Fig. 9 shows the measured gate-to-source voltages of voltage VS1 and drain current IS1 (100V/div.; 20V/div.; 20V/div.; 25A/div.;
10us/div.)
switches S1 and S2 and the currents through inductors L1 and L2.
It can be seen in Fig. 9 that the current drawn by the proposed
converter presents a low current ripple, increasing the reliability
of the battery bank for example.
Fig. 10 shows the same control signals of switches S1 and S2
and the voltage and current in the switch S1. According to Fig.
10, the drain-to-source voltage in S1 is lower than half output
voltage, as expected in the theoretical analysis.
Fig. 11 shows the same gating signals as showed before in
Figs. 9-10, the current through the primary of the transformer
and also the voltage across the primary of the transformer. The
resulting current through the diodes D3 and D1 are a bit different
compared to the theoretical waveforms. It is important to notice
that all experimental results present this difference due to the Fig. 11. Measured gate-to-source voltages VGS1 and VGs2, current through
primary of trasformer and voltage across the primary of the transformer
leakage inductance obtained during the construction of the (100V/div.; 20V/div.; 20V/div.; 10A/div.; 10us/div.)
magnetic components.
Fig. 12 shows the current through the diodes D3. The
resulting current through the diode D3, as well as the current in
the transformer are a bit different compared to the theoretical
waveforms. It is important to notice that all experimental results
present this difference due to the leakage inductance obtained
during the construction of the magnetic components.
Fig. 13 shows the secondary voltage and current in the
transformer Tr, where a symmetry of each semi-cycle is
observed.
Finally, Fig. 13 presents the efficiency of the converter as a
function of the output power. This converter presented a good
efficiency compared to the previous works that can also be Fig. 12. Measured gate-to-source voltages VGS1 and VGs2, current through diode
improved if the design is optimized. D3 (20V/div.; 20V/div.; 5A/div.; 10us/div.)

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DO CEARA. Downloaded on September 13,2023 at 14:12:12 UTC from IEEE Xplore. Restrictions apply.
 application where high voltage gain between the input and the
output voltages are required, the proposed circuit is incased.
The practical application, such as, photovoltaic systems and
UPS systems requires this type of converter.
One advantage of this topology is that there is no direct path
for dc current between the input and output of the converter,
then in a fault condition the input voltage does not appear at
converter output. Other features that can be seen in the
experimental results are the lower blocking voltages across the
controlled switches compared to similar circuits, which allow
the utilization of MOSFETs switches with lower conduction
losses.
Fig. 13. . Measured gate-to-source voltages VGS1 and VGs2, secondary voltage The qualitative analysis, theoretical analysis, and the
and current in the transformer (100V/div.; 20V/div.; 20V/div.; 25A/div.;
10us/div.)
experimental results were presented for a 1kW prototype. The
converter achieved reasonable efficiency for nominal load and
better efficiency for lower loads.

REFERENCES

[1] Qun Zhao, Fengfeng Tao, Yougxuan Hu, and Fred C. Lee, “DC/DC
Converters Using Magnetic Switches”, in IEEE Applied Power
Electronics Conference and Exposition, 2001, APEC2001, Vol.2, 4-8
March 2001, pp. 946-952.
[2] Qun Zhao, and Fred C. Lee. “High-Effiency, High Step-Up DC-DC
Converters”, in IEEE Transactions on Power Electronics, Vol. 18, No1,
January 2003, pp. 65-73.
[3] K. C. Tseng and T. J. Liang, “Novel high-efficiency step-up converter”, in
IEE Proc. Electr. Power Appl., Vol. 151, No.2, March 2004, pp. 182-190.
[4] R. J. Wai and R. Y. Duan, ‘High-efficiency DC/DC converter with high
voltage gain”, in IEE Proc. Electr. Power Appl., Vol. 152, No.4, July
2005, pp. 793-802.
[5] J. W. Baek. M. H. Ryoo, T. J. Kim, D. W. Yoo, and J. S. Kim, “High Boost
Converter Using Voltage Multiplier” , in IEEE Industrial Electronics
Conference, 2005, pp.567-572.
[6] B. Axelrod, Y. Berkovich, and A. Ioinovici, “Transformerless DC-DC
Converters with a very High DC Line-to-Load Voltage Ratio”, in Proc. of
the 2003 International Symposium on Circuits and Systems, 2003,
Fig. 14. Efficiency of the converter, as a function of the output power. ISCAS´03, Vol.3, 25-28 May 2003, pp. III-435 - III-438.
[7] O. Abutbul, A. Gherlitz, Y. Berkovich, and A. Ioinovici, “Step-Up
V. PICTURE OF THE ASSEMBLED PROTOTYPE Switching-Mode Converter with High Voltage Gain Using a
Switched-Capacitor Circuit”, in IEEE Transactions on Circuits and
Systems – I:Fundamental Theory and Applications, Vol. 50, No.8, August
The picture of the 1kW assembled prototype is shown in 2003, pp.1098-1102.
[8] Grover V. Torrico Bascopé, and Ivo Barbi. “Generation of a Family of
Fig. 15. Non-Isolated Dc-Dc PWM Converters Using New Three-State Switching
Cells”, in IEEE Power Electronic Specialists Conference, 2000, PESC’00,
Vol.2, 18-23 June 2000, pp. 858-863.
[9] G. V. Torrico-Bascopé, “New Family of Non-isolated DC-DC PWM
Converters Using the Three-State Switching Cell”, Ph.D. thesis, Dept.
Elect. Eng., Federal University of Santa Catarina, Brazil, 2001.
[10] G. V. T. Bascopé, R. P. T. Bascopé, D. S. Oliveira Jr., S. V. Araújo, F. L.
M. Antunes, C. G. C. Branco. “A High Step-Up Converter Based on
Three-State Switching Cell”. In: Proc. of ISIE '2006 - IEEE International
Symposium on Industrial Electronics Proceedings, pp. 998-1003, 2006.
[11] G. V. T. Bascopé, R. P. T. Bascopé, D. S. Oliveira Jr., S. V. Araújo, F. L.
M. Antunes, C. G. C. Branco. “A Generalized High Voltage Gain Boost
Converter Based on Three-State Switching Cell”. In: Proc. of IECON
'2006 - IEEE Industrial Electronics, Control and Instrumentation
Proceedings, pp. 1927-1932, 2006.

Fig. 15. Picture of the proposed converter.

VI. CONCLUSIONS
This paper has proposed a non-isolated Sepic converter with
a high voltage gain based on three-state switching cell. In

Authorized licensed use limited to: UNIVERSIDADE FEDERAL DO CEARA. Downloaded on September 13,2023 at 14:12:12 UTC from IEEE Xplore. Restrictions apply.