Hello, and welcome to this presentation of the STM32G0

reset and clock controller.

1
The RCC unit implemented in the STM32G0 offers new
features with regard to STM32F0 microcontrollers.
The NRST pin has 3 possible usages:
1. reset input used by an external logic to signal a reset
condition to the STM32G0
2. reset input & output (legacy mode), any valid reset
signal on the pin is propagated to device internal
logic and all internal reset sources are externally
driven through a pulse generator to this pin
3. GPIO, in this mode, the pin can be used as standard
GPIO, reset is only possible from the device’s
internal reset sources.
The reset holder option can be used, if enabled in the
option bytes, to ensure that the pin is pulled low until its
voltage meets the VIL threshold.
The PLL has 3 post-dividers providing 3 independent
outputs: PLLPCLK, PLLQCLK and PLLRCLK.

2
The Clock Security System (CSS) also monitors the LSE
and detect failures. If the low-speed external 32.768 kHz
oscillator (LSE) is used as system clock, and a failure of
LSE clock is detected, the system clock switches
automatically to the low-speed internal 32 kHz RC
oscillator (LSI).
HSISYS is the high-speed internal 16 MHz RC oscillator
(HSI16) divided by a programmable ratio in range 1-128.
PLLQCLK is selectable for high-speed TIM1 and TIM15
timers, its frequency must be set so as not to exceed 128
MHz. This is twice the maximum frequency of the
Cortex®-M0+.

2
The STM32G0 reset and clock controller manages
system and peripheral clocks. STM32G0 devices embed
two internal oscillators, 2 oscillators for an external
crystal or resonator, and one phase-locked loop (PLL).
Many peripherals have their own clock, independent of
the system clock.
The RCC also manages the various resets present in the
device.
The STM32G0 RCC provides high flexibility in the choice
of clock sources, which allows the system designer to
meet both power consumption and accuracy
requirements. The numerous independent peripheral
clocks allow a designer to adjust the system power
consumption without impacting the communication baud
rates, and also keep some peripherals active in low-
power modes. Finally, the RCC provides safe and flexible
reset management.

3
Safe and flexible reset management without any need for
external components reduces application costs.
The RCC manages three types of resets: the system
reset, the power reset and the backup domain reset.
The peripherals have individual reset control bits.

4
The first type of reset is the System reset, which resets
all the registers except certain registers for the Reset
and Clock Controller. It also does not reset the RTC
domain.
The System reset sources are:
• The external reset (generated by a low level on the
NRST pin),
• A window watchdog event,
• An independent watchdog event,
• A software reset request,
• A low-power-mode security reset (which is generated
when Stop, Standby or Shutdown mode is entered
but is prohibited by the option byte configuration),
• An option byte loader reset,
• And a Brown-out or Power-on reset.
The reset source flag can be found in the RCC Control
and Status register.

5
Two fields in the option bytes are used to configure the
NRST pin:
• NRST_MODE selects the operation mode of the
NRST pin: input / output reset, input only reset or
GPIO.
• IRHEN stands for Internal Reset Holder Enable.
When this mode is enabled, the NRST pin is driven
low until its voltage level goes under the voltage input
low threshold.

6
Here is the simplified block diagram of the system reset.
All internal reset sources provide a reset signal on the
NRST pin, which can be used to reset other components
of the application board. In addition, no external reset
circuitry is needed due to the internal glitch filter and the
safe power monitoring feature which guarantees the
reset of the application when VDD is below the selected
threshold. The internal pull-up on the NRST pin, which
maintains a high level when no reset signal drives it low,
is deactivated when an internal reset is driven in order to
reduce power consumption under reset. Additionally,
except the debug pins and some test pins, all I/O pins
are placed in analog mode during and after reset to
eliminate power consumption through the Schmitt trigger
when the I/Os are floating under reset and before
software initialization.

7
The purpose of the reset holder is to maintain NRST driven
LOW until the voltage level of this signal goes below VIL.
This is useful when the NRST line has an important
capacitive load.

8
The second type of reset is the Power reset. The Brown-
out reset (BOR) resets all registers except those in the
RTC domain powered by VBAT which contains the RTC,
the backup registers and the external low-speed
oscillator. When exiting Standby mode, all registers
powered by the regulator are reset. When exiting
Shutdown mode, a Brown-out reset is generated.
The third type of reset is the RTC domain reset, which
resets the RTC registers, the Backup registers, and the
RTC Domain Control Register. This reset occurs when
the BDRST bit is set in the RTC Domain control register.
It also occurs when VDD and VBAT are powered on if
both supplies have previously been powered off.

9
The RCC offers a large choice of clock sources, which
can be selected depending on low-power, accuracy, and
performance requirements.
STM32G0 devices embed two internal clock sources: a
high-speed internal 16 MHz RC oscillator (HSI16) and a
low-speed internal 32 kHz RC oscillator (LSI).
STM32G0 devices embed two oscillators for use with an
external crystal or resonator: a high-speed external 4 to
48 MHz oscillator (HSE) with a clock security system and
a low-speed external 32.768 kHz oscillator (LSE) also
with a clock security system.
STM32G0 devices embed a phase-locked loop with
three independent outputs for clocking different
peripherals at different frequencies.

10
The system clock can be derived from the high-speed
internal 16 MHz RC oscillator (HSI16), the high-speed
external 4 to 48 MHz oscillator (HSE), the low-speed
internal oscillator (LSI) or the low-speed external
oscillator (LSE). The AHB clock, called HCLK, is derived
by dividing the system clock by a programmable
prescaler. The APB clock, called PCLK is generated by
dividing the AHB clock by a programmable prescaler.

The RTC clock is generated by the low-speed external

32.768 kHz oscillator (LSE), the low-speed internal 32
kHz RC oscillator (LSI), or the HSE divided by 32.

The LSE can remain enabled in all low-power modes

and in VBAT mode, because the LSE belongs to the
RTC power domain.
The LSI can remain enabled in all modes except

11
Shutdown and VBAT modes.

11
Stop modes (Stop 0 and Stop 1) stop all the clocks in the
VCORE domain and disable the PLL as well as the
HSI16 and HSE oscillators.
The high-speed internal oscillator (HSI16) is a 16 MHz
RC oscillator which provides 1% accuracy and fast
wakeup times. The HSI16 is trimmed during production
testing, and can also be user-trimmed.
The HSISYS clock (which is the HSI16 clock divided by
HSIDIV) is used as the clock at wakeup from Stop 0 or
Stop 1 modes.
HSI16 is can be used as a backup clock source
(auxiliary clock) if the HSE crystal oscillator fails, which is
detected by the Clock Security System.
The USART1, USART2, LPUART1, CEC, UCPD and
I2C1 peripherals can enable the HSI16 oscillator even
when the MCU is in Stop mode (if HSI16 is selected as
clock source for that peripheral).

12
This table provides the characteristics of the HSI16
clock.
The HSI16 accuracy can be improved by implementing a
trimming procedure, by measuring its frequency with the
TIM14, TIM16 or TIM17 by clocking the timer by HSI
clock and providing precise clock reference like HSE/32,
RTCCLK or LSE on their channel 1 input capture.
The HSI clock has a typical 1 microsecond startup time
while the HSE clock has a typical 2 millisecond startup
time.
The high-speed external oscillator provides a safe crystal
system clock.
The HSE supports a 4 to 48 MHz external crystal or
ceramic resonator, and also an external source in
Bypass mode.
A clock security system allows an automatic detection of
HSE failure. In this case a Non-Maskable Interrupt is
generated, and a break input can be sent to timers in
order to put critical applications such as motor control in
a safe state. When an HSE failure is detected, the HSE
oscillator is automatically disabled.
If HSE is selected directly or indirectly (PLLRCLK
selected for SYSCLK and HSE selected as PLL input) as
system clock, and a failure of HSE clock is detected, the
system clock switches automatically to HSISYS, so the
application software does not stop in case of crystal
oscillator failure.

14
In External source mode, also called HSE bypass mode,
an external clock source must be provided. It can have a
frequency of up to 48 MHz.
The external clock signal (square, sinus or triangle) with
40-60 % duty cycle depending on the frequency must
drive the OSC_IN pin.
The OSC_OUT pin can be used as GPIO or it can be
configured as an OSC_EN alternate function to provide a
signal enabling the stop of the external clock synthesizer
when the device enters low-power modes.

15
STM32G0 devices embed an ultra-low-power 32 kHz RC
oscillator, which is available in all modes except
Shutdown and VBAT.
The LSI can be used to clock the RTC, the low-power
timers, and the independent watchdog. The LSI
consumption is typically 110 nA.

16
The 32.768 kHz low-speed external oscillator can be
used with external quartz or resonator, or with an
external clock source in Bypass mode. The oscillator
driving capability is programmable. Four modes are
available, from an ultra-low power mode with a
consumption of only 250 nanoamperes, to a high-driving
mode.
A clock security system monitors for failure of the LSE
oscillator. If LSE is used as system clock, and a failure of
LSE clock is detected, the system clock switches
automatically to LSI. The CSS is functional in all modes
except Shutdown and VBAT. It is also functional under
reset.
The LSE can be used to clock the RTC, the CEC, the
USARTs or low-power UART peripherals, and the low-
power timers.

17
STM32G0 devices embed a phase-locked loop, each
with 3 independent outputs. The input clock of the PLL
can be selected between HSI16 and HSE.
PLLQCLK can be used to clock the RNG and timers
TIM1 and TIM15.
PLLPCLK can be used to clock I2S1 and ADC.
PLLRCLK can be selected as the system clock called
SYSCLK, which is the root clock for AHB and APB clock
domains.
Note that PLLQCLK and PLLPCK maximum frequencies
are larger than the maximum SYSCLK frequency.
Range 1 and Range 2 are two different power ranges
that can be programmed in the main regulator in order to
optimize the consumption depending on the system
maximum operating frequency.

18
The system clock is selected between the HSI16, HSE,
LSI, LSE and PLL output.
The maximum system clock frequency is 64Hz. The
APB1 and APB2 bus frequencies are also up to 64 MHz.
The maximum clock source frequency depends on the
voltage scaling and power mode. The system clock is
limited to 64 MHz in Range 1, 16 MHz in Range 2 and 2
MHz in Low-power run/Low-power sleep modes.
The various clocks can be output on an I/O. The
Microcontroller Clock Output feature allows you to output
on a pin one of these six clocks, HSI16, HSE, LSI, LSE,
SYSCLK, and PLLCLK.
The low-speed clock output (LSCO) feature allows the
output of the LSI or LSE clock on a pin. The low-speed
clock output is available in Stop 0, Stop 1, Standby and
Shutdown modes. This is enabled by setting the
LSCOEN bit in the RCC_BDCR register.
Note that LSI is not available in Shutdown mode.

20
The dynamic power consumption can be optimized by
using peripheral clock gating.
Each peripheral clock can be gated ON or OFF in Run
and Low-power run modes.
By default, the peripheral’s clock is disabled, except the
Flash memory clock which is enabled by default. When a
peripheral’s clock is disabled, the peripheral’s registers
cannot be read or written.
Other registers allow for configuring the peripheral’s
clock during the Stop, Sleep and Low-power sleep
modes. This also affects Stop 0 and Stop 1 modes for
peripherals with an independent clock active in Stop
modes. These control bits have no effect if the
corresponding peripheral clock enable is cleared. By
default no active peripheral clock is gated in Stop, Sleep
and Low-power Sleep modes. When a peripheral is not
needed, its clock enable bit should be cleared to reduce

21
the power consumption.

21
This slide lists the RCC interrupts. The LSE and HSE
clock security systems, the PLL ready, and all five
oscillator ready signals can generate an interrupt.
In addition to this training, you may find the Power
Control and Interrupt Controller trainings useful.

23
For more details, please refer to application note
AN2867, an oscillator design guide for STM8S, STM8A
and STM32 microcontrollers and application note
AN5126 which explains how to calibrate STM32G0
internal RC oscillators.

24