COMPUTER ARCHITECTURE

PIPELINE HAZARDS

Falguni Sinhababu
Government College of Engineering and Leather Technology

PIPELINE HAZARDS 1
 Pipeline the data path

PIPELINE HAZARDS
 PIPELINE IN EXECUTION INSTRUCTIONS
▪ Instruction execution is typically divided into 5
stages:
▪ Instruction Fetch (IF)
▪ Instruction Decode (ID)
▪ ALU Operation (EX)
▪ Memory Access (MEM)
▪ Write back result to register (WB)
▪ These five stages can be executed in a overlap
fashion in a pipeline architecture.
▪ Results in significant speedup by overlapping instruction
execution.

PIPELINE HAZARDS
 BASIC REQUIREMENT
▪Basic requirements for pipeline the data path
▪ We should able to start a new instruction in every
clock cycle.
▪ Each of the five steps mentioned before (IF, ID, EX,
MEM and WB) becomes a pipeline stage.
▪ Each stage must finish its execution within one clock
cycle.
▪Since execution of several instructions are
overlapped, we must ensure that there is no
conflict during the execution.
PIPELINE HAZARDS
 SPEEDUP
▪ If time to execute each stage = T
▪ Total time to execute nonpipelined 5 stages (IF + ID + EX + MEM + WB) = 5T
▪ So total time to execute n instructions = 5Tn

L L L L L L

IF
A A

ID EX MEM WB
A A A A
T T T T T T
C C C C C C
H H H H H H

 If time of each latch = d

 Time to execute n pipeline instructions = (4 + n).(T + d)
 If T >> d
 Ideal speedup = 5Tn/(4 + n)T = 5, for large n
 In practice, due to various conflicts, speedup is much less.

PIPELINE HAZARDS
 PIPELINE EXECUTION
Clock Cycles
instruction 1 2 3 4 5 6 7 8

i IF ID EX MEM WB
i+1 IF ID EX MEM WB
i+2 IF ID EX MEM WB
i+3 IF ID EX MEM WB

▪ Some examples of conflicts:

▪ IF &MEM: in clock cycle 4, both instructions i and i+3 access memory.
▪ Solution: use separate instruction and data cache.
▪ ID & WB: in clock cycle 5, both instructions i and i+3 access register
bank.
▪ Solution: Allow both read and write access to registers in the same clock cycle

PIPELINE HAZARDS
 ADVANTAGES OF PIPELINE
▪ In the non-pipelined version, the execution time of an
instruction is equaled to the combined delay of the 5
stages ( say, 5T).
▪ In the pipelined version, once the pipeline is full, one
instruction gets executed after every T time.
▪ Assuming all state delays are equal (T) (neglecting latch delay)
▪ However, due to various conflicts between instructions
(called hazards), we cannot achieve the ideal
performance.
▪ Several techniques have been propose to improve the
performance
PIPELINE HAZARDS
 SOME OBSERVATIONS
▪ To support overlapped execution, peak memory
bandwidth must be increased 5 times over that required
for the non-pipelined version.
▪ An instruction fetch must occur every clock cycle.
▪ Also there can be two memory accesses per clock cycle
(one for instruction and one for data).
a. Separate instruction and data caches are typically
used to support this.
I-Cache
CPU
D-Cache
PIPELINE HAZARDS
 SOME OBSERVATIONS
b. The register bank is accessed both in the stages ID and WB
▪ In the ID stage, we are prefetching both the register operands source 1 and
source 2, so ID requires two register reads, and WB requires 1 register write.
▪ We thus have the requirement of 2 reads and 1 write in every clock cycle.
▪ Two register reads can be supported by having two read ports.
▪ Simultaneous reads and write may result in clashes (e.g. same register used).
▪ Solution: perform the write operation during the first half of the clock cycle, and the reads
during the second half of the clock cycle

Clock Cycle Clock Cycle Clock Cycle

Read Write Read Write Read Write

PIPELINE HAZARDS
 EXAMPLE
Source Register 1
Read (5 bits)
Destination Register
Port1 Register Data (5 bits)
(32 bits)
REGISTER BANK Write
Register Data Port
Source Register 2 (32 bits)
(5 bits)
Read
Port2 Register Data
(32 bits)

PIPELINE HAZARDS
 SOME OBSERVATIONS
c. Since a new instruction is fetched every
clock cycle, it is required to increment the
PC on every clock.
▪PC updating has to be done during IF stage
itself, as otherwise the next instruction cannot be
fetched.
▪In the nonpipelined version discussed earlier,
this was done during the MEM stage.
PIPELINE HAZARDS
 BASIC PERFORMANCE ISSUES IN A PIPELINE
L L L L L L

IF
A A

ID EX MEM WB
A A A A
T T T T T T
C C C C C C
H H H H H H

▪ Register stages are inserted between pipelined stages, which

increases the execution time of an individual instruction.
▪ Because of overlapped execution of instructions, throughput increases.
▪ The clock period T has to be chosen suitably because it depends
on:
▪ Slowest stage in the pipeline.
▪ Register setup time: minimum time the register input must be held
stable before the active clock edge arrives
▪ Clock skew refers to the variation in arrival times of clock cycles at
different components.
▪ Clock jitter represents the fluctuations in the timing of clock edges.

PIPELINE HAZARDS
 EXAMPLE 1
▪ Consider the 5 stage MIPS32 pipeline, with the
following features:
▪ Pipeline clock rate of 1 GHz (i.e. 1 ns clock cycle time).
▪ For a non-pipelined implementation, ALU operations and
branches takes 4 cycles, while memory operation takes 5
cycles.
▪ Relative frequencies of ALU operations, branches and
memory operations are 50%, 15% and 35% respectively.
▪ In the pipelined implementation, due to clock skew and setup
time, the clock cycle time increases by 0.25 ns.
▪ Calculate the estimated speedup of the pipelined
implementation
PIPELINE HAZARDS
SOLUTION
a) For non-pipelined processor:
▪ Average instruction execution cycle = clock cycle
time x average CPI
▪ 1 ns x (0.50 x 4 + 0.15 x 4 + 0.35 x 5) = 4.35 ns
b) For pipelined processor:
▪ Clock cycle time = 1 + 0.25 = 1.25 ns
▪ In the steady state (there are large number of
instructions), one instruction will get executed
every clock.
▪ Speedup = 4.35 / 1.25 = 3.48
PIPELINE HAZARDS
 Pipeline Hazards

PIPELINE HAZARDS
 INTRODUCTION
▪ Pipeline Hazards:
▪ Ideally, an instruction pipeline should complete the
execution of an instruction in every clock cycle.
▪ Hazards refer to the situations that prevent a pipeline from
operating at its maximum possible clock speed.
▪ Prevents some instructions from executing during its
designated clock cycle.
▪ Three types of hazards:
▪ Structural Hazard: Arise due to resource conflicts.
▪ Data Hazard: Arise due to data dependencies between
instructions.
▪ Control Hazard: Arise due to branch and other instructions
that change the PC.
PIPELINE HAZARDS
 WHAT HAPPENS WHEN HAZARDS APPEAR?
▪ We can use special hardware and control circuits to avoid
the conflict that arise due to hazard.
▪ As an alternative, we can insert stall cycles in the
pipeline.
▪ When an instruction is stalled, all instructions that follow also get
stalled.
▪ Number of stall cycles depends on the criticality of the hazard.
▪ Instructions before the stall instruction can continue, but no new
instructions are fetched during the stall.
▪ In general, hazards result in performance degradation.

PIPELINE HAZARDS
 CALCULATION OF PIPELINE DEGRADATION

▪ We can treat pipelining as a way to reduce the CPI, or reduce

C.
▪ Let us consider that we are decreasing the CPI
▪ The ideal CPI (in the absence of any hazards) of an instruction
pipeline can written as:

PIPELINE HAZARDS
 CALCULATION OF PIPELINE DEGRADATION
▪ If we restrict ourselves to stall cycles only, we can write:
▪ CPIpipe = Ideal CPI + (Pipeline Stalls Cycles per instruction)
▪ We can thus write:

▪ If we ignore the increase in clock cycle time due to pipeline

(i.e. Cnonpipe = Cpipe )

PIPELINE HAZARDS
 (A) STRUCTURAL HAZARDS
▪ They arise due to resource conflicts when the hardware
cannot support overlapped execution under all possible
scenarios.
▪ Examples:
▪ Single memory (cache) to store instructions and data: while an
instruction is being fetched some other instruction is trying to read
or write data.
▪ An instruction is trying to read data from the register bank (in ID
stage), while some other instruction is trying to write into a register
(in WB stage).
▪ Some functional unit (like floating – point ADD or MULTIPLY) is not
fully pipelined.
▪ A sequence of instructions that try to use the same functional unit will result in
stalls.

PIPELINE HAZARDS
 ILLUSTRATION
▪ Structural Hazard in a single port memory system, which stores
both instructions and data.
Instruction 1 2 3 4 5 6 7 8
LW R1, 10(R2) IF ID EX MEM WB
ADD R3, R4, R5 IF ID EX MEM WB
SUB R10, R2, R9 IF ID EX MEM WB
AND R5, R7, R7 IF ID EX MEM WB
ADD R2, R1, R5 IF ID EX MEM

▪ Here both LW and AND instructions are trying to access the

memory at the cycle time 4.
▪ So we have to give a stall at cycle time 4 for the instruction AND.
PIPELINE HAZARDS
 ILLUSTRATION
Instruction 1 2 3 4 5 6 7 8
LW R1, 10(R2) IF ID EX MEM WB
ADD R3, R4, R5 IF ID EX MEM WB
SUB R10, R2, R9 IF ID EX MEM WB
AND R5, R7, R7 STALL IF ID EX MEM
ADD R2, R1, R5 STALL IF ID EX

▪ The control circuit will automatically detect that there

is a conflict at cycle time 4 and add a stall cycle there
for the instruction AND.
▪ The next instructions will automatically incur 1 stall
cycles
PIPELINE HAZARDS
 EXAMPLE1
▪ Consider an instruction pipeline with the following features:
▪ Data references (load and store) constitute 35% of the instructions (each of them had 1 stall
cycle).
▪ Ideal CPI ignoring structural hazard is 1.3.
▪ How much faster is the ideal machine without the memory structural hazard, versus the
machine with the hazard?

PIPELINE HAZARDS
 WHY STRUCTURAL HAZARDS APPEAR IN REAL MACHINES?
▪ Why can’t we remove structural hazards by
incorporating new hardware?
a) To reduce the cost of implementation.
b) Pipelining all the functional units may be too costly.
c) If structural hazards are not frequent, it may not be
worth the effort and cost to avoid it.
▪ Memory access structural hazard is quite frequent.
▪ Makes use of separate instruction and data caches in the first
level.
PIPELINE HAZARDS
 DATA HAZARDS
▪ Data Hazards occur due to data dependencies between
instructions that are in various stages of execution in the
pipeline.
Instruction 1 2 3 4 5 6
ADD R2, R5, R8 IF ID EX MEM WB
SUB R9, R2, R6 IF ID EX MEM WB

The value of R2 is written in the WB stage of the ADD instruction

and the new value of R2 is required in the ID stage of the SUB
instruction. Unless proper precaution is taken, the SUB
instruction can fetch the wrong value of R2.
PIPELINE HAZARDS 24-Apr-24 25
 DATA HAZARDS
▪ Simple solution by inserting stall cycles:
▪ After the SUB instruction is decoded and the control unit determines that
there is a data dependency, it can insert stall cycles and re-execute the ID
stage again later.
▪ 3 cycles are wasted.

Instruction 1 2 3 4 5 6 7 8
ADD R2, R5, R8 IF ID EX MEM WB
SUB R9, R2, R6 IF ID STALL STALL ID EX MEM

Instr (i + 2) IF STALL STALL IF ID EX

Instr (i + 3) STALL STALL IF ID
Instr (i + 4) STALL STALL IF

PIPELINE HAZARDS 24-Apr-24 26

HOW TO REDUCE THE NUMBER OF STALL CYCLES?
a. Concurrent register access: By splitting the clock
cycle into two halves, the register read and write
can be carried out in the two halves of a clock
cycle (register write in first half, and register
read in second half).
b. Data forwarding/ bypassing: By using extra
hardware consisting of multiplexers, the data
required can be forwarded as soon as they are
computed, instead of waiting for the result to be
written into the register.
PIPELINE HAZARDS 24-Apr-24 27
 ILLUSTRATION
Instruction 1 2 3 4 5 6 7 8 9
ADD R4, R5, R6 IF ID EX MEM WB
SUB R3, R4, R8 IF ID EX MEM WB
ADD R4, R2, R4 IF ID EX MEM WB
AND R9, R4, R10 IF ID EX MEM WB
OR R11, R4, R5 IF ID EX MEM WB

▪ The first instruction computes R4, which is required by all the subsequent 4 instructions.
▪ The result of the 1st instruction at stage 5 (WB) is used by the ID stage of all the
subsequent 3 instructions.
▪ The last instruction (OR) is not affected by the data dependency
▪ The last AND instruction is solved by splitting the resistor access, writing is done in the
first half of the clock cycle and reading is done in the second half of the clock cycle.

PIPELINE HAZARDS 24-Apr-24 28

 REDUCING DATA HAZARD BY SPLITTING REGISTER READ/WRITE
▪ The data forwarding concept as discussed can solve the data
hazards between ALU instructions.
▪ It is desirable to reduce the number of instructions to be
forwarded, since each level requires special hardware
▪ In the forwarding scheme as discussed, we need to forward 3
instructions.
▪ We can reduce this number 2 by avoid the conflict between the first
and the fourth (AND) instruction, where WB and ID are accessed in
the same cycle.
▪ We perform register write (in WB) during the first half of the clock
cycle, and the register reads (in ID) during the second half of the
cycle.
▪ The data hazard between the first and fourth instructions get eliminated

PIPELINE HAZARDS 24-Apr-24 29

 SPLITTING REGISTER
Clock Cycle Clock Cycle Clock Cycle

No data
hazards here
Read Write Read Write Read Write

Instruction 1 2 3 4 5 6 7 8 9
ADD R4, R5, R6 IF ID EX MEM WB
SUB R3, R4, R8 IF ID EX MEM WB
ADD R4, R2, R4 IF ID EX MEM WB
AND R9, R4, R10 IF ID EX MEM WB
OR R11, R4, R5 IF ID EX MEM WB

PIPELINE HAZARDS 24-Apr-24 30

 REDUCING DATA HAZARDS USING DATA FORWARDING /BYPASSING
▪ Basic idea
▪ The result computed by the previous instruction(s) is stored
in some register within the data path (e.g. ALUout)
▪ Take the value directly from the register and forward it to the
instruction requiring the result.
▪ Additional data transfer paths are to be added in the
data path.
▪ Requires multiplexers to select these additional paths.
▪ The control unit identifies data dependencies and selects the
multiplexers in a suitable way.

PIPELINE HAZARDS 24-Apr-24 31

 DATA FORWARDING
Instruction 1 2 3 4 5 6 7 8 9
ADD R4, R5, R6 IF ID EX MEM WB
SUB R3, R4, R8 IF ID EX MEM WB
ADD R4, R2, R4 IF ID EX MEM WB
AND R9, R4, R10 IF ID EX MEM WB
OR R11, R4, R5 IF ID EX MEM WB

▪ The first instruction (ADD) finishes the computation at the end of

stage EX but is supposed to write into R4 only in WB.
▪ We need to forward the result directly from the output of the
ALU (in EX stage) to the appropriate ALU input registers of the
following instructions.
▪ To be used in the respective stages.

PIPELINE HAZARDS 24-Apr-24 32

 DATA HAZARD WHILE ACCESSING MEMORY
▪In MIPS32 pipeline, memory references are always
are kept in order, and so data hazards between
memory references never occur.
▪ Cache misses can result in pipeline stalls.

Accessed in order No Hazard

PIPELINE HAZARDS 24-Apr-24 33

A LOAD INSTRUCTION FOLLOWED BY THE USE OF LOADED DATA
▪ Example of a data hazard that requires unavoidable pipeline
stalls.

ALU wants to use the loaded data;

Loaded data
Forwarding cannot be solved Forwarding can solve
available here
PIPELINE HAZARDS 24-Apr-24 34
 SOLUTION
▪ As we have seen the hazard cannot be eliminated by forwarding
alone.
▪ Common solution is to add a special hardware that will be added to
the data path in the ID stage which is called pipelined interlock.
▪ The hardware detects the hazard and stalls the pipeline until the hazard is
cleared.
▪ The pipeline with stall is shown.

PIPELINE HAZARDS 24-Apr-24 35

 INSTRUCTION ISSUE
▪This is the process of allowing an instruction to
move from the ID stage to the EX stage.
▪In the pipeline, all possible data hazards can be
checked in the ID stage itself.
▪If a data hazard (LOAD followed by use) exists,
the instructions is stalled before it is issued.

PIPELINE HAZARDS 24-Apr-24 36

 EXAMPLE
▪ A = B+C
▪ Pipeline execution is given in the following
Instruction 1 2 3 4 5 6 7 8 9
LW R1, B IF ID EX MEM WB
LW R2, C IF ID EX MEM WB
ADD R5, R1, R2 IF ID STALL EX MEM WB
SW R5, A IF STALL ID EX MEM WB

▪ Instruction scheduling or pipeline scheduling

▪ Complier tries to avoid generating code with a LOAD followed by
immediate use.

PIPELINE HAZARDS 24-Apr-24 37

INSTRUCTION SCHEDULING

Both
interlocked
Two Load are
Interlocks eliminated

PIPELINE HAZARDS 24-Apr-24 38

 SOME OBSERVATIONS
▪ Pipeline scheduling can increase the number of
registers required, but result in performance
improvement in general.
▪ A LOAD instruction requires that the following
instruction do not use the loaded value is called the
delayed load.
▪ A pipeline slot after a LOAD is called delay load slot.
▪ If the complier cannot move some instruction to fill
up the delay slot (scheduling), it can insert a NOP
(No Operation) instruction.
PIPELINE HAZARDS 24-Apr-24 39
 TYPES OF DATA HAZARDS

PIPELINE HAZARDS 24-Apr-24 40

 READ AFTER WRITE (RAW)
Execution Order is: ▪ InstrJ tries to read operand before InstrI writes it
InstrI
InstrJ I: add r1,r2,r3
J: sub r4,r1,r3

▪ Caused by a “Dependence” (in compiler

nomenclature).
▪ For MIPS32 integer pipeline, only RAW hazard is
possible and only one type (LOAD followed by
immediate use) can result in performance loss.
▪ Complier tries to eliminate the performance loss by
instruction scheduling.
PIPELINE HAZARDS 24-Apr-24 41
 WRITE AFTER READ (WAR)
▪ InstrJ tries to write operand before InstrI reads i
Execution Order is:
InstrI ▪ Gets wrong operand
InstrJ I: sub r4,r1,r3
J: add r1,r2,r3
K: mul r6,r1,r7
▪ Called an “anti-dependence” by compiler writers.
This results from reuse of the name “r1”.
▪ Can’t happen in MIPS 5 stage pipeline because:
▪ All instructions take 5 stages, and
▪ Reads are always in stage 2, and
▪ Writes are always in stage 5

PIPELINE HAZARDS 24-Apr-24 42

WRITE AFTER WRITE (WAW)
▪ InstrJ tries to write operand before InstrI writes it
Execution Order is:
▪ Leaves wrong result ( InstrI not InstrJ )
InstrI
InstrJ I: sub r1,r4,r3
J: add r1,r2,r3
K: mul r6,r1,r7
▪ Called an “output dependence” by compiler
writers
▪ This also results from the reuse of name “r1”.
▪ Can’t happen in MIPS 5 stage pipeline because:
▪ All instructions take 5 stages, and
▪ Writes are always in stage 5

PIPELINE HAZARDS 24-Apr-24 43

 CONTROL HAZARDS

PIPELINE HAZARDS 24-Apr-24 44

 CONTROL HAZARDS
▪ Control Hazards arise because of branch instructions being
executed in a pipeline.
▪ Can cause greater performance loss than data hazards
▪ What happens when a branch is executed?
▪ The value of PC may or may not change to something
other than PC + 4.
BEQ R1, L
▪ If the branch is taken, the PC is normally not updated
→ (Not Taken) until the end of MEM (The targeted branch address can
only be known after the MEM) cycle. i.e. branch
outcome only known in the MEM.
▪ The next instruction can be fetched only after that (3
→ L: (Taken) stall cycles).
▪ Actually by the time we know that the instruction is
branch, the next instruction already been fetched.
▪ We have to redo the fetch if it is branch.
PIPELINE HAZARDS 24-Apr-24 45
EXAMPLE

PIPELINE HAZARDS 24-Apr-24 46

 HOW TO REDUCE BRANCH STALL PENALTY
▪ The penalty can be reduced if both the following are achieved
a. Determine whether the branch is taken earlier in the pipeline.
b. Compute the branch target address earlier in the pipeline

▪ How to achieve a.?

▪ In MIPS32, the branches require testing a register for zero, or comparing the values of 2
registers
▪ Possible to complete this decision by the end of the ID cycle where the registers are
pre-fetches, by adding special comparison logic.
▪ How to achieve b.?
▪ Both the possible PC values can be pre-computed in the IF stage by using separate
adder
▪ By the end of the ID cycle, we know whether the branch is taken and also
know the branch target address
▪ Requires a single stall cycle during branches

PIPELINE HAZARDS 24-Apr-24 47

EXAMPLE

PIPELINE HAZARDS 24-Apr-24 48

 REDUCING THE PIPELINE BRANCH PENALTIES
▪ Four techniques based on compile-time guesses
a. The simplest scheme is to freeze the pipeline and
insert one stall cycle.
▪ Main advantage is simplicity.
b. We predict that the branch is not taken, and allow
the hardware to continue as if the branch was not
executed.
▪ Must not change the machine state until the branch outcome
is finally known.
▪ If the prediction is wrong (i.e. branch is taken), we stop the
pipeline and restart the fetch
PIPELINE HAZARDS 24-Apr-24 49
 EXAMPLE
Branch is
not taken
(No
penalty)

Branch is
taken (1
cycle
penalty)

PIPELINE HAZARDS 24-Apr-24 50

 REDUCING THE PIPELINE BRANCH PENALTIES
c. We predict that the branch is taken
▪ As soon as the branch outcome is decoded and the target address computed, fetching of instructions
can commence from the computed target.
▪ Since in MIPS32 pipeline, we can know about the branch outcome and the target address together
(at the end of ID), there is no advantage in this approach.
▪ May be used for complex instruction machines where the branch outcome is known later than the
branch target address.

Branch is
taken (1
cycle
penalty)

PIPELINE HAZARDS 24-Apr-24 51

 REDUCING THE PIPELINE BRANCH PENALTIES
d. We can use a technique called delayed branch, which makes
the hardware simple but puts more responsibility on the
complier.
▪ If a branch instruction incurs a panelty of n stall cycles, the execution
cycle of a branch instruction is defined as follows:

Branch Delay
Slots For MIPS32, n=1

▪ Just like in load delay slots, the task of the compiler is to try and fill-up the
branch delay slots with meaningful instructions.
▪ Instructions in the branch-delay slot are always executed irrespective of
the outcome of the branch.
PIPELINE HAZARDS 24-Apr-24 52
EXAMPLES

PIPELINE HAZARDS 24-Apr-24 53

 INTERRUPT HANDLING
(EXCEPTION HANDLING)

PIPELINE HAZARDS 24-Apr-24 54

 DEALING WITH INTERRUPTS
▪ Interrupt is the method of creating a temporary halt during program execution
and it complicate the design of an instruction pipeline.
▪ Overlapping of instruction executions make it more difficult to decide whether an
instruction can safely change the state of the machine.
▪ Suppose an instruction changes the value of a register later on it is found that it
is an interrupt. The instruction has to be withdrawn. Already it has change the
value of the register.
▪ Some interrupts can force the machine to abort the instruction before it is
completed (e.g. page fault).
▪ Whenever you try to fetch an instruction it is found that the instruction is not in
the memory and you have to fetch it from disk. Under those cases the instruction
has to be again restarted.
▪ The most difficult interrupts to handle in a pipeline have the properties.
a. They occur within instruction.
b. They have to be restarted.

PIPELINE HAZARDS 24-Apr-24 55

 DEALING WITH INTERRUPTS
▪ An interrupt can occur at any stage
a. When an interrupt occurs, the pipeline state can be saved
safely as follows:
b. A TRAP instruction is forced into the pipeline at the next IF
cycle.
c. When the TRAP is taken, the control unit will know a TRAP is
inserted and it will disable all writes for the faulting
instruction and all others that follow. It will continue until the
TRAP reaches the WB stage
▪ Prevent any state change
d. After the interrupt handler takes control, it saves the PC of the
faulting instruction.
PIPELINE HAZARDS 24-Apr-24 56
 INTERRUPT IN BRANCH DELAY SLAT
▪ For delayed branches, suppose that an instruction in the
branch-delay slot causes an interrupt
▪ If the branch is taken, then the instructions to start are those in the slot
plus the instruction at the branch target.
▪ A number of PC values need to be saved and restored.

▪ After handling the interrupt, special instruction (RFE [return

from Exception]in MIPS32) return the machine from the
interrupt handler by reloading the PC’s and restarting the
interrupt instructions.
▪ Precise interrupt: if the pipeline can be stopped such that the
instructions before the faulting instruction are completed,
while those after can be restarted from the scratch.
PIPELINE HAZARDS 24-Apr-24 57
SOME EXCEPTIONS THAT MAY OCCUR IN MIPS32 PIPELINE

PIPELINE HAZARDS 24-Apr-24 58

 MULTIPLE INTERRUPTS
▪ Multiple interrupts may also occur in the same clock
cycle

▪ Can cause a data page fault (in MEM) and arithmetic

exception (in EX) at the same time (clock cycle 4).
▪ Solution: we can deal only with the page data fault
and restart the execution. The second interrupt will
occur again and will be handled later.
PIPELINE HAZARDS 24-Apr-24 59
 OUT OF ORDER INTERRUPT

▪ LW causes a page data fault (cycle 4), and ADD causes an instruction page
fault (cycle 2).
L L L L L L

IF ID EX WB
A A A A A A
T
C
T
C
T
C
T
C
MEM T
C
T
C
H H H H H H

Status Register
▪ Solution: the hardware posts each interrupt in a status vector, which is
carried with each instruction as it moves through the pipeline.
▪ When an instruction reaches WB, the interrupt status vector is checked and
handled if present.
▪ Guarantees that all interrupt handling is carried out in precise order.
PIPELINE HAZARDS 24-Apr-24 60
 THANK YOU

PIPELINE HAZARDS