IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 67, NO.

12, DECEMBER 2020 4161

Incremental Delta-Sigma ADCs: A Tutorial Review

Zhichao Tan , Senior Member, IEEE, Chia-Hung Chen , Member, IEEE,
Youngcheol Chae , Senior Member, IEEE, and Gabor C. Temes , Life Fellow, IEEE

Abstract— In many sensor applications, a high-resolution in incremental mode for sensor interfaces, and the incremental
analog-to-digital converter (ADC) is a key block. The use of  ADCs (IADCs) offer the best choice for achieving high
an incremental delta-sigma ADC (IADC) is often well suited energy efficiency [1]–[6]. Since the modulators of the IADCs
for such applications. While the energy-efficiency of IADCs has
improved by several orders of magnitude over the past decade, usually have finite impulse response (FIR), the corresponding
the implementation of high performance IADCs, especially in decimation filter can be as simple as a cascade of integrators
battery-powered systems, is still challenging. This paper presents (CoIs), much simpler than their  counterparts that use an
a tutorial review on energy-efficient IADCs and addresses the infinite impulse response (IIR) decimation filters. The other
progress in this area. This paper describes the fundamentals of advantages of the IADCs include easy multiplexing and low
IADCs and energy-efficient hybrid IADC architectures. Various
design techniques for improving the energy-efficiency of the latency [7]–[11] and are also less subject to idle tones [10].
IADCs are described. This paper is intended to serve as a starting A first-order IADC requires a long conversion time, result-
point for the development of a new energy-efficient IADC. ing in poor energy efficiency. To shorten the conversion time
Index Terms— Analog-to-digital converter (ADC), incremental and thereby improve energy efficiency, higher-order IADCs
ADC (IADC), incremental delta-sigma () modulator, decima- can be used. However, they are more prone to instability and
tion filter, energy-efficiency, energy-efficient amplifier, chopping, have a reduced input range. Hence, multi-stage noise-shaping
FIR-DAC, integrator slicing, negative-R assisted integrator, and (MASH) IADCs [12], [13], and hybrid IADCs incorporating
sensor interface. with Nyquist-rate ADCs have been investigated. This paper
reviews energy-efficient IADC architectures, such as extended
I. I NTRODUCTION counting [6], [9], two-step [24], [25], multi-step [26], [27] and
zoom [33] structures.
S ENSORS are ubiquitous devices, including audio, tem-
perature, light, magnetic, capacitive sensing, as well
as bio-potential acquisition and biometrics identification for
The circuit techniques for implementing energy-efficient
IADCs are also reviewed. Several important energy-efficient
wearable devices. It usually processes narrow-band signals amplifier topologies have been proposed in the past decade,
with frequencies from DC to tens of kHz [1]–[4]. For including inverter-based amplifiers and its improved versions
battery-powered sensor systems, energy-efficient analog-to- with optimal gm /Id are also described in this paper [33]–[37],
digital converter (ADCs) are especially important and are [41]–[52]. Another important amplifier topology, the ring
usually customized to meet the sensor’s requirements. Such amplifier which benefits from high gain and fast settling
ADCs must also be robust against offset and flicker noise. is also reviewed [53]–[60]. In recent years, dynamic ampli-
In addition, the integrated ADC often needs to be multi- fiers have drawn attention, because they exhibit the lowest
plexed across many channels and applications requiring a large bandwidth for a target speed due to their class-B opera-
number of channels, such as image sensors or bio-potential tion [61]–[63]. The principles of several dynamic amplifiers
acquisition [3]–[6], [7]–[11], [18], [32], [41], [71], [82]. These are described in this paper [64]–[69]. Other useful tech-
must be very efficient in terms of energy and area. niques for implementing energy-efficient IADCs such as chop-
Among all categories of ADCs, delta-sigma () ADCs ping [70]–[73], FIR DAC [74]–[85], integrator slicing [85],
utilizing oversampling and noise-shaping are widely used for and 1st integrator optimization [81], [82], [88]–[91] are also
achieving high resolution. The  ADCs are often operated discussed.
The paper is organized as follows. Section II deals with
Manuscript received May 31, 2020; revised September 29, 2020; accepted the fundamental operation and design of a single-loop IADC
October 21, 2020. Date of current version December 1, 2020. This work was and describes the advantages over its  counterparts.
supported by the Ministry of Science and Technology (MOST), Taiwan. (Con-
tract ID: MOST 108-2218-E-009-034-MY3). This article was recommended Energy-efficient hybrid IADC architectures are discussed in
by Associate Editor J. Yin. (Corresponding author: Chia-Hung Chen.) Section III. Energy-efficient amplifier topologies for IADCs
Zhichao Tan is with the Department of Electrical Engineering, Zhejiang are described in Section IV. Section V describes circuit tech-
University, Hangzhou 310058, China.
Chia-Hung Chen is with the Department of Electrical and Computer niques that are useful in the IADC design. Section VI gives
Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: the summary and conclusions of the paper.
[email protected]).
Youngcheol Chae is with the Department of Electrical and Electronic
Engineering, Yonsei University, Seoul 03722, South Korea. II. F UNDAMENTALS OF IADC S
Gabor C. Temes is with the School of Electrical Engineering and Computer
Science, Oregon State University, Corvallis, OR 97331 USA. A. Delta-Sigma ADCs
Color versions of one or more of the figures in this article are available
online at https://ieeexplore.ieee.org. A general  ADC, shown in Fig. 1(a), consists of
Digital Object Identifier 10.1109/TCSI.2020.3033458 an oversampled loop filter, a low-resolution quantizer and
1549-8328 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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4162 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 67, NO. 12, DECEMBER 2020

Fig. 2. (a) A 2nd -order IADC, (b) its decimation filter and (c) timing diagram.
Fig. 1. (a) Block diagram of a  ADC. (b) A decimation filter example
(c) The Hogenauer third-order sinc filter [16].

a multi-rate decimation filter. L cascaded integrators form CoI decimation filter accumulates the oversampled bitstream.
an L th -order loop filter. The quantization noise spectrum is The feedforward with an input direct path is used as an
high-pass filtered by the noise transfer function (NTF), which example to illustrate the operation of IADC [7], [17], and
is usually of the form other architectures can be derived similarly. Fig. 2 depicts the
z-domain model of a 2nd -order incremental ADC (IADC) and
V 1
N T F(z) = = its simplified timing diagram, including the two-phase non-
E 1 + L 1 (z) overlapping clock and reset pulses. Here, M is the oversam-
(z − 1) L pling ratio (OSR), defined as the number of oversampling
= (1)
a L z L + a L−1 z L−1 + · · · a0 within one conversion time.
The design methodology of loop filter for the required signal- The operation of an IADC is best understood using
to-quantization-noise (SQNR) is well known. It can be found time-domain analysis [4], [7], [11], [13]. It begins with a
in [14], including a discussion of loop filter architecture, loop global reset pulse to clear the memories in all analog and
filter order, oversampling ratio (OSR), in-band zero position, digital blocks. After the initial reset, the  modulator loop
and quantizer levels. Schreier’s toolbox [15] is a powerful quantizes the analog input voltage U , and the digital filter
help for finding the coefficients, optimizing the out-of-band concurrently processes the output bitstream V . At the end of
gain (OBG), dynamic range scaling, and other practical design the conversion for i = M in Fig. 2, the output of the first
issues. integrator W1 and the second one W2 can be expressed as [7]
The decimation filter for  ADCs, shown in Fig. 1(b),
usually has several stages, and consists of a sincL+1 filter 
M−1

and an FIR half-band filters (HBF). The decimation filter W1 = (U [i ] − V [i ]) (2)

samples the digitized bitstream at an oversampled-rate ( f s ) i=1
 K
M−1 −1
and then converts it to samples at the Nyquist-rate ( f s /OSR).
A Hogenauer sinc3 decimation filter [16] for a second-order W2 = (U [i ] − V [i ]) (3)
modulator is shown in Fig. 1(c). It introduces a delay (latency) K =1 i=1

from bitstream input V to the final digital output D. If the

oversampled bitstream is decimated down to Nyquist-rate by The variables of the closed loop satisfy the equation
a sinc3 filter and no additional filtering is used, the latency

M−1  K
M−1 −1
becomes 3TN , where TN is a required time for single Nyquist
U [M] + 2 U [i ] + U [i ] + E[M]
conversion period. In general, for a L t h -order  modulator,
i=1 K =1 i=1
the latency is (L + 1) TN .

M−1  K
M−1 −1
= V [M] + 2 V [i ] + V [i ] (4)
B. Operation of IADCs i=1 K =1 i=1
Using the same circuitry of a  modulator and adding a
global reset, the  modulator can process and accumulate Here, the least-significant-bit (LSB) quantization error E of
a finite length of analog samples. In the meantime, the the internal L-level quantizer is VF S /(L − 1), where VF S is

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TAN et al.: IADCs: TUTORIAL REVIEW 4163

the full-scale voltage. From (4),


M 
K 
M 
K
U [i ] + E[M] = V [i ] (5)
K =1 i=1 K =1 i=1
After M clock periods, the next reset pulse reads out the output
word of the CoI filter and clears all memories. The IADC
converts analog data sample-by-sample, and hence functions
as a Nyquist-rate ADC. We can define the average input
voltage Ũ by the relation in Eq. (6). Note that Ũ represents the
input accurately only if U does not vary significantly during
the conversion.
1 M  K
Ũ = U [i ] (6)
M(M+1)
K =1 i=1
Fig. 3. SQNR versus OSR for one-bit modulators with first-order
2 VFS 2 M  K
(N = 1) to fifth-order (N = 5) loops. Assumes 1-bit quantizer and no overload
Ũ + · = V[i ] (7) at full-scale voltage input.
M(M+1) L-1 M(M+1)
K =1 i=1

To reconstruct Ũ from the output bitstream V , the digital

decimation filter obviously needs to perform the operation C. Advantages of IADC Versus  ADC
on the right-hand-side of Eq. (7). For the 2nd -order IADC, The IADC offers true Nyquist-rate conversion, and is
the decimation filter can thus be simply realized by two inte- often more suitable for use in sensor interfaces requiring
grators in cascade (Fig. 2b). Note that no additional sample- high-resolution ADCs. The essential advantages [13] against
and-hold circuit in front of the ADC is needed to acquire the a  ADC are as follows:
DC signal. As Eq. (7) shows, the loop filter samples the input • The decimation filter is much simpler. This can be seen
signal M times in a single conversion, and performs finite- comparing Figs. 1b and 1c with Fig. 2b. It may be as
impulse-response (FIR) filtering [11], [13] on the input signal. simple as a cascade of a few accumulators, or a single
The equivalent LSB quantization error E I ADC2 is given by multiplier-accumulator stage 18]. Thus, the energy and
2 VF S area overhead of the decimation filter is reduced.
E I ADC2 = (8) • The latency is shorter. The latency from the analog input
M(M + 1) L − 1
to the digital output is only a single Nyquist conversion
The analysis can be extended to an N t h -order IADC [7]. The
period TN . For an L t h -order  ADC, it is (L + 1) TN .
N t h -order NTF is designed as (1-z−1 )N , and the decimation
The  ADC’s longer latency may cause problems when
filter is implemented as number of N cascaded counters.
the ADC is integrated into a feedback system.
The equivalent quantization error E I ADC N and the maximum
• An IADC is easier to be multiplexed. An IADC can be
SQNR of an N t h -order IADC are
shared by multiple channels, thus reducing the required
N! VF S area, and the sensor system can be implemented cost-
E I ADC N ≈ N (9)
M L−1 effectively.
S Q N R N ≈ N · 20 log(M) + 20 log(L − 1) − 20 log(N!) • Reduced idle tone power. The FIR operation makes the
(10) idle tone generation much less likely than in a conven-
The N t h -order loop filter scales down the internal quantization tional IIR  ADC [10].
error by a factor N!/M N . As same as the conventional modu- In addition, the global reset makes it easy to reconfigure an
lators, increase the internal quantizer by 1-bit will improve IADC and combine it with a Nyquist-rate ADC to implement
the SQNR by 6 dB. And, a higher-order modulator will a hybrid ADC. These hybrid schemes combine the advantages
require a higher-level internal quantizer to extend the non- of ADC with oversampling and Nyquist-rate. The operation
overloaded range. To highlight the SQNR versus OSR and of several hybrid ADCs will be discussed in Section III.
order, the quantizer is assumed as 2-level and no overloaded
D. Disadvantages of IADCs Versus  ADCs
at full-scale voltage input. Fig. 3 shows the SQNR vs. OSR
curves for single-bit (L = 2) modulators with orders N = The signal-to-noise ratio (SNR) of a  ADC is usually
1 ∼ 5. As described in Sec. II-A, a 2nd -order  ADC determined by the sampled kT/C noise, and this is also true for
uses Sinc3 and half-band filter (Fig. 1b 1c) to filter out more IADCs. In a first-order  ADC or IADC circuit, the input-
quantization noise at high frequency. An IADC2 simply uses referred noise power is v¯n2 /M. However, when a higher-order
two cascaded counters (Fig. 2b) and more high-frequency  ADC is operated as an IADC, every conversion has a
quantization are aliased back to in-band. IADCs’ SQNR are weighting associated with each input sample, and the total
therefore inferior to their  counterparts. Even though the input-referred noise power is
DT operation is derived here, the IADC can be implemented 
M 
M
by using a continuous-time (CT) loop filter. A further analysis v n2 = ωi2 v s2 = v s2 ωi2 (11)
of CT IADC’s STF and NTF are described in [28]. i=1 i=1

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4164 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 67, NO. 12, DECEMBER 2020

Fig. 4. (a) An IADC using a second Nyquist-rate ADC for extended Fig. 5. (a) An IADC with extended counting using hardware sharing [9].
counting [6]. (b) The simplified timing diagram for one conversion period. (b) A discrete-time IADC1 acting as the coarse quantization ADC. (c) Recon-
figured stage acting as a 10-bit cyclic ADC to perform the fine quantization.

Here, v¯s2 is the input noise power of each sample, and ωi

The system is like a 2-0 MASH  ADC, but the fine ADC
is the weight of the decimation filter associated with each
does not operate at the oversampling frequency but at the
sample.
 2 Using the CoI filters as a decimation filter, the factor
Nyquist frequency. The quantization error E 1 is cancelled by
ωi reaches a maximum value of 1.33/M for 2nd -order
the fine stage and only the quantization error E 2 appears in
IADC and 1.8/M for 3rd -order IADC. For a 4th -order IADC,
the loop. The IADC with extended counting can achieve a
the thermal noise penalty can be increased by a factor of 2.
SQNR equivalent of a single-loop IADC with a B-bit internal
A more detailed analysis can be found in [7], [11], [13], [29],
quantizer. However, the last integrator needs to drive the large
[41]. Since a higher-order IADC has increased thermal noise,
input capacitor of the fine SAR ADC, and therefore consumes
the size of the input capacitor should be increased to maintain
additional power. A continuous-time IADC is certainly possi-
the same SNR. The amplifier then dissipates more power
ble to implement the extended counting and this is proposed
to drive the increased capacitive loads. Hence, higher-order
in [30].
IADCs consume more power than the equivalent  ADCs.
This noise penalty is part of the trade-off in using the IADC!
B. Hardware-Sharing IADCs With Extended Counting
III. H YBRID IADC A RCHITECTURES As shown in Fig. 3, each doubling of the OSR improves
the SQNR of the 1st and 2nd -order IADC by 6 and 12 dB,
A. IADCs With Extended Counting respectively. The OSR increase of the IADC does not signif-
In Fig. 2, the feed-forward loop filter only processes the icantly improve the SQNR. High-resolution ADCs typically
shaped quantization noise [17]. At the end of the  conver- require relatively long conversion time. Hence, instead of
sion, the residue voltage is stored in the last integrator, and cascading two loops of the ADC as in Fig. 4, the conver-
can be used for further fine quantization. Hence, a Nyquist sion can be performed in two steps, as shown next. This
ADC such as a SAR or cyclic ADC can sample the residue allows for sharing of hardware and also improves the energy
voltage just before the reset pulse, and continue with the efficiency [8], [21], [22].
fine conversion [6], [21] – [23]. An example of such an Fig. 5 shows an example of a hardware sharing IADC
extended-counting IADC is shown in Fig. 4(a) [6], and the with extended counting [8]. The 1st -order IADC performs
simplified timing diagram for one conversion in Fig. 4(b). the coarse conversion (Fig.5b), and the integrator stores the
Before the reset clears the signal held in the last integrator, residue voltage at the end. In the second step, the hardware is
the SAR ADC with B-bit resolution samples the residue reconfigured as a cyclic ADC to perform the fine conversion,
voltage, and then carries out its conversion. The result is as shown in Fig. 5(c). Therefore, to improve the SQNR
 K
M−1 −1 by 60 dB, only ten additional cycles are required. This
(U [i ] − V [i ]) + E2 = D2 (12) hardware-sharing has been used with column-parallel ADCs
K =1 i=1 for CMOS image sensors [8], [9], because the area is severely
With proper design of the digital summation logic and deci- limited by the pixel pitch. Although using a cyclic ADC alone
mation filter, the two cascaded loops can achieve a very high needs very large area to meet the kT/C noise requirement, this
resolution with good energy efficiency. The final result is hybrid scheme using the IADC reduces the capacitor size and
reuses the same hardware as the cyclic ADC. In combination
2 VF S with its benefits, this results in excellent energy efficiency.
Ũ + · B
(M − 1)(M − 2) 2 − 1 Since the gain mismatch between steps degrades the linear-
2 M K ity and SQNR, it should be reduced sufficiently for high
= V [i ] (13)
(M − 1)(M − 2) K =1 i=1 resolution IADCs.

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TAN et al.: IADCs: TUTORIAL REVIEW 4165

Fig. 6. A 2nd -order IADC in two-step operation. (a) First step (b) Second
step.

C. Two-Step IADCs and Multi-Step IADCs

A two-step IADCs were proposed to improve energy effi-
ciency and minimize hardware complexity [4], [13], [26], [27].
Fig. 6 describes an example of the two-step IADC [4].
During the first conversion, lasting for M1 cycles, the struc-
ture operates as a conventional 2nd -order IADC as shown
in Fig. 6(a). The feed-forward  architecture generates the
residue voltage at the end of first conversion step. For the
second conversion, the analog loop filter and the digital filter Fig. 7. The 1st -order IADC with multi-step extended counting by
are reconfigured, as shown in Fig. 6(b). The second integrator slope ADCs. (a) First step: IADC (b) Second step: extended counting
now acts as a holding amplifier that feeds the residue voltage by reconfiguring as a single-slope ADC. (c) Third-step: extended counting
by using a reduced coefficient single-slope ADC. (d) The simplified timing
V R E S into the L-level quantizer and the first integrator. The sequences.
first integrator is reset again and then samples the residue
voltage V R E S from the second integrator. This configuration
serves as a 1st order IADC for the remaining M2 clock cycles. and subtracts from it the output of the feedback DAC. The
After the two-step operation, the quantization error E 1 of the DAC capacitor is also rescaled by 1/(M 2 − 1). Meanwhile,
first step is cancelled, and only the final error E 2 remains. The the accumulators collect the digital bitstreams V1 and V2 with
decimation filter for the first step can be realized by the CoI2 proper gains, and the outputs are decimated before the reset.
and one of the digital integrators is also reused for the second The additional cycles raise the SQNR by about
step. Thus, both the analog and digital hardware of 2nd -order 20log(M2 ) dB. The residue voltage V R E S2 can be further
IADC is reused in the two steps. As a result, the circuit can quantized by reusing the slope ADC for another M3 clock
achieve high SQNR with a simple reconfiguration [4]. Reusing cycles. The coefficient of the slope ADC must be changed
the 2nd -order hardware in a two-step operation, it achieves to 1/(M 2 − 1)/(M 3 − 1). This can be achieved by scaling
the SQNR of 110 dB, which is 27 dB higher than that of the down the reference voltage by 1/(M 3 − 1). One way to scale
2nd order IADC and has almost the same SQNR as the the reference is to use a capacitive T-network, as shown
3rd order one. The two-step IADC offers good energy effi- in Fig. 7(c). A digital counter can also be reused to accumulate
ciency (Schreier’s FoM = 174 dB) [4]. Another two-step the bitstreams from each step, and the decimated samples of
conversion is reported in [31] and it achieves the Schreier each step are added with an appropriate scaling to give the
FoM 176 dB. This uses an IADC1 of 246 cycles as the first- final output. The SQNR is given by
step to avoid the thermal noise penalty, and another 10 cycles
S Q N R ≈ 20 log(M1 · M2 · M3 ) (14)
exponential accumulation as extended counting.
To avoid any complicated reconfigurations and retain the in dB Extensive hardware recycling can be used in multi-step
benefits of hardware recycling, a multi-step IADC was pro- IADC, and the reconfiguration only requires additional control
posed [26], [27], which utilizes a one-bit 1st order IADC as switches for multi-step operation. With a proper selection of
a single slope ADC. The conversion is performed in several OSRs (320 = 256+32+32), the multi-step IADC in [27]
steps. It starts by operating a single-bit 1st order IADC for achieved a dynamic range of 99dB and a high Schreier’s FoM
M1 cycles, as shown in Fig. 7(a). After the IADC completed of 175dB.
the conversion of the input voltage U , it is reconfigured as A two-step CT IADC implementation is reported in [32].
a single-slope ADC with a gain 1/(M 2 − 1) to quantize the It uses a CT IADC2 as the first stage, and an additional inter-
residue voltage V R E S1 for another M2 , as shown in Fig. 7(b). stage amplifier to sample and hold the residue voltage into
The integrator holds the residue cycles voltage of the first step the second stage CT IADC2.

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4166 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 67, NO. 12, DECEMBER 2020

IADCs [33]–[38], [40]–[52]. Unlike opamps (or OTAs),

a CMOS inverter does not offer a virtual ground. This brings a
design issue because when a negative feedback is applied, the
inverter input is close to the inverter’s offset voltage and the
amount of charge delivered to the feedback capacitor is highly
dependent on the offset voltage. The inverter-based amplifier
usually requires an additional offset cancellation or biasing
techniques [33]–[38], [41]–[48] due to the large variation and
Fig. 8. Zoom ADC architecture. drift of the inverter’s offset.
The gain of the inverter is limited and is continuously
reduced by the CMOS scaling. Cascode inverters can be used,
D. Zoom ADCs but they have drawbacks such as reduced output swing. Alter-
A zoom ADC is an energy-efficient, two-step architecture, natively, correlated double sampling (CDS) [39] or correlated
where a coarse Nyquist ADC is used in combination with a level shifting (CLS) [40] provide an elegant solution to miti-
fine  ADC [33]. For incremental operation, the Nyquist gate the limited gain of the amplifier, using a correlation capac-
ADC first performs a coarse conversion with a low resolution. itor before (CDS) or after (CLS) the amplifier. By applying a
In the next phase, the coarse results are used to set the refer- correlated sampling result to the second estimate, the error
ences of the fine  ADC, so that its input straddles the refer- in the final output can be reduced, thereby increasing the
ences of the current input. In contrast to other two-step archi- gain of the amplifier without suffering a signal swing penalty.
tectures, the fine  ADC of the zoom ADC does not involve The technique can effectively boost the gain of inverter-based
a residue calculation, so the ADC accuracy depends only on amplifier and extend the linear output swing [41], [42].
the accuracy of the fine  ADC and its references. The The inverter-based amplifier is susceptible to process, sup-
accuracy of the references should be maintained during the ply voltage and temperature (PVT) variations due to the
 conversion. However, this ‘zoom in’ operation relaxes lack of a reference current. However, numerous studies on
the resolution requirement of the fine ADC, since the input inverter-based amplifiers have been carried out. As a result,
range of the fine ADC is smaller than that of the coarse ADC. the PVT tolerances of the inverter-based amplifiers have
As a result, the conversion time of the  ADC is reduced, been significantly improved with various techniques, such as
resulting in a significant energy saving. current starving, dynamic biasing [33]–[36], [43]–[46], body-
Fig. 8 shows the block diagram of the zoom ADC. The first biasing [47], [48], and adaptive supply-biasing [49]–[51].
stage is an M-bit Nyquist ADC, and its coarse results are used
to select a subset of the  modulator references. The input
B. gm /I D Optimization of Inverter-Based Amplifiers
range of the  modulator is very small, typically a few LSBs
of the coarse ADC, so the internal swings of the loop filter can The maximum gm /I D can be obtained when the inverter
be reduced accordingly. This allows high-resolution IADCs is biased in weak inversion. Assuming that the two input
to be implemented with a single-bit  modulator [33]. The transistors are balanced in an inverter, both transistors are
reference linearity can be improved by using dynamic element equally biased to a half of the supply. Therefore, the supply
matching (DEM) during the fine  conversion. With the voltage must be scaled to achieve the maximum gm /ID [33].
zoom ADC, the timing overhead associated with the DEM However, such a supply scaling is not available for many
can be greatly relaxed compared to the multi-bit architecture, applications. This issue can be solved by using two coupling
because the coarse result has been decided beforehand and the capacitors (CC ), as shown in Fig. 9 [33], [34], [36], [45], [46].
DEM logic can be placed outside the -loop. Depending on This enables both input transistors to be biased with separate
the target applications, the coarse and fine ADCs in the zoom bias voltages and accordingly maximizes the gm /ID regardless
ADC can operate sequentially [33] or concurrently [34]–[36]. of the supply voltage. Typically, the value CC is designed to be
Since the update rate of the references determines the signal much larger than the input parasitic capacitance to minimize
bandwidth of the zoom ADC, a dynamic update with a fast the signal loss and distortion.
SAR is often used to increase the signal tracking capability To provide the optimal bias to input transistors, a reference
and the robustness against interferences [34]–[36]. While current can be used that also offers PVT immunity [43], [44].
zoom ADCs with a coarse SAR, a single-bit  modulator, Fig. 10 shows an inverter-based amplifier using a dynamic
and an SC loop filter are particularly efficient (Schreier’s bias scheme [33], [34], [46]. This basically consists of two
FoM = 182.7dB [33], 185.8dB [35]), a CT zoom ADC has branches: the main- and sub-branches, alternatively connected
been reported recently and achieved the similar efficiency to the input transistors (MP and MN ). During auto-zeroing
(183.6dB FoM) [36]. phase, the input transistors are connected to the sub-branch
with a floating current source IO , which defines the operating
IV. E NERGY-E FFICIENT A MPLIFIERS FOR IADC S points with the two CC capacitors. This provides the same
bias current for both MP and MN , canceling the offset and
A. Inverter-Based Amplifiers 1/ f noise. During integration phase, the inverter is discon-
An inverter-based amplifier offers an elegant solution nected from the IO and reconfigured as an inverter with a
for the challenges of high-performance ADCs, including well-defined bias current. Alternatively, the bias voltages for

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TAN et al.: IADCs: TUTORIAL REVIEW 4167

Fig. 9. An inverter-based amplifier using two coupling capacitors (CC ) during Fig. 11. An inverter-based amplifier that uses a dynamic bias scheme via
amplification. resistors Rb .

Fig. 10. An inverter-based amplifier using dynamic bias scheme (a) auto-
zeroing (b) integration.
Fig. 12. A dynamic amplifier using a dynamic integrator.

the transistors can be applied via resistors Rb , as shown charging with wide output swing. There are several vari-
in Fig. 11 [36], [43], [52]. This also allows the input transistors ants of the ring amplifier [55]–[58]. The number of invert-
to be biased to the desired current level and block the input ers is reduced in the second stage and the external biases
common-mode voltage. Since the Rb form a high-pass filter reduced by using a resistor [55]. It can achieve a high-speed
in the signal path, the resistance should be large enough not operation (>600MS/s) [56], [57] or a very precise settling
to compromise its signal gain. The use of large Rb can be a (>16bit) [58]. Some systematic design approaches also can
burden, but this can be solved by using a switched-resistor be found in [56], [58], [60].
technique [52].
D. Dynamic Amplifiers
C. Ring Amplifiers A dynamic integrator can be used for a gain ampli-
So far, single-stage inverter-based amplifiers are discussed, fier [61]–[63]. As shown in Fig. 12, the amplifier consists of
but a multi-stage amplifier can also be energy efficient. an input differential pair and two load capacitors. Since the
The ring amplifier provides an energy-efficient solution for common-mode (CM) voltage of the output changes during the
many ADCs [53]–[60] and can be readily used for  integration, the CM detection circuit provides the timing for
ADCs [54], [59]. The ring amplifier is essentially a three-stage disconnecting the current source with the load capacitors. This
inverter, two wideband amplifiers followed by the output gives the lowest bandwidth for a given integration time, and
stage. The second stage introduces an offset called dead thus the excess noise can be kept very low. The amplifier’s gain
zone, such that the output stage can be turned off for certain varies with temperature and supply voltage, and a background
conditions and the dead zone control enables the cascade calibration is often required to achieve a precise gain in
inverters to operate as an amplifier without using Miller pipeline ADCs [62]. With the appropriate design of the NTF,
compensation [53]. At the start, the large output current however, the loop filter of  ADC can be stable enough
quickly charges the load capacitor, in a so-called slew-based to accommodate moderate gain variations without calibration.
charging. During its stabilization, the ring amplifier transitions The dynamic amplifier can be used to build a FIR-IIR loop
from the large-signal behavior into its steady-state phase. filter [63].
Since the residual transients settle in the steady-state, the The conventional current-steering amplifier can be modified
small-signal behavior determines the final accuracy and noise to a charge-steering one, as shown in Fig. 13, whose tail
performance. The ring amplifier can achieve a high gain from current source has been replaced by a capacitor CT with
the cascade of three inverters, and benefits from slew-based switches [64]–[67]. The CT is discharged to ground in the

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4168 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 67, NO. 12, DECEMBER 2020

Fig. 15. Simplified schematic of 1st opamp incorporating chopping.

Since these noises in a  ADC are mainly determined by

the first integrator, their effects can be suppressed by chopping
the first amplifier stage (Gm1 ) of the opamp, as shown in
Fig. 15 [1], [36], [52], [70]–[73]. In SC implementation,
the chopper control fc is usually done by non-overlapping
Fig. 13. A charge-steering amplifier.
clocks with a frequency of fs /2, and the chopping is carried
out in the middle of the integrator’s hold phase [70]. The input
chopper switches are turned off shortly before the output ones
to minimize the charge injection from the output chopper.
In CT implementation, the situation is more complicated,
because the feedback DAC is mostly connected to the first
integrator [71]–[73]. One of the key issues is the quantization
noise (Q-noise) folding due to the intermodulation of the
shaped Q-noise and the chopper switches, severely degrading
the in-band noise performance. To address this issue, sev-
eral techniques have been proposed [71]–[73]. Chopping the
integrator at fs can be effective due to the NTF zeros at the
multiples of fs , but such high frequency chopping can cause
Fig. 14. A CMOS inverter with a reservoir capacitor CRES . performance degradation. Using a FIR feedback DAC with
its zeros at the multiples of 2fc both the chopping frequency
and Q-noise folding can be greatly reduced [72]. Recently, a
reset phase. During the amplification phase, the input pair is general model for Q-noise folding in a chopped integrator has
connected to CT and steers the charge to the outputs depending been provided, enabling fast estimation without long transient
on the input signal. The VGS of the input pair continues to simulations [73].
decrease until the input pair is switched off. This prevents the Better cancellation of the IADC’s offset can be achieved
load from being fully discharged and boosts the gm /ID during with high-order chopping, which is described as a fractal
amplification. This charge-steering concept can be evolved into sequencing in [1]. The configuration of the chopper switch
either open- or close-loop configurations [65]. Better energy- is the same, but with different control sequence. For instance,
efficiency can be achieved by a CMOS inverter with a reservoir the 2nd and 3rd -order sequences can be obtained with (+−−+)
capacitor CRES as shown in Fig. 14 [68], [69]. During the reset and ((+−−+) (−++ −)), respectively. Here, the +/− symbol
phase, the CRES is pre-charged to the supply voltage. During represents the in/out-phase connections of the chopper
the amplification, the inverter is turned on by connecting the switches. This is useful for high order IADCs because the
inverter with its supply rail to the CRES , and the differential offset is accumulated into the later integrators (not first one)
charge is integrated into the load capacitors. Since the supply and the output offset becomes non-zero value. The inverted
voltage of the inverter decreases over time due to the dis- chopping pattern of the high-order sequences can avoid the
charging of the CRES , the inverter current also decreases and offset integrations in the following integrators, resulting in a
eventually drops to zero, when the reservoir voltage is reached smaller offset. More intuitively, the high-order sequence can
at the threshold voltage of the input transistor. As a result, be seen as a nested chopping and has a better rejection for
it only consumes dynamic power. Since the input and output low-frequency errors.
current of CRES must be the same, the output common-mode
(CM) current is set to zero. It is worth noting that it offers
B. FIR Feedback
a decent CM rejection without a CMFB circuit. A two-stage
configuration has been used for an energy-efficient loop filter Fig. 16 shows a single-bit  modulator with finite impulse
design [69]. response (FIR) feedback F(z). The FIR feedback was pro-
posed in [74], [75], and now becomes quite popular [27],
V. E NERGY-E FFICIENT D ESIGN T ECHNIQUES [52], [72], [77]–[82]. The FIR filter reduces the high frequency
Q-noise, and its output closely follows the input signal. This
A. Chopping reduces the signal swings of the integrators and relaxes the
In many applications, the low frequency accuracy is very loop filter requirements. Assuming an N-tap FIR, the step
important, and is often limited by offset and 1/ f noise. size of the feedback DAC is reduced by a factor of N, and

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TAN et al.: IADCs: TUTORIAL REVIEW 4169

Fig. 17. An IADC using an integrator slicing scheme.

Fig. 16. A single-bit modulator with FIR feedback DAC.

the noise from clock jitter is correspondingly reduced due to

the reduced signal level during the DAC transition. As shown
in Fig. 16, the FIR-DAC is often implemented in a semi-digital
manner. The element mismatches between FIR tap weights
modify the transfer function but do not introduce nonlinearity.
Among the several feedback DAC options, therefore, FIR feed-
back is becoming increasingly popular, especially in single-bit
modulators [27], [77]–[81]. The FIR feedback can cause loop
instability due to the added delay, but a compensation FIR filter
can stabilize the loop, while preserving the original NTF [76].
The FIR feedback is not limited to single-bit modulators, and
multi-bit design have also been reported [82]–[84].
In the context of the incremental operation, the internal
states of the loop filer are reset prior to conversion, and the
initial state of the FIR taps does not track the input signal for
several cycles. This may cause a huge CM drift and increase
the initial signal swings of the integrators. When using a
cascade-of-integrators (CoI) filter and high number of taps, Fig. 18. (a) A negative-R assisted integrator. (b) The 1st integrator with an
assisted opamp technique.
the initial behavior has a significant impact on the dynamic
range. A possible solution is a differential resetting scheme
for FIR taps, where the elements are alternatively reset to high This slice implementation allows to deactivate parts of the
and low [80], [81]. This ensures that the feedback DAC output integrator one after another. This keeps the coefficient of the
starts at the right CM voltage and fast settling throughout first integrator constant, and the GBW of the integrator remains
the conversion cycles. This also allows more taps to be used the same. The prototype ADC shows a 43% power reduction
for IADCs. in the first integrator with very little noise increase (< 1dB).
It is worth to mention that this concept can be applied to any
C. Integrator Slicing nonlinearities in IADCs.
The IADCs often use unequal weights in the digital deci-
mation filter, especially for the high order decimation filters, D. 1st Integrator Optimization
and the contribution of the input samples is not uniform It is very important to maximize the energy-efficiency of
over the conversion time. It is therefore possible to increase the first integrator in  ADCs. There are several interesting
the non-idealities of the incremental  modulator during approaches to improve the energy-efficiency of the 1st inte-
a single conversion, thereby saving power [85], [86]. For grator. Fig. 18(a) shows the negative-R assisted integrator,
example, a 3rd -order IADC can be implemented with a an active RC integrator that uses a negative resistor in the
3rd -order modulator and a CoI3 decimation filter. As men- virtual ground [87]. This benefits the design of a CT  ADC
tioned earlier, the CoI3 filter causes a non-uniform weighting by relaxing the amplifier specifications. In particular, the noise
of the input signal as well as any input-referred noise. Since of the amplifier including thermal and 1/ f noise is attenuated,
the first integrator consumes most of the power to meet the and the integrator distortion is cancelled, resulting in signifi-
noise and linearity requirements, the slicing scheme shown cant power saving. In an active-RC integrator, the finite gain
in Fig. 17 can provide significant power savings [85]. The first of the amplifier creates a non-ideal virtual ground, resulting
integrator is divided into four identical slices, each slice acting in a current loss Iloss, as shown in Fig. 18. However, if a
as a standalone integrator. The overall integrator, i.e. 4-slice negative-R is applied to the virtual ground, the compensation
parallel, is designed to meet the target noise specifications. current Icomp can be generated to compensate for the Iloss.

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4170 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 67, NO. 12, DECEMBER 2020

Assuming ideal compensation, the DC gain of the integrator Circuit techniques were also reviewed to arrange an energy
with negative-R becomes infinite, and the UGB of the integra- efficient IADC implementation. The amplifier topologies
tor becomes 1/RIN CINT , regardless of the finite response of the based on inverters were reviewed in detail. The class-AB
amplifier. The transfer function of the amplifier noise seen at biasing nature can provide large driving capability, while
the integrator’s input shows a high-pass response sRIN CI, and keeping the quiescent current low. The low DC gain can be
the amplifier noise is significantly attenuated within the band tolerated through architectural optimizations, and this makes
of interest. Therefore, the negative-R assisted integrator can inverter-based amplifier a popular approach to IADC imple-
effectively handle the finite gain, finite bandwidth, and noise of mentation. The ring-amplifier is designed for fast settling as
the amplifier. Considering PVT variations, the desired value of well as high loop gain. Three cascaded inverters behave like an
the negative-R cannot be implemented exactly. Therefore, the amplifier, and second stage introduces a dead zone, such that
ultimate performance improvement of the negative-R assisted the last stage can be properly turned off. This arrangement
integrator is limited by the matching property between RIN yields fast settling and a sufficient phase margin without
and negative-R. The intrinsic 1/ f noise of the negative-R can Miller compensation, which leads to significate power savings.
also be a problem in low frequency applications. This can Several dynamic amplifiers have been reviewed. Among these,
be solved by chopping the negative-R of the 1st integrator, the floating inverter combines both an inverter-based amplifier
thereby mitigating the 1/ f noise of the IADC [81], [82]. It is and a dynamic biasing scheme that provides good power
worth noting that the integrator with the chopped negative-R efficiency and can be used for low power IADC design.
can achieve much less Q-noise folding compared to chopped Design techniques to improve the performance of IADCs
opamps [82]. are also introduced. Since the nature of such an IADC process
Compared to multibit modulators, the single-bit modulator mostly slowly varying input signals, the 1/ f noise of the
has stringent slew rate requirements for the first integrator, circuits must be mitigated. Chopped integrator and negative-R
due to the voltage steps in the feedback DAC. This leads to assisted integrator can be used to suppress 1/ f noise in which
voltage jumps in the virtual ground of the 1st opamp when the chopping involves modulation and filtering, while negative-R
feedback DAC switches, which degrades the modulator’s per- relies on the suppression. The FIR-DAC technique can be
formance. The conventional way of overcoming this problem applied to suppress errors of the 1st integrator. It utilizes a
is to enhance the oamp’s speed simply by increasing the bias feedback FIR filter to remove the high frequency quantization
current, thereby improving the linearity of the 1st integrator. noise, thereby the FIR-DAC output closely follows the input
However, the required current of the opamp is exactly known signal, and such an arrangement reduces the integrators’ output
due to the access to VIN and VDAC , and the efficiency of swing and relaxes the loop filter requirements even with
the 1st integrator can be improved by using an assistant, as the use of single-bit quantizer. The integrator slicing scheme
shown in Fig. 18(b) [88]. In this assisted opamp technique, is also very useful for the energy reduction of the IADC.
a pair of a transconductor (gm = 1/R) and a replica DAC Since the contribution of the input samples is not equal
(Iout = ±Vref /R) supplies a current at the output of the opamp. over the conversion in the IADC, the noise increases due to
This removes the current requirements of the first opamp from the integrator slicing during a single conversion result in a
the first place and reduces the excursion of the virtual ground. very little noise increase. To improve the energy-efficiency of
This results in a low distortion operation even with single- the IADCs, it is essential to optimize the 1st integrator. Some
bit  ADCs [88], [89]. Since the opamp does not require useful techniques such as the negative-R assisted integrator
to source/sink current, it can be implemented with very low and the assisted opamp technique can be used to make the
quiescent currents, thus saving the energy of the 1st integrator. integrator more efficient.
This assisted opamp technique is successfully applied to The insights from many IADCs are that hybrid structures
a CT IADC [90]. are employed to achieve higher resolution while maintaining
speed. One should maximize the SQNR within a conversion
time. Merging  ADC and Nyquist-rate ADC combines
VI. S UMMARY AND C ONCLUSION
advantages of both architectures. The recycling of IADC
In this paper, the fundamentals and operations of the IADC with several steps provides an extra degree of freedom for
were reviewed, and their pros and cons were compared with an additional resolution. Additional insights from the IADC
those of  ADCs. Several energy-efficient hybrid IADC implementation is that inverters are widely used as an analog
architectures that combine  ADC with Nyquist-rate ADC gain block. Using inverter-based amplifiers, IADCs achieve
were discussed. To achieve improved energy-efficiency, the very high resolution (20 bits) as well as very high energy
internal stages of the IADC can be recycled to perform an efficiency. Probably, we are likely to see more results with
extended counting. One can also use multi-step IADC to similar approaches that have never been used before. Another
improve area- and energy-efficiency. The principle of zoom aspect not to be forgotten is that the signals of interest are
ADCs is proposed to take advantage of the speed of Nyquist often aimed at using near DC. Therefore, IADCs must be
conversion and the accuracy of  conversion. In the incre- robust against offset and 1/ f noise, which requires additional
mental zoom ADC, the coarse ADC for fast range-finding care. Deeper insights into the unique features of IADCs can
indicates the fine range where the input voltage resides and pose challenges, but the design of IADCs would be more
the  ADC only works within a few coarse LSBs, which interesting. We hope that these citations can be a good starting
greatly improves the SQNR. point for new IADC research.

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TAN et al.: IADCs: TUTORIAL REVIEW 4171

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TAN et al.: IADCs: TUTORIAL REVIEW 4173

Zhichao Tan (Senior Member, IEEE) received Youngcheol Chae (Senior Member, IEEE) received
the B.Eng. degree from Xi’an Jiaotong University, the B.S., M.S., and Ph.D. degrees in electrical
Xi’an, China, in 2004, the M.Eng. degree from and electronic engineering from Yonsei Univer-
Peking University, Beijing, China, in 2008, and the sity, Seoul, South Korea in 2003, 2005, and 2009,
Ph.D. degree from the Delft University of Technol- respectively.
ogy, Delft, The Netherlands, in 2013. He was with the Delft University of Technology,
He was with Analog Devices Inc., from 2013 to Delft, The Netherlands, from 2009 to 2011, as a
2019, as a Staff IC Design Engineer working on Post-Doctoral Researcher. Since 2012, he has been
low power high-precision analog/mixed signal cir- on the faculty with Yonsei University, where he
cuit design. In 2019, He joined Zhejiang University is currently an Associate Professor. His work has
as a Faculty Member. In addition to five U.S. patents, focused on data converters and sensor interfaces. His
he has authored or coauthored more than 20 technique journal and conference results in more than 90 journal and conference papers and 30 patents.
papers. His current research interests include energy-efficient sensor interfaces, Dr. Chae is a member of the Technical Program Committees of International
precision analog circuits, and ultra-low-power ADCs. Solid-State Circuits Conference (ISSCC) and Asian Solid-State Circuits
Dr. Tan is a member of the Technical Program Committee (TPC) of IEEE Conference (A-SSCC). He received the Best Young Professor Award in
Asian Solid-State Circuits Conference. He has served as an Associate Editor Engineering from Yonsei University in 2018, the Haedong Young Engineer
for IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS —I: R EGULAR Award from IEE Korea in 2017, the Outstanding Research Award of Yonsei
PAPERS from 2016 to 2019 and a TPC Member of IEEE Sensors Confer- University from 2017 to 2019, and the Outstanding Teaching Awards of
ence and IEEE International Instrumentation and Measurement Technology Yonsei University from 2013 to 2014. He received a research grant from
Conference. He is currently an Associate Editor of IEEE T RANSACTIONS the Samsung Research Funding Center in 2017 and a VENI grant from the
ON I NDUSTRIAL E LECTRONICS and IEEE S ENSORS J OURNAL. He is the Dutch Technology Foundation STW in 2011. He has served as a Guest Editor
Chair of IEEE Industrial Electronics Society Technical Committee on MEMS of the Journal of Solid-State Circuits and a Distinguished Lecturer of IEEE
and Nanotechnology for the period of 2019–2020. Solid-State Circuits Society from 2018 to 2019.

Gabor C. Temes (Life Fellow, IEEE) received the

bachelor’s degrees from the Technical University of
Budapest, Budapest, Hungary, and Eötvös Univer-
sity, Budapest, Hungary, in 1952 and 1955, respec-
tively, the Ph.D. degree in electrical engineering
from the University of Ottawa, Ottawa, ON, Canada,
Chia-Hung Chen (Member, IEEE) received the B.S. in 1961, and the Honorary Doctorate degree from the
degree in nuclear engineering from National Tsing Technical University of Budapest, in 1991.
Hua University, Hsinchu, Taiwan, in 1994, the M.S. He is a member of the U.S National Academy
degree in electrical engineering from Columbia Uni- of Engineering and the U.S. National Academy of
versity, New York, NY, USA, in 2003, and the Ph.D. inventors. In 1968 and 1981, he was co-winner of
degree from Oregon State University, Corvallis, OR, the IEEE CAS Darlington Award, and in 1984 winner of the Centennial
USA, in 2013. Medal of the IEEE. He received the Andrew Chi Prize Award of the IEEE
He worked with Analog Devices, Taiwan, from Instrumentation and Measurement Society in 1985, the Education Award of
2003 to 2006. From 2006 to 2009, he worked the IEEE CAS Society in 1987, and the Technical Achievement Award of
with Terawins Inc., Taiwan, designing audio codec the IEEE CAS Society in 1989. He received the IEEE Graduate Teaching
circuits, DC–DC power converters and PLLs. From Award in 1998, and the IEEE Millennium Medal, as well as the IEEE CAS
2013 to 2014, he was with Mediatek, Woburn, MA, USA. He is currently Golden Jubilee Medal in 2000. He was the 2006 recipient of the IEEE Gustav
an Assistant Professor with the Department of Electrical and Computer Robert Kirchhoff Award, and the 2009 IEEE CAS Mac Valkenburg Award.
Engineering, National Chiao Tung University, Hsinchu, Taiwan. His research He received the 2017 SIA-SRC University Researcher Award. He was an
interests include the design of precision analog circuits and energy-efficient Editor of the IEEE T RANSACTIONS ON C IRCUIT T HEORY and the Vice
data converters. President of the IEEE Circuits and Systems (CAS) Society.

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