LXT905

Universal 10BASE-T Transceiver with 3.3V Support

Datasheet
The LXT905 Universal 10BASE-T Transceiver is designed for IEEE 802.3 physical layer
applications. It provides, in a single CMOS device, all the active circuitry for interfacing most
standard IEEE 802.3 controllers to 10BASE- T media.

The LXT905 functions include Manchester encoding/decoding, receiver squelch and transmit
pulse shaping, jabber, link integrity testing, and reversed polarity detection/correction. The
LXT905 drives the 10BASE-T twisted-pair cable, with only a simple isolation transformer,
using a single 3.3V or 5V power supply. Integrated filters simplify the design work required for
FCC-compliant EMI performance.

The LXT905 is part of the Intel Carrier Class Ethernet family of products. The LXT905
Universal Transceiver offers 10BASE-T connectivity solutions that support operations over an
extended temperature range, while providing features that increase reliability. The device has an
operational lifetime of at least ten years, with less than 100 failures per billion hours, and will be
available a minimum of five years from the introduction of the product.

Intel Carrier Class Ethernet products are ideal for applications where equipment must function
reliably under environmentally controlled conditions, such as base stations, telecom/network
switches, factory floor equipment, and industrial computers.

Applications
■ Access devises (DSL, Cable Modems, and ■ Telecom Backplane
Set-top Boxes) ■ USB to Ethernet Converters
■ Routers/Bridges/Switches/Hubs

Product Features
■ Transparent 3.3V or 5V operation ■ Full-duplex capability
■ Integrated filters – Simplifies FCC ■ Power-down mode with tri-state
compliance ■ Available in 28-pin PLCC and 32-pin
■ Integrated Manchester encoder/decoder LQFP packages
■ 10BASE-T compliant transceiver ■ Commercial Temperature Range ( 0 to
■ Automatic polarity correction +70ºC)
■ SQE enable/disable ■ Extended Temperature Range (-40 to
+85ºC)
■ Four LED drivers

For technical assistance on this product, please call 1-800-628-8686, Order Number: 249271-002
or send an e-mail to [email protected]. June 2001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT905 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.

2 Datasheet
Document #: 249271
Revision #: 002
Rev. Date: June 19, 2001
 Contents

Contents
1.0 Pin Assignments and Signal Descriptions ...................................................... 8
2.0 Functional Description........................................................................................... 10
2.1 Introduction.......................................................................................................... 10
2.2 Controller Compatibility Modes ........................................................................... 11
2.3 Transmit Function................................................................................................ 11
2.4 Jabber Control Function ...................................................................................... 12
2.5 SQE Function ...................................................................................................... 13
2.6 Receive Function................................................................................................. 13
2.7 Polarity Reverse Function ................................................................................... 14
2.8 Collision Detection Function................................................................................ 14
2.9 Loopback Functions ............................................................................................ 15
2.9.1 Internal Loopback................................................................................... 15
2.9.2 External Loopback/Full Duplex............................................................... 15
2.10 Link Integrity Test Function ................................................................................. 15
3.0 Application Information ......................................................................................... 17
3.1 Introduction.......................................................................................................... 17
3.1.1 Termination Circuitry .............................................................................. 17
3.1.2 Twisted-Pair Interface ............................................................................ 17
3.1.3 RBIAS Pin .............................................................................................. 17
3.1.4 Crystal Information ................................................................................. 17
3.1.5 Magnetic Information.............................................................................. 18
3.2 Typical 10BASE-T Application ............................................................................ 18
3.3 Dual Network Support - 10BASE-T and Token Ring........................................... 19
3.4 Simple 10BASE-T Connection ............................................................................ 21
4.0 Test Specifications .................................................................................................. 22
4.1 Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low) Figures 11 - 14............ 26
4.2 Timing Diagrams for Mode 2 (MD1 = Low, MD0 = High) Figures 15 - 18 ........... 28
4.3 Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low) Figures 19 - 22 ........... 30
4.4 Timing Diagrams for Mode 4 (MD1 = High, MD0 = High) Figures 23 - 26 .......... 32
5.0 Mechanical Specifications.................................................................................... 34
A Ordering Information .............................................................................................. 37

Figures
1 LXT905 Block Diagram ......................................................................................... 7
2 LXT905 Pin Assignments ...................................................................................... 8
3 LXT905 TPO Output Waveform .......................................................................... 10
4 Jabber Control Function ...................................................................................... 12
5 SQE Function ...................................................................................................... 13
6 Collision Detection Function................................................................................ 14
7 Link Integrity Test Function ................................................................................. 16

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Contents

8 Intel Controller Application (Mode 2) ................................................................... 19

9 LXT905/380C26 Interface for Dual 10BASE-T and Token Ring Support
(Mode 4).............................................................................................................. 20
10 LXT905/MC68EN360 Interface for Full-Duplex 10BASE-T (Mode 1) ................. 21
11 Mode 1 RCLK/Start-of-Frame Timing ................................................................ 26
12 Mode 1 RCLK/End-of-Frame Timing .................................................................. 26
13 Mode 1 Transmit Timing .................................................................................... 27
14 Mode 1 COL Output Timing ............................................................................... 27
15 Mode 2 RCLK/Start-of-Frame ............................................................................ 28
16 Mode 2 RCLK/End-of-Frame Timing .................................................................. 28
17 Mode 2 Transmit Timing .................................................................................... 29
18 Mode 2 COL Output Timing ............................................................................... 29
19 Mode 3 RCLK/Start-of-Frame Timing ................................................................ 30
20 Mode 3 RCLK/End-of-Frame Timing................................................................... 30
21 Mode 3 Transmit Timing .................................................................................... 31
22 Mode 3 COL Output Timing ............................................................................... 31
23 Mode 4 RCLK/Start-of-Frame Timing ................................................................ 32
24 Mode 4 RCLK/End-of-Frame Timing .................................................................. 32
25 Mode 4 Transmit Timing .................................................................................... 33
26 Mode 4 COL Output Timing ............................................................................... 33
27 LXT905PC Package Specifications ................................................................... 34
28 LXT905LC Package Specifications .................................................................... 35
29 Ordering Information - Sample............................................................................ 37

Tables
1 LXT905 Signal Descriptions .................................................................................. 9
2 Controller Compatibility Mode Options................................................................ 11
3 Loopback Modes ................................................................................................. 15
4 Suitable Crystals ................................................................................................. 17
5 Absolute Maximum Values.................................................................................. 22
6 Recommended Operating Conditions ................................................................. 22
7 I/O Electrical Characteristics ............................................................................... 22
8 TP Electrical Characteristics ............................................................................... 23
9 Switching Characteristics .................................................................................... 23
10 RCLK/Start-of-Frame Timing .............................................................................. 24
11 RCLK/End-of-Frame Timing................................................................................ 24
12 Transmit Timing .................................................................................................. 24
13 Miscellaneous Timing.......................................................................................... 25
14 PLASTIC LEADED CHIP CARRIER ................................................................... 34
15 QUAD FLAT PACKAGE...................................................................................... 35
16 Product Information............................................................................................. 37

4 Datasheet
Document #: 249271
Revision #: 002
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 Contents

Revision History
Date Revision Page # Description

1 New information under “Applications”.

1 Added new carrier class information (paragraphs 3 and 4).
19 Added +5V to Line Status, Figure 8.
20 Added +5V to Line Status, Figure 9.
June 2001 002
Added second paragraph under Test Specifications “Note”
22
regarding Quality and Reliability issues.
22 Deleted Ambient operating temperatures from Table 5.
Added new diagram and table for LXT905PC/PE mechanical
34
specifications.

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 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

Figure 1. LXT905 Block Diagram

Mode Select Logic

Controller MD0
LI MD1
Compatibility /
TCLK Loopback /
Link Test RC
CLKI XTAL Pulse
CLKO OSC Watch-Dog Shaper CMO TPOP
Manchester Timer D S
TEN &
Encoder Filter TX TPON
TXD
Loopback RC
Control
CD Squelch/
Collision/ TPIP
LEDL Link Detect RX
RCLK Polarity
Manchester Detect/ Slicer
RXD Decoder TPIN
Correct

Collision
COL Logic

LEDR LEDT/PDN LEDC/FDE DSQE LBK

Datasheet 7
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LXT905 — Universal 10BASE-T Transceiver with 3.3V Support

1.0 Pin Assignments and Signal Descriptions

Figure 2. LXT905 Pin Assignments

GND4
CLKO

VCC5
VCC4
VCC3
TPIN
TPIP
CLKI

GND3
CLKO

VCC1
TPIN
CLKI

TPIP
MD1
32
31
30
29
28
27
26
25
24 MD1

4
3
2
1
28
27
26
LBK 1
TEN 2 23 MD0 LBK 5 25 MD0
TCLK 3 Rev # 22 TPON TEN 6 24 TPON
4 LQFP 21 GND3 TCLK 7 Rev # 23 GND2
TXD PLCC
COL 5 Part # LXT905LC/LE XX 20 VCC2 TXD 8 Part # LXT905PC/PE XX 22 VCC2
LOT # XXXXXX COL TPOP
LEDC/FDE 6 FPO # XXXXXXXX 19 TPOP 9 LOT # XXXXXX 21
FPO # XXXXXXXX
LEDT/PDN 7 18 DSQE LEDC/FDE 10 20 DSQE
LEDR 8 17 RBIAS LEDT/PDN 11 19 RBIAS

12
13
14
15
16
17
18
10
11
12
13
14
15
16
9

LEDR

CD

RXD
LEDL

GND1
RCLK

LI
LI
CD

RXD
LEDL

GND1
GND2
VCC1
RCLK

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 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

Table 1. LXT905 Signal Descriptions

LQFP PLCC
Symbol I/O Description
Pin # Pin #

13 1 VCC1 –
20 22 VCC2 –
27 – VCC3 – Power Inputs 1 thru 5. Power supply inputs of 3.3V or 5V.
28 – VCC4 –
29 – VCC5 –
30 2 CLKI I Crystal Oscillator. A 20 MHz crystal must be connected across these pins, or a
31 3 CLKO O 20 MHz clock applied at CLKI, with CLKO left open.

11 15 GND1 –
12 23 GND2 –
Ground.
21 4 GND3 –
32 – GND4 –
Loopback. When High, forces internal loopback. Disables collision and the
1 5 LBK I
transmission of both data and link pulses. Pulled Low internally1.
Transmit Enable. Enables data transmission and starts the Watch-Dog Timer
2 6 TEN I
(WDT). Synchronous to TCLK. Pulled Low internally1.
Transmit Clock. A 10 MHz clock output. This clock signal should be directly
3 7 TCLK O
connected to the transmit clock input of the controller.
Transmit Data. Input signal containing NRZ data to be transmitted on the
4 8 TXD I network. TXD should be connected directly to the transmit data output of the
controller. Pulled Low internally1.
5 9 COL O Collision Signal. Output that drives the collision detect input of the controller.
LED Collision or Full-Duplex Enable.
O LEDC is an open drain driver for the collision indicator pulls Low during collision.
LEDC/
6 10 LED “on” (which is Low output) time is extended by approximately 100 ms.
FDE I
FDE enables full-duplex mode (external loopback) if tied Low externally. Pulled
High internally1.
LED Transmit or Power Down.
LEDT is an open drain driver for the transmit indicator. LED “on” (which is Low
LEDT/ O output) time is extended by approximately 100 ms. Output is pulled Low during
7 11
PDN I transmit.2
If externally tied Low, the LXT905 goes to power down state (PDN). In power-
down mode, all logic inputs and outputs are tristated.
LED Receive. Open drain driver for the receive indicator LED. LED “on” (i.e.,
8 12 LEDR O Low output) time is extended by approximately 100 ms. Output is pulled Low
during receive. Pulled High internally1.
LED Link. Open drain driver for link integrity indicator. Output is pulled Low
9 13 LEDL O
during link test pass. Pulled High internally1.
Carrier Detect. An output for notifying the controller that activity exists on the
10 14 CD O
network.
Receive Clock. A recovered 10 MHz clock that is synchronous to the received
14 16 RCLK O
data and connected to the controller receive clock input.
Receive Data. Output signal connected directly to the receive data input of the
15 17 RXD O
controller.
1. Externally pull-up or pull-down each pin separately using a 10k Ω, 1% termination resistor or tie directly to VCC or ground.
2. Do not allow this pin to float. If unused, tie High.

Datasheet 9
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LXT905 — Universal 10BASE-T Transceiver with 3.3V Support

Table 1. LXT905 Signal Descriptions (Continued)

LQFP PLCC
Symbol I/O Description
Pin # Pin #

Link Enable. Controls link integrity test; enabled when LI is High, disabled
16 18 LI I
when LI is Low.
Bias Circuitry. A 7.5 kW 1% resistor to ground at this pin controls operating
17 19 RBIAS I
circuit bias.
SQE Disable. When DSQE is High, the SQE function is disabled.
18 20 DSQE I When DSQE is Low, the SQE function is enabled. SQE should be disabled for
normal operation in Hub/Switch/Repeater applications. Pulled Low internally1.
19 21 TPOP O Twisted-Pair Outputs. Differential outputs to the twisted-pair cable. The
22 24 TPON O outputs are pre-equalized.

23 25 MDO I Mode Select 0 and 1. Mode select pins determine controller compatibility mode
24 26 MDI I in accordance with Table 2. Pulled Low internally 1.

25 27 TPIP I Twisted-Pair Inputs. A differential input pair from the twisted-pair cable.
26 28 TPIN I Receive filter is integrated on-chip. No external filters are required.

1. Externally pull-up or pull-down each pin separately using a 10k Ω, 1% termination resistor or tie directly to VCC or ground.
2. Do not allow this pin to float. If unused, tie High.

2.0 Functional Description

2.1 Introduction
The LXT905 Universal 10BASE-T Transceiver performs the physical layer signaling (PLS) and
Media Attachment Unit (MAU) functions, as defined by the IEEE 802.3 specification. It functions
as an integrated PLS/MAU for use with 10BASE-T twisted-pair networks.

The LXT905 interfaces a back-end controller to a twisted-pair (TP) cable. The controller interface
includes a transmit and receive clock and NRZ data channels, as well as mode control logic and
signaling. The twisted-pair interface comprises two circuits: Twisted-Pair Input (TPI) and Twisted-
Pair Output (TPO). In addition to the two basic interfaces, the LXT905 contains an internal crystal
oscillator and four LED drivers for visual status reporting.

Functions are defined from the back-end controller side of the interface. The LXT905 Transmit
function refers to data transmitted by the back-end to the twisted-pair network The LXT905
Receive function refers to data received by the back-end from the twisted-pair network. The
LXT905 performs all required functions defined by the IEEE 802.3 10BASE-T MAU
specification, such as collision detection, link integrity testing, signal quality error messaging,
jabber control, and loopback.
Figure 3. LXT905 TPO Output Waveform

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 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

2.2 Controller Compatibility Modes

The LXT905 is compatible with most industry standard controllers, including devices produced by
Advanced Micro Devices (AMD), Intel, Fujitsu, National Semiconductor, Seeq, Motorola, and
Texas Instruments. Four different control signal timing and polarity schemes (Modes 1 through 4)
are required to achieve this compatibility. Mode select pins MD0 and MD1 determine controller
compatibility modes as listed in Table 2. Refer to the Test Specifications section for timing
diagrams and parameters.

2.3 Transmit Function

The LXT905 receives NRZ data from the controller at the TXD input, as shown in the block
diagram, and passes it through a Manchester encoder. The encoded data is then transferred to the
twisted-pair network (TPO circuit). The advanced integrated pulse shaping and filtering network
produces the output signal on TPON and TPOP, as shown in Figure 3 on page 10. The TPO output
is pre-distorted and pre-filtered to meet the 10BASE-T jitter template. An internal, continuous
resistor-capacitor filter is used to remove any high-frequency clocking noise from the pulse
shaping circuitry. Integrated filters simplify the design work required for FCC compliant EMI
performance. During idle periods, the LXT905 transmits link integrity test pulses on the TPO
circuit (if LI is enabled and LBK is disabled).

Table 2. Controller Compatibility Mode Options

Controller Mode MD1 MD0

Mode 1 - For Motorola MC68EN360 or compatible controllers (AMD AM7990) Low Low
1
Mode 2 - For Intel 82596 or compatible controllers Low High
2
Mode 3 - For Fujitsu MB86950, MB86960 or compatible controllers (Seeq 8005) High Low
Mode 4 - For TI TMS380C26 or compatible controllers High High
1. Refer to Intel Application Note 51 (MAC Interface Design Guide for Intel Controllers) when designing with
Intel controllers.
2. SEEQ controllers require inverters on CLKI, LBK, RCLK and COL.

Datasheet 11
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LXT905 — Universal 10BASE-T Transceiver with 3.3V Support

2.4 Jabber Control Function

Figure 4 is a state diagram of the LXT905 jabber control function. The LXT905 on-chip Watch-
Dog Timer (WDT) prevents the DTE from locking into a continuous transmit mode. When a
transmission exceeds the time limit, the WDT disables the transmit and loopback functions and
activates the COL pin. Once the LXT905 is in the jabber state, the TXD circuit must remain idle
for a period of 0.25 to 0.75 seconds before it exits the jabber state.
Figure 4. Jabber Control Function

Power On

No Output

DO=Active

Nonjabber Output
Start_XMIT_MAX_Timer

DO=Idle DO=Active ∗
XMIT_Max_Timer_Done

Jab
XMIT=Disable
LPBK=Disable
CI=SQE

DO=Idle

Unjab Wait
Start_Unjab_Timer
XMIT=Disable
LPBK=Disable
CI=SQE

Unjab_ Timer_Done DO=Active ∗

Unjab_Timer_Not_Done

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 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

2.5 SQE Function

The LXT905 supports the Signal Quality Error (SQE) function as shown in Figure 5. After every
successful transmission on the 10BASE-T network, the LXT905 transmits the SQE signal for 10
bit times (BT) ± 5BT on the COL pin of the device.

The SQE can be disabled for repeater/switch applications. When DSQE is set High, the SQE
function is disabled. When DSQE is Low, the SQE function is enabled.
Figure 5. SQE Function

Power On

Output Idle

DO=Active

Output Detected

DSQE=1 DO=Idle ∗
DSQE=0

SQE Wait Test

Start_SQE_Test__Wait_Timer

XMIT=Disable SQE_Test__Wait_Timer_Done ∗
XMIT=Enable

SQE Test
Start_SQE_Test_Timer
CI=SQE

SQE_Test_Timer_Done

2.6 Receive Function

The LXT905 receive function acquires timing and data from the twisted-pair network (TPI circuit).
Valid received signals are passed through the on-chip filters and Manchester decoder, then output
as decoded NRZ data and receive timing on the RXD and RCLK pins, respectively.

An internal RC filter and an intelligent squelch function discriminate noise from link test pulses
and valid data streams. The receive function is activated only by valid data streams above the
squelch level with proper timing.

If the differential signal at the TPI circuit inputs falls below 85 percent of the threshold level
(unsquelched) for 8 bit times (typical), the LXT905 receive function enters the idle state. The
LXT905 automatically corrects reversed polarity on the TPI circuit.

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LXT905 — Universal 10BASE-T Transceiver with 3.3V Support

2.7 Polarity Reverse Function

The LXT905 polarity reverse function uses both link pulses and end-of-frame data to determine
polarity of the received signal. If Link Integrity testing is disabled, polarity detection is based only
on received data. A reversed polarity condition is detected when eight consecutive opposite receive
link pulses are detected without receipt of a link pulse of the expected polarity. Reversed polarity is
also detected if four consecutive frames are received with a reversed start-of-idle. Whenever a
correct polarity frame or a correct link pulse is received, these two counters are reset to zero. If the
LXT905 enters the link fail state and no valid data or link pulses are received within 96 to 128 ms,
the polarity is reset to the default non-flipped condition. Polarity correction is always enabled.

2.8 Collision Detection Function

A collision is defined as the simultaneous presence of valid signals on both the TPI circuit and the
TPO circuit. The LXT905 reports collisions to the back-end via the COL pin. If the TPI circuit
becomes active while there is activity on the TPO circuit, the TPI data is passed to the back-end
over the RXD circuit, disabling normal loopback. Figure 6 is a state diagram of the LXT905
collision detection function.
Figure 6. Collision Detection Function

A Power On

TEN=Active ∗ Idle
TPI=Idle ∗
XMIT=Enable TPI=Active

Output Input
TPO=TXD RXD=TPI
RXD=TXD

TEN=Active ∗ TEN=Active ∗
TPI=Active ∗ TPI=Active ∗
XMIT=Enable XMIT=Enable

Collision

A TPO=TXD A
RXD=TPI
TEN=Idle + COL=ACTIVE TPI=Idle
XMIT=Disable

TEN=Active ∗
TEN=Idle
TPI=Idle

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 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

2.9 Loopback Functions

2.9.1 Internal Loopback

The LXT905 provides standard loopback mode as specified in the IEEE specification for the
twisted-pair port, as well as a forced internal loopback mode. Loopback mode operates in
conjunction with the transmit function. Data transmitted by the MAC is internally looped back
within the LXT905 from the TXD pin through the Manchester encoder/decoder to the RXD pin
and returned to the MAC.

Standard loopback mode is disabled when a data collision occurs, clearing the RXD circuit for the
TPI data. Standard loopback is also disabled during link fail, jabber, and full-duplex states.
Loopback is always enabled during forced internal loopback mode.

2.9.2 External Loopback/Full Duplex

The LXT905 also provides an external loopback test mode for system-level testing. When both
LEDC/FDE and LBK are Low, the LXT905 enables external loopback and full-duplex mode.
Internal loopback circuits, SQE, and collision detection are disabled. Refer to Table 3 for a
summary of loopback and duplex modes.

Table 3. Loopback Modes

Pin Settings
Mode Description
LEDC/
LBK
FDE

Disable internal loopback.

Low Low
Enable external loopback test mode and full-duplex mode.
Standard loopback mode (default).
Data transmitted by the MAC is internally looped back and returned to the MAC except during
Low High collision.
Standard loopback is disabled when a data collision occurs, clearing RXD for data on the
twisted-pair port.
High Low Not Used.
Forced internal loopback.
High High
Transmit data is looped back on the receive data bus and the twisted-pair port is ignored.

2.10 Link Integrity Test Function

Figure 7 on page 16 is a state diagram of the LXT905 Link Integrity test function. The link
integrity test is used to determine the status of the receive side twisted-pair cable. Link integrity
testing is enabled when LI is tied High. When enabled, the receiver recognizes link integrity pulses
which are transmitted in the absence of receive traffic. If no serial data stream or link integrity
pulses are detected within 50~150 ms, the chip enters a link fail state and disables the transmit and
normal loopback functions. The LXT905 ignores any link integrity pulse with interval less than
2~7 ms. The LXT905 remains in the link fail state until it detects either a serial data packet or two
or more link integrity pulses.

Datasheet 15
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LXT905 — Universal 10BASE-T Transceiver with 3.3V Support

Figure 7. Link Integrity Test Function

Power On

Idle Test
Start_Link_Loss_Timer
Start_Link_Test_Min_Timer TPI=Active +
(Link_Test_Rcvd=True ∗
Link_Test_Min_Timer_Done)
Link_Loss_Timer_Done ∗
TPI=Idle ∗
Link_Test_Rcvd=False

Link Test Fail Reset

Link_Count=0 Link Test Fail Wait
XMIT=Disable
XMIT=Disable
RCVR=Disable
RCVR=Disable
LPBK=Disable
LPBK=Disable
Link_Count=Link_Count + 1
TPI=Active Link_Test_Rcvd=False
∗ TPI=Idle
TPI=Active Link_Test_Rcvd=Idle
∗ TPI=Idle

Link Test Fail

Start_Link_Test_Min_Timer
Start_Link_Test_Max_Timer
XMIT=Disable
RCVR=Disable
LPBK=Disable
TPI=Active +
Link_Count=LC_Max
Link_Test_Min_Timer_Done
∗ Link_Test_Rcvd=True

Link Test Fail Extended

XMIT=Disable
RCVR=Disable
(TPI=Idle ∗ Link_Test_Max_Timer_Done) +
LPBK=Disable
(Link_Test_Min_Timer_Not_Done ∗
Link_Test_Rcvd=True)
TPI=Idle ∗
DO=Idle

16 Datasheet
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Rev. Date: June 19, 2001
 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

3.0 Application Information

3.1 Introduction
Figure 8 on page 19 through Figure 10 on page 21 show typical LXT905 applications. These
diagrams group similar pins; they do not portray the actual chip pinout. The controller interface
pins; Transmit Data (TXD), Transmit Clock (TCLK) Transmit Enable (TEN), Receive Data
(RXD), Receive Clock (RCLK), Collision Signal (COL), and Carrier Detect (CD) pins are at the
upper left of the diagram.

Power and ground pins are at the bottom of each diagram. VCC1 and VCC2 use a single power
supply with decoupling capacitors installed between the power and ground busses. VCC may be
powered by a 5V or 3.3V supply.

3.1.1 Termination Circuitry

Several I/O pins are pulled-up or pulled-down internally to keep the signals from floating. It is
recommended to hard-wire these pins either High or Low. Externally pull-up pins (LEDT/PDN,
LEDC/FDE, LEDR, LEDL) and pull-down pins (LBK, TEN, TXD, DSQE, MDO, MDI)
separately using a 10k Ω, 1% resistor, or tie directly to VCC or ground.

3.1.2 Twisted-Pair Interface

The Twisted-Pair interface (TPOP/N and TPIP/N) is at the upper right of the diagram. The I/O
pairs have impedance-matching resistors for 100Ω UTP, but no external filters are required.

3.1.3 RBIAS Pin

The RBIAS pin sets the levels for the LXT905 output drivers. The LXT905 requires a 7.5k Ω, 1%
resistor directly connected between the RBIAS pin and ground. This resistor should be located as
close to the device as possible. Keep the traces as short as possible and isolated from all other high
speed signals.

3.1.4 Crystal Information

Based on limited evaluation, Table 4 lists some suitable crystals. Designers should test and validate
all crystals before committing to a specific component.

Table 4. Suitable Crystals

Manufacturer Part Number

MP-1
MTRON
MP-2

Datasheet 17
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LXT905 — Universal 10BASE-T Transceiver with 3.3V Support

3.1.5 Magnetic Information

The LXT905 requires a 1:1 turns ratio for the receive transformer and a 1:2 turns ratio for the
transmit transformer. Application Note 073, Magnetic Manufacturers (248991-001) lists
transformers suitable for the applications described in this data sheet. Designers are advised to test
and validate all magnetics before committing to a specific component.

3.2 Typical 10BASE-T Application

Figure 8 on page 19 is a typical LXT905 application. The DTE is connected to a 10BASE-T
network through the twisted-pair RJ-45 connector. With MD0 tied high and MD1 grounded, the
LXT905 logic and framing are set to Mode 2 (compatible with Intel 82596 controllers*). Connect a
20 MHz system clock input at CLKI (leave CLKO open). The LI pin externally controls the link
test function.

* Refer to Intel Application Note 51, MAC Interface Design Guide for Intel Controllers (249007-
001) when designing with Intel controllers.

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 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

Figure 8. Intel Controller Application (Mode 2)

0.1 µF RJ-45
Not Connected 1 1:1 16
CLKO TPIN 6
CLK

Twisted-Pair Network
20 MHz System Clock CLKI 50 Ω 1%
TXD 5

To 10 Base-T
TXD
RTS
82596 TEN 50 Ω 1% 4
Back-End/ TXC
TCLK 3 14
Controller RXC TPIP 3
Interface RXD
RCLK 6 1:2 11
RXD TPON 2
CRS 11.8 Ω 1%
CD 1
CDT
COL LXT905
11.8 Ω 1%
TPOP
8 9
Programming MD0
Options 100 pF
MD1
DSQE
100 pF
Link Test Enable LI
Loopback Enable LBK

Line Status
10K
LEDL
10K
+5V LEDC/FDE
10K
LEDT/PDN 7.5 kΩ 1%
RBIAS
+5V VCC1
VCC2 GND1 GND2
Power Full
Down Duplex

0.1 µF

1 Optional: Centertap capacitor may improve EMC depending on board layout and system design.

3.3 Dual Network Support - 10BASE-T and Token Ring

Figure 9 on page 20 shows the LXT905 with a Texas Instruments 380C26 CommProcessor. The
380C26 is compatible with Mode 4 (MD0 and MD1 both high). When used with the 380C26, both
the LXT905 and a TMS38054 Token Ring transceiver can be tied to a single RJ-45 allowing dual
network support from a single connector.

Datasheet 19
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LXT905 — Universal 10BASE-T Transceiver with 3.3V Support

Figure 9. LXT905/380C26 Interface for Dual 10BASE-T and Token Ring Support (Mode 4)

To TI TMS38054 From TI TMS38054

Token Ring Token Ring
Transceiver 20 MHz Transceiver

20 pF 20 pF 1

CLKI CLKO 0.1 µF 2 RJ-45

TXD TXD
1 1:1 16
TXE TEN TPIN 6

Twisted-Pair Network
TXC TCLK 50 Ω 1%
380C26

To 10 Base-T
RXC RCLK
RXD RXD 50 Ω 1% 4
3 14
CRS CD TPIP 3
COL COL 6 1:2 11
LBK TPON 2
LBK
11.8 Ω 1%
LXT905

1
MD0
11.8 Ω 1%
MD1
TPOP
8 9
+5V Line Status LI
100 pF
300 300 300 300
100 pF

LEDR
Green Red Red Red
LEDC/FDE
LEDT/PDN
LEDL
7.5 kΩ 1%
+5V VCC1 RBIAS
VCC2
GND1 GND2 GND3
0.1 µF

1 Optional: Centertap capacitor may improve EMC depending on board layout and system design.

2 Additional magnetics and switching logic (not shown) are required to implement the dual network solution.

3.4 Simple 10BASE-T Connection

Figure 10 shows a simple 10BASE-T application using an LXT905 transceiver and a Motorola
MC68EN360. The MC68EN360 is compatible with Mode 1 (MD0 and MD1 both Low).

20 Datasheet
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 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

Figure 10. LXT905/MC68EN360 Interface for Full-Duplex 10BASE-T (Mode 1)

20 MHz
MC68EN360 System CLKI CLKO Not Connected
Clock
RJ-45
CLK1-4 RCLK
1 1:1 16
CLK1-4 TCLK TPIN 6

Twisted-Pair Network
TXD TXD
5
100 Ω

To 10 Base-T
RXD RXD
SCC1

RTS TEN 4

LXT905
3 14
CD CD TPIP 3
CTS COL 6 1:2 11
TPON 2
LBK
11.8 Ω 1%
DSQE 1
Parallel +5V
I/O 11.8 Ω 1%
10 kΩ 1 8 9
TPOP
LEDC/FDE
100 pF

+5V MD0
100 pF
MD1
300 Ω

Green
LEDL

+5V VCC1
7.5 kΩ 1%
VCC2
RBIAS
LI
GND1 GND2 GND3
0.1 µF

1 LEDC/FDE requires an open-collector driver.

Datasheet 21
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LXT905 — Universal 10BASE-T Transceiver with 3.3V Support

4.0 Test Specifications

Note: The minimum and maximum values in Table 5 through Table 13 on page 25 and Figure 11 on
page 26 through Figure 26 on page 33 represent the performance specifications of the LXT905 and
are guaranteed by test, except where noted by design. Minimum and maximum values in Table 7
through Table 13 on page 25 apply over the recommended operating conditions specified in
Table 6.

For all Quality and Reliability issues (for example, parts packaging and thermal specifications),
please send your questions to Intel at the following e-mail address: [email protected].

Table 5. Absolute Maximum Values

Parameter Symbol Min Max Units

Supply voltage VCC -0.3 +6 V

Storage temperature TST -65 +150 ºC

Caution: Exceeding these values may cause permanent damage. Functional operation
under these conditions is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.

Table 6. Recommended Operating Conditions

Parameter Symbol Min Typ Max Units

Recommended supply voltage1 VCC 3.135 5.0 5.25 V

Recommended operating temperature (Commercial) TOP 0 – +70 ºC
Recommended operating temperature (Extended) TOP -40 – +85 ºC
1. Voltage is with respect to ground unless specified otherwise.

Table 7. I/O Electrical Characteristics

Parameter Sym Min Typ1 Max Units Test Conditions
2
Input low voltage VIL – – 0.8 V
2
Input high voltage VIH 2.0 – – V
VOL – – 0.4 V IOL = 1.6 mA
Output low voltage
VOL – – 10 %VCC IOL < 10 µA
Output low voltage
VOLL – – 0.7 %VCC IOLL = 10 mA
(Open drain LED driver)
VOH 2.4 – – V IOH = 40 µA
Output high voltage
VOH 90 – – %VCC IOH < 10 µA
Output rise CMOS – – 3 15 ns CLOAD = 20 pF
time
TCLK & RCLK TTL – – 2 15 ns

1. Typical values are at 25 °C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed
at levels of 0V and 3V. This applies to all inputs except TPIP and TPIN.

22 Datasheet
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 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

Table 7. I/O Electrical Characteristics (Continued)

Parameter Sym Min Typ1 Max Units Test Conditions

Output fall CMOS – – 3 15 ns CLOAD= 20 pF

time
TCLK & RCLK TTL – – 2 15 ns

CLKI rise time (externally driven) – – – 10 ns

CLKI duty cycle (externally
– – 50/50 40/60 %
driven)
ICC – 40 80 mA Idle Mode
Normal Mode
ICC – 70 100 mA Transmitting on TP
Supply current
Power Down µA
ICC – 0.01 1
Mode
1. Typical values are at 25 °C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed
at levels of 0V and 3V. This applies to all inputs except TPIP and TPIN.

Table 8. TP Electrical Characteristics

Parameter Symbol Min Typ1 Max Units Test Conditions

Transmit output impedance ZOUT – 5 – Ω –

0 line length for internal
Transmit timing jitter addition2 – – ±6.4 ±10 ns
MAU
After line model
Transmit timing jitter added by specified by IEEE 802.3
– – ±3.5 ±5.5 ns
the MAU and PLS sections2, 3 for 10BASE-T internal
MAU
Receive input impedance ZIN – 24 – kΩ Between TPIP/TPIN
5 MHz square wave
Differential squelch threshold VDS 300 420 585 mV
input
1. Typical values are at 25 °C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Parameter is guaranteed by design; not subject to production testing.
3. IEEE 802.3 specifies maximum jitter additions at 0.5 ns from the encoder, and 3.5 ns from the MAU.

Table 9. Switching Characteristics

Parameter Symbol Minimum Typical1 Maximum Units

Maximum transmit time – 20 – 150 ms

Jabber Timing
Unjab time – 250 – 750 ms
Time link loss receive – 50 – 150 ms

Link Integrity Link min receive – 2 – 7 ms

Timing Link max receive – 50 – 150 ms
Link transmit period – 8 10 24 ms
1. Typical values are at 25 °C and are for design aid only, are not guaranteed, and are not subject to
production testing.

Datasheet 23
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LXT905 — Universal 10BASE-T Transceiver with 3.3V Support

Table 10. RCLK/Start-of-Frame Timing

Parameter Symbol Min Typ1 Max Units

Decoder acquisition time tDATA – 1300 1500 ns

CD turn-on delay tCD – 400 550 ns

Receive data setup from Mode 1 tRDS 60 70 – ns

RCLK Modes 2, 3, and 4 tRDS 30 45 – ns
Mode 1 tRDH 10 20 – ns
Receive data hold from RCLK
Modes 2, 3, and 4 tRDH 30 45 – ns
RCLK shut off delay from CD assert (Mode 3) tsws – ±100 – ns
1. Typical values are at 25 °C and are for design aid only, are not guaranteed, and are not subject to
production testing.

Table 11. RCLK/End-of-Frame Timing

Parameter Type Sym Mode 1 Mode 2 Mode 3 Mode 4 Units

RCLK after CD off Min tRC 5 1 – 5 BT

Rcv data through-put delay Max tRD 400 375 375 375 ns
2
CD turn-off delay Max tCDOFF 500 475 475 475 ns
Receive block out after TEN off 3 Typical1 tIFG 5 50 – – BT
RCLK switching delay after CD
Typical1 tswe – – 120 (±80) – ns
off
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production
testing.
2. CD Turnoff delay measured from middle of last bit: timing specification is unaffected by the value of the last
bit.
3. Blocking of Carrier Detect is disabled during full-duplex operation.

Table 12. Transmit Timing

Parameter Symbol Minimum Typical1 Maximum Units

TEN setup from TCLK tEHCH 22 – – ns

TXD setup from TCLK tDSCH 22 – – ns
TEN hold after TCLK tCHEL 5 – – ns
TXD hold after TCLK tCHDU 5 – – ns
Transmit start-up delay tSTUD – 350 450 ns
Transmit through-put delay tTPD – 338 350 ns
1. Typical values are at 25 °C and are for design aid only, are not guaranteed, and are not subject to
production testing.

24 Datasheet
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 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

Table 13. Miscellaneous Timing

Parameter Symbol Minimum Typical1 Maximum Units

COL (SQE) Delay after TEN off 2 tSQED 0.65 – 1.6 µs

COL (SQE) Pulse Duration2 tSQEP 500 – 1500 ns
Power Down recovery time tPDR – 25 – ms
1. Typical values are at 25 °C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. When SQE is enabled (DSQE is Low).

Datasheet 25
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LXT905 — Universal 10BASE-T Transceiver with 3.3V Support

4.1 Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low)

Figures 11 - 14

Figure 11. Mode 1 RCLK/Start-of-Frame Timing

1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0

TPIP/TPIN

tCD

CD

RCLK

tRDS
tRDH
tDATA
RXD

1 0 1 0 1 0 1 0 1 1 1 0 1

Figure 12. Mode 1 RCLK/End-of-Frame Timing

1 0 1 0 1 0 1 0 0

TPIP/TPIN

tCDOFF
CD
tRD
tRC

RCLK

RXD

1 0 1 0 1 0 1 0 0

26 Datasheet
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 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

Figure 13. Mode 1 Transmit Timing

TEN
tEHCH tCHEL

TCLK

tDSCH
tCHDU

TXD

tSTUD tTPD
TPO

Figure 14. Mode 1 COL Output Timing

TEN
tSQED

COL
tSQEP

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LXT905 — Universal 10BASE-T Transceiver with 3.3V Support

4.2 Timing Diagrams for Mode 2 (MD1 = Low, MD0 = High)

Figures 15 - 18

Figure 15. Mode 2 RCLK/Start-of-Frame

1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0
TPIP/TPIN

CD tCD

RCLK

tRDS
tRDH
tDATA
RXD

1 0 1 0 1 0 1 0 1 1 1 0 1
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.

Figure 16. Mode 2 RCLK/End-of-Frame Timing

1 0 1 0 1 0 1 0 0
TPIP/TPIN

CD tCDOFF

tRD

RCLK

RXD

1 0 1 0 1 0 1 0 0
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.

28 Datasheet
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 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

Figure 17. Mode 2 Transmit Timing

TEN

tEHCH tCHEL

TCLK

tDSCH
tCHDU

TXD

tSTUD tTPD
TPO

Figure 18. Mode 2 COL Output Timing

TEN tIFG
tSQED

COL
tSQEP

NOTE:
1. CD output is disabled for a maximum of 55 bit times after TEN turns off.

Datasheet 29
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LXT905 — Universal 10BASE-T Transceiver with 3.3V Support

4.3 Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low)

Figures 19 - 22

Figure 19. Mode 3 RCLK/Start-of-Frame Timing

1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1

TPIP/TPIN

tCD
CD
tSWS Recovered from Input Data Stream

RCLK

Generated from TCLK tRDS

tRDH
tDATA
RXD

1 0 1 0 1 0 1 0 1 1 1 0 1

NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.

Figure 20. Mode 3 RCLK/End-of-Frame Timing

1 0 1 0 1 0 1 0 0
TPIP/TPIN

tCDOFF
CD
tRD
tSWE
RCLK

Recovered Clock Generated from TCLK

RXD

1 0 1 0 1 0 1 0 0
NOTE:
1. RSD changes at the rising edge of RCLK. The controller is sampled at the falling edge.

30 Datasheet
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 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

Figure 21. Mode 3 Transmit Timing

TEN
tCHEL
tEHCH

TCLK

tDSCH tCHDU

TXD

tSTUD
tTPD
TPO

Figure 22. Mode 3 COL Output Timing

TEN
tSQED tSQEP

COL

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LXT905 — Universal 10BASE-T Transceiver with 3.3V Support

4.4 Timing Diagrams for Mode 4 (MD1 = High, MD0 = High)

Figures 23 - 26

Figure 23. Mode 4 RCLK/Start-of-Frame Timing

1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1
TPIP/TPIN

tCD
CRS

RCLK
tRDS
tDATA tRDH

RXD

1 0 1 0 1 0 1 0 1 1 1 0 1

NOTE:
1. RXD changes at the falling edge of RCLK. The controller is sampled at the rising edge.

Figure 24. Mode 4 RCLK/End-of-Frame Timing

1 0 1 0 1 0 1 0 0

TPIP/TPIN

tCDOFF
CD
tRD

RCLK

RXD

1 0 1 0 1 0 1 0 0
OTE:
1. RXD changes at the falling edge of RCLK. The controller is sampled at the rising edge.

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 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

Figure 25. Mode 4 Transmit Timing

TEN
tEHCH tCHEL

TCLK

tDSCH tCHDU

TXD

tTPD
tSTUD

TPO

Figure 26. Mode 4 COL Output Timing

TEN
tSQED

COL
tSQEP

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LXT905 — Universal 10BASE-T Transceiver with 3.3V Support

5.0 Mechanical Specifications

Figure 27. LXT905PC Package Specifications

28-Pin PLCC
• Part Number LXT905PC (Commercial Temperature Range)
• Part Number LXT905PE (Extended Temperature Range)

Table 14. PLASTIC LEADED CHIP CARRIER

Inches Millimeters
Dim
Min Max Min Max

A 0.165 0.180 4.191 4.572

A1 0.090 0.120 2.286 3.048
A2 0.062 0.083 1.575 2.108
B 0.050 – 1.270 –
C 0.026 0.032 0.660 0.813
D 0.485 0.495 12.319 12.573
D1 0.450 0.456 11.430 11.582
F 0.013 0.021 0.330 0.533

34 Datasheet
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 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

Figure 28. LXT905LC Package Specifications

32-Pin LQFP
• Part Number LXT905LC (Commercial Temperature Range)
• Part Number LXT905LE (Extended Temperature Range)
D
D1

E1 E
e/
2

o
11/13 8 PLACES
o
0 MIN.

-H- 0.08/0.20 R.
A A2
o
0-7
-C-

A1 b M L
0.20 MIN.
All Dimensions in millimeters 0.08 R. MIN.
1.00 REF.

Table 15. QUAD FLAT PACKAGE NOTES:

1. All dimensions are in millimeters.
All Dimensions in millimeters 2. This package conforms to JEDEC publication 95
Dim. registration MO-136, variation BC.
Min. Typ. Max. Notes 3. Datum plane -H- located at mold parting line and is
coincident with leads where leads exit plastic body at
A --- --- 1.60 bottom of parting line.
4. Measured at seating plane -C-.
A1 0.05 0.10 0.15 5. Measured at datum plane -H-.
6. Dimensions D1 and E1 do not include mold protrusion.
A2 1.35 1.40 1.4
Allowable mold protrusion is 0.254 mm.
D 9.00 BSC. 5 7. Package top dimensions are smaller than bottom
dimensions. Top of package will not overhang bottom of
D1 7.00 BSC. 6, 7, 8 package.
8. Dimension b does not include dambar protrusion.
E 9.00 BSC 5
Allowable dambar protrusion is no more than 0.08 mm.
E1 7.00 BSC 6, 7, 8
L 0.45 0.60 0.75
M 0.15 --- ---
b 0.30 0.37 0.45 9
e 0.80 BSC.

Datasheet 35
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 Universal 10BASE-T Transceiver with 3.3V Support — LXT905

Appendix A Ordering Information

Table 16. Product Information

Number Revision Qualification Tray MM Tape & Reel MM

DJLXT905LC.C2 C2 S 831645 831804

NLXT905PC.C2 C2 S 831661 831817
DJLXT905LE.C2 C2 S 831646 831805
NLXT905PE.C2 C2 S 831662 831818

Figure 29. Ordering Information - Sample

DJ LXT 905 L C C2 S E001

Build Format
E000 = Tray
E001 = Tape and reel
Qualification
Q = Pre-production material
S = Production material

Product Revision
xn = 2 Alphanumeric characters

Temperature Range
A = Ambient (0 - 55° C)
C = Commercial (0 - 70° C)
E = Extended (-40 - +85° C)
Internal Package Designator
L = LQFP
P = PLCC
N = DIP
Q = PQFP
H = QFP with heat spreader
T = TQFP
B = BGA
E = TBGA
K = HSBGA (BGA with heat slug)

xxxx = 3-5 Digit Alphanumeric Product Code

IXA Product Prefix
LXT = PHY layer device
IXE = Switching engine
IXF = Formatting device (MAC)
IXP = Network processor

Intel Package Designator

DJ = LQFP
FA = TQFP
FL = PBGA (<1.0 mm pitch)
FW = PBGA (1.27 mm pitch)
HB = QFP with heat spreader
HD = QFP with heat slug
HG = SOIC
S = QFP
GC = TBGA
N = PLCC

Datasheet 37
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