2

OUTLINE OF CHAPTER 5

Sequential Latches Flip-flop Analysis of State Reduction

Circuits Clocked and Assignment
Sequential Circuits

Design Procedure

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

5.1 SEQUENTIAL
CIRCUITS
 4

SEQUENTIAL CIRCUITS
• Every digital system is likely to have combinational circuits.

• Most systems encountered in practice also include storage

elements, which require that the system be described in terms
of sequential logic.

Inputs Outputs
Combinational
Circuit
Memory
Elements

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

 5

SEQUENTIAL CIRCUITS
• The storage elements are devices capable of storing binary
information.
• The binary information stored in these elements at any given
time defines the state of the sequential circuit at that time.
• The sequential circuit receives binary information from external
inputs.
• These inputs, together with the present state of the storage
elements, determine the binary value of the outputs.

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

 6

SEQUENTIAL CIRCUITS
• They also determine the condition for changing the state in the
storage elements.

• A sequential circuit is specified by a time sequence of inputs,

output, and internal states.

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

 7

SEQUENTIAL CIRCUITS
• There are two main types of sequential circuits.

• Their classification depends on the timing of their signals.

Synchronous Asynchronous

Sequential
Circuit

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

 8

SEQUENTIAL CIRCUITS
• Asynchronous Sequential Circuit

Inputs Outputs
Combinational
Circuit
Memory
Elements

– The behaviour of the circuit depends upon the input signals at any
instant of time and the order in which the inputs change.

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

 9

SEQUENTIAL CIRCUITS
• Asynchronous Sequential Circuit
– In gate – type asynchronous systems, the storage elements consist
of logic gates whose propagation delay provides the required
storage.

– Thus, an asynchronous sequential circuit may be regarded as a

combinational circuit with feedback.

– Because of the feedback among logic gates, an asynchronous

sequential circuit may become unstable at times.

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

 10

SEQUENTIAL CIRCUITS
• Synchronous Sequential Circuit

Inputs Outputs
Combinational
Circuit
Flip-flops
Clock

– The behaviour can be defined from the knowledge of its signals at

discrete instants of time.

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

 11

SEQUENTIAL CIRCUITS
• Synchronous Sequential Circuit
– Employs signals that affect the storage elements only at discrete
instants of time.

– Synchronisation is achieved by a timing device called a clock

generator.
• Provides a periodic train of clock pulses.

• Clock pulses are distributed throughout the system in such a way that
storage elements are affected only with the arrival of each pulse.

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

 12

SEQUENTIAL CIRCUITS
• Synchronous Sequential Circuit
• In practice, the clock pulses are applied with other signals that specify
the required change in the storage elements.

– Circuits that use clock pulses in the inputs of storage elements are
called clocked sequential circuits.
– The storage elements used in clocked sequential circuits are called
flip – flops.
– A flip – flop is a binary storage device capable of storing one bit of
information.

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

5.2 LATCHES
 14

L ATC H E S
• Latches are the basic circuits from which all flip – flops are
constructed.

• Although latches are useful for storing binary information and

for the design of asynchronous sequential circuits.

• They are not practical for use in synchronous sequential circuits.

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

 15

L ATC H E S
• SR Latch
S R Q Q’

1 0 1 0 Set State
Reset (R) 1
0 0
1
Q Hold
0 0 1 0 State

0 1 Reset
0 1
State

Set (S) 1 Q 0 0 0 1
Hold

0 0 State

Invalid
1 1 0 0
State

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

 16

L ATC H E S
• SR Latch
S R Q
R Q 0 0 Q0 No change
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S Q S R Q
0 0 Q=Q’=1 Invalid
0 1 1 Set
R Q 1 0 0 Reset
1 1 Q0 No change
23 December, 2016 INTRODUCTION TO LOGIC DESIGN
 17

L ATC H E S
• SR Latch with Control Input
R R S S
Q Q

C C
R Q
S Q R
S
C S R Q
0 X X HOLD No change
1 0 0 HOLD No change
1 0 1 Q=0 Reset

1 1 0 Q=1 Set

1 1 1 Q = Q’ Invalid

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

 18

L ATC H E S
• D Latch (D = Data)
– One way to eliminate the undesirable condition of the indeterminate
state in the SR latch is to ensure that inputs S and R are never equal
to 1 at the same time.

– D latch has two inputs

• D (data) - directly goes to the S input and its complement is applied to
the R input.

• C (control)

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

 19

L ATC H E S
Timing Diagram
• D Latch (D = Data)
D S C
Q
C D
R Q
Q

C D Q t
0 X HOLD No change
1 0 Q=0 Reset Output may
1 1 Q=1 Set change

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

 20

L ATC H E S
Timing Diagram
• D Latch (D = Data)
D S C
Q
C D
R Q
Q

C D Q
0 X HOLD No change
Output may
1 0 Q=0 Reset
change
1 1 Q=1 Set

23 December, 2016 INTRODUCTION TO LOGIC DESIGN

 21

L ATC H E S
• D Latch (D = Data)
– The D latch has an ability to hold data in its internal storage.

– It is suited for use as a temporary storage for binary information.

– This circuit is often called transparent latch.

• The output follow changes in the data input as long as the control input
is enabled.

23 December, 2016 INTRODUCTION TO LOGIC DESIGN