Department Of

Electronics and Communication Engineering

BONAFIDE CERTIFICATE

Name:
Branch:
Section:
Year:
Semester:
Register Number:

Certified that this is a bonafied Record of work done by the above

student in the CS3351 Digital Principles and Computer
Organization Laboratory During the academic Year 2023 - 2024

Faculty In-Chrage Head of the Deparment

Submitted to the Anna University Practical Examination Held at
on

Internal Examiner External Examiner

 DO’S and DON’TS in Laboratory

1. Come fully prepared for the experiment in the

laboratory.
2. Check for appropriate power supply before
connecting to the equipment.
3. Decide the appropriate range of the measuring
instruments on the basis of quantity to be measured.
4. Make the connections without connecting the leads
to the supply.
5. Re-check the connections and show it to the
teacher/instructor before switching-on the power
supply to the circuit.
6. Energize the circuit only with the permission of the
teacher/instructor.
7. After the experiment, disconnect the connections and
put back the connecting wires/leads at appropriate
place.
8. Return all the apparatus to the lab-staff.
9. In case of shock, switch-off the power supply
immediately.
10. Strictly follow the procedure given with the
respective experiments.
11. Avoid loose connections.
12. Don’t touch the main power supply leads with bare
hand and avoid body earth.
13. Don’t use the mobile phones during laboratory.
 Syllabus
Practical Exercises:
1. Verification of Boolean theorems using logic gates.
2. Design and implementation of combinational circuits
using gates for arbitrary functions.
3. Implementation of 4-bit binary adder/subtractor
circuits.
4. Implementation of code converters.
5. Implementation of BCD adder, encoder and decoder
circuits.
6. Implementation of functions using Multiplexers.
7. Implementation of the synchronous counters.
8. Implementation of a Universal Shift register.
9. Simulator based study of Computer Architecture.
 Index
Exp. Page Mark
Date Name of the Experiment Signature
No. No. Obtained
1a. Study of Logic Gates 01
Verification of Boolean
1b. 07
Theorems using Logic Gates
Design and implementation
of Combinational Circuits
2. 15
using Gates for Arbitrary
Functions
Implementation of 4-bit
3. Binary Adder/Subtractor 23
Circuits
Implementation of Code
4a. Converters-Binary to Gray 29
Code Converter
Implementation of Code
4b. Converters-Gray to binary 33
Code Converter
Implementation of Code
Converters-BCD to Excess-3
4c. 33
Code Converter & Excess-3
to BCD Code converter
Implementation of BCD
5a. 39
Adder
Implementation of Encoder
5b. 45
and Decoder
Implementation of Functions
6. 49
using Multiplexers
Implementation of the
7. 53
Synchronous Counters
Implementation of a
8. 57
Universal Shift Register.
Simulation Based Study of
9. 63
Computer Architecture
Total (50)

Signature of the Faculty Member

 Exp. No.: 1a Date: Page No.: 01
Exp. Name: Study of Logic Gates
Aim: To study about logic gates and verify their truth tables.
Apparatus Sl.
Required: Components Specification Quantity
No.
1. NOT Gate IC 7404 1
2. OR Gate IC 7432 1
3. AND Gate IC 7408 1
4. EX-OR Gate IC 7486 1
5. NAND Gate IC 7400 1
6. NOR Gate IC 7402 1
8. IC Trainer Kit - 1
9. Patch Cord - As Required
Theory: A logic gate performs a logical operation on one or more logic
inputs and produces a single logic output. The logic is normally
performed as Boolean logic and is most commonly found in
digital circuits. OR, AND and NOT are basic gates. NAND, NOR
and X-OR are known as universal gates.
The different types of logic gates are:
 NOT gate
 OR gate
 AND gate
 EX-OR gate
 NAND gate
 NOR gate
 Inverter or NOT Gate:
The inverter is a logic gate which has only one input & one
output. In inverter a low input produces a high output and a
high input produces a low output.
a. Logic Equation is: Y = 𝐴̅
b. Digital IC for NOT: IC 7404

 OR Gate:
An OR gate is a logic gate which can have two or more inputs
and a single output. The output of an OR gate is high if any of
the inputs or all inputs are high. The output is low only if all
the inputs are low.
a. Logic Equation is: Y = A + B
b. Digital IC for OR: IC 7432

 AND Gate:
AND gate is a logic gate which can have two or more inputs.
But there is only one output. The output of AND gate is high
only if all inputs are high. Even if one input is low, the output
will be low.
a. Logic equation is: Y = AB
b. Digital IC for AND: IC 7408
 EX-OR Gate:
In EX-OR gate if either of the inputs is high, output will be
high. If both the inputs are high output will be low. If both
inputs are low then also output will be low.
a. Logic equation is: Y = AB+ BA= A B
b. Digital IC for EX-OR: IC 7486

 NAND Gate:
NAND gate is a combination of AND & NOT gates. Thus NAND
gate is the inverse of AND gate. The output is low when all
inputs are high. The output is high for all the remaining
combinations.
a. Logic equation is: Y = 𝐴̅𝐵
b. Digital IC for NAND: IC 7400

 NOR Gate:
NOR gate is a combination of OR & NOT gates. Thus NOR gate
is the inverse of OR gate. When all or either of the inputs are
high output is low. The output of NOR gate is high only when
all inputs are low.
a. Logic equation is: Y = 𝐴̅
𝐵
+
b. Digital IC for NOR: IC 7402
 Circuit 1. NOT Gate (IC 7404) 2. OR Gate (IC 7432)
Diagram:

Figure 1.1: NOT Gate (IC 7404) Figure 1.2: OR Gate (IC 7432)
3. AND Gate (IC 7408) 4. EX-OR Gate (IC 7486)

Figure 1.3: AND Gate (IC 7408) Figure 1.4: Ex-OR Gate (IC 7486)
5. NAND Gate (IC 7400) 6. NOR Gate (IC 7402)

Figure 1.5: NAND Gate (IC 7400) Figure 1.6: NAND Gate (IC 7402)
Symbol &
Truth Table:
Verification: 1. NOT Gate (IC 7404) 2. OR Gate (IC 7432)
Input Output Input Output
A Y = 𝐴̅ A B Y= A+B
0 1 0 0 0
1 0 0 1 1
1 0 1
1 1 1
3. AND Gate (IC 7408) 4. EX-OR Gate (IC 7486)
Input Output Input Output
A B Y = AB A B Y=A B
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 0
5. NAND Gate (IC 7400) 6. NOR Gate (IC 7402)
Input Output Input Output
A B Y = 𝐴̅𝐵 A B Y = 𝐴̅
+
𝐵
0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0
Procedure: Step 1: Connect the NOT gate using digital IC‟s as shown in the
figure 1.1 to 1.6.
Step 2: Use +5V for logic 1 and 0V for logic 0.
Step 3: Feed the logic signals 0 or 1 from the logic input
switches at the inputs A & B.
Step 4: Monitor the output using LED indicators and verify its
truth table.
Step 5: Repeat step l to 4 for all the remaining gates.
Result: The logic gates are studied and its truth tables are verified.

Marks Marks
Description
Signature of the Alloted Obtained
Faculty Member: Performance 25
Record 15
Viva-Voce 10
Date: Total 50
 Viva  Why NAND & NOR gates are called universal gates?
Questions:  Realize the EXOR gate using minimum number of NAND
gates.
 Give the truth table for EX-NOR (EX-OR+NOT) and realize
using NAND gates.
 Explain the operation of NAND gate when realized using
discrete components.
 What are the logic low and High levels of TTL IC‟s and CMOS
IC‟s.
 Compare TTL logic family with CMOS family.
 Which logic family is called fastest and which logic family is
called low power dissipated.
 Explain the operation of OR, NOR gates when realized using
discrete Components.
 Why the transistor operates as NOT gate.
 What is fan-in and fan-out?
 Why this IC series starts with 74XX.
References:  https://vikramlearning.com/jntuh/notes/pulse-and-digital-
circuits-lab/study-of-logic-gates/35
 https://www.semiconductorforu.com/7400-series-integrated-
circuits/
 https://www.etechnog.com/2023/04/different-types-of-logic-
gates-with.html
Rough Work
 Exp. No.: 1b Date: Page No.: 07
Exp. Name: Verification of Boolean Theorems using Logic Gates
To verify the truth table of basic Boolean algebraic laws by using
Aim:
Basic gates.
Apparatus Sl.
Required: Components Specification Quantity
No.
1. NOT Gate IC 7404 1
2. OR Gate IC 7432 1
3. AND Gate IC 7408 1
4. EX-OR Gate IC 7486 1
5. NAND Gate IC 7400 1
6. NOR Gate IC 7402 1
4. IC Trainer kit - 1
5. Patch Cord - As Required

Theory:  Boolean Algebra is a form of mathematical algebra that is used

in digital logic in digital electronics. Albebra consists of
symbolic representation of a statement (generally mathematical
statements). Similarly, there are expressions, equations and
functions in Boolean algebra as well.
 The main aim of any logic design is to simplify the logic as
much as possible so that the final implementation will become
easy. In order to simplify the logic, the Boolean equations and
expressions representing that logic must be simplified.
 So, to simplify the Boolean equations and expression, there are
some laws and theorems proposed. Using these laws and
theorems, it becomes very easy to simplify or reduce the logical
complexities of any Boolean expression or function.
Basic Laws and Proofs:
The basic rules and laws of Boolean algebraic system are known
as “Laws of Boolean algebra”. Some of the basic laws (rules) of
the Boolean algebra are:
(i) Associative law
(ii) Distributive law
(iii) Commutative law
(iv) Absorption law
(v) De Morgan‟s Theorem

(i) Associative Law:

1. Associate Law of Addition
Statement:
 Associative law of addition states that OR ing more than two
variables i.e. mathematical addition operation performed on
variables will return the same value irrespective of the
grouping of variables in an equation.
 It involves in swapping of variables in groups.
 The Associative law using OR operator can be written as
A+(B+C) = (A+B)+C
Proof:
 If A, B and C are three variables, then the grouping of 3
variables with 2 variables in each set will be of 3 types,
such as (A + B), (B + C) and(C + A).
 According to associative law
(A + B + C) = (A + B) +C = A + (B + C) = B + (C + A)
 We know that, A + AB = A (according to Absorption law)
 Now let‟s assume that, x = A + (B + C) and y = (A + B) + C
 According to associative law, we need to prove that x = y.
 Now, find Ax = A [ A + (B + C)
= AA +A (B + C)
= A + AB + AC → since AA = A
= (A+ AB) + AC
= A + AC → since A + AB = A
= A → since A + AC = A
Therefore Ax = A
 Similarly, for Bx = B [ A + (B + C) ]
= AB +B (B + C)
= AB + BB + BC
= AB + B + BC → since BB = B
= (B+ BC) + AB
= B + AB → since B + BC = B
= B → since B + AB = B
 Using these above equations, we can say that the relation
between A, B, C and + operator doesn‟t change when
multiplied by other variable like x, such as xy = yx = x = y.
yx = ((A + B) + C) x
= (A + B) x + Cx
= (Ax + Bx) + Cx
= (A + B) + C
= y xy = (A + (B + C)) y
= Ay + (B + C) y
= Ay + (By + Cy)
= A + (B + C)
=x
 So x = y, which means A + (B + C) = (A + B) + C = B + (A +C)
Example:
 Take three variables 0, 1 and 0, then
 According to associative law,
(0 + 1) + 0 = 0 + (1 + 0)
1+0=0+1
1=1
 Hence associative law is verified.
 Hence the Associative law is proved,
(A + B + C) = (A + B) +C = A + (B + C) = B + (C + A)

2. Associate Law of Multiplication

Statement:
 Associative law of multiplication states that ANDing more
than two variables i.e. mathematical multiplication
operation performed on variables will return the same value
 irrespective of the grouping of variables in an equation.
 The Associative law using AND operator can be written as
A * (B * C) = (A * B) * C

(ii) Distributive Law

 This is the most used and most important law in Boolean
algebra, which involves in 2 operators: AND, OR.
 The addition of two variables and multiplying the result
with a variable will result in same value as addition of
multiplication of the variable with individual variables.
 In other words, ORing two variables and ANDing the result
with another variable is equal to OR of ANDing of the
variable with the two individual variables.
 Distributive law can be written as
A (B+C) = (A B) + (A C)
 This is called AND distributes over OR.
Proof:
A (B + C) = A (B*1) + A (C*1) → since 1 * B = B, 1 * C = C
= [(AB)*(A*1)] + [(AC) *(A*1)]
= [(AB) * A] + [(AC) *A]
= (A +1) (AB + AC)
= (AB +AC) → since 1 + A = 1
 Hence, distributive law is proved.
Example:
 Take three variables 0, 1 and 0, then
 According to distributive law,
0 (1 + 0) = (0*1) + (0*0)
0 (1) = (0) + (0)
0=0
 Hence,distributive law is verified.

(iii) Commutative Law:

Statement:
 Commutative law states that the inter-changing of the order
of operands in a Boolean equation does not change its
result.
 Using OR operator → A + B = B + A
 Using AND operator → A * B = B * A
 This law is also has more priority in Boolean algebra.
Example:
 Take 2 variables 1 and 0, then
1+0=0+1
1=1
Similarly,
1*0=0*1
0=0
(vi) Absorption Law:
 Absorption law involves in linking of a pair of binary
operations.
(i) A+AB = A
(ii) A(A+B) = A
Statement 1: (A + AB = A)
Proof:
A + AB = A.1 + AB → since A.1 = A
=A(1+B) → since 1 + B = 1
= A.1
=A

Statement 2: (A (A + B) = A)
Proof:
A (A + B) = A.A + A.B
= A+AB → since A . A = A
= A (1 + B)
= A.1
=A

(v) De Morgan’s Theorem:

 Boolean algebra involves in binary addition, binary
subtraction, binary division and binary multiplication of
binary numbers. Similar to these basic laws, there is
another important theorem in which the Boolean algebraic
system mostly depends on. That is De Morgan‟s law.
 This can be also known as De Morgan‟s theorem. This law
works depending of the concept of Duality. Duality means
interchanging the operators and variables in a function,
such as replacing 0 with 1 and 1 with 0,AND operator with
OR operator and OR operator with AND operator.
 De Morgan‟s law is like extension of the Duality principle.
De Morgan proposed 2 theorems, which will help us in
solving the algebraic problems in digital electronics.
 The De Morgan‟s statements are,
Statement 1:
 The negation of conjunction is the disjunction of the
negations. Or we can define that as “The compliment of the
product of 2 variables is equal to the sum of the
compliments of individual variables.
(A.B)‟ = A‟ + B‟
Statement 2:
 The negation of disjunction is the conjunction of the
negations. Or we can define that as “The compliment of the
sum of two variables is equal to the product of the
compliment of each variable”.
(A + B)‟ = A‟.B‟
 Circuit 1. Associative Law
Diagram: A+(B+C) = (A+B)+C A.(B.C) = (A.B).C

Figure 2.1: Associative Law of Figure 2.2: Associative Law of

Addition Multiplication
2. Distributive Law
A.(B+C) = A.B + A.C

Figure 2.3: Distributive Law

3. Commutative Law
A+B = B+A A.B = B.A

Figure 2.4: Commutative Law of Figure 2.5: Commutative Law of

Addition Multiplication
4. Absorption Law
A+A.B = A A.(A+B) = A

Figure 2.6: Absorption Law- Figure 2.7: Absorption Law-

Statement 1 Statement 2
5. De Morgan’s Theorem
(A.B)’ = A’ + B’ (A + B)’ = A’.B’

Figure 2.8: De Morgan‟s Theorem-1 Figure 2.9: De Morgan‟s Theorem-2

Truth Table: 1. Associative Law of Addition (A+(B+C) = (A+B)+C)
A B C (A+B) (A+B)+C (B+C) A+(B+C)
0 0 0 0 0 0 0
0 0 1 0 1 1 1
0 1 0 1 1 1 1
0 1 1 1 1 1 1
1 0 0 1 1 0 1
1 0 1 1 1 1 1
1 1 0 1 1 1 1
1 1 1 1 1 1 1
 2. Associative Law of Multiplication (A.(B.C) = (A.B).C)
A B C (A*B) (A*B)*C (B*C) A*(B*C)
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 0 1 0
1 0 0 0 0 0 0
1 0 1 0 0 0 0
1 1 0 1 0 0 0
1 1 1 1 1 1 0
3. Distributive Law (A.(B+C) = A.B+A.C)
A B C (B+C) A.(B+C) (A.B) (A.C) (A.B+A.C)
0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1
04. Commutative Law
Addition (A+B = B+A) Multiplication (A.B = B.A)
A B (A+B) (B+A) A B (A.B) (B.A)
0 0 0 0 0 0 0 0
0 1 1 1 0 1 0 0
1 0 1 1 1 0 0 0
1 1 1 1 1 1 1 1
5. Absorption Law
A+A.B = A A.(A+B) = A
A B (A.B) A A B (A+B) A
0 0 0 0 0 0 0 0
0 1 0 0 0 1 1 0
1 0 0 1 1 0 1 1
1 1 1 1 1 1 1 1
6. De Morgan’s Theorem
(A.B)’ = A’ + B’ (A + B)’ = A’.B’

A B A’ B’ A.B (A.B)’ A’+B’ A B A’ B’ A.B (A.B)’ A’+B’

0 0 1 1 0 1 1 0 0 1 1 0 1 1
0 1 1 0 0 1 1 0 1 1 0 0 1 1
1 0 0 1 0 1 1 1 0 0 1 0 1 1
1 1 0 0 1 0 0 1 1 0 0 1 0 0
 Procedure: Step 1: Connect the digital IC‟s as shown in the figure 2.1.
Step 2: Use +5V for logic 1 and 0V for logic 0.
Step 3: Feed the logic signals 0 or 1 from the logic input
switches at the inputs A & B.
Step 4: Monitor the output using LED indicators and verify its
truth table.
Step 5: Repeat step l to 4 for all the remaining law.
Step 6: Verify the output with the truth table.
Result: Thus the above stated boolean theorems using logic gates are
verified.

Marks Marks
Description
Signature of the Alloted Obtained
Faculty Member: Performance 25
Record 15
Viva-Voce 10
Date: Total 50

Viva  What is Boolean algebra?

Questions:  State the De Morgan's Theorem.
 List the fundamental properties of Boolean algebra.
 What is NAND, NOR, X-OR, and X-NOR operations in Boolean
algebra?
 Name the two forms of Boolean expression.
 What do you mean by an Axim?
 What is associate law?
 In boolean algebra, the OR operation is performed by which
properties?
References:  https://www.electronicshub.org/boolean-algebra-laws-and-
theorems/
 https://www.javatpoint.com/laws-and-rules-of-boolean-
algebra-in-digital-electronics
 https://www.allaboutcircuits.com/technical-articles/boolean-
identities/
Rough Work
 Exp. No.: 2 Date: Page No.: 15
Design and Implementation of Combinational Circuits using
Exp. Name:
Gates for Arbitrary Functions
To design and construct half adder, full adder, half subtractor
Aim: and full subtractor circuits and verify the truth table using logic
gates.
Apparatus
Required: Sl.
Components Specification Quantity
No.
1. NOT Gate IC 7404 1
2. OR Gate IC 7432 1
3. AND Gate IC 7408 1
4. EX-OR Gate IC 7486 1
5. IC Trainer Kit - 1
6. Patch Cord - As Required

Theory: Introduction:
 In digital electronics, adders and subtractors both are the
combinational logic circuits (a combinational logic circuit is
one whose output depends only on the present inputs, but
not on the past outputs) that can add or subtract numbers,
more specifically binary numbers.
 Adders and subtractors are the crucial parts of arithmetic
logic circuits in processing devices like microprocessors or
microcontrollers. In this experiment, we will discuss adders
and subtractors in detail.
(i) Adder:
 We have different types of digital devices like computers,
calculators that can perform a variety of processing
functions like addition, subtraction, multiplication, division,
etc.
 The most basic arithmetic operation that the ALU
(arithmetic logic unit) of a computer performs is the
addition of two or more binary numbers.
 To perform the operation of addition, a combinational logic
circuit, named Adder is used.
 Adders are classified into two types namely:
a. Half Adder
b. Full Adder
 A half-adder is a combinational logic circuit that performs
the addition of only two bits (binary digits).
 Whereas, a full-adder is a combination circuit that performs
three bits (binary digits), where two are the significant bits
and one is a carry from previous execution.
(a) Half-Adder:
 A combinational logic circuit which is designed to add two
binary digits is called as a half adder.
 The half adder provides the output along with a carry value
(if any).
  The half adder circuit is designed by connecting an EX-OR
gate and one AND gate. It has two input terminals and two
output terminals for sum and carry.
 In the case of a half adder, the output of the EX-OR gate is
the sum of two bits and the output of the AND gate is the
carry.
 Although, the carry obtained in one addition will not be
forwarded in the next addition because of this it is known
as half adder.
(b) Full Adder:
 A combinational logic circuit that can add two binary digits
(bits) and a carry bit, and produces a sum bit and a carry
bit as output is known as a full-adder.
 In other words, a combinational circuit which is designed to
add three binary digits and produces two outputs (sum and
carry) is known as a full adder.
 Thus, a full adder circuit adds three binary digits, where
two are the inputs and one is the carry forwarded from the
previous addition.
(ii) Subtractor:
 The subtraction of two binary numbers can be performed by
taking the 1‟s or 2‟s complement of the inputs.
 By this method, the subtraction operation becomes an
addition operation, and thus can be performed by using the
adder circuits.
 This results in the reduction of hardware and cost.
 In the subtraction operation, each subtrahend bit (B) of the
number is subtracted from its corresponding significant
minuend bit (A) to obtain a difference bit.
 Similar to adders, subtractors are also of two types:
a. Half Subtractor
b. Full Subtractor
 Let us discuss the half-subtractor and full-subtractor in
detail.
(i) Half-Subtractor:
 A half-subtractor is a combinational logic circuit that have
two inputs and two outputs (i.e. difference and borrow).
 The half subtractor produces the difference between the two
binary bits at the input and also produces a borrow output
(if any).
 In the subtraction (A-B), A is called as Minuend bit and B is
called as Subtrahend bit.
(ii) Full-Subtractor:
 A full-subtractor is a combinational circuit that has three
inputs A, B, bin and two outputs d and b.
 Where, A is the minuend, B is subtrahend, bin is borrow
produced by the previous stage, d is the difference output
and b is the borrow output.
 Since, the half subtractor can only be used to find the
difference of LSBs (Least Significant Bits) of two binary
numbers.
  Thus, if there is any borrow during the subtraction of the
LSBs, it will affect the subtraction of the next bits of
numbers.
 To overcome this problem of the half subtractor, a full
subtractor is realized.
Note:
 A combinational logic circuit which is designed to add two
binary digits is called as a half adder.
 A combinational logic circuit that can add two binary digits
(bits) and a carry bit, and produces a sum bit and a carry
bit as output is known as a full-adder.
 A half-subtractor is a combinational logic circuit that have
two inputs and two outputs (i.e. difference and borrow).
 A full-subtractor is a combinational circuit that has three
inputs A, B, bin and two outputs d and b.

Aplication:
(a) Adder:
 The ALU of a computer uses half adder to compute the
binary addition operation on two bits.
 Half adder is used to make full adder as a full adder
requires 3 inputs, the third input being an input carry i.e.
we will be able to cascade the carry bit from one adder to
the other.
 Ripple carry adder is possible to create a logical circuit
using multiple full adders to add Nbit numbers.
 Each full adder inputs a C (in), which is the C (out) of the
previous adder. This kind of adder is called RIPPLE CARRY
ADDER, since each carry bit "ripples" to the next full
adder.
(b) Subtractor:
 Half subtractor is used to subtract the least significant
column numbers. For subtractionof multi-digit numbers, it
can be used for the LSB.
 Half subtractor is used to reduce the force of audio or
radio signals.
 It can be used in amplifiers to reduce the sound distortion.
 Half subtractor is used in ALU of processor.
 It can be used to increase and decrease operators and also
calculates the addresses. 
 Logic 1. Half Adder
Diagram: (i) Logic Diagram:

(ii) Truth Table:

Input Output
A B Sum (A’B + AB’) Carry (AB)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
(iii) K-Map Simplification:
Sum (A’B + AB’) Carry (AB)

2. Full Adder
(i) Logic Diagram:

(ii) Truth Table:

Input Output
Sum (A’B’Cin + A’BCin’ + Carry (AB +
A B Bin ACin + BCin)
AB’ Cin’ + ABCin)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
(iii) K-Map Simplification:
Sum (A’B’Cin + A’BCin’ +
Carry (AB + ACin + BCin)
AB’Cin’ + ABCin)

3. Half Subtractor
(i) Logic Diagram:

(ii) Truth Table:

Input Output
A B Difference (A'B+AB') Borrow (A'B)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
(iii) K-Map Simplification:

3. Full Subtractor
(i) Logic Diagram:
 (ii) Truth Table:
Input Output
Difference (A’B’Bin + Borrow
A B Bin A’BBin’ + AB’Bin’ + (A’Bin + A’B
ABBin) + BBin)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
(iii) K-Map Simplification:

Procedure: Step 1: Connect the digital IC‟s as shown in the logic diagrams.
Step 2: Use +5V for logic 1 and 0V for logic 0.
Step 3: Feed the logic signals 0 or 1 from the logic input
switches at the inputs A, B, Cin/Bin.
Step 4: Monitor the output using LED indicators and verify its
truth table.
Step 5: Repeat step l to 4 for the adders and Subtractor.
Step 6: Verify the output with the truth table.
Result: Thus, the half adder, full adder, half subtractor and full
subtractor circuits are designed, constructed and verified the
truth table using logic gates.

Marks Marks
Signature of the Description
Alloted Obtained
Faculty Member: Performance 25
Record 15
Viva-Voce 10
Date: Total 50
 Viva  What are the limitations of the Karnaugh Map?
Questions:  How will you execute a full subtractor from a full adder?
 What are the basic operations in Boolean algebra?
 What is NAND, NOR, X-OR, and X-NOR operations in Boolean
algebra?.
 What do you mean by an Axim?
References: https://www.electronicshub.org/half-adder-and-full-adder-
circuits/
https://www.engineersgarage.com/vhdl-tutorial-11-designing-
half-and-full-subtractor-circuits/
Rough Work
 Exp. No.: 3 Date: Page No.: 23
Exp. Name: Implementation of 4-bit Binary Adder/Subtractor Circuits
To design and implement 4-bit adder and subtractor using basic
Aim:
gates and IC 7483.
Apparatus Sl.
Required: Components Specification Quantity
No.
1. 4-Bit Binary Full Adder IC 7483 1
2. NOT Gate IC 7404 1
3. EX-OR Gate IC 7486 1
4. ic Trainer Kit - 1
5. Patch Cord - As Required
Theory: Introduction:
 IC type 7483 is a 4-bit binary parallel adder.
 It has two 4-bit inputs. Each input consists of 4-bits.
 The input A consists of A4 , A3 , A2 and A1 whereas
input B consists of B4 , B3 , B2 and B1.
 Ithas four sum outputs consisting of S4 , S3 , S2 and S1.
 C0 is the input carry and C4 output carry.
 The Vcc is at pin 5 and GND is at pin 12.
(i) 4-Bit Binary Adder:
 A binary adder is a digital circuit that produces the
arithmetic sum of two binary numbers.
 It can be constructed with full adders connected in
cascade, with the output carry from each full adder
connected to the input carry of next full adder in chain.
 The augends bits of „A‟ and the addend bits of „B‟ are
designated by subscript numbers from right to left, with
subscript 0 denoting the least significant bits.
 The carries are connected in chain through the full adder.
 The input carry to the adder is C0 and it ripples through
the full adder to the output carry C4.
(ii) 4-Bit Binary Subtractor:
 The circuit for subtracting A-B consists of an adder with
inverters, placed between each data input „B‟ and the
corresponding input of full adder. The input carry C0 must
be equal to 1 when performing subtraction.
(iii) 4-Bit Binary Adder/Subtractor:
 The addition and subtraction operation can be combined
into one circuit with one common binary adder.
 The mode input M controls the operation. When M=0, the
circuit is adder circuit. When M=1, it becomes subtractor.
(iv) 4-Bit BCD Adder:
 Consider the arithmetic addition of two decimal digits in
BCD, together with an input carry from a previous stage.
 Since each input digit does not exceed 9, the output sum
cannot be greater than 19, the 1 in the sum being an input
carry.
 The output of two decimal digits must be represented in
BCD and should appear in the form listed in the columns.
 ABCD adder that adds 2 BCD digits and produce a sum
digit in BCD. The 2 decimal digits, together with the input
carry, are first added in the top 4 bit adder to produce the
binary sum.
Diagrams: 1. IC 7483 (4-Bit Binary Adder/Subtractor)
(i) Block Diagram:

(ii) Pin Diagram:

(iii) Logic Diagram (Adder):

(iv) Logic Diagram (Subtractor):

(v) Logic Diagram (Adder/Subtractor):

Truth Tables: 4-Bit Binary Adder/Subtractor

M Input Data A Input Data B Sum Carry

Bit A4 A3 A2 A1 B4 B3 B2 B1 S4 S3 S2 S1 C4
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 1 0 0 1 0 0
0 0 0 1 0 0 0 1 0 0 1 0 0 0
0 0 0 1 1 0 0 1 1 0 1 1 0 0
0 0 1 0 0 0 1 0 0 1 0 0 0 0
0 0 1 0 1 0 1 0 1 1 0 1 0 0
0 0 1 1 0 0 1 1 0 1 1 0 0 0
0 0 1 1 1 0 1 1 1 1 1 1 0 0
M Input Data A Input Data B Difference
Borrow
Bit A4 A3 A2 A1 B4 B3 B2 B1 D4 D3 D2 D1
1 0 0 0 0 0 0 0 0 0 1 0 0 0
1 0 0 0 1 0 0 0 1 0 1 1 0 0
1 0 0 1 0 0 0 1 0 1 0 0 0 0
1 0 0 1 1 0 0 1 1 1 0 1 0 0
1 0 1 0 0 0 1 0 0 1 1 0 0 0
1 0 1 0 1 0 1 0 1 1 1 1 0 0
1 0 1 1 0 0 1 1 0 1 1 1 1 0
Procedure: Step 1: Connect the Digital Logic Trainer to 220V AC power
supply.
Step 2: Turn on the trainer and verify the voltage of the power
supply using the multi-meter. It should be exactly
+5V.
Step 3: Insert the IC 7483 on the trainer‟s breadboard.
Step 4: Develop the circuit according to the figure.
Step 5: Connect A4 , A3 , A2 and A1 of input A to logic
switches and mark them carefully.
Step 6: Connect B4 , B3 , B2 and B1 of input B to logic
switches and mark them carefully.
Step 7: Connect carry in to ground and S4 , S3 , S2 and S1
of output S to LEDs .
Step 8: Connect carry out to the other LED and marks all
outputs.
Step 9: Connect Vcc of all IC‟s to the +5V available in the
trainer.
Step 10: Connect GND of all IC‟s to the ground available in the
trainer.
Step 11: Set the mode select bit for addition/subtraction
operation (M Bit=0 for Addtion and M Bit=1 for
subtraction)
Step 12: Now change the values of inputs A and B, and
observe the output.
 Result: Thus the 4 bit parallel adder/subtractor was implemented and
tested using the IC 7483.

Marks Marks
Description
Alloted Obtained
Signature of the
Faculty Member: Performance 25
Record 15
Viva-Voce 10
Date: Total 50

Viva  Controlled inverter is also known as?

Questions:  Why XOR gate is called an inverter?
 How many basic binary subtraction operations are possible?
 What happen if to a 4-bit parallel adder, if the carry-in is
connected to a logical HIGH?
 How four-bit adder is converted to subtraction?
 What is one disadvantage of the ripple-carry adder?
 What is Manchester carry chain?
 The main disadvantages of Manchester carry chain.
 The summing outputs of a half or full-adder are designated by
which Greek symbol?
 Why is a fast-look-ahead carry circuit used in the 7483 4-bit
full-adder?
 Mention the need of mode select bit in the 4-bit adder/
subtractor.
References:  https://electronics.stackexchange.com/questions/161947/bi
nary-adder-and-parallel-adder
 https://datasheetspdf.com/datasheet/7483.html
 https://holooly.com/solutions/figure-16-7-shows-a-four-bit-
binary-adder-subtractor-circuit-configured-around-a-four-bit-
parallel-binary-adder-type-number-7483-and-a-quad-two-
input-ex-or-gate-type-number-7486-the-arran/
 https://microcontrollerslab.com/74ls83-4-bit-full-adder-
pinout-examples-applications-datasheet/
Rough Work
 Exp. No.: 4a Date: Page No.: 29
Exp. Name: Implementation of Code Converters
To design and implement 4-bit:
Aim: (i) Binary to Gray Code Converter
(ii) Gray to Binary Code Converter
Apparatus Sl.
Required: Components Specification Quantity
No.
1. X-OR GATE IC 7486 1
2. IC Trainer Kit - 1
3. Patch Cord - As Required
Theory:

Introduction:
 The code converter is a combinational circuit i.e., a circuit
whose output depend upon the input of the current time
which performs interconversion between codes of one form
to another. Converters has been used in concepts of digital
electronics and devices like microprocessor or computers.

(i) Binary to Gray Code Converter:

 The logical circuit which converts the binary code to
equivalent gray code is known as binary to gray code
converter.
 The gray code is a non-weighted code.
 The successive gray code differs in one-bit position only
that means it is a unit distance code.
 It is also referred as a cyclic code. It is not suitable for
arithmetic operations.
 It is the most popular of the unit distance codes. It is also
a reflective code.
 An n-bit Gray code can be obtained by reflecting an n-1 bit
code about an axis after 2 n-1 rows and putting the MSB of
0 above the axis and the MSB of 1 below the axis.

(ii) Gray to Binary Code Converter:

 Gray codes are very useful in the normal sequence of
binary numbers generated by the hardware that may cause
an error or ambiguity during the transition from one
number to the next.
 So, the Gray code can eliminate this problem easily since
only one bit changes its value during any transition
between two numbers.
 Gray codes are used in rotary and optical encoders,
Karnaugh maps, and error detection.
 The hamming distance of two neighbours Gray codes is
always 1 and also first Gray code and last Gray code also
has Hamming distance is always 1, so it is also called
Cyclic codes.
 Logic 1. Binary to Gray Code 2. Gray to Binary Code
Diagrams: Converter Converter

Truth Tables: 1. Binary to Gray Code Converter 2. Gray to Binary Code Converter
Binary (Input) Gray (Output) *UD\ (Input) Binary (Output)
B3 B2 B1 B0 G3 G2 G1 G0 G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 1 0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1
1 0 0 0 1 1 0 0 1 0 0 0 1 1 1 1
1 0 0 1 1 1 0 1 1 0 0 1 1 1 1 0
1 0 1 0 1 1 1 1 1 0 1 0 1 1 0 0
1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 1
1 1 0 0 1 0 1 0 1 1 0 0 1 0 0 0
1 1 0 1 1 0 1 1 1 1 0 1 1 0 0 1
1 1 1 0 1 0 0 1 1 1 1 0 1 0 1 1
1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 0
K-Map: 1. Binary to Gray Code Converter
 Procedure: Step 1: Place the IC on IC Trainer Kit.
Step 2: Turn on the trainer and verify the voltage of the power
supply using the multi-meter. It should be exactly
+5V.
Step 3: Implement the circuit as shown in the circuit
diagram.
Step 4: Connect the inputs to the input switches provided in
the IC Trainer Kit.
Step 5: Connect the outputs to the switches of O/P LEDs.
Step 6: Apply various combinations of inputs according to the
truth table and observe the condition of LEDs..
Step 7: Note down the corresponding output readings for
various combinations of inputs.
Step 8: Power Off Trainer Kit, disconnect all the wire
connections and remove IC's from IC-Base.
Result: Thus, the code converters using logic gates were designed,
implemented and tested with truth table.

Marks Marks
Description Alloted Obtained
Signature of the
Faculty Member: Performance 25
Record 15
Viva-Voce 10
Date: Total 50
Viva  One way to convert BCD to binary using the hardware approach
Questions: is?
 Why is the Gray code more practical to use when coding the
position of a rotating shaft?
 Why do we use gray codes?
 Code conversion circuits mostly uses which gate IC?
 Why is a decoder used in digital electronics?
References:  https://www.tutorialspoint.com/conversion-of-gray-code-to-
binary
 https://www.javatpoint.com/binary-to-gray-code-cconversion-in-
digital-electronics
 https://www.javatpoint.com/conversion-of-bcd-to-excess-3-
code-in-digital-electronics
 https://www.engineersgarage.com/vhdl-tutorial-20-designing-4-
bit-binary-to-gray-gray-to-binary-code-converters/
 https://www.deldsim.com/study/material/16/implementation-
of-binary-to-gray-code-converter-using-logic-gates/
Rough Work
 Exp. No.: 4b & 4c Date: Page No.: 33
Exp. Name: Implementation of Code Converters
To design and implement 4-bit:
Aim: (i) BCD to Excess-3 Code Converter
(ii) Excess-3 to BCD Code Converter
Apparatus Sl.
Required: Components Specification Quantity
No.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC Trainer Kit - 1
6. Patch Cord - As Required
Theory: Introduction:
 The code converter is a combinational circuit i.e., a circuit
whose output depend upon the input of the current time
which performs interconversion between codes of one form
to another. Converters has been used in concepts of digital
electronics and devices like microprocessor or computers.
(i) BCD to Excess-3 Code Converter:
 The Excess-3 binary code is an example of a self-
complementary BCD code. A self-complementary binary
code is a code which is always complimented in itself.
 By replacing the bit 0 to 1 and 1 to 0 of a number, we find
the 1's complement of the number.
 The sum of the 1'st complement and the binary number of
a decimal is equal to the binary number of decimal 9.
 The process of converting BCD to Excess-3 is quite simple
from other conversions.
 The Excess-3 code can be calculated by adding 3, i.e.,
0011 to each four-digit BCD code. Below is the truth table
for the conversion of BCD to Excess-3 code. In the below
table, the variables A, B, C, and D represent the bits of the
binary numbers.
 The variable 'D' represents the LSB, and the variable 'A'
represents the MSB. In the same way, the variables w, x, y,
and z represent the bits of the Excess-3 code.
 The variable 'z' represents the LSB, and the variable 'w'
represents the MSB. The 'don't care conditions' is
expressed by the variable 'X'.
(ii) Excess-3 to BCD Code Converter:
 Excess-3 binary code is an unweighted self-complementary
BCD code.
 Self-Complementary property means that the 1‟s
complement of an excess-3 number is the excess-3 code of
the 9‟s complement of the corresponding decimal number.
 This property is useful since a decimal number can be
nines‟ complemented (for subtraction) as easily as a binary
number can be ones‟ complemented; just by inverting all
bits.
  For example, the excess-3 code for 3(0011) is 0110, and to
find the excess-3 code of the complement of 3, we just
need to find the 1‟s complement of 0110 -> 1001, which is
also the excess-3 code for the 9‟s complement of 3 -> (9-3)
= 6.
Logic 1. BCD to Excess-3 Code Converter
Diagrams:

2. Excess-3 to BCD Code Converter

 Truth 3. BCD to Excess-3 Code Converter
Tables: BCD I/P Excess-3 O/P
Decimal
Value A B C D W X Y Z
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
2. Excess-3 to BCD Code Converter

Decimal Excess-3 I/P BCD O/P

Value W X Y Z A B C D
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 0
3 0 0 1 1 0 0 1 1
4 0 1 0 0 0 1 0 0
5 0 1 0 1 0 1 0 1
6 0 1 1 0 0 1 1 0
7 0 1 1 1 0 1 1 1
8 1 0 0 0 1 0 0 0
9 1 0 0 1 1 0 0 1
K-Map: 1. BCD to Excess-3 Code Converter
 4. Excess-3 to BCD Code Converter

Procedure: Step 1: Place the IC on IC Trainer Kit.

Step 2: Turn on the trainer and verify the voltage of the power
supply using the multi-meter. It should be exactly
+5V.
Step 3: Implement the circuit as shown in the circuit
diagram.
Step 4: Connect the inputs to the input switches provided in
the IC Trainer Kit.
Step 5: Connect the outputs to the switches of O/P LEDs.
Step 6: Apply various combinations of inputs according to the
truth table and observe the condition of LEDs..
Step 7: Note down the corresponding output readings for
various combinations of inputs.
Step 8: Power Off Trainer Kit, disconnect all the wire
connections and remove IC's from IC-Base.
Result: Thus, the code converters using logic gates were designed,
implemented and tested with truth table.

Marks Marks
Description
Signature of the Alloted Obtained
Faculty Member: Performance 25
Record 15
Viva-Voce 10
Date: Total 50
 Viva  One way to convert BCD to binary using the hardware
Questions: approach is?
 Why is the Gray code more practical to use when coding the
position of a rotating shaft?
 Why do we use gray codes?
 Code conversion circuits mostly uses which gate IC?
 Why is a decoder used in digital electronics?
References:  https://www.tutorialspoint.com/conversion-of-gray-code-to-
binary
 https://www.javatpoint.com/binary-to-gray-code-cconversion-
in-digital-electronics
 https://www.javatpoint.com/conversion-of-bcd-to-excess-3-
code-in-digital-electronics
 https://www.engineersgarage.com/vhdl-tutorial-20-
designing-4-bit-binary-to-gray-gray-to-binary-code-
converters/
 https://www.deldsim.com/study/material/16/implementatio
n-of-binary-to-gray-code-converter-using-logic-gates/
Rough Work
 Exp. No.: 5a Date: Page No.: 39
Exp. Name: Implementation of BCD Adder
Aim: To design and implement BCD adder using IC 7483.
Apparatus Sl.
Required: Components Specification Quantity
No.
1. 4-Bit Binary Full Adder IC 7483 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
5. IC Trainer Kit - 1
6. Patch Cord - As Required
Theory: Introduction:
 BCD addition is the same as binary addition with a bit of
variation: whenever a sum is greater than 1001, it is not a
valid BCD number, so we add 0110 to it, to do the
correction. This will produce a carry, which is added to the
next BCD position.
 Add the two 4-bit BCD code inputs. Determine if the sum
of this addition is greater than 1001; if yes, then add 0110
to this sum and generate a carry to the next decimal
position.
BCD Adder:
 BCD adder is a circuit that performs the addition of two
BCD numbers in parallel.
 BCD additions are performed in 4-bit binary form so there
is a possibility of increasing binary number greater than 9
that results wrong output.
 To avoid this, in BCD addition correction logic I included
as described below,
1. If the binary sum is equal or less than 9 with carry 0,
then that binary sum is correct BCD sum.
2. I the binary sum is equal or less than 9 with carry 1,
then that binary sum is an incorrect BCD sum. To get
the correct BCD sum add 0110 with least significant
binary sum digits.
3. If the binary number is greater than 9, then that binary
sum is an incorrect BCD sum. To get the correct BCD
sum add 0110 with binary sum digits.
 BCD adder can be constructed with three blocks such as
two binary adders and the correction logic circuit. Initially
in the BCD adders, the four bit binary numbers are added
using parallel binary adder and then, the binary output is
checked to correct as BCD number.
 The correction logic generates the correction code based on
the binary output values. When we get the incorrect binary
output as per the condition described above, the correction
code is added with the binary output to get the correct
BCD number through second binary adder.
 To implement BCD adder we require:
1. 4-bit binary adder for initial addition
 2. Logic circuit to detect sum greater than 9 and
3. One more 4-bit adder to add 01102 in the sum if the
sum is greater than 9 or carry is 1.
 The two decimal digits, together with the input carry, are
first added in the top4- bit binary adder to provide the
binary sum.
 When the output carry is equal to zero, nothing is added to
the binary sum. When it is equal to one, binary 0110 is
added to the binary sum through the bottom 4-bit adder.
 The output carry generated from the bottom adder can be
ignored, since it supplies information already available at
the output carry terminal.
 The output carry from one stage must be connected to the
input carry of the next higher-order stage.
 Logic BCD Adder
Diagrams:
 Truth BCD Adder
Tables:
Binary sum BCD sum
Decimal
K Z3 Z2 Z1 Z0 C S3 S2 S1 S0
0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 1 0 0 0 0 1
2 0 0 0 1 0 0 0 0 1 0
3 0 0 0 1 1 0 0 0 1 1
4 0 0 1 0 0 0 0 1 0 0
5 0 0 1 0 1 0 0 1 0 1
6 0 0 1 1 0 0 0 1 1 0
7 0 0 1 1 1 0 0 1 1 1
8 0 1 0 0 0 0 1 0 0 0
9 0 1 0 0 1 0 1 0 0 1
10 0 1 0 1 0 1 0 0 0 0
11 0 1 0 1 1 1 0 0 0 1
12 0 1 1 0 0 1 0 0 1 0
13 0 1 1 0 1 1 0 0 1 1
14 0 1 1 1 0 1 0 1 0 0
15 0 1 1 1 1 1 0 1 0 1
16 1 0 0 0 0 1 0 1 1 0
17 1 0 0 0 1 1 0 1 1 1
18 1 0 0 1 0 1 1 0 0 0
19 1 0 0 1 1 1 1 0 0 1
K-Map: BCD Adder
 Procedure: Step 1: Place the IC on IC Trainer Kit.
Step 2: Turn on the trainer and verify the voltage of the power
supply using the multi-meter. It should be exactly
+5V.
Step 3: Implement the circuit as shown in the circuit
diagram.
Step 4: Connect the inputs to the input switches provided in
the IC Trainer Kit.
Step 5: Connect the outputs to the switches of O/P LEDs.
Step 6: Apply various combinations of inputs according to the
truth table and observe the condition of LEDs..
Step 7: Note down the corresponding output readings for
various combinations of inputs.
Step 8: Power Off Trainer Kit, disconnect all the wire
connections and remove IC's from IC-Base.
Result: Thus, the BCD adder were designed, implemented and tested
with truth table.

Marks Marks
Description
Signature of the Alloted Obtained
Faculty Member: Performance 25
Record 15
Viva-Voce 10
Date: Total 50

Viva  The BCD adder to add two decimal digits number needs
Questions: minimum of how many full adders and how many half adders?
 Decimal digit in BCD can be represented by?
 Mention the gates used to detect the sum greater than 9.
 Give the role of second 74283 IC in the circuit.
References:  https://www.youtube.com/watch?app=desktop&v=ScYHQt_Q
YPQ
 https://www.eeeguide.com/bcd-adder-circuit/
 https://www.tutorialspoint.com/what-is-bcd-adder-in-
computer-architecture
 https://www.javatpoint.com/decimal-or-bcd-adder-in-digital-
electronics
 http://www.faadooengineers.com/online-
study/post/ece/digital-elecronics/447/bcd-adder
Rough Work
 Exp. No.: 5b Date: Page No.: 45
Exp. Name: Implementation of Encoder and Decoder
Aim: To design and implement encoder and decoder using logic gates.
Apparatus Sl.
Required: Components Specification Quantity
No.
1. NOT Gate IC 7404 1
2. OR Gate IC 7432 3
3. AND Gate IC 7408 1
5. IC Trainer Kit - 1
6. Patch Cord - As Required
Theory: Introduction:
 The priority encoder is a combinational logic circuit that
contains 2n input lines and n output lines and represents
the highest priority input among all the input lines.
 When multiple input lines are active high at the same time,
then the input that has the highest priority is considered
first to generate the output.
 It is used to solve the issues in binary encoders, which
generate wrong output when more than one input line is
active high. If more than one input line is active high(1) at
the same time, then this encoder prioritizes every input
level and allocates the priority level to each input.
 An encoder produces an m bit binary code corresponding
to the digital input number. The encoder accepts an n
input digital word and converts it into an m bit another
digital word.
 A decoder is a combinational circuit. It has n input and to
a maximum m = 2n outputs.
 Decoder is identical to a demultiplexer without any data
input.
 It performs operations which are exactly opposite to those
of an encoder.

(i) Encoder:
 This kind of encoder is also named an 8-bit or Octal to
Binary priority encoder. This type of encoder consists of 8
inputs and 3 outputs.
 When multiple inputs are active high at the same time, the
input with the highest priority is considered to represent
the output.
 For example, if D1, D2, and D3 inputs are active high or
logic 1 regardless of other input bits, then the encoded
output of the priority encoder will be D3 i.,e 111.
 Here, the D1, and D2 input bits are either irrelevant or
don‟t care conditions.
 The output „A‟ of a priority encoder is represented as active
high or logic „1‟ only when the inputs D4, D5, D6, and D7
are active high.
  The output „B‟ of an encoder is at logic 1 only when the
inputs D2, D3, D6, and D7 are active high.
 Similarly, the output „C‟ is represented as logic „1‟ only
when the inputs D1, D3, D5, and D7 are active high.
 The output expressions for A, B, and C are written either
from Karnaugh map (K-map) simplification Or truth table.
 The output expression are obtained as shown below,
C = D1+D3+D5+D7
B = D2+D3+D6+D7
A = D4+D5+D6+D7

(ii) Decoder:
 In the 2 to 4 line decoder, there is a total of three inputs,
i.e., A0, and A1 and E and four outputs, i.e., Y0, Y1, Y2,
and Y3.
 For each combination of inputs, when the enable 'E' is set
to 1, one of these four outputs will be 1. The block diagram
and the truth table of the 2 to 4 line decoder are given
below.
 Decoder is a multiple input multiple output combinational
digital circuit that converts n number of coded binary
inputs in to 2n number of coded binary outputs.
 In the decoder, the combination of input information lines
define the logic output of any one output line as logic high
at a time and rest of the output lines are being fixed to
logic 0. When the combination of input binary information
changes the logic 1 output line also be changes. Usually
decoder produces unique output corresponding to each
input pattern.
 Therefore, the n to 2n decoder is also called as simple
minterm generator with each output corresponding to
exactly one minterm. The enable input used in the diagram
acts as a controller of decoder. To operate the decoder the
enable input must set as active high.
 The output expression are obtained as shown below,
Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'
 Circuit Encoder
Diagrams:

Decoder

Input

Output

Truth Encoder
Tables:
Input Output
D7 D6 D5 D4 D3 D2 D1 D0 C B A
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
 Decoder
Enable Input Output
En B A Y0 Y1 Y2 Y3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
0 X X 0 0 0 0
Procedure: Step 1: Place the IC on IC Trainer Kit.
Step 2: Turn on the trainer and verify the voltage of the power
supply using the multi-meter. It should be exactly
+5V.
Step 3: Implement the circuit as shown in the circuit
diagram.
Step 4: Connect the inputs to the input switches provided in
the IC Trainer Kit.
Step 5: Connect the outputs to the switches of O/P LEDs.
Step 6: Apply various combinations of inputs according to the
truth table and observe the condition of LEDs..
Step 7: Note down the corresponding output readings for
various combinations of inputs.
Step 8: Power Off Trainer Kit, disconnect all the wire
connections and remove IC's from IC-Base.
Result: Thus, the BCD adder were designed, implemented and tested
with truth table.

Marks Marks
Description
Signature of the Alloted Obtained
Faculty Member: Performance 25
Record 15
Viva-Voce 10
Date: Total 50

Viva  How many input lines exist in Decimal to BCD Encoder ?

Questions:  How many output lines exist in Decimal to BCD Encoder ?
 For conversion of BCD to seven segment display which
omponent is required.
 By using only which of the gates decoder can be formed?
 A circuit that changes a code into a set of signals is called?
References:  https://learn.circuitverse.org/docs/comb-msi/encoders-
decoders.html
 https://www.indiamart.com/proddetail/encode-10-line-
decimal-to-4-line-bcd-74147-ic-26123361830.html
 https://www.javatpoint.com/decoder-digital-electronics
 https://www.elprocus.com/priority-encoder/
 Exp. No.: 6 Date: Page No.: 49
Exp. Name: Implementation of Functions Using Multiplexers
To design and implement the combinational logic using
Aim:
multiplexer.
Apparatus Sl.
Required: Components Specification Quantity
No.
1. 8-Input Multiplexer IC 74151 1
2. IC Trainer Kit - 1
3. Patch Cord - As Required
Theory:
Introduction:
 A multiplexer is a combinational circuit that has 2n input
lines and a single output line.
 Simply, the multiplexer is a multi-input and single-output
combinational circuit.
 The binary information is received from the input lines and
directed to the output line.
 On the basis of the values of the selection lines, one of
these data inputs will be connected to the output.
 Unlike encoder and decoder, there are n selection lines and
2n input lines. So, there is a total of 2N possible
combinations of inputs. A multiplexer is also treated as
Mux.
(i) Implementation of functions using Multiplexers:
 Let us solve some problems on implementing the boolean
expressions using a multiplexer. In this method, 3
variables are given(say P, Q, R), which are the selection
inputs for the mux. For three selection inputs, the mux to
be built was 2n = 23 = 8 : 1. So, in this method, the type of
mux can be decided by the given number of variables.
 Way to solve the given function:
1. The first step is to select the multiplexer. If the given
expression has n variables, then determine the
multiplexer using the formula 2n : 1.
2. Connect the inputs, that correspond to the given
minterms to logic 1.
3. Connect all the other inputs to the ground(logic 0).
4. Connect the input variables(P, Q, R) as the selection
lines.
 Implement the following boolean expression using a
multiplexer.

F(A, B, C) = ∑ m(2, 3, 6, 7)

 The inputs, corresponding to the minterms (2, 3, 6, 7) are

connected to logic 1 and the remaining terms to logic
0(grounded). The given input variables are connected as
three selection lines.
 IC 8x1 Multiplexer
Diagrams:

Logic For the function F=Σm(2, 3, 6, 7)

Diagrams:

Truth For the function F=Σm(2, 3, 6, 7)

Tables:
Input Output
Minterm
A B C (F)
0 0 0 0 0
1 0 0 1 0
2 0 1 0 1
3 0 1 1 1
4 1 0 0 0
5 1 0 1 0
6 1 1 0 1
7 1 1 1 1
 Procedure: Step 1: Place the IC on IC Trainer Kit.
Step 2: Turn on the trainer and verify the voltage of the power
supply using the multi-meter. It should be exactly
+5V.
Step 3: Implement the circuit as shown in the circuit
diagram.
Step 4: Connect the inputs to the input switches provided in
the IC Trainer Kit.
Step 5: Connect the outputs to the switches of O/P LEDs.
Step 6: Apply various combinations of inputs according to the
truth table and observe the condition of LEDs..
Step 7: Note down the corresponding output readings for
various combinations of inputs.
Step 8: Power Off Trainer Kit, disconnect all the wire
connections and remove IC's from IC-Base.
Result: Thus, the implementation of the given Boolean function using
multiplexer was designed, implemented and verified with its
truth table.

Marks Marks
Description
Signature of the Alloted Obtained
Faculty Member: Performance 25
Record 15
Viva-Voce 10
Date: Total 50

Viva  Which combinational circuit is renowned for selecting a single

Questions: input from multiple inputs & directing the binary information
to output line?
 Which is the major functioning responsibility of the
multiplexing combinational circuit?
 What is the function of an enable input on a multiplexer chip?
 How many select lines would be required for an 8-line-to-1-
line multiplexer?
 How many NOT gates are required for the construction of a 4-
to-1 multiplexer?
 How many NOT gates are required for the construction of a 4-
to-1 multiplexer?
References:  https://www.electrically4u.com/solved-problems-on-
multiplexer/#google_vignette
 http://www.ee.surrey.ac.uk/Projects/Labview/multiplexer/in
dex.html
 https://www.geeksforgeeks.org/implementation-of-sop-
function-using-multiplexer/
 https://www.javatpoint.com/multiplexer-digital-electronics
Rough Work
 Exp. No.: 7 Date: Page No.: 53
Exp. Name: Design and Implementation of Synchronous Counter
To design and implement a 3-bit synchronous binary up and
Aim:
down counter using JK flip- flop.
Apparatus Sl.
Required: Components Specification Quantity
No.
1. Dual JK Flip-Flop IC 7476 2
2. AND gates IC 7408 1
3. OR Gate IC 7432 1
4. IC Trainer Kit - 1
5. Patch Cord - As Required
Theory: Introduction:
 In digital electronics, a set of flip-flops that changes its
states in response to pulses applied at the input is called a
digital counter.
 In the digital counter circuit, the flip flops are connected in
such a way that their combined state at any time is the
binary equivalent of the total number of pulses that have
occurred up to that time. Therefore, as its name implies, a
counter is used to count pulses in a digital system.
 Digital counters are classified into the following two types
namely,
1. Asynchronous Counter: The type of counter in which
the flip flops are connected in such a way that they are
not triggered simultaneously is known as asynchronous
counter. Asynchronous counter is also known as ripple
counter.
2. Synchronous Counter: The type of counter in which all
the flip flops are clocked simultaneously is known as a
synchronous counter.
(i) 3-Bit Synchronous Binary Up Counter:
 The J and K inputs of the flip-flop B are connected to with
QC. The J and K inputs of the flip-flop A, are connected
with AND operated output of QC and QB.
 The flip-flop C changes its state when with the occurrence
of negative transition at each clock pulse.
 The flip- flop B changes its state when QC = 1 and when
there is negative transition at clock input.
 Flip- flop A changes its state when QC = QB = 1 and when
there is negative transition at clock input.
(ii) 3-Bit Synchronous Binary Down Counter:
 The J and K inputs of the flip-flop B are connected to with
QC‟. The J and K inputs of the flip-flop A, are connected
with AND operated output of QC‟ and QB‟.
 The flip-flop C changes its state when with the occurrence
of negative transition at each clock pulse.
 The flip-flop B changes its state when QC‟ = 1 and when
there is negative transition at clock input.
 Flip-flop A changes its state when QC‟ = QB‟ = 1 and when
there is negative transition at clock input.
 IC Dual JK Flip-Flop (IC 7476)
Diagrams:

Logic 3-Bit Synchronous Binary UP Counter

Diagrams:

3-Bit Synchronous Binary Down Counter

 Truth 3-Bit Synchronous Binary UP Counter
Tables: Present State Next State JK Flip-Flop Input
A B C A B C JA KA JB KB JC KC
0 0 0
0 0 1
0 0 0
0 0 1
1 1 0
1 1 1
1 1 0
1 1 1
3-Bit Synchronous Binary UP Counter
Present State Next State JK Flip-Flop Input
A B C A B C JA KA JB KB JC KC
0 0 0
0 0 1
0 0 0
0 0 1
1 1 0
1 1 1
1 1 0
1 1 1
Procedure: Step 1: Place the IC on IC Trainer Kit.
Step 2: Turn on the trainer and verify the voltage of the power
supply using the multi-meter. It should be exactly +5V.
Step 3: Implement the circuit as shown in the circuit diagram.
Step 4: Connect the inputs to the input switches provided in
the IC Trainer Kit.
Step 5: Connect the outputs to the switches of O/P LEDs.
Step 6: Apply various combinations of inputs according to the
truth table and observe the condition of LEDs.
Step 7: Note down the corresponding output readings for
various combinations of inputs.
Step 8: Power Off Trainer Kit, disconnect all the wire
connections and remove IC's from IC-Base.
Result: Thus the synchronous up and down counters were designed
using JK flip-flop and verified with their state table.

Marks Marks
Signature of the Description
Alloted Obtained
Faculty Member: Performance 25
Record 15
Viva-Voce 10
Date: Total 50
 Viva  Which signal in synchronous counter is given as input
Questions: simultaneously to individual flip-flop?
 How many clock inputs does a counter comprises of?
 In which of the form does the output of a binary counter is
represented in?
 A 4-bit synchronous counter starts from?
 How many inputs does a single flip-flop in a synchronous
counter comprises of?
 A standard Binary counter converts data in to which format
via additional logic to deploy desired state of sequence?
 A decade counter is also called?
 A synchronous counter uses what types of flip-flop to change
its state?
 When input clock applied to synchronous counter is „1‟ then
the flip-flop output is?
 A 3-bit synchronous counter comprises of what type of logic
gates?
 A 3-bit synchronous counter comprises of what type of flip-
flop?
 How many JK flip flops does a 3-bit synchronous counter
comprises of?
References:  https://www.tutorialspoint.com/design-of-synchronous-
counter
 https://www.iitg.ac.in/cseweb/vlab/Digital-System-
Lab/up_counter.php?id=13#:~:text=In%20the%203%2Dbit%2
0synchronous,outputs%20of%20FF0%20and%20FF1
 https://www.watelectronics.com/mcq/synchronous-counter/
 https://www.geeksforgeeks.org/synchronous-3-bit-up-down-
counter/
 https://www.brainkart.com/article/Design-of-Synchronous-
Counters_12975/
 Exp. No.: 8 Date: Page No.: 57
Exp. Name: Implementation of Universal Shift Registers
To design, implement and verify the functioning of Universal shift
Aim:
right register using D flip-flop.
Apparatus Sl.
Required: Components Specification Quantity
No.
1. Dual D Flip-Flop IC 7474 2
2. IC Trainer Kit - 1
3. Patch Cord - As Required
Theory: Introduction:
 Flip flops can be used to store a single bit of binary data (1
or 0). However, in order to store multiple bits of data, we
need multiple flip-flops. N flip flops are to be connected in
order to store n bits of data.
 A Register is a device that is used to store such
information. It is a group of flip-flops connected in series
used to store multiple bits of data.
 The information stored within these registers can be
transferred with the help of shift registers.
 Shift Register is a group of flip flops used to store multiple
bits of data. The bits stored in such registers can be made
to move within the registers and in/out of the registers by
applying clock pulses.
 An n-bit shift register can be formed by connecting n flip-
flops where each flip-flop stores a single bit of data. The
registers which will shift the bits to the left are called “Shift
left registers”.
 The registers which will shift the bits to the right are called
“Shift right registers”. Shift registers are basically of
following types.
1. Serial In Serial Out shift register
2. Serial In parallel Out shift register
3. Parallel In Serial Out shift register
4. Parallel In parallel Out shift register
5. Bidirectional Shift Register
6. Universal Shift Register
7. Shift Register Counter
(i) Serial In Serial Out Shift Register (SISO):
 The shift register, which allows serial input (one bit after
the other through a single data line) and produces a serial
output is known as a Serial-In Serial-Out shift register.
 Since there is only one output, the data leaves the shift
register one bit at a time in a serial pattern, thus the name
Serial-In Serial-Out Shift Register.
 The logic circuit given below shows a serial-in serial-out
shift register. The circuit consists of four D flip-flops which
are connected in a serial manner.
 All these flip-flops are synchronous with each other since
the same clock signal is applied to each flip-flop.
  The above circuit is an example of a shift right register,
taking the serial data input from the left side of the flip
flop.
 The main use of a SISO is to act as a delay element.

(ii) Serial-In Parallel-Out Shift Register (SIPO):

 The shift register, which allows serial input (one bit after
the other through a single data line) and produces a
parallel output is known as the Serial-In Parallel-Out shift
register.
 The logic circuit given below shows a serial-in-parallel-out
shift register. The circuit consists of four D flip-flops which
are connected.
 The clear (CLR) signal is connected in addition to the clock
signal to all 4 flip flops in order to RESET them.
 The output of the first flip-flop is connected to the input of
the next flip flop and so on.
 All these flip-flops are synchronous with each other since
the same clock signal is applied to each flip-flop.

 The above circuit is an example of a shift right register,

taking the serial data input from the left side of the flip-
flop and producing a parallel output.
 They are used in communication lines where
demultiplexing of a data line into several parallel lines is
required because the main use of the SIPO register is to
convert serial data into parallel data.
 IC Dual D Flip-Flop (IC 7474)
Diagrams:

Logic Serial In Serial Out Shift Register (SISO)

Diagrams:

Serial-In Parallel-Out Shift Register (SIPO)

 Truth Serial In Serial Out Shift Register (SISO)
Tables:
Data Input=
Clock
Q4
I/P Q1 Q2 Q3 (Dout)
0 0 0
0 0 1
0 0 0
0 0 1
Serial-In Parallel-Out Shift Register (SIPO)
Data Input=
Clock Dout
I/P
Q1 Q2 Q3 Q4
0 0 0
0 0 1
0 0 0
0 0 1
Procedure: Step 1: Place the IC on IC Trainer Kit.
Step 2: Turn on the trainer and verify the voltage of the power
supply using the multi-meter. It should be exactly +5V.
Step 3: Implement the circuit as shown in the circuit diagram.
Step 4: Connect the inputs to the input switches provided in
the IC Trainer Kit.
Step 5: Connect the outputs to the switches of O/P LEDs.
Step 6: Apply various combinations of inputs according to the
truth table and observe the condition of LEDs.
Step 7: Note down the corresponding output readings for
various combinations of inputs.
Step 8: Power Off Trainer Kit, disconnect all the wire
connections and remove IC's from IC-Base.
Result: Thus, the Universal shift register using D flip-flop were
implemented and studied the operation in 2 different modes.

Marks Marks
Description
Signature of the Alloted Obtained
Faculty Member: Performance 25
Record 15
Viva-Voce 10
Date: Total 50
 Viva  How many clock pulses will be required to completely load
Questions: serially a 5-bit shift register?
 How is a strobe signal used when serially loading a shift
register? 
 How is a strobe signal used when serially loading a shift
register? 
 How many types of shift registers are there? and what are
they.
 Which shift registers are used for time delays?
 How many methods are there to shift the data?
 A shift register is made up of how many flip-flops?
 What happens when a shift register is clocked? 
References:  https://www.tutorialspoint.com/design-of-synchronous-
counter
 https://www.iitg.ac.in/cseweb/vlab/Digital-System-
Lab/up_counter.php?id=13#:~:text=In%20the%203%2Dbit%2
0synchronous,outputs%20of%20FF0%20and%20FF1
 https://www.watelectronics.com/mcq/synchronous-counter/
Rough Work
 Exp. No.: 9 Date: Page No.: 63
Exp. Name: Simulation Based Study of Computer Architecture
To study about the single instruction execution using design of a
Aim:
single instruction CPU.
Note:  This experiment study was performed using virtual labs
from MHRD. It is an online virtual platform for performing
practical experiments under different disciplines. This
experiment was performed using Logic Design and
Computer Organization laboratory from vlabs.
The link for performing the simulation is:
http://vlabs.iitkgp.ac.in/coa/exp12/index.html
Procedure: Step 1: Start the simulator as directed. This simulator
supports 5-valued logic.
Step 2: To perform the experiment on the given modules, we
need the CPU, the working memory with a program and
data loaded, a clock input, Bit switch (to give
input,which will toggle its value with a double click),
Bit displays(for seeing output), wires.
Step 3: Load Memory: Click on the load memory button in the
left pane. you can either load the memory by filling the
form or you can directly load the program form a text
file. The memory provides 4-bit address space and 12
bit data word, thus providing 16 memory address
starting from 0000 to 1111. For loading from file, the
file should contain only binary values, it must contain
16 lines, each line containing the content to be stored
in the corresponding memory address. For example,
content of first line will be loaded to the 0000 address
of the memory, similarly, the second line will
correspond to the 0001 address and so on, finally the
content of last line will be fed to the 1111 address. The
progrm should use self loop for halting, for example,
the instruction stored at address 1010 will cause self
loop execution, if it content of a has -1 in binary format
(in 2's complement), the content of b has 0 and c is
1010, then once the execution reaches to this 1010
address, it will finally point to itself.
Step 4: Instantiating the Memory: After loading the memory,
click on the memory component from the computer
design drawer in the palette of the simulator then click
on the position of the design editor where you want to
put the component(no drag and drop, simple click will
serve the purpose).
Step 5: The pin configuration of the component is shown
whenever the mouse is hovered on any canned
component of the palette or pressing the show pin
configuration button on the toolbar will show it
constantly in the left pane. Pin numbering starts from
1 and from the bottom left corner(indicating with the
circle) and increases anticlockwise.
 Step 6: Pin configuration of the memory module:
 Input pins (upper terminals): memory enable: 30,
R/W': 29, address: 25-28, data: 13-24 (13 is LSB)
 Output pins(lower terminals): data output : 1-12
(1 is MSB)
Step 7: Instantiate the CPU from the computer design drawer
in the palette of the simulator then click on the
position of the design editor where you want to put the
component.
Step 8: Pin configuration of the CPU:
 Input pins (upper terminals): data input: 20-31
(20 is MSB), clock input: 19.
 Output pins(lower terminals): memory enable: 1,
R/W': 2, address: 3-6( 3 is MSB), data output: 7-
18 (7 is MSB)
Step 9: To connect any two components select the Connection
menu of Palette, and then click on the Source terminal
and click on the target terminal. According to the
following diagram connect all the components. Connect
the memory outputs to the input terminals of the CPU,
specified datapath outputs to the inputs of the
controller, the clock input, Bit switches with the inputs
and Bit displays component with the outputs (from
Display and Input drawer of the pallet,if it is not seen
scroll down in the drawer). After the connection is over
click the selection tool in the pallete.
Step 10: Start clock and observe the behavior of the CPU. See
the content of memory by clicking show memory button
in the left pane. Observe how the program is executing
sequentially and modify the data content as per the
program.
Block Single Instruction CPU
Diagram:
 Output Screenshots:
(i) CPU and Memory Added in the Simulator

(ii) CPU and Memory Added with clock pulse in the simulator:
 (iii) CPU and Memory with changing clock pulse in the simulator:

(iv) CPU and Memory connected with address and data lines with clock pulse in
the simulator:
 (v) CPU and Memory connected with loaded Memory option:

(vi) CPU and Memory connected with Memory loaded with data under Execution:
 Marks Marks
Description
Signature of the Alloted Obtained
Faculty Member: Performance 25
Record 15
Viva-Voce 10
Date: Total 50

Viva  The program controller of digital computer works

Questions:  The minimum time delay required between initiation of two
successive memory operations is called?
 General purpose internal registers are also called?
 How many units in a single bus structure can communicate at
a time?
 A single bus structure is found in generally.
 During read operation what is fetched by the CPU?
References:  http://vlabs.iitkgp.ernet.in/coa/exp12/index.html#
 NPTEL (e-learning courses from IITs and IISC)