Mixed Signal Programming

Student Manual

Applications Engineering Training

Book 2 of 2 PN 553-405-85 MRP Rev 002

October 2003
DCTime Instrument

Rev0343
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 Objectives

• The goal of this session is to introduce you to

the DCTime Instrument
– Learn the basic concepts about the dc time stampers
– Understand the DCTime Instrument functionality
– Learn how to use the DCTime to make measurements
– Build a DCTime Test Procedures in order to develop custom test
procedures that are specifically suited for unique testing needs.

Module 19 - 2

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 Measuring Time

• There are three basic ways of measuring time

1. Using the High Speed Digital by use of a technique called Edge
Find
- Limited to the edge placement accuracy/resolution of the High
Speed Digital.
- Requires no other instrument.
2. Standard Counter Technology such as a frequency counter
- Limited to the bandwidth of the instrument
3. Time Stamper Architecture
- Limited to the bandwidth of the instrument

Module 19 - 3

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 Edge Find

• Comparator edge placement is changed on a channel

to find where the comparator changes from a pass to
a fail.

• Compare strobe is set for a Low expect value with a

vil set to the expected trigger voltage value
• The point of failure can then be said to be the edge
value.
Module 19 - 4

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 Standard Counter

• Two events are used to record the time.

– Start event – begins the count
– Stop event – stops the count
• The answer is read directly

Start = 0ns Stop = 10.04ns

Module 19 - 5

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 Time Stamper Basics
• When a signal is recognized by the DCTime
Instrument, a time value is recorded.
• Each event will be recorded as a time value

124.75ns 175.56ns 50.81ns

Or

• Recorded times are stored in memory 19.68Mhz

• Following completion of stored samples, calculations

are performed on the collected samples.
Module 19 - 6

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 DCTime Clock

• DCTime instrument references a circular clock.

• The clock has a max time of ~ 671ms.
• The method of “stamping” is nothing more than
recording the current time
• All DCTime clocks are synchronized on a system.
• There is no way to know if the clock circled multiple
times (no equivalent to a minute hand)
671ms

503¼ms 167¾ms

335½ms
Module 19 - 7

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 1 Stamper’s Samples
• Each Stamper has a memory depth of 512.

Triggered and started

Event

Capture Memory
= Time Stamp
640.02ms
655.89ms
669.77ms
512
016.13ms
Samples
Clock has gone
through 1 cycle

Module 19 - 8

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 DCTime Capability

• The DCTime Instrument can make the following

measurements:
– Frequency
– Period
– Pulse Width
– Duty Cycle
– Rise/Fall Time
– Pin to Pin Delays

• DCTime Modules are the same on all DCVI boards

Module 19 - 9

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 DCTime Instrument
• The DC Time consists of two DC Time
instruments per DC board, each consisting of:
– one timer front end (TFE)
– two time Stampers (TS)
– two asynchronous trigger lines
– One high performance input for larger bandwidth
– one return output pin to the DIB for DIB triggers

DCTime

Module 19 - 10

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 DC Time Architecture
for
Pat DIB triggers
Gen
16b DAC
via
DIB Access
Thresh
Select
Ranging
XOR
From channel output
sense lines or 16b DAC
High Performance
Input 4:1

4 DGS lines

Enable/Event
Memory Stamper 1 Select
Each Stamper share
the Start logic but
Start Logic have their own
Trigger the Stampers
enable/holdoff logic
from the Pattern or
Enable/Event
from test elements. Memory Stamper 2
Select

Module 19 - 11

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 DC Time Instrument
All channels can send out a DIB Access
DIB trigger to:
DA 1,2 on DC30 XOR
High performance path for
wider Bandwidth DA 1,3 on DC75
DC90 NA
Trigger Line 1

50 ohm
Vref
Comp
High Z
Atten
Dual Time
Stampers
To Channels
Comp
DC Timer Stampers are free Vref
running clocks that cycle
between 0 and 671ms.
Both stampers share the same
Trigger and Start signal DCTime Front End Trigger Line 2
Module 19 - 12

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 DCTime Front End
Setting the
. voltage range Each threshold comparator can
programs the signal attenuator. be set to its own voltage value
This can be done by inputting a and when that voltage value is
max voltage value and an reached the threshold is tripped
impedance type. The software
then selects the best available Threshold 1
attenuator setting given those
values

Dual
Attenuator Time
VRange Select Stampers

Threshold 2

Module 19 - 13

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 Connections to the DCTime
• There are three basic ways to connect to the DCTime Unit.
– DCTime: (Most Commonly Used)
• Connection to the V/I’s (sense lines)
• The channel time-measurement relay is on the DUT side of the V/I
disconnect relay, and therefore the V/I does not need to be connected
to the DUT in order to use the DCTime Unit.
– DCTimeHP:
• Direct connection to the DCTime
• One connection per DCTime Unit
• Example: DCTime-2 on DC-30 is accessible on 10.b38
– DCTimeTrig: (DIB Access – Output Pin)
• The trigger output that goes through the DIB access channel.
• Cannot enable or start another instrument.
• Connect to the DIB through an XOR gate. This provides a pulse.
• Example: DCTime-2 on DC-30 is accessible on 10.b6

Module 19 - 14

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 Connections to the DCTime
• There are Additional connections to the DCTime Unit.
– Asynchronous Trigger Lines: (Advanced Topic)
• Connected to any of the V/I channels through the internal
trigger bus
– Pin: (Advanced Topic)
• Selected from the programmed pins, this controls the operation
of the DC Time and can enable the time stamp when a signal
should occur. An enable signal is used to selectively capture
events.
– Pattern: (Advanced Topic)
• controls by HSD patterns and microcode

Module 19 - 15

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 DCTime Inputs
DC30 Sense Channels DC75 Sense Channels

DCTime 0 1, 2, 5, 6, 9, 10, 13, 14, 17, 1, 2

18

DCTime 1 3, 4, 7, 8, 11, 12, 15, 16, 3, 4

19, 20

DC30 High Performance DC75 High Performance

Channels Channels

DCTime 0 1 1

DCTime 1 2 2

Module 19 - 16

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 DCTime Dual Stampers

• “Dual stampers” refers to the two stampers on the

DCTime instrument
• A stamper records the value on a clock when an
event occurs
Dual Stampers
671ms
Stamper1 Stamper2

503¼ms 167¾ms

335½ms

Module 19 - 17

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 DCTime Dual Stampers
Both DCTime stampers
use the same trigger
None Stamper1
Threshold1 slope
command
Pattern select Event
and start signal.
None
slope Mode Enable
Stamper1’s select select
Enable Pin Pattern Holdoff
Time/ SampleSize
Off count
Precount select
Trigger: Used to initiate a BeforeEach
capture. Threshold2 Interleave
• Can look at it as equivalent
to plugging in the stampers Stamper2
to “electricity” (but they still None slope
need to be turned “on”) Event
select
– Can be done via Test Pattern slope Mode Enable
Elements, VBT select select
Stamper2’s Enable None Holdoff
language, or pattern.
Pin Pattern
Start: Signal used to activate Time/ SampleSize
(turn “on”) the stampers ON count
• Input: OnTrigger Start Pin Off select
OFF
(automatically activated) Precount
• Slope: positive or negative Trigger BeforeEach

Module 19 - 18

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 DCTime Stampers
Stamper1
Event Each DCTime Stamper consists of:
Enable 1. Event: signal used to measure time (signal
Holdoff on which the stampers will be recording time)
SampleSize 2. Enable: controls when the individual stamper
is capable of stamping (“on/off”)
3. Hold-off: means of delaying when the stamper
Interleave
is stamping
Stamper2 4. SampleSize: number of time recordings the
Event stamper is requested to take
Enable
Holdoff
SampleSize

Module 19 - 19

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 DCTime Start
Start.Input = Pin
Start.Slope = Positive

Positive
Triggered Slope Threshold
Level

Start

Event

Stamp Events
Waiting for
Start Signal
Sample Size = 8
= Time Stamp

Module 19 - 20

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 DCTime Interleave On
• Interleave: used to properly align stamper1 and stamper2
– Stamper2 cannot stamp until stamper1 stamps first. Then stamper1 cannot stamp
again until stamper2 stamps. This continues “interleaving” the stampers.
– Settings: on/off
– Default is on
SampleSize of 5 each
Interleave On
SampleSize = 5

Triggered and started

Stamper 1’s
Event
Stamper 2’s
Event
= Stamper 1’s Time Stamp = Stamper 2’s Time Stamp

Note: Assuming enable input = none and holdoff mode = off

Module 19 - 21

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 DCTime Interleave Off
Interleave Off
SampleSize = 5

Triggered and started

Stamper 1’s
Event

Stamper 2’s
Event

SampleSize of 5

= Stamper 1’s Time Stamp = Stamper 2’s Time Stamp

Note: Assuming enable input = none and holdoff mode = off
Module 19 - 22

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Measurement Examples

Rev0343
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 Rise Time/Fall Time
• Stamper 1 stamps the start using threshold1
• Stamper 2 stamps the finish using threshold2
• Interleave is on
• To set up only need to program the following:
– Voltage Range
– Thresholds (method that takes two threshold values)
– Hysteresis (For slower or noisy signals)
– Start
– SampleSize

Rise Time

= 1st DCTime’s Stamps = 2nd DCTime’s Stamps

Module 19 - 24

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 Pulse Width
• Stamper 1 stamps the start using threshold1
• Stamper 2 stamps the finish using threshold1
• Interleave is on
• To set up only need to program the following:
– Voltage Range
– Threshold
– Hysteresis (For slower or noisy signals)
– Slope (determines if measuring positive or negative pulse)
– Start
– SampleSize Pulse Width

= 1st DCTime’s Stamps = 2nd DCTime’s Stamps

Module 19 - 25

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 Period Example

• To set up only need to program the following:

– Voltage Range
– Threshold
– Hysteresis (For slower or noisy signals)
– Slope
– Start
– SampleSize

Period 1 Period 2

= 1st DCTime’s Stamps = 2nd DCTime’s Stamps

Module 19 - 26

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 Duty Cycle
• Duty Cycle = PulseWidth/Period
• Stamper 1 stamps the period using threshold1
• Stamper 2 stamps the second half of pulse using
threshold1
• Interleave is on
• To set up only need to program the following:
– Voltage Range
– Threshold
– Hysteresis (only if using small voltage values)
– Slope (determines if measuring positive or negative pulse)
– Start
– SampleSize

Module 19 - 27

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 Duty Cycle cont.

• Max sample size is 511.

• Takes two stamps by stamper1 and one stamp by
stamper2 to get a duty cycle measurement
• Stamps by stamper1 are reused for the next
measurement.
Pulse Width Pulse Width Pulse Width

Period Period Period

= 1st DCTime’s Stamps = 2nd DCTime’s Stamps

Module 19 - 28

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 Frequency

• Stamper 1 stamps using threshold1

• Stamper 2 is not used
• Holdoff is used to give greater accuracy.
• To set up only need to program the following:
– Voltage Range
– Threshold
– Hysteresis (only if using small voltage values)
– Slope
– Start
– SampleSize

Module 19 - 29

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 Frequency cont.

• The SampleSize specified is used to program the

holdoff count
• SampleSize can be 1 through 262,144
• Holdoff Count is always set to 511
• SampleSize set is equal to the requested SampleSize
/ 511 + 1.
• Example: SampleSize = 1024.
SampleSize = (1024/511) +1 = 3

Module 19 - 30

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 Frequency cont.

• Returned value from hardware is average of 512

periods
• Software returns back as a frequency measurement =
1 / (measured period / 512)

Average of 512 Periods

= Stamp = Holdoff

Module 19 - 31

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 Pin-to-Pin Delay Example
• Requires two DCTime instruments
• Only Stamper1 is used
• To set up only need to program the following:
– Voltage Range
– Threshold
– Hysteresis
– Slope
– Start
– SampleSize
• A positive result from CalculateResults means the 1st
set of stamps passed into the method came first. A
negative means the 2nd set came first.

Module 19 - 32

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Pin-to-Pin Delay Example
– In VBT CalculateResults take a PinData variable allowing the user to
match up data on a pin-by-pin basis
– In TE CalculateResults returns a DSPWave

Pin to Pin Delay Pin to Pin Delay

(negative) (positive)

= 1st DCTime’s Stamps = 2nd DCTime’s Stamps

Module 19 - 33

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Programming DCTime

Rev0343
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 Objectives
• The goal of this session is to introduce you to building DC
Time Test Procedures in order to develop custom test
procedures that are specifically suited for unique testing
needs.

Module 19 - 35

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 Introduction
The steps for creating a DC Time Test Procedure are very similar to
adding DCVI Test Procedures

¾ Add a procedure worksheet

¾ Add a test Name to the procedure worksheet
¾ Click on the ellipsis button to enter the PDE
¾ Click on the test element chooser to display a list of test elements
¾ Select DCTime test elements from the instruments list
¾ Add each element required to create a test
¾ Click on each test element in the Flow Chart Editor and select <New
Variables> or previously defined variables from the drop – down lists
¾ Edit variables in the variables table when necessary and reselect from the
variable drop-down lists
¾ Save the test procedure to Excel
¾ Run the Instance Editor Wizard to create the instance form
¾ Add the test procedure to the instance sheet
¾ Add the test to the flow table

Module 19 - 36

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 DC Time Test Elements
In order to add DC Time test elements to the Flow Chart Editor click on
the TE icon. Select >Elements by instrument and then select> DCTime.
¾ Click on the test element chooser to display a list of test elements
¾ Select DCTime test elements from the instruments list
¾ Add each element required to create a test

Module 19 - 37

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 DC Time Elements
The following test elements can be used to make
time measurements, using the DCTimer:
¾ DCTimeConnection - Connect DC Time to channel pins

¾ DCTimeMeasurementSetup - Set the mode of operation for DC

Time Measurements

¾ DCTimeCapture - Set the Stampers for the DC Time

¾ DCTimeCalculateResults – Calculate results made in the capture

¾ DCTimeEventCaptureSetup - Set the different modes of operation for

individual DC Time Stampers

Module 19 - 38

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 DC Time Connection
¾ First: Select the DCTime Connection element from the chooser and
add it to the Flow Chart Editor.

Click on
DCTimeConnection
element in the Flow
Chart Editor and
connect the pin(s).

Pins: Select <New Variable>

from drop- down list

Connection: Select “Connect”

from drop-down list

Debug Display

Module 19 - 39

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 DC Time Measurement Setup
¾ Next: Select the DCTimeMeasurementSetup element from the chooser
and add it to the Flow Chart Editor.
Click on the
DCTimeMeasurement
Setup element in the
Flow Chart Editor and
setup the pin(s).

¾Pins: Select previously

defined variable from drop-
down list

¾Measurement Type: Select

type from the drop-down
list

¾Threshold 1: Select <New

Variable> from drop-down
list

¾Threshold 2: Select <New

Variable> from drop-down
list
Sample Size: Select <New
Variable) from drop-down
list
Module 19 - 40

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 DC Time Capture
¾ Next: Select the DCTimeCapture element from the chooser and add it to
the Flow Chart Editor.
Click on
DCTimeCapture
element in the Flow
Chart Editor and setup
the DCTime Instrument
to capture.

¾Pins: Select previously

defined variable from drop-
down list

¾Catpure Action: Select from

the drop-down list

¾Capture Label: Select <New>

Variable from drop- down list These are DSPWave
objects
¾Stamper 1 Measurement:
Select <New>
Variable from drop- down list Note:Should add a wait time
between capture and calculate
¾Stamper 2 Measurement: based on the frequency and
Select <New> number of samples of signal.
Variable from drop-down list
Module 19 - 41

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 DC Time Calculate Results
¾ Next: Select the DCTimeCalculateResults element from the chooser and
add it to the Flow Chart Editor.
Click on
DCTimeCalculateResults
element in the Flow
Chart Editor and setup the
DCTime Instrument to
capture.

¾Pins: Select previously defined variable

from drop-down list

¾Stamper 1 Measurement: Select

previously defined Variable from drop-
down list

¾Stamper 2 Measurement: Select

previously defined Variable from drop-
down list

¾Average Measurement: Select <New>

Variable from drop-down list
These are
¾Measurement: Select <New> DSPWave
Variable from drop-down list
objects
Module 19 - 42
¾Measurement Type: Select type from
the drop-down list - confidential -
 DSP Procedure
¾Next: Select a DspProcedure element from the chooser and add it to the Flow
Chart Editor.
Click on the DspProcedure
element in the Flow
Chart Editor and setup the
DSP Procedure.

¾DSP Procedure Name: Select procedure

from the drop-down list. These are a
user created VBT DSP Procedures

¾RunMode: Select from the drop-down

list

¾dataAsDSPWave: Select a DSPWave

object that was defined in the Calculate
test element

¾Variable Name(s) Select new variable

from the drop-down list. Change
variable names in variables table.
Number of variables is determined by
number of arguments in VBT DSP
Procedure.

Module 19 - 43

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 Limits
¾Next: Select a Limits element from the chooser and add it to the Flow Chart
Editor.
Click on the Limits
element in the Flow
Chart Editor and setup the
limits.

¾Result: Select previously defined

variable from the drop-down list. This
variable is defined as rise_time As
double in the DspProcedure

¾Low Limit: Select <New>

Variable from drop-down list

¾High Limit: Select <New>

Variable from drop-down list
¾
¾Units: Select from the drop-down list

¾Datalog Comment: Add optional

comment as a string

Module 19 - 44

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 DC Time Event Capture Setup
¾ The Event Capture Setup lets you do individual Stamper Programming
Select the element from the chooser and add it to the Flow Chart Editor.

Click on
DCTimeEventCapture
element in the Flow
Chart Editor and setup
the DCTime
Instrument to capture
events.

¾Pins: Select previously

defined variable
from drop-down list,
Other Choices: This element
allows you to program each
individual stamper
In this example Stamper 1 is
being used to trigger another
on board instrument

Module 19 - 45

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 Time Measurement
• The number of instruments and samples will vary based on the
type of measurement being made.

– Rise and Fall Time

• Uses 2 thresholds and 2 stampers of a 1 DC Time instrument connected to a
channel

– Period
• Uses 1 threshold and 2 stampers of 1 DC Time instrument connected to a channel

– Pulse Width
• Uses 1 threshold and 2 stampers of 1 DC Time instrument connected to a channel

– Frequency
• Uses 1 threshold and 1 stamper (A) of 1 DC Time instrument connected to a
channel
– Duty Cycle
• Use 1 threshold and 1 stamper (A) of 1 DC Time instrument connected to a channel

– Pin to Pin Delay

• Uses 1 threshold and 1 stamper (A) of 2 DC Time instrument connected to different
channels Module 19 - 46

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 Measurement Programming
Ordering Rules

• Software determines ordering by making the first

stamper time difference the smallest
• Max time delay when using the CalculatedResults
methods = 671ms/2 = 335.5ms
• If the delay is greater than above, the ordering will be
incorrectly generated
• Can work around this by not using
CalculatedResults!

Module 19 - 47

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Debug Displays

Rev0343
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 Debug Display
• Use the DCTime Debug Display to debug test
programs with the Step functions.

Module 19 - 49

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 DC Time
Dib Access
Output

Time
Stampers
To
channels

Threshold
Values

To Trigger
Start control: Lines 1 and 2
Input
Slope
Module 19 - 50

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Input Info
Mode:
Stamper: connects to
the time stamper
On Board Trigger:
connects to Trigger 1
and 2
DIB Trigger: connects
Output Pin

Module 19 - 51

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Choose Measurement

Choose a measurement
from a drop-down list

Module 19 - 52

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Time Stamper
Event Input:
1. None
2. Threshold 1
3. Threshold 2
4. Pattern
Slope
Sample Size

Enable Input
Slope
Mode

Holdoff

Module 19 - 53

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Enable
Input:
Enable Pin: A valid DCTime
channel selected from the
programmed pins, this controls
the operation of the DC Time and
enables the time stamp when a
signal should occur. An enable
signal is used to selectively
capture events.
Pattern: controls by HSD
patterns and microcode
Mode:
Trigger Each Event Stamper
must receive a trigger on its
enable input before capturing
the next event signal.
Gate Window Stamper captures
events as long as its enable
input is at the specified level
(gate_high or gate_low).

Module 19 - 54

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HoldOff
Hold-Off Mode: The hold-off mode is
used to specify which hold-off is used.
A hold off mode is used to allow time
for a signal to settle before making a
time measurement. The following
options can be selected:
• Off
• Precount Once - Time required before
stamping is counted once and then
never again.
• Precount Before - Time required
before stamping is counted before each
sample.

Module 19 - 55

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Start Input Selection

On Trigger: This button triggers the

instrument to start the
measurement/capture.
Pin: Selected from the programmed
pins, this controls the operation of the
DC Time and starts the time stamp
when a signal should occur. A start
signal is used to begin the
measurement.
Pattern: controls by HSD patterns and
microcode

Module 19 - 56

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 DCTime Alarms
• DGS over voltage alarm in the hardware
– Device ground sense not tied to ground
• Measurement incomplete alarm in the hardware
– Caused by a trigger event occurring while a measurement is in progress
• Timeout Alarm
– At the time when the user requests the data, the stamper did not get enough events to
stamp the number requested by the SampleSize
• Data lost
– Memory was overwritten by subsequent captures
• Capture not triggered
• Capture Alarm
– Instrument alarmed during capture

Module 19 - 57

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Device Ground Sense (DGS)

• Each DCTime can be connected to any of the 4 DGSs

present on the DC30/DC75 boards
– DGS connections are specified in the channel map following the
channel string
– DGS connections occur during connect
– If not specified in the channel map, there is a default DGS used
• It is best to specify the wanted DGS in the channel map

Module 19 - 58

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Specifying DGS in ChanMap
DGS 1 DGS 2 DGS 3 DGS 4
a34 b34 c34 d34

With Specifiers:
Device Under Test Tester Channel
Pin Name Package Pin Type Site 0 Site 1
PinA DCTime 23.a2.a34 23.a10.b34
PinB DCTime 50.a2.c34 50.a10.c34

Optional DGS
Without Specifiers: Specifiers
Device Under Test Tester Channel
Pin Name Package Pin Type Site 0 Site 1
PinA DCTime 23.a2 23.a10
PinB DCTime 50.a2 50.a10

Module 19 - 59

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Default DGS for DCTime
DC30 DC75
DC30 DGS: DC30 DGS: DC75 DGS:
Sense: Sense: Sense:
1 1 11 2 1a 1
2 1 12 2
1b 1
3 2 13 1
2a 1
4 2 14 1
2b 1
5 1 15 2
6 1 16 2 3a 2

7 2 17 1 3b 2
8 2 18 1 4a 2
9 1 19 2 4b 2
10 1 20 2
Module 19 - 60

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Asynchronous Triggers

Rev0343
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 Objective

• The goal of this session is to show you how a

DCTime instrument, when receiving a signal from a
device pin, can be programmed to tell another DC
Instrument when to make a measurement.

Module 19 - 62

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 Asynchronous Triggering
• Asynchronous Triggering is when an asynchronous
signal is used to trigger an instrument
• Asynchronous Triggering on the DC30/DC75
boards is done by using the DCTime instrument to
generate the asynchronous signal

Signal to be
used to trigger DCTime
from device pin

DUT Asynchronous
Trigger Signal on
internal bus
Other
Signal to be DC Inst.
measured
Module 19 - 63

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 Asynchronous Triggers
• There are two internal trigger lines to supports
asynchronous capture of voltage and current
measurements per DCTime Instrument. These lines can be
driven by DUT pins connected to any of the V/I channels.

Internal Lines Connected to

Device pin

Module 19 - 64

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 Asynchronous Example
1. Source a ramp from the DCVI to Pin1.
2. Pin1’s threshold is exceeded and a state change occurs to pin2.
3. Signal is output from the State Change Pin to the DCTime.
4. The DCTime Front End drives the asynchronous trigger line.
5. The DC meter is set to listen to the asynchronous trigger and strobes the ramp.

pin1

Pin1_time

Module 19 - 65

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 Using Asynchronous Triggering
When Programming Asynchronous
triggering:
• Set up the DCTime doing the
triggering
• Set up the instrument to be
triggered
• Input any signal of interest
• Activate the triggering and
triggered instrument
• Input the signal that is used to do
the triggering

Module 19 - 66

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 Trigger Using Elements
Set up a DCTime on the same board
to do the triggering
– Send Output to: “On Board
Trigger”
– Set up Threshold(s)
– Set up Hysteresis and Voltage
Range
– Set up Event Input
– Start Input (Typically on trigger)
– Start Slope (Positive or
negative)
– Interleave mode (on or off)

Module 19 - 67

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 DCTime Instrument

DCTime Instrument Display

DCTime is connected to a
device pin called
pin1_time
On Board Trigger is used
Threshold is set to 2.50 volts
Voltage range is 10 volts
Input is set to on board
Trigger positive slope
Hysteresis in On, Positive

Module 19 - 68

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 Trigger Using Elements
Set up the DCVI to be triggered
by programming the DCVI’s
AsynchronousTrigger input
– Asynchronous slope (Positive
or Negative)
– Asynchronous pin (DCTime
channel)
– Asynchronous Channel type
(Either DCTime or
DCTimeHP)
– Asynchronous which (Set to
Trigger line 1 or 2)

Module 19 - 69

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 DCVI Instrument

DCVI Instrument Display

DCVI is connected to a
device pin called
pin1
Asynchronous Trigger is enabled
Slope is set to positive
Pin is set to pin1_time
Channel Type is set to DCTime
Which is set to Trigger 1

Module 19 - 70

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Triggering a DCTime Instrument

1. Set up a DCTime (1st) on the same board to do the

triggering
2. Set up the DCTime (2nd) to be triggered (use Enable
or Start to do the triggering)
3. Input the signal for the 2nd DCTime to measure
4. Trigger the 2nd DCTime
5. Input a signal into the 1st DCTime to trigger the 2nd
DCTime instrument

Module 19 - 71

- confidential -
Trigger a DCVI or DCDiffMeter
Instrument Using VBT

¾ thehdw.DCVI.Pins("VIPin").AsynchronousTrigger
.SetInput pinName, ChanType, Which
– PinName = name of the pin attached to the DCTime instrument (triggering
instrument)
– ChanType = channel type of the pin attached to the DCTime instrument
(“DCTime” or “DCTimeHP”)
– Which = board specific, but for both the DC30 and DC75 this means which
stamper output. A “1” means stamper1, a “2” means stamper2.

Module 19 - 72

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 Triggering a DCTime in VBT

• 1st DCTime must have the Front End set up. (vrange,
hysteresis and thresholds)
• 2nd DCTime must program either it’s start or enable
input

¾ Thehdw.DCTime.Pins(“DCTime2”).Start
.SetInput tlDCTimeStartInputPin, PinName, ChanType, Which
– PinName = name of the pin attached to the 1st DCTime instrument
(triggering instrument)
– ChanType = channel type of the pin attached to the 1st DCTime
instrument (“DCTime” or “DCTimeHP”)
– Which = board specific, but for both the DC30 and DC75 this means which
threshold output. A “1” means threshold1, a “2” means threshold2.

Module 19 - 73

- confidential -
 Appendix
• DC Time Specifications • Hysteresis
• DIB Triggering • Internal Triggers
• Event • Period example
• Enable • Stamper samples
• Enable examples • Flow charts
• Holdoff • Pattern control
• Holdoff examples
• Holdoff/Enable examples
• Sample Size

Module 19 - 74

- confidential -
 Characteristics
• SIGNAL DELIVERY PATH
– Skew
• Channel-to-channel 1 ns, typical
• Trigger-to-trigger 500ps, typical
• DC30
– Range: 0 to +/- 30 V
– Ranges: 10V 50 Ohm, 10V High-Z, 30V High-Z
• DC75
– Range: 0 to +/- 75 V
– Ranges: 10V 50 Ohm, 20V High-Z, 75V High-Z
• Memory Depth: 512 samples/channel, nominal
• Resolution 1ns, typical

Module 19 - 75

- confidential -
 Characteristics

• Bandwidth
– Channel Input 5 MHz, typical
– High Performance Input 25 MHz, typical

• Clock Period 10 ns, nominal

• Interpolator
– Number of Delay Elements 20, nominal
– Delay per Element 1 ns, nominal
– Accuracy 2 ns

• RE-FIRE RATE
– Non-Interleave Mode 40 ns, typical
– Interleave Mode 20 ns, typical

• SETUP TIME
– Start to Enable Setup Time 50 ns, minimum, typical
– Enable to Event Setup Time 10 ns, minimum, typical
Module 19 - 76

- confidential -
 Characteristics
Accuracy +/- 2ns
Resolution 1ns
Range 670ms
Re-fire Rate (one stamper) Interleave on 40ns
Re-fire rate (two stampers) 20ns
Memory Depth 512 Samples
per Stamper
Stamper Enabling Time (A to B) 20ns
Time Base Error System RefClk
Error
Hystersis 10V 50Ohm, HighZ 300mv
30V HighZ 900mv

Module 19 - 77

- confidential -
 DCTime DIB Triggering
• Each DCTime instrument can trigger to the DIB via
the DIB Access channel path.
– The DC30’s and DC75’s DCTime instruments XOR the outputs of
the two comparators as the DIB Trigger signal
– Once signal is connected it is actively triggering

DC30 DC75
DCTime 0 DA 1 DA 1a,
DA 1b

DCTime 1 DA 2 DA 3a,
DA 3b

Module 19 - 78

- confidential -
 DCTime Stampers Event
1. Event: signal used to measure time (signal on which
the stampers will be recording time)
– Input: none (off), pattern (Stamp microcode), the signal from
threshold1 and the signal from threshold2
– Slope: positive or negative

– VBT Commands
¾ thehdw.DCTime.Pins("vcc").Stamper1.Event.Input =
tlDCTimeInputThreshold1
¾ thehdw.DCTime.Pins("vcc").Stamper2.Event.Slope = tlSlopeNegative

Module 19 - 79

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 DCTime Stampers Enable

2. Enable : controls when the individual stamper

is capable of stamping (“on/off”)
– Input: none (automatically enabled), pattern (microcode),
and pin
– Slope: positive or negative
– Mode: trigger each, gate window
– VBT Commands
¾ thehdw.DCTime.Pins("vcc").Stamper1.Enable.SetInput
tlDCTimeEnableInputPattern
¾ thehdw.DCTime.Pins("vcc").Stamper2.Enable.Slope =
tlSlopePositive
¾ thehdw.DCTime.Pins("vcc").Stamper1.Enable.mode =
tlDCTimeEnableModeGate

Module 19 - 80

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 DCTime Stampers Enable
Enable.Input = Pin
Enable.Mode = Gate
Enable.Slope = Positive
Triggered and started

Enable

Event

Enabled to
= Time Stamp stamp events

Note: Assuming no holdoff

Module 19 - 81

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 DCTime Stampers Enable
Enable.Input = Pin
Enable.Mode = Trigger Each
Enable.Slope = Positive

Triggered and started

Enable

Event

Enabled to
= Time Stamp stamp events

Note: Assuming no holdoff

Module 19 - 82

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DCTime Stampers Holdoff
3. Holdoff : means of delaying when the stamper is
stamping
– Mode: off (holdoff not used), precount, and before each
– Count: used to holdoff a specified number of events.
Max count = 511.
– Time: used to holdoff a specified amount of time. If programmed,
count will be set to 0
Max Time = 4.088ms
– VBT Commands
¾ thehdw.DCTime.Pins("vcc").Stamper1.Holdoff.mode =
tlDCTimeHoldOffModeBeforeEach
¾ thehdw.DCTime.Pins("vcc").Stamper2.Holdoff.Count = 5
¾ thehdw.DCTime.Pins("vcc").Stamper2.Holdoff.Time =0.00001

Module 19 - 83

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 DCTime Stampers Holdoff

Precount: wait before the first stamp

Holdoff.Count = 3
Triggered and started

Event

Pre-count Stamp Events

N=3 Events

Note: Assuming enable input = none

Module 19 - 84

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 DCTime Stampers Holdoff
Precount: wait before the first stamp
Holdoff.Time = 0.000010
Triggered and started

Event

Pre-count Stamp Events

10 µsecs

Note: Assuming enable input = none

Module 19 - 85

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 DCTime Stampers Holdoff
Before Each (Interleave Off): wait before each and every stamp

Triggered and started

Event

Hold-off N=3 Hold-off Hold-off

Events N=3 Events N=3 Events

= Stamper’s time stamps

Note: Assuming enable input = none

Module 19 - 86

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 DCTime Stampers Holdoff
Before Each (Interleave On): start waiting after the other stamper stamps
Stamper1’s Hold-off = 2
Stamper2’s Hold-off = 1

Triggered and started

Event

S2 S2
S1’s HO S1 S2 S1’s HO S1 HO 1 S2
2 Events HO 1 2 events
Stamp Stamp Stamp event Stamp
event

= Stamper1 stamps = Stamper2 stamps

= Stamper1 holdoff = Stamper2 holdoff
Note: Assuming enable input = none
Module 19 - 87

- confidential -
 DCTime Holdoff/Enable
Interleave is off.
Enable.Mode = Gate
Holdoff.Count = 3

Triggered and started

Enable

Event
Enabled Enabled Enabled

= Time Stamp = Holdoff Count

Module 19 - 88

- confidential -
 DCTime Holdoff/Enable
Interleave is off.
Enable.Mode = Trigger Each
Holdoff.Count = 3

Triggered and started

Ignored

Enable

Event

Enabled Enabled

= Time Stamp = Holdoff Count

Module 19 - 89

- confidential -
DCTime Stampers SampleSize

4. SampleSize
– Sets the number of samples that the user wants to capture
– VBT Commands
¾ thehdw.DCTime.Pins("vcc").Stamper1.SampleSize = 10

Module 19 - 90

- confidential -
 DCTime Front End

3. Hysteresis Control:
– Hysteresis is used to prevent multiple threshold crossings due to
noise
– Hysteresis can be set to “off”, “positive adjust”, “negative adjust”,
“on, no adjust”
– A setting of “off” has no hysteresis control and noise can cause
multiple threshold crossings

¾ thehdw.DCTime.Pins(“vcc”).FrontEnd.Hysteresis = tlDCTimeHysteresisOff

Î Signal must exit the hysteresis window on the opposite end

that it entered in order to reset the hysteresis
Î Without resetting the hysteresis the signal output of the
comparator will not invert

Module 19 - 91

- confidential -
 DCTime Hysteresis cont.

Hysteresis Off

Voltage

Threshold

Time

Module 19 - 92

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 DCTime Hysteresis
Hysteresis On – No Adjust (centered around threshold)
Reset Point
Stamp Points
Voltage

Threshold Hysteresis
Window

Reset Point

Time

Hysteresis is “reset” by the signal passing out of the hysteresis

window on the opposite side that it entered.
Module 19 - 93

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 DCTime Hysteresis cont.
Hysteresis On – No Adjust
Voltage
Stamp Point

Threshold Hysteresis
Window

Time
Î Hysteresis reset point never reached.
Î Signal must exit the hysteresis window on the opposite
end that it entered in order to reset the hysteresis
Module 19 - 94

- confidential -
 DCTime Hysteresis cont.
Hysteresis On – Positive Adjust
(adjusted to above threshold)

Reset Point
Stamp Points
Voltage

Hysteresis
Threshold Window

Reset Point

Time
Module 19 - 95

- confidential -
 DCTime Hysteresis cont.
Hysteresis On – Negative Adjust
(adjusted to below the threshold)

Reset Point
Stamp Points
Voltage

Threshold
Hysteresis
Window

Reset Point

Time
Module 19 - 96

- confidential -
DCTime Internal Trigger Lines
None Stamper1 Trigger
Threshold1 slope Line 1
Pattern select Event
slope Mode
None Enable
Stamper1’s select select

Enable Pin Pattern Holdoff

Time/
Off count SampleSize
Precount select
BeforeEach
Threshold2 Interleave

Stamper2 Trigger
None slope
select Event Line 2
Pattern slope Mode
Enable
select select
Stamper2’s None
Holdoff
Enable Pin Pattern Time/
ON count SampleSize
Start Pin Off select
OFF Precount
Trigger BeforeEach
Module 19 - 97

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DCTime Internal Triggering
• The internal trigger lines can be used to trigger another
instrument on the SAME board.
• The event input of the stamper must be set (to either
threshold1 or threshold2)
• Once signal is connected it is actively triggering
(“Trigger” command not required)

Module 19 - 98

- confidential -
 1 Stamper’s Samples

• Each Stamper has a memory depth of 512.

Triggered and started

Event

Capture Memory
= Time Stamp
640.02ms
655.89ms
669.77ms
512
016.13ms
Note: Assuming enable input = none Samples
and holdoff is off
Module 19 - 99

- confidential -
 1 Stamper’s Samples cont.
• Each stamper “unwraps” it’s data
Capture Memory Returned Data
640.02ms 640.02ms
655.89ms 655.89ms
669.77ms 669.77ms
016.13ms 687.22ms

16.13ms + Max_Clock_Time = 16.13ms + 671.09ms = 687.22ms

• Because time stamp 4 (016.13ms) is less than time stamp

3 (669.77ms) it is assumed that the stamper wrapped.
There is no bit in hardware to allow the driver to know that
the clock wrapped

Module 19 - 100

- confidential -
 2 Stamper’s Samples
Stamper1’s Memory
640.02ms
Triggered and started
655.89ms
669.77ms
512
016.13ms
Samples
Event 1

Event 2
Stamper2’s Memory
642.10ms
658.03ms
= Time Stamper 1
000.54ms
= Time Stamper 2 512
018.43ms
Samples

Note: Assuming enable input = none

and holdoff is off
Module 19 - 101

- confidential -
 2 Stamper’s Samples cont.
Stamper1’s Memory Stamper1’s Returned Data
640.02ms 640.02ms
655.89ms 655.89ms
669.77ms 669.77ms
016.13ms 687.22ms Rise Time Results
2.08ms
2.14ms
1.86ms
2.30ms
Stamper2’s Memory Stamper2’s Returned Data
642.10ms 642.10ms
658.03ms 658.03ms
000.54ms 671.63ms
018.43ms 689.52ms

Module 19 - 102

- confidential -
 2 Stamper’s Samples cont.

• Each stamper’s data is always unwrapped

individually
• If the clock wraps between stamper1’s and
stamper2’s first set of stamps no unwrapping will
occur between the two sets of data
• The user must manage this or use the CalculateResults
methods (discussed later) to perform their
measurements

Module 19 - 103

- confidential -
2 Stamper’s Samples cont.
Stamper1’s Stamper1’s
Memory Returned Data
669.77ms 669.77ms
016.13ms 687.22ms RiseTime
Results
032.03ms 703.12ms
001.86ms
048.16ms 719.25ms
002.30ms
002.43ms
001.83ms

Stamper2’s Stamper2’s Stamper2’s Translated

Memory Returned Data Data (by CalculateResults)
000.54ms 000.54ms 671.63ms
018.43ms 018.43ms 689.52ms
034.46ms 034.46ms 705.55ms
049.99ms 049.99ms 721.08ms

Module 19 - 104

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 Period Example

• Want to take a period measurement of a signal that

goes from –5V to 5V
• Want the threshold to be the mid point
• Want to take the positive slope
• Want 10 data points
• Don’t need any special start/enable/holdoff signals

Voltage
5V
0V
-5V
Time

Module 19 - 105

- confidential -
 VBT Period Example
'Set up
With thehdw.DCTime.Pins("vcc").Measurement.Period
.SetVoltageRange 5, tlDCTimeImpedanceHiZ
.Threshold = 0
.Hysteresis = tlDCTimeHysteresisOnPosAdjust
.Slope = tlSlopePositive
.Start.SetInput tlDCTimeStartInputOnTrigger
.SampleSize = 10
End with

'Connect
thehdw.DCTime.Pins("vcc").Connect

Module 19 - 106

- confidential -
 VBT Period Example cont.
'Set up the signal to be measured before trigger is called

'Trigger the capture

thehdw.DCTime.Pins("vcc").TimeStamps.Trigger "Period1"

thehdw.Wait 0.01 ‘must wait long enough for all samples to be taken.

Dim pld1 As IPinListData, pld2 As IPinListData

Dim pldResults As IPinListData

'Get data and calculate period

thehdw.DCTime.Pins("vcc").TimeStamps("Period1").GetWaves pld1, pld2
Set pldResults = thehdw.DCTime.Pins("vcc").Measurement.Period.
CalculatedResults(pld1, pld2)

'Disconnect
thehdw.DCTime.Pins("vcc").Disconnect
Module 19 - 107

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DCTime Dual Stamper Flow
IDLE

Trigger Command
Wait for
Start

Start signal False

received

True
Dual
Stampers
Activated
Module 19 - 108

- confidential -
DCTime Stamper Flow

False
Dual Wait for
Stampers Enable signal
Enable And
Activated received
Interleave
True

False Interleave
satisfied

True

Wait for
Holdoff

Module 19 - 109

- confidential -
 DCTime Stamper Flow

Wait for
Holdoff True Wait for
Holdoff
satisfied Event

False
Event signal False
received

True

True Sample size False

achieved

IDLE Dual
Stampers
Activated
Module 19 - 110

- confidential -
 DCTime Pattern Control
Pattern Control
The DC instruments can be controlled by patterns and microcode allowing
changes to instrument states and parameters during a program. A very
accurate level of control can be obtained by programming an instrument
with microcodes, patterns and psets.
There are three forms of pattern control:
1. Microcode A microcode controls a single function, such as gating a V/I on or off or starting a
waveform segment for example.
2. Psets A PSET defines a programmed state for an instrument, so that a DC V/I PSET
contains parameters such as voltage and voltage range. When an instrument receives a
PSET from the pattern, it goes to the programmed state represented by that PSET.
3. Pattern A pattern is created independently of the test program, by using the Pattern Tool.
Patterns are composed of a series of numbered digital vectors that define the data for each
channel listed in the pattern and the pattern microcode for controlling pattern execution.

This is an Advanced topic and will be covered in a later

module.

Module 19 - 111

- confidential -
 Module 19 - 112

- confidential -
Visual Basic for Test

Rev0343
- confidential -
Objectives- Visual Basic for Test

• Understand the Visual Basic(VB)

Integrated Development Environment(IDE)
basics
•Introduce the FLEX/VBT extensions of IDE
(class objects used by FLEX: theHdw,
theExec, theVars, DSPWave)
•LABS and code RUNS using VBT

Module 20 - 2
- confidential -
Specific Objectives -1
•VB-environment
•Editor
•Object browser
•Project explorer
•Watch window
•Immediate window
•Properties window
•Immediate mode debugging

Module 20 - 3
- confidential -
Specific Objectives -2
•VB Paradigm
•Form creation
•Code structure
•Delimiters
•Parameters
•Data types
•Syntax
•Constructs
•Standard functions

•IDE (Integrated Development Environment)

Module 20 - 4
- confidential -
Specific Objectives -3
•VB-VBA-VBT
•How VB is used with
Microsoft applications as a
support language
•How VBT for Flex extends
this support to:
•Hdw
•Exec
•Vars
•DspWave

Module 20 - 5
- confidential -
 Specific Objectives -4
4 ways of calling standard VB from FLEX text
1. Call interpose function (constructed in VB) from a
Test Template
2. Call interpose function from a FLEX test procedure
3. Call VBT function from test instance worksheet
4. Call DSP procedure written in VB from a FLEX test
procedure

Module 20 - 6
- confidential -
 Session 1
•Introduction to Visual Basic
•Overview of IDE paradigm
•Relate IDE paradigm to FLEX paradigm
•Intro IDE environment

Module 20 - 7
- confidential -
 VB: What Is It?
• Visual Basic For Test is an
extension of Microsoft
Visual Basic. It is the Visual Basic = VB
Teradyne specific code and
objects.

• Microsoft products like

Word, Excel and PowerPoint Visual Basic for
use a version of VB called applications = VBA
Visual Basic for Applications
as a scripting language.

• IGXL uses the VBA

Visual Basic For
development environment
Test = VBT
in Excel, and this is where
the VBT code is written.

Module 20 - 8
- confidential -
 VB: What Is It?

Visual Basic = VB
• We will first introduce the
Visual Basic core language

• Visual Basic is the

foundation on which Visual Basic for
Microsoft builds Visual Basic applications = VBA
for Applications (VBA),
which is a scripting code
package integrated in all
office products
Visual Basic For
Test = VBT

Module 20 - 9
- confidential -
 Visual Basic Fundamentals
Variables
Dim variable_name As type

Dim myName As String

Dim count As Integer
‘Declaring Arrays
Dim counters(14) As Integer
Dim sums(20) As Double

Constants
Const const_name As type = expression

Const PI As Double = 3.14159265

Const ZERO As Integer = 0

Module 20 - 10
- confidential -
 Visual Basic Fundamentals
If… Statement
If condition1 Then [statements]
ElseIf condition2 Then [statements]
: optional

Else [statements]
End If

If bin_number = 3 Then
MsgBox “Fatal Error!”
ElseIf bin_number = 2 Then
MsgBox “Warning!”
Else
MsgBox “Test successful!”
End If

Module 20 - 11
- confidential -
 Visual Basic Fundamentals
Looping Structures
• Do While … Loop
Do While condition Do While result = “fail”
[statements] result = myFunc()
Loop Loop

• Do … Loop Until
Do Do
[statements] result = myFunc()
Loop Until [condition] Loop Until result = “pass”

• For … Next Statement

For counter = start To end [Step Increment]
[statements] For count = 0 to 100
Next [counter] result = myFunc()
Next count

Module 20 - 12
- confidential -
 Visual Basic Fundamentals
Procedures
1) Subroutine Procedures (no return value)
Sub proc_name (param1 As type1, param2 As type2,…)
[Sup procedure code]
End Sub
Sub display_message (info As String)
MsgBox info
End Sub
2) Function Procedures (return a value)
Function proc_name (param1 As type1, param2 As type2,…) As type
[Function procedure code]
proc_name = [return_value]
End Function
Function Square (d As Double) As Double
Square = d * d
End Function

Module 20 - 13
- confidential -
 Visual Basic Fundamentals
Working With Objects
A newly dimensioned Class Object can be thought of as a pointer to an object
Before a class object can be used, it must have its reference set
The Set keyword is used with object to set references (have a pointer point to
something)
The New keyword is used to allocate memory for class objects
The Set and New keywords are used in conjunction to set up Class Objects for use

Dim myObject as SomeObjectType ‘create variable

Set myObject = New SomeObjectType ‘allocate new object

Dim myObject as New SomeObjectType ‘create and allocate

Module 20 - 14
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 Visual Basic Fundamentals
With Construct
Enable multiple properties setting and methods calling within the same
object

With Object
[Statements]
End With

The following two example code sets are equivalent

With txtName.Font
.Bold = True
txtName.Font.Bold = True
.Size = 24
txtName.Font.Size = 24
.Type =
txtName.Font.Type = “Arial”
“Arial”
End With

Module 20 - 15
- confidential -
Visual Basic Fundamentals

Note the Appendix Sections for

Further Details

Module 20 - 16
- confidential -
 VBA: What Is It?

• The next topic is Visual Visual Basic = VB

Basic for Applications (VBA)

• VBA is a Visual Basic

environment built into
Microsoft Office products Visual Basic for
and is used for scripting applications = VBA
and extending the software

• Teradyne uses the VBA

environment to implement Visual Basic For
IGXL functionality Test = VBT

Module 20 - 17
- confidential -
 IDE Overview
The Visual Basic For Applications (VBA) editor which is part of Excel is where VBT
code is written and debugged
The VBA Editor is an Integrated Development Environment (IDE) with different
tools in dockable windows which can be customized by the user

IDE
Environment for VB,VBA,VBT

Project Properties Code Form

Browser Editor Editor Editor

Immediate Watch Locals Object Debug

Window Window Window Browser Tools

Module 20 - 18
- confidential -
 IDE
Project Browser
Properties Editor
Code Editor

VBA IDE
Form Editor
Immediate Window
Watch Window
Locals Window
Object Browser
Debug Tools

• Visual Basic for Applications is where the user accesses Visual Basic code. Alt + F11
• The Project explorer is located in the upper left hand section of the VBA window. It
holds the VB code associated with DataTool, Templates, and VBAProject.
• To access the folders within each project, it is necessary to expand the column using
the (+) that is to the left of each segment.

Module 20 - 19
- confidential -
 IDE
Project Browser
Properties Editor
Code Editor

VBA Environment
Form Editor
Immediate Window
Watch Window
Locals Window
Object Browser
The Visual Basic For Applications (VBA) editor which is part of Excel is Debug Tools

where VBT code is written and debugged

The VBA Editor is an Integrated Development Environment (IDE) with
different tools in dockable windows which can be customized by the user

Menu Bar

Project Tool Bar

Browser

Development
Area with
two code
modules
open

Properties Immediate
Window Window

Module 20 - 20
- confidential -
 IDE
Project Browser
Properties Editor
Code Editor

VBA Project Browser

Form Editor
Immediate Window
Watch Window
Locals Window
Object Browser
Debug Tools

The Project Browser Class

displays a implementations
are created in
hierarchical list of
separate modules Open
the projects and all Projects
of the items Project for
contained in and current test
referenced by each program
of the projects
Forms Folder
The project called stores instance
VBAProject editors and
corresponds to the custom user forms
users test program,
the DataTool and User code is
written in
Template projects
code
are opened as well modules
because the
VBAProject has References
references to those indicate other
projects projects to open
with this project

Module 20 - 21
- confidential -
 IDE
Project Browser
Properties Editor
Code Editor

VBA Properties Editor

Form Editor
Immediate Window
Watch Window
Locals Window
Object Browser
Debug Tools

Object whose
properties are
being displayed

Name of
selected object
The Properties Editor
lists the design-time
properties for Different
property types
selected objects and
may have
their current settings different
These values can be property editors
(color choosers,
edited by the user enumerated
types, etc.)

The properties
list changes
depending on
the type of
object selected

Module 20 - 22
- confidential -
 IDE
Project Browser
Properties Editor
Code Editor

VBA Code Editor

Form Editor
Immediate Window
Watch Window
Locals Window
Object Browser
The code editing window is where all programming will occur Debug Tools

The editor is ‘Smart’ and will automatically correct typos, report

syntax errors, complete declarations and prompt the user for
necessary information

Choose/create
the routine to be
edited

The color of text

indicates
comments
(green) and
keywords (blue)

VBA separates
different code
routines with line
dividers

Toggle between
viewing all code
or just one
procedure

Module 20 - 23
- confidential -
 IDE
Project Browser
Properties Editor
Code Editor

VBA Form Editor

Form Editor
Immediate Window
Watch Window
Locals Window
Object Browser
Debug Tools
Forms are an integral part of VB
The instance editors used by test templates are
VB forms, and the Instance Editor Wizard in the
Procedure Development Environment dynamically
creates forms depending on your procedure
elements
Forms can be created and edited easily in the
VBA environment and are made up of a set of
controls

The forms toolbox This form was generated by

should pop up while a The properties of any the Wizard, controls can be
form is being edited, if selected form or control moved and edited easily, and
not choose ‘Toolbox’ can be edited with the new controls can be added
from the ‘View’ menu properties window using the toolbox

Module 20 - 24
- confidential -
 IDE
Project Browser
Properties Editor
Code Editor

VBA Form Editor Code

Form Editor
Immediate Window
Watch Window
Locals Window
Object Browser
Debug Tools
Forms are made up of the visible
interface and the code behind each
of the controls
Event handlers can be written for the
form elements and add the
functionality to the elements

Use the dropdowns to

choose a form
element and to pick
an event to create or
edit

Use these buttons on

the project browser to
view the code or form
for a form object

Module 20 - 25
- confidential -
 IDE
Project Browser
Properties Editor
Code Editor

VBA Immediate Window

Form Editor
Immediate Window
Watch Window
Locals Window
Object Browser
Debug Tools
The Immediate window is a very valuable debug and feedback
tool in VBA, to show this window select it from the view menu or
press Ctrl+G while in the VBA environment
Code can be tested and called from the Immediate window just by
typing the code and pressing Enter
Users can make VB code write messages to the immediate
window using the Debug.Print statement, this is useful for viewing
debug information

Print the results of

operations by typing ‘print’
followed by the operation
Call routines by typing the
name of the routine and
typing ‘Enter’

Module 20 - 26
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 IDE
Project Browser
Properties Editor
Code Editor

VBA Watch Window

Form Editor
Immediate Window
Watch Window
Locals Window
Object Browser
Debug Tools

Watch Window
The Watch Window is with three
used to keep track of variables added
the values of
variables while Right click to
stepping through edit watches
code in debug mode
Bring up this window
by selecting Watch
Window from the
View menu
Watches are added
using the Add Watch
dialog, bring this up Add a watch:
select the
by right clicking in expression to
the code watch, where to
development area or watch it and
watch window and how to watch it
selecting Add Watch

Module 20 - 27
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 IDE
Project Browser
Properties Editor
Code Editor

VBA Locals Window

Form Editor
Immediate Window
Watch Window
Locals Window
Object Browser
Debug Tools
The Locals Window shows a hierarchical view of all variables and
objects visible in the current procedure call, to view this window
select Locals Window from the View menu
This window can only be used during debug and is empty unless
you are stepping through code

Currently
executing code,
click on … to
bring up call
stack

List of all
variables and
objects, values
and types

Module 20 - 28
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 IDE
Project Browser
Properties Editor
Code Editor

VBA Object Browser

Form Editor
Immediate Window
Watch Window
Locals Window
Object Browser
The object browser displays the classes, properties, methods, Debug Tools

events, constants and procedures in your project and referenced

by you project. You can use it to find and use both your own
objects and system objects.

Invoke the
object browser
by pressing F2 or
selecting it in the
view menu

This example
shows the valid
settings of the
“enumerated
type”
BpmuIRange

Module 20 - 29
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 IDE
Project Browser
Properties Editor
Code Editor

VBA Object Browser

Form Editor
Immediate Window
Watch Window
Locals Window
Object Browser
Debug Tools
Library to search Search Search
or browse Term results

The Object Browser

can also search
local code libraries
to find classes and
functions.

Here are the results Method

from searching for Property
event
‘dspwave’.

Class Member Members of

Browser info selected class

Module 20 - 30
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 IDE
Project Browser
Properties Editor
Code Editor

VBA Debug Tools

Form Editor
Immediate Window
Watch Window
Locals Window
Object Browser
Debug Tools

VBA has many

debug tools
Code does not
need to be
compiled to run A breakpoint,
click in the gutter
VBA checks or press F9 to
toggle
syntax on the fly
Next line of code
to be run, the
arrow can be
dragged

Debug Hotkeys
Mouse over a
F5 Run variable to
display the value
F8 Step
Immediate
Shift+F8 Step over window (ctrl+G)
Type code here
Ct+Sh+F8 Step out for immediate
execution

Module 20 - 31
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 IDE

VBA Programming/Debugging
Project Browser
Properties Editor
Code Editor
Form Editor

Tool: Auto Complete Immediate Window

Watch Window
Locals Window
Object Browser
Debug Tools

• The Auto Complete features of Visual Basic accelerate programming

• VB will list functions and members for

programming objects when the user
types the name of the object followed
by a period

• As the user types, the dropdown list will scroll to the proper region
and highlight the first match, use arrows to navigate the list and the
tab key to auto complete the selected entry

• If a function is selected, VB will show a

prompt with the function arguments

• This lets the user explore and experiment without a manual or a list
of functions

Module 20 - 32
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 IDE
Project Browser

VBA Programming/Debugging Tool:

Properties Editor
Code Editor
Form Editor

Integrated Online Help Immediate Window

Watch Window
Locals Window
Object Browser
Debug Tools

Invoke help by pressing F1, the system is context sensitive

Module 20 - 33
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 Session 2
•Introduction to VBT
•Interface w/FLEX (VBT class objects)
•Calling methods
•Calling interpose function from template
•Calling interpose function from FLEX procedure
•Call VBT function from test instance worksheet
•Call DSP procedure written in VB from a FLEX
procedure

Module 20 - 34
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 VBT: What Is It?

Visual Basic = VB
• The next topic is Visual
Basic for Test (VBT), a code
level interface to the FLEX
test system
Visual Basic for
• Visual Basic for Test is an applications = VBA
extension of the Visual
Basic language, with
Teradyne created objects
and functions implementing
tester functionality Visual Basic For
Test = VBT

Module 20 - 35
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 VBT: Uses
• Here are some cases where VBT code is used:

Interpose Functions Test Templates

Custom functions Customized or user
for test procedures written test
and test templates templates

DSP Procedures VBT Element Functions

DSP language code Custom VBT

for DSP analysis element functions
for test procedures

Module 20 - 36
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 VBT Uses Standard VB Subroutines
This is an example of a Visual Basic Subroutine
A Subroutine is a code procedure that can take arguments but does not return a
value

Scope of Function Arguments

Name of
Subroutine (none in this case)
Subroutine
(public/private)

Local Variable
Declarations

Subroutine Conditional Statement

delimiters (if…end if)

(sub…end sub)
VB will create
end sub

theHdw object

Module 20 - 37
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 VBT Uses Standard VB Functions
This is an example of a Visual Basic Function
A Function is a code procedure that can take arguments and return a value

Name of Function Function

Function Arguments Return Type

Function Looping Statement

delimiters (for…next)
(function…end
function)
VB will create
end function

Module 20 - 38
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 VBT Uses Special Class Objects
hdw object, theHdw
• VBT is built around Class Objects which
Contains tester
contain tester language functions programming functions
and instrument objects

• Class objects are a software abstraction of

some object or concept, they can contain exec object, theExec
functions, variables and other class objects Contains functions and
objects to control the test
executive
• All but the DspWave object are global
objects and do not need to be created by ProcVars obj, theVars
the user Used with test procedures to
access and modify a
procedures local variables
• For these objects, type through code

the name of the object

followed by a period to DspWave object
get a dropdown list of Represents a set of samples
and the functions to
functions and objects analyze the samples

Module 20 - 39
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 VBT: Tester Hardware: theHDW Object
BBACCapture Program BBAC
Capture Instrument
Contains Test
Computer Computer Details
Program DCVI
DCVI Instrument
Program the state
TheHdw (hdw object) ExtUtility of utility bits
Memory Test
MTO Option
Pin object,
Pins program by pin
Pin Parametric
PPMU Measurement unit

See Appendix for complete detailed list

TheHdw is an object that provides access to properties and methods relating to the
test system hardware
It is a global instance of an ‘hdw’ object and does not need to be created by the user
The properties and methods for the TheHdw object are themselves objects
corresponding to the instruments used for testing

Module 20 - 40
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 VBT Uses Special FLEX Objects
(theHdw), Example

This example shows how to disconnect the relays to a list of digital

pins and then reconnect the same relays.
First type thehdw. and a popup list with valid parameters
appears.

Module 20 - 41
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 VBT Uses Special FLEX Objects
(theHdw), Example Cont.
The completed
example shows
relay re-connection

VBT prompts for any

expected input
parameters

VBT prompts the user for any required parameters, in this case
the argument is a string specifying the pins
VBT lists all the properties and methods of an object when a
period is typed.

Module 20 - 42
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 VBT: Test Executive: theExec Object
Datalog Object, set
Datalog up datalog
Error Object, set
Error error behavior

ExcelHandle Excel Object,

access excel
Flow Object, flow
TheExec (exec object) Flow control functions
Boolean Valid
JobIsValid indicator
RunOptions
RunOptions object, set options
Function to restart
StartDataTool DataTool

See Appendix for complete detailed list

TheExec is an object that provides access to properties and methods relating to test
execution and flow
It is a global instance of an ‘exec’ object and does not need to be created by the user
The properties and methods for the TheExec object are themselves objects

Module 20 - 43
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 VBT Uses Special FLEX Objects (theExec),
Example

The previous example is extended to use functionality from

theExec to write an optional message to the datalog indicating that
the relays have been set

Module 20 - 44
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VBT Uses Special FLEX Objects (theExec),
Example Cont.

The plus sign can be

used to concatenate
strings.
This code will write
the pins specified in
argv(0) followed by
“ relay is set”

Select
“WriteComment” to
send a string to the
datalog

Module 20 - 45
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 VBT: DSPWave Object
The DspWave object is used in writing DSP functions, it represents a
set of samples and functions on those samples.
Unlike the other objects covered, there can be multiple DspWave
objects and they can be created by the user.

Module 20 - 46
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 VBT: TheVars Object
The TheVars object is used with user created test procedures.

TheVars is used to access the user variables in a test procedure

through code, the user can get the value of any variable in the Variable
Table or store a new value.

TheVars is a global instance of a ProcVars object and does not need to

be created by the user.

MyVariable = theVars(“varName”, [site]) ‘get variable from variable table

theVars(“varName”, [site]) = MyVariable ‘write value back to variable table

theVars.IsSet(“varName”) ‘determine if variable has been set

The optional site number parameter is used when the variable should
not be uniform to all sites, if the variable is the same for all sites, this
parameter can be omitted.

Module 20 - 47
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 VBT: IPinListData
Returns a pin object
Pin for a given pin name
Returns a set of
Pins pin objects
Returns list of
IPinListData object Sites sites
Is the value the
IsUniform same for all sites
Value of result
Value (only if uniform)

Measured value for

Value the given pin/site
Name of selected
Name pin
Channel of
Chan selected pin/site
Is the value the
IsUniform same for all sites

IPinListData variables are returned as the result of instrument measurements

The object contains measured values for a set of pins and sites, as well as
information about each pin and channel
Module 20 - 48
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 VBT: IPinListData
An example of the IPinListData object in code
The object is used to hold a DCVI measurement, then the result for a
particular pin and site is extracted from the object as a double

'create variable to hold result

Dim IDDMeas As IPinListData

'make a DCVI measurement, store result

Set IDDMeas = thehdw.DCVI.pins(MeasPin).Meter.read(tlStrobe, NumSamp, SampRate)

'extract the result from the iPinListData object

result = IDDMeas.pins(MeasPin).Value(theExec.Sites.SelectedSite)

Module 20 - 49
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 VBT: ParametricResult
Get/set individual
PinData pin results
Get/set individual
ChanData channel results

ForceCondition Access the force

condition value
Name of this
ParametricResult object VarName variable
Get sample count
NumSamples
Get/set current site
SiteNum number
Launch a view
View form for the result

The ParametricResult object is used to access the full results of a

parametric test
Parametric result data types are returned by different test elements and
contain parametric results for a set of pins and sites with additional
information about the test conditions and setup, this information is
used for data logging purposes
Module 20 - 50
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 VBT: ParametricResult
An example of the ParametricResult object in code
A set of samples for a pin is extracted from the existing
ParametricResult object meas1, the samples are then averaged

Public Function ResultAverage(paramRes1 As ParametricResult, AvgResult As Double)

Dim pinName As String 'name of pin
Dim i As Integer 'loop variable

pinName = paramRes1.PinList(0) 'get pin name

For i = 0 To paramRes1.NumSamples - 1
AvgResult = AvgResult + paramres1.PinData(pinName, i) 'sum samples
Next i

AvgResult = AvgResult / paramRes1.NumSamples 'get the average

End Function

Module 20 - 51
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VBT: Code Examples
Interpose VBT from Test
Functions Template

VBT Test VBT from Test

Element
Functions Procedure

VBT VBT from VBT

Functions Test Type

VBT VBT from Test

Functions Instance Sheet

DSP
Procedure DSP Procedure
Function

Module 20 - 52
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 VBT: Interpose Functions

The calling convention for an interpose function is:

Public Function name (argc As Long, argv() As string) As Long
For example:
Public Function SetFlag (argc As Long, argv() As string) As Long

argc specifies the number of arguments to the function, and argv() is an

array of strings which hold each argument. Interpose functions use argc
and argv() to process arguments.

The instance editor allows the entry of a comma separated list of

parameters for each interpose function. When the interpose function is
called by the test instance the arguments are translated to the argc,
argv() format and are passed to the function.

Interpose functions can return the constants TL_SUCCESS (0) or TL_ERROR

(1), if TL_ERROR is returned IGXL will halt execution.

One Interpose Function is called for all sites during a test.

Module 20 - 53
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 VBT: Interpose Functions Modules

Interpose functions
must be written in a
module placed in
the Modules folder
of the VBAProject

Interpose functions are part of the test program workbook and are
added using Excel’s built in Visual Basic editor. All functions written
here are saved with the workbook.
Visual Basic can be invoked by pressing Alt+F11 or by selecting
Tools->Macro->Visual Basic Editor

Module 20 - 54
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 VBT: Interpose Functions Modules

A finished interpose
function ready to be
called by a test
instance

With your VBAProject selected in the project browser, select Insert->Module in the menu
to add a new module. The module is placed in the Modules folder, and in this file is
where interpose functions are written with Visual Basic for Test.

Module 20 - 55
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VBT: Code Examples
Interpose VBT from Test
Functions Template

VBT from Test

Procedure

VBT from VBT

Test Type

VBT from Test

Instance Sheet

DSP Procedure

Module 20 - 56
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 VBT: Test Templates Overview

• Templates provide generic

structured test actions using
values saved in the workbook. Current Templates
Functional_T
• Arguments that are specified in
PinPmu_T
the workbook are applied to
PowerSupply_T
template’s PreBody (test
Empty_T
initialization), Body (Test), and
MtoMemory_T
PostBody (Cleanup) functions at
runtime.

Module 20 - 57
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VBT from Test Templates Customization
Using Interpose Functions

At certain defined points, the test templates

can execute a user-written interpose function,
if one exists

Interpose Functions allow the user to modify

the behavior of a Test Template without the
need to dissect the template and modify
internal code

Module 20 - 58
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 VBT from Test Templates: Interpose
Function Insertion Points
There are seven types of hooks in each test template where a custom
Interpose function can be called:

StartOfBodyF: Called as the first operation in the template body.

PrePatF: Called before each pattern burst.

PreTestF: Called before the test is executed or the measurement is made.

PostTestF: Called after the test is executed or the measurement is made.

PostPatF: Called after each pattern burst.

EndOfBodyF: Called as the last operation in the template body.

PatFlagFunc : Called to modify tester setups while the pattern is running.

All interpose functions are executed within the body portion of the test
template.

Module 20 - 59
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VBT from Test Templates: Interpose Tab

After an interpose function is

written, it can be called by a test
template. The name of the
function is entered in the instance
editor for that test

For each interpose function,

specify a function name (value)
and an optional comma-
separated list of parameters .
The parameters are passed to
the function as an array of
strings.

Module 20 - 60
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 VBT from Test Templates: Pattern Flag Tab

The Functional Test Template

includes a PatFlagF parameter,
specifying a function to be called
when certain flag conditions are
met
The Pattern Flag Function tab
within Instance Editors can be
used to modify tester setups while
a pattern is running

Specify a function name (value)

and an optional comma-
separated list of parameters.
Select the pattern flags for
which to execute the function.

Module 20 - 61
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 VBT Interpose Functions Called From Test
Templates: 2 Examples

Interpose
VBT code can be function
required format
called from test
templates to modify
Using theHdw
their functionality
to program the
These functions are ppmu voltage
called “Interpose
Functions”
Interpose Functions
must follow a specific
function declaration
format
These two functions
will be added to a
test template to
program a ppmu VB ‘With’ construct
voltage and then (with… end with)
disconnect the ppmu

Module 20 - 62
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 VBT from Test Templates: Inserting
Previous Examples Into Templates
User name for Template Interpose functions and arguments are
test instance to use specified on the Interpose Functions tab

Interpose functions are added to

test template instances using the
instance editor
The Interpose Functions tab has
inputs for interpose function
names and input arguments

Function name Fuction arguments as

from vbt code a comma separated list

Module 20 - 63
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 VBT from Test Templates: Instantiating
Template and Adding to Flow Table

The test instance that calls the

interpose functions is then added
to the flow table
The modified test instance can
now be run

Module 20 - 64
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VBT: Code Examples
Interpose VBT from Test
Functions Template

VBT from Test

Procedure

VBT from VBT

Test Type

VBT from Test

Instance Sheet

DSP Procedure

Module 20 - 65
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 VBT Interpose Functions: Used by Test
Procedures

Test Procedures are a more

flexible way to develop
tests
The user can build a test
using test elements, which
is much more flexible than
test templates
Like test templates,
procedures can call custom
code in interpose functions
Procedures can also call
DSP language code with
the DspProcedure element

Module 20 - 66
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 VBT Interpose Function Called From Test
Procedures

Same interpose
Interpose Function format
code can also be
called from test
procedures to modify
their functionality
theVars object
Interpose functions
for procedures follow
the same rules as
templates
This code will connect
the DA relay of a set
of specified pins

Module 20 - 67
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 VBT from Test Procedures (hard coded): Inserting
Previous Examples Into Flow Chart Editor

Interpose function code is called

by a procedure with the
Interpose element
The interpose element allows
input of the name of the
interpose function and the
function arguments as a comma
separated list
In this case, the function name
and arguments are hard coded
instead of being left as instance
editor inputs

Module 20 - 68
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 VBT from Test Procedures: Instantiating a Procedure
and Adding it to the Flow Table

Use _TP to specify

test procedures for
The Test Procedure needs to be readability
Instantiated on the Test
Instances worksheet
If the interpose function
information has not been hard-
coded, the interpose information
is entered on the procedures
instance editor
The completed test instance is
added to the flow table to run

Module 20 - 69
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 VBT from Test Procedures - Another Case(not hard
coded): Inserting Previous Examples Into Instance Editor

Instead of hard coding the name

and arguments of an interpose
function into a test procedure,
these parameters can be
specified as inputs
When an instance of the test
procedure is created, the name
of any interpose functions and
arguments are added on the
instance editor

Module 20 - 70
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VBT: Code Examples
VBT from Test
Template

VBT Test VBT from Test

Element
Functions Procedure

VBT from VBT

Test Type

VBT from Test

Instance Sheet

DSP Procedure

Module 20 - 71
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 VBT Test Element
The VBT Test Element is a
new way to add custom
code to a test procedure
The interface is friendlier
that the interpose function
VBT Element functions can
have flexible inputs,
variables can be passed in
directly, and the element
interface adjusts to match
the chosen function
VBT Element functions
must be specified at
procedure design time,
unlike interpose functions
which can be left as input
parameters

Module 20 - 72
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 VBT Element Function
The ByVal keyword indicates only
the value of the variable is passed,
so the code cannot modify the
VBT Element Functions value of the variable
have flexible declaration
rules

No fixed
return
VBT test type
element
functions must
be contained
in VB modules
whose name
begins with
VBT so that
the software
can find them

Module 20 - 73
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 VBT Element Editor

Choose a written
function from The element
Run one
the dropdown interface
function for all
changes to
sites or one
match the
for each
selected
function

Variables are
created with
the dropdown
or hard coded
depending on
the design of
the function

Module 20 - 74
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 VBT Function and Interpose
Comparison
Interpose Functions VBT Element
Functions
Multi-Site One call for all sites, One for each site or one
user handles site for all sites, depending
Functionality variables on checkbox

Function Fixed input parameters, Flexible input parameters

argc, argv()
Definition
Rules
Flexibility Function name and Function is chosen and
arguments can be variables built into the procedure
at Test that change at run time, at design time
Instantiation flexible

Procedure Access to procedure Variables passed directly

variables through theVars as arguments to VBT
Variable object element function
Communication

Module 20 - 75
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VBT: Code Examples
VBT from Test
Template

VBT from Test

Procedure

VBT VBT from VBT

Functions Test Type

VBT from Test

Instance Sheet

DSP Procedure

Module 20 - 76
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 VBT Test Type: Function
For tests written completely in
VBT, the VBT Test Type can
be used
A function which will
The VBT Test Type allows a be called from a VBT
Test Type
VBT Function to be called
without using the Procedure
Development Environment
The VBT Test Type is another
type of test that can be chosen
from the type column on the
test instances sheet, the user
then selects a function to call
The VBT Test Type will
automatically create an
instance editor for the selected
function
Note: embedded DSP and
deferred limits cannot be used
with a VBT Test Type

Module 20 - 77
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VBT Test Type: Instantiation
Here a test instance is created for the preceding VBT function using the
VBT test type
1) The test is named
2) Type VBT is selected
3) A user written VBT Function is chosen from the dropdown list
Note: Functions called from a VBT Test Type follow the same rules as
VBT Test Element functions (flexible declaration, no fixed return type,
must be placed in a module with a name beginning in VBT)

Module 20 - 78
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VBT Test Type: Instance Editor
The instance editor for the VBT Test Type is created automatically when the function to
be called is chosen
The instance editor has a Levels & Timing tab plus tabs containing inputs for the selected
function

Module 20 - 79
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VBT: Code Examples
VBT from Test
Template

VBT from Test

Procedure

VBT from VBT

Test Type

VBT VBT from Test

Functions Instance Sheet

DSP Procedure

Module 20 - 80
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 VBT Function Called From the Test Instance
Sheet

Format is different
from interpose, no
function arguments
VBT code can also be
called directly from
the Test Instance
Sheet
This code follows a
different format than
interpose functions
This code turns off all
alarms on a set of
pins For each of these
DCVI pins, turn off
all alarms

Module 20 - 81
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 VBT from Instance Sheet: Instantiating
Function and Adding to Flow Table

Give the function an instance

name, select other as type, and
give the name of the function to
call (called as excel macro)
The function can then be called
from the flow table using the test
opcode and the specified instance
name Instance name VBT function name

Test opcode and

instance name

Module 20 - 82
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VBT: Code Examples
VBT from Test
Template

VBT from Test

Procedure

VBT from VBT

Test Type

VBT from Test

Instance Sheet

DSP
Procedure DSP Procedure
Function

Module 20 - 83
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 VBT DSP Function Called From a Test
Procedure

DSP Procedures are another type of

VBT that are used in test procedures
to do DSP analysis
This procedure takes in a DSPWave
object and returns the average DC
offset of part of the samples
Unlike interpose functions, a DSP
function is called for each site

DSP procedures have

Input waveform Variable for the result
flexible declaration rules

DSP functions
must be contained
in VB modules
whose name
begins with DSP
or DSP_VBT so Select 50 samples
that the software
can find them
Get the mean value

Module 20 - 84
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 VBT DSP Function Called From a Test
Procedure(hard coded): Inserting Previous
Examples Into Flow Chart Editor
The DspProcedure test element is used in the PDE to call DSP Functions
The name of the DSP procedure to be used must be hard coded in the
PDE and cannot be an instance editor input

Select a user
created DSP
procedure from
the list

The editor
changes to match
the selected DSP
procedures
arguments

The DspWave
contains the input
samples captured
previously, the
second argument
will get the result

Module 20 - 85
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 VBT DSP Function Called From a Test Procedure:
Instantiating a Procedure and Adding it to the Flow
Table

The test procedure is

instantiated on the Test
Instances sheet, where any
variable parameters are
entered
The test is the added to
the flow table and is ready
to run

Module 20 - 86
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VBT Module Naming Conventions

When using DSP functions and VBT element

functions there are restrictions on where the
code can be written so that IGXL can tell where
to look for different functions
Interpose Functions: no restrictions
VBT Element Functions: in a module starting
with VBT (not case sensitive)
VBT Test Type Functions: in a module starting
with VBT
DSP Functions: in a module starting with DSP
Offline DSP Functions: In a module starting
with DSP_VBT

Module 20 - 87
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Case Study : Sinewave Example

Reference the imported code

from the sinewave lab

Module 20 - 88
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 Session 3

•LAB
•Write several interpose functions and call
them from a test template
•View the results in the datalog

Module 20 - 89
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Checklist Self Assessment
‰VB-environment
‰Editor
‰Object browser
‰Project explorer
‰Watch window
‰Immediate window
‰Properties window
‰Immediate mode debugging
‰VBT Fundamentals
‰theHdw basics
‰theExec basics
‰theVars basics
‰DspWave basics
‰Calling VB code
‰VBT from Test Templates
‰VBT from Test Procedures
‰VBT from Test Instances Sheet
‰VBT DSP from Procedures

Module 20 - 90
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Appendix

Module 20 - 91
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 Session 4

•Review using Quickhelp VB Summary page

Module 20 - 92
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Quick Help VB Summary 1

Module 20 - 93
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Quick Help VB Summary 2

Module 20 - 94
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Quick Help VB Summary 3

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Quick Help VB Summary 4

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 VB Data Types
Selected Data Types:
Type Bytes Range Type Byte Range
s
boolean 2 True/False integer 2 -32,768 to 32,767

byte 1 0-255 long 4 -2,147,483,648 to

2,147,483,647

string N/A 64K char for single 4 -3.402823E38 to –1.301298E-

fixed, 2 billion 45 for Neg
for variable 1.301298E-45 to 3.402823E38
for Pos

object 4 N/A double 8 -1.79769313486232E308 to

-4.94065645841247E-324 for
Negative
4.94065645841247E-324 to
1.79769313486232E308 for
Positive

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 VB Operators
Common Operators (in precedence order):
Arithmetic Comparison Logical
Exponent ^ Equality = Not Not

Negation - Inequality <> And And

Multiply,Divide * / Less Than < Or Or

Integer Divide \ Greater Than > Exclusive Or Xor

Modulus Divide Mod Less Than or Equal <= Equivalence Eqv

Add,Subtract + - Greater Than or >= Implication Imp

Equal
String Concatenation & Like Pattern Like Is The Same Object Is

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 VB Math Functions
Visual Basic Math Functions:
Absolute Value Abs() Log Log()

Arc Tangent Atn() Random Number (0-1) Rnd()

Cosine Cos() Sign(-1, 0 or 1) Sgn()

Exponentiation Exp() Sine Sin()

Fix Places Fix() Square Root Sqr()

Integer Value Int() Tangent Tan()

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 theHdw Members
Members of the hdw class object:

Alarms alarms object, allows dumpstate and enable all

BBACCapture BBAC capture object, set up for a given list of pins
BBACSource BBAC source object, set up for a given list of pins
Boards Boards object
ChanFromPinSite return channel of given pin at given site with given type
Computer computer object, get information like processor speed and user name
DCDiffMeter DCDiffMeter object
DCTime DCTime object
DCVI DCVI object
DGSConnected boolean value, is DGS connected
DIB DIB object, has EEPROM, power options, etc.
Digital Digital setup object
DSSC DSSC object
ExtUtility ExtUtility object, used to control state of utility bits
MTO MTO object, controls memory test option functionality
PinLevels pin levels object, used to connect and disconnect pins, appy power, etc.
Pins pins object allows by pin programming
PinSiteFromChan get a pin site and name from the channel and type
PPMU PPMU object
ReadStopwatch read elapsed time in seconds from start/last read
SetSettlingTimer set a value for settle time
SettleWait wait a certain amount of time for settle
StartStopwatch start stopwatch timing
Utility utility bits object
Wait wait for a specified number of seconds
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 theHdw.Digital Members
Members of the digital (theHdw.Digital) class object:

ACCalExcludePins specify pins excluded from TDR calibration

ACCalSetTDRLevels specify non-default voltage levels that should be calibrated to during TDR calibration
ChannelFailed see if a channel failed the last burst
connectPins connect device pins
disconnectPins disconnect device pins
FailedPinsCount get the count of failed pins at a given site
FreqCtr frequency counter functions
HRAM history RAM driver functions
KeepAlive keepAlive functions
Patgen pattern generator driver functions
Patterns pattern loader driver functions
PinSiteFailed see if a given pin at a given site failed the last burst
PinSiteFromChan get the pin name as site number for a given channel
SyncEnabled get the sync pulse enable state of a channel
SyncModeOn program the channel's timing and format to be able to produce a sync pulse
SyncPulseOff disable sync pulse generation
SyncPulseOn output a sync pulse on a channel when a pattern is run
SyncPulseOn channel board timing driver functions

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 theExec Members
Members of the exec class object:

AddOutput sends a message to the output window

CalibrateTDR validates and runs TDR calibration
ClearAllEnableWords set the value of all created enable words to false
CurrentChanMap get or set the name of the current channel map
CurrentEnv get or set the name of the current environment
CurrentJob get or set the name of the current job
CurrentPart get or set the name of the current part
Datalog datalog object, lots of options
DataManager data manager object
DevChar access active data object or data object collection
EnableWord create, access and modify enable words
Error error object, set behavior and message destination
ErrorCloseLogfile close error log file
ErrorLogfileName path to error log text file
ErrorLogMessage write an error log message
ErrorMessageToLogfile write a string to the log file
ErrorOutputMode mode number
ErrorReport create error report
ExcelHandle excel object, use to access worksheets, excel options, etc.
ExecutionCount run count of test program
Flow flow object, lots of flow control functions
JobIsValid boolean valid indicator
MSTimingContext mstimingcontext object, context name, slice name, slice count
Rootpath path to install directory
RunMode mode number
RunOptions run options object
RunTestProgram run the current test program
Simulator simulator object, two functions to run simulator
Sites sites object
SoftwareBuild software build number
SoftwareVersion software version number
StartDataTool start data tool
StopDataTool stop data tool
TesterMode current mode of tester
Timer takes an optional time reference, returns a time difference?
Validate validate the test program
VariableValue get the value of a variable in a given test Module 20 - 102
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 VBT: Get and Set Properties

• The Properties of an Object work in two ways (get and set):

– Get property returns the value of the object

Limit = thehdw.PPMU.Pins("a1").ForceIRange.Max ‘get value

– Set property stores a value on the Tester

thehdw.PPMU.Pins("a1").ForceIRange.Max = 2.3 ‘set value

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 VBT: Top Level “Pins” Property

Use the Pins property to focus on the DUT pins to be worked

with rather than the instruments to be used

Note:Timing edges are read from hardware to Memory,

modified in memory, then written back to the hardware.

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 Session 5

•Case study 1
•Add a simple and useful
feature to IGXL using VBT
•Discuss process and code
•LAB Æ run code and
modify

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 Custom Code Example (Case Study 1)
This subroutine will display a
This is an example of a custom configuration file specified by ‘FilePath’
subroutine used to extend the
capabilities of IGXL
This code will display
configuration files from the IGXL
install directory
The code can be called by custom
IGXL menu items

Three use cases for this subroutine

The IGXL environment can be extended
to call custom code

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 Session 6

•Case study 2
•Example of creating a class object
•Explain object oriented programming
•Intro key object oriented programming
terms and concepts
•Discuss use of class objects
•Discuss example code and run code LAB

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 Object Oriented Coding
Object-oriented programs are made up of objects. An object packages both
data and the procedures that operate on that data. The procedures are typically
called methods or operations. An object performs an operation when it
receives a request(or message) from a client.

Requests are the only way to get an object to execute an operation. Operations
are the only way to change an object’s internal data. Because of these
restrictions, the object’s internal state is said to be encapsulated; it cannot be
accessed directly and its representation is invisible from outside the object.

From “Design Patterns” by Gamma, Helm, Johnson and Vlissides

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Visual Basic: Class & Object

Class is an abstract data type

composed of properties and
procedures.
Properties are a set of data Class class_name
describing characteristics of the
Properties
class
:
Procedures are a set of methods
used to retrieve, modify the Procedures
properties or to perform particular - Subs
actions
- Functions
In object-oriented programming,
properties should be hidden and can
only be accessed through
procedures (Data Encapsulation)

Module 20 - 109
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Visual Basic: Class & Object
Object is an Instance of the Class

Class Car
Properties
- PS
- Mileage
- Year
- Color
Instantiate
Procedures
Sub start( )
Sub stop( )
Sub speedup( ) Object myCar
Function displayCurrentSpeed()

In Visual Basic Object can be Example:

instantiated using the following
Set myCar = New Car
syntax:
or
Dim object_name As class_name
Dim myCar As New Car
Each procedure can be called as
follow: :
object_name.proc_name myCar.start()
myCar.speedup()
V = myCar.displayCurrentSpeed()
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User Type Example: A Type Contains
Variables Only
User Types can easily be created
and used in visual basic
This example shows a dummy
type that stores information for a
device pin

Type definition Using the new The example is

with type name Type in code, run from the
and member the type shows immediate
variables up as a new window to show
variable type results

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 Case Study 2: User Class Example in Code: A Class
Contains Both Variables and Operators(Functions)

Creating a User Class is a little more involved than a

User Type
User Classes are created in separate Class Modules
Here we see a User Class called Histogram used in
code, this example type will take the samples from a
DSP wave and create a histogram of the data

The Histogram
Data type is
created like any
Input data other class
comes from a object
DSP Wave
Get data from
DSPWave object
and plot the
Read data back
hisogram
out of Histogram
to DSPWave and
plot
Flexibility achieved through encapsulation, see next page

Module 20 - 112
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 Case Study 2: User Class Example Implementation Part 1

Implementation Part 1 of 3
Here is the first part of the code that creates the
Histogram Class implementation

Initialization
routine is called Private data
whenever this members, not
type of class directly
object is created accessible,
and is used to public members
set up the class would be
object for use
Property Let is
used to create
an interface for
Property Get is this object, Let
another part of allows this
interface object to have a
creation and is value passed in
used to write out by the user
the value of a without giving
given parameter direct access to
to the user internal data

These methods are used

to achieve encapsulation
Module 20 - 113
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 Case Study 2: User Class Example Implementation Part 2

plotHistogram is
an externally
visible method
The function used to tell this
checks for errors class object to
before calling plot a histogram
two hidden of internal data
functions to
create the
histogram
The hidden
function
CreateHistogram
churns through
the input data
and creates a
histogram array

The code counts

how many data
elements lie
within ranges of
length
IntervalWidth

Module 20 - 114
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Case Study 2: User Class Example Implementation Part 3

The hidden
function
showHistogram
takes the
histogram array
and loads it into
a display form

The output form

was designed as
a new form in
the forms folder
of the test
project, the
MSChart control
was used to
display the data

Controls are selected from the

toolbox window, the MSChart
control was added by right
clicking on the toolbox,
selecting ‘additional controls’
and checking Microsoft Chart
Control
Module 20 - 115
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 Case Study 2: User Class Example Function Results

Here are the results of

running the example
code
The histogram shows
the number of
elements in the input
waveform that appear
in different ranges
The waveform is the
multitone data that
the histogram class
operates on

Module 20 - 116
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 Session 7
•Case study 3
•How to use THE vars,
exec,hw,dspwave
•Use of intellisense
•Key example of elements after
DOT
•Example code for all types of
objects in VBT
•LAB the use of types and
summary code using sinewave, etc.
•Summary of Objectives via a
checklist self assessment

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VBT for Test Procedures

Rev0343
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 Outline

• Test design techniques using as case study a regulation test

• Test development with procedures and the VBT element
• Case Study 1:VBT IDD test example
• Case Study 2: DCVI lab example converted to VBT
• Case Study 3: DCVI lab example with VBT Test Type
• Additional Considerations: Site loop creation, Limits, etc.
• Best programming techniques summary
• Good programming practices highlighted by test program rewrite
• Appendix

Module 21 - 2
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 Topic

9 Test design techniques using as case study a regulation test

• Test development with procedures and the VBT element
• Case Study 1:VBT IDD test example
• Case Study 2: DCVI lab example converted to VBT
• Case Study 3: DCVI lab example with VBT Test Type
• Additional Considerations: Site loop creation, Limits, etc.
• Best programming techniques summary
• Good programming practices highlighted by test program rewrite
• Appendix

Module 21 - 3
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Regulation Test Design Examples
The next set of slides covers several methods of building a regulation test:
• Standard method *
• Hard coded IMAGE translation method
• IMAGE translation with variables method
• IMAGE translation with nested procedures method
• VBT method **
The advantages* and disadvantages of each approach will be discussed

Module 21 - 4
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Regulation Test: Standard
This is a standalone regulation test
that can be reused for different test
situations

Module 21 - 5
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Regulation Test: Hard Coded
This is the result of directly
translating an Image regulation test
to a FLEX test procedure
The procedure makes three
measurements with different setups
This procedure has several
weaknesses:
1) All the inputs are hard coded, this
test can only be used once for a hard
coded set of pins
2) The limits are tested one at a time
when the current limits element can
test all limits in a procedure at once
3) The length of the procedure
makes it difficult to figure out what
the test is doing
4) The same set of elements are
repeated three times

Module 21 - 6
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Regulation Test: Variables
This is a slightly improved version of
the regulation test
The element inputs are now variable
so the test procedure can be reused
for different pins or different setups

Module 21 - 7
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Regulation Test: Nested Procedures
Another way to implement
the test is with nested test
procedures
This is a procedure that sets
up a test, makes a
measurement, and stores
the result to a global
variable using VBT
This procedure will be
nested inside another
procedure

Module 21 - 8
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Regulation Test: Nested Procedures
This test calls the previous
nested procedure three times
and uses the VBT element to
retrieve the stored results
The limits for all three
measurements are tested at
once, and the test flow from the
nested procedure is reused
The number of elements has
not dropped by much though

Module 21 - 9
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Regulation Test: VBT
Another way to implement the
test is with the VBT element
A VBT function runs the setup and
measurement flow and returns
the results to the procedure
The Limits element checks the
results to finish the test
See the VBT code on the next
slide

Module 21 - 10
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 Regulation Test: VBT
Public Function DCVI_Reg(pinlist1 As String, pinlist2 As String, voltage1 As Double, _
current1 As Double, voltage2 As Double, current2 As Double, _
measvarname As String, pinlistout As String)
Dim dcvi_result As IPinListData This is the VBT function
Dim thisSite As Long that runs the regulation
With thehdw.DCVI.Pins(pinlist1) test
.CurrentRange.Autorange = True
.Current = current1 The code sets up the
source pin and capture
.VoltageRange.Autorange = True
.Voltage = voltage1
.Mode = tlDCVIModeVoltage pin, then connects and
gates on both pins
.Gate = False
End With

With thehdw.DCVI.Pins(pinlistout) After a programmed

wait the measurement
.Current = current2
.CurrentRange.Autorange = True
.Voltage = voltage2 is made and the results
.VoltageRange.Autorange = True
.Mode = tlDCVIModeCurrent are returned to the
.Mode = tlDCVIMeterVoltage procedure for each site
.VoltageRange = voltage1

This function makes

.Gate = False
End With
one measurement, and
thehdw.DCVI.Pins(pinlist2).Connect
thehdw.DCVI.Pins(pinlist2).Gate = True the function can be
thehdw.Wait (0.03)
Set dcviresult = thehdw.DCVI.Pins(pinlistout).Meter.Read(tlStrobe, 1, 10000)
easily extended to
make more
For thisSite = 0 To theexec.Sites.ExistingCount
If theexec.Sites.Site(thisSite).Active Then
thevars(measvarname, thisSite) = dcvi_result.Pin(0).Value(thisSite)
End If
Next thisSite ' Site loop

End Function
Module 21 - 11
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 Topic

• Test design techniques using as case study a regulation test

9 Test development with procedures and the VBT element
• Case Study 1:VBT IDD test example
• Case Study 2: DCVI lab example converted to VBT
• Case Study 3: DCVI lab example with VBT Test Type
• Additional Considerations: Site loop creation, Limits, etc.
• Best programming techniques summary
• Good programming practices highlighted by test program rewrite
• Appendix

Module 21 - 12
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Extending Test Development Using VBT
Where Does VBT Fit Into the overall use model

The Flexibility of the IG-XL programming platform allows tests to be

developed with different techniques
The user can use a predefined test template, create their own test
procedure using test elements, or use the VBT element to build tests at the
code level

Test Templates Test Procedures

Teradyne supplied User designed tests
test templates using procedures

Procedures/VBT Elements
VBT Test Type
A mix of procedure
Test written entirely
elements and VBT
in VBT, no usage of
elements
PDE

Module 21 - 13
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When To Use The VBT Element Approach

Revised User Model - Some guidelines for

choosing to implement a test using VBT
elements:
•When the same operations are being done in
many places in the test program, convert that
set of elements to a VBT function
•Tests that contain complicated logic and/or
loops should be implemented in VBT
•Tests that contain complicated instrument
setup sequences should be written in VBT,
especially if many options are possible or
measurements affect the setup

Module 21 - 14
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 How To Use The VBT Element Approach
Former Use Model Revised Use Model - Even more options

Test Elements Test Elements Hybrid Procedures

Standard test procedures Standard test procedures Procedures with elements
written primarily with test written primarily with test and VBT functional blocks
elements elements forming the test flow
Maximizing elements Mixing elements with VB

Hybrid Procedures Hybrid Procedures VBT Procedures

Test procedures with Test procedures with Test procedures with most of
elements and Interpose elements and Interpose the functionality done in VBT
Functions Functions elements (levels/timing and
limits still done in elements)

Mixing elements with VB Minimizing elements, mostly VB

Function changeable at run time
VBT Test Type
Test written entirely in VBT,
PDE is not used, Limits and
levels/timing must be done
in code

Entirely in VB
Module 21 - 15
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Where PDE Framework Advantages
Still Apply, Using the VBT

By writing VBT tests taking advantage of PDE the test

designer can use the benefits of:
• Limits Element
• Levels and Timing Element
• DSP Procedures Element
• Deferred Binning
…Use PDE elements when and where appropriate
• Instance Editor Wizard

Module 21 - 16
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 Topics

• Test design techniques using as case study a regulation test

• Test development with procedures and the VBT element
9 Case Study 1:VBT IDD test example
• Case Study 2: DCVI lab example converted to VBT
• Case Study 3: DCVI lab example with VBT Test Type
• Additional Considerations: Site loop creation, Limits, etc.
• Best programming techniques summary
• Good programming practices highlighted by test program rewrite
• Appendix

Module 21 - 17
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Case Study1-VBT IDD Test: Flow

The following example is an IDD test from a production

test program
The test is built in PDE with a Levels and Timing element
and a Limits element
The testing is done in two VBT elements that run the
same test with different input parameters

Module 21 - 18
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Case Study1-VBT IDD Test: Flow
This is the test flow
for the Run_Idd_TP
test
The LevelsTiming
element is used,
followed by two
VBT elements
which run the same
VB test but with
different input
parameters
The results of both
VBT tests are
checked in the
limits element

Module 21 - 19
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 Case Study1-VBT IDD Test: Function
RunIddTest is the VBT function
called by both VBT elements
Public Function RunIddTest(PatName As String, StartLabel As String, _
MeasPin As String, MeasWaitTime As Double, _ (1) A pattern is started using a
NumSamples As Long, SampleRate As Double, _
ResultVarName As String) As Long user written function, (2) the
mode of the measure pin is set,
(3) a pattern flag is reset, (4)
Dim IDDMeas As IPinListData

1 Call StartPatternWaitFlagA_1(PatName, StartLabel) followed by a wait for the flag

2 thehdw.DCVI.pins(MeasPin).Meter.Mode = tlDCVIMeterCurrent
to be set again by the pattern

'set cpuA flagA to 0 and let pattern continue to the next cpuA loop
(5) A programmed wait occurs
3
Call thehdw.Digital.Patgen.Continue(0, cpuA) (6) after which the
measurement is made
'wait for cpuA flag to be true, pattern in cpu loop
4 Call thehdw.Digital.Patgen.FlagWait(cpuA, 0)
(7) The pattern is halted (8) and
'perform meas wait a user written function is called
5
thehdw.Wait (MeasWaitTime) to return the test results
'perform MCU IDD measurement
6
Set IDDMeas = thehdw.DCVI.pins(MeasPin).Meter.read(tlStrobe, NumSamples, SampleRate)

'halt pattern
7
Call thehdw.Digital.Patgen.Halt

'set return values

8
Call SetReturnVar_IPD(ResultVarName, IDDMeas.pins(0))

End Function

Module 21 - 20
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Case Study1-VBT IDD Test: Support
These are user written support functions called from the previous code
The first will start a pattern and wait until the pattern sets the cpuA flag
The second is used to return the results contained in an IPinData object to the
procedure variables table using a site loop and the name of the variable in the
variables table

Public Function StartPatternWaitFlagA_1(ByVal PatName As String, ByVal StartLabel As String)

'start pattern
Call thehdw.Digital.Patterns.Pat(PatName).Start(StartLabel)

'wait for cpuA to be 1

Call thehdw.Digital.Patgen.FlagWait(cpuA, 0)

End Function

Public Function SetReturnVar_IPD(ByVal VarName As String, MeasResult As IPinData)

Dim SiteStatus As Long, thisSite As Long

SiteStatus = theexec.Sites.SelectFirst
Do While SiteStatus <> loopDone
thisSite = theexec.Sites.SelectedSite
thevars(VarName, thisSite) = MeasResult.Value(thisSite)
SiteStatus = theexec.Sites.SelectNext(loopTop)
Loop ' Site loop

End Function

Module 21 - 21
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 Topics

• Test design techniques using as case study a regulation test

• Test development with procedures and the VBT element
• Case Study 1:VBT IDD test example
9 Case Study 2: DCVI lab example converted to VBT
• Case Study 3: DCVI lab example with VBT Test Type
• Additional Considerations: Site loop creation, Limits, etc.
• Best programming techniques summary
• Good programming practices highlighted by test program rewrite
• Appendix

Module 21 - 22
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Case Study2-Referencing Previous
DCVI Lab Exercise

The next example shows the Force_and_Measure_DC test

from the DCVI test elements lab and the equivalent VBT
example

Module 21 - 23
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Case Study 2: Elements
This is the
Force_and_Measure_DC test
implemented in elements
The pins are connected, the
source and capture pins are
set up, there is a wait, the
measurement is made, the
result is tested against limits,
Previous course exercise the instruments are reset and
used elements only, no gated off, and the pins are
VBT disconnected

Test Elements
Standard test procedures
written primarily with test
elements

Maximizing
elements

Module 21 - 24
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 Case Study 2: VBT Element
This is the same
Force_and_Measure_DC
test implemented primarily
in the VBT element
The VBT element handles
setup, connection,
Minimizing elements, measurement and cleanup
mostly VB
The results from the VBT
VBT Procedures element are tested with the
Test procedures with most of limits element
the functionality done in VBT
elements (levels/timing and Why do we pass the hard coded
limits still done in elements) string name of the variable
instead of the actual variable?
The code manually creates a
site loop it has to return results
to each site, this is done with
theVars object that needs the
name of a procedure variable
and a site number

Module 21 - 25
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 Case Study 2: the VBT under the VBT Element
Public Function Vreg(ByVal
ByVal
inputpin As String, ByVal outputpin As String, _
inputcurrent As Double, ByVal Vin As Double, _
This is the user designed
ByVal NumSamples As Long, ByVal SampleRate As Double, _ VBT element function
ByVal LoadCurrent As Double, Vout_VarName As String) that implements the DC
test
Dim VMeas As IPinListData 'object to store measurement
Dim thisSite As Long 'index of current site

With thehdw.DCVI.Pins(inputpin) 'setup force pin The function is designed

.Connect to receive the information
.Meter.Mode = tlDCVIMeterVoltage
.Meter.Filter.Value = 5000
to do the test from the
.Meter.VoltageRange.Value = 10 input parameters
.Current = inputcurrent
.Voltage = Vin This first half of the
.VoltageRange.Autorange = True function sets up the
.Gate = True
End With source and capture pins
and waits a specified
time
With thehdw.DCVI.Pins(outputpin) 'setup measure pin
.Connect
.Meter.Mode = tlDCVIMeterVoltage
.Meter.Filter.Value = 5000 The function is continued
.Meter.VoltageRange.Value = 10 on the next slide
.Current = LoadCurrent
.Voltage = 0
.VoltageRange.Autorange = True
.Mode = tlDCVIModeCurrent
.Gate = True
End With

thehdw.Wait (2 * ms) 'wait

Module 21 - 26
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Case Study 2: the VBT under the VBT Element cont.
After the wait, the measurement is made and stored in the IPinListData
object (which stores data for all sites)
Since the Execute in Site Loop checkbox on the VBT element was not
checked, the function manually loops through the sites and returns the
results to the procedure variable table using TheVars
The pins are then disconnected and gated off
'perform voltage measurement
Set VMeas = thehdw.DCVI.Pins(outputpin).Meter.read(tlStrobe, NumSamples, SampleRate)

'extract v meas for each site from ipinlist data and stick in procedure variable
'note that we are extracting 1st pin in pin array of ipinlist data
For thisSite = 0 To theexec.Sites.ExistingCount - 1
If (theexec.Sites.Site(thisSite).Active) Then
thevars.Value(Vout_VarName, thisSite) = VMeas.Pin(0).Value(thisSite)
End If
Next thisSite

'disconnect pins
With thehdw.DCVI.Pins(inputpin & "," & outputpin)
.Gate = False
.Disconnect
End With
End Function

Module 21 - 27
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 Topics

• Test design techniques using as case study a regulation test

• Test development with procedures and the VBT element
• Case Study 1:VBT IDD test example
• Case Study 2: DCVI lab example converted to VBT
9 Case Study 3: DCVI lab example with VBT Test Type
• Additional Considerations: Site loop creation, Limits, etc.
• Best programming techniques summary
• Good programming practices highlighted by test program rewrite
• Appendix

Module 21 - 28
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Case Study 3- Previous DCVI Lab
Exercise With VBT Test Type

The next example shows the VBT version of

Force_and_Measure_DC test from the DCVI test elements
lab with modifications to be used with the VBT Test Type

Module 21 - 29
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 Case Study 3: VBT Test Type Instance and
Instance Editor

These are the test instance and instance

editor for the VBT Test Type version of
the previous example
The test is done entirely in VBT, and the
instance editor is created for the user by
the VBT Test Type
The VBT function from the previous
example needs slight modifications to
work as a VBT Test Type Function

VBT Test Type

Test written entirely in VBT,
PDE is not used, Limits and
levels/timing must be done
in code Module 21 - 30
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 Case Study 3: the VBT under the VBT Test Type

Public Function Vreg(ByVal inputpin As String, ByVal outputpin As String, _

ByVal inputcurrent As Double, ByVal Vin As Double, _
ByVal NumSamples As Long, ByVal SampleRate As Double, _ This is the code from the
ByVal LoadCurrent As Double) 1
Dim VMeas As IPinListData 'object to store measurement previous example with
2 some modifications to
With thehdw.DCVI.Pins(inputpin)
.Connect
'setup force pin
work with the VBT Test
.Meter.Mode = tlDCVIMeterVoltage Type
.Meter.Filter.Value = 5000
.Meter.VoltageRange.Value = 10 The primary difference is
.Current = inputcurrent that the limits will be
.Voltage = Vin
.VoltageRange.Autorange = True tested in the function and
.Gate = True not passed back to a
End With
procedure
With thehdw.DCVI.Pins(outputpin) 'setup measure pin
.Connect The code is continued on
.Meter.Mode = tlDCVIMeterVoltage the next slide
.Meter.Filter.Value = 5000
.Meter.VoltageRange.Value = 10
Note 1: Vout_VarName As String
.Current = LoadCurrent
removed
.Voltage = 0
.VoltageRange.Autorange = True
.Mode = tlDCVIModeCurrent Note 2: Dim thisSite As Long
.Gate = True removed
End With

thehdw.Wait (2 * ms) 'wait

Module 21 - 31
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Case Study 3: the VBT under the VBT Test Type
The modified code does not need a site loop to return results to a test
procedure
Using theexec.Flow.TestLimit allows results for all sites to be tested at
once by using the IPinListData object returned by the DCVI .Meter
statement
Note 1: Site Loop Removed

'perform voltage measurement

Set VMeas = thehdw.DCVI.Pins(outputpin).Meter.read(tlStrobe, NumSamples, SampleRate)
1
'test vmeas results for all sites
theexec.Flow.TestLimit VMeas, 4.95, 5.05, , , , unitVolt

'disconnect pins
With thehdw.DCVI.Pins(inputpin & "," & outputpin)
.Gate = False
.Disconnect
End With

End Function

Datalog output from limits VBT statement

Module 21 - 32
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 Topics

• Test design techniques using as case study a regulation test

• Test development with procedures and the VBT element
• Case Study 1:VBT IDD test example
• Case Study 2: DCVI lab example converted to VBT
• Case Study 3: DCVI lab example with VBT Test Type
9 Additional Considerations: Site loop creation, Limits, etc.
• Best programming techniques summary
• Good programming practices highlighted by test program rewrite
• Appendix

Module 21 - 33
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 Additional Consideration:
Pattern Management

When starting a pattern in VBT, the user must

take care of the loading of patterns

‘load the pattern

Call thehdw.Digital.Patterns.Pat(PatName).Load

‘start the pattern at the specified start label

Call thehdw.Digital.Patterns.Pat(PatName).Start(StartLabel)

Module 21 - 34
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 Additional Consideration:
Levels and Timing in VBT
Levels and Timing can be applied and controlled in VBT using theHdw.PinLevels,
theHdw.Digital.Timing, and theHdw.Digital.ApplyLevelsTiming

A view of the
members of
theHdw.PinLevels

.ApplyPower method

theHdw.Digital.Timing is
used to set up digital timing
information for patterns

theHdw.Digital.ApplyLevelsTiming can apply

the currently selected pin levels and timing

Module 21 - 35
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 Additional Consideration:
Limits Testing in VBT
Test Limits can be done in VBT using a single exec statement: theexec.Flow.TestLimit
This will test the selected result against supplied limits and write the result to the datalog
Here is the VBT auto-complete popup showing the optional input parameters

.ApplyPower method

Two examples of testing limits

in VBT, Note: Optional
parameters with default values
can be skipped with a comma

Datalog results for the second limits call shown above, Note:
the pin name and units parameter are clearly reflected in the
datalog output

Module 21 - 36
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 Additional Consideration:
Creating a Site Loop, First Type
When different operations need to be done for each site in VBT, a site loop
is used
The site loop selects each active site one after another, and will activate
the corresponding hardware and software for programming
Do not use this type of site loop when simply returning variables to a
procedure

Dim siteStatus As Long 'status of site loop

Dim thisSite As Long 'current selected site

'try to select the first site

siteStatus = TheExec.Sites.SelectFirst

'do site loop until siteStatus indicates all sites complete

Do While siteStatus <> loopDone
'get the number of the current site for use in code
thisSite = TheExec.Sites.SelectedSite

'
' do per site operations
'

'try to select the next site

siteStatus = TheExec.Sites.SelectNext(loopTop)
Loop

Module 21 - 37
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 Additional Consideration:
Creating a Site Loop, Second Type

This simpler site loop does not activate the hardware and software for
each site, it simply checks each site to see if it is active
If the site is active the loop does the specified per site operations
Use this type of site loop when returning variables to a procedure

Dim thisSite As Long 'current selected site

‘select each site one after another

For thisSite = 0 To theexec.Sites.ExistingCount - 1

‘if the site is still active

If (theexec.Sites.Site(thisSite).Active) Then

thevars.Value(Vout_VarName, thisSite) = VMeas.Pin(0).Value(thisSite)

End If

Next thisSite

Module 21 - 38
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 Test Time Resulting from Site Loop
Architecture
When the Execute in Setup and
When a VBT element is executed

Time
measurement
Site Loop checkbox is for multiple sites, if the Execute
checked, a separate in Site Loop checkbox is not
VBT function will run selected, the setup and
for each site serially, measurement for all sites can be
Return
and the results will be results
done in parallel
returned to the
The VBT function must handle
appropriate site Setup and returning of results in a site loop
variables measurement

internal site loop

Setup and Setup and
VBT test without

Time
Setup and
measurement measurement measurement
Return

VBT test with

results
site loop

Site 0 results Site 0 results

Setup and
Return Site 1 results Return Site 1 results
measurement Return
results Site 2 results results Site 2 results results

Site 3 results Site 3 results

Return
results

Setup and
measurement

Return
results

Module 21 - 39
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 Topics

• Test design techniques using as case study a regulation test

• Test development with procedures and the VBT element
• Case Study 1:VBT IDD test example
• Case Study 2: DCVI lab example converted to VBT
• Case Study 3: DCVI lab example with VBT Test Type
• Additional Considerations: Site loop creation, Limits, etc.
9 Best programming techniques summary
• Good programming practices highlighted by test program rewrite
• Appendix

Module 21 - 40
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 Best Programming Techniques Recommendations
and Guidelines Summary
Hard & Fast Rules
• If you need to call a DSP Procedure you must use the DSP
Procedure element and corresponding DSPWave setup elements
• Deferred binning is only supported through the DSPProcedure
Element and Limits Element
Recommendations
• Tests that contain complicated logic and/or loops should be written
in VB. Use VBT Element to call function.
• Tests that contain complicated instrument setup sequences should
be written in VB, especially if many options are possible or if
measurements affect setups. Use VBT Element to call function.
• For common setup functions that are called by a lot of tests and
need to support a number of different options, should be written in VB
because it easier to make decisions based on input data. Use VBT
Element to call function.
Module 21 - 41
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 Best Programming Techniques Recommendations
and Guidelines Summary

Recommendations (cont.)
• Use Test Procedures or the VBT test type as a “wrapper” even when
test could be done entirely in VB. No sense re-inventing wheel for
things like LevelsTiming and Limit element. Plus, Instance Editor
creation is supported.
• Remember to design Interpose Functions into Test Procedures for
what they’re suppose to be used for, a means to customize a standard
test thereby eliminating the need to create a custom Test Procedure
for minor variations.

Module 21 - 42
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 Topics

• Test design techniques using as case study a regulation test

• Test development with procedures and the VBT element
• Case Study 1:VBT IDD test example
• Case Study 2: DCVI lab example converted to VBT
• Case Study 3: DCVI lab example with VBT Test Type
• Additional Considerations: Site loop creation, Limits, etc.
• Best programming techniques summary
9 Good programming practices highlighted by test program rewrite
• Appendix

Module 21 - 43
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Applying the Revised Use Model to an Existing Test Program:
Programming Practices and Observations resulting from a test program
rewrite exercise

• Using VBT (under the revised use model) is found to

significantly reduce the complexity of test procedures, i.e. the
number of elements.
• Using the VBT Procedures model is found to be useful. In this
model,many test procedures are mostly VBT based( that is a VBT
element, a LevelsTiming element, and Limits element) and nearly
the entire test is performed via the VBT element.
• Using the VBT Procedures model, there is a second category,
a hybrid approach. Several test procedures fall into this
category. For these tests, VBT is used as a helpful method for
taking the place of nested procedures.
• Using the VBT Procedures model, test time (using test
procedures with the VBT based test element ) tends to be faster
( than using test procedures without the VBT element).

Module 21 - 44
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Applying the Revised Use Model to an Existing Test Program:
Programming Practices and Observations resulting from a test program
rewrite exercise

• Using the VBT Procedures model, writing tests in VBT allows users to
make a minor change to a test and then re-run the test without having to
re-validate the test program, thus saving debug time.
•Using the VBT Procedures model, there are some additional
advantages when writing tests in VBT. One such advantage is the ability
to easily make changes on the fly. Another is the ability to perform
“Undo’s” in the VB environment.
• Using the VBT Procedures model, tests written in VBT allow for easier
readability and debug . In VBT, the surrounding information is clearly
and easily visible when debugging. This is found to be an enhancement
over working solely in the PDE, wherein users click on elements to view
how these elements are setup during debug.
• Using the VBT Procedures model, the new Limit element provides a
significant improvement . The new <input_parm> capability reduces the
number of input variables significantly for all the test procedures.

Module 21 - 45
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 Homework Assignment

Read the Variable Passing In IG-XL white paper, this paper contains
valuable information about:
• Communication between different IG-XL programming layers
• Job to Test Instance and Flow communication
• Interpose Functions
• Test Procedure to VBT Test Element communication
• VBT Functions and Parametric Result usage
• Test Procedure to Nested Test Procedure communication
• Test to Test Site Variables communication
• Flow to Test Enable Word communication
• IPinListData and Decomposed Pin List

Module 21 - 46
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 Topics

• Test design techniques using as case study a regulation test

• Test development with procedures and the VBT element
• Case Study 1:VBT IDD test example
• Case Study 2: DCVI lab example converted to VBT
• Case Study 3: DCVI lab example with VBT Test Type
• Additional Considerations: Site loop creation, Limits, etc.
• Best programming techniques summary
• Good programming practices highlighted by test program rewrite
9 Appendix

Module 21 - 47
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 Remember: Good Programming
Practices Apply for All Use Models
Do not use many test elements to do actions on
a set of pins when one element will do
Do not hard code all procedure values and create
multiple unique procedures when one could have
been created with variable input parameters
Try to design procedures and VBT functions that
can be debugged once and reused several times

Module 21 - 48
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PSETS

Rev0343
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 Introduction

• A Parameter Sets (PSets) is a set of values that

describe a specific instrument setup.
• PSets allow the test program to change
instrument setups on the fly without stopping
and later resuming pattern execution.
• PSets are defined in the VBT language and
invoked by the PSet micro code.

Module 22 - 2

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 How to use PSets

3 Steps:

(1) Add a new instrument-specific PSet using VBT

(2) Set the properties of the PSet using VBT
(3) Apply the PSet in the pattern using micro code

Module 22 - 3

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 How to use PSets
Step1: Add a new instrument-specific PSet using VBT

Syntax: thehdw.<instrument>.Pins(<pinName>).PSets.Add <psetName>

<instrument>: DCVI, DCDiffMeter, DCTime, BBACSource,
BBACCapture

Example: Adding a new PSet called “srcPSet” for DCVI instrument and apply to srcPin

Module 22 - 4

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 How to use PSets
Step2: Set the properties of the PSet using VBT
Syntax:
thehdw.<instrument>.Pins(<pinName>).Psets(<psetName>).<propertyName> = value
Example: Set the properties of the PSet “srcPSet” for DCVI instrument

Note:
A complete list of
properties specific to
DCVI instruments is
shown in the appendix
of this section
Module 22 - 5

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 How to use PSets
Step3: Apply the PSet in the pattern using micro code
Syntax: Pset <psetName>
Example:

Note:
The PSet Name must not
be surrounded by any
single or double quotes,
otherwise => runtime error

Module 22 - 6

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Appendix

Module 22 - 7

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Appendix

Module 22 - 8

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 Module 22 - 9

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IG-XL Mixed Signal
Development
Overview

Rev0343
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 Mixed Signal testing
Mixed Signal Test Techniques are used to setup source and capture
instruments when testing converters.

Digital Input Analog Output

Digital words
Analog instrument
representing ADC/DAC
captures the DAC
samples are
output
sourced to the
device input using DAC
a digital waveform
generator

An analog
waveform is
sourced to the Digital instrument
device captures the ADC
output
Waveform samples ADC
are represented by
Analog Input Digital Output
voltage levels

Module 23 - 2
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 IG-XL Mixed Signal Test Development

Step 1 Step 2 Step 3 Step 4 Step 5

Define the Create or re-use Build a Test Create/ Update Created or re-
digital specs, required analog Procedure using digital test use and
levels and and digital PDE, create dsp patterns to instantiate a test
timing (DUT waveshapes. functions using include source, template,
clock rate and Create mixed- VBT capture loops, procedure or
data rate). signal contexts and m/s VBT and DSP
(solve microcodes. procedure,
coherency). Insert test in
Data Tools/Sheets:
flow.
Data Tools/Sheets: Data Tools/Sheets: Data Tools/Sheets:
• PinMap/Chan Map • Test Proc. Sheet • Pattern Tool
• WaveDesigner Data Tools/Sheets:
• AC/DC Spec • PDE-Test • Pattern Sets
• Wave definitions •Instance Editor
Sheet Elements
• MS Workshop •Test Instance Sheet
• Levels MSUM using
• MS Timing Sheet • Flow Table
• Time/Edge Set elements & VBT
Sheet • DSP VBT Code

Module 23 - 3
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 Step 1a-Create Pinmap/Channel Map
Device Pin-Out Diagram

Module 23 - 4
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Step 1b-Digital Specs/Levels/Timing Setup
Digital Interface Specs

Module 23 - 5
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 Step 2-WaveDesigner
Vertically-sliced,
extensible library of
basic and complex
functions

The WaveDesigner tool

helps create complex,
reusable test waveforms
using an extensible built-in
library of waveform
Embedded
primitives
WaveScope
allows checking
of the created
waveforms

Module 23 - 6
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Step 2a-Coherent Timing Solutions
Mixed-Signal Workshop Clock Coherency Solutions

Module 23 - 7
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Step 3 - Test Procedure Design
Procedure Development Environment (PDE)
1

Test Procedure Flow

Module 23 - 8
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 Step 3a-Applying timing solution
to instrument using Elements
Load from Mixed Signal Workshop Define Manually using Variable names

Module 23 - 9
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Step 3b - DSP Design Using VBT
FLEX DSP Software: complete, extensible library of DSP algorithms
Complex DSP functions can be added using standard VB language

Module 23 - 10
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Step 4 - Create M/S Test Pattern

Mixed Signal
Microcodes

Selecting Microcodes

Module 23 - 11
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Step 5 - Test Instance Editor
2

Instance Editor
Forms can be
modified in
VBA

Module 23 - 12
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Step 5a-Test Procedure Instantiation

Flow Table Sheet

Module 23 - 13
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Step 5b - Define Test Sequence

Note: The Test

Various OpCode’s Sequence can’t be
are available
validated before Test
Instances have been
defined.

Module 23 - 14
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Wave Designer

Rev0343
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 Wave Designer: Introduction
Consider the problem of defining wave shapes to be sourced in mixed signal
testing
Instead of creating a set of samples that may have to be recreated if the test
program changes, it would be useful to define the shape of a waveform separate
from the sampling information (which would be generated somewhere else)
By doing this, waveform shape definitions can be reused and do not have to be
changed if sampling parameters are changed
The same definitions can also be used to create both digital and analog inputs

Digital Input Analog Output

ADC/DAC
Digital words
representing samples are
sourced to the device
input DAC

An analog waveform is
sourced to the device
Waveform samples are
represented by voltage
levels ADC
Analog Input Digital Output

Module 24 - 2

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 Wave Designer: Introduction

• Wave Designer is a tool for creating mixed signal

wave definitions to be used in tests.

• The Details of each wave definition are stored on

the Wave Definitions Sheet in the IG-XL
Workbook.

• Wave Designer allows the user to build general

wave shape definitions that can be applied in
multiple test situations.

Module 24 - 3

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Wave Definition Worksheet
Wave Definition details are stored on the Wave
Definitions sheet

Wave definitions can be created here or in the

Wave Designer tool in TDE

Module 24 - 4

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 Wave Designer: Primitives

• Wave Definitions are built up from a set of

predefined primitives:
DC Constant voltage level Ramp Create a ramp shape waveform
Excel Get samples from an Excel Range Sine Create a simple sine wave
Range in the workbook
Multitone Create multitone waveform Staircase Create a step staircase set of
Lab samples samples
Pulse Create a step pulse waveform VBT Call a user written VBT routine to
generate samples

• Each primitive has a set of options such as

phase, offset etc.
• Wave definitions can also incorporate other
wave definitions

Module 24 - 5

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 Wave Designer: Tool Intro

Wave Designer
window for
creating wave
definitions

Wave scope
window for
viewing wave
definitions

Module 24 - 6

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 Wave Designer: Adding a Worksheet

There does not need to

be a Wave Definitions
worksheet in the
workbook before
launching Wave
Designer, if one does not
exist, IGXL will
automatically add one

Select Worksheet from

the Insert menu and
choose Wave Definitions
from the dialog to
manually add a
worksheet

Module 24 - 7

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 Wave Designer: Opening Wave Designer

The Wave
Designer tool
runs as part of
TDE

Launch TDE and

select
WaveDesigner
from the Tools
submenu of the
TDE menu

All current valid

Wave Definitions
will be loaded
into
WaveDesigner

Module 24 - 8

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 Wave Designer: Create a New Wave
Definition

If there are no
pre-existing Wave
Definitions, Wave
Designer will
create a new
definition called
aSine which
contains a simple
sinewave

Click on the New

Wave Definition
button on the
Wave Designer
tool bar to create
additional Wave
Definition

Module 24 - 9

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Wave Designer: Create a New Wave
Definition

The New Wave

Definition button
brings up a dialog
box

The name for the

new wave
definition should
be specified

The user may also

choose an initial
primitive for the
wave definition or
leave it empty
using the primitive
dropdown list

Module 24 - 10

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 Wave Designer: Adding Waveform
Primitives

New primitives are

added by right
clicking on a row
in the definitions
table and selecting
a primitive from
the primitive
submenu of the
insert menu

These options can

also be selected
from the edit
menu in TDE

Module 24 - 11

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 Wave Designer: Primitive Options

Three primitives have

been added to
myDef1

Each primitive has

general options which
appear on the row of
that primitive

A primitive may have

options specific to the
primitive type which
appear in the box to
the right of the wave
definition area

A simulation of the
wave definition is
shown in the preview
area at the bottom by
selecting sampling
information and
clicking show wave

Module 24 - 12

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 Wave Designer: Compound Definitions

Further wave
definitions can
contain previously
defined wave
definitions

Here the definition

myWave2
contains
myWave1

Module 24 - 13

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 Excel Range Primitive
The Excel Range primitive allows samples to be generated from a range on a worksheet

1) Create
sample
values on
an excel
worksheet 2) Select
the range
of samples
to use on
the sheet

3) Define
Note: a name for
Excel Range the
requires the samples 4) Type a
number of with insert name for
samples the range
requested to and click
match the OK
size of the
range

Module 24 - 14

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Excel Range Primitive

Enter the name

of the excel
range defined
previously

To use excel
range, the
number of
samples asked
for must match
the size of the
range (128 in
this case)

The samples
produced by
the excel range

Module 24 - 15

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 VBT Primitive
The most flexible way to produce custom wave shapes is to use the VBT primitive
and write a visual basic subroutine to generate waveform samples
The code can be stored in a VB module as part of the workbook
All waveform generating subroutines can have any name but must match the
argument list given below to work with WaveDesigner

Required
calling
format

Samples
are
created in
an array
and then
loaded
into a
DSPWave

Module 24 - 16

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VBT Primitive

Enter the name

of the VBT
subroutine for
generating
samples (case
sensitive)

The samples
produced by
the VBT
subroutine

Module 24 - 17

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 Multitone Lab Primitive
The Multitone Lab primitive
allows creation of multitone
waveforms with full control
over the tones which
compose the waveform
Each tone can be
represented on a separate
row, and related tones can
be created on one row
The tool can find a set of
phases for the composite
tones to minimize the
multitone crest factor
Clicking the “MultitoneLab
Editor…” button on the
element editor will open this
form

Module 24 - 18

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Run the Wave Designer Lab

Module 24 - 19

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 Module 24 - 20

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DSP Introduction

Time to Frequency

Rev0343
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 Mixed-Signal Device

Consider testing an ADC/DAC IC. A Digital Engineer can easily understand and
analyze the digital input/output. But how do we analyze the analog
input/output? How can we quantify a good sinusoid or a bad sinusoid?
To succesfully test mixed signal devices a Digital Engineer needs to learn a new
set of analog tools and techniques. DSP is fundamental to mixed signal test.

ADC/DAC
Digital Input
Analog Output
DAC

ADC
Analog Input Digital Output

Module 25 - 2

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 Mixed Signal Tester Synchronization

D Clocks and Synchronization

i
g
V i
t
e a
c l Capture
t V Source Memory Memory
e
o c
r t
M o
r
e
m S DAC ADC
o e
q
r u
y e
n
c
e
r Serial/Parallel Source Serial/Parallel Capture Memory

Module 25 - 3

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Sampling Theory

Module 25 - 4

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 Sampling Theory Fundamentals

• Real world signals are analog defined by time,

phase and amplitude.

• Computers require changing analog signals to

digital.

• Sampling converts analog signals from continuous

time to digital signals with discrete time.

• Discrete sampling represents a unique set of

samples which describes a waveform.

Module 25 - 5

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 Sampling Theory Fundamentals

• A sample is the value of a signal measured

at specific point in time.

• A waveform is a series of samples

produced at a specified and constant rate.

Note: A signal can be exactly reproduced if sampled at

frequency F, where F is greater than or equal to
twice the maximum frequency in the signal.
To preserve all information in a signal, sample at
least twice the maximum frequency of the signal.
This is the Nyquist rate. (more on this later)

Module 25 - 6

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Sampling Process

Module 25 - 7

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 Constructing a Sine Wave
• What is needed to create this wave?

Module 25 - 8

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 Creating a Wave

• To source a signal on a Tester

– Convert Digital to Analog

OUT +
Source Zero-Order
Memory Hold DAC PGA
LPF(s)
OUT -

Programmable Clock Range Output Driver

Control

Module 25 - 9

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 Constructing a Sine Wave
• What is needed to create a wave?
– Clock (data rate – fs)
– Amplitude (value)
– Frequency (ft)
– Number of Samples (N)

Sample [n(6)]

Step
Amplitude

Sample
Rate
fs

Module 25 - 10

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 Constructing a Wave

Create a Wave (primitive)

• Example:
– Number of samples (N) = 12
– Fs (Sample Rate) = 859 ms
– Amplitude = 1v peak
– Frequency ? (about 100 Hz)

Module 25 - 11

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Smoothing Steps

Low Pass Filter

Module 25 - 12

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 Replicating Single Wave in Tester

Start with Primitive Continue Sequence

Module 25 - 13

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 Time Domain
Second Harmonic Distortion

1 KHz 1 KHz + 1% SHD

Little or no distortion can be noticed

Module 25 - 14

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 Frequency Domain
Second Harmonic Distortion

1 KHz 1 KHz + 1% SHD

The distortion can be easily noticed

Module 25 - 15

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 Fast Fourier Transform
a numerical algorithm

The Fast Fourier Transform (FFT) is similar to a spectrum analyzer

or a bank of filters with peak detecting meters attached.

Calculates the time domain to frequency domain transformation

of a sample data set. It has advantages over a simple spectrum
analyzer in that it also will return the phase angle relative to the
start of sampling.

Module 25 - 16

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 Correlation and DFT

• The next set of slides will build the concept

of the DFT using “correlation”.
• Correlation can be used to extract
information from a signal.

Module 25 - 17

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 How Does ATE DFT Work? (1/3)
“Correlation” is a measure of how closely related two waveforms are. To
“Correlation”: calculate “correlation” of two sets of N samples, multiply the samples
together point by point, sum the products, and then scale the sum by 2/N.

The Sin(t) Sin(t)

“correlation”
of sin(t) and
sin(t) is one Sin(t) ● Sin(t)

0 + ½ + 1 + ½ + 0 + ½ + 1 + ½ = 4 ► 4*2/8 = 1

The Sin(t) Cos(t)

“correlation”
of sin(t) and
cos(t) is zero Sin(t) ● Cos(t)
0 + ½ + 0 - ½ + 0 + ½ + 0 - ½ = 0 ► 0*2/8 = 0

The Sin(t) Sin(2t)

“correlation”
of sin(2t) and
sin(t) is zero Sin(2t) ● Sin(t)
0 + .71 + 0 - .71 + 0 - .71 + 0 + .71 = 0 ► 0*2/8 = 0

Module 25 - 18

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 Independent Sample Sets

sinx sin2x sinx sinx cosx cos2x cos2x cos3x

sin2x sin3x cosx sinx cos2x cos3x cos2x cos3x
0 0 0 0 1 1 1 1
0.1294095 0.3535534 0.25 0.0669873 0.8365163 0.6123724 0.75 0.5
0.4330127 0.8660254 0.4330127 0.25 0.4330127 3.063E-17 0.25 3.752E-33
0.7071068 0.7071068 0.5 0.5 4.332E-17 -4.33E-17 3.752E-33 0.5
0.75 1.061E-16 0.4330127 0.75 -0.25 0.5 0.25 1
0.4829629 -0.353553 0.25 0.9330127 -0.224144 0.6123724 0.75 0.5
1.225E-16 -1.23E-16 6.126E-17 1 -6.13E-17 1.838E-16 1 3.377E-32
-0.482963 0.3535534 -0.25 0.9330127 0.2241439 -0.612372 0.75 0.5
-0.75 2.122E-16 -0.433013 0.75 0.25 -0.5 0.25 1
-0.707107 -0.707107 -0.5 0.5 1.299E-16 -1.3E-16 3.377E-32 0.5
-0.433013 -0.866025 -0.433013 0.25 -0.433013 1.531E-16 0.25 9.381E-32
-0.12941 -0.353553 -0.25 0.0669873 -0.836516 -0.612372 0.75 0.5
-3E-32 -9.01E-32 -1.23E-16 1.501E-32 -1 -1 1 1
-0.12941 -0.353553 0.25 0.0669873 -0.836516 -0.612372 0.75 0.5
-0.433013 -0.866025 0.4330127 0.25 -0.433013 6.738E-16 0.25 1.816E-30
-0.707107 -0.707107 0.5 0.5 -2.17E-16 2.166E-16 9.381E-32 0.5
-0.75 -4.24E-16 0.4330127 0.75 0.25 -0.5 0.25 1
-0.482963 0.3535534 0.25 0.9330127 0.2241439 -0.612372 0.75 0.5
-3.68E-16 3.675E-16 1.838E-16 1 1.838E-16 -5.51E-16 1 3.04E-31
0.4829629 -0.353553 -0.25 0.9330127 -0.224144 0.6123724 0.75 0.5
0.75 -5.31E-16 -0.433013 0.75 -0.25 0.5 0.25 1
0.7071068 0.7071068 -0.5 0.5 -3.03E-16 3.032E-16 1.839E-31 0.5
0.4330127 0.8660254 -0.433013 0.25 0.4330127 -1.23E-15 0.25 6.003E-30
0.1294095 0.3535534 -0.25 0.0669873 0.8365163 0.6123724 0.75 0.5
0.0 0.0 0.0 12.0 0.0 0.0 12.0 12.0

Module 25 - 19

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 Component Phase

• In addition to magnitude and frequency

information, the components that make up
the signal also have an associated phase.
• The phase-shifted component can be
described as a combination of a sine and
cosine component of zero phase.
• Correlation can extract magnitude
information from a signal

Module 25 - 20

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 Sinusoid and Cosinusoid

• Initially, for any Arbitrary Waveform Generator (AWG) the signal has to be
created mathematically. To do this we have to call on some simple trigonometry.
y = sin x

y = cos x

• Every sinusoid can be represented by a phase shifted cosinusoid and vice versa.
y = cos (x – 90º)

Module 25 - 21

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 Phase-shifted Sinusoid

sin(a + b) = sin a × cos b + cos a × sin b

Phase-shifted sinusoid with peak value A = 1

sin( x + 60º ) = sin x × cos 60º + cos x × sin 60º

sin( x + 60º ) = sin x × 0.5 + cos x × 0.866
What this means is that any phase-shifted sinusoid can be
thought of as made up of a sine and a cosine component.

A= (0.5)2 + (0.866)2 = 0.25 + 0.75 = 1 = 1

Module 25 - 22

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 Phase-shifted Cosinusoid

cos(a + b) = cos a × cos b − sin a × sin b

Phase-shifted cosinusoid with peak value A = 2

2 cos( x + 70º ) = 2 (cos x × cos 70º − sin x × sin 70º )
2 cos( x + 70º ) = 2 cos x × 0.3420 − 2 sin x × 0.9397
2 cos( x + 70º ) = cos x × 0.4837 − sin x × 1.3289

A= (0.4837)2 + (1.3289)2 = 0.2341 + 1.7659 = 2

Later, when you do a Fourier Transform in analyzing a signal, it will return this two numbers, 0.4837, and
1.3289, which are: the amplitude times the cosine of the phase, and the amplitude times the sine of the phase.

Module 25 - 23

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 How Does ATE DFT Work? (2/3)
A waveform can be decomposed into cosine and sine terms using “correlation”. Start with a Cosine wave
with a phase shift Θ= 53°, and “correlate” this wave with both a sine and a cosine wave to get two vectors.

Cos(t)
Input Waveform “Correlation”
= 0.601815
Cos(t- 53°) Cos(t- 53°) ● Cos(t)

Sin(t)
“Correlation”
= 0.798636
Cos(t- 53°) ● Sin(t)

The angle between these two vectors is 53°, and the magnitude of their sum is 1. The original waveform
can be reconstructed by scaling a cosine wave by the first vectors magnitude, scaling a sine wave by the
second vectors magnitude, and then summing the two waves

Re*Cos(t)+ Im*Sin(t) Cos(t- 53°)

Im = mag = 1.0
0.79…
Θ= 53° =
Re = 0.60…

Module 25 - 24

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 How Does ATE DFT Work? (3/3)
A DFT uses “correlation” to transform a time domain waveform to a frequency domain representation.

Input samples (8):

(1.71, 0.29, 0.71, 0.71,
-1.71, -0.29, -0.71, -0.71) Average cos(0) ► 0
Bin 0, DC
Sin(t+45°) + Cos(3t)
Empty sin(0) ► 0

Cosine(1*t) ► √2/2 = 0.707

Bin 1, 1*Fres
Sine(1*t) ► √2/2 = 0.707
Output spectrum (8):
(0, 0, 0.71, 0.71,
0, 0, 1, 0) Cosine(2*t) ► 0
Bin 2, 2*Fres
Sine(2*t) ► 0

Cosine(3*t) ► 1
Bin 3, 3*Fres
Sine(3*t) ► 0

The DFT takes the 8 input samples and converts them to an 8 point frequency representation. The
waveform can be completely recovered from the output spectrum.

Module 25 - 25

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 Analog Signal
Time and Frequency Domains

Sinusoid

1
T
T

2 µs 0.5 MHz

Module 25 - 26

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 Waveform Signal
Time and Frequency Domains

Rectangular Wave

T
T/5

1 1 1 1 1 1 1 1 1 1
TT T T T T T T T T T T

T
0.2

µs 1 2 3 4 5 6 7 8 9 10 MHz
1

Module 25 - 27

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 Time vs. Frequency

64 waveform
samples points
containing
1 cycle –
Frequency of
Repetition (1FR)

Signal power is
found in bin 1 of
the 32
spectrum bins

Module 25 - 28

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 Time vs. Frequency

64 waveform
samples points
containing
3 cycles –
Frequency of
Repetition (3FR)

Signal power is
found in bin 3 of
the 32
spectrum bins

Module 25 - 29

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 Time vs. Frequency

64 waveform
samples points
containing the
sum of a 1
cycle waveform
and a 3 cycle
waveform

Signal power is
found in bin 1
and bin 3 of the
32 spectrum
bins

Module 25 - 30

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Important Relationships for Coherency

FR / Fs = M / N N = 64

F0 = Fs / N M=3

M = FR × N / Fs FS / FR = N / M
= FR / F0 FS / FR = 64 / 3 64 unique samples in 3 cycles

Module 25 - 31

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 Sampling Theory
The Primitive Frequency

• The primitive frequency, F0 is that frequency which produces exactly

one cycle within the UTP. Seeing that all frequencies in a signal MUST
complete a whole number of cycles within the UTP, this means they
must all be multiples of F0.

1 x F0

2 x F0
frequency

3 x F0

4 x F0

time Module 25 - 32

- confidential -
 ATE Fast Fourier Transform
Amplitude Spectrum

• For N (power of 2) time domain samples, Magnitude

Amplitude Spectrum
there will be N frequency domain values Real Component
A Cos θ
• The N values are grouped in pairs called Imaginary Component

bins (0,1 -> bin 0; 2,3 -> bin 1; 4,5 -> A Sin θ

bin 2; ...) that represent one frequency

component (magnitude and phase)
• The two values are a real and imaginary Array Index 0 1 2 3 4 5 k k+1 N-2 N-1

component that represent a sinusoidal Bin Number 0 1 2 M N/2-1

component with a given phase and Frequency DC F0 2*F0 FR Fs/2-F0s

amplitude
Vector Representation
of a Sinsusoid
FR / Fs = M / N

F0 = Fs / N
Imaginary A
= A Sin θ
M = FR × N / Fs
θ

Real =
= FR / F0
A Cos θ

Module 25 - 33

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 ATE Fast Fourier Transform
Power Spectrum

• For N time-domain signal samples

Magnitude Power Spectrum
• There are N frequency-domain signal
values A2
Frequency Component

• There are N/2 frequency-domain – Power

Spectrum values
• For amplitude A in a time-domain signal
component
Array Index 0 1 2 k N/2-1

Bin Number 0 1 2 Fbin N/2-1

Frequency DC F0 2*F0 FR Fs/2-F0

Module 25 - 34

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 Frequency Domain Multitone
Time Domain 1/Fs
wave1 M=3
The bold wave is the sum wave2 M=5
of the two dark waves

amp
with M = 3 for one and M
sum wave1
= 5 for the other.
+ wave2
Fs is frequency of
samples, 1/Fs is time
between samples. Nth (16th)
UTP (unit test period) is sample
time for one set of unique
samples to repeat,
UTP = N * (1/FS) UTP = 1/F0

Frequency Domain Bin 3, Bin 5,

3*F0 5*F0 FR = M * F0
Bin 0, DC

0 1 2 3 4 5 6 7

Bin 1,
term at F0

Frequency Bins
Module 25 - 35

- confidential -
 Frequency Domain Multitone
Time Domain 1/Fs
wave1 M=2
The bold wave is the sum wave2 M=4
of the two dark waves

amp
with M = 2 for one and M
sum wave1
= 4 for the other.
+ wave2
What is wrong with the
choice of M = 2 and M =
4 for the components of Nth (16th)
the composite wave? sample

UTP = 1/F0

Frequency Domain Bin 2, Bin 4,

2*F0 4*F0 FR = M * F0
Bin 0, DC

0 1 2 3 4 5 6 7

Bin 1,
term at F0

Frequency Bins
Module 25 - 36

- confidential -
 A Few Useful Definitions

Frequency Bin The frequency spectrum contains signal amplitudes at discrete

frequencies normally called frequency bins.

DC Component The first frequency bin resulting from the FFT is the DC component of
the signal or the average value of the sample points.

Fundamental This is the frequency of interest. The input signal to the A/D.

Spectrum The entire array of frequencies represented by the FFT.

Harmonic Odd and even multiples of the fundamental signal.

Noise The frequency components represented in a given bandwidth other than

the DC component, the fundamental, and harmonics.
2 2 2
a1 + a2 + ... + an
RMS Root Mean Square.
( N − 1) 2
Module 25 - 37

- confidential -
 Coherence

Critical Concept behind ATE DSP Test:

• ATE DSP sources and captures periodic deterministic waveforms which

complete a whole number of cycles over a whole number of samples
during the test interval.

• ALL numerical relationships and calculations follow simple ATE DSP

rules.

• ALWAYS return to first principal of DSP test: COHERENCE

Module 25 - 38

- confidential -
 Sampled Signals Example

• The plain old telephone system (POTS) uses an encoder. The standard test
signal used to be 1020Hz. The sample rate is fixed by international agreement
at 8KHz

Q How do we create this signal to be used for test?

In all that follows, we will use Fs to represent the sampling frequency and Ft to
represent the frequency of interest

We start with Ft 1020

=
FS 8000
and reduce this fraction to lowest terms Ft 1020 51
= =
FS 8000 400
• The numerator 51, in this case, is always designated by the letter M. This is the
number of cycles of the signal that will be sampled. The denominator
represented by the letter N is the number of times the signal will be sampled

Q So why do we do this? We need an independent repetitive sample set

Module 25 - 39

- confidential -
 Repetitive Sample Sets

1
• Note that if Fs is the sampling rate then T = is the sampling period or the time
between samples. FS
• We have to use a discrete formula instead of a continuous one. This means the formula
generates a finite set of points (not all values of time can be used as in a continuous
case):
Vt = sin(2πft ) allows any value of t
Vnt = sin( 2πFt nT ) n = 0, 1, …, N-1
1
Notice that since T = , the formula contains Ft = M
FS FS N
M 51
So, in our math we will use Vnt = sin( 2πn ) For our example: Vnt = sin( 2πn )
N 400
51 cycles
3x45.9º
1x45.9º 399x45.9º

0x45.9º 398x45.9º
2x45.9º
400 samples Module 25 - 40

- confidential -
Frequency Analysis

Module 25 - 41

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 Single Tone Signal Analysis

• SNR (Signal to Noise Ratio): The power ratio of carrier signal against
the sum of all non-harmonic noise power within a captured waveform.
• THD (Total Harmonic Distortion): The power sum of all harmonics to
the power of the carrier.
• SINAD (Signal to Noise And Distortion): The power ratio of carrier
signal against the sum of all remaining power including noise and
harmonics within a captured waveform.
• SFDR (Spurious Free Dynamic Range): The power ratio of carrier signal
against the power of the second highest frequency component (not
including DC).

– Because of magnitude considerations, all ratios above are usually

expressed in dB.

Module 25 - 42

- confidential -
 Decibel (dB)

• Decibel is a unit usually applied when comparing levels of

voltages or powers that are orders of magnitude apart:

– When comparing powers:

2 2
W1  V1   V1  V12  V12 
=   → 10 log  = 10 log 2 =
W2  V2  V 2 
 V2  V2  2  dB

– When comparing voltages:

2 2
W1  V1  V  V V V 
=   → 10 log 1  = 2 × 10 log 1 = 20 log 1 =  1 
W2  V2   V2  V2 V2  V2  dB

Module 25 - 43

- confidential -
 Decibel (dB)
Power Ratio Examples

a = 0.00000001 b = 1.000000 10 * log10 (a/b) = 10 X (-8) = - 80 dB

a = 0.0000001 b = 1.000000 10 * log10 (a/b) = 10 X (-7) = - 70 dB
a = 0.000001 b = 1.000000 10 * log10 (a/b) = 10 X (-6) = - 60 dB
a = 0.00001 b = 1.000000 10 * log10 (a/b) = 10 x (-5) = - 50 dB
a = 0.0001 b = 1.000000 10 * log10 (a/b) = 10 x (-4) = -40 dB
a = 0.001 b = 1.000000 10 * log10 (a/b) = 10 x (-3) = -30 dB
a = 0.01 b = 1.000000 10 * log10 (a/b) = 10 x (-2) = -20 dB
a = 0.1 b = 1.000000 10 * log10 (a/b) = 10 x (-1) = -10 dB
a = 1.00000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.000000 = 0.0 dB
a = 2.00000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.301030 = 3.010300 dB
a = 3.00000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.477121 = 4.771213 dB
a = 4.00000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.602060 = 6.020600 dB
a = 5.00000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.698970 = 6.989700 dB
a = 6.00000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.778151 = 7.781513 dB
a = 7.00000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.845098 = 8.450980 dB
a = 8.00000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.903090 = 9.030900 dB
a = 9.00000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.954243 = 9.542425 dB
a = 10.0000000 b = 1.000000 10 * log10 (a/b) = 10 x1 = 10 dB
a = 100.000000 b = 1.000000 10 * log10 (a/b) = 10 x2 = 20 dB
a = 1000.00000 b = 1.000000 10 * log10 (a/b) = 10 x3 = 30 dB
a = 10000.0000 b = 1.000000 10 * log10 (a/b) = 10 x4 = 40 dB
a = 100000.000 b = 1.000000 10 * log10 (a/b) = 10 x5 = 50 dB
a = 1000000.00 b = 1.000000 10 * log10 (a/b) = 10 x6 = 60 dB
a = 10000000.0 b = 1.000000 10 * log10 (a/b) = 10 x7 = 70 dB

a = 10000000.0 b = 1.000000 10 * log10 (a/b) = 10 x 7 = 70 dB

In linear scale, a and b could not be clearly shown in the same plot
Module 25 - 44

- confidential -
 Common Frequency Analysis Algorithms

• Signal To Noise Ratio (SNR)

• Total Harmonic Distortion (THD)

• Signal to Noise and Distortion (SINAD)

• Spurious Free Dynamic Range (SFDR)

Module 25 - 45

- confidential -
 What are the Spectral Components?

• Captured sine wave with N samples

v2 Fundamental
• Power spectrum has N/2 samples

DC Component Second
Harmonic

Noise
Third Components
Harmonic

ƒ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Power Spectrum
Module 25 - 46

- confidential -
 Signal to Noise Ratio (SNR)

v2
Store the value of the fundamental
This is the signal power

ƒ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Power Spectrum
Module 25 - 47

- confidential -
 Signal to Noise Ratio (SNR)

v2
Stride through the array and zero out fundamental,
harmonics (usually up to 5), and the DC component

ƒ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Power Spectrum
Module 25 - 48

- confidential -
 Signal to Noise Ratio (SNR)

v2
Sum all bins of the remaining power spectrum
This gives the noise power

ƒ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Power Spectrum
Module 25 - 49

- confidential -
 Signal to Noise Ratio (SNR)

• Expressed in decibels (dB)

• The signal to noise ratio is a positive value
(assuming the fundamental power is greater than
the noise power)

Fundamental
SNRdB = 10 log10
Noise Power

Module 25 - 50

- confidential -
 Total Harmonic Distortion (THD)

v2
Store the value of the fundamental tone.
This is the signal power

ƒ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Power Spectrum
Module 25 - 51

- confidential -
 Total Harmonic Distortion (THD)

Stride through the array and keep a running sum of

v2 the total harmonic power (usually only the first five
harmonics).
Start at the second harmonic.
sum sum

sum

ƒ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Power Spectrum
Module 25 - 52

- confidential -
 Total Harmonic Distortion (THD)

• Expressed in decibels (dB)

• The THD is a negative value (assuming the
fundamental power is greater than the noise power)

Harmonic Power
THDdB = 10 log10
Fundamental

Module 25 - 53

- confidential -
 Signal to Noise and Distortion (SINAD)

• This is the same methodology as computing SNR.

However, now power of the harmonics is added to the
noise power.
• Only zero out the DC component.
S D S
SNR = THD = SINAD =
N S N+D
−1 N D N+D
SNR + THD = + = = SINAD −1
S S S
−1 −1
SINAD = ( SNR + THD)
Module 25 - 54

- confidential -
 Spurious Free Dynamic Range (SFDR)

v2
Store the value of the
fundamental
This is the signal power

ƒ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Power Spectrum
Module 25 - 55

- confidential -
 Spurious Free Dynamic Range (SFDR)

v2 Stride through ALL array elements. Find the highest

element (ignoring the fundamental and DC component).
Note that the highest element may or may not be a
harmonic! Store the value of this component.

For this example, the highest

element other than the
fundamental is the second
harmonic.

ƒ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Power Spectrum
Module 25 - 56

- confidential -
 Spurious Free Dynamic Range (SFDR)

•Expressed in decibels (dB)

•The spurious free dynamic range is a positive
value (assuming the fundamental is greater
than the next highest spur power)

Fundamental
SFDRdB = 10 log10
Next Highest

Module 25 - 57

- confidential -
 Dual-Tone Signal Analysis

• Dual-tone technique is usually used for narrow-

band device where harmonics are outside device
pass band and can not be measured
• Two signals of frequency f1 and f2, one close to
the other within the pass band are used
• Instead of measuring harmonics, 3rd order inter-
modulation products: 2f1-f2 and 2f2-f1 are been
measured.
• For wide-band device, 2f1+f2 and 2f2+f1 can
also be measured. Notice those two frequencies
are usually outside the band-width of a narrow
band device.

Module 25 - 58

- confidential -
Dual-Tone Signal Spectrum

f1 f2

2f1-f2

2f2-f1
2f1+f2 2f2+f1

Module 25 - 59

- confidential -
 Aliasing Example

v2
FS/2 FS
Where will the aliased images of the
frequency components located at bins 4,
6, 8 and 10 fall due to undersampling?

ƒ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Power Spectrum
Module 25 - 60

- confidential -
 Digital-to-Analog Conversion
1 data set (words)
00110001
x[n] 2
00110010

00110011
lookup table at Fs
...

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
00111111
xˆ[t ] 3

zero-order hold*

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
* A first-order holder can be
used. Instead of maintaining the
sample’s value for 1/Fs, the first-
x[t ] 4
order holder approximates x(t)
by straight-line segments which
have a slope that is determined
analog LPF
by the current sample x[i] and
the previous sample x[i-1]. ++
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
++ based on Digital Signal Processing, by Proakis and Module
Manolakis
25 - 61

- confidential -
 3-bit DAC
Binary Words
User array
What happens when we try to represent a sine
0.000000 0.00 011 wave using a 3 bit DAC? Start with an array of
0.258819 0.25 100 24 points of a sine wave. A 3 bit DAC can only
0.500000 0.50 101 represent 23 = 8 levels, so the original sine data
0.707107 0.75 110 is rounded to the nearest level. Each sample
0.866025 0.75 110 must be represented by a 3 bit binary word.
0.965926 1.00 111
1.000000 1.00 111
0.965926 1.00 111
0.866025 0.75 110
0.707107 0.75 110
0.500000 0.50 101
1/Fs

0.258819 0.25 100

0.000000 0.00 011
-0.258819 -0.25 010
-0.500000 -0.50 001
-0.707107 -0.75 000
-0.866025 -0.75 000
-0.965926 -0.75 000
-1.000000 -0.75 000
-0.965926 -0.75 000
-0.866025 -0.75 000
-0.707107 -0.75 000
-0.500000 -0.50 001
-0.258819 -0.25 010

Quantized array Module 25 - 62

- confidential -
 Analog to Digital Conversion
sampling
x(t ) δ [n]
1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

x(t ) × δ [n] 2 quantization

x[n] 3

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

data set: 00110001, 4

captured data
00110010,
00110011,
... ,
Module 25 - 63
00110001
- confidential -
Mixed Signal Workshop

Rev0343
- confidential -
 Mixed Signal Workshop: Introduction
Consider the problem of setting up sampling and timing for a mixed
signal test
For proper dsp analysis the input and output must be coherent (the
sample rates and sizes must be related so that a whole number of
cycles is captured)
The user will need to specify (1) the waveforms to be sourced and (2)
the coherent sampling setup which should be created with some sort
of sampling calculator

Digital words Digital Input The analog output must

Analog Output
representing samples are be captured and sampled
sourced to the device ADC/DAC at a sampling rate and
input according to the size that is related to the
clocking rate of the device clocking rate so
device DAC that a coherent set of
samples is captured

An analog waveform is
sourced to the device, The digital words from
the source sampling the device must be
setup must be related to captured at a sample rate
the sampling clocking and size that is related to
rate of the ADC for
coherent sampling
ADC the input waveform and
the clocking rate of the
Analog Input Digital Output
device

Module 26 - 2

- confidential -
 Mixed Signal Workshop: Introduction

• Mixed Signal Workshop (MSW) is a tool for

creating coherent clocking solutions to be used in
tests.

• The Details of each clocking solution are stored as

a timing context on the Mixed Signal Timing Sheet
in the IG-XL Workbook.

• Waveforms for each instrument are also specified

in MSW as part of each timing context.

Module 26 - 3

- confidential -
 Mixed Signal Workshop:
Anatomy of a Mixed Signal Timing Context

Wave Shape canned wave

definition or a
Source Information Wavelab wave

Instrument Sampling source sample size,

source frequency,
Information cycle count, etc.
Mixed Signal
Timing
Context

Capture Sampling capture size,

capture frequency,
A snapshot of a Instrument Information cycle count, etc.
hardware state that
can be applied during
a test

Module 26 - 4

- confidential -
 Mixed Signal Workshop:
Mixed Signal Timing Sheet

The Mixed Signal Timing sheet is where completed timing contexts

are stored. These contexts are created and edited in the Mixed
Signal Workshop.

These contexts are applied to hardware in test procedures and

indicate the state of the instrument for the given test.

Think of the timing context as a hardware setup snapshot that can

be applied during a test (the values in the timing context can be
overwritten in the test setup if needed).

Module 26 - 5

- confidential -
 Mixed Signal Workshop: Mixed Signal
Timing Sheet Column Descriptions

Set Name Name of clocking context Fs Sample Frequency, frequency of sample

sourcing or capturing

Subset To distinguish multiple clock setups for a test N Number of samples in waveform

Type Type of instrument row describes (BBACSrc, Fr Frequency of interest/repeat in source/capture

DSSCCap etc.) waveform
ID Used to distinguish multiple duplicate types M Number of waveform cycles
in a context (BBACSRC 1, BBACSRC 2, etc.)
Data Instrument specific data USR Under Sample Ratio (capture only)
Definition For legacy software compatibility Filter For legacy software compatibility

Module 26 - 6

- confidential -
 Mixed Signal Workshop

The Mixed Signal

Workshop Tool is where
timing contexts are
edited.
Each instrument in the
context is represented,
as well as their frequency
relation through the DUT.
The instruments and
options change
depending on user input.

Module 26 - 7

- confidential -
 Mixed Signal Workshop

• Mixed Signal Workshop generates solutions with

three sets of constraints:

DUT Constraints: DSP Constraints:

Waveform Coherency, N, M,
frequency, etc. etc.

Instrument Constraints:

Sample rate,
Bandwidth, etc.

• All solutions will conform to these constraints

Module 26 - 8

- confidential -
 Mixed Signal Workshop
• For example:
– The DUT may require a signal Repeat Frequency ‘Fr’
of 1000Hz, with a Sample Frequency ‘Fs’ of 8000Hz
– DSP may require a Sample Size ‘N’ that is a power of
2, and a Cycle Count ‘M’ that is mutually prime with N
– For N = 512, with Fs/Fr=N/M, M is 64
– Since N and M should be mutually prime, we instead
choose M = 65, and Fr becomes 1015.625

• Mixed Signal Workshop takes these type of

restrictions into consideration when generating
solutions

Module 26 - 9

- confidential -
 Mixed Signal Workshop
The File menu Subsets are used for including The DUT block is used to define Blocks on the right
allows creation, multiple setups in one context. the relationship between the DUT represent capture
opening, closing Create a new subset with the input and output frequencies. instruments.
and saving of file menu, and change subsets The (…) button brings up an Capture settings
timing contexts with the Subset dropdown list. equation editor. and coherence
error are displayed.
The Edit menu is
Click on the Solve
used to create,
button to bring up
delete and edit
the Solver tool to
timing subsets
find valid solutions.
The MSW menu is
used to add and Any instrument
delete instruments specific settings will
and manage timing appear at the
subsets bottom of the
instrument block.
Click on the
Blocks on the left More/Less button
represent source to hide and unhide
instruments. the extra options.
Signal settings and
the wave definition
to be sourced are
displayed. Click on
the Solve button
to bring up the
Solver tool to find
valid solutions.
Module 26 - 10

- confidential -
 Mixed Signal Workshop: Source Detail
Signal sampling FR is the Test Tone
Solve… brings up the solver frequency of the source
information can be directly
window to generate coherent waveform
entered or generated with
solutions which conform to the
the Solver tool
selected instrument Fr = Fs*M/N
Fs is the sampling
frequency, the rate at Bandwith requirements
which samples are come from the wave
produced by the source definition and test tone
instrument frequency

N is the number of
waveform samples used to NOTE: Right clicking on a
represent the given selected instrument will
waveform bring up a menu to view
the waveform samples, to
M is the number of view the simulated
waveform cycles The previously defined waveform instrument output, or
represented by the given shape to be sourced is chosen delete the instrument
set of samples. from the dropdown menu

Fs/Fr = N/M Click on the Edit button to edit

the selected wave definition in
Wave Designer

Module 26 - 11

- confidential -
 Mixed Signal Workshop: Capture Detail

Solve… brings up the FS is the frequency

solver window to at which samples
generate coherent will be captured
solutions
FS/FRCAP = N/M
The DUT test tone N is the number of
output frequency to waveform samples
be coherently that will be captured
captured
M is the number of
FRCAP is the test waveform cycles
tone capture represented in the
frequency captured set of
samples
Coherence Error is
the discrepancy
between the capture
Fr and the DUT
output frequency

Module 26 - 12

- confidential -
 Mixed Signal Workshop: Solver

• At the heart of the MSW tool

is a solver that assists the
user in selecting a coherent
timing solution for analog and
digital, source and capture
instruments.

• The solver presents the user

with a list of generated
solutions to choose from.

• The solver is a tool for creating instrument-compatible,

coherent timing solutions over a wide range of device scenarios.
Proficiency can only be achieved through practice and
experimentation.

Module 26 - 13

- confidential -
 Mixed Signal Workshop: Solver

• Example Solver
solutions for a
DSSCSrc

• FS is selected as
the element to be
computed

• The solutions can

be sorted by any
column

Module 26 - 14

- confidential -
 Mixed Signal Workshop: Solver

• Example Solver
solutions for a
BBACCap capture
instrument

• FS is selected as
the element to be
computed

• Columns are
different: Fres and
UTP

Module 26 - 15

- confidential -
 Mixed Signal Workshop:
Test Time Reduction

• EXAMPLE: Testing
a Codec Receiver

• Fs = 8,000 s/s

• Ft = 1,000 Hz
(nominal)

Module 26 - 16

- confidential -
 Mixed Signal Workshop:
Test Time Reduction

• EXAMPLE:
Testing a
Codec Receiver

• Ft = 1,015.625

• UTP = 64 ms

Module 26 - 17

- confidential -
 Mixed Signal Workshop:
Test Time Reduction

• If 512 samples
works, maybe
~10% fewer
samples will also
work

• Ft = 1,004.255
• UTP = 58.75 ms

• UTP down by 5.25

ms (-8.2%)

• Fourier transform
up by < 100us
(actually unchanged since
it overlaps with testing)

Module 26 - 18

- confidential -
Run the Mixed Signal Workshop Lab

Module 26 - 19

- confidential -
 Module 26 - 20

- confidential -
Digital Signal Processing

Rev0343
- confidential -
 FLEX DSP

The objectives of this section are:

• An overview of DSP Hardware
• Understanding PDE and DSP Procedures
• DSP Language
• Debugging in VBT
• Characteristics of VBT for DSP
• DSP Functions
• Deferred Binning

Module 27 - 2

- confidential -
DSP
Ones and Zeros

1111100000011111000001111110
0100010000100000100000100001
0100010000100000000000100001
0100010000011111000000111110
0100010000000000100000100000
0100010000100000100000100000
1111100000011111000001110000
Module 27 - 3

- confidential -
DSP
DSP

1111100000011111000001111110
0100010000100000100000100001
0100010000100000000000100001
0100010000011111000000111110
0100010000000000100000100000
0100010000100000100000100000
1111100000011111000001110000
Module 27 - 4

- confidential -
System Overview

Hardware
Instrument Initiated Move (IIM)
Parallel Processing

Rev0343
- confidential -
DSP
FLEX DSP: Hardware
left hemisphere right hemisphere

SDRAM
SDRAM MBR 50MByte/sec MBM Slot1 Inst Slot13 Inst MBM 50MByte/sec MBR
SDRAM
SDRAM
1.536Gbit
1.536Gbit 1.536Gbit
1.536Gbit

MBR 50MByte/sec MBM Slot2 Inst Slot14 Inst MBM 50MByte/sec MBR

DSP
DSP MBR 50MByte/sec MBM Slot3 Inst Slot15 Inst MBM 50MByte/sec MBR DSP
DSP

MBR 50MByte/sec MBM Slot4 Inst Slot16 Inst MBM 50MByte/sec MBR

MBR 50MByte/sec MBM Slot5 Inst Slot17 Inst MBM 50MByte/sec MBR

Crosspoint
Matrix

Crosspoint Matrix
Crosspoint Matrix

DSP
DSP MBR 50MByte/sec MBM Slot6 Inst Slot18 Inst MBM 50MByte/sec MBR DSP
DSP

MBR 50MByte/sec MBM Slot7 Inst Slot19 Inst MBM 50MByte/sec MBR
Crosspoint

Slot8 Inst Slot20 Inst

Matrix
MBR 50MByte/sec MBM MBM 50MByte/sec MBR

DSP
DSP MBR 50MByte/sec MBM Slot9 Inst Slot21 Inst MBM 50MByte/sec MBR DSP
DSP

MBR 50MByte/sec MBM Slot10 Inst Slot22 Inst MBM 50MByte/sec MBR

MBR 50MByte/sec MBM Slot11 Inst Slot23 Inst MBM 50MByte/sec MBR

DSP
DSP DSP
DSP
Test Computer MBR 50MByte/sec MBM Slot12 Inst Slot24 Inst MBM 50MByte/sec MBR

TCIO
Left support board (master) Right support board
Module 27 - 6

- confidential -
DSP
FLEX DSP: Hardware
1‘return the relative gain between two input dSPWaves
Steps that occur before code is run
Public Function Gain(SrcInWv As DSPWave, CapInWv As DSPWave, _ on the embedded processors
AbsGain As Double) As Long

1) The user writes a DSP Function in

Dim SrcSigLvl As Double, CapSigLvl As Double

SrcSigLvl = SrcInWv.CalcRMS
CapSigLvl = CapInWv.CalcRMS
‘get source signal magnitude
‘get capture signal magnitude
Visual Basic
‘calculate the gain between the input and output signal 2) The Visual Basic is translated to DSP
Processor Byte-Code with a compiler
AbsGain = 20 * Log(CapSigLvl / SrcSigLvl) / Log(10)
End Function

3) The Byte-Code is loaded in the DSP

Processor and will be used to process
captured signals as programmed
2
VB To DSP
Byte-Code
Compiler

0010110001100011
1010100001101011
1010100001101011
3
1101100010101000
0111010101011101
1010100001101011
1010100001101011
0010110001100011
0111010101011101
0111010101011101
1101100010101000
0010110001100011
0010110001100011
DSP DSP
1010100001101011
0111010101011101
1101100010101000
0111010101011101
0010110001100011
1010100001101011
0010110001100011
1101100010101000
0111010101011101
1101100010101000
1101100010101000
1010100001101011
1010100001101011
1010100001101011
0111010101011101
0111010101011101
0111010101011101

Module 27 - 7

- confidential -
IIM FLEX DSP: Hardware Moves
Overview
Instrument Boards Support Boards
PSET
PSET

G4G4
Digitizer
Digitizer
G4
DSP
Cap Mem
PatGen
PatGen

Move and processing are autopipelined

No host computer intervention
Instrument Initiated Moves are automatic
DSP processes results automatically when move is complete
Instrument free to start another test as soon as capture is complete

Module 27 - 8

- confidential -
IIM FLEX DSP: IIM Example
step 0 - setup

PSET
PSET

G4G4
Digitizer
Digitizer
G4
DSP
Cap Mem
PatGen
PatGen

First the Pattern sets up the digitizer

Module 27 - 9

- confidential -
IIM FLEX DSP: IIM Example
step 1: capture samples

PSET
PSET

G4G4
Digitizer
Digitizer
G4
DSP
Cap Mem
PatGen
TRIG
PatGen

The Pattern triggers the digitizer

Module 27 - 10

- confidential -
IIM FLEX DSP IIM: Example
step 2 – cont. sampling

PSET
PSET

G4G4
Digitizer
Digitizer
G4
DSP
Cap Mem
PatGen
PatGen

The Digitizer fills up capture memory

Module 27 - 11

- confidential -
IIM FLEX DSP: IIM Example
step 3: datamove

PSET
PSET

G4G4
Digitizer
Digitizer
G4
DSP
Cap Mem
PatGen
PatGen

When the Capture is complete

The Instrument Initiated Move (IIM) enables the datamove

Module 27 - 12

- confidential -
IIM FLEX DSP: IIM Example
step 4: upon completion of datamove

PSET
PSET

G4G4
Digitizer
Digitizer
G4
DSP
Cap Mem
PatGen
PatGen 50MB/sec

The is Capture automatically moved to support board

The Digitizer free to be programmed for next test

Module 27 - 13

- confidential -
IIM FLEX DSP: IIM Example
step 5: additional trigger available

PSET
PSET

G4G4
Digitizer
Digitizer
G4
DSP
Cap Mem
PatGen
TRIG
PatGen 50MB/sec

The Digitizer can trigger during a datamove

Module 27 - 14

- confidential -
IIM FLEX DSP: IIM Example
step 6 – read/write

PSET
PSET

G4G4
Digitizer
Digitizer
G4
DSP
Cap Mem
PatGen
PatGen 50MB/sec

Data can also be written to capture memory while it is being read out

Module 27 - 15

- confidential -
IIM FLEX DSP: IIM Example
step 7 – processing data

PSET
PSET

G4G4
Digitizer
Digitizer
G4
DSP
Cap Mem
PatGen
PatGen 50MB/sec

Once the move is complete, the support board automatically starts processing the
data
This can occur while data from the next test is moving to the support board

Module 27 - 16

- confidential -
IIM FLEX DSP: IIM Example
note: auto pipelining

PSET
PSET

G4G4
Digitizer
Digitizer
G4
DSP
PatGen
TRIG
PatGen 50MB/sec

All Moves are pipelined

Module 27 - 17

- confidential -
IIM FLEX DSP: IIM Example
step 8: result storage

PSET
PSET

G4G4
Digitizer
Digitizer
G4
DSP
PatGen
PatGen 50MB/sec

The Results from DSP processor are stored.

Module 27 - 18

- confidential -
IIM FLEX DSP: IIM Example
step 9: result retrieval, continue testing

PSET
PSET

G4G4 Test Computer

Digitizer
Digitizer
G4
DSP DSP Answer
DSP Answer
PatGen
DSP Answer
PatGen 50MB/sec
DSP Answer

The Host picks up answer when complete

The DSP engine can process next available data
The Support board continues to load information from instrument
The Instrument is free for next test setup

Module 27 - 19

- confidential -
DSP Procedures
Test Element
DSP Functions
DspWave Object

Rev0343
- confidential -
 DSP Procedures
• This section will cover:
– Using the DspProcedure in PDE – the DSP Test element
– Understanding the DspProcedure test element editor
– DspProcedures in VBT
– Using DspProcedures in a test
– DSP Functions

Module 27 - 21

- confidential -
 DSP Test Element: in PDE
Example:Adding elements in the Flow Chart

Mixed signal tests are

usually created in the
procedure
development
environment
Test elements are
added to a test flow
to create a mixed
signal test algorithm
A DSP Test Element
should be added to
the flow after a
capture test element
The DspProcedure
receives the data
from the capture as a
DSPWave object
The DSP function will
then analyze the
DSPWave object

Module 27 - 22

- confidential -
DSP Test Element: in PDE
How to add a dsp test element
This is the default DSPProcedure
test element editor

Module 27 - 23

- confidential -
 DSP Test Element: in PDE
DspProcedure Element Editor
The DspProcedure test element
will add fields to the editor area
depending on the DSP Procedure
selected
The DSP Procedure Name drop-
down will list all valid DSP
Procedures
Depending on the input
parameters for the selected
function, new fields will appear in
the Element Editor

Module 27 - 24

- confidential -
 DSP Test Element: in PDE
Variables Table showing DspWave Variables

The Variables Table lists all

the variables used by the
test elements
Test elements communicate
by reading and writing data
to the variables
The data stored in the
variables for a procedure
can be accessed in VB code
using the theVars object
Captured signal information
from test elements is stored
in DSPWave objects in the
variables table

Module 27 - 25

- confidential -
 DSP Language
• A DspWave object is a Class Object
• A newly dimensioned DspWave variable can
be thought of as a pointer to a DspWave
object
• A newly dimensioned DspWave variable must
have its reference set before it can be used
– Dim MyWave as DspWave ‘create variable
– Set MyWave = New DspWave ‘allocate new object

• Short hand dimensioning notation:

– Dim MyWave as New DspWave ‘create and allocate

Module 27 - 26

- confidential -
 DSP Language: Overview
• DSPWave functions work in two ways
– 1: The function returns a value
– 2: The function changes the DSPWave objects data
• Type 1 function example
– The AddScalar function returns a new DSPWave and does not
change the base DSPWave
– To keep the result it must be set to a DSPWave variable
– Set ResultWave = MyWave.AddScalar(2.3)
• Type 2 function example
– The letdata function is done “in place” and returns no value
– MyWave.letdata Array1 ‘MyWave now holds Array1
– Clear, FileImport, LetData, LetDataInt, LetElement,
Selection, Replace, and FillWithConstant are in place
functions

Module 27 - 27

- confidential -
 DSP Language:
Create DSP Procedures in VBT under modules folder
The Visual Basic Editor is where DSP
All DSP Procedures are created in code is written and debugged
VBT under the modules folder The
procedure begins with the string The Editor has a host of tools and
DSP, such as DSP_Procedures. features to aid in debugging and
code development

Module 27 - 28

- confidential -
 DSP Language:
Adding a DSP Procedure
Open up a test program and enter the VBT environment by clicking Alt+F11
Once in VBT click on the test program name in the project window
From the insert menu select Module. A new module is added to the modules directory.
Click on the module in the project window and rename it to DSP_Procedures in the
Properties window.

Use the Visual Basic editor

to create DSP Functions.

Rename the module to

something that starts with
dsp using the properties
Module 27 - 29
box
- confidential -
 DSP Language:
Creating a DSP Function with a DSP procedure
Create a public function and define the input parameters, in this case
there is the input variable capture which is a DspWave that contains
capture data
Other input parameters are defined, separated by commas

Using the type

ahead features
of VBT you can
type in part of a
command and
then select the
appropriate
choice from a
drop-down list

Module 27 - 30

- confidential -
 DSP Language:
Creating a DSP Function with a DSP procedure (cont.)

Continue to add arguments and use the type ahead feature selecting
from a drop-down list until all the necessary inputs for the dsp analysis
are included. The number of arguments will be defined by the test
being executed
In this case, the data to be analyzed is in the DspWave Capture, a
calculated signal to noise ratio will be returned in snr, and the total
harmonic distortion will be returned in thd

VBA will automatically The return type for all

add the End Function Dsp Procedures must be
delimeter Long

Module 27 - 31

- confidential -
 DSP Language:
Creating a DSP Function with a DSP procedure (cont.)

Dimension a
New DspWave
variable
specwave

Set specwave to point

to the result of the
.Spectrum operation
Specwave will then
contain the spectrum
of the input capture

Module 27 - 32

- confidential -
 DSP Language:
Creating a DSP Function with a DSP procedure (cont.)

Use the Dsp object

CalcSNR method to
calculate the signal to noise
ratio of the captured data

VB will prompt for any required

inputs after an open parentheses

Module 27 - 33

- confidential -
 DSP Language:
Creating a DSP Function with a DSP procedure (cont.)

Like the last slide, use the

Dsp object CalcTHD
method to calculate the
total harmonic distortion of
the captured data and
supply inputs as necessary

Module 27 - 34

- confidential -
 DSP Language:
Creating a DSP Function with a DSP procedure (cont.)

The .Plot method will

display the contents of a
DspWave in a WaveScope
window
This code line is considered
a no-op when run on an
embedded processor

Module 27 - 35

- confidential -
 DSP Language:
Summary of DSP Wave Objects

• Refer to the Object

Browser in VBA to
see members of a
DspWave object
– In VBA, press F2 and
search for dspwave
– DspWave members will
appear in the members
frame

Help is available for each

DSPWave

Module 27 - 36

- confidential -
 DSP Language: Example

Source DUT Capture

We will now create an example DSP Procedure using the Procedure

Development Environment
This example measures Gain Tracking Error (how consistent the gain
(from input to output) remains, based on providing several input
levels)
Several signals will be sourced with decreasing amplitude
The gain for each input/output pair will be calculated with respect to
the full scale gain, and the worst case gain error will be stored and
tested against limits

Module 27 - 37

- confidential -
 DSP Language:
Example: Gain Tracking Error Test Flow
Here is the test flow for the gain tracking procedure. In each loop iteration the amplitude of the sourced
signal will be halved, and the gain between the device input and output will be calculated and compared to
the full scale gain. The worst deviation from the full scale gain will be stored and compared against limits.

Connect and setup Wait long enough for

source and capture captures to complete

Stop the source

Tracking loop to be Calculate gain for

executed several times current capture

VBT to track gain,

increment loop count,
Setup source, capture, and halve the source
and read back signals amplitude

Reset the instrument

Start source and trigger

capture and read back Test the limits
Module 27 - 38

- confidential -
 DSP Language:
Example: Timing Context and Source Signal

The test will use

a sinewave
signal as shown, Source Signal
and the source
and capture
sampling
information is
shown in the
mixed signal
timing context

Mixed Signal
Timing Context

Module 27 - 39

- confidential -
DSP Language:
VB Code: DSP Procedure

This DSP Procedure calculates the relative gain between

the device input and output signals and returns the value
to the test procedure

'return the relative gain between two input DSPWaves

1 2
Public Function Gain(SrcInWv As DSPWave, CapInWv As DSPWave, _
AbsGain 3As Double) As Long
4 Dim SrcSigLvl As Double, CapSigLvl As Double

SrcSigLvl = SrcInWv.CalcRMS 'get signal magnitude for source

5
CapSigLvl = CapInWv.CalcRMS 'get signal magnitude for capture

'calculate the gain between the input signal and output signal
6 AbsGain = 20 * Log(CapSigLvl / SrcSigLvl) / Log(10)
End Function

(1),(2):input dsp waves, (3): input for return of result, (4): create local variables,
(5):calculate signal levels, (6): calculate gain from levels and return results

Module 27 - 40

- confidential -
 DSP Language:
VB Code: VBT Element Function

This multipurpose VBT Element Function keeps track of the

worst case gain, handles the incrementing of loop variables,
and reduces the source waveform amplitude by a factor of two
'Handle gain tracking operations, loop variables, and source amplitude
Public Function GainTrackingOps(AbsGain As Double, GainErrMax As Double, _
loopCount As Long, LoopMax As Long, srcPin As String, srcAmp As Double) 1
'static storage for base line gain
2 Static BaseLineGain As Double

'if first loop, store baseline gain, otherwise check gain tracking
If loopCount = 0 Then
BaseLineGain = AbsGain
3 ElseIf Abs(BaseLineGain - AbsGain) > GainErrMax Then
GainErrMax = Abs(BaseLineGain - AbsGain)
End If

'increment loop count

4 loopCount = loopCount + 1

'decrease source amplitude by half

5 srcAmp = srcAmp / 2
End Function

(1):Inputs, (2): Static local variable that holds value between function calls, (3): On first loop
store gain in static variable, otherwise check and store gain tracking values, (4): Increment loop
count, (5): Attenuate source amplitude

Module 27 - 41

- confidential -
 DSP Language:
Variable Table and Element Editors

Here is the final variables table for the

gain tracking procedure and the
completed element editors for the
DspProcedure and VBT Element

Here are the completed

element editors for the
Interpose elements

Module 27 - 42

- confidential -
 DSP Language:
Test Procedure Instance Editor
The instance editor is used to specify any variable procedure inputs
when creating an instance of the procedure
The Instance Editor Wizard will do most of the work of creating
this form, and the user can customize the results in the Visual
Basic Editor (this example has the inputs sorted onto named tabs)

Module 27 - 43

- confidential -
 DSP Language:
Test Procedure Instance Editor

Module 27 - 44

- confidential -
 Debugging in VBT:
Visual Basic - Setting Breakpoints

A breakpoint is set
in the code by
clicking in the
gutter area where
the red dot is, by
using the debug
menu, or by right
clicking on a line
and selecting
Toggle/breakpoint

Module 27 - 45

- confidential -
 Debugging in VBT:
Using the Step Function

When the function

executes in debug
mode, execution
will stop before the
breakpoint line is
executed
The next line of
code to be run is
indicated by the
yellow highlight
The F8 key steps to
the next line of
code, and the
yellow arrow can be
dragged to change
the next line of
code to be
executed
Mousing over a
variable in break
mode will popup
display the value

Module 27 - 46

- confidential -
 Debugging in VBT:
Visual Basic Add Watch

Variables can be
watched in a
special window so
their values can be
seen at all times
The easiest way to
add a watch is to
select the name of
the desired variable
in the code editor,
right click, and
select Add Watch…
This will bring up
the add watch
dialog with different
watch options

Module 27 - 47

- confidential -
 Debugging in VBT:
Visual Basic Step

This shows the

code after stepping
to the last line of
the function
Notice the three
variables in the
watch window and
their reflected
values

Module 27 - 48

- confidential -
DSP Functions

Rev0343
- confidential -
 DSP Functions
Constructs

Allowed constructs

For Step Next

If Then Else
Do Loop
While Wend
Select Case

Resume

Module 27 - 50

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 DSP Functions
VB Functions

Allowed VB functions

Sin
Cos
Tan
Atn
Rnd
Exp
Log
Sqr

Module 27 - 51

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 DSP Functions
DataTypes

Allowed datatypes

Dim MyDspWave As DspWave

Dim dbl As Double

Dim int As Integer
Dim cpx As Complex

Module 27 - 52

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 DSP Functions
Some Key Properties and Functions(1)

MyDspWave.SampleSize
MyDspWave.SampleRate

Set A = B.Add(C)
Set A = B.AddScalar(1.0)
Set A = B.Sin
Set A = B.LogBase(double)

value = A.Element(index)
rmsval = A.CalcRMS
sum = A.CalcSum
snr = A.CalcSNR(bin,#harmonics)

Module 27 - 53

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 DSP Functions
Some Key Properties and Functions(2)
A.CreateSin omega,phase,size
A.LetData dataArray()

Set A = B.Histogram(bins,min,max)

Set A = B.Spectrum
Set A = B.FFT
Set A = B.FFTInverse([newSampSize])

A.Plot(plotName)
Set A = B.Copy

Module 27 - 54

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IIM
Deferred Binning
Test Flow

Traditional Test Flow

Setup Measure DSP Bin Setup Measure DSP Bin Setup Measure DSP Bin

time

Deferred Binning Test Flow

Setup Measure Setup Measure Setup Measure Bin Bin Bin

DSP DSP DSP time

Module 27 - 55

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 Deferred Binning
Flow Table

Deferred binning is set up in the flow table

The Test-defer-limits opcode is used instead of the Test opcode to set up
deferred limits for a test procedure
The limits opcode will evaluate the limits of a previously deferred test (waiting
for the results of unfinished analysis if necessary)
The limits-all opcode will evaluate all outstanding limits

Module 27 - 56

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-Appendix-

Module 27 - 57

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FLEX VB DSP Code Analysis

Module 27 - 58

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Some DSP pieces (lpf)

Module 27 - 59

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Some DSP pieces(squareFD)

Module 27 - 60

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Some DSP pieces(squareTD)

Module 27 - 61

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Some DSP pieces(notch)

Module 27 - 62

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Some DSP pieces(rms)

Module 27 - 63

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 Chaining
• DspWave Functions that return DspWaves as
results can be chained
• Here are two examples
– the first takes a waveform, adds 4.2 to each element,
then divides each element of the result by 1.8, the result
is then stored in the original variable using the set
statement
– The second plots the spectrum of a wave with each
element divided by two, the value of MyWave is not
changed

Module 27 - 64

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 WaveScope

The WaveScope tool is used to look at waveform data. It currently

supports displaying waveforms from the Mixed Signal Workshop, text
files and IMAGE .wav files.

Module 27 - 65

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 Properties

Basic Properties
MyDspWave.Name
MyDspWave.DataType
MyDspWave.SampleSize
MyDspWave.SampleRate
MyDspWave.CaptureID
MyDspWave.Data
MyDspWave.Domain
MyDspWave.FrequencyResolution
MyDspWave.Power
myDspWave.SpectrumFormat

MyDspWave.Info…

Module 27 - 66

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 Usage

Basic Usage

Dim A As DspWave
Dim B As DspWave
Dim C As DspWave

Set A = B.Operation(C)

Module 27 - 67

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 Selections

Selections

A.Selection(offset,stride,size) *
NOTE:
These three A.Selection().Replace B *
calls are done
in place -> A is A.Selection().FillWithConstant k *
changed after
the function A.Selection().Clear *
call

Set B = A.Copy
A.Concatenate(B)

*not supported for complex rectangular data

Module 27 - 68

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 Functions

Arithmetic functions
Set A = B.Abs #
Set A = B.Negate #
Set A = B.Reciprocate #

Set A = B.Add(C) *
Set A = B.Subtract(C) *
Set A = B.Multiply(C) *
Set A = B.Divide(C) *

Set A = B.AddScalar(1.0) #
Set A = B.SubtractScalar(1.0) #
Set A = B.MultiplyScalar(1.0) #
Set A = B.DivideScalar(1.0) #

* B and C must have same type

# not supported for complex rectangular data

Module 27 - 69

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 Functions
Trigonometric functions (not supported for cplx rect data)

Set A = B.Sin
Set A = B.Cos
Set A = B.Tan
Set A = B.Atan
Set A = B.Atan2(C)

Set A = B.LogBase(double)
Set A = B.LogBase10
Set A = B.LogBaseE
Set A = B.ExpBase(double)
Set A = B.ExpBase10
Set A = B.ExpBaseE

Set A = B.SquareRoot
Set A = B.Square

Module 27 - 70

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 Scalars(1)

Functions which return scalars (not supported for cplx rect data)

value = A.Element(index)
dotprod = A.CalcDotProduct(B)
rmsval = A.CalcRMS
maxmag = A.CalcMaxMagnitude
maxval = A.CalcMaxValue(returnIndex)
meanval = A.CalcMean
minmag = A.CalcMinMagnitude
minval = A.CalcMinValue(returnIndex)
sum = A.CalcSum
sumsqr = A.CalcSumSquares

Module 27 - 71

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 Scalars(2)

Functions which return scalars (A must be a power spectrum)

binval = A.CalcAmplitudeFromSpectrum(bin)
freqval = A.CalcFrequencyFromSpectrum(bin)
sfdr = A.CalcSFDR(bin)
sinad = A.CalcSINAD(bin)
snr = A.CalcSNR(bin,#harmonics)
thd = A.CalcTHD(bin,#harmonics)

Module 27 - 72

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 Data Creation, Import/Export

Functions (not supported for cplx rect data)

A.CreateConstantInt val,size
A.CreateConstantReal val,size
A.CreateCos omega,phase,size
A.CreateSin omega,phase,size
A.CreateRampInt initial,increment,size
A.CreateRampReal initial,increment,size

A.FillWithConstant val
A.FileExport fileName,fileType
A.FileImport fileName,fileType

A.LetData dataArray()
A.LetDataInt dataArray()
A.LetElement

Module 27 - 73

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 Functions

Functions
Set A = B.Histogram(bins,min,max) *
Set A = B.Integrate(InitVal) *
Set A = B.IntegrateElements *
Set A = B.Differentiate *
Set A = B.Clip(LowLim,HighLim) *
Set A = B.Lookup(C) *
Set A = B.MatrixMultiply(rows,cols,C) *

Set A = B.ExtractImag #
Set A = B.ExtractReal #
Set A = B.CombineRealAndImag(C) *
Set A = B.ExtractMagnitude #
Set A = B.ExtractMagnitudeSquared #
Set A = B.ExtractPhase #
Set A = B.CombineMagnitudeAndPhase(C) *
*not supported for complex rectangular data
#only complex rectangular data supported
Module 27 - 74

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 Conversion

Conversion Functions (not supported for cplx rect data)

Set A = B.ConvertToBinary
Set A = B.ConvertToOffsetBinary
Set A = B.ConvertToInteger
Set A = B.ConvertToReal
Set A = B.ConvertFromFrac2
Set A = B.ConvertTo1sComp
Set A = B.ConvertTo2sComp
Set A = B.ConvertToSerial(…)
Set A = B.ConvertToSignMagnitude(#bits)

Module 27 - 75

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 Bitwise

Bitwise Functions (integer datatype)

Set A = B.BitwiseComplement
Set A = B.BitwiseExtract(#bits, BitPosition)

Set A = B.BitwiseAnd(C)
Set A = B.BitwiseOr (C)
Set A = B.BitwiseXor(C)

Set A = B.BitwiseAndScalar(mask)
Set A = B.BitwiseOrScalar(mask)
Set A = B.BitwiseXor(mask)

Set A = B.BitwiseShiftLeft(#bits)
Set A = B.BitwiseShiftRight(#bits)

Module 27 - 76

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 Comparison

Logical Comparison functions (not supported for cplx rect data)

Set A = B.LogicalEqual(C)
Set A = B.LogicalGreater(C)
Set A = B.LogicalGreaterThanOrEqual(C)
Set A = B.LogicalLessThan(C)
Set A = B.LogicalLessThanOrEqual(C)
Set A = B.LogicalNotEqual(C)

Set A = B.LogicalEqualScalar(val)

Set A = B.LogicalNot

Module 27 - 77

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 Spectral

Spectral functions
Set A = B.Spectrum *
Set A = B.Convolve(C) *
Set A = B.Correlate(C) *
Set A = B.Filter(C,factor) *

Set A = B.FFT *
Set A = B.FFTInverse([newSampSize]) #

*not supported for complex rectangular data

#only complex rectangular data supported

Module 27 - 78

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 Spectral

Spectral functions (not supported for cplx rect data)

Set A = B.Resample(rate,samples)

Set A = B.WindowHamming
Set A = B.WindowHanning
Set A = B.WindowHanning2
Set A = B.WindowBlackmann

Module 27 - 79

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 Display

Display functions (not supported for cplx rect data)

A.Plot(plotName)
A.PlotRemove(plotName)
A.PlotRemoveAll

Module 27 - 80

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 Multiple Captures

Functions

A.Next

Module 27 - 81

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 VBT DSP Function/Procedure Called From a Test Procedure

DSP Procedures are another type of

VBT that are used in test procedures
to do DSP analysis
This procedure takes in a DSPWave
object and returns the average DC
offset of part of the samples
Unlike interpose functions, a DSP
function is called for each site

DSP procedures have

Input waveform Variable for the result
flexible declaration rules

Select 50 samples

Get the mean value

Module 27 - 82

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 VBT DSP Function/Procedure Called From a Test Procedure(hard coded):
coded): Inserting
Previous Examples Into Flow Chart Editor

The DspProcedure test element is used in the PDE to call DSP Functions
The name of the DSP procedure to be used must be hard coded in the
PDE and cannot be an instance editor input

Select a user
created DSP
procedure from
the list

The editor
changes to match
the selected DSP
procedures
arguments

The DspWave
contains the input
samples captured
previously, the
second argument
will get the result

Module 27 - 83

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 VBT DSP Function/Procedure Called From a Test Procedure: Instantiating
Instantiating a Procedure
and Adding it to the Flow Table

The test procedure is

instantiated on the Test
Instances sheet, where any
variable parameters are
entered
The test is the added to
the flow table and is ready
to run

Module 27 - 84

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 Module 27 - 85

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Digital Source/Capture

Rev0343
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 Objective

• The Goal of this session is to introduce the

Digital Signal Source Capture instruments,
understand the hardware functionality, and learn
how to program the source and capture
instrument in a Pattern File.

Module 28 - 2
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 Outline
¾ DSSC Overview

¾ Wave Definition and Sampling Size

¾ Programming Digital Signal Source and Capture

¾ Test Procedures and Test Elements

¾ Pattern File Instrument Commands

¾ Pattern Tool

¾ Debug Displays

Module 28 - 3
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 Converter Testing
DSSC Analog
1111110000 Capture
D/A
0111001100
1010101010
DSSC
1111110000
Analog A/D 0111001100
Source
1010101010

Digital Signal Source is used as a digital waveform input to a D/A

Digital Signal Capture is used as an digital waveform output of a A/D

Module 28 - 4
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 Digital Source/Capture
• Each DSSC can send/capture data to the digital channels
in either serial or parallel. When sending/capturing data
in parallel, the data sample or word width can be :
– Up to 32 bits wide
– Up to 16 bits wide
– Up to 8 bits wide.
• When sending/capturing data in serial, the data can be
sent/captured with the most significant bit (MSB) first or
with the least significant bit LSB) first. The sample or
word width can be
– Up to 32 bits wide
– Up to 16 bits wide
– Up to 8 bits wide

Module 28 - 5
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 HSD Block Diagram
Patterns LVM
Load
SVM circuit
Opcodes Driver
VIH
VT
DSSC Alternate
B Data Pogo
a Alternate Source
c Data Select VIL
MTO Bus
k
p
SCAN
l
PATGEN Detector Voh
a
PPMU
n
e
History Vol
RAM Voh
PPMU
12 Timing
Generators Vol

VIH Driver
VT

To Pin Electronics 4 Pogo

device channels per
VIL
TG
Load
circuit

Module 28 - 6
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 Overview

Alternate Data Bus

6 DSSC engines (per HSD board)
Source/Capture

16M x 16 bits per engine

32-bit maximum word size
Memory

(32 bit shift register)

Digital Signal 100 Mbits per second maximum data
Source/Capture transfer rate
For >50Mbps operation, the DSSC
source waveform sample size must be
even (2 bits per channel)

Serial or Parallel modes

IIM LVM Full matrix connection to any digital
Format channel (ADB lines)
Up to 64 Mb
Timing
PEM Reconfigurable between patterns
SVM 1K

To DSP
Capture and source instruments can exist
on the same HSD board, a DSSC instrument
can span multiple HSD boards.

Module 28 - 7
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 DSSC & ADB
Sub- SVM LVM
Routine Microcodes
vector
memory
Large
DSSC Source DSSC Capture vector
MTO
memory

SCAN
Alternate Data Bus (ADB)

6 Independent 16-
bit Digital Signal
Engines per Board
for Digital Signal The data may be sent
Source and to any of the 48
Capture. channels over the
Channels 1-48 HSD 200
alternate data bus.

Module 28 - 8
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 Architecture
A DSSC instrument can
span multiple HSD Ch #1-16 Ch #17-32 Ch #33-48
boards. However, in
such cases, the same
number of engines will
be allocated on each
board.
A digital channel can
28-bit 28-bit 28-bit be connected to a

The DSSC is a virtual instrument. An

slice slice slice DSSC source and a
DSSC capture
instrument can be made up of 6 DSSC 1 2 3 instrument to provide
engines depending on the mode of I/O.
operation. The software driver takes care of
the engine assignment once the user has
set up the instrument mode. 84-bit Alternate Data Bus

16-bit 16-bit 16-bit 16-bit 16-bit

16-bit

Module 28 - 9
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Programming the Digital
Signal Source/Capture
1. Waveform Creation
Use Wave designer and Mixed-Signal Workshop to create
primitives and sampling size

2. Digital Signal Test Elements

Create test elements using PDE for edit and debug

3. Extended Microcodes in a Pattern file

Setup Instrument initiated commands and add microcodes
to create DSSC

4. VBT Language
Use interpose functions when necessary

Module 28 - 10
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 Wave Definition Worksheet

Add a wave definition

worksheet and a wave
name. Click on the ellipsis
button to create waveform
primitives

Module 28 - 11
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 Mixed Signal Worksheet

Add a mixed Signal

timing sheet and
Context Name. Click
on the ellipsis button Use mixed signal
to create a timing workshop to
context. determine sample
size to be applied to
the waveform
created using Wave
Designer for DSSC
start.

Module 28 - 12
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 Procedure Worksheet

Typically a
procedure will
include DSSC
Add a test procedure instrument setup
worksheet and add a elements and a
DSSC procedure name. pattern start
Click on the Ellipsis element which will
button to enter PDE. be used to start or
trigger the
instrument

Module 28 - 13
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 Test Elements

The DSSC Test

elements can be
used to setup the
instrument
instrument and the
pattern final can
initiate the start or
capture.

Module 28 - 14
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 DSSC Source Element

The DSSC Source

Signal Element
editor lets you set
up the instrument
to source a
waveform.

Module 28 - 15
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 DSSC Capture Element

The DSSC Capture

Signal Element
editor lets you set
up the instrument
to capture a
waveform.

Module 28 - 16
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 Pattern Start Element

Use the pattern

Start Editor to
define a pattern file
that will initiate the
DSSC instrument
to Source and
Capture.

Module 28 - 17
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 Instance Editor

Add a test to the

instance sheet to
call the DSSC test
procedure.

Module 28 - 18
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Instance Editor

Select the Pattern

file that initiates the
DSSC Instruments.

Module 28 - 19
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 Instance Editor

Define the amplitude

and offset and the
Source and capture
labels. The labels
should match the
wave names in the
pattern file that will be
used to Start the
Source and Trigger
the capture.

Module 28 - 20
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 Pattern File Commands
The Digital Source and Capture are typically defined and initiated in the
Pattern File.
For the Digital Signal Source Capture (DSSC) instrument, the
instrument statement defines:
¾ Which pins or channels are to be used for DSSC
¾ How each is to be used for source or for capture
¾ Width of the instrument
¾ Connection mask (optional)
¾ Bit order (optional)
¾ Instrument mode— serial or parallel (optional)
¾ Site uniqueness (optional)
¾ Timing mode (optional)
¾ Format (optional)

Module 28 - 21
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 Pattern File Header Syntax

Source Instrument
instruments = {
pin-item : digsrc : instrument-width : connection-mask : bit-order :
instrument-mode : site-uniqueness : timing-mode : format ;
}

Capture Instrument

instruments = {
pin-item : digcap : instrument-width : connection-
mask : bit-order : instrument-mode : site- uniqueness : timing-mode :
format ;
}

DSSC Language

Module 28 - 22
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 Header Syntax Examples
The following are some examples of valid instrument statements:

Parallel Example:
Instruments={
(A7, A6, A5, A4, A3, A2, A1): digsrc:7:connection_mask=00fe:timing_mode=dual;
(RBus, GBus, BBus): digsrc: 8;
(RBus, GBus, BBus): digcap: 8; In the parallel mode of
operation, pin order is always
}
determined by the test pattern.

Serial Example: RBus, GBus and BBus are pin

Instruments= { groups containing 8 pins each
(Din) : digsrc : 4 : lsb: serial :format=twos_complement;
(Dout): digcap: 4 : lsb: Serial:format=twos_complement;
}

Module 28 - 23
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 Pattern File Body Syntax
asine1 is the
General Syntax: name of a
primitive
(pin-item: instrument = microcode) created using
Wave
designer and
Mixed Signal
Workshop.

Source Examples: Capture Examples:

((Din): digsrc = start asine) ((Dout): digcap = trig my_cap)
((Din): digsrc = nop) ((Dout): digcap = nop)
((Din): digsrc = shift) ((Dout): digcap = shift)
((Din): digsrc = send) ((Dout): digcap = store)

Module 28 - 24
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 Source Microcodes
• start <wave name> (512 different names per pattern)
Load a source segment from memory defined by wavename and resets
• starte <wave name>
Load a source segment from memory defined by wavename but wait for
current waveform to complete before beginning.
• start_inst_cond <wave name>
Normal start, but instrument condition is enabled.
• shift
Serially shift the data MSB or LSB as controlled by the instrument setup.
• send
Send Data to the digital channel(s).
• nop
No operation
• stop
Immediately stops the source state machine and clears the data FIFO

There must be at least 20 “nop”s between a “start” and “shift” or

“send”

DSSC Language Module 28 - 25

- confidential -
definitions
 Capture Microcodes
• trig <capture label> (4 unique labels per pattern)
Trigger data collection
• nop
• No operation
• shift
Serially shift data 1 bit at a time lsb or msb first
• store
•Capture the data currently on the bus and store it in capture memory

There must be at least 20 “nop”s between a “trig”

and “shift” or “store”

Module 28 - 26
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 DigCap Opcode Display

Triple click on the

Microcode cell to
display the Menu.

Module 28 - 27
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DigSrc Opcode Display

Triple click on the

Microcode cell to
display the Menu.

Module 28 - 28
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 Source Debug Display
Select Source or
Capture from the
drop down menu.

DIB Slot,
Instrument slot,
ADB line
Source Waveform
Settings

Instrument Slot,
Engine selected.

Module 28 - 29
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Capture Debug Display

Use the view

button to display
the captured data
as a DSPwave
object

Module 28 - 30
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 16-bit Parallel, 50Mbps
In this example:
16 digital channels
16 ADB bits
1 DSSC engine is used
DUT

16 digital channels

16-bits of ADB

1 DSSC engine 16 bits

Module 28 - 31
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 32-bit Parallel-dual, 100Mbps
In this example:
32 digital Channels
14 channels from slice 1 any channels
14 channels from slice 2 any channels
4 channels from slice 3 any channels
64 ADB bits – 2 bits per channel DUT
4 DSSC engines are used – 16 bits each Remember: In dual mode
2 adb bits are required for
14 channels 14 channels 4 channels each digital channel.

32 digital channels 100Mbps

28 bits 28 bits 8 bits

64-bits of ADB

4 DSSC engines 16-bits 16-bits 16-bits 16-bits

Module 28 - 32
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Width of DUT data bus
DSSC Modes - Examples
Instruments ADB
Engines Channels
Mode Width Speed per board Lines
Used Used
Used
Parallel_dual 32 100 1 4 32 64
Parallel_dual 16 100 2 4 32 64

Parallel_dual 8 100 5 5 40 80
Parallel_single 32 50 1 2 32 32
Parallel_single 16 50 3 3 48 48
Parallel_single 12 50 4 X 4 = 48 48

Serial_dual 32 100 6 6 6 12
Serial_dual 16 100 6 6 6 12
Serial_single 32 50 6 6 6 6
Serial_single 16 50 6 6 6 6

Parallel and serial modes can exist on the same HSD board

Module 28 - 33
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Appendix

Rev0343
- confidential -
 DSSC Rules
No Pinmap or channel map entries required specifically for DSSC

An Instance of the instrument is identified by a pin and pattern combination in

a pattern file.

if a job contains 10 test patterns, and each of these patterns makes use of 1
digital signal source, there are 10 uniquely identifiable instances of the
instrument.

These 10 instances of the digital signal source or capture may or may not
make use of the same DSSC engine(s).

The DSSC driver software automatically allocates the DSSC engine(s) to

each instrument instance at the start of the test pattern and de-allocates the
engine(s) after the test has been executed.

Module 28 - 35
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 DSSC Language
Instrument width

instrument-width specifies the width of the instrument used for source or capture. This is a
required field.
It is used as follows:

For parallel instruments, instrument-width should equal the total number of pins in the pin
items, except in the case of source fanout.

For serial instruments, instrument-width should equal the number of shifts per word in the
pattern.

To use source fanout, the number of pins must be an integer multiple of the number of bits.
The number of bits for parallel instruments equals the instrument-width. For serial
instruments, the number of bits equals 1. (Capture instruments cannot fanout; each pin
item must have its own capture instrument. This case is not valid for a capture
instrument.) If source fanout is used, each opcode statement for the shared instrument
must specify the same pins in exactly the same way.

Module 28 - 36
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 DSSC Language
Connection Mask
connection-mask is an optional field used only for parallel modes to indicate the output-bit-to
pin connections. It is only relevant when the number of bits is not equal to 8, 16, or 32. The
syntax is connection_mask=<mask>. This mask must be specified in hex format, and its
maximum value is 32 bits (0xffffffff). If this field is not specified, it defaults to lsb justified.

Bit Order
bit-order is an optional field used only for serial modes to indicate the bit order of the data. The
bit-order value is either msb, meaning the most significant bit is shifted in first, or lsb, meaning
the least significant bit is shifted in first. If the DSSC is in a serial mode, and this field is not
specified, it defaults to msb.

Instrument Mode
instrument-mode is an optional field used to indicate a serial or parallel instrument. The
instrument-mode value is either serial or parallel. If the field is not specified, it defaults to
parallel.

Module 28 - 37
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 DSSC Language
Site Uniqueness
site-uniqueness is an optional field used only for source instruments to specify source
instrument sharing across sites, where possible. The site-uniqueness value is either
unique_sites or nonunique_sites. If this field is not specified, it defaults to
unique_sites.

Timing Mode
timing-mode is an optional field used to specify the timing mode of the DSSC. The
syntax is timing_mode=<mode>. The valid values for the mode are patgen, single or
dual. If the value is patgen, then the DSSC will run in the same timing mode as the
patgen. If the value is single or dual, the DSSC will run in single or dual timing modes
regardless of the patgen. If this field is not specified, it defaults to patgen.

Format
format is an optional field used to indicate the format of the data being sourced or
captured. The syntax is format=<format>. The valid values for the format are binary,
offset_binary, ones_complement, twos_complement, sign_magnitude,
format_unknown, or frac_twos_complement. If this field is not specified, it defaults to
binary.

Module 28 - 38
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 Source VBT Language
TheHdw.DSSC.Pins(Din).Pattern(Pattern).Source.Waveforms

Module 28 - 39
- confidential -
 Source VBT Language
TheHdw.DSSC.Pins(<pin spec>).Pattern(<pattern spec>).Source
Pin(PinSpec As String) As DriverDSSCPins Pattern(PatternSpec As String) As DriverDSSCPattern

ApplyMSTiming(resourceID As String)

Module 28 - 40
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 Digital Signal Capture VBT Language

TheHdw.DSSC.Pins(<pin spec>).Pattern(<pattern spec>).Capture

Module 28 - 41
- confidential -
 Digital Signal Capture VBT Language

.Waveforms.

TheHdw.DSSC.Pins(Din).Pattern(Pattern).Capture.Waveforms.Item.DSPWave.Pin.Chan(

Module 28 - 42
- confidential -
 VBT Language

TheHdw.DSSC.Reset

TheHdw.DSSC.ListInstruments

Module 28 - 43
- confidential -
BBAC

Revision: 0343
- confidential -
 Main Objective

“Successfully generate, source and capture an analog waveform using

the FLEX BBAC Source and BBAC Capture instruments”

PRELIMINARY VERSION Module 29 - 2

- confidential -
 SESSION 1

• Overview of BBAC Source and Capture Instruments

– Generic Source and Capture Instruments
– FLEX Family of AC Instruments
– BBAC Board and Instrument Block Diagrams
– Recommended Configuration
– BBAC Source Characteristics
– BBAC Capture Characteristics

• FLEX User-Model
– Worksheet and related tools

PRELIMINARY VERSION Module 29 - 3

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 Generic Arbitrary Waveform Generator

OUT +
Source Zero-Order
PGA
Memory Hold DAC LPF(s)
OUT -

Programmable Clock Range Output Driver

Control

• Source Memory used to store digital samples for conversion into a continuous time
waveform
• D/A Converter converts waveform data into stepped analog voltages
• Low Pass Filter smoothes stepped signal into a continuous waveform
• Programmable Gain Amplifier adjusts the signal amplitude
• Output Driver

based on An Introduction to Mixed-Signal IC Test and Measurement, by Burns and Roberts

PRELIMINARY VERSION Module 29 - 4
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 Generic Waveform Digitizer

INPUT + Capture
PGA ADC
INPUT - LPF(s) Memory

Input Programmable Clock

Range
Control

• Input for capturing differential outputs from the DUT

• Programmable Gain Amplifier adjusts the signal level entering the ADC to minimize noise
effects of quantization error from the ADC
• Low Pass Filter used to limit the bandwidth of the incoming signal
• Analog to Digital Converter converts continuous time analog waveforms into digitized
representations
• Capture Memory used to store digital samples of continuous time waveform
based on An Introduction to Mixed-Signal IC Test and Measurement, by Burns and Roberts
PRELIMINARY VERSION Module 29 - 5
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 FLEX AC Instrumentation

SOURCES:
DCVI DCVI AC Source used for power, automotive and low-res converters
BBACSRC Broad Band AC Source used for audio, baseband and DSL
VHFACSource Very High Frequency AC Source for video and consumer device testing

DIGITIZERS:
DCVI DCVI AC Capture used for power, automotive and low-res converters
BBACCAP Broad Band AC Capture used for audio, baseband and DSL
VHFACCapture Very High Frequency AC Capture for video and consumer device testing

PRELIMINARY VERSION Module 29 - 6

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 What is the BBAC

• The BBAC instrument board contains 2 independent differential AWG sources

and 2 differential digitizers.

• The BBAC Source is a high-performance instrument that can generate

differential, low-noise, low-distortion waveforms with frequency components
of up to 15MHz.

• The BBAC Capture is a high-accuracy, low-noise instrument that can acquire

differential waveforms with frequency components of up to 15MHz with very
little distortion.

PRELIMINARY VERSION Module 29 - 7

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 BBAC Board Block Diagram
Psets
Pattern Parameter
Generator Sets Memory

UCode

PPMU
PPMU
PPMU

4Meg SMEM SOURCE Offset Level

PPMU
PPMU
High BW DataPort

1 Meg CMEM CAPTURE Offset Range

PPMU
PPMU
PPMU

4Meg SMEM SOURCE Offset Level

PPMU
PPMU

1 Meg CMEM CAPTURE Offset Range

PRELIMINARY VERSION Module 29 - 8

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 BBAC Board Block Diagram

PRELIMINARY VERSION Module 29 - 9

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 BBAC Source Block Diagram

1 2 3 4 5 6

1. Normalized digital samples of the waveform are loaded into source memory (SMEM).
The source memory is 4M samples in depth.
2. Digital resampling is used to convert the data from the user sample rate (Fs), to the
insturments fixed 100Msps sample rate. This data is then passed through a digital to
analog convertor to generate an analog source signal.
3. The analog signal is then passed through a fixed 15MHz low pass filter to remove
images that were generated from the conversion process.

PRELIMINARY VERSION Module 29 - 10

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 BBAC Source Block Diagram

1 2 3 4 5 6

4. The analog signal passes through a voltage ranging stage, to attenuate the signal
to the desired amplitude. Note that the impedance is controlled to maintain a 50Ω
output.
5. Common mode offset can be added to the source signal using the bias voltage
input on the reference pin, and then additionally using the DC baseline circuitry.
6. The differential signal is delivered to the DUT on the Positive and Negative source
pins.

PRELIMINARY VERSION Module 29 - 11

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 BBAC Capture Block Diagram

1 2 3 4 5 6 7 8

1. The signal to be captured enters the BBAC capture differential input pins.
2. If necessary, the signal can be AC coupled to remove the DC components present in
the input signal. Typically, this is only necessary if the input signal has an AC + DC
voltage level that exceeds the instrument compliance (+/-7V with respect to CCC).
3. The DC baseline removal circuitry can be used to adjust the DC signal level of either
the positive pin, the negative pin, or both. This is useful for removing differential
offset in the signal so that a smaller capture range can be used, and so that the AC
component of the signal will make better use of the instruments dynamic range.
PRELIMINARY VERSION Module 29 - 12
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 BBAC Capture Block Diagram

1 2 3 4 5 6 7 8

4. The voltage ranging circuitry is used to scale the signal to ensure that it fits within
the dynamic range of the analog to digital converters. The range specifies the
maximum instantaneous voltage difference that can be applied between the
positive and negative input pins.
5. The scaled input signal passes through a 15MHz low pass filter to attenuate out of
band frequency components that would result in aliased signal components.
6. The filtered analog signal is then converted to a digital signal using a combination
of low frequency and high frequency analog to digital converters.
PRELIMINARY VERSION Module 29 - 13
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 BBAC Capture Block Diagram

1 2 3 4 5 6 7 8

7. The high and low frequency digital signals are recombined into one signal by a
digital crossover filter. This fixed data rate signal is then resampled to the user’s
sample rate through states of interpolation and decimation. The signal is then
passed through a ¾ band filter, which removes any aliasing that was introduced
by the resampling process.
8. Digital samples from the resampling and filtering stage are routed to a 1M sample
capture memory. When the capture is complete, the BBAC automatically transfers
the capture data to the support board for DSP processing

PRELIMINARY VERSION Module 29 - 14

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 Recommended Configuration

• The BBAC Board may be installed in any and all of 24 universal test head slots

• For the following reasons, it is recommended that slot selection guidelines are
adhered to as much as possible when a tester is configured with the BBAC:
– Minimize the number of different configurations within an organization,
which simplifies resource and production planning
– Reduce the likelihood of not being able to move an application from one
tester to another without having to make hardware changes to the second
tester
– Standardize tester configurations at test houses
– Increase the probability of finding a matching tester when outsourcing test
requirements

• Typical test head slots (in recommended order) for the FLEX BBAC are:
1, 14, 13 and 26

• These correspond to typical DIB slots:

2, 50, 25 and 27 respectively.

PRELIMINARY VERSION Module 29 - 15

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 BBAC Source Characteristics
These are not official specifications and are subject to change. See ESSD for actual specifications.

• Frequency Range (Bandwidth) DC → 15MHz

• Programmable User Sample Rate Range 5Ksps → 1Gsps

• Waveform Memory Depth 4 Msample (1024 single segments)
• AC Performance (Noise Density) -140 → -145 dBFs/√Hz

• Amplitude Variation with Frequency 10Hz → 20kHz ±0.05dB

20kHz → 1MHz±0.10dB
1MHz → 5MHz ±0.20dB
5MHz → 15MHz +0.20, -1.0dB

• DC Offset - Common Mode +5.0V, -2.5V

• Maximum AC 2.56 Vpk single-ended, pos/neg - ground
5.12 Vpk differential, pos - neg
• Peak Output Voltage (DC + AC) +6.0Vpk, -5.0Vpk

PRELIMINARY VERSION Module 29 - 16

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 BBAC Source Characteristics cont’d
These are not official specifications and are subject to change. See ESSD for actual specifications.

• Output Impedance 50Ω ± 0.4Ω

• Capacitive Load < 1 nF

• Output Current Compliance Limit > 51 mA

• Short Circuit Current < 80 mA
• Slew Rate > 500 V/µs, nominal

• Total Harmonic Distortion -105dBc → -68dBc

(50Hz → 15MHz)

• Spurious Free Dynamic Range -98dBc → -70dBc for single tone

(@ 50Ω , based on 5.12V range) (50Hz → 15MHz)
-90dBc → -62dBc for dual tone
(50Hz → 15MHz)

PRELIMINARY VERSION Module 29 - 17

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 BBAC Capture Characteristics
These are not official specifications and are subject to change. See ESSD for actual specifications.

• Frequency Range DC → 15MHz

• Programmable User Sample Rate Range 5Ksps → 50Msps

• Waveform Memory Depth 1 Msample
• Capture Pass Band (up to 15MHz) 0 → 3/4 * Fs/2
• Capture Stop Band 5/4 * Fs/2 → ∞

• Amplitude Variation with Frequency 10Hz → 20KHz ±0.05dB

20KHz → 1MHz ±0.10dB
1MHz → 5MHz ±0.20dB
5MHz → 15MHz +0.20, -1.0dB

• DC Offset (Baseline Removal) ± 6.0Vdc, pos/neg or both

• Maximum AC 10.24 Vpk

PRELIMINARY VERSION Module 29 - 18

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 BBAC Capture Characteristics cont’d
These are not official specifications and are subject to change. See ESSD for actual specifications.

• Input Impedance > 9.8 MΩ (nominal)

• Input Capacitance < 300 pF (nominal)
• CMRR (DC to 10KHz) > 90dB (typical)

• AC Coupling
Maximum DC Input ± 150 Vdc (nominal)
LF cutoff, precharge OFF < 1Hz (nominal)
LF cutoff, precharge ON 68kHz

• Total Harmonic Distortion -97dBc → -70dBc

(50Hz → 15MHz)

• Spurious Free Dynamic Range -93dBc → -70dBc for single tone

(@ 50Ω , based on 10.24V range) (50Hz → 15MHz)
-93dBc → -67dBc for dual tone
(50kHz → 15MHz)

PRELIMINARY VERSION Module 29 - 19

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 Mixed-Signal Basic Test Program
Worksheets Block Diagram
Home

7
1
Pinmap Specification Sheets 3 Mixed-Signal Pattern
Calls
6a
0 Microcode
DUT pin: name, type Global Wave 1
Specs Definition 2
Wave ASCII
Designer 3 file
2 Tool
Visual Basic Channel Map DC Specs Calls
Interpose Calls 6b Returns
Tester Pin AC Specs Returns
Functions Pattern Tools
channel name
Mixed-Signal
Timing Editor
Mixed-Signal Debugger
8 4 5 Workshop
User defined Tool
procedures Procedures Pin Levels Time Sets
via PDE tool
Returns
Invoke TDE
9 for Hardware Displays
Visual Basic Test
Interpose Instances
Functions

Order
10 Default Programming Sequence:
Tests
Flow Worksheets
Table 1 to 6 7 8 to 10
Opcode (sequencing) Additional Worksheets P attern Worksheets
Worksheets and PDE Tools and PDE

PRELIMINARY VERSION Module 29 - 20

- confidential -
 SESSION 2

• Developing a Test Program:

– DIB Considerations
– Pinmap and Channel Map
– Wave Designer (wave shape definition)
– Mixed-Signal Workshop (timing solution)
– Developing a Test Procedure
• BBAC Source Test Elements
• BBAC Capture Test Elements

PRELIMINARY VERSION Module 29 - 21

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 DIB Connectivity

BBAC SRC REF

BBAC SRC POS

BBAC SRC NEG

BBAC CAP POS

BBAC CAP NEG

Differential CODEC (with Internal Digital Loopback)

PRELIMINARY VERSION Module 29 - 22

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 Home Worksheet

PRELIMINARY VERSION Module 29 - 23

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 Pin Map Worksheet

PRELIMINARY VERSION Module 29 - 24

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 Channel Map Worksheet (Signal View Mode)

BBAC SRC REF

BBAC SRC POS
BBAC SRC NEG
BBAC CAP POS
BBAC CAP NEG

PRELIMINARY VERSION Module 29 - 25

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 Channel Map Worksheet (Pogo View Mode)

BBAC SRC REF

BBAC SRC POS
BBAC SRC NEG
BBAC CAP POS
BBAC CAP NEG

PRELIMINARY VERSION Module 29 - 26

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 Wave Definitions Worksheet

PRELIMINARY VERSION Module 29 - 27

- confidential -
 Wave Designer Tool

PRELIMINARY VERSION Module 29 - 28

- confidential -
 Mixed Signal Timing Worksheet

Expected Capture
Frequency
Capture Sample Rate
Capture Sample Size

Source Frequency

PRELIMINARY VERSION Module 29 - 29

- confidential -
 Mixed Signal Workshop Tool

Capture Sample Rate

Source Frequency

Expected Capture Frequency

Capture Sample Size

PRELIMINARY VERSION Module 29 - 30

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 Mixed Signal Workshop Tool
Solving the Coherency Equation for the Source, ...

Target Capture
Frequency

Source Frequency

PRELIMINARY VERSION Module 29 - 31

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 What Does MSW Do For The Source?

Source Sample Rate and Size Rules:

• The BBAC Source instrument requires a source sample rate that is greater than
20 times the highest frequency of interest:

Fs ≥ 20 × Fi where Fi is the highest frequency

component of the source waveform

• The BBAC Source has a miminum sample size to realize the ESSD performance.
This minimum sample size guarantees that the resampling process meets all
the spur and distortion requirements of the instrument.
• The minimum sample size required is the larger of 20 or the next higher integer
of the ratio of the user sample rate to 100Msps, times 8:

Fs
N = max[ 20 || ceiling ( ) × 8]
100 Msps

PRELIMINARY VERSION Module 29 - 32

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 Mixed Signal Workshop Tool
... and now for the Capture

Minimum Capture
Bandwidth

PRELIMINARY VERSION Module 29 - 33

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 Capture BW Sample Rate Rule
• The BBAC Capture instrument has a digital low pass filter that begins to roll off at 3/8
of the capture sample rate. Accordingly, choose a capture Fs such that:
8
Fs = × BW where BW is the bandwidth of interest
3
B B A C C a p tu r e 3 /4 F ilte r

20
A tte n u a ti o n
0

-20

-40
N yq u i s t
-60 F re q u e n c y
dB -80
A li a s i n g
-1 00

-1 20

-1 40

-1 60

-1 80
0 1 /8 1 /4 3 /8 1 /2 5 /8 3 /4 7 /8 1
F / Fs

PRELIMINARY VERSION Module 29 - 34

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 Test Procedures Worksheet

1. Connect BBAC Src/Cap

2. Setup BBAC Src/Cap

3. Start/Trigger BBAC Src/Cap

4. Analyze Captured Signal

5. Stop Source & Disconnect

PRELIMINARY VERSION Module 29 - 35

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 BBAC Source Test Elements

1. BBAC Source Connection

The BBACSourceConnections test element is used to connect and disconnect the
BBAC Source instrument.

2. BBAC Source Signal

The BBACSourceSetup test element is used to specify the amplitude and timing
parameters on the BBAC Source instrument. Scaling and ranging information are
specified using the voltage range, amplitude, and common mode controls. Timing
information is specified using a mixed signal timing context.

3. BBAC Source Actions

The BBACSourceActions test element can be used for start, stop, and instrument
reset actions on the BBAC Source instrument.

PRELIMINARY VERSION Module 29 - 36

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 BBAC Source Connection Element
Pins
Specifies a pin or a pin list, which identifies the BBAC
Source channel(s) that is to be connected or
disconnected from a resource.
Pos, Ref, Neg
The Positive (POS), Reference (REF), and Negative
(NEG) parameters each specify whether to connect or
disconnect the instrument channel to the pin specified.
To/From
The TO/FROM parameter is a dynamic setting which
specifies the destination of the instrument’s channel
connection. Choose DUT, CCC, or DGS from the drop-
down list.

VBT Example:
Public Function Connnect_BBAC_Source(SrcPin As String) As Long
' typical differential instrument connection to DUT/DIB
thehdw.BBACSource(SrcPin).Connect tlBBACSourceFromInst, tlBBACSourceToDUT
End Function

PRELIMINARY VERSION Module 29 - 37

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 BBAC Source Signal Element
Pins
Specifies a pin or a pin list, which identifies the BBAC
Source channel(s) that is to be setup.
Signal Name
The name of the signal which is to be programmed
Use as Default Signal
If the signal is the default, it can be started later
without referring to the signal name
Load Settings
Load the signal settings into the hardware

PRELIMINARY VERSION Module 29 - 38

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 BBAC Source Signal Element
Load from Mixed Signal Timing Set
Load waveform information from the Mixed Signal
Timing Context specified on the levels and timing tab
Resource ID
If multiple BBAC sources appear in the timing
context, specify the resource ID of the one to load
WaveDef Name
Specify the name of the wave definition which
defines the signal shape
Sample Rate (Fs)
Specify or override the sampling rate
Number of Samples (N)
Specify or override the number of samples
Number of Cycles (M)
Specify or override the number of cycles
Phase
Specify the starting phase of the signal in degrees

PRELIMINARY VERSION Module 29 - 39

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 BBAC Source Signal Element
Connection Type
Specify a single ended or differential connection
Amplitude
Specifies the amplitude of the signal in Volts peak (VPK)
Offset
Signal offset, added to the pos signal, subtracted from neg
Common Mode
Common mode offset, value is added to both the pos and
neg pins
Voltage Range
The element programs the smallest voltage range above
the value specified.
Programming Tip:
When the common mode hardware is disabled, the BBAC Source
Reference pin input is not buffered. If the Source Reference pin is
connected to a device pin that does not have drive capabilities, a
buffer should be added to your DIB.
Programming Tip:
When the common mode hardware is enabled it adds noise to the
source signal. Accordingly, the common mode hardware should be
disabled unless it is needed for the device/test application.

PRELIMINARY VERSION Module 29 - 40

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 BBAC Source Signal Element
VBT Example:
Public Function Setup_BBAC_Source (SrcPin As String, Amp As Double, _
SigName As String) As Long

With thehdw.BBACSource (SrcPin)

.VoltageRange.Autorange = True
'.VoltageRange.Value = Vrange
.Amplitude = Amp
.CommonModeVoltageEnabled = False
'.CommonModeVoltage.Value = CM_Offset
.ApplyMixedSignalTiming
End With

With thehdw.BBACSource(SrcPin).Signals.Item(SigName)
.WaveDefinitionName = "aSine“
.SampleRate = 22500
'.CycleCount = 3
.Phase = 45
.LoadSettings
End With
End Function

Programming Tip:
Using the auto range feature simplifies test development and picks
a range for optimal dynamic performance. However, re-ranging
requires additional instrument settling time.

PRELIMINARY VERSION Module 29 - 41

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 BBAC Source Actions Element
Pins
Specifies a pin or a pin list, which identifies the BBAC
Source channel(s) that will execute the action.
Action
Specifies the action to be performed – there are
several methods to start and stop waveforms, and a
reset method
Signal Name:
Specifies the name of a Signal to start or stop

VBT Example:
Public Function Start_BBAC_Source (SrcPin As String, SigName As String) As Long
' perform a start immediate on the default waveform
thehdw.BBACSource(srcpin).Signals.Item(SigName).Start
End Function

PRELIMINARY VERSION Module 29 - 42

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 BBAC Capture Test Elements

1. BBAC Capture Connection

The BBACCaptureConnections test element is used to connect and disconnect the
BBAC Capture instrument.

2. BBAC Capture Signal

The BBACCaptureSetup test element is used to specify parameters such as
voltage range, DC offset control, and coupling mode. Additionally, the sampling
parameters like sample rate and capture sample size are provided from the mixed
signal timing context but can be overwritten in the test element.

3. BBAC Capture Actions

The BBACCaptureActions test element can be used for trigger, precharge and
instrument reset actions on the BBAC Capture instrument.

4. BBAC Capture Alarms

The BBACCaptureAlarms test element can be used to program instrument alarm
behavior.

PRELIMINARY VERSION Module 29 - 43

- confidential -
 BBAC Capture Connection Element
Pins
Specifies a pin or a pin list, which identifies the
BBAC Source channel(s) that is to be connected
or disconnected from a resource.
Pos, Neg
The Positive (POS), and Negative (NEG)
parameters each specify whether to connect or
disconnect the instrument channel to the pin
specified.
To/From
The TO/FROM parameter is a dynamic setting
which specifies the destination of the
instrument’s channel connection. Choose DUT,
CCC, or DGS from the drop-down list.

VBT Example:
Public Function Connnect_BBAC_Capture(CapPin As String) As Long
' typical differential instrument connection to DUT/DIB
thehdw.BBACCapture(CapPin).Connect tlBBACCaptureFromInst, tlBBACCaptureToDUT
End Function

PRELIMINARY VERSION Module 29 - 44

- confidential -
 BBAC Capture Signal Element
Pins
Specifies a pin or a pin list, which identifies the BBAC
Capture channel(s) that is to be setup.
Signal Name
The name of the signal which is to be programmed
Use as Default Signal
If the signal is the default, it can be triggered later
without referring to the signal name
Load Settings
Load the signal settings into the hardware

PRELIMINARY VERSION Module 29 - 45

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 BBAC Capture Signal Element
DSP Wave
The DSP Wave variable in the variables table which will
receive the captured signal
Load from Mixed Signal Timing Set
Load signal information from the Mixed Signal Timing
Context specified on the levels and timing tab
Resource ID
If multiple BBACCapture instruments appear in the
timing context, specify the resource ID of the one to
load
Sample Rate (Fs)
Specify or override the sampling rate
Number of Samples (N)
Specify or override the number of samples
Number of Cycles (M)
Specify or override the number of cycles

PRELIMINARY VERSION Module 29 - 46

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 BBAC Capture Signal Element
Voltage Range
The element programs the smallest voltage range
above the value specified.
Coupling
Specifies if the capture should use AC or DC coupling.
Offset Mode
Enable and set up the offset mode
Offset
Specifies the value of the offset to be removed from
the capture signal.

Programming Tip:
When DC coupled, the BBAC Capture requires significantly less
settling time as compared to AC coupling. Accordingly, unless
necessary for device/test conditions, using the BBAC Capture DC
coupled is recommended.

Programming Tip:
As can be noticed by the test element, the majority of the BBAC
Capture Setup parameters are not required. During initial test
development it helps to focus on the critical/required test
parameters.

PRELIMINARY VERSION Module 29 - 47

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 BBAC Capture Signal Element
VBT Example:
Public Function Setup_BBAC_Capture (CapPin As String, Vrange As Double, _
CapSig As String) As Long

' code example for setting up the BBAC Capture

With thehdw.BBACCapture (CapPin)
.VoltageRange.Value = Vrange
.Offset.Enable = tlBBACCaptureOffsetDisable
.Coupling = tlBBACCaptureCouplingDC
.ApplyMixedSignalTiming
End With

With thehdw.BBACCapture(CapPin).Signals(CapSig)
.SampleRate = 150000
.SampleSize = 512
.CycleCount = 1
.LoadSettings
End With
End Function

PRELIMINARY VERSION Module 29 - 48

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 BBAC Capture Actions Element
Pins
Specifies a pin or a pin list, which identifies the BBAC
Capture channel(s) that will execute the action.
Action
Specifies the action to be performed: Trigger, Reset,
Precharge.
Signal Name:
Specify the capture signal to trigger.
Precharge Time
Amount of time to precharge instrument

VBT Example:
Public Function Trigger_BBAC_Capture (CapPin As String, CapSig As String) As Long
' perform a trigger using the current instrument settings.
thehdw.BBACCapture(CapPin).Signals(CapSig).Trigger
End Function

PRELIMINARY VERSION Module 29 - 49

- confidential -
 BBAC Capture Alarms Element
Pins
Specifies a pin or a pin list, which identifies the BBAC
Capture channel(s) to be programmed.
Alarms
Specifies the Alarm or Alarms to be programmed.
Alarm Behavior
Specifies the action to take when the selected alarm
occurs.

PRELIMINARY VERSION Module 29 - 50

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 SESSION 3

• Instantiating a Procedure

• Using the Instruments (BBAC Source and Capture Analog Loopback)

– Step-Through using Test Debug Environment (TDE)
• Flow Chart Editor
• BBAC Source Debug Display
• BBAC Capture Debug Display
• Pattern Tool

• Lab 1: BBAC Source – BBAC Capture Analog Loopback

PRELIMINARY VERSION Module 29 - 51

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 Test Instances Worksheet

PRELIMINARY VERSION Module 29 - 52

- confidential -
 Test Instances Tabs

PRELIMINARY VERSION Module 29 - 53

- confidential -
 TDE: BBAC Source Debug Display

PRELIMINARY VERSION Module 29 - 54

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 TDE: BBAC Capture Debug Display

PRELIMINARY VERSION Module 29 - 55

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 TDE: Flow Chart & Pattern Tool

PRELIMINARY VERSION Module 29 - 56

- confidential -
 Mixed-Signal Basic Test Program
Worksheets Block Diagram
Home

7
1
Pinmap Specification Sheets 3 Mixed-Signal Pattern
Calls
6a
0 Microcode
DUT pin: name, type Global Wave 1
Specs Definition 2
Wave ASCII
Designer 3 file
2 Tool
Visual Basic Channel Map DC Specs Calls
Interpose Calls 6b Returns
Tester Pin AC Specs Returns
Functions Pattern Tools
channel name
Mixed-Signal
Timing Editor
Mixed-Signal Debugger
8 4 5 Workshop
User defined Tool
procedures Procedures Pin Levels Time Sets
via PDE tool
Returns
Invoke TDE
9 for Hardware Displays
Visual Basic Test
Interpose Instances
Functions

Order
10 Default Programming Sequence:
Tests
Flow Worksheets
Table 1 to 6 7 8 to 10
Opcode (sequencing) Additional Worksheets P attern Worksheets
Worksheets and PDE Tools and PDE

PRELIMINARY VERSION Module 29 - 57

- confidential -
 LAB 1: Dual Site Audio Loopback

• Create an analog loopback test program using the BBAC Source and BBAC
Capture instruments.

Key Test Conditions:

Source Capture
Fi = 1kHz Fs = 96kHz
Amplitude = 1VRMS N = 4096

PRELIMINARY VERSION Module 29 - 58

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 SESSION 4

• HSD and BBAC Clocking

• PSets

• Pattern Microcodes

• Lab 2: Pattern controlled Start and Trigger

PRELIMINARY VERSION Module 29 - 59

- confidential -
 HSD Reference Clock

29
fhsd = 100MHz •2 29
29 I ≥ 1, 0 < J < 2
2 •I+J

fhsd = 53,687,091,200,000,000.00 Hz
N

(N ≥ 536,870,912)

PRELIMINARY VERSION Module 29 - 60

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 BBAC Reference Clock

40
fbbac= 100MHz •2 40
40 I ≥ 1, 0 < J < 2
2 •I+J

fbbac = 109,951,162,777,600,000,000.00 Hz
N

(N ≥ 1,099,511,627,776)

PRELIMINARY VERSION Module 29 - 61

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 BBAC Parameter Sets

• An instrument Parameter Set (PSet) can be used to modify instrument

hardware settings using a pattern microcode.
• It improves repeatability due to Host computer independence.
• PSets can improve throughput by minimizing pattern – Host computer
handshaking.
• BBAC PSets support incremental programming.
• PSets allow for the control of a subset of instrument parameters:
BBAC Source BBAC Capture
– Amplitude – Sample Rate
– Voltage Range – Block Size (Sample Size)
– Sample Rate – Block Count
– Block Spacing
– Extra Samples
– Voltage Range

PRELIMINARY VERSION Module 29 - 62

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 BBAC Source PSet Examples

Add new PSet “a” to all the instument instances behind pin Ain
TheHdw.BBACSource.Pins(“Ain”).PSets.Add “a”

Set all the parameters of PSet “a” (Amplitude = 2.2, SampleRate = 44kHz,VoltageRange = 2.56)
TheHdw.BBACSource.Pins(“Ain”).PSets(“a”).Set 2.2, 44000, 2.56

Adding a PSet that already exists resets the PSet back to its default state (Amplitude of 1.0V, SampleRate of
10MHz, VoltageRange of 1.28V, all parameters set to tlPSetUseValue).
TheHdw.BBACSource.Pins(“Ain”).PSets.Add “a”

Set PSet “a” SampleRate to 1.5MHz

TheHdw.BBACSource.Pins(“Ain”).PSets(“a”).SampleRate = 1500000

Apply PSet “a”. Since SampleRate is the only tlPSetUseValue parameter SampleRate will be programmed to
1.5MHz, while Amplitude and VoltageRange remain unchanged.
TheHdw.BBACSource.Pins(“Ain”).PSets(“a”).Apply

PRELIMINARY VERSION Module 29 - 63

- confidential -
 BBAC Capture PSet Examples

Add and setup PSet “a” on pin “Aout”. This sets BlockCount to 20, BlockSize to 1024, BlockSpacing to
500, ExtraSamples to 100, SampleRate to 400kHz, and VoltageRange to 5.12V.
TheHdw.BBACCapture.Pins(“Aout”).PSets.Add(“a”).Set 20, 1024, 500, \
100, 400000, 5.12

Disable ExtraSamples from PSet a.

TheHdw.BBACCapture.Pins(“Aout”).PSets(“a”).ExtraSamples.Mode = \
tlPSetNoChange

Try to apply PSet a. This will result in a run-time error, because ExtraSamples.Mode, BlockSize.Mode and
BlockCount.Mode all have to be set the same for the current BBAC Capture.
TheHdw.BBACCapture.Pins(“Aout”).PSets(“a”).Apply

Disable BlockSize and BlockCount from PSet a so the PSet can be applied.
TheHdw.BBACCapture.Pins(“Aout”).PSets(“a”).BlockCount.Mode = tlPSetNoChange
TheHdw.BBACCapture.Pins(“Aout”).PSets(“a”).BlockSize.Mode = tlPSetNoChange

Now the PSet can be applied. This will program ExtraSamples to 100, SampleRate to 400kHz and
VoltageRange to 5.12.
TheHdw.BBACCapture.Pins(“Aout”).PSets(“a”).Apply

PRELIMINARY VERSION Module 29 - 64

- confidential -
 BBAC Source Opcodes
START <wavename> Start sourcing the named waveform immediately and repeat indefinitely.

START1 <wavename> Start sourcing the named waveform immediately but do not repeat it.

Start sourcing the named waveform at the end of the currently running
STARTE <wavename> segment and repeat it indefinitely.
Start sourcing the named waveform at the end of the currently running
START1E <wavename> segment but do not repeat it.
Stop sourcing any continuously running (only if started with START or
STOP STARTE) segment immediately. Upon a STOP, the BBAC Source jumps to the
last sample in the segment and continuously sources the value.
Forces the source channel clock into phase alignment with the High Speed
RESYNC Digital T0 clock
PSET <name> Change the setup parameters to those specified in the named Parameter Set.

NOTE: Refer to the ESSD for microcode spacing requirements

PRELIMINARY VERSION Module 29 - 65

- confidential -
 BBAC Capture Opcodes
TRIG <trig_id> Start capturing to CMEM under the label <trig_id>.

Forces the capture channel clock into phase alignment with the High Speed
RESYNC Digital T0 clock
PSET <name> Change the setup parameters to those specified in the named Parameter Set.

ENABLE_INST_COND Enables the instrument condition bit to drive the condition bus.

DISABLE_INST_COND Disables the instrument condition bit to drive the condition bus.

Enables the alarm window for Capture alarms. Alarm conditions that exist
ENABLE_ALARM after this opcode are reported.
Disables the alarm window for Capture alarms. Alarm conditions that exist
DISABLE_ALARM after this opcode are reported.

NOTE: Refer to the ESSD for microcode spacing requirements

PRELIMINARY VERSION Module 29 - 66

- confidential -
 LAB 2: Dual Site Audio Loopback

• Modify the Lab 1 solution to use pattern microcode control for the BBAC
Source and Capture Instruments

PRELIMINARY VERSION Module 29 - 67

- confidential -
 -Appendix-

PRELIMINARY VERSION Module 29 - 68

- confidential -
 SESSION 5

• Hardware Block Diagrams

– BBAC Pinout
– BBACSRC and BBACCAP Summary of Operation
• Multirate Signal Processing

PRELIMINARY VERSION Module 29 - 69

- confidential -
 BBAC Pinout in the FLEX
1 15 38
D
C
B
A
CABLE

A B
1
2 Src2+
3 Src1+ Src2sh
4 Src1sh Src2Ref
5 Src1Ref Src2Refsh
6 Src1Refsh Src2-
7 Src1-
8 DGSs2
9 DGSs1 DGSs2sh
10 DGSs1sh Cap2+
11 Cap1+ Cap2sh
12 Cap1sh DGSc2
13 DGSc1 DGSc2sh
14 DGSc1sh Cap2-
15 Cap1-

PRELIMINARY VERSION Module 29 - 70

- confidential -
 BBAC Pinout cont’d

A B A B C D
16 Accs1- 31
17 Accs1+ Accs1-sh 32
18 Accs1+sh Accs1Ref 33
19 Accs2Ref Accs1Refsh 34
20 Accs2Refsh Accs2- 35
21 Accs2+ Accs2-sh 36 DIBtrigs2 DIBtrigc2
22 Accs2+sh AccCap1- 37 DIBtrigs1 DIBtrigs2sh DIBtrigc1 DIBtrigs2sh
23 AccCap1+ AccCap1-sh 38 DIBtrigs1sh DIBtrigc1sh
24 AccCap1+sh AccCap2-
25 AccCap2+ AccCap2-sh
26 AccCap2+sh
27
28
29
30

PRELIMINARY VERSION Module 29 - 71

- confidential -
 BBAC Source Block Diagram

Let’s look at the source architecture in more detail

PRELIMINARY VERSION Module 29 - 72

- confidential -
1
Source Memory

• Sample memory and control memory are stored in the source memory, or
SMEM.

• SMEM is 4M sample deep.

• SMEM is where segments are stored. The segment is a group of samples

that describes the shape of a waveform.

PRELIMINARY VERSION Module 29 - 73

- confidential -
2
BBAC Source Digital Resampler

• A time-domain filter convolves with n samples located in the source memory,

and the result is expressed as a new sample. This process is repeated at
100Msps. A window of n samples, n/2 located before, and n/2 after the
required 100Msps sample, is used.
calculated samples

samples to be calculated

user-specified sample

new sample at 100Msps

time-domain samples
* user-specified sampling frequency

fixed 100Msps sampling frequency

SLIDE

CONVOLUTION

PRELIMINARY VERSION Module 29 - 74

- confidential -
3
Noise Shaping Requantizer

• If oversampling (Fs >> 2*Fmax), quantization noise is almost uniformly

distributed over the entire frequency band up to Nyquist frequency.
• Oversampling can move most of the quantization noise out of the band
of interest, but it is not yet noise shaping.
• Noise Shaping technique can move almost all the noise out of the band
of interest.

• For more information on Noise Shaping, please see Noise Shaping Requantization

PRELIMINARY VERSION Module 29 - 75

- confidential -
4
Parallel Digital-to-Analog Conversion

• BBAC Source uses multiple DACs in parallel to create a composite DAC.

Signal adds in current, and Noise

adds in power (not correlated
DAC between 1 DAC and another).
FS = 100Msps

The DAC structure is optimized to give the highest performance in the

full bandwidth up to 15MHz.
The fixed sample rate input allows a simpler, more efficient calibration.

PRELIMINARY VERSION Module 29 - 76

- confidential -
5
Fixed Low-pass Filter

• It is an analog smoothing filter with the following characteristics:

Passband Edge Frequency 15 MHz
Stopband Start Frequency 65 MHz, -80dB typical

0dB

-80dB

15MHz 65MHz

PRELIMINARY VERSION Module 29 - 77

- confidential -
6
Attenuator

• The BBAC Source attenuator behaves as the circuit below:

POS

3dB 3dB 3dB 3dB

(diff)
REF
LPF
3dB 3dB 3dB 3dB

NEG

• The REFerence can be connected to a DC baseline, or channel card common.

• The passive attenuator has 3 dB steps and provides a constant 50Ω output
impedance between the POS and REF pins as well as between the NEG and
REF pins. Fine level control is provided with a digital multiplier on the
motherboard.
PRELIMINARY VERSION Module 29 - 78
- confidential -
 BBAC Capture Block Diagram

Let’s look at the capture architecture in more detail

PRELIMINARY VERSION Module 29 - 79

- confidential -
1 Programmable Voltage Amplifier
Voltage Scaling
• The BBAC Capture ranging circuitry scales the analog input signal so that it
fits within the range of the A/D converters.

• Before rescaling the input signal’s amplitude, the programmable DC

baseline, or the AC coupling, can be used to remove its DC offset.

• If the peak to peak amplitude of the analog input signal is greater than
10.24Vpp, then it is necessary to attenuate the signal to avoid clipping:

CLIPPED
+ 5.12 V

+ AMPLITUDE

FU LL -S CA LE
R AN GE OF
AIN = 4.0 Vpk 0 0 V ou t
AD C
SCALE FACTOR = 2

– AMPLITUDE
– 5.12 V
CLIPPED

PRELIMINARY VERSION Module 29 - 80

- confidential -
1 Programmable Voltage Amplifier
Voltage Scaling cont’d
• If the peak to peak amplitude of the analog input signal is less than
10.24V, then the amplitude should be adjusted to occupy as much of the
10.24Vpp dynamic range of the analog to digital converter as possible:
SCALE FACTOR ++5.12
11 V
V
+ AMPLI TUDE

F U LL -S CA LE
0 0 V out R AN G E O F
AIN
ADC

– AMPLITUDE

– 11
- V
5.12V

• As in the BBAC Source, 3dB steps between scale factors. However, no

fine tuning is present.

PRELIMINARY VERSION Module 29 - 81

- confidential -
1 Programmable Voltage Amplifier
Voltage Scaling cont’d

Voltage Range Scale Factor

- 3dB + 3dB
- 3dB + 3dB
- 3dB + 3dB

.
.
.
+ 3dB

PRELIMINARY VERSION Module 29 - 82

- confidential -
2
Analog Anti-Aliasing Filter

• Passband Edge Frequency 15 MHz

• Stopband Start Frequency 25 MHz, 55dB typical

0dB

-55dB

15MHz 25MHz

PRELIMINARY VERSION Module 29 - 83

- confidential -
3
Analog-to-Digital Conversion

• BBAC Capture uses a composite ADC structure with a crossover filter.

ADC

Crossover Filter
ADC
FS

This ADC structure is optimized to give the best performance in the full
15MHz bandwidth.

PRELIMINARY VERSION Module 29 - 84

- confidential -
4
Crossover Filter

• Combines the captured signal’s higher and lower frequency bands.

Crossover Filter frequency response

1V

HPF frequency response 3.5MHz LPF frequency response 15MHz

PRELIMINARY VERSION Module 29 - 85

- confidential -
5
BBAC Capture Digital Resampler

• A time-domain filter convolves with samples located in the capture memory,

and the result is expressed as a new sample. This process is repeated at the
user-defined sample rate for the BBAC Capture.

calculated samples
samples to be calculated
... ... 100 Msps sample
... ...
new sample at the user-defined
sample rate

time-domain samples

* fixed 100 Msps sampling frequency

new 50 → 100 Msps sample rate

(2n integer multiple of user-defined Fs)

SLIDE

CONVOLUTION
PRELIMINARY VERSION Module 29 - 86
- confidential -
5b
Decimating Filter

• A decimating filter that pre-decimates the 50 → 100 Msps sample rate by h,

where h is a 2n integer (1 ≤ h ≤ 512).

• The result equals M * Fs, where 1 ≤ M ≤ 16, and Fs is the user defined
sample rate.

• Please refer to Decimation and BBAC Capture Summary of Operation

PRELIMINARY VERSION Module 29 - 87

- confidential -
6
¾ Band Filter

• This new sequence of samples is then fed into a ¾ band tracking

digital LPF and the (50 → 100 Msps / Decimating Filter = M * Fs,
where M is a 2n integer) sample rate converted to the used defined Fs.

M * Fs M DIGITAL user defined Fs

LPF

1 1
≥
M 16

• More on this topic in Sample Rate Conversion

PRELIMINARY VERSION Module 29 - 88

- confidential -
6
¾ Band Filter

BBAC Capture 3/4 Filter

Passband:
DC → 3/8*Fs
20
Attenuation Flat response
0

-20

-40
Rolloff:
-60
Nyquist
Frequency
3/8 * Fs → Fs/2
dB -80 - 3dB at 0.47 * Fs
-100
Aliasing
-12dB at Fs/2
-120

-140 Fs/2 → 5/8 * Fs

-160 - 50dB at 0.57 * Fs
-180 -150dB at 5/8 * Fs
0 1/8 1/4 3/8 1/2 5/8 3/4 7/8 1
F / Fs
Stopband:
NOTE: Choose an Fs such that Fs >= 8/3 * BW 5/8 * Fs → 15MHz
Attenuation >= -150dB

PRELIMINARY VERSION Module 29 - 89

- confidential -
7
Capture Memory → DSP → Host CPU
BBACCAP #1 CMEM XpT Support Board

DSP DSP

BBACCAP #2 CMEM

DSP DSP Host Computer

BBACCAP #3 CMEM

Move Bus ~ 50Mbps

TCIO Bus ~6Mbps
Crosspoint Matrix Access ~1.4Gbps

PRELIMINARY VERSION Module 29 - 90

- confidential -
 More information on BBAC

• Acronyms

• References

• DSP & Multirate DSP for ATE

PRELIMINARY VERSION Module 29 - 91

- confidential -
 Useful Acronyms
AC Alternating Current
ADC, A/D Analog-to-Digital Converter
ADSL Asynchronous Digital Subscriber Line
AFE Analog Front End
ANSI American National Standards Institute
ATE Automatic Test Equipment
ATU-C ADSL Termination Unit - Central
ATU-R ADSL Termination Unit - Remote
AWG Arbitrary Waveform Generator
BBAC Broad Band Alternating Current
BBACCAP Broad Band Alternating Current Capture
BBACSRC Broad Band Alternating Current Source
BW Bandwidth
C_MEM Capture Memory
CAP Carrierless AM/PM (Amplitude Modulation/Phase Modulation)
CCC Channel Card Common
CO Central Office
DAC, D/A Digital-to-Analog Converter

PRELIMINARY VERSION Module 29 - 92

- confidential -
 Useful Acronyms cont’d
dB Decibel
DC Direct Current
DIB Device Interface Board
DMT Discrete Multi Tone
DSIO Digital Subsystem Input/Output
DSP Digital Signal Processing (or Processor)
DUT Device Under Test
FIFO First In First Out
FS Sampling Frequency
HIB Handler Interface Board
HPF High-Pass Filter
HSD High-Speed Digital
Hz Hertz (second-1)
IMD Inter-Modulation Distortion
LPF Low-Pass Filter
LSB Least Significant Bit
MBD Missing Band Depth
Msps Mega Samples Per Second

PRELIMINARY VERSION Module 29 - 93

- confidential -
 Useful Acronyms cont'd
MTPR Multi Tone Power Ratio
MUX Multiplexer
ONU Optical Network Unit
PGA Programmable Gain Amplifier
PLL Phase-Locked Loop
POTS Plain Old Telephone System
PSTN Public Switching Telephone Network
QAM Quadrature Amplitude Modulation
RAM Random Access Memory
RX Receiver
S_MEM Source Memory
SERDES Serializer – Deserializer
TX Transmiter
VHF Very High Frequency
VDSL Very high rate Digital Subscriber Line
Vpk Volts (peak)
Vpp Volts (peak to peak)

PRELIMINARY VERSION Module 29 - 94

- confidential -
 References

• IG-XL Solutions (BBAC Source and BBAC Capture Instruments)

• An Introduction to Mixed-Signal IC Test and Measurement,

by Mark Burns and Gordon W. Roberts

• DSP-Based Testing of Analog and Mixed-Signal Circuits, by Matthew Mahoney

• Signal Processing Fundamentals (internal Teradyne seminar), by Dr. Fang Xu

• A Course in Digital Signal Processing, by Boaz Porat

• Digital Signal Processing, by John G. Proakis and Dimitri G. Manolakis

PRELIMINARY VERSION Module 29 - 95

- confidential -
 DSP & Multirate DSP for ATE

• Resampling

• Expansion
• Decimation
• Sample Rate Conversion

• Oversampling
• Dither
• Decibel (measurement scale)
• Noise Shaping Requantization

• Multirate Sampling
• Digital Low-pass Filter/Band Limiting Filter
• Digital-to-Analog Conversion
• Analog-to-Digital Conversion

PRELIMINARY VERSION Module 29 - 96

- confidential -
 Resampling

• Conceptually, a signal which has been sampled at one sample rate can be
converted to a continuous waveform, and then resampled at a different
sampling frequency:

data set 1 DAC ADC data set 2

LPF

Fs1 Fs2

different data sets

• If both sample rates are faster than 2*BW, and the low pass filter cuts off
perfectly at FS1/2, data set 2 will preserve all the information contained in
data set 1.
• We would not actually want to build this physically using DAC’s and ADC’s.

PRELIMINARY VERSION Module 29 - 97

- confidential -
 Expansion

• Expansion is an operation that inserts zero-valued samples in between existing

samples of a discrete-time signal in order to increase the perceived sample rate.
• Expansion is also called interpolation.
• Expansion can be mathematically represented as:

 n
 x  , n/L integer
y[ n ] =   L 
 0,
 n/L noninteger

L = number of zeros inserted in between existing samples + 1

based on A Course in Digital Signal Processing, by Boaz Porat

PRELIMINARY VERSION Module 29 - 98
- confidential -
 Expansion cont’d
Example: L=2

x[n]

0 1 2 3 4 5 6 7 8

n
y[n] = 0 y[n] = x  
2

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

based on A Course in Digital Signal Processing, by Boaz Porat

PRELIMINARY VERSION Module 29 - 99
- confidential -
 Decimation

• Decimation can be considered the discrete-time counterpart of sampling. In sampling,

start with a continuous-time signal x(t), and convert to a sequence of samples x[n].
• Decimation starts with a discrete-time signal x[n], and converts to another discrete-
time y[n], which is formed by subsamples of x[n].
• The formal definition of M-fold decimation, or down-sampling, is:

y[n] = x[nM ] , n integer

• See example on the next slide.

based on A Course in Digital Signal Processing, by Boaz Porat

PRELIMINARY VERSION Module 29 - 100
- confidential -
 Decimation cont’d
Example: M=2

x[n]

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

y[n] = x[2n]

0 1 2 3 4 5 6 7 8

based on A Course in Digital Signal Processing, by Boaz Porat

PRELIMINARY VERSION Module 29 - 101
- confidential -
 Sample Rate Conversion

• Sampling rate conversion can be accomplished by L-fold expansion, followed by

lowpass filtering and M-fold decimation. It can be mathematically described as:

y[n] = ∑ x[i] × h[Mn − Li]

i
or as in the diagram below:

x[n] L DIGITAL M y[n]

LPF

• Although traditionally M/L has been small, such as ¾ and ½, in ATE DSP M/L ratio
can be ANY double-precision value.

based on A Course in Digital Signal Processing, by Boaz Porat

PRELIMINARY VERSION Module 29 - 102
- confidential -
 Sample Rate Conversion cont’d

• Example: L = 3, M = 2 (as in from 40Msps to 60Msps)

x[n] L=3 DIGITAL M=2 y[n]

LPF

x[n]

y[n]

PRELIMINARY VERSION Module 29 - 103

- confidential -
 Sample Rate Conversion cont’d
x[n] y[n]
2-fold interpolation

0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Digital-to-Analog Conversion
r h old
- or de
ze ro
yˆ[t ] z[t ]

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

analog LPF

based on A Course in Digital Signal Processing, by Boaz Porat

PRELIMINARY VERSION Module 29 - 104
- confidential -
 Oversampling

• By oversampling a signal, one can lower the noise power in the band of interest,
i.e., DC to Nyquist.
• In the following example, the noise power is lowered by a factor of 3dB, when
sampling the signal at twice the initial sample rate (2*Fs).
V2

Signal

Noise

V2

initial noise power

3dB lowered noise power

DC Fs/2 Fs 2Fs

PRELIMINARY VERSION Module 29 - 105

- confidential -
 Oversampling cont’d

• Expected SNR (with a full scale signal) due to quantization noise can be calculate,
over the Nyquist band, as:

SNRdB = 6.02 * number_bits + 1.72

• Since the total noise power is in fact the area limited by DC and the actual
sample rate, by changing sampling frequency one can change the actual noise floor.

PRELIMINARY VERSION Module 29 - 106

- confidential -
 Decibel (dB)

10 * log10(1*ref / ref) = the reference power = 0 dB

10 * log10(2*ref / ref) = double the power = 3 dB twice 0dB
10 * log10(4*ref / ref) = double again = 6 dB twice 3 dB
10 * log10(8*ref / ref) = double again = 9 dB twice 6dB

a = 0.000000 b = 1.000000 10 * log10 (a/b) = 10 X (-7) = - 70 dB

a = 0.000001 b = 1.000000 10 * log10 (a/b) = 10 X (-6) = - 60 dB
a = 0.00001 b = 1.000000 10 * log10 (a/b) = 10 x (-5) = - 50 dB
a = 0.0001 b = 1.000000 10 * log10 (a/b) = 10 x (-4) = -40 dB
a = 0.001 b = 1.000000 10 * log10 (a/b) = 10 x (-3) = -30 dB
a = 0.01 b = 1.000000 10 * log10 (a/b) = 10 x (-2) = -20 dB
a = 0.1 b = 1.000000 10 * log10 (a/b) = 10 x (-1) = -10 dB
a = 1.000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.000000 = 0.0 dB
a = 2.000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.301030 = 3.010300 dB
a = 3.000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.477121 = 4.771213 dB
a = 4.000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.602060 = 6.020600 dB
a = 5.000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.698970 = 6.989700 dB
a = 6.000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.778151 = 7.781513 dB
a = 7.000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.845098 = 8.450980 dB
a = 8.000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.903090 = 9.030900 dB
a = 9.000000 b = 1.000000 10 * log10 (a/b) = 10 x 0.954243 = 9.542425 dB
a = 10.00000 b = 1.000000 10 * log10 (a/b) = 10 x 1 = 10 dB
a = 100.0000 b = 1.000000 10 * log10 (a/b) = 10 x 2 = 20 dB
a = 1,000.000 b = 1.000000 10 * log10 (a/b) = 10 x 3 = 30 dB
a = 10,000.00 b = 1.000000 10 * log10 (a/b) = 10 x 4 = 40 dB
a = 100,000.0 b = 1.000000 10 * log10 (a/b) = 10 x 5 = 50 dB

PRELIMINARY VERSION Module 29 - 107

- confidential -
 Dither

• When increasing the sampling frequency by a large factor, it’s possible

that the samples being digitized do not change for several samples;

• Oversampling no longer works well because the noise becomes non-

uniform in the frequency domain. Adjacent samples are correlated.

• In this situation, mixing some random noise, called dither, at the

quantizer input can make the quantization noise uniform in the
frequency domain again;

PRELIMINARY VERSION Module 29 - 108

- confidential -
 Noise Shaping Requantization
• If oversampling (Fs >> 2*Fmax), quantization noise is almost uniformly
distributed over the entire frequency band up to Nyquist frequency
• Oversampling can move most of the quantization noise out of the
band of interest, but it is not yet noise shaping
• Noise Shaping technique can move almost all the noise out of the
band of interest
• A common example of noise shaping is the Sigma-Delta converter:

+
LPF
Amp ADC
-

DAC

PRELIMINARY VERSION Module 29 - 109

- confidential -
 Noise Shaping Requantization cont’d

• In the example below, most of the noise has been moved to beyond Fs/4, which in
this case is out of the band of interest, that is, where the signal’s frequency
component of interest is located.
• However, notice that none of the noise has been eliminated, since the area between
DC and Fs remains the same:

area of = area of

Signal
V2
Noise

DC FS/4 Fs/2 3Fs/4 Fs

PRELIMINARY VERSION Module 29 - 110

- confidential -
 Dither and Noise Shaping Example

PRELIMINARY VERSION Module 29 - 111

- confidential -
 Multirate Sampling

• Example:
In certain circumstances, X bits at Y Msps = 2X bits at Y/2 Msps,
a X-bit DAC at Fs could perform similarly as a X/2-DAC at 2Fs Msps:

data set 1 0 1 0 1 0 1 0 8-bit DAC

t

1/FS
Fs

1 0 1 0 1 0 1 0 4-bit DAC
data set
t + logic

1/(2FS) 1/(2FS)
2Fs

PRELIMINARY VERSION Module 29 - 112

- confidential -
 Low-pass/Band Limiting Filter

What happens when using a low-pass filter?

X H
dot-product
(inner-product)

fcutoff fcutoff

=
fcutoff

Σxixhi
PRELIMINARY VERSION Module 29 - 113
- confidential -
 Digital-to-Analog Conversion
1 data set (words)
00110001
x[n] 2
00110010

00110011
lookup table at Fs
...

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
00110010
xˆ[t ] 3

zero-order hold*

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
* A first-order holder can be
used. Instead of maintaining the x[t ] 4
sample’s value for 1/Fs, the first-
order holder approximates x(t)
by straight-line segments which analog LPF
have a slope that is determined
by the current sample x[i] and
the previous sample x[i-1]. ++
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
++ based on Digital Signal Processing, by Proakis and Manolakis
PRELIMINARY VERSION Module 29 - 114
- confidential -
 Analog-to-Digital Conversion
sampling
x(t ) δ [n]
1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

x(t ) × δ [n] 2 quantization

x[n] 3

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

data set: 00110001, 4

captured data
00110010,
00110011,
... ,
PRELIMINARY VERSION 00110001Module 29 - 115
- confidential -
 Questions?

PRELIMINARY VERSION Module 29 - 116

- confidential -
 VHFAC
Option
Preliminary

Revision: 0343
PRELIMINARY VERSION - confidential -
 Main Objectives of Class

• Source and capture a sinewave looping back the

VHFAC Source to the Capture instrument

• Understand how to program the other VHFAC

instruments:
– Time
– Serial Bus
– Trigger Control
– PPMU

PRELIMINARY VERSION
 Session 1

• VHFAC Overview
– High Level Description
– Physical Description
– Licensing
– Use with FLEX Microwave Option
– VHFAC Characteristics
• Source
• Capture
• Time
• Serial Bus
• Trigger Control
• PPMU

PRELIMINARY VERSION
 VHFAC
Complete VHF Test Option
Pat
Gen
Up to 2 Source & 2 Capture Instruments
PSETS

PPMU
Features:
SRC
- Independent Instrument Clocks
Event Lines
- Precisely Synchronized Sources
PPMU
- Event Lines Sync’d to Source for TV/VTR
CAP
- Multiport Capture Memory
Move
Bus
- Instrument Initiated Move
TMU
PPMU
- Time Measurement Unit
- Serial Bus Digital
Serial
PPMU - Trigger Control
Bus DIB and Internal Instrument Initiated
- PPMU per I/O
Trigger
DIB Triggers
Control

- Multiplexed, Single-ended or Differential

Inputs & Outputs

PRELIMINARY VERSION
 Physical Board
Teradyne Part Number 810-330-xx

PO W ER BO A RD

M O TH ER BO ARD

RID ER RI D ER
BO ARD B O ARD

STI
FFEN ER
FRAME

The physical VHFAC STU D X 12

board is composed of a
frame, a power board, B AC KPLANE C O NN . AU X
C O AX C O N N. CO NN

a mother board, and 2

rider boards. The DIB
interface cable is a
separate part.
PO G O A SSY
Teradyne Part Number 810-330-00

PRELIMINARY VERSION
 DIB Interface Cable

DIB Resources Anywhere

Five standard lengths to meet all

configuration requirements

Available Teradyne Part Numbers:

TEST
HEAD DIB Pogo DIB
SLOT Instrument Description SLOT - 810-330-10
1 1
2
- 810-330-23
2 3 - 810-330-45
4
3 VHFAC_1 5 - 810-330-67
4
VHFAC_1 6
7 - 810-330-89
Support Board 8
5 9
10
6 11
12
7 Support Board 13
(Master) 14
8 15

PRELIMINARY VERSION
 VHFAC Licensing
Instrument Enabling Licenses

Boards
Flexible Configuration
Sources Captures
0 0
- Sources can be selected
1 1 1 0, 1, 2, 4, 6, 8, …, 48
2 2 All with same frequency license
2 4 4
3 6 6 - Capture can be selected
4 8 8 0, 1, 2, 4, 6, 8, …, 48
All with same frequency license

- Source and Capture frequency licenses can

differ
Sampling Frequency Licenses
- Minimum of 1 Source or Capture included in
Video High Speed
base configuration per VHFAC
Msps Bits Msps Bits
Source 100 14 400 14
- Maximum of 2 Sources and 2 Captures per
Capture 80 14 125 12
VHFAC board

PRELIMINARY VERSION
 Mother Board

PO W ER BO A RD

M O TH ER BO ARD

RID ER
Time Trigger RI D ER

Control
BO ARD B O ARD

STI
FFEN ER

Serial Bus
FRAME

PPMU
PPMU
PPMU
PPMU
STU D X 12

B AC KPLANE C O NN . AU X
C O AX C O N N. CO NN

PO G O A SSY

PRELIMINARY VERSION
 VHFAC used with Microwave
Microwave Transmit and Receive
Via VHFAC AUX Connector,

1. VHFAC Source provides modulated

IF signals for FLEX Microwave, and

2. VHFAC Capture digitizes IF signals

down-converted from RF frequencies
by FLEX Microwave

Note: 1. FLEX Microwave Option and

cabling is required in the
configuration
2. Refer to supplemental training:
VHFAC for Microwave

PRELIMINARY VERSION
 VHFAC Source
Arbitrary Waveform Generator
Condition Bit
Filters
Pattern DAC AC/ DC Single End to
2 MHz
Trigger Memory 400 Msps Coupling, Differential
5.5 MHz
8 MB 14 Bits DC Offset Converter
(Video)
10 MHz
20 MHz
40 MHz
80 MHz
160 MHz
Bypass

Event
Trigger
Memory 8 Event Lines
Control
2 MB

Features:
- High Speed, High Resolution DAC
- DC to 160MHz Analog bandwidth
- Wide Filter Selection
- Harmonics and Spurs –70dB @ 10MHz, –55dB @ 40MHz
- Large Waveform and Event Memory
- Event Lines Synced to Source for TV/VTR
- Multiplexed, Single-ended or Differential Outputs

PRELIMINARY VERSION
 VHFAC Source Characteristics
VHFAC Source
AWG Source synchronized with video event lines
Specification Conditions Min Max Units Notes
Sample Rate 0.003434 400 Msps
Resolution 14 bits

Analog Bandwidth DC 160 MHz

Peak Output Voltage
Single Ended (AC + DC Baseline) DC Mode, Open Load -4 4 V

Differential (H or L Output) AC Mode, 50 Ohm Load -3 3 V

Programmable DC Baseline -2 2 V
Waveform Memory 8 MSamples
Event Lines 8 Lines
Event Memory 2 MSamples
Sinewave Spurious DC - 10MHz -70 dBm BW = 10kHz to 100MHz
Level = -30 to -10 dBm
DC - 40MHz -55 dBm BW = 10kHz to 150MHz
Level = -30 to -10 dBm
Noise DC - 80MHz Range, 20 uVms BW = 100Hz to 200MHz
30kHz Resolution BW
Source-Source Relative Phase Error @ 50MHz 0.1 Degree Typical

PRELIMINARY VERSION
 VHFAC Capture
High Resolution Digitizer
Hi Res ADC Filters
Lightening Bus 80 Msps 0.5MHz
14 Bits 2 MHz Peak Detector Impedance
6.1 MHz
Capture Matching,
(Video) Ranging,
Trigger Memory Single End to
10 MHz DC Removal
1 MSample Differential
20 MHz Track and Converter
Hi Speed ADC 40 MHz Hold
Condition Bit 125 Msps 62.5 MHz
12 Bits Bypass

Trigger
Control

Features:
- High Speed and High Resolution ADCs
- Harmonics and Spurs -70dB @ 5Mhz
- Undersampling: DC to 300MHz
- Wide Filter Selection
- Multiport Capture Memory
- Peak Detector for Fast Peak Voltage Measurements
- Multiplexed, Single-ended or Differential Inputs
- Input Voltage Range: 8 mV to 8 V peak
- Instrument Initiated Move Client

PRELIMINARY VERSION
 VHFAC Capture Characteristics
VHFAC Capture
Four mode digitizer instrument: high resolution, high speed, undersampling, peak detect
Specification Conditions Min Typ Max Units Notes
High Resolution Sample Rate 0.003343 80 Msps 14 bit resolution

High Speed Sample Rate 80 125 Msps 12 bit resolution

High Voltage Single Ended 10KOhm (AC + DC) -20.48 20.48 V DC - 9.5MHz frequency
Peak Input Voltage range
Differential AC Coupled 50 Ohm Level Peak differential 0.016 4.096 V In 6 dB steps, DC -
Range 61.5MHz frequency
range
DC Baseline Removal Single Ended DC Coupled -2 2 V
50 Ohm Input
Sinewave Spurious Single Ended DC Coupled -60 dBm 100kHz to 10MHz freq
(High Resolution Mode) 50 Ohm Input range
Differential DC Coupled -70 dBm 100kHz to 5MHz freq
50 Ohm Input range
Undersampling Mode Sampling Rate DC - 300MHz 0.6 3.0 MHz 14 bit resolution

Peak Detector
Frequency Range 0.1 100 MHz 14 bit resolution
Detection Pulse Width 2.0 ns Typical
Reset Pulse Width 1 us Typical

PRELIMINARY VERSION
 VHFAC Time
Time Measurement Unit
Trigger 1 (CH3)
Trigger 2 (CH4)

Front End 1
Event A
Single
Capture Time CH1
Memory A Stamper A
Differential
Move Bus

TMU Slope Event

Vterm
Control Selector Selector

Capture Time Front End 2

Memory B Stamper B CH2
Event B

Features:
- Period, Frequency, Duty Cycle, Pulse Width, Rise/Fall Time,
Propagation Delay, Event Capture Measurements
- Average, Minimum, Maximum of multiple samples, Single-
shot, Variation over Samples and over Time
- Edge, Period, Signal-to-Signal, Jitter Frequency Analysis,
Peak-to-Peak and RMS Jitter Measurements
- Single ended and differential inputs

PRELIMINARY VERSION
 VHFAC Time Characteristics
VHFAC TMU
Mid-performance time measurement unit with dual time stampers and interleavers

Specification Conditions Min Typ Max Units Notes

Input Bandwidth 400 MHz Typical

Resolution Time Range: Low 2.44 ps Nominal

Time Range: High 5 ns Nominal

Time Base 200 MHz

Time Base Error Synchronous Mode -1 1 ppm

Time Between Stamps Time Range: Low 20 ns

Time Stamp Jitter 20 ps rms

Time Stamper Accuracy 30 ps Typical

Memory Depth 512 kSamples

Input Voltage Single Ended, 50 Ohm -10 10 V

Threshold Range Single Ended, 50 Ohm -6 6 V

Hysteresis Range 50 mV Typical

Hysteresis Resolution 0.5 mV Typical

PRELIMINARY VERSION
 VHFAC Serial Bus

VHFAC Serial Bus

Simple digital serial bus for register setting and I2C control.
Specification Conditions Min Max Units Notes
Clock Channel 1
Drive/Receive 2
Vector Rate 0.0024 1.67 MHz
Voltage Levels No Load -4 10 V
Edge Placement Accuracy 30 ns Displacement
between 2
channels
programmed to the
same point in time
Pattern Memory 64 kVectors

PRELIMINARY VERSION
 VHFAC Trigger Control

Condition Bit DUT controlled Instruments

Trigger SRC Video Device Test Pattern Requirement

Condition Bit Features:

Trigger CAP
- 4 trigger I/O lines to DIB

Condition Bit - Access to all instruments

Trigger CH3
TMU
Trigger CH4 - Instruments can trigger other instruments
and the DUT
Condition Bit
Serial
Trigger
Bus

Trigger
To DIB
Control

PRELIMINARY VERSION
 VHFAC Trigger Control Characteristics

VHFAC Trigger Control

Trigger control to and from instruments and device under test

Specification Conditions Min Typ Max Units Notes

Number of Trigger I/O Channels 4

DC Input and Output Levels

VIL -0.5 0.8 V Typical

VIH 2.0 3.6 V Typical

VOL 0.4 V Typical

VOH 2.4 V Typical

IOL 24 mA Typical

IOH -24 mA Typical

Input Leakage Current -10 10 uA Typical

Propagation Delay 10 ns Typical

Minimum Input Pulse Width 20 ns Typical

PRELIMINARY VERSION
1/2
Parallel Test Architecture
DIB Access
DIB Access DC30

1A
DCVI
- Reduce the number of relays
SRC 1 1B on DIB
DIB Access

2A
- Enable true parallel testing by
SRC 2 2B allowing multiple devices to
DIB Access
access resources simultaneously
1A
DUT
CAP 1 1B

DIB Access

2A
CAP 2 2B

DIB Access

TMU CH1
CH2

PRELIMINARY VERSION
2/2
Parallel Test Architecture

DIB Access
1:2 MUX Channels
1A
SRC 1 1B
- Reduce the number of relays
DIB Access
on DIB
DUT 0
2A
SRC 2 2B - Assign instrument to 2 DUTs
or 2 pins on one DUT
DIB Access

CAP 1
1A
1B
- Trade off parallel test for
reduced capital cost
DIB Access

2A
CAP 2 2B DUT 1
DIB Access

TMU CH1
CH2

PRELIMINARY VERSION
 Session 2

• Hardware Block Diagrams

– VHFAC in Integra FLEX
– VHFAC Pinout
– VHFAC Instrument Block Diagrams
– VHFAC Source and VHFAC Capture Summary of Operation
– Signal Processing Block Diagram – Blocks Explained

• Map worksheet fields and tabs to block diagram

– Source
– Capture

• Integra FLEX user-model

– Worksheet and related tools
– Integration with PDE and TDE

PRELIMINARY VERSION
 VHFAC in FLEX

Abundant Analog Resources

2 Sources + 2 Captures per Slot

X 24 Slots

96 analog channels (max)

Plus 1 TMU per board !

Configuration Rules:

- VHFAC requires 1 Integra FLEX slot

- 24 slots in FLEX
- 0 to 24 VHFAC options per system

- IGXL does not limit the number of VHFACs

in a system

PRELIMINARY VERSION
 VHFAC in FLEX
TEST TEST
HEAD DIB Pogo DIB Apps DIB DIB Pogo HEAD
SLOT Instrument Description SLOT Space SLOT Description Instrument SLOT
1 1 26
2 27 26
2 3 28
4 29 25
3 VHFAC_1 5 30 VHFAC_4
VHFAC_1 6 31 VHFAC_4 24
4 7 32
Support Board 8 33 Support Board 23
5 9 34
10 35 22
6 11 36
12 Apps 37 21
7 Support Board 13 38 Support Board
(Master) 14 Space 39 (Slave) 20
8 15 40
16 41 19
9 17 42
18 43 18
10 19 44
Support Board 20 45 Support Board 17
11 VHFAC_3 21 46 VHFAC_2
VHFAC_3 22 47 VHFAC_2 16
12 23 48
24 49 15
13 25 50
14

PRELIMINARY VERSION
 VHFAC Pinout
1 15 38
D
C
B
CABLE
A

VHFAC Hardware Pinout (DIB view)

A B C D
1 Gnd Gnd Gnd Gnd
2 Gnd src2a+ Gnd src2b+
3 src1a+ Gnd src1b+ Gnd
4 Gnd nc Gnd nc
5 nc Gnd nc Gnd
6 Gnd src2a- Gnd src2b-
7 src1a- Gnd src1b- Gnd
8 Gnd DGSs2 Gnd nc
9 DGSs1 Gnd nc Gnd
10 Gnd cap2a+ Gnd cap2b+
11 cap1a+ Gnd cap1b+ Gnd
12 Gnd DGSc2 Gnd nc
13 DGSc1 Gnd nc Gnd
14 Gnd cap2a- Gnd cap2b-
15 cap1a- Gnd cap1b- Gnd
16 Gnd accs1- Gnd event2_1
17 accs1+ Gnd event1_1 Gnd
18 Gnd nc Gnd event2_2
19 nc Gnd event1_2 Gnd
20 Gnd accs2- Gnd event2_3
21 accs2+ Gnd event1_3 Gnd
22 Gnd acccap1- Gnd event2_4
23 acccap1+ Gnd event1_4 Gnd
24 Gnd acccap2- Gnd event2_5
25 acccap2+ Gnd event1_5 Gnd
26 Gnd tmu_ch1- Gnd event2_6
27 tmu_ch1+ Gnd event1_6 Gnd
28 Gnd tmu_ch2- Gnd event2_7
29 tmu_ch2+ Gnd event1_7 Gnd
30 Gnd nc Gnd event2_8
31 tmudgs Gnd event1_8 Gnd
32 Gnd acctmu- Gnd sb_io2
33 acctmu+ Gnd sb_io1 Gnd
34 Gnd nc Gnd sb_clk
35 nc Gnd sbdgs Gnd
36 Gnd dibtrig2 Gnd dibtrig4
37 dibtrig1 Gnd dibtrig3 Gnd
38 Gnd Gnd Gnd Gnd

PRELIMINARY VERSION
 VHFAC Pinout (DIB View)
VHFAC Hardware Pinout (DIB view) VHFAC Software Tester Channel Type
A B C D A B C D
1 Gnd Gnd Gnd Gnd 1 Gnd Gnd Gnd Gnd
2 Gnd src2a+ Gnd src2b+ 2 Gnd VHFACSourcePrimaryPos Gnd VHFACSourceSecondaryPos
3 src1a+ Gnd src1b+ Gnd 3 VHFACSourcePrimaryPos Gnd VHFACSourceSecondaryPos Gnd
4 Gnd nc Gnd nc 4 Gnd nc Gnd nc
5 nc Gnd nc Gnd 5 nc Gnd nc Gnd
6 Gnd src2a- Gnd src2b- 6 Gnd VHFACSourcePrimaryNeg Gnd VHFACSourceSecondaryNeg
7 src1a- Gnd src1b- Gnd 7 VHFACSourcePrimaryNeg Gnd VHFACSourceSecondaryNeg Gnd
8 Gnd DGSs2 Gnd nc 8 Gnd DGSs2 Gnd nc
9 DGSs1 Gnd nc Gnd 9 DGSs1 Gnd nc Gnd
10 Gnd cap2a+ Gnd cap2b+ 10 Gnd VHFACCapturePrimaryPos Gnd VHFACCaptureSecondaryPos
11 cap1a+ Gnd cap1b+ Gnd 11 VHFACCapturePrimaryPos Gnd VHFACCaptureSecondaryPos Gnd
12 Gnd DGSc2 Gnd nc 12 Gnd DGSc2 Gnd nc
13 DGSc1 Gnd nc Gnd 13 DGSc1 Gnd nc Gnd
14 Gnd cap2a- Gnd cap2b- 14 Gnd VHFACCapturePrimaryNeg Gnd VHFACCaptureSecondaryNeg
15 cap1a- Gnd cap1b- Gnd 15 VHFACCapturePrimaryNeg Gnd VHFACCaptureSecondaryNeg Gnd
16 Gnd accs1- Gnd event2_1 16 Gnd accs1- Gnd VHFACSourceEvent0
17 accs1+ Gnd event1_1 Gnd 17 accs1+ Gnd VHFACSourceEvent0 Gnd
18 Gnd nc Gnd event2_2 18 Gnd nc Gnd VHFACSourceEvent1
19 nc Gnd event1_2 Gnd 19 nc Gnd VHFACSourceEvent1 Gnd
20 Gnd accs2- Gnd event2_3 20 Gnd accs2- Gnd VHFACSourceEvent2
21 accs2+ Gnd event1_3 Gnd 21 accs2+ Gnd VHFACSourceEvent2 Gnd
22 Gnd acccap1- Gnd event2_4 22 Gnd acccap1- Gnd VHFACSourceEvent3
23 acccap1+ Gnd event1_4 Gnd 23 acccap1+ Gnd VHFACSourceEvent3 Gnd
24 Gnd acccap2- Gnd event2_5 24 Gnd acccap2- Gnd VHFACSourceEvent4
25 acccap2+ Gnd event1_5 Gnd 25 acccap2+ Gnd VHFACSourceEvent4 Gnd
26 Gnd tmu_ch1- Gnd event2_6 26 Gnd VHFACTimePrimaryNeg Gnd VHFACSourceEvent5
27 tmu_ch1+ Gnd event1_6 Gnd 27 VHFACTimePrimaryPos Gnd VHFACSourceEvent5 Gnd
28 Gnd tmu_ch2- Gnd event2_7 28 Gnd VHFACTimeSecondaryNeg Gnd VHFACSourceEvent6
29 tmu_ch2+ Gnd event1_7 Gnd 29 VHFACTimeSecondaryPos Gnd VHFACSourceEvent6 Gnd
30 Gnd nc Gnd event2_8 30 Gnd nc Gnd VHFACSourceEvent7
31 tmudgs Gnd event1_8 Gnd 31 tmudgs Gnd VHFACSourceEvent7 Gnd
32 Gnd acctmu- Gnd sb_io2 32 Gnd acctmu- Gnd VHFACSerialBusIO1
33 acctmu+ Gnd sb_io1 Gnd 33 acctmu+ Gnd VHFACSerialBusIO0 Gnd
34 Gnd nc Gnd sb_clk 34 Gnd nc Gnd VHFACSerialBusClock
35 nc Gnd sbdgs Gnd 35 nc Gnd sbdgs Gnd
36 Gnd dibtrig2 Gnd dibtrig4 36 Gnd VHFACTrigControl Gnd VHFACTrigControl
37 dibtrig1 Gnd dibtrig3 Gnd 37 VHFACTrigControl Gnd VHFACTrigControl Gnd
38 Gnd Gnd Gnd Gnd 38 Gnd Gnd Gnd Gnd

Inconsistent, in process of being changed

PRELIMINARY VERSION Chans

1/2
VHFAC Source Block Diagram
EVENTS AC/ DC SE or DIFF H AC/ DC DIFF L

Bias T Bias T
Motherboard
L

Differential
Single End
AC
SE to DIFF DC

DC
Offset

AC DC

Gain Gain

Offset
DC
Attenuators

Microwave DC Path
AUX

Low Pass Filters

Microwave AC Path

DAC

14

MUX

14 14 14 14

Event Memory Waveform Memory

2M 8M

DDS Cloc k
Generator
Trigger Waveform
Trigger
Control Control
Condition

PG
100 MHz Reference Clock

PRELIMINARY VERSION
2/2
VHFAC Source Block Diagram

EVENTS
acc src + src a+ src b+ acc src - src a- src b- Riderboard

PPMU

PPMU

PPMU

PPMU
Leveling
Detector

ALRO
ADC

EVENTS AC/ DC SE or DIFF H AC/ DC DIFF L

PRELIMINARY VERSION
 Source Memory

• Sample memory and control memory are stored in the source

memory, or SMEM.

• SMEM is 8M sample deep.

• SMEM is where segments are stored, along with sampling

frequency, shape and size information.

• Digital data in SMEM is normalized to [-1,1] range as to

maximize SNR by utilizing the full dynamic range of the VHFAC
Source DAC’s.

PRELIMINARY VERSION
1/2
VHFAC Capture Block Diagram

acc cap +
PPMU
cap a+ cap b+ cap src - cap a- cap b- Riderboard

PPMU

PPMU

PPMU
AC/ DC SE or DIFF H AC/ DC DIFF L

PRELIMINARY VERSION
2/2
VHFAC Capture Block Diagram
AC/ DC SE or DIFF H AC/ DC DIFF L
L

Motherboard

Differential
Single End
AC DC
SE t o DIFF

AUX

50

Normal Mode
Track and Peak
Hold Det ect or
10K 50
Offset

DC Baseline
DC

Low Pass Filt ers

Internal DC Of fset
Offset
DC

Calibration DAC

ADC ADC
14 bit 12 bit
80 Msps 125 Msps

14 12

Capt ure Memory

1M

Trigger Capture DDS Cloc k

Trigger
Cont rol Cont rol Generat or
Condit ion

PG
DSP 100 MHz Ref erence Clock

PRELIMINARY VERSION
 Programmable Voltage Amplifier
Voltage Scaling

• The VHFAC Capture PGA scales the analog input signal so that it fits within the
range of the A/D converters.

• Before rescaling the input signal’s amplitude, the programmable DC baseline, or

the AC coupling, can be used to remove its DC offset.

• If the peak to peak amplitude of the analog input signal is greater than
10.24Vpp, then it is necessary to attenuate the signal to avoid clipping:

CLIPPED
+ 5.12 V

+ AMPLITUDE

FU LL -S CA LE
R AN GE OF
AIN = 4.0 Vpk 0 0 V ou t
AD C
SCALE FACTOR = 2

– AMPLITUDE
– 5.12 V
CLIPPED

PRELIMINARY VERSION
 Programmable Voltage Amplifier
Voltage Scaling cont’d

• If the peak to peak amplitude of the analog input signal is less than 10.24V, then
the amplitude should be adjusted to occupy as much of the 10.24Vpp dynamic
range of the analog to digital converter as possible:

SCALE FACTOR ++5.12

11 V
V
+ AMPLI TUDE

F U LL -S CA LE
0 0 V out R AN G E O F
AIN
ADC

– AMPLITUDE

– 11
- V
5.12V

PRELIMINARY VERSION
 Programmable Voltage Amplifier
Voltage Scaling cont’d

Voltage Range Scale Factor

- 3dB + 3dB
- 3dB + 3dB
- 3dB + 3dB

.
.
.
+ 3dB

PRELIMINARY VERSION
 Capture Memory → DSP → Host CPU
VHFAC Capture XpT Support Board
Capture #1 Memory
Capture
VHFAC DSP DSP
Memory
Capture #2

VHFAC Capture
Capture #3 Memory

Capture
VHFAC Memory
Capture #4
DSP DSP Host Computer

Move Bus ~ 50MBps

TCIO1 ~6MBps
Crosspoint Memory Access ~1.4GBps

PRELIMINARY VERSION
 Session 3

• Develop a working program

– FLEX User Model
– Pinmap and Channel map
• DIB connections
– Single-ended
– Differential
– Wave Designer (define shape)
– Mixed-Signal Workshop (define coherence)
– Test Procedure Development Environment (PDE)

PRELIMINARY VERSION
 Mixed-Signal Basic Test Program
Worksheets Block Diagram

Home

7
1
Pinmap Specification Sheets 3 Mixed-Signal Pattern
6a
Calls
0 Microcode
DUT pin: name, type Global Wave 1
Specs Definition 2
Wave ASCII
Designer 3 file
2 Tool
Visual Basic Channel Map DC Specs Calls
Interpose Calls
6b Returns
Functions Tester Pin AC Specs Ret urns
channel name Pattern Tools
Mixed-Signal
Timing Editor
Mixed-Signal Debugger
8 4 5 Workshop
User defined Tool
procedures Procedures Pin Levels Time Sets
via PDE tool
Returns
Invoke TDE
9 for HardwareDisplays
Visual Basic PDE Test
Interpose Instances
Functions

Order
10 Default Programming Sequence:
Tests
Flow Worksheets
Table 1 to 6 7 8 to 10
Opcode (sequencing) Additional Worksheets P attern Worksheets
Worksheets and PDE Tools and PDE

PRELIMINARY VERSION
 Home Worksheet

PRELIMINARY VERSION
 Pinmap Worksheet

Redo for VHFAC

PRELIMINARY VERSION
 Channel Map Worksheet

Redo for VHFAC

PRELIMINARY VERSION
 Wave Definitions Worksheet

Redo for VHFAC

What’s the name for the “…” button?
PRELIMINARY VERSION
 Wave Designer Tool

Need relative vs absolute explanation of building waveforms

PRELIMINARY VERSION
 Mixed Signal Timing Worksheet

Need explanation of why we are using mixed

signal timing sheets and what are the benefits
PRELIMINARY VERSION
 Mixed Signal Workshop Tool

Specified by the user here

PRELIMINARY VERSION
 Mixed Signal Workshop Tool
Solving the Coherency Equation

PRELIMINARY VERSION
 Test Procedures Worksheet

Show changes

No spaces in Test Procedure Names

PRELIMINARY VERSION
 Session 4

• Using the Instruments

• Instantiate procedure
• VHFAC Source and Capture loopback
– Debug run from Flow Table
– Step-through using Test Debug Environment (TDE)
• Flow Chart Editor
• VHFAC Source Debug Display
• VHFAC Capture Debug Display
• Pattern Tool

PRELIMINARY VERSION
 User Delay Example

VHFAC Source and

Capture instruments have
a feature called output
delay and input delay,
respectively. Collectively
they are referred to as
user delay.

This feature allows the

user to add up to 10 us
of delay to the start of
the source or capture.
Resolution is 32 bits.
1 us of delay added
User delay simplifies
digital pattern timing,
provides greater
resolution than re-
generating waveforms,
and shortens test develop
time.

PRELIMINARY VERSION
 Programming User Delay

PRELIMINARY VERSION
 Compound Segments

PRELIMINARY VERSION
 Test Instances Worksheet

PRELIMINARY VERSION
 Test Instances Editor

PRELIMINARY VERSION
 Flow Table Worksheet

PRELIMINARY VERSION
 TDE: Flow Chart & Instruments Debug Displays

PRELIMINARY VERSION
 VHFAC Test Elements

VHFACSourcAction VHFACTimeCalculateResults
VHFACSourceConnection VHFACTimeCapture
VHFACSourceExternalTriggerCommand VHFACTimeConnection
VHFACSourceInternalConnection VHFACTimeEventCaptureSetup
VHFACSourceSetup VHFACTimeMeasurementSetup
VHFACSourceWaveformPool

VHFACSerialBusAction
VHFACCaptureAction VHFACSerialBusCalculation
VHFACCaptureConnection VHFACSerialBusConnection
VHFACCaptureExternalTriggerCommand VHFACSerialBusInternalConnection
VHFACCaptureInternalConnection VHFACSerialBusSetup
VHFACCaptureSetup
VHFACCaptureCaptureWaveformSetup
VHFACTriggerControlConnection
VHFACTriggerControlInternalConnection

PRELIMINARY VERSION
 VHFAC Source Debug Display

PRELIMINARY VERSION
 VHFAC Capture Debug Display

PRELIMINARY VERSION
 VHFAC Serial Bus Debug Display

PRELIMINARY VERSION
 VHFAC Time Debug Display

PRELIMINARY VERSION
 VHFAC Trigger Control Debug Display

PRELIMINARY VERSION
 TDE: Flow Chart & Pattern Tool

PRELIMINARY VERSION
 Mixed-Signal Basic Test Program
Worksheets Block Diagram

Home

7
1
Pinmap Specification Sheets 3 Mixed-Signal Pattern
Calls
6a
0 Microcode
DUT pin: name, type Global Wave 1
Specs Definition 2
Wave ASCII
Designer 3 file
2 Tool
Visual Basic Channel Map DC Specs Calls
Interpose Calls 6b Returns
Tester Pin AC Specs Returns
Functions Pattern Tools
channel name
Mixed-Signal
Timing Editor
Mixed-Signal Debugger
8 4 5 Workshop
User defined Tool
procedures Procedures Pin Levels Time Sets
via PDE tool
Returns
Invoke TDE
9 for Hardware Displays
Visual Basic PDE Test
Interpose Instances
Functions

Order
10 Default Programming Sequence:
Tests
Flow Worksheets
Table 1 to 6 7 8 to 10
Opcode (sequencing) Additional Worksheets P attern Worksheets
Worksheets and PDE Tools and PDE

PRELIMINARY VERSION
 Test Procedure Development Environment
PDE

VHFAC Source-Capture Loopback Test Procedure

1. Setup Source instrument

2. Load 9MHz sinewave in Interpose function

3. Connect Source relays

4. Setup Capture instrument

5. Setup DSP for capture

6. Connect Capture relays

7. Wait for instruments to settle

8. Start sourcing waveform to loopback path on DIB

9. Start capturing waveform

10. Perform DSP on captured waveform to get frequency

11. Test against limits and return result

PRELIMINARY VERSION Home

 Test Procedure Development Environment
VHFACSourceSetup

Select <New Variable>

The default variable name

PinListVHFACSource will appear in the text
box and below in the Variables Table

Setting Pins as a variable allows the test

procedure to be reused for multiple pins

Text boxes turn red if their contents are invalid.

Pins must be defined a valid test procedure

PRELIMINARY VERSION Pinmap

 Test Procedure Development Environment
VHFACSourceSetup

Select <New Variable>

The default variable name

PinListVHFACSource will appear in the
text box and below in the Variables Table.

Setting Pins as a variable allows the test

procedure to be reused for multiple pins

PRELIMINARY VERSION Pinmap

 Test Procedure Development Environment
VHFACSourceSetup

Select Amplitude Unit

For example, V Peak

The order of setting parameters does not

matter. Amplitude could be set before
Amplitude Unit. Likewise, Coupling could
be set before Low Pass Filter Bypass

PRELIMINARY VERSION
 Test Procedure Development Environment
VHFACSourceSetup

Type in numerical value for Amplitude

For example, 1.75

This parameter modifies the amplitude of the

waveform set in the Wave Definition, which will be
sourced by the VHFACSourceAction test element

aSine Wave Definition

Relative Amplitude = 1

VHFAC Source Output

Actual Amplitude = 1.75 Vpeak

Wave Definition
PRELIMINARY VERSION VHFACSourceAction
 Test Procedure Development Environment
VHFACSourceSetup

Select Bypass False when

selecting a Low Pass Filter

Suppose that the signal we want to source is

a 9MHz sine wave. Choosing a 10MHz filter
is most appropriate

PRELIMINARY VERSION
 Test Procedure Development Environment
VHFACSourceSetup

Select Output Type

For example, Single Ended

This should match the channel type defined

in the Chans worksheet for the above Pins

PRELIMINARY VERSION Chans

 Test Procedure Development Environment
VHFACSourceSetup

Select Coupling

For example, DC coupling

Note that in this example we do not use

Output Delay. It defaults to 0, so you do
not need to input any value.

PRELIMINARY VERSION
 Test Procedure Development Environment
VHFACSourceSetup

Input 50 Ohms for the Load Impedance

Doing loopback, VHFAC Capture presents a 50 Ohm

load impedance.

After entering 50, clicking anywhere will enable the

Imaginary input box. VHFAC Capture only
presents a real impedance (Zload = 50 + j0), so leave
Imaginary blank. It defaults to 0.

PRELIMINARY VERSION
 Test Procedure Development Environment
VHFACSourceSetup

Skip DC Offset

Defaults to 0

Skip Condition Bit

Skip Calibration

Defaults to Automatic level accuracy calibration.

Automatic calibration is run at first run and whenever the

driver detects a change in condition, time, or temperature that
could cause drift
Input 9MHz for the Signal Frequency to perform level
calibration

PRELIMINARY VERSION
 Test Procedure Development Environment
VHFACSourceSetup

Select CPU for Microcode Control

The host computer will send the control bit to

start the waveform loaded in the VHFAC
Source pattern memory

PRELIMINARY VERSION
 Test Procedure Development Environment
VHFACSourceSetup

Check Apply MS Timing

Input Resource ID 1

Link VHFACSourceSetup to the appropriate Context

on the Mixed Signal Timing worksheet

PRELIMINARY VERSION
 Test Procedure Development Environment
PDE

VHFAC Source-Capture Loopback Test Procedure

1. Setup Source instrument

2. Load 9MHz sinewave in Interpose function

3. Connect Source relays

4. Setup Capture instrument

5. Setup DSP for capture

6. Connect Capture relays

7. Wait for instruments to settle

8. Start sourcing waveform to loopback path on DIB

9. Start capturing waveform

10. Perform DSP on captured waveform to get frequency

11. Test against limits and return result

PRELIMINARY VERSION Home

 Test Procedure Development Environment
VHFACSourceAction

Input WaveName

Name must be in quotes and refer to WaveDefName

in the Wave Definitions worksheet

Home
Wave Definition
PRELIMINARY VERSION Back
 Pinmap Worksheet

Home
PRELIMINARY VERSION Back
 Channel Map Worksheet

The VHFAC DIB Interface Cable is VHFAC Hardware Pinout (DIB view)
A B C D A
V

installed in DIB Slot 6 1

2
Gnd
Gnd
Gnd
src2a+
Gnd
Gnd
Gnd
src2b+
1
2
Gnd
Gnd
Gnd
VHFACSource
3 src1a+ Gnd src1b+ Gnd 3 VHFACSourcePrimaryPos Gnd
4 Gnd nc Gnd nc 4 Gnd nc
The appropriate channel for ACSRC 5 nc Gnd nc Gnd 5 nc Gnd
6 Gnd src2a- Gnd src2b- 6 Gnd VHFACSource
pin in Site 0, is 6.a3 7 src1a- Gnd src1b- Gnd 7 VHFACSourcePrimaryNeg Gnd
8 Gnd DGSs2 Gnd nc 8 Gnd DGSs2
Hardware name: src1a+ 9 DGSs1 Gnd nc Gnd 9 DGSs1 Gnd
10 Gnd cap2a+ Gnd cap2b+ 10 Gnd VHFACCapture
Software channel type: 11 cap1a+ Gnd cap1b+ Gnd 11 VHFACCapturePrimaryPos Gnd

VHFACSourcePrimaryPos 12
13
Gnd
DGSc1
DGSc2
Gnd
Gnd
nc
nc
Gnd
12
13
Gnd
DGSc1
DGSc2
Gnd

Home
PRELIMINARY VERSION Back
 Wave Definitions Worksheet

Home
PRELIMINARY VERSION Back
 Session 5

• HSD and VHFAC Clocking

• Visual Basic for Test (VBT) for control
– Interpose functions – part I
• The.HDW…
• VBT for analysis
– Interpose functions – part II

PRELIMINARY VERSION
 HSD Optical Reference Clock

29
fhsd = 100MHz •2 29
29 I ≥ 1, 0 < J < 2
2 •I+J

fhsd = 53,687,091,200,000,000.00 Hz
N

(N ≥ 536,870,912)

PRELIMINARY VERSION
 VHFAC Optical Reference Clock

40
fbbac= 100MHz •2 40
40 I ≥ 1, 0 < J < 2
2 •I+J

fbbac = 109,951,162,777,600,000,000.00 Hz
N

(N ≥ 1,099,511,627,776)

Update!!

PRELIMINARY VERSION
 Visual Basic for Test - VBT

• Statement Order Matters!

PRELIMINARY VERSION
 VHFAC Microcodes
Type Source Capture Time
Instrument Nop Nop Nop
Start Trig Start
StartE Resume Stamp
Start1 Measure_Peak Enable_Trig
StartE1 Enable_Gate_On
Stop Enable_Gate_Off
StopE
State PSet PSet PSet
Enable_Alarm Enable_Alarm Enable_Alarm
Disable_Alarm Disable_Alarm Disable_Alarm
Enable_Inst_Cond Enable_Inst_Cond Enable_Inst_Cond
Disable_Inst_Cond Disable_Inst_Cond Disable_Inst_Cond
Reset_Peak Start_Alt
Resync Resync Sync

Consecutive VHFAC Microcodes need to

be at least ???ns apart from each other.

PRELIMINARY VERSION
 VHFAC Source Microcodes
Type Microcode Parameter Description
Source Nop No operation
Start <wavename> Immediately (on the next available logical analog
clock) start sourcing the named waveform in
SMEM and repeat it continuously until a Stop
microcode is executed or the instrument is reset.
StartE <wavename> At the end of the currently sourced waveform,
source the named waveform in SMEM and
repeat it continuously until a Stop microcode is
executed or the instrument is reset.
Start1 <wavename> Immediately (on the next available logical analog
clock) start sourcing the named waveform in
SMEM and source it exactly once.
StartE1 <wavename> At the end of the currently sourced waveform,
source the named waveform in SMEM and
source it exactly once.
Stop Stop sourcing the currently sourced waveform
immediately.
StopE Stop sourcing the currently sourced waveform at
the end of the waveform.
State PSet <PSet name> Cause the named group of PSetable parameters
to be applied to the VHFAC Capture Instrument.
Enable_Alarm Enable instrument alarms to be latched.
Disable_Alarm Disable alarms from affecting alarm latch.
Latch is cleared by software at pattern start.
Enable_Inst_Cond Enable condition.
Disable_Inst_Cond Disable condition.
Resync Initiate a sequence within the instrument that
synchronizes the instrument clock.
PRELIMINARY VERSION
 VHFAC Source PSETable Parameters

Parameter Name Description

Amplitude Switch the attenuator and amplifier according to the programmed range.
AmplitudeUnit
DCOffsetForAC
DCOffsetForDC
Frequency
LowPass

PRELIMINARY VERSION
 VHFAC Capture Microcodes

Type Microcode Parameter Description

Capture Nop No operation
Trig <wavename> Trigger data collection and store the data set
with its associated name.
Resume When in BlockResume mode this command will
continue a capture that has been suspended.
Measure_Peak Capture the peak detector output and store into
Peak Capture Memory
State PSet <PSet name> Cause the named group of psetable parameters
to be applied to the VHFAC Capture Instrument.
Enable_Alarm Enable instrument alarms to be latched.
Disable_Alarm Disable alarms from affecting alarm latch.
Latch is cleared by software at pattern start.
Enable_Inst_Cond Opens the window that allows the instrument
condition signal onto the pattern domain COND
resource.
Disable_Inst_Cond Closes the window to prevent the instrument
condition signal from driving the pattern domain
COND resource.
Reset_Peak Reset the peak detector.
Resync Initiate a sequence within the instrument that
synchronizes the instrument clock.

PRELIMINARY VERSION
 VHFAC Capture PSETable Parameters

Parameter Name Description

CommonMode Change the common mode dc when differential input mode : -4.0V to 4.0V
DCOffset Change the DC baseline voltage: -12.288 to 12.282V
LowPass Select the low pass filter:
0.5MHz, 2MHz, 6.1MHz, 10MHz, 20MHz, 40MHz, 62.5MHz or Bypass
PeakDetect
SelectChannel Select channel A or channel B input.
VoltageRange Switch the attenuator and amplifier according to the programmed range.

PRELIMINARY VERSION
 VHFAC Time Microcodes
Type Microcode Parameter Description
Time Nop No operation
Start <wavename> Start is used to begin the measurement
if the Start mode is waiting for a
microcode. The wave name is tagged
to the measurement data. 16 unique
names can be provided.
Stamp Outside of pattern Stamper A and B can
be setup to listen to a pattern event.
When Stamp is used, the appropriate
stamper records the current time off the
counter. This can be used to generate
a reference time. If no stamper is
setup to listen for a pattern event, then
no time is recorded. Under trigger
setup, a Stamp microcode does
nothing.
Enable_Trig This provides an Enable Trigger signal
to the Enable input of the dual stamper,
if the Enable input is set to listen for a
microcode.
Enable_Gate_On This will turn on the Enable Gate
window. While this Gate is open the
time stamper will be enabled
Enable_Gate_Off This will turn off the Enable Gate
window.
State PSet <PSet name> Cause the named group of PSetable
parameters to be applied to the
instrument.
Enable_Alarm Open Alarm Window for VHFAC TMU
Alarms
Disable_Alarm Close Alarm Window for VHFAC TMU
Alarms
Enable_Inst_Cond Enables VHFAC TMU to drive the
PRELIMINARY VERSION condition wire
 VHFAC Time PSETable Parameters
Parameter Name Description
CH1 Voltage Range / Selects the Voltage Range and Hysteresis setting for the CH1
Hysteresis side
CH1 Voltage Threshold 14 bit threshold value for the CH1-side of the Front End1
Start Mode Select Select the Start input, start slope select, and Time Range for
the Dual Time Stamper Unit
A Enable Selects the Enable input and mode for Stamper A.
B Enable Selects the Enable input and mode for Stamper B.
Interleave Selects the interleave mode for the dual time stampers
A Event Input Selects the input and the input slope to be stamped using
Stamper A
B Event Input Selects the input and the input slope to be stamped using
Stamper B
A Hold-off Counter Specifies the hold-off count before enabling Stamper A.
B Hold-off Counter Specifies the hold-off count before enabling Stamper B.
CH2 Voltage Range / Selects the Voltage Range and Hysteresis setting for the CH2
Hysteresis side
CH2 Voltage Threshold 14 bit threshold value for the CH2-side of the Front End2
A Sample Counter Specify number of samples on stamper A to make during this
measurement.
B Sample Counter Specify number of samples on stamper B to make during this
measurement.
CH1 V_TERM 14 bit termination value for the CH1-side of the Front End1
CH2 V_TERM 14 bit termination value for the CH2-side of the Front End2

PRELIMINARY VERSION
 Distributed Instrument Control
Local control of Architecture Enables:
instrument setup
uCodes from Pat Gen - Control of instruments
Tester
Computer
Sync Bus synchronized with pattern
TCIO
Psets PSET - Independent multisite DUT
Pat MEM
Gen synchronization, can match
uCode PSET
Local Pat
Psets loop per site
MEM
Pattern GenCLK
CLK uCode PSET
Generator Pat
Psets
MEM
- Multiple time domain
GenCLK
CLK uCode PSET
Instrument Channels capability
Psets
Pat MEM
GenCLK Instrument Channels - Concurrent test of IP cores
REF CLK CLK uCode

Instrument Channels
CLK
CLK
Clock Domain C
Instrument Channels
Clock Domain B
Local Digital VHFAC
Synthesized Clock Domain A
Clock

PRELIMINARY VERSION
 Appendix

• Acronyms
• VHFAC & BBAC Comparison

PRELIMINARY VERSION
 Acronyms

PRELIMINARY VERSION
 VHFAC vs. BBAC Pinout
VHFAC Hardware Pinout (DIB view) BBAC Hardware Pinout (DIB view)
A B C D A B C D
1 Gnd Gnd Gnd Gnd 1
2 Gnd src2a+ Gnd src2b+ 2 src2+
3 src1a+ Gnd src1b+ Gnd 3 src1+ src2sh
4 Gnd nc Gnd nc 4 src1sh src2Ref
5 nc Gnd nc Gnd 5 src1Ref src2Refsh
6 Gnd src2a- Gnd src2b- 6 src1Refsh src2-
7 src1a- Gnd src1b- Gnd 7 src1-
8 Gnd DGSs2 Gnd nc 8 DGSs2
9 DGSs1 Gnd nc Gnd 9 DGSs1 DGSs2sh
10 Gnd cap2a+ Gnd cap2b+ 10 DGSs1sh cap2+
11 cap1a+ Gnd cap1b+ Gnd 11 cap1+ cap2sh
12 Gnd DGSc2 Gnd nc 12 cap1sh DGSc2
13 DGSc1 Gnd nc Gnd 13 DGSc1 DGSc2sh
14 Gnd cap2a- Gnd cap2b- 14 DGSc1sh cap2-
15 cap1a- Gnd cap1b- Gnd 15 cap1-
16 Gnd accs1- Gnd event2_1 16 accs1-
17 accs1+ Gnd event1_1 Gnd 17 accs1+ accs1-sh
18 Gnd nc Gnd event2_2 18 accs1+sh accs1Ref
19 nc Gnd event1_2 Gnd 19 accs2Ref accs1Refsh
20 Gnd accs2- Gnd event2_3 20 accs2Refsh accs2-
21 accs2+ Gnd event1_3 Gnd 21 accs2+ accs2-sh
22 Gnd acccap1- Gnd event2_4 22 accs2+sh acccap1-
23 acccap1+ Gnd event1_4 Gnd 23 acccap1+ acccap1-sh
24 Gnd acccap2- Gnd event2_5 24 acccap1+sh acccap2-
25 acccap2+ Gnd event1_5 Gnd 25 acccap2+ acccap2-sh
26 Gnd tmu_ch1- Gnd event2_6 26 acccap2+sh
27 tmu_ch1+ Gnd event1_6 Gnd 27
28 Gnd tmu_ch2- Gnd event2_7 28
29 tmu_ch2+ Gnd event1_7 Gnd 29
30 Gnd nc Gnd event2_8 30
31 tmudgs Gnd event1_8 Gnd 31
32 Gnd acctmu- Gnd sb_io2 32
33 acctmu+ Gnd sb_io1 Gnd 33
34 Gnd nc Gnd sb_clk 34
35 nc Gnd sbdgs Gnd 35
36 Gnd dibtrig2 Gnd dibtrig4 36 DIBtrigs2 DIBtrigc2
37 dibtrig1 Gnd dibtrig3 Gnd 37 DIBtrigs1 DIBtrigs2sh DIBtrigc1 DIBtrigc2sh
38 Gnd Gnd Gnd Gnd 38 DIBtrigs1sh DIBtrigc1sh

PRELIMINARY VERSION
 Converter Testing
Option
Preliminary

PRELIMINARY VERSION Rev0343

- confidential -
A/D Converter Test with CT-30 on FLEX

Analog Source

PRELIMINARY VERSION
CT-30 as an A/D & D/A Converter Test Option
• 30 High Accuracy DC • Pattern Control
Source & Captures • 15 Bit + Sign Resolution
• +/- 0.5, 1, 2, 5, 10, 30v • 2.5K X 16 Source Memory
Ranges • 512 x 16 Capture Memory

PRELIMINARY VERSION
8 bit ADC Test Requirements

Typical 8 Bit ADC Typical 8 Bit ADC

Dut Vref = 5v, 8 Hits per Code Dut Vref = 3v, 8 Hits per Code
Requires: Requires:
Dut LSB = 19.53mv Dut LSB = 11.71mv
Offset = 1 LSB Offset = 1 LSB
Gain = 1 LSB Gain = 1 LSB
INL = 1 LSB INL = 1 LSB
DNL = 0.5 LSB DNL = 0.5 LSB

2048 step ramp 2048 step ramp

Test Step Resolution 4.88mv Test Step Resolution 2.92mv
Source INL 1 in 11 bits Source INL 1 in 11 bits
Source DNL 1 in 11 bits Source DNL 1 in 11 bits
Absolute Accuracy 1.95mv Absolute Accuracy 1.17mv

PRELIMINARY VERSION
10 bit ADC Test Requirements

Typical 10 Bit ADC Typical 10 Bit ADC

Dut Vref = 5v, 8 Hits per Code Dut Vref = 3v, 8 Hits per Code
Requires: Requires:
Dut LSB = 4.88mv Dut LSB = 2.92mv
Offset = 1 LSB Offset = 0.5 LSB
Gain = 1 LSB Gain = 1 LSB
INL = 0.5 LSB INL = 0.5 LSB
DNL = 0.5 LSB DNL = 0.5 LSB

8196 step ramp 8192 step ramp

Test Step Resolution 610uv Test Step Resolution 366uv
Source INL 1 in 13 bits Source INL 1 in 13 bits
Source DNL 1 in 13 bits Source DNL 1 in 13 bits
Absolute Accuracy 488uv Absolute Accuracy 292uv

PRELIMINARY VERSION
12 bit ADC Test Requirements

Typical 12 Bit ADC Typical 12 Bit ADC

Dut Vref = 3v, 8 Hits per Code Dut Vref = 1v, 8 Hits per Code
Requires: Requires:
Dut LSB = 732uv Dut LSB = 244uv
Offset = 2 LSB Offset = 4 LSB
Gain = 4 LSB Gain = 8 LSB
INL = 1 LSB INL = 1 LSB
DNL = 1 LSB DNL = 1 LSB

32768 step ramp 32768 step ramp

Test Step Resolution 91uv Test Step Resolution 30uv
Source INL 1 in 15 bits Source INL 1 in 15 bits
Source DNL 1 in 15 bits Source DNL 1 in 15 bits
Absolute Accuracy 73uv Absolute Accuracy 3uv

PRELIMINARY VERSION
CT-30 Relevant Specs
• INL (2.0 LSB in 16) • Resolution is 15bit + Sign
0.5v range 32uv
5.0v range 313uv • Source Gain & Offset
10v range 625uv 0.5v 0.05% + 0.9mv
1.0v 0.05% + 1.0mv
• DNL (1.5 LSB in 16) 2.0v 0.05% + 1.2mv
0.5v range 47uv 5.0v 0.05% + 1.0mv
5.0v range 469uv 10.0v 0.05% + 1.5mv
10v range 968uv (3.0 lsb)
• Capture Gain & Offset
• Stability 0.5v 0.05% + 0.9mv
110uV per degree C typ 1.0v 0.05% + 1.0mv
2.0v 0.05% + 1.2mv
• Noise 5.0v 0.05% + 1.4mv
150uV < 200Khz, Pk-Pk typ 10.0v 0.05% + 2.5mv
PRELIMINARY VERSION
FLEX CT-30 vs Integra J750 CTO Spec Comparison
CT-30 CT-30
CTO single ramp Segmented Ramp
Voltage Forcing
Nominal Output Range 1 -10 mV to +3v +/- 5v +/- 0.5v
Nominal Output Range 2 -20 mV to +6 V +/- 10v
Gain & Offset Range 1 +/-(30 ppm + 30 uV) 0.05% + 1.0mv 0.05% + 0.9mv
Gain & Offset Range 2 +/-(60 ppm + 60 uV) 0.05% + 1.5mv
Source Linearity 2 LSB in 16 2 LSB in 16 2 LSB in 16
Nominal Resolution Range 1 50 uV 150 uV 15 uV
Nominal Resolution Range 2 100 uV 300 uV

Voltage Reference Ref A CT-30 Channel

Nominal Output Range 0 to +6 V +/- 10 Volts
Nominal Resolution 1.5mV (12 bits) 300uV (15 bits)
Output Current Capability 10 mA 100mA
Accuracy +/- (1% +3mv) 0.5% + 1.5mV
Settling Time 50 mS to specified acc
Noise 30 uV RMS < 150 uV Pk-Pk
Stability (2 C and 30 Minutes) +/- 90 uV over system range

PRELIMINARY VERSION
FLEX CT-30 vs Integra J750 CTO Configuration Comparison

• 20 channels per board • (8) 4 channel groups per

– 1 CT-20 chan as Vref board
– 1 CT-30 chan as Source – 1 CTO chan group for Vref
– 1 CT-30 chan as Capture A / Vref B / Src / Cap

• Any CT-30 Channel can be used …..

– As a Source
– As a Capture
– As a Precision Reference
• Increases DIB layout flexibility
• Reduces the number of board types

PRELIMINARY VERSION
2 X 8Bit Flash ADC Test using the CT-30
VIH
Tester
Computer
Memory
DAC ADC Functional
2.5kx16 8Bit
VOH VIL

ADC
1. Source 8Bit

Pattern 2. Source HRAM

Generator
CT-30 DUT 3k
VOL

Single Burst

Pin Electronic
40.5us/Sample

TCIO 100MBit/s
Segment Burst Time Computer
1/8 LSB 2048Samples*40.5us = 82.94ms

Unload 3K HRAM and Transfer 2048 samples =

8Bit * 2ADC = 8ms 256 codes @ 8 Hits per code
82.94ms 7ms

2048 Samples ==> 82.94ms + 8ms = 90.94ms

PRELIMINARY VERSION
2 X 10Bit Flash ADC Test with Source Memory Reload
VIH
Tester
Computer
Memory
DAC ADC Functional
2.5kx16 10Bit
VOH VIL

ADC
1. Source 10Bit

Pattern 2. Source HRAM

Generator
CT-30 DUT 3k
VOL

1.Burst 2.Burst 3.Burst 4.Burst

Pin Electronic
40.5us/Sample
TCIO 100MBit/s
Computer
1/8 LSB Segment Burst Time
8192 samples =
2048*40.5us = 82.94ms
1024 codes @ 8 Hits per code
Unload 3K HRAM and Transfer = 8ms
Src Memory Reload Time = 4ms
82.94 ms 7ms Pattern restarted 3 times
8192 Samples = (82.94ms ) * 4 + (12ms * 3) = 367.76ms
PRELIMINARY VERSION
Segmented Ramp Technique for 12 bit ADC Testing
• First channel is the “ramp”
• Second channel is the “pedestal”
• Connected together using CT-30 Dib Access, summed via the
dib access and mod in capability, and sent to DUT

Memory Memory
2.5kx16
DAC 2.5kx16 DAC

CH1 - Ramp Ch2 - Pedestal

Set to most accurate & Drives DUT, kelvin Pedestal Points

sensitive range connection to DUT

Ramp is 15 bits, from –0.5v to +0.5v. This is an LSB of 1v / 2^15, or 30uV.

Using three pedestal steps, the first at 0.5v, then 1.5v, and finally at 2.5v, we
build a 3v ramp with 30uV resolution. Working backwards, and solving for
effective bits (x), we have 3v/2^x = 30uv , which gives about 16.5 bits, for a
gain of 1.5 bits over the base instrument capability of 15 bits
PRELIMINARY VERSION
DUT connections for the Segmented Ramp Technique

CT-30 DIB
Memory
2.5kx16
DAC
To DUT
Pedestal

CT-30 Mod In
Summing Junction Dib Access Input

Memory
2.5kx16
DAC
Standard User
Output Supplied
ramp Pins
Loopback

PRELIMINARY VERSION
1 X 12Bit ADC test with Segmented Ramp using the CT-30
VIH
Tester
Computer
Memory
DAC ADC Functional
2.5kx16 12Bit
VOH VIL

Pedestal
Pattern Ramp HRAM
Generator
CT-30 DUT 3k
VOL

1.Burst 2.Burst N-1.Burst 16.Burst

Pin Electronic
40.5us/Sample
TCIO 100MBit/s
Computer
1/8 LSB
Segment Burst Time 32768 samples =
2048*40.5us = 82.94 ms
4096 codes @ 8 Hits per code
Unload 3K HRAM and Transfer = 8ms

82.94ms 7ms
Pedestal Step = 1ms Segments sourced 16 times,
But not reloaded!
32768 Samples = (82.94ms * 16) + (9ms * 15) = 1462ms

PRELIMINARY VERSION
1 X 12Bit ADC test with Segmented Ramp & DSSC
VIH
Tester
Computer
Memory
DAC ADC Functional
2.5kx16 12Bit
VOH VIL

Pedestal
Pattern Ramp HRAM
Generator
CT-30 DUT 3k
VOL

1.Burst 2.Burst N-1.Burst 16.Burst

Pin Electronic
10us/Sample

Digital Source and

Capture Memory
1/8 LSB
Segment Burst Time 8Mx16
2048*40.5us = 82.94 ms
DSSC
Unload DSSC and Transfer = 1ms
Pedestal Step = 1ms TCIO 100MBit/s
82.94ms 1us
Computer
32768 Samples = (82.94ms * 16) + (1ms * 15) + 1ms = 1343ms
PRELIMINARY VERSION
Absolute Accuracy Issue for Gain & Offset Test

• CT-30 absolute accuracy is insufficient in some

cases.

• Two Possible solutions:

– Augment the standard Ramp test method with direct testing
using the Precision Meter Option, or PMO, connected using
DIB Access.

– Use the CT-30’s onboard DIFF Voltmeter instead of the

PMO

PRELIMINARY VERSION
Gain & Offset test with PMO

• Serially enable PMO to each CT-30 Src & DUT Input

• Two possible correction methods:

– Measure Gain/Offset Directly with PMO

• Uses CT-30 Source to force 0v, Max V
• Measure actual force value with PMO, compare to DUT
converted value.

– Calibrate offset
• Measure CT-30 Source error with PMO
• Apply to measured values

PRELIMINARY VERSION
DUT connections for the PMO

CT-30 DIB
Memory
2.5kx16
DAC
To DUT
Pedestal
Dib Access
Input

TestHead
GPIO
User
Supplied
Loopback

MainFrame
PMO

PRELIMINARY VERSION
Gain & Offset test with DIFF VM

• Connect DIFF VM to CT-30 Source, DUT Input

• Two correction possible methods:

– Measure Gain/Offset Directly with DIFF VM

• Uses CT-30 Source to force 0v, Max V
• Measure actual force value with DIFF VM, compare to DUT
converted value.

– Calibrate offset
• Measure CT-30 Source error with DIFF VM
• Apply to measured values

PRELIMINARY VERSION
DUT connections for the DIFF VM

CT-30 DIB
Memory
2.5kx16
DAC

To DUT 1
Pedestal

DIFF DGS
VM

Memory
2.5kx16
DAC
Standard
Output
To DUT 2
ramp Pins

PRELIMINARY VERSION
CT-30 - ADC Test Template

Required
Template
Arguments

Optional
Template
Arguments

PRELIMINARY VERSION
CT-30 - ADC Test Template Selectable Parameters

• Basic Parameters • Ramp Test Limits

– Number of Bits – Test Parameter Selection
– MSB / LSB (INL/DNL/Gain/Offset…)
– Vref Hi / Vref Lo setting – Limit Setting
– Best Fit Adjusted
• Ramp Test Conditions – End Point Adjusted
– End V / Start V – None
– Hits per Code
– LSBs beyond endpoints • User Defined Analysis
– Input source array
– Output captured array
– Output histogram data

PRELIMINARY VERSION
Standard Ramp Template Tests
• Diff-Err:
– Differential non-linearity error (DNL). This is the difference of the code width
from 1 LSB.
• Int-Err:
– Integral (cumulative) non-linearity error, (INL). This is the difference between the
normalized transition point and the ideal transition point.
• Off-Err:
– Offset error. This is the difference between the first transition point and the ideal
first transition point.
• Absolute error:
– This is the difference between the observed transition point and the ideal
transition point.
• GainErr:
– A gain error, as an allowable percentage of ideal gain. The GainErr drop-down
list contains the integers from 0 to 10.

• Missing Codes (ADC), Missing Out (DAC)

– How many of the expected output items (digital codes for ADC, analog voltages
for DAC) were not generated by the steps in input. You can specify the
maximum number of allowable missing items

PRELIMINARY VERSION
 CT-30 Debug Tools and Displays
Able to control all relay, gate
functions, voltage settings
and modes.

Can view source & capture

Can strobe
waveforms interactively
while forcing
interactively

PRELIMINARY VERSION
CT-30 Source / Capture Waveform Display

PRELIMINARY VERSION
CT-30 Pattern Language Example

Digital Analog MicroCode

MicroCode
Enable

Initial
Value

Step
Read
Source
Converted
Value

PRELIMINARY VERSION
CT-30 Pattern Tool Debug

• Able to set / change Analog Microcode “on the fly”

using standard tools
• Able to view Analog waveform with Digital in same
display

PRELIMINARY VERSION
J750 Software Compatibility

• Template source code is part of the IG-XL software

distribution
– CT-30 templates use same arguments as J750-CTO
templates
– Converts directly from J750 IGXL into Integra FLEX IGXL.

• Patterns are similar, but must be re-written

– Maintains 11/12 HRAM bug
– CTO – send_I, send_d, store, nop
– CT-30 – gate, next_mem, capture, strobe

PRELIMINARY VERSION
J750 8 Bit ADC Test Time Comparison

• At 8 Hits per code shows roughly equivalent.

– Flex Prebody time higher due to gating function of CT-30
– Flex Body time faster due to faster host computer?

CTO
Flow Step Line Total PreBody Body PostBody
AtoD_8bits 7 0.2127352 0.014536 0.194492 0.003708

CT-30
Flow Step Line Total Prebody Body Postbody
AtoD_8bits 8 0.1818428 0.033372 0.147462 0.001009

PRELIMINARY VERSION
J750 10 bit ADC Test Time Comparison

• At 8 Hits per code shows 35% increase

CTO
Flow Step Line Total PreBody Body PostBody
AtoD_10bits 8 0.471436 0.002068 0.468331 0.001037

CT-30
Flow Step Line Total Prebody Body Postbody
AtoD_10bits 0.636488 0.005161 0.630332 0.000995

PRELIMINARY VERSION
J750 8 Bit Test Result Correlation
• Calibrated CT-30 performance (v3.60.11)

CTO
Misscode Gain DNL INL Offerr ABS
0 -0.07129 0.125 0.75 0.875 0.75

CT-30
Misscode Gain DNL INL Offerr ABS
0 -0.087 0.125 0.625 0.875 0.625

PRELIMINARY VERSION
J750 10 Bit Test Result Correlation

• Calibrated CT-30 performance (v3.60.11)

CTO
Misscode Gain DNL INL Offerr ABS
0 -0.0481 0.05 0.55 1.375 0.55

DC30
Misscode Gain DNL INL Offerr ABS
1 -0.0721 -0.875 -1.4625 1.375 1.575

PRELIMINARY VERSION
Differences when using the CT-30 vs the CTO to test ADC

• The CTO Ref A is less noisy than the CT-30 Voltage

Source
– Passive or Active filtering required for similar performance

• Absolute Accuracy of CT-30 is less than the CTO,

and may not suffice in some 10 Bit cases
– Due to large DC offset error on CT-30.
– Can use PMO to do a user dib cal for offset correction.

• Higher noise bandwidth of CT-30 requires a 0.1uf cap

on source.

PRELIMINARY VERSION
Integra FLEX New Capabilities
• Multi-Purpose Instrument
– Volt meter, DUT Supply, Converter Test, VLFAC

• New Capabilities
– Positive and Negative Source / Capture Covers a wider
range of converters
– Pattern Control over levels via PSet reprogramability
– 12 bit Converters Test via DIB Access using Segmented
Ramp technique
– Wave form filtering 530hz / 4.6khz / 44kz

• New Instruments
– Differential Voltmeter
– Time Measurement Unit for analog Rise / Fall Time, Slew
Rate measurements
PRELIMINARY VERSION
 Backup Slides

PRELIMINARY VERSION
Converter Resolution vs Array & Segment Size
• Shows number of memory reloads and segments based on converter
resolution, reference voltage, and hits per code

PRELIMINARY VERSION
Ramp Analysis Equations

The equations for the analysis tests are as follows. Note

that these equations, as specified here, are for the
CT-30 ADC Test template. For the CT-30 DAC Test
template, the digital value required by the DAC input
is converted to an analog equivalent for use during
processing

PRELIMINARY VERSION
Diff-Err - Differential non-linearity error - DNL

y
MAX[ABS(ViStart-ViEnd) - Bitweight]
i=x

where
x = location in the normalized results array where a voltage ramp
begins
y = location in the normalized results array where a voltage ramp
ends
ViStart = the input voltage when the observed normalized output
changes
ViEnd = the input voltage when the normalized output changed
previously
Bitweight = volts per LSB step
PRELIMINARY VERSION
Int-Err - Integral non-linearity error - INL

y
MAX[(ViActual - ViIdeal)]
i=x

where
x = location in the normalized results array where a voltage ramp
begins
y = location in the normalized results array where a voltage ramp
ends
ViActual = the input voltage when the observed normalized output
changes
ViIdeal = the input voltage that would ideally cause the observed
output

PRELIMINARY VERSION
Off-Err - Offset error

VActual - VIdeal

where

VActual = the output voltage for the first observed output change
during or after the point at which the input voltage is
increased from VIdeal
VIdeal = the input voltage that would cause the first output
transition above VrefL

PRELIMINARY VERSION
Absolute - Absolute error

y
MAX[(ViActual - ViIdeal)]
i=x

where:

x = location in the actual results array where a voltage ramp begins

y = location in the actual results array where a voltage ramp ends

ViActual = input voltage when the observed actual output changes

ViIdeal = input voltage that would ideally cause observed output

PRELIMINARY VERSION
GainErr - Gain error

(M - 1)*100

where

M is the slope of a line.

If "Normalization Method" is "End-Points," the line is through the

endpoints of the returned voltage ramp relative the applied
voltage values.

If "Normalization Method" is "Best Fit Line," the line is through all

the points of the returned voltage ramp relative the applied
voltage values.

PRELIMINARY VERSION
Missing Codes/Out

y
[1, if MissCodeArray(i)=0]
i=x

where

MissCodeArray is a histogram array of the results returned

x = 0 if "to Ref or Start/End" is "to references"

y = 2**bits-1 if "to Ref or Start/End" is "to references"

x = the starting bitcode if "to Ref or Start/End" is "to endpoints"

y = the ending bitcode if "to Ref or Start/End" is "to endpoints"
PRELIMINARY VERSION
Demo Device: AD7880 – 8/10/12 Bit ADC

CT-30 as
DPS

CT-30

CT-30

CT-30 as
Ref

PRELIMINARY VERSION
Characterization

Rev0343
- confidential -
 Outline

• Overview
• Characterization Mode
• Characterization Setup
• Running Characterization
• Lab

Module 30 - 2

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 Overview

What is Device Characterization?

• Experimenting with the DUT by investigating its behavior

under a variety of input conditions.

• Determining the extremes at which the device will operate

• Exploring the pass/fail regions caused by certain

combinations of input parameters

Module 30 - 3

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 Overview

IG-XL Characterization Features

• Can be performed from the Flow Table during the regular
testing process, or interactively during the debugging process
• Adjustment can be made to
- Levels parameters, such as VDriveHi, Vps
- Timing parameters in the Edge and Time Sets sheets.
- AC or DC spec values.
IG-XL will determine the full effect of changing a spec value,
modifying any dependent hardware values as needed.
• The results can be viewed graphically, or sent to a file or a
DataTool worksheet.

Module 30 - 4

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 Overview

General Setups
• Specifies the parameters to be varied, and range over which to
vary them

• The setups are stored in the Characterization Sheet.

• Setups can be called from the Flow Table, as part of a test

program, or from a Characterization Editor (CE) for interactive
debugging

• The CE can also be used to create or modify setups on the fly.

Module 30 - 5

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 Overview

Characterization and Test Instances

Characterization
Setup

Specifies
parameters Varying hardware
to be varied parameter
according to setup

Characterization results DataTool Hardware

to be graphed or binned or
propagated to remain in tests Characterization Setup

Return test results as

Pass/Fail/Error or
Measure values
Test instance
to be characterized
Module 30 - 6

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 Outline

• Overview
• Characterization Mode
• Characterization Setup
• Running Characterization
• Lab

Module 30 - 7

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Characterization Modes

• Shmoo – 1D, 2D, or 3D

• Margin
• Adjust
• Measure

MODE

Shmoo Margin

Adjust

Measure

Module 30 - 8

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Characterization Modes

SHMOO – 1D, 2D, or 3D

Vary one, two, or three primary

parameters or specs (and any number
of tracking parameters or specs for
each axis) over a range. For each point
defined by the axes, record
Pass/Fail/Error for the point. The results
can be shown graphically or sent to a
file or data worksheet.

Module 30 - 9

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 Characterization Modes

Margin
• Vary one primary parameter or spec over a
range while recording Pass/Fail/Error information.
• Cannot be combined with other modes

Margin vs. 1D-Shmoo

• Margin does not allow tracking parameter.

• Margin result can only be stored in a file or

worksheet - no graphical display.

Module 30 - 10

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 Characterization Modes

Adjust

• Vary a hardware parameter or spec over a range

until the transition point between Pass and Fail is
located, and optionally set a spec to the final result.

• The spec can be propagated and "overlaid" onto

subsequent test instances, so they can use the
new adjusted value.

• An Adjust is sometimes known as an edge find

Module 30 - 11

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 Characterization Modes

Adjust aka. Edge Find

• Primarily used to locate an output edge of the DUT and then to
adjust the tester setup based on the actual location of that edge.
• This is done in cases where the DUT timing is referenced to an
output event that cannot be determined before runtime.

Input Data t
Input DUT Output
Output Data t

Tadj

• Once Tadj is measured, an AC spec can be used to propagate its

value to timing sheets, causing the recalculation of edge and window
placements for the device.
Module 30 - 12

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 Characterization Modes

Measure
Measure one or more parameters, finding the
pass/fail transition point, and return the measured
value.

Measure vs. Adjust

• Measure restores the tester’s state and does not set a
spec with the result.
• Adjust leaves the tester in the "just passing" state if no
spec is specified to receive the final result. If a spec is
specified, the result is applied to the spec and the tester
state is restored.

Module 30 - 13

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 Characterization Modes

Comparison of modes

Feature Shmoo Margin Adjust Measure

Support Tracking
Yes No No No
Parameter
Locate pass/fail
No No Yes Yes
transition?
Each Each At the At the
Datalogs when?
point Point end end

Restores state? N/A N/A Yes/No Yes

Can overlay tester

N/A N/A Yes No
setup?

Support “backoff”? N/A N/A Yes No

Module 30 - 14

- confidential -
 Outline

• Overview
• Characterization Mode
• Characterization Setup
• Running Characterization
• Lab

Module 30 - 15

- confidential -
 Characterization Setup

Characterization Sheet

1 2

To insert a characterization sheet

1. Go to Insert, and select
Worksheet. The Worksheet
window will pop up
2. Select Characterization from the
Sheet Type drop-down menu list.

Module 30 - 16

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 Characterization Setup

Characterization Sheet

Click to invoke the Editor

In the characterization sheet

1. Specify Setup Name and Mode of the characterization to be set up
2. Click on the ellipsis button to invoke the Characterization Editor
Module 30 - 17

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 Characterization Setup

Characterization Editor

General
Field

Field specific
to selected
characterization
mode

Output
field
Module 30 - 18

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 Characterization Setup
Characterization Editor - General Field

"Setup" drop-down list

• Use to select the setup to edit or run.
• To create a new setup, select (New) at the top of the list.
• If invoked the Editor from the Characterization sheet, the name of the current
setup will be displayed. The control will be disabled

"Mode" control
• Two radio buttons: one for Margin and one for all Modes other than Margin.
• A setup that contains a Margin row cannot contain rows of any other mode.
• In non-Margin mode, you can have any combination of Shmoo, Adjust, and
Measure: check the box for one or more of these modes.

Module 30 - 19

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 Characterization Setup

Characterization Editor - Output Field

Shmoo Data Display (For Shmoos only)

-> Bring up the Shmoo Data Display window

Worksheet
-> Specify the worksheet to which the characterization data is
to be written.
File
-> Specify the full name of the file to which the characterization
data is to be written.
-> Use the "Browse" button to browse to a folder or file.

Module 30 - 20

- confidential -
 Characterization Setup
Shmoo Setup

• Appear, when the Shmoo box under Mode is checked

• Three tabs for X-axis, Y-axis, and Z-axis
Module 30 - 21

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 Characterization Setup

Shmoo Setup
Type -> Select the type parameter to
vary:
Spec Spec Parameter defined on
an AC or DC or Global spec
Edge Timing Parameter defined on
a Time Set or Edge Set sheet
Level DC Parameter defined on a
Pin Levels sheet
Period Period value defined on a
Time Set sheet
Name ->Select or enter the name of
the parameter (level, edge, or
spec) to vary.
A drop-down list may be
available, depending on the
type selected.

Module 30 - 22

- confidential -
 Characterization Setup

Shmoo Setup
Algorithm -> Select the algorithm to
be used
Linear - Sweep from "From" to "To" in
"Step Size" steps
List - Use a specific set of values
(specified as Point List)
If Algorithm is List, enter a comma-
separated list of points to be used in
the Point List field

From, To, Steps, Step Size

If Algorithm is Linear, enter the values
to be used to define the steps in the
sweep.
From and To fields are required.
Either Steps or Step Size is required:
either can be calculated from the other.

Module 30 - 23

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 Characterization Setup

Shmoo Setup – “Apply To” Field

Pins/Groups: Enter a list of the pins whose parameter is to be varied

(blank = all pins). Enabled if Type = Edge or Level.

Time Sets: Enter a list of the time sets whose parameter is to be

varied (blank = all time sets). Disabled if Type = Level.

Module 30 - 24

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 Characterization Setup

Shmoo Setup – “Interpose” Field

function name function arguments

• Enter the names of the user-created functions to be called at specific points

in the characterization. These fields are enabled only on the X-axis tab.
• For each function, the second input box can take a comma-separated list of
arguments.

Start: Function to be called before beginning the characterization.

PrePoint: Function to be called before performing the test at each point.
PostPoint: Function to be called after performing the test at each point.
End: Function to be called at the completion of the characterization.

Module 30 - 25

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 Characterization Setup

Shmoo Setup – “Test Method” Field

•Retest: Causes the Body section of the current template to be

re-executed. This method is applicable to all types of tests.

•Reburst: Causes the current test pattern to be rerun. It is

applicable primarily to Functional tests. Rebusrting a
pattern set only reruns the last pattern in the set, not the
entire set.

Module 30 - 26

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 Characterization Setup

Shmoo Setup – Primary vs. Tracking Parameters

• Useful, when one parameter must move with another.

For example: VCompareHi <-> Vps
Vps -> Primary Parameter,
VCompareHi -> Tracking Parameter

• The first parameter is taken as the primary parameter.

• Any subsequent parameters are tracking parameters.
• Tracking parameters are varied in lock step with the primary
parameter.
• All the parameters for an axis are updated together before
the test instance is re-executed.
• To add tracking parameter, click on Add button

Module 30 - 27

- confidential -
 Characterization Setup
Margin Setup

• Only X-axis tab appears. No other tabs are used with Margin
• Similar to a one-dimensional (X-axis) Shmoo, except that tracking
parameters are not permitted.
• If a new parameter is added, each parameter is executed independently as
a separate Margin operation.
Module 30 - 28

- confidential -
 Characterization Setup

Adjust Setup

Module 30 - 29

- confidential -
 Characterization Setup

Adjust Setup – “Algorithm” Field

Auto - Use a variation of binary search that works

even if the parameter being measured drifts.
Pos – Use the Auto method, but find only a Fail-to-
Pass transition
Neg – Use the Auto method, but find only a Pass-to-
Fail transition.

Pos Binary - Use a pure binary search method; find

Linear search only a Fail-to-Pass transition.
Neg Binary - Use a pure binary search method; find
only a Pass-to-Fail transition.

Pos Linear - Use a linear method to find the first

passing point in the search range; if the first point
passes, returns a "Stuck at Pass" error code.
Neg Linear - Use a linear method to find the first
failing point in the search range; if the first point fails,
Binary search returns a "Stuck at Fail" error code.

Module 30 - 30

- confidential -
 Characterization Setup

Adjust Setup – Backoff and Adjust Spec Name

Backoff -> Enter the “backoff" or safety margin value to be applied to the
adjusted value.
Spec Name -> Enter the name of the levels or timing spec that will receive
the results of the Adjust.
The spec value resulting from an Adjust can be applied to subsequent test
instances in the flow. If a "backoff" value is specified, it will be applied to the
result in order to leave the test passing with a certain safety margin.
If a subsequent test instance has an "Overlay" column that specifies the
Adjust setup, the Adjusted value will be overlaid on top of that base timing or
levels definition.

Module 30 - 31

- confidential -
 Outline

• Overview
• Characterization Mode
• Characterization Setup
• Running Characterization
• Lab

Module 30 - 32

- confidential -
 Running Characterizations

Two ways:
1. Interactive Characterization
2. Characterization in the test program

Module 30 - 33

- confidential -
 Running Characterizations

Interactive Characterization
1. Set a breakpoint on the Flow Table sheet at the desired test to be
characterized.

2. Run to the breakpoint on the Flow Table sheet by clicking

3. When the breakpoint is reached, use the Step key to step through
the Pre-Body. (The Pre-Body is executed.)

4. The yellow flow arrow must be horizontal ,that is, pointing to the
Body.

5. Press the characterization button to bring up the Characterization

Editor, to select, edit, or create a new characterization.

6. Run the characterization by pressing the Run button on the

Characterization Editor.
Module 30 - 34

- confidential -
 Running Characterizations

Interactive characterization: Inter-sheet relations

Module 30 - 35

- confidential -
 Running Characterizations

Characterization in the test program

1. In the Flow Table sheet, select “characterize” in the Command Opcode.
2. Enter the instance name, defined in Test Instance sheet, and the setup
name, defined in Characterization sheet, into the Command Parameter,
separated by a blank.

Module 30 - 36

- confidential -
Running Shmoo

Shmoo Data Display

1D Shmoo (X axis only)

Display appears as a line of cells
along the X axis
2D Shmoo (X and Y axes)
Display appears as a grid of square
cells
3D Shmoo (X, Y, and Z axes)
Display appears like 2D Shmoo,
but with a slider bar beneath the
display, corresponding to Z axis.
Moving the slider bar displays the
different values of the Z axis.

Module 30 - 37

- confidential -
Running Shmoo

Shmoo Data Display

Site buttons

• Site n button for each site used,

plus one Site Merge button.
• Press individual Site buttons to see
the results for that site
• Press Site Merge button to see the
results from all sites merged.

Module 30 - 38

- confidential -
Running Shmoo

Shmoo Data Display

Cell Result
P - green = Pass
F - red = Fail
E - gray = Error
(none) - white = No test result, or
unable to test
On the Site Merge display, cells that
have both passing and failing sites
use a mix of green and red to indicate
the relative number of passing and
failing sites.
In addition, these cells display a
percentage of the sites that passed
the test at this cell.

Module 30 - 39

- confidential -
Running Shmoo

Shmoo Data Display

"Tool tip" point information

Moving mouse cursor over a cell,

following information will be displayed:

• Values of [X,Y,Z] at that cell

• Test result - Pass/Fail or Error
message.
• The measured values, if Measures
or Adjusts mode checked

On the Site Merge display, only the X,

Y, and Z values are displayed.

Module 30 - 40

- confidential -
Running Shmoo

Shmoo Data Display

Context Bar at the bottom of the

window shows:

• Name of the characterization setup

• Name of the test instance
• Name of AC category and selector
• Name of DC category and selector

Module 30 - 41

- confidential -
Running Shmoo

Shmoo Data Display

Reshmooing a cell
• Double-click on the cell to be
reshmooed
• Useful for cells to determine the
repeatability of the results

"Zoom" button
1. Drag from one corner to the
opposite corner of a rectangular
area to be zoomed
2. Press Zoom button to display a
new area of Shmoo

Module 30 - 42

- confidential -
 Running Adjust

Adjust Inter-sheet Relation

myAdjust

MUX

tadj

Module 30 - 43

- confidential -
Running Shmoo with Measures and Adjusts

If a Shmoo setup also contains Adjusts or Measures, the order of

operations is as follows:

• Apply the X, Y, and Z axis parameter values, to set up the

current conditions.
• Perform any Adjusts, in the order they are defined in the setup.
Propagate the results to specs, if desired.
• Perform any Measures, in the order they are defined in the
setup.
• If Measures were performed, move to the next X, Y, and Z point.
If no Measures are performed, either reburst the pattern or rerun
the test, as specified; then move to the next X. Y, and Z point.

Module 30 - 44

- confidential -
 Outline

• Overview
• Characterization Mode
• Characterization Setup
• Running Characterization
• Lab

Module 30 - 45

- confidential -
 DIB Access
Multiple Resources
Resource Sharing

Rev0343
- confidential -
 Objective

• The goal of this session is to understand how

DIB Access can help limit the number of DIB
relays when multiple resources are required to
perform different device tests on both single and
multi-site.

Module 31 - 2
- confidential -
 Outline

• Typical Configurations
• DIB Access Goals
• DIB Access Configuration
• Instrument DIB Access
• Channel Mapping
• Resource Sharing
• Multiple Resources
• Single-Site Example
• Multi-Site Example

Module 31 - 3
- confidential -
 Measurements
Examples:

1. Measure different parameters:

1. i.e. test the output of a comparator using a time measurement
instrument to measure the slew-rate, and a voltmeter to
measure the voltage swing.
2. Perform different types of tests on the same pin:
1. i.e., PPMUs are used to check that the input impedance is
within specification, and HSD channels are used to verify that
there are no functional/logic defects.

3. Test a device pin that is multi-functional and works as an analog

input under certain conditions and as an analog output under other
conditions.

Module 31 - 4
- confidential -
 Typical Configurations
BBAC

DUT Relay TMS

DIB TOOOO Many Relays

Relay
AWG
Test devices which
require multiple
instrument HSD
connections.
Module 31 - 5
- confidential -
 Ideal Solution
Universal Instrument

Digital, AC source,
DIB trace AC capture, Time
Measurement,
DUT Microwave, DC,
etc.

With higher levels of integration, we

When executing a sequence of can achieve greater
tests on a device, different instrument/channel density per
types of instruments may board but it is still not possible or
have to be connected to a cost-effective to have just one board
particular device pin at type with the full range of
different points during the capabilities offered by all the
test flow. instruments available on the tester
today.

Module 31 - 6
- confidential -
 DIB Access Design Goals
1. Reduce the number of relays needed to provide access to
multiple tester resources to a device pin.

2. Enable true parallel testing by allowing devices in any

number of sites to access the resource(s) needed
simultaneously.

3. Control the degradation in performance (hardware and

software) when the feature is used.

Module 31 - 7
- confidential -
 Flex Solution for DIB Access
Provides electrical
Primary Instrument Secondary Instrument path allowing a
secondary instrument
to be connected to a
device pin through
AC inst. DC inst. the primary
Provides access to instrument.
S F

PPMU
moderately high

TCAL
frequency AC, DC,
high-voltage and Allows the user to
digital resources. program the
secondary instrument
using “pin
programming” as if it
were connected
directly to the pin.
main access main access

Traces on DIB TP
DUT DIB

No busing, and thus

higher-quality signal
paths.

Module 31 - 8
- confidential -
 DCVI
DIB Access
X.a1 X.a2 X.b1 X.a3 X.a4 X.b4 X.b2

F S G F S G
X=<slot #>

Channel 1 Channel 2

2 DC channels per 1 DIB Access

Module 31 - 9
- confidential -
DCVI Pins

Module 31 - 10
- confidential -
 High Speed Digital
Main Access Main Access
DIB Access DIB Access
X.a33 X.c33 X.b32 X.d32 X.b36 X.a31 X.c31 X.b30 X.d30 X.a35

X=<slot #>

1 2 3 4 5 6 7 8

4 HSD channels per 1 DIB Access

Module 31 - 11
- confidential -
High Speed Digital Pins

Module 31 - 12
- confidential -
 BBAC Source
Differential Output Main Access
POS

REF

NEG
ACDGS

PPMU
PPMU
PPMU
DIB Access
1 DIB Access per BBAC channel line

Module 31 - 13
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 BBAC Capture
Differential Inputs Main Access
POS

NEG

ACDGS

PPMU

DIB Access
PPMU

1 DIB Access per BBAC channel

Module 31 - 14
- confidential -
 Channel Map Syntax
3.b4
MIC1P DUT 3.b3
MIC1N
4.d4 4.b4 4.c5 4.a5 POS NEG
4.d2 4.b2 4.c3 4.a3

HSD BBAC

REF
48 47 46 45 44 43 42 41
Slot 4 Slot 3

Pin Name Package Pin Type Site 0

MIC1P 20 I/O 4.d2
MIC1P:DA BBACSrcPos 3.b3
MIC1N 21 I/O 4.d4
MIC1N:DA BBACSrcNeg 3.b4

Module 31 - 15
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 Single-Site Example
Slot10 Slot15 Slot25
Channel A1 Channel B1 Channel B1

Primary InstA InstB InstC

Instrument

Main Access Main Access Main Access

DIB Access DIB Access DIB Access

Example 1: Traces on DIB

Connect a primary
and 2 secondary
instruments to PinA1 DIB
Site0
same device pin.

Pin Name Package Pin Type Site 0

PinA1 20 InstA 10.a1
PinA1:DA InstB 15.b1
PinA1:DA InstC 25.b1
Module 31 - 16
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 Multi-Site Example
Primary Instrument board
Slot 10 Secondary Instrument (B)
Slot 25
Channel B1
Multi-site
devices using
the same
instruments
B2 B4 C1 C3
DIB Access Main Access

Syntax for
sharing pinA1 pinA1 pinA1 pinA1

resources
across sites

Pin Name Package Pin Type Site 0 Site 1 Site 2 Site 3

PinA1 20 InstA 10.b2 10.b4 10.c1 10.c3
PinA1:DA InstB 25.b1 site0 site0 site0

Module 31 - 17
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 Resource Sharing
• It is possible for a single instrument to be shared by more than one
DUT pin or by more than one site in a multi-site test environment.
• To indicate that a resource is shared, you use special syntax for the
entry in the Tester Channel Site column of the Channel Map sheet.
– A pin can share a resource with another pin by indicating that the
same tester channel is connected to both pins.

Vcc shares a
dcvi channel
with vcc1

– Two or more sites can share a resource by indicating that the same tester
channel is connected to more than one site.

Dcvi at pins
10.a2 and 10.a6
are shared
between site0
and site1
Module 31 - 18
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 DIB Access/Resource Sharing
Primary Instrument(A) Secondary Instrument(C) Primary Instrument(B)
Slot 10 Slot 15 Slot 35
Channel A1 Channel B1 Channel B1

Main Access DIB Access Main Access DIB Access DIB Access Main Access

Example 2:
Device pins a1 and
a2 share the same Traces on DIB
secondary resource. pinA1 pinA2
DUT

DIB

Pin Name Package Pin Type Site 0

PinA1 20 InstA 10.a1
PinA1:DA InstC 15.b1
PinA2 30 InstB 35.b1
PinA2:DA InstC S:PinA1
Module 31 - 19
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 Multiple Resource
• Instruments of different types on the same board
can be directly connected to a DUT pin.
– To indicate that several resources are connected to a pin,
you use special syntax M for the entry in the Device Under
Test Pin Name column of the Channel Map sheet.
– For example, the following channel map entries indicate that
pin a1 is connected to three different instruments:

Module 31 - 20
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 DIB Access/Multiple Resource
Instrument(C) Primary Instrument (A)
Secondary Instrument (B)
Slot 25 Slot10 Slot15
Example 4: Channel a1 Channel a1 Channel b1

Device pin a1
connects directly
to two resources Main Access Main Access DIB Access Main Access DIB Access
and indirectly to
another.

pinA1
DIB

Pin Name Package Pin Type Site 0

PinA1 20 InstA 10.a1
PinA1:DA InstB 15.b1
PinA1:M InstC 25.a1

Module 31 - 21
- confidential -
Appendix

Rev0343
- confidential -
 Single-Site Example
Primary Instrument A Secondary Instrument B

Example 3: Slot 10 Slot 25

Device pins a1,
a2, a3, and a4
share the same
B2 B4 C1 C3
secondary B1

resource. DIB Access Main Access

a1 a2 a3 a4
DUT
DIB

A1 1 InstA 10.b2
A1:DA InstB 25.b1
A2 2 InstA 10.b4
A2:DA InstB S:A1
A3 3 InstA 10.c1
A3:DA InstB S:A1
A4 4 InstA 10.c3
A4:DA InstB S:A1

Module 31 - 23
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 Single-Site Example
Primary Instrument (A) Secondary Instrument (B)
Slot10 Slot25
Channel A1 Channel B1 Using an instrument as a
secondary resource (ie,
through the DA of another
Main Access DIB Access Main Access DIB Access instrument) does not
preclude the possibility of
using it as a primary
instrument (ie, connecting
pinA1 pinA2
it directly to another DUT
pin).
DIB

Pin Name Package Pin Type Site 0 Resource

PinA1 20 InstA 10.a1 sharing
syntax.
PinA1:DA InstB 25.b1
PinA2 InstB S:PinA1

Module 31 - 24
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 Multi-Site Example
Secondary Instrument
Primary Instrument
Slot10 Slot15
Channel A1 Channel B1

Sharing a secondary
instrument across Main Access DIB Access Main Access DIB Access

sites is supported.

pinA1 pinA1

Site 0 Site 1
DIB

Pin Name Package Pin Type Site 0 Site 1

PinA1 20 InstA 10.a1 site0
PinA1:DA InstB 15.b1 site0

Module 31 - 25
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 Multi-Site Example
Primary Instrument Secondary Instrument Primary Instrument Secondary Instrument
Slot 10 Slot 15 Slot 20 Slot25
Channel ch1 Channel ch1 Channel ch1 Channel ch1

DIB Access DIB Access DIB Access DIB Access

Main Access Main Access Main Access Main Access

pinA1 pinA2 pinA1 pinA2

DIB
Site 0 Site 1

Pin Name Package Pin Type Site 0 Site 1

PinA1 20 InstA 10.a1 20.a1
PinA1:DA InstB 15.a2 25.a2
PinA2 21 InstA S:PinA1 S:PinA1
PinA2:DA InstB S:PinA1 S:PinA1

Module 31 - 26
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 Multi-Site Example
Primary Instrument Secondary Instrument
Slot 10 Slot 25
Channel ch1 Channel ch1
This simply shows
the syntax for
sharing instruments
Main Access DIB Access Main Access
across sites and DIB Access

across pins

pinA1 pinA2 pinA1 pinA2

Site 0 Site 1
DIB

Pin Name Package Pin Type Site 0 Site 1

PinA1 20 InstA 10.a1 site0
PinA1:DA InstB 25.a2 site0
PinA2 21 InstA S:PinA1 S:PinA1
PinA2:DA InstB S:PinA1 S:PinA1

Module 31 - 27
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 Limitations
Based on premise that device pin requires connection to a primary
resource during most tests, and requirements on secondary resource is
less demanding.

Performance of secondary instrument is somewhat degraded.

DIB access is not intended to be used as an instrument mux.

Connection on the DIB must be between the main access of the secondary
instrument and the DIB access of the primary instrument.

Only the use cases described in the preceding section are supported.

Module 31 - 28
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Utility Bits & DIB
Power

Rev0343
- confidential -
 User Power & Utility Bits

• Purpose:
– User power for supplying voltages to DIB devices such as
relays
• 3 - 5 volt supplies
• 2 - 15 volts supplies
• 1 – 12 volt supply

– Utility bits for driving coils on Dib relays and for low speed
readback of logic states
• 128 Utility bits

Module 32 - 2
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 Support Boards
There are Two support boards in the Flex test system.
One is designated as the master support board (MSB) (805-003-00) and the other is the slave
support board (SSB) (805-003-01).

The test head is divided into two sections known as hemispheres.

The MSB is in the hemisphere of the test head which contains slots 1-13 and is located in slot 7.
The SSB is in the hemisphere which contains slots 14-26 and is located in slot 20.

Two cables from each board connect to 2 DIB slots. MSB to slots 8 and 20, SSB to slots 33
and 45. Left Hemisphere Right Hemisphere

8 DIB 33
Support Board Support Board
(Master) (Slave)
Slot 7 20 45 Slot 20

Module 32 - 3
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 Features

The customer-accessible functions are:

128 Utility data bits (UDBs) – 64 per support board.
User power Supplies - 6 supplies
Synchronization pulse signals
Serial bus

Module 32 - 4
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 Utility Bit Overview
Utility bits provide low-speed logic signals, which are capable of driving relay coils, and with low-speed readback of
The logic state on each pin.
Each circuit is similar to a simple digital channel with a driver, comparator, and digital control to change the state of the
driver and read the state of the comparator.
The driver controls the state of the relays on the DIB. (The driver output is a strong pull-down circuit with a weak pull-up
to 3.3V.)
Each UDB signal is connected to a comparator on the support board. DACs on the support board creates a threshold
voltage for the comparator. There is one DAC for each of the 32 UDBs.

DIB DAC
A

32 Serial Relay Serial

Drivers Comparators
Readback

TCIO

Comparators Serial
32 Serial Relay
Drivers Readback

DIB DAC
B

Module 32 - 5
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Support Board Pinouts

Module 32 - 6
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 Utility Bit Test Element
Utility bits are pins that allow a user control over relays or
logic that may be on the DIB. In this element, you must
supply a Utility pinlist
Utility Bits test element allows for turning utility bits on and
off.

Module 32 - 7
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 Utility Bits Off

• A Utility Bits Pinlist specifies utility bits on

support boards. Utility Pins "off" (0) is the list of
pins to turn off, or the list of relays to disconnect.

• Argument Details
- Optional
- Expression allowed
- Variable type – Pinlist
- Default input parm
- Default Read/Write

Module 32 - 8
- confidential -
 Utility Bits On

• A Utility Bits Pinlist specifies utility bits on

support boards. Utility Pins "on" (1) is the list of
pins to turn on, or the list of relays to connect.

• Argument Details
- Optional
- Expression allowed
- Variable type – Pinlist
- Default input parm
- Default Read/Write

Module 32 - 9
- confidential -
Pinmap/Channelmap

CurrentChannelMap.txt located in IGXL/tester

Module 32 - 10
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 User Power
• The purpose of user power is to provide voltages to the DIB to power relays,
logic and analog devices in user-supplied circuitry. This external circuitry is
used for additional signal processing capabilities that cannot be provided by
the test system.
• The DC/DC converters are located on the power board, which is mounted to
the support board.
– Two different power boards are used to support the different needs of the
MSB and the SSB.
– The on/off control and the alarm and shutdown circuits are located on the
support board itself.
• There are locations for six DC/DC converters, three on each support board’s
power board.
• Input to the converters comes from the external +48V power supply.
• All six of the user supplies have floating outputs.
– This means that each supply can be either a positive supply or a negative
supply and that they can be stacked to create higher voltages.

Module 32 - 11
- confidential -
 User Power Supplies
The user supplies are split between the MSB and SSB as follows:
MSB:+5V (generally used for powering digital circuits)
+5V (generally used for powering digital circuits)
+15V (generally used for powering analog circuits)
SSB: +12V (generally used for powering relays)
+5V (generally used for powering relays)
+15V (generally used for powering analog circuits)
The +15V supplies are filtered to provide an electrically quieter signal to the DIB.
Since each support board drives two DIB locations, the signals are split coming out of the board and driven to both DIB locations.
+ 12

+5

+15 V
+ 48V C onne ctor
to D IB
+ 5V

+ 5V

+15 V

T C IO A larm and
On/ Off C ontrol T C IO
(U se r Contr olle d) S hutdow n

Module 32 - 12
- confidential -
 User Power Pins
Master Support Board Left hemisphere connects to Dib slots 8 and 20

Slave Support Board Right hemisphere connects to Dib slots 33 and 45

Module 32 - 13
- confidential -
 User Power Test Element
The DIB Power Test Element is used to turn voltages available on the DIB on or
off.
Voltages can be turned on/off individually by selecting “Turn On”/ “Turn Off”
from the drop down list.

Each supply connects to 2 DIB

blocks through 8 pogo pins
labeled a-h. There is a Hi and Lo
side for each pin.

Module 32 - 14
- confidential -
 Sync Pulses
The synchronization (sync) pulse system allows the user to view internal test system signals on an oscilloscope while
debugging a test program.
The sync signals pass through the support board to the DIB area via the support board’s I/O connector.
The signals include one analog signal (A1) and two digital signals (D1 and D2).
The backplane contains three buses from the slots to the support board.
The support board takes the three backplane buses, multiplexes them and connects them to the DIB via the I/O
connector.
The muxing and pulse generation are done in the TCIO FPGA. A Sync Microcode must be placed on the appropriate
vector during debug
The support board simply passes the analog signal from the backplane to the DIB.
The A1, D1, and D2 signals are also made available at the test head EMO panel on the test head.
S y n c S ig n al s o n D IB b o ard B ac k p lan e
A1 D1 D2 In s tru m en t
P IO

Pa tG en D A DU T

S y n c P u ls e M u x /S p o t
P u ls e
One-shot 5-8us pulse
F
H UB C
X

Su p p o rt B o ard
D ig S Y N C 1 Tes t H ea d
D ig S Y N C 2 E MO
A n alo g Sy n c P an e l

Module 32 - 15
- confidential -
 References

• See DIB Design Guide and Support Board

Guide in IGXL Help:
– DIB Design Guide
– Support Board

Module 32 - 16
- confidential -
 Support Boards

Slot 1 DIB Slot 26

J1 J26
Test Head Slots

Test Head Slots

J8 J33
Slot 7 Slot 20
C
A
B
J20 L J45
E

J25 J50
Slot 13 Slot 14

Slots 7 and 20 are FLEX Support Boards

Module 32 - 17
- confidential -
FLEX

FLEX
SCAN Concepts
FLEX
Terms, Acronyms and Abbreviations

ATP ASCII Test Pattern

ATPG Automated Test Pattern Generation
DIB Device Interface Board
EDA Engineering and Design Automation (software)
FPGA Field programmable gate array
IG-XL Teradyne’s Windows™-based Test Programming Tools Environment
NIST National Institute of Standards and Technology
PDE Procedure Development Environment
SCAN Teradyne Integra Flex digital scan testing
TCIO Test Computer Input/Output
TDE Test Debug Environment
TE Test Element
VBA Visual Basic for Applications
VBT Visual Basic for Test
FLEX
Pre-requisites

• General understanding of scan-based digital testing

• Familiar with IG-XL
• Experienced with creating /compiling digital patterns
FLEX
To Learn More About…

FLEX SCAN Capability and Programming:

• Integra FLEX “IG-XL Solutions: SCAN Testing” Manual
• Due for release with IG-XL V5.0

Scan Testing:
• “Design for Test for Digital ICs and Embedded Core Systems” by
A. L. Crouch (1999)

• “IEEE Standard Test Access Port and Boundary-Scan

Architecture” (IEEE Std 1149.1)
FLEX
Topics Covered

Level I:
• FLEX HSD200 SCAN
• Architecture
• Capability
• Scan programming
• Simplified SCAN Optimization Methodology
• Scan chain oriented
• Assess Æ Assign

Level II:
• SCAN Concepts in Detail
• Shared LMV, Packing & ADB Data Path
• SCAN Depth and Data Rate Accounting
FLEX
Flex SCAN Architecture

DIB
16 x 200MHz digital channels
per SCAN region (instrument)

Each channel can select

data from a 28-bit ADB

3G “Sea-of-bits” available
to any channel
Flex
FlexChannel
ChannelBoard
Board
FlexHSD200
ChannelBoard
Board

3 SCAN regions per HSD200

• Scan available on any digital pin

• 3G vector memory configurable at load time for narrow or wide scan
• Up to 200MHz scan possible for widest range of scan applications
FLEX
Table 1: HSD200 SCAN Capability
Number of Maximum Depth Maximum Data Rate
Scan Chains (M cycles) (M cycles/sec)
1, 2 1,536 200
3 1,024 200
4 768 200
5 576 50
5, 6 512 200
7 256 200
7, 8 384 100
9 256 100
9 320 50
10, 11, 12 256 100
13, 14 128 100
13, 14, 15, 16 192 50
17 to 24 128 50

• All HSD200 boards support SCAN (Subject to License Restrictions)

• Each HSD200 board supports the above scan chain configurations
FLEX
Flex SCAN Programming Steps

1. Decide if SCAN optimization is required. (This must be done

before a DIB is designed!)
2. If optimization is not required, skip to Step 5.
3. Gather the optimization information together.
4. Use the SCAN Optimization Tables and Equations to assess
scan test requirements against available HSD200 resources.
5. Develop the Channel Map. If SCAN optimization is required, it is
important to include the appropriate channel allocation
constraints in the Channel Map (and DIB design!).
6. Create Integra Flex SCAN pattern (.atp) files. These may be
hand-generated. Most often they will be machine-generated
using an EDA vendor’s ATPG tool.
7. Compile pattern files. To take advantage of SCAN optimization,
scan pattern files must not be compiled as parallel.
8. Use scan pattern (.PAT) files in pattern groups, pattern sets and
functional test instances like any other test patterns
FLEX
Why Optimize for SCAN?
Why optimize?
• To make the most of the Flex’s SCAN capability, you must assign
scan channels to optimize for SCAN depth. Otherwise, you will
not be able to achieve the HSD200 SCAN capability described in
Table 1.

What is optimized?
• Maximum SCAN pattern depth (and/or data rate).

What is the result of optimization?

• Digital channel assignment (Channel Map) requirements.

How easy is it to optimize?

• An optimal scan channel allocation table has all ready been
created for you.
• You simply need to assess your scan test requirements
against available HSD200 resources. Then use the optimal
channel allocation table while assigning channels.
FLEX
How easy is it?

Flex SCAN Optimization

ASSESS ASSIGN

• An optimal scan channel allocation table has all

ready been created for you.
• You simply need to assess your scan test
requirements against available HSD200 resources.
Then use the optimal channel allocation table while
you assign channels.
FLEX
HSD200 SCAN Regions

There are 3 SCAN Regions per HSD200 board.

There are 16 Channels per SCAN Region.

Region #1: Ch1 to Ch16
Region #2: Ch17 to Ch32
Region #3: Ch33 to Ch48

The SCAN Region Channels share 3,072 M scan data bits.

FLEX
Table 2: Optimal Channel Allocation
SCAN Region SCAN Region SCAN Region
Scan Chains 1 2 3
Per Board In Out In Out In Out
1 1 0 0 1 0 0
To maximize scan 2 2 0 0 1 0 1
depth, assign 3 1 1 1 1 1 1
4 2 1 2 1 0 2
SCAN channels 5 3 1 1 2 1 2
based on these 6 2 2 2 2 2 2
per-region 7 1 3 3 2 3 2
8 4 2 2 3 2 3
channel 9 3 3 3 3 3 3
allocations 10 4 3 2 4 4 3
11 3 4 3 4 5 3
12 4 4 4 4 4 4
13 3 5 7 3 3 5
14 6 4 4 5 4 5
15 5 5 5 5 5 5
16 4 6 6 5 6 5
17 5 6 5 6 7 5
18 6 6 6 6 6 6
19 6 7 6 7 7 5
20 6 7 6 7 8 6
21 7 7 7 7 7 7
22 6 8 6 8 10 6
23 9 7 7 8 7 8
24 8 8 8 8 8 8
FLEX
When not to bother?

• If all of your test program’s scan patterns will be

compiled and loaded as parallel patterns, then no
optimization is necessary. In this case, the loading
and run-time behavior of scan vectors can be
considered to follow the same rules as parallel
vectors.

• If the test program’s total test pattern size is less than

the maximum available LVM size (E.g. 64 M).
FLEX
Important SCAN Information
To optimize, you first need to assess the scan test requirements. To
do this you need to know:
• Number of Flex HSD200 boards available
• Number of device scan chains
• LVM Depth and Parallel Pattern memory requirements

Where can a Test Engineer get this information?

For the number of Flex HSD200 boards:
•Check the Flex configuration file (CurrentConfig.txt)
For Device-specific information, refer to:
•Device DFT and Test Guideline Documentation
•DFT Engineers
•Design and Validation Engineers
•Product Engineers
FLEX
How to Optimize for SCAN?

Once you have the necessary information, the rest is straight-forward.

First, ASSESS needs and capabilities:

1. Calculate the number of scan chains per HSD200.
2. Determine the pattern memory configuration factor.
3. Determine the system’s unrestricted scan pattern depth.
4. Calculate the available scan pattern depth when LVM is reserved
for parallel pattern memory.
5. If the result of 4 satisfies the scan testing requirements (scan
depth and data rate), then continue. Otherwise, additional
HSD200 boards may be required and these steps will need to be
repeated.

Next, ASSIGN channels:

• Follow the optimal SCAN channel assignment table (Table 2).
This optimized scan channel assignment information must be
included as part of the DIB design requirements.
FLEX
Assess Step 1

1.First, Calculate then maximum number of chains that will be assigned to a channel
board (Nmax_chains_per_board):

If Nchannel_boards divides evenly into Nchains_per_device without a remainder then:

N max_ chains _ per _ board = N chains _ per _ device ÷ N channel _ boards

Equation 1

Otherwise:
N max_ chains _ per _ board = N chains _ per _ device ÷ N channel _ boards  + 1
Equation 2

(Recall: The open-top brackets mean round-down the result)

FLEX
Assess Steps 1 thru 4

2.Calculate the Pattern Memory Configuration Factor (kmem_config) based on the LVM
depth and the parallel pattern memory depth.

k mem _ config = [1 − Parallel _ Pattern _ Memory / Total _ LVM ]

3.Next, use the previous calculated Nmax_chains_per_board to lookup the maximum scan
depth (Dmax_scan_depth) from Table 1.

Note: In Table 1 several scan chain configurations offer the option to trade-off maximum
available scan depth to support increased scan data rate. Depending on the application
requirements, this may be desirable.

4. Using the values in steps 2 and 3, calculate the scan depth available for the given
configuration (Dscan_depth) using the following expression:

D scan _ depth = k mem _ config × Dmax_ scan _ depth

If Dscan_depth meets the scan testing requirements, then continue. Otherwise, it may be
necessary to add more HSD200 boards to reduce Nmax_chains_per_board . If more boards
are added, you will need to repeat steps 1 through 4.
FLEX
Assign Steps 1 & 2
1. Use the value for the number of scan chains per board (Nmax_chains_per_board calculated in
Assess step 1) to look up an optimal scan channel allocation from Table 2.

2. Assign digital channels to the Channel Map using the channel allocation
recommendations described in Table 2. IMPORTANT: Make sure that the DIB design
conforms to the required channel assignment.

Next, we will consider a practical example.

FLEX
Optimization Example

Example 1:
1 site, 32 scan chains per site. At least 256 M cycles of scan data is required and 8
M of LVM will be reserved for parallel pattern data. Scan data will be run at up to 50
MHz. The Flex system is configured with 6 HSD200 boards.

Assess Step 1:
32 chains / 6 boards = 5.33 chains per board
In this case the number of boards does not divide evenly into the number of scan
chains. So, Equation 2 applies and Nmax_chains_per_board = 6

Assess Step 2:
kmem_config= (1 – 8 / 64) = 0.875

Assess Step 3:
Referring to Table 1, and using Nmax_chains_per_board = 6, we find Dmax_scan_depth = 512 M
(with a maximum data rate of 200 MHz)

Assess Step 4:
Calculate Dscan_depth = kmem_config x Dmax_scan_depth
= 0.875 x 512 M = 448 M cycles SCAN (@ up to 200 MHz)
This configuration can support the scan testing requirements (320 M @ up to 50 MHz)
FLEX
Optimization Example

Example 1 (continued):

Assign Step 1:
As noted earlier, 6 does not divide evenly into 32. This implies that some boards will
have 5 chains whild others will have one extra chain. In fact, 5 chains will be
assigned to 4 of the available HSD200 boards and 6 chains will be assigned to
2. (However, the 6-chain boards must be used to calculate the maximum scan
depth.)

From Table 2, the optimal scan channel allocation for each 5-chain board is:
SCAN Region #1 Æ 3 scan-in, 1 scan-out
SCAN Region #2 Æ 1 scan-in, 2 scan-out
SCAN Region #3 Æ 1 scan-in, 2 scan-out

Similarly, the optimal scan channel allocation for each 6-chain board is:
SCAN Region #1 Æ 2 scan-in, 2 scan-out
SCAN Region #2 Æ 2 scan-in, 2 scan-out
SCAN Region #3 Æ 2 scan-in, 2 scan-out

NOTE: Actual channel assignments do not have to be sequential. It is only important

that the sum of scan-in (or scan-out) channels be as prescribed here.
FLEX
Optimization Example

Example 1 (continued):

Assign Step 2:
Channel Assignment Steps:
A. Assign channels to 5-chain channel boards:
Using the per board channel allocation from Step 5:
1) Assign Scan-in channels for one SCAN region
2) Assign Scan-out channels for the same region
3) Repeat 1 and 2 for each of the 3 SCAN regions on a board
4) Copy the channel assignment to the other 5-chain boards

B. Assign channels to 6-chain channel boards

Using the per board channel allocation from Step 5:
1) Assign Scan-in channels for one SCAN region
2) Assign Scan-out channels for the same region
3) Repeat 1 and 2 for each of the 3 SCAN regions on a board
4) Copy the channel assignment to the other 6-chain boards

NOTE: Actual channel assignments do not have to be sequential. It is only important

that the sum of scan-in (or scan-out) channels be as described in Table 2.
FLEX
Optimization Example
Example 1 (continued):
This is what an optimized channel map could look like:
Scan-in pins Scan-out pins
Scroll down…

NOTE: These are

bogus Flex Channel
names used to simplify
this example.
However, currently,
one needs to use Flex
DIB pogo names here.
This is conversion is
easily done using this
channel allocation
description and a
lookup table.

Non-scan pins can be assigned to any free channels

FLEX
Multi-site considerations

If SCAN Broadcast is used for multi-site testing, additional sites may

tested without consuming additional LVM scan memory.

The previously discussed methodology can be used for up to 8 sites.

However, there are additional channel assignment restrictions when

using SCAN Broadcast. In particular, for a given device pin,
channels for each site must come from the same SCAN region.

For Multi-site configurations, Step 6 is repeated for each site:

• After assigning channels for the first site, re start the process for the next site
using free channel. Be sure that all channels for a given device pin are part of
the same SCAN region.
FLEX
Multi-site Example
Example 1 for 2 sites:
This is what an optimized channel map could look like:
Scan-in pins Scan-out pins
Scroll down…

Non-scan pins can be assigned to any free channels

FLEX
SCAN Broadcast

SCAN Broadcast (a.k.a. Scan data sharing)

– Enables channels from the same SCAN region to “listen”
to the same scan data
– Therefore, drive and compare data for the same scan pins
across multiple sites does not need to be duplicated.
– This capability is automatically managed by IG-XL based
on the device channel mapping.
– This feature can be disabled. However, maximum scan
data depth will be reduced. (scan patterns may no longer
load)
– Adds a per-site channel count constraint on this SCAN
optimization methodology. (This makes the methodology
a little more complex.)
FLEX
SCAN Pattern Programming
SCAN pins declaration: // .ATP File Example
scan_pins = { <scan_pin_list> } scan_pins = {
pin0:1, // a.k.a. si0 Cannot use
pin1:1, // a.k.a. si1 pin group
SCAN Micro-codes: pin2:2, // a.k.a. so0 names in
scan_setup (optional) pin3:2, // a.k.a. so1 scan_pins
scan <N> }
declaration.
import tset TS_S, TS_P;
SCAN Vectors:
vector ( $tset, pinCLK:S, pins_0to3:S)
Scan-in pin: {
( si <pin>:<data_type> > <vector_data> ) > TS_P 0 0011;
scan_setup defines
the states of the non-
Scan-out pin: > TS_P 0 0000;
scan_setup scan pins during a
( so <pin>:<data_type> > <vector_data> )
> TS_S 1 10LH; scan vector.
scan 10
Where: ( si si0:S > 1000101001 ) Can use pin group
<scan_pin_list> = comma-delimited list of ( so so0:S > HHHLHLHLLH ) names in scan
( si si1:S > 0010101011 )
<pin>:<data_size>,
( so so1:S > LLHLLXLXHL );
vectors. Eg. Single-
(Note: Last item listed must also include a comma.) > TS_P 0 1110; pin pin group as
> TS_P 0 0100; scan pin name
<data_size> = 1 or 2 > TS_P 0 1011; aliases.
(Note: Scan-in pinÆ1, Scan-out pin Æ 2) end_module
> TS_P 0 0011;
}
<N> = integer value 2 to 65280
(In Dual Timing Mode, N must be evenly divisible by 2.
In Quad Timing Mode, N must be evenly divisible by 4.) This .ATP will compile into Single and
Dual Timing mode patterns. What
<pin> = pin from job pin map changes are needed for Quad Mode?
Hint: 4-cycle vector grouping and
<data_type> = S, X (Default is S) “by-4” scan cycles are required.

<vector_data> = valid data for data type

FLEX
SCAN Pattern Programming

For more information about IG-XL SCAN Pattern Programming please

refer to the IG-XL on-line help.

Related Topics:
• Scan vector shorthand
• Compiling scan vectors as parallel vectors
FLEX
Pin Map
FLEX
Channel Map
FLEX
Pattern Tool
FLEX
Flex SCAN Calculator

• Developed by DFT Apps (J. Gatej)

• Handles the detailed calculations

• Supports assessing multi-site configurations including greater-than

8 site SCAN broadcast applications

• Handles asymmetric (un-paired) scan-in and scan-out pin configs

• Enables side-by-side comparison of various configurations

PREVIEW: Flex SCAN Calculator Tutorial

Slated for General Release at TUG 2003
Previews available upon request.
FLEX
Up to 3G and 6G (Scan-in Only)

If up to a single scan-in pin is assigned to each

SCAN region:
– Up to 3,072 M (3 G) of scan data can be stored in
LVM.
– If high-frequency drive mode is use, 2 SCAN
regions’ worth of LVM can be used behind a single
scan-in channel. This provides up to 6,144 M (6 G)
scan-in only depth.
• Xilinx uses this technique for extremely large scan-
in-only patterns
• I think Keith Thomas is familiar with how this is
implemented.
FLEX
Related Topics

Non-paired scan-in and scan-out pins

– The calculations are more complex and the scan-chain-
oriented methodology can not be used.

– Instead, some resource accounting is required. Use

these expressions to calculate the maximum scan depth
and determine the maximum scan data rate for a given
scan region.
FLEX
Future Work/Related Topics

SCAN Fail Capture

– HRAM 1-bit-mode for up to 6 k fails
• Caveat:
Failed cycle number known for only 256 of 6 k

– Fail Capture Memory

• Initial experiments done by Noreen Ward.
• Promising, but there are additional scan chain configuration
constraints… not discovered yet.
• Likely to consume additional ADB bits. This will reduces
maximum number of scan chains per board and may reduce
max data rate.

Identifying SCAN applications

– Reading a scan pattern file to identify DC vs AC scan
tests
FLEX
SCAN Lab Outline

Test program to:

• Practice the SCAN channel assess and assign methodology.
• Practice how to write a scan test pattern
• Illustrate how the same test pattern may use different amounts of
LVM based on the channel map configuration.
• Illustrate how Scan Broadcast (Scan data sharing) is used for
multi-site testing.
• Use Pattern Tool II to debug and edit scan patterns

• Possible tie-in to diagnosis software (Future work)

FLEX

Background Materials
(a.k.a. The Gory Details)
FLEX Flex Alternate Data Bus (ADB)

Alternate Data Bus

Used to transfer SCAN data bits to
tester channels.

Facilitates deep and flexible SCAN

data distribution from LVM to each
channel.

Facilitates SCAN Broadcast

Single set of scan data to several scan
channels (Multiple sites)

One 28-bit ADB per SCAN Instrument.

ADB bits are multiplexed to achieve

higher data rates.
FLEX
HSD200 SCAN Instrument

Key Features:
Shared Linear Vector Memory (LVM)
Alternate Data Bus (ADB)

The following will discuss these features in

terms of a single, 16-channel SCAN region.
There are 3 SCAN regions available per digital
channel board!

NOTE: A “SCAN Region” may also be referred to as a

“SCAN Instrument”.
FLEX
Flex Shared Large Vector Memory (LVM)

Scan pattern shares the same Large Vector

Memory subsystem with parallel pattern
data.

Scan pattern data can be thought of as a being

stored in a “Sea-of-bits”.

SCAN concepts:
How pattern data is:
1) Allocated during load
2) Accessed and distributed at run time
FLEX
Flex Shared LVM
Loaded Pattern Data
Parallel Pattern Data
3-bits per cycle loaded behind each
channel.
Up to 64M of parallel cycles stored.
2 channels use the LVM space of one!
(Up to 3 scan in cycles per parallel cycle.)
Scan Pattern Data
Each set of 3-bits is no longer
devoted to a particular channel.

1-bit or 2-bits per cycle, per scan

channel.

Sea-of-bits stored in a separate

region of LVM

At least 2X increase in pattern depth

(per chain) as compared to
equivalent parallel vectors.
Up to 24X increase in pattern depth
(per chain) possible.
FLEX
Flex Shared LVM
Runtime access of Pattern Data
Parallel Pattern Data
Per-cycle data is always 3-bits per
channel.
A total of 48-bits per tester cycle (16
channels).

Scan Pattern Data

Per-cycle data access is
“orthogonal” to parallel pattern
data access.

Total number of bits accessed per

cycle is determined by scan
channel assignments.
FLEX
Shared LVM & ADB

How Shared LVM and the ADB work together

for Flex SCAN…
 FLEX
LVM Pattern Data
How LVM pattern data is organized after loading and accessed
at runtime…
Parallel LVM data is
Data
accessed four
LVM addresses
at a time.

Size of each
LVM vector:
3-bits per channel
per LVM Address
X
16 channels
=
Scan 48-bits per LVM
Data
(8 chains) address

This is true for both

Note: In this 8-chain example, each Parallel and SCAN
LVM address stores 2 cycles of So, if all 64 M LVM locations pattern data
single timing mode scan data. are used for scan data only, 2 x
64 M = 128 M cycles of scan
pattern data can be stored!
FLEX
LVM Pattern Data

Parallel LVM data is

Data
accessed four
LVM addresses
at a time.

Size of each
LVM vector:
3-bits per channel
per LVM Address
X
16 channels
=
Scan 48-bits per LVM
Data
(1-chain) address

This is true for both

Note: In this 1-chain example, Parallel and SCAN
each LVM address stores 16 So, if all 64 M LVM locations are pattern data
cycles of single timing mode used for scan data only, 16 x 64 M
scan data. = 1,024 M cycles of scan pattern
data can be stored!
FLEX
Shared LVM & ADB

Using the channel assignments indicated in the

IG-XL channel map worksheet, IG-XL
automatically allocates ADB resources. So
for the most part, all you need to do is get
the channel map right for your scan testing
application.

The discussion here is to help you better

understand what is going on “under the
hood”.
 FLEX
1,536 M cycles: One Scan-in only region
NOTE: This slide is best understood when viewed in color.

Pin
Electronics

Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
Formatters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 50
LVM/ADB MHz
Select
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Parallel
Vector
Data Bus
(16x3 = 48 bits)
48
Note: In this case, 48 bits / 2bits-per-
2 2 2 2 = 242 cycles
cycle 2 data
2 of scan 2 fits in2 2 2 2 2 2 2 2
ADB
Bit Select each LVM location.

28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28
Alternate
Data 28
Bus
(28 bits) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

1 48
Vector Parallel
Memory Data 50
(64Mx48 = 3G bits) .. MHz
Scan So, if all 64 M LVM locations are
Data
used for scan data only, 24 x 64
M = 1,536 M cycles of scan
pattern data can be stored!
 FLEX
1,536 M cycles: Two Scan-out regions
NOTE: This slide is best understood when viewed in color.

Pin
Electronics

Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
Formatters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 50
LVM/ADB MHz
Select
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Parallel
Vector
Data Bus
(16x3 = 48 bits)
48
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
ADB
Bit Select
28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28
Alternate
Data 28
Bus
(28 bits) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

1 48
Vector Parallel
Memory Data 50
(64Mx48 = 3G bits) .. MHz
Scan
Data
FLEX
How to get up to 1,536 M
Earlier, we saw how a single 1,024 M cycle scan chain will fit
into a single scan region.
DIB

Using 3 SCAN regions, a single HSD200 supports up to two

1,536 M cycle scan chains.

Of course, the secret is in the Channel Mapping:

SCAN Region 1 Æ 2 scan-in channels
SCAN Region 2 Æ 1 scan-out channel
SCAN Region 3 Æ 1 scan-out channel
 FLEX
Pattern Data Path Diagram
NOTE: This slide is best understood when viewed in color.

Pin
Electronics

Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
Formatters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
LVM/ADB 50/
Select
100/
Parallel 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 200
Vector MHz
Data Bus
(16x3 = 48 bits)

48
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
ADB
Bit Select
28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28
Alternate
Data 28
Bus
(28 bits) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

1 48
Vector Parallel
Memory Data 50
(64Mx48 = 3G bits) .. MHz
Scan
Data
 FLEX
Parallel Vector Only
NOTE: This slide is best understood when viewed in color.

Pin
Electronics

Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
Formatters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 50
LVM/ADB MHz
LVM

LVM

LVM

LVM

LVM

LVM

LVM

LVM

LVM

LVM

LVM
LVM

LVM

LVM

LVM

LVM
Select
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Parallel
Vector
Data Bus
(16x3 = 48 bits)
48
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
ADB
Bit Select
28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28
Alternate
Data 28
Bus
(28 bits) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

1 48
Vector Parallel
Memory Data 50
(64Mx48 = 3G bits) .. MHz
Scan
Alternate Data Bus
Data is not used at all.
 FLEX
8 Chains in Single Mode Example
NOTE: This slide is best understood when viewed in color.

Pin
Electronics

Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
Formatters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 50
LVM/ADB MHz
ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB
ADB
Select
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Parallel
Vector
Data Bus
(16x3 = 48 bits)
48
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
ADB
Bit Select 1,2 3 4,5 6 7,8 9 10,11 12 13,14 15 16,17 18 19.20 21 22,23 24

28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28
Alternate
Data 28
Bus
(28 bits) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

1 48
Vector Parallel
Memory Data 50
(64Mx48 = 3G bits) .. 1 cycle worth of data placed on the MHz
Scan ADB every 20 ns (50 MHz). The
Data total number of bits placed on the
ADB at a time is referred to as the
SCAN Stride.
 FLEX
1 Chain in Single Mode Example
NOTE: This slide is best understood when viewed in color.

Pin
Electronics

Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
Formatters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 50
LVM/ADB MHz

ADB

ADB
LVM

LVM

LVM

LVM

LVM

LVM

LVM

LVM

LVM

LVM
LVM

LVM

LVM

LVM
Select
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Parallel
Vector
Data Bus
(16x3 = 48 bits)
48
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
ADB
Bit Select 2,3 1

28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28
Alternate
Data 28
Bus
(28 bits) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

1 48
Vector Parallel
Memory Data 50
(64Mx48 = 3G bits) .. MHz
Scan 1 cycle worth of data placed on
Data
the ADB every 20 ns (50 MHz). scan_setup data applied
(Here, the SCAN Stride = 3) to non-scan channels.
 FLEX
1 Chain in Dual Mode Example
NOTE: This slide is best understood when viewed in color.

Pin
Electronics

Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
Formatters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 100
LVM/ADB MHz

ADB

ADB
LVM

LVM

LVM

LVM

LVM

LVM

LVM

LVM

LVM

LVM
LVM

LVM

LVM

LVM
Select
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Parallel
Vector ADB bits are
Data Bus multiplexed 2X.
(16x3 = 48 bits)
48
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
ADB
Bit Select (2,3)
(5,6)
(1)
(4)

28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28
Alternate
Data 28
Bus
(28 bits) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

1 48
Vector Parallel
Memory Data 50
(64Mx48 = 3G bits) 2 cycles’ worth of data .. MHz
placed on the ADB every
Scan The number of cycles
Data 20 ns (50 MHz).
(SCAN Stride = 6) placed on the ADB
depends on the pattern
timing mode.
 FLEX
1 Chain in Quad Mode Example
NOTE: This slide is best understood when viewed in color.

Pin
Electronics

Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
Formatters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 200
LVM/ADB MHz

ADB

ADB
LVM

LVM

LVM

LVM

LVM

LVM

LVM

LVM

LVM

LVM
LVM

LVM

LVM

LVM
Select
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Parallel
Vector ADB bits are
Data Bus multiplexed 4X.
(16x3 = 48 bits)
48
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
ADB (2,3) (1)
Bit Select (5,6)
(8,9)
(4)
(7)
(11,12) (10)
28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28
Alternate
Data 28
Bus
(28 bits) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

1 48
Vector Parallel
Memory Data 50
(64Mx48 = 3G bits) .. 4 cycles’ worth of data MHz
Scan placed on the ADB every
Data
20 ns (50 MHz).
(SCAN Stride = 12)
FLEX
50MHz ADB

Data 1 0 1 0

200MHz
100MHz
Scan
Input

ADB1 ADB2 ADB1

ADB3 ADB2
ADB4
0 ns 10 ns 20 ns 30 ns 40 ns

• The Alternate Data Bus (ADB) has a 50MHz bandwidth

• In order to run scan patterns over 50MHz, multiplexing is required
• For 50-100MHz, two ADB lines must be multiplexed per scan bit
• For 100-200MHz, four ADB lines must be multiplexed
FLEX
Scan Resource Allocation Examples

LVM ADB Pin Electronics

28 bits 16 chans
64Mx48 24
3
6
12
2 bits
bits 12
824bits
bits
bits 28
21scan-in
4 chains
chain

28 bits 16 chans
64Mx48 24
3
6
12
2 bits
bits 12
824bits
bits
bits 18
21scan-out
4 chains
chain

28 bits 16 chans
64Mx48 24
3
6
12
2 bits
bits 12
824bits
bits
bits 18
21scan-out
4 chains
chain

HSD200

Number of Max Depth Max Data Rate

This table lists
Scan Chains (M cycles/sec) some per-board
2 1,536 M 200 results
Table 1 lists all
3 1,024 M 200 of the
possibilities.
6 512 M 200
12 256 M 100
24 128 M 50
FLEX
More about SCAN Stride
SCAN Stride:
• The number of SCAN data bits placed on the ADB at a
time (During a 20 ns period). These data bits may be for
several scan channels as well as several scan cycles.
• Up to 28 bits can be placed on the ADB at a time.

Factors that affect SCAN Stride:

• Number of scan in channels per SCAN region
• Number of scan out channels per SCAN region
• Pattern Data Rate Mode (Single, Dual or Quad)

Stride Loss:
• Each LVM pattern data memory location is 48-bits wide
• So, if the SCAN Stride does not divide evenly (without a
remainder) into 48, then some LVM bits cannot be used.
FLEX
SCAN Stride Loss
Stride Loss Examples:

Example A: 3 chains in Single Mode: SCAN Stride = 9 bits

cycle N cycle N+1 cycle N+2 cycle N+3 cycle N+4

1 48
48 mod 9 = 3 bits
(unused)

Example B: 6 chains in Single Mode: SCAN Stride = 18 bits

cycle N cycle N+1

1 48
48 mod 18 = 12 bits
(unused)
FLEX
SCAN Stride Loss
Stride Loss and Data Rate Example:

Example A: 3 chains in Single Mode: SCAN Stride = 9 bits

cycle N cycle N+1 cycle N+2 cycle N+3 cycle N+4

1 48
48 mod 9 = 3 bits
(unused)

Example C: 3 chains in Dual Mode: SCAN Stride = 18 bits

cycle N & cycle N+1 cycle N+2 & cycle N+3

1 48
48 mod 18 = 12 bits
(unused)

Therefore, Scan Depth may be affected by Data Rate.

(N.B. This is not always the case.)
 FLEX
Additional SCAN Data “Loss”
Due to 4 LVM Location Memory Access
• Some SCAN data bits may be wasted if a pattern’s sequential
scan data does not fill the entire 4x48 = 192 bits
• This occurs on a per pattern file (.PAT) basis
• This does NOT occur per scan vector loop
• However, in most practical use cases:
• Each pattern will have hundreds of scan vector loops.
• Each scan vector will have several scan pins each with several
hundred cycles.
• Under these circumstances, this loss is negligible.
Worst-Case Example:
• In one pattern file, two cycles per scan vector loop, one scan-in pin. This
pattern file (or similar ones) are loaded sequentially many times to LVM.
Scan LVM data is
Data accessed four
(1 scan-in)
LVM addresses
at a time.
(Total of 192 bits of
SCAN data)

Only 2 out of every 192 bits used.

 FLEX
Additional SCAN Data “Loss”
Practical Example:
• The pattern has: Single chain, (one scan-in, one scan-out). 250
scan cycles per scan vector loop. 100 scan vector loops.
(Assumption: Both channels assigned to same SCAN region.)
16 cycles of scan data per LVM address

Scan
Data With this channel
(1-chain) configuration, 1536
LVM addresses are
used to store
250x100 = 25,000
cycles of scan data.
bits of SCAN data.
..
. Therefore, 391 sets
of 192 bits are
needed for a total of
391x192 = 75,072 raw
data bits.

..
.
In this example, only 72 out of
Start of data for Calculating the number of lost bits:
75,072 bits are not used.
the next scan =192-3*mod(25000,4*16) = 72
This is a negligible (<1%) loss.
vector loop.
 FLEX
SCAN Data Broadcast (1-Chain Example)
NOTE: This slide is best understood when viewed in color.
Site 0 Site 1 Site 2 Site 3 Site 4 Site 5 Site 6 Site 7

Pin
Electronics

Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
Formatters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 50
LVM/ADB MHz
ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB
ADB
Select
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
Parallel
Vector
Data Bus
(16x3 = 48 bits)
48
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
ADB
Bit Select 1,2 3 1,2 3 1,2 3 1,2 3 1,2 3 1,2 3 1,2 3 1,2 3

28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28
Alternate
Data 28
Bus
(28 bits) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

1 48
The SCAN data is shared across several
Vector Parallel channels. Effectively, each channel has the
Memory Data 50
(64Mx48 = 3G bits) ..
ability to “tune-into” any ADB bits. In this
example, each red-blue channel pair, MHz
Scan represents the same scan chain data across
Data
8 different device test sites.
 FLEX
SCAN Data Broadcast (1-Chain Example)
NOTE: This slide is best understood when viewed in color.
I’ve omitted sites from here because it gets messy when the per-site scan channels are not adjacent to each other.

Pin
Electronics

Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch Ch
Formatters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 50
LVM/ADB MHz
ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB

ADB
ADB
Select
For simplicity, previous examples have illustrated scan channels in pairs
3 3 3 3 3 3 3 of scan-in
3 and3scan-out
3 channels.
3 In3general,3 this is 3not necessary.
3 3
Parallel This slide illustrates, how data is mapped to individual channels is
Vector determined by the IG-XL ADB Resource Manager based on the DIB
Data Bus wiring described in the test program’s Channel Map.
(16x3 = 48 bits)
48
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
ADB
Bit Select 1,2 1,2 1,2 1,2 3 3 3 3 1,2 3 1,2 3 1,2 3 1,2 3

28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28
Alternate
Data 28
Bus
(28 bits) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

1 48
Vector Parallel
Memory Data 50
(64Mx48 = 3G bits) .. MHz
Scan
Data
FLEX
More about SCAN Broadcast
SCAN Data Broadcast:
• IG-XL handles broadcast automatically based on the DIB
wiring described in the Channel Map.
• Can use VBT to disable SCAN Broadcast (This is also
available for the J750)
• VBT Code:
(See J750 IG-XL documentation / Contact Bruce Norskog)
• When disabled, more ADB resources are used (one set per site).
So, maximum scan depth per site will be reduced and maximum
data rate will also be reduced.
FLEX
Now Consider 3 SCAN Regions

• So far, we have discussed what goes on within a single, 16-

channel SCAN Region.

• However, each HSD200 offers 3 16-channel SCAN regions.

• So, when dividing SCAN resources across channel scan

pins should be divided across all three SCAN regions.

• Another simplification that we’ve made is to keep scan-in

and scan-out channels for a given scan chain paired to the
same SCAN region. There is no technical reason to do this.

• In general, up to 16 scan-in or scan-out (or a combination of

scan-in and scan-out) pins can be assigned to each SCAN
channel region.
FLEX
SCAN Stride Loss
Stride Efficiency & Stride Loss:
SCAN Bit Loss Stride Stride
Stride Per Chunk Efficiency Loss Stride Efficiency:
 (48 mod(k data _ rate × N scan _ bits _ per _ cycle )) 
0 0 100% 0%
1 0 100% 0%
2 0 100% 0% η stride =  
3 0 100% 0%
 48 
4 0 100% 0%
5 3 94% 6%

= (1 − η stride )
6 0 100% 0%
7 6 88% 13% Stride Loss:
8 0 100% 0%
9 3 94% 6%
10 8 83% 17%
11 4 92% 8%
12 0 100% 0%
13
14
9
6
81%
88%
19%
13%
From the table, it is apparent that
15 3 94% 6% Stride Loss can be minimized
16 0 100% 0%
17 14 71% 29% when SCAN Stride is minimized
18 12 75% 25%
19 10 79% 21% and/or an even number value.
20 8 83% 17%
21 6 88% 13%
22 4 92% 8%
23 2 96% 4% Do this by minimizing the number
24
25
0
23
100%
52%
0%
48%
of scan channels assigned to
26 22 54% 46% each SCAN Region.
27 21 56% 44%
28 20 58% 42%
FLEX
Additional SCAN Data “Loss”
• Normally, Stride loss is the dominant loss
• Depends on number of cycles per scan vector loop.
• This will vary between devices and test programs
• So, unlike SCAN Stride loss, we cannot spec this out before
hand.

• This loss is negligible under the following assumptions:

1. The number of scan cycles per scan vector is greater than 500
2. OR
3. When the SCAN stride does not divide evenly into 48, Stride

• Even if the per scan loop loss is high, the overall loss is
negligible so long as the number of scan loops is less than
10,000 or so
• Worst-case Example: Lose 191 raw bits per scan loop.
So:
100 scan loops Æ 19.1 K bits loss (6.4 K single-chain cycles)
1000 loops Æ 191 K bits loss (64 K single-chain cycles)
10 000 l Æ 1 9 M bit l (640 K i l h i l )
FLEX
Optimizing SCAN Configurations

Given our knowledge of SCAN Stride and Stride Loss, we

can develop an effective methodology for optimizing
Flex SCAN capabilities to meet specific DFT Scan Test
requirements.

Channel Allocation Rule of Thumb:

“Evenly distribute the number of scan-in and scan-out
channels across all available SCAN regions.”
REMEMBER: 3 SCAN regions per Channel Board.

To determine the results of SCAN channel allocation, the

previously discussed concepts can be rolled into a
handful of mathematical relationships.
FLEX
SCAN Resource Accounting

Scan Depth Expression

N raw _ bits
Dscan = (1 − η stride )× [Megacycles] LVM Used for Parallel Data
(In Megacycles)
N scan _ bits _ per _ cycle
Number of Scan In Channels
(Requires 1-bit per cycle)
N raw _ bits = 3 × 16 × (64 − D parallel ) [Megabits]
Number of Scan Out Channels
(Require 2-bits per cycle)
N scan _ bits _ per _ cycle = 1 × N scan _ in + 2 × N scan _ out [Bits per cycle]

 (48 mod(k data _ rate × N scan _ bits _ per _ cycle )) 

Stride Efficiency Factor

η stride =  
 48 
If Single Mode (50 MHz) : k data _ rate = 1
Higher Data Rates
If Dual Mode (100 MHz) : k data _ rate = 2 require more ADB bits

If Quad Mode (200 MHz) : k data _ rate = 4

Resource Constraints : 28-bit ADB width

k data _ rate × N scan _ bits _ per _ cycle ≤ 28
16 channels per SCAN Instrument
N scan _ in + N scan _ out ≤ 16 (3 SCAN Instruments per channel board)
FLEX
SCAN Resource Accounting

All-in-one Scan Depth Calculation

 (48 mod(k data _ rate (1 × N scan _ in + 2 × N scan _ out )))   48 × (64 − D parallel ) 
Dscan = 1 −  ×   [Megacycles]
48  (1 × N + 2 × N ) 
   scan _ in scan _ out 

If Single Mode (50MHz) : k data _ rate = 1

If Dual Mode (100MHz) : k data _ rate = 2
If Quad Mode (200MHz) : k data _ rate = 4

Resource Constraints :
k data _ rate (1× N scan _ in + 2 × N scan _ out ) ≤ 28
N scan _ in + N scan _ out ≤ 16
FLEX
Accounting Results

For a Single SCAN Instrument

Not really a practical use case since every digital channel
board has three SCAN instruments readily available. If
you use the Rule of Thumb mentioned earlier, you will
use each available SCAN instrument.

So, we will move on to the accounting results for a Flex

Channel Board (3 SCAN instruments).

(Calculating the Depth/Data Rate results for a single SCAN

instrument is an exercise that you may attempt on your
own.)
FLEX
Accounting Results

Accounting Results for a single Flex Channel Board

These results are more practical since scan channels are
spread across all three SCAN instruments.

Number of Scan Chain Depth Max Data Rate

Chains (M cycles) (M cycles/sec)
1, 2 1,536 200
3 1,024 200
4 768 200 NOTE:
5 576 50 Several configurations allow
a trade-up in speed at the
5,6 512 200 cost of scan depth.
7 256 200
7,8 384 100
9 256 100
9 320 50
10,11,12 256 100
13,14 128 100
13,14,15,16 192 50
17 to 24 128 50

Feel free to derive the results yourself.

FLEX
Using Your Knowledge

Now you understand Flex SCAN concepts...

You know the results for a single board…

How do you apply this knowledge?

Teradyne has created a spreadsheet-based tool to

help users manage the SCAN resource accounting
and quickly derive an optimal channel
configuration.
FLEX

The End
FLEX

Back Up
FLEX
Implication From Moore’s Law

"Rent's Rule" vs "Moore's Law" - The Gap Widens

1200 1200

1000 Pins 1000

Internal "Gates"
Relative Pin Count

800 800

"Relative Gates"
“The Gap” is driving the
600 need for scan on devices 600

with 500K gates and up

"The Gap"
400 400

200 200

0 0
1 2 3 4 5 6 7 8 9 10
Generations of Devices (18 month steps)
FLEX
Different Approaches
DUT with Narrow Scan DUT with Wide Scan

Scan Done Done

Clock

• Narrow scan takes longer to test but requires fewer pins

• Wide scan has shorter test times but requires more pins
FLEX
Scan Data Volume

Total Scan Data Volume Number of scan-in and scan-out pairs. (They often
= Number of Scan Chains come in pairs. One pair per chain.)
Usually this is the number of scan cycles per scan
x Length of Longest Chain vector loop
x Number of Scan Patterns This is the total number of scan vector loops. (A
pattern file will normally have many.)

According to the ITRS 2001 ATE Requirements Roadmap:

Scan Data Volume Requirement To calculate the required ATE scan pattern
2001 – 2002: 6 G depth, these data volume values need to
be divided by the number of scan chains!
2003 – 2004: 12 G
2005 – 2007: 16 G Keep this in mind when assessing
Customer scan depth requirements.

This does not necessarily equal to required ATE per-pin pattern depth!

To meet test time requirements, Customers will most likely use more
scan chains and/or internally decompressed/compressed scan chains.
FLEX
LVM Data to Parallel Channels

Parallel Pattern Data

Four 48-bit chunks of channel data accessed from LVM.
Each chunk is a single cycle’s worth of pin data for 16 channels.
Before the beginning of each cycle, per-channel data sent to
Format/Compare subsystem.

Example: 1 chain, 1 site, Single Mode (50 MHz)

FLEX
SCAN Data Across the ADB

SCAN Pattern Data

Four 48-bit chunks of channel data accessed from LVM.
Each chunk may be divided into several cycles and several
channels worth of SCAN data.
Before the beginning of each cycle, per-chain SCAN data sent
to Format/Compare Subsystem via the ADB.

Example: 1 chain, 1 site, Single Mode (50 MHz)