Processor Organization and Architecture

Processor Organization and Architecture

• CPU Architecture, Register Organization, Instruction cycle,
Instruction Formats
• Control Unit Design- Hardwired and Micro-programmed
Control: Vertical and Horizontal Micro-Instructions,
Nano-programming
• Comparison between CISC and RISC architectures
Processor Role
 System level
• At the system level, the processor is the major subsystem of a
computer. It has two functions:
• Program execution (performing instruction cycle): This involves a
variety of data operations such as data processing, data storage,
and data movement.
• Interfacing with other subsystems
such as Main memory, Cache
memory, DMA controller, I/O
controllers, etc. The processor has
the responsibility of overall
coordination of
intercommunication between
these subsystems. This is usually
done through a bus structure
 Architecture Level
• At the architecture level, the processor consists of program
addressable hardware resources for the instruction set such as such
as program counter, accumulator, operand registers, stack,
interrupt vectors, status flags, etc.
• Each instruction specifies a
major role known as
macro-operation.
• The exact macro-operation for
an instruction is indicated in the
opcode portion.
 Register Transfer Level
• At the register transfer level, the processor has a set of digital
modules such as registers, adders, counters, multiplexors,
decoders, flip–flops, etc. each performing one or more specific
functions.
• Each macro-operation involves one or
more register transfer operations.
• For example, a MOVE macro-operation
(i.e. moving the data from the memory
location to the register) needs two
register transfer operations memory
read and register transfer.
 Gate Level
• At the gate level, the processor consists of hardware circuits which
perform the microoperations.
• In many practical cases, there is an overlap between register
transfer level and gate level due to the usage of LSIs and VLSIs.
 Processor Design Goals
• The overall goal in designing a processor is to meet the needs of
the instruction set.
• This involves designing appropriate hardware so that all
macro-operations are executed accurately as per the requirements
of the instructions.
• The designer has to
consider certain other
factors that are
responsible for the
success or failure of the
processor in the
commercial market.
• A low cost processor with a single bus structure and limited
hardware registers and other resources? or
• A high performance processor with multiple bus and extensive
resources and / or parallelism?
• The extent of design varies with the type of processor
 Processor Design Process
• The design of a processor follows a series of steps each involving
a different level of design activity.
• Some of the steps are interdependent and hence require some
amount of back and forth travel.
• Identifies the input and output of the processor design activity.
• There are two kinds of input.
• The first one is finalized by the computer architect.
• It includes the instruction set description and operand formats.
• The second one serve as a knowledge base.
• It includes the details of various algorithms, functions and
behavior of different hardware components, and knowledge on
different design techniques.
• The designer should evaluate the usefulness and limitations of the
options available in each of these and pick the appropriate ones.
• The dictionary of the hardware components keeps growing due to
new inventions and developments.
• The designer should have a clear idea about the latest and obsolete
components so as to come out with a state-of-the art design.
• The processor is functionally divided into
data path and control unit. Figure shows
the
• interface between these two units.
• This interface is implemented in a low
cost processor with a single bus.
• The same bus acts as an internal bus
inside the data path.
• In a medium performance based
processor, two internal busses are
included whereas, a high performance
processor has three internal busses.
• Physically there is hardly any difference
between the data path and control unit. In
a contemporary computer, the hardware
of both the units are tightly coupled
(integrated) in a single physical module as
compared to the earlier main frame
computers.
 Processor Design Steps
• The design of a processor is described in the following sequence of steps as
indicated below:
– Understand each instruction clearly. Define the macro-operation in terms of the
given computer architecture.
– Identify the hardware resources needed (to implement the macro-operation) in
terms of programmer visible hardware items (registers, flags, stack etc.).
– Translate each macro-operation as one or more register transfer operations.
– Design the data path (starting with the resources identified in step 2) required
for performing the register transfer operations and identify the control points.
Analyze whether the data path circuits can be reduced by combining the
designs for various instructions, eliminating redundant circuits.
– List the timing sequence of control signals required to activate the control
points.
 Register Transfer Language (RTL)
• The RTL is a notation used to specify the micro-operation transfer
between the registers.
• It is a tool used for describing the behavior of the instructions.

• For example, the RTL statement R3: = R1

indicates a simple register transfer
involving two registers R1 and R3.
• The action described by this statement
is—the contents of the register R1 are
transferred (copied) to the register R3.
• The same RTL statement can be also
written as R3 ← R1.
• The micro-operations are classified into four types:
– Register transfer micro-operations : transfer (copy) the contents
of one register to another register without any change in
contents.
– Arithmetic micro-operations : perform the arithmetic
operations on data present in the register: addition, subtraction,
increment, decrement and shift are common arithmetic micro-
operations.
– Logic micro-operations : perform the bit manipulation
operations on data available in registers. These
micro-operations consider each bit as a separate binary
variable. They are used for making logical decisions and also
for bit manipulation of the binary data. The following special
symbols are used for some of the logic micro-operations:

– Shift micro-operations : perform the shift operations on data

held in registers. These are of three types: logical shift
operations, circular shift operations and arithmetic shift
operations.
– In logical shift, all bits (including sign bit) take part in shifting
operation. A ‘0’ is entered in the vacant extreme bit (left most
or right most) position.

– In circular shift, the bit shifted out from one extreme bit
position enters the other extreme side. It is also known as
‘rotate’ operation.
– In arithmetic shift, sign bits remain unaffected and other bits
take part in shift operation
 Datapath Organization
• The term datapath includes the following hardware components:
– ALU.
– Registers for temporary storage.
– Various digital circuits for executing different
micro-operations. These include hardware components such as
gates, latches, flip–flops, multiplexers, decoders, counters,
complementer, delay logic etc.
– Internal path for movement of data between ALU and registers.
– Driver circuits for transmitting signals to external units (control
unit, memory, I/O).
– Receiver circuits for incoming signals from external units.
 INSTRUCTION CYCLE
• An instruction cycle includes the following stages:
• Fetch: Read the next instruction from memory into the
processor.
• Execute: Interpret the opcode and perform the indicated
operation.
• Interrupt: If interrupts are
enabled and an interrupt has
occurred, save the current
process state and service the
interrupt.
 The Indirect Cycle
• The execution of an instruction may involve one or more operands
in memory, each of which requires a memory access.
• Indirect addressing is used, then additional memory accesses are
required.
• The main line of activity consists of alternating instruction fetch
and instruction execution activities.
• After an instruction is fetched, it is examined to determine if any
indirect addressing is involved.
• If so, the required operands are fetched using indirect addressing.
• Following execution, an interrupt may be processed before the
next instruction fetch.
• This illustrates more correctly the nature of the instruction cycle.
• Once an instruction is fetched, its operand specifiers must be
identified.
• Each input operand in memory is then fetched, and this process
may require indirect addressing.
• Register-based operands need not be fetched.
• Once the opcode is executed, a similar process may be needed to
store the result in main memory.
 Data Flow
• The exact sequence of events during an instruction cycle depends on
the design of the processor.
• Let us assume that a processor that employs a memory address register
(MAR), a memory buffer register (MBR), a program counter (PC), and
an instruction register (IR).
• During the fetch cycle, an instruction is read from memory.
• The PC contains the address of the next instruction to be fetched.
• This address is moved to the MAR and placed on the address bus.
• The control unit requests a memory read, and the result is placed on the
data bus and copied into the MBR and then moved to the IR.
Meanwhile, the PC is incremented by 1, preparatory for the next fetch.
• Once the fetch cycle is over, the control unit examines the contents of
the IR to determine if it contains an operand specifier using indirect
addressing.
• If so, an indirect cycle is performed.
• The rightmost N bits of the MBR, which contain the address reference,
are transferred to the MAR.
• Then the control unit requests a memory read, to get the desired
address of the operand into the MBR.
• The fetch and indirect cycles are simple and predictable.
• The execute cycle takes many forms; the form depends on which of the
various machine instructions is in the IR.
• This cycle may involve transferring data among registers, read or write
from memory or I/O, and/or the invocation of the ALU.
• Like the fetch and indirect cycles, the interrupt cycle is simple and
predictable.
• The current contents of the PC must be saved so that the processor can
resume normal activity after the interrupt.
• Thus, the contents of the PC are transferred to the MBR to be written
into memory.
• The special memory location reserved for this purpose is loaded into
the MAR from the control unit.
• It might, for example, be a stack pointer.
• The PC is loaded with the address of the interrupt routine.
• As a result, the next instruction cycle will begin by fetching the
appropriate instruction.
 Control Unit Design
• If we know the machine instruction set, including an understanding of
the effect of each opcode and an understanding of the addressing
modes, and if we know the set of user-visible registers, then we know
the functions that the processor must perform.
• This is not the complete picture.
• We must know the external interfaces, usually through a bus, and how
interrupts are handled.
• With this line of reasoning, the following list of those things needed to
specify the function of a processor emerges:
1. Operations (opcodes)
2. Addressing modes 5. Memory module interface
3. Registers 6. Interrupts
4. I/O module interface
• Items 1 through 3 are defined by the instruction set.
• Items 4 and 5 are typically defined by specifying the system bus.
• Item 6 is defined partially by the system bus and partially by the type
of support the processor offers to the operating system.
 Hardwired Implementation
• A wide variety of techniques have been used.
• Most of these fall into one of two categories:
– Hardwired implementation
– Microprogrammed implementation
• In a hardwired implementation, the control unit is essentially a
state machine circuit.
• Its input logic signals are transformed into a set of output logic
signals, which are the control signals.
Control Unit
 Control Unit Inputs
• The key inputs are the instruction register, the clock, flags, and
control bus signals.
• In the case of the flags and control bus signals, each individual bit
typically has some meaning (e.g., overflow).
• The other two inputs, however, are not directly useful to the
control unit.
• First consider the instruction register.
• The control unit makes use of the opcode and will perform
different actions (issue a different combination of control signals)
for different instructions.
• To simplify the control unit logic, there should be a unique logic
input for each opcode.
•
•
 Control Unit Logic
• To define the hardwired implementation of a control unit, the
internal logic of the control unit that produces output control
signals as a function of its input signals.
• Essentially, what must be done is, for each control signal, to derive
a Boolean expression of that signal as a function of the inputs.
• This is best explained by example.
• Let us consider a single control signal, C5.
• This signal causes data to be read from the external data bus into
the MBR.
• We can see that it is used twice in Table
• Let us define two new control signals, P and Q, that have the
following interpretation:
– PQ = 00 Fetch Cycle
– PQ = 01 Indirect Cycle
– PQ = 10 Execute Cycle
– PQ = 11 Interrupt Cycle
• Then the following Boolean expression defines C5:

• That is, the control signal C5 will be asserted during the second
time unit of both the fetch and indirect cycles.
• This expression is not complete.
• C5 is also needed during the execute cycle.
• For our simple example, let us assume that there are only three
instructions that read from memory: LDA,ADD, and AND.
• Now we can define C5 as

• This same process could be repeated for every control signal

generated by the processor.
• The result would be a set of Boolean equations that define the
behavior of the control unit and hence of the processor.
• To tie everything together, the control unit must control the state
of the instruction cycle.
• As was mentioned, at the end of each subcycle (fetch, indirect,
execute, interrupt), the control unit issues a signal that causes the
timing generator to reinitialize and issue T1.
• The control unit must also set the appropriate values of P and Q to
define the next subcycle to be performed.
• The reader should be able to appreciate that in a modern complex
processor, the number of Boolean equations needed to define the
control unit is very large.
• The task of implementing a combinatorial circuit that satisfies all
of these equations becomes extremely difficult.
• The result is that a far simpler approach, known as
microprogramming, is usually used.