DLD LAB

REPORT

Name : Chandra Sekhar U

Reg.no : 23BCE9222
Slot :L2+L3
Faculty : Dr.Agam Das Goswami
Verification of Gates in Data flow , behavioural
and gate-level modelling.

AND GATE
Data flow:
Testbench code

module and_gate_tb;

reg A;

reg B;

wire Y;

integer i;

and_gate inst(.A(A),.B(B),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;
 #10;

end

end

endmodule

Design
module and_gate(

input A,

input B,

output Y);

assign Y=A&&B;

endmodule

Behavioral:
Testbench code

module and_gate_tb;

reg A;

reg B;

wire Y;

integer i;

and_gate inst(.A(A),.B(B),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)
 begin

{A,B}=i;

#10;

end

end

endmodule

Design
module and_gate(

input A,

input B,

output Y);

always @(A or B)

begin

if (A==0 & B==0);

Y=0

else if (A==0 & B==1);

Y=0

else if (A==1 & B==0);

Y=0

else (A==1 & B==1);

Y=1

end

endmodule

Gate Level Modeling:

Testbench code
module and_gate_tb;

reg A;

reg B;

wire Y;

integer i;

and_gate inst(.A(A),.B(B),.Y(Y));
initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;

end

end

endmodule

Design
module and_gate(

input A,

input B,

output Y);

and g2(Y,A,B,)

endmodule
 OR GATE
Data flow:
Testbench code
module or_gate_tb;

reg A;

reg B;

wire Y;

integer i;

or_gate inst(.A(A),.B(B),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;

end

end
endmodule

Design
module or_gate(

input A,

input B,

output Y);

assign Y=A||B;

endmodule

Behavioral:
Testbench code
module or_gate_tb;

reg A;

reg B;

wire Y;

integer i;

or_gate inst(.A(A),.B(B),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;
 end

end

endmodule

Design
module or_gate(

input A,

input B,

output Y);

always @(A or B)

begin

if (A==0 ; B==0);

Y=0

else if (A==0 ; B==1);

Y=1

else if (A==1 ; B==0);

Y=1

else (A==1 ; B==1);

Y=1

end

endmodule

Gate Level Modeling:

Testbench code
module or_gate_tb;

reg A;

reg B;

wire Y;

integer i;

or_gate inst(.A(A),.B(B),.Y(Y));
initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;

end

end

endmodule

Design
module or_gate(

input A,

input B,

output Y);

or g2(Y,A,B,)

endmodule
 NOT GATE

Data flow:
Testbench code
module not_gate_tb;

reg A;

wire Y;

integer i;

not_gate inst(.A(A),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

$monitor ("A=%0b Y=%0b",A,Y);

for (i=0;i<2;i=i+1)

begin

{A}=i;

#10;

end

end

endmodule

Design
module not_gate(
 input A,

output Y

);

assign Y = ~A;

endmodule

Behavioral:
Testbench code

module not_gate_tb;

reg A;

wire Y;

integer i;

not_gate inst(.A(A),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

$monitor ("A=%0b Y=%0b",A,Y);

for (i=0;i<2;i=i+1)

begin

{A}=i;

#10;

end

end

endmodule

Design
module not_gate (A, Y);
input A;

output Y;

not n1(Y,A);

endmodule

Gate Level Modeling:

Testbench code
module not_gate_tb;

reg A;

wire Y;

integer i;

not_gate inst(.A(A),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

$monitor ("A=%0b Y=%0b",A,Y);

for (i=0;i<2;i=i+1)

begin

{A}=i;

#10;

end

end

endmodule

Design
module not_gate(A,Y);

input A;

output reg Y;
 always @(A)

begin

if ( A ==0)

y = 1;

else

y = 0;

end

endmodule
 NAND GATE
Data flow:
Testbench code

module nand_gate_tb;

reg A;

reg B;

wire Y;

integer i;

nand_gate inst(.A(A),.B(B),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;

end

end

endmodule

Design
module nand_gate(
input A,

input B,

output Y);

assign Y=~(A&&B);

endmodule

Behavioral:
Testbench code

module nand_gate_tb;

reg A;

reg B;

wire Y;

integer i;

nand_gate inst(.A(A),.B(B),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;

end

end
endmodule

Design
module nand_gate(

input A,

input B,

output Y);

always @(A or B)

begin

if (A==0 ; B==0);

Y=0

else if (A==0 ; B==1);

Y=1

else if (A==1 ; B==0);

Y=1

else (A==1 ; B==1);

Y=0

end

endmodule

Gate Level Modeling:

Testbench code
module nand_gate_tb;

reg A;

reg B;

wire Y;

integer i;

nand_gate inst(.A(A),.B(B),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;
end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;

end

end

endmodule

Design
module nand_gate(

input A,

input B,

output Y);

nand g2(Y,A,B,)

endmodule
 NOR GATE

Data flow:
Testbench code

module nor_gate_tb;

reg A;

reg B;

wire Y;

integer i;

nor_gate inst(.A(A),.B(B),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;

end

end

endmodule
Design
module nor_gate(

input A,

input B,

output Y);

assign Y=~(A||B);

endmodule

Behavioral:
Testbench code

module nor_gate_tb;

reg A;

reg B;

wire Y;

integer i;

nor_gate inst(.A(A),.B(B),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;
 end

end

endmodule

Design
module nor_gate(

input A,

input B,

output Y);

always @(A or B)

begin

if (A==0 ; B==0);

Y=0

else if (A==0 ; B==1);

Y=1

else if (A==1 ; B==0);

Y=1

else (A==1 ; B==1);

Y=0

end

endmodule

Gate Level Modeling:

Testbench code
module nor_gate_tb;

reg A;

reg B;

wire Y;

integer i;

nor_gate inst(.A(A),.B(B),.Y(Y));

initial begin
 $dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;

end

end

endmodule

Design
module nor_gate(

input A,

input B,

output Y);

nor g2(Y,A,B,)

endmodule
 XOR GATE
Data flow:
Testbench code
module xor_gate_tb;

reg A;

reg B;

wire Y;

integer i;

xor_gate inst(.A(A),.B(B),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;

end

end

endmodule

Design
module xor_gate(

input A,

input B,

output Y);

assign Y=A^B;
endmodule

Behavioral:
Testbench code
module xor_gate_tb;

reg A;

reg B;

wire Y;

integer i;

xor_gate inst(.A(A),.B(B),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;

end

end

endmodule

Design
module xor_gate(

input A,

input B,

output Y);

always @(A or B)
 begin

if (A==0 ; B==0);

Y=0

else if (A==0 ; B==1);

Y=1

else if (A==1 ; B==0);

Y=1

else (A==1 ; B==1);

Y=0

end

endmodule

Gate Level Modeling:

Testbench code

module xor_gate_tb;

reg A;

reg B;

wire Y;

integer i;

xor_gate inst(.A(A),.B(B),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

 for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;

end

end

endmodule’

Design
module xor_gate(

input A,

input B,

output Y);

xor g2(Y,A,B,)

endmodule
 XNOR GATE

Data flow:
Testbench code

module xnor_gate_tb;

reg A;

reg B;

wire Y;

integer i;

xnor_gate inst(.A(A),.B(B),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;

end

end

endmodule

Design
module xnor_gate(
input A,

input B,

output Y);

assign Y=~(A^B);

endmodule

Behavioral:
Testbench code

module xnor_gate_tb;

reg A;

reg B;

wire Y;

integer i;

xnor_gate inst(.A(A),.B(B),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end

initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;

end

end

endmodule
Design
module xnor_gate(

input A,

input B,

output Y);

always @(A or B)

begin

if (A==0 ; B==0);

Y=0

else if (A==0 ; B==1);

Y=1

else if (A==1 ; B==0);

Y=1

else (A==1 ; B==1);

Y=0

end

endmodule

Gate Level Modeling:

Testbench code
module xnor_gate_tb;

reg A;

reg B;

wire Y;

integer i;

xnor_gate inst(.A(A),.B(B),.Y(Y));

initial begin

$dumpfile("dump.vcd");

$dumpvars;

#100 $finish;

end
initial

begin

A<=0;

B<=0;

$monitor ("A=%0b B=%0b Y=%0b",A,B,Y);

for (i=0;i<4;i=i+1)

begin

{A,B}=i;

#10;

end

end

endmodule

Design
module xnor_gate(

input A,

input B,

output Y);

xnor g2(Y,A,B,)

endmodule

AND OR NOT NAND NOR XOR XNOR

GATES