MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.

MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.

MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
 2. MOS INVERTERS
 metal–oxide–semiconductor (MOS) transistor can be considered as a
voltage-controlled resistor -Basic property to realize digital circuits
.
 Different inverter configurations that can be realized using the four
types of metal–oxide–semiconductor field-effect transistors
(MOSFETs).
 Gate-based inverters and switch-based inverters are Two different
types of electronic circuits used for inverting the input signal,
typically from a logic high to a logic low or vice versa. They have
distinct characteristics and applications:

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  Inverter forms the basic building block
of gate-based digital circuits.
 An inverter can be realized with the
Gate-based
source of an ntype metal–oxide–
semiconductor (nMOS) enhancement
transistor connected to the ground, and
the drain connected to the positive supply
rail Vdd through a pull-up device.
Switch-based

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 Initially, output is Vdd when the
input is 0 V, and as the input crosses
Vdd/2, the output switches to 0 V,
and it remains at this level till the
maximum input voltage Vdd.

Ideal transfer characteristics of an inverter

The input voltage, Vdd/2, at which the output changes from high ‘1’ to
low ‘0’, is known as inverter threshold voltage.

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For the low input voltage level ,Because of
some voltage drop across the pull-up
device, the out-put high voltage level is less
than Vdd . This voltage is represented by VOH,
which is the maximum output voltage level
for output level ‘1’.
As the input voltage increases and crosses the
threshold voltage of the pull-down transistor,
it starts conducting, which leads to a decrease
in the output voltage level. However, instead
of an abrupt change in the voltage level from
logic level ‘1’ to logic level ‘0’, the voltage
decreases rather slowly.
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 1. The unity gain point at which in dV0 /
dVin = −1 is defined as the input high
voltage VIL, which is the maximum input
voltage which can be treated as logic level
‘0’.
2. As the input voltage is increased
further, the output crosses a point where
Vin = Vout.The voltage at which this
Various voltage levels on the occurs is referred to as the inverter
transfer characteristics
threshold voltage VT.

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For practical inverters inverter threshold
voltage may not be equal to Vdd/2.

Before the output attains the output low

voltage VOL, which is the minimum output
voltage for output logic level ‘0’, the
transfer-characteristic curve crosses another
important point VIH, the minimum input
voltage that can be accepted as logic ‘1’.This
point is also obtained at another unity gain
point at which dV0 / dVin = −1

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MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
NOISE MARGIN : It is defined as the allowable noise voltage on
the input of a gate so that the output is not affected.

Is a measure of the immunity of a digital circuit to noise, specifically

in terms of its ability to tolerate variations in the input voltage levels
without causing incorrect logic states.

Two types of noise margins in MOSFET circuits

1.High Noise Margin (NMH )
2. Low Noise Margin (NML )

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1.High Noise Margin (NMH ):
Defined as the difference in
magnitude between the minimum
high output voltage of the driving
gate and the minimum voltage
acceptable as high level by the
driven gate.

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 Low Noise Margin (NML ):
The low-level noise margin is
defined as the difference in
magnitude between the
minimum low output voltage
of the driving gate and the
maximum input low voltage
accepted by the driven gate.

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Designers aim to have large noise margins to make digital circuits
robust against noise and variations in supply voltage. A larger noise
margin provides better noise immunity, ensuring that the circuit
operates correctly even in less-than-ideal conditions.

Designers can optimize noise margins by carefully selecting the

threshold voltage levels of the transistors, controlling transistor
sizing, and considering various factors like power supply voltage,
temperature, and process variations that can affect the noise margin
of the circuit.

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 Passive Resistive as Pull-up Device
1. At point x 𝑉𝑖𝑛 = 0
z
𝑉𝑜𝑢𝑡 = 𝑉𝑑𝑑 −Cut-off region
y

x 2. At point y 𝑉𝑖𝑛 > 𝑉𝑡𝑛

𝑉𝑜𝑢𝑡 = 0 ≤ 𝑉𝑜 < 𝑉𝑑𝑑 --
Saturation

3. At point z 𝑉𝑖𝑛 = 𝑉𝑑𝑑

𝑉𝑜𝑢𝑡 = 𝑉𝑜𝑙 ---Active
a An nMOS inverter with resistive load; region
b voltage–current characteristic;
c transfer characteristic. nMOS n-type–metal–oxide semiconductor

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 A passive resistor 𝑅𝐿 can be used as the pull-up device.
 Value of the resistor should be chosen such that the circuit
functionally behaves like an inverter.
 When the input voltage Vin is less than Vtn, the transistor is OFF
and the output capacitor charges to Vdd. Therefore, we get Vdd as
the output for any input voltage less than Vtn.
 When Vin is greater than Vtn, the MOS transistor acts as a
resistor Rc, where Rc is the channel resistance with Vgs > Vtn.
The output capacitor discharges through this resistor and output
𝑅𝐶
voltage is given by 𝑉𝑂𝐿 = 𝑉𝑑𝑑
𝑅𝐶 +𝑅𝐿

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Normally, this output is used to drive other gates.
This voltage can be accepted as low level provided it is less than Vt.
So,
𝑅𝐶
𝑉𝑂𝐿 = 𝑉𝑑𝑑 < 𝑉𝑡𝑛
𝑅𝐶 + 𝑅𝐿

With typical value of threshold voltage Vtn =0.2 Vdd

𝑅𝐶
𝑉𝑂𝐿 = 𝑉𝑑𝑑 < 𝑉𝑡𝑛 =0.2 Vdd or 𝑅𝐿 > 4𝑅𝐶
𝑅𝐶 +𝑅𝐿
Imposes a restriction on the minimum value of load resistance for a
successful operation of the circuit as an inverter.

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implementation of this inverter has a number of disadvantages:
1. As the charging of the output capacitor takes place through the
load resistor RL and discharge through Rc and their values must
be different as per Eq, there is asymmetry in the ON-to-OFF
and OFF-to-ON switching times.
2. To have higher speeds of operation, the value of both Rc and
RL should be reduced. However, this increases the power
dissipation of the circuit. Moreover, as we shall see later, to
achieve a smaller value of Rc, the area of the MOS inverter
needs to be increased.

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Resistive load can be fabricated by two approaches
1. using a diffused resistor approach
2. using an undoped poly-silicon approach.
diffused resistor approach To realize resistor of the order of K Ω,
length to width must be large in a small area, a serpentine form is used
this requires a very large chip area.
Undoped poly-silicon approach Leads to a
very compact resistor compared to the previous
approach, the resistance value cannot be accurately
controlled leading to large process parameter
variations. In view of the above discussion, it is
evident that this inverter configuration is not
suitable for VLSI realization.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
Disadvantages

Asymmetry in the ON-to-OFF and OFF-to-ON switching times

Large Static power dissipation
Requires a very large chip area
Unsuitable for VLSI realization
Strong High Output and Weak Low Output Level

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Four possible alternatives for pull-up devices—
1. an nMOS enhancement-mode transistor, a depletion-mode nMOS
transistor
2. an pMOS enhancement-mode transistor, a depletion-mode nMOS
transistor

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 2.nMOS Depletion-Mode Transistor as Pull up

a nMOS inverter with depletion-mode transistor as pull-up device; b

voltage current characteristic; c transfer characteristic. nMOS n-type
metal–oxide–semiconductor
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 output of an inverter is commonly connected to the gate of one or
more MOS transistors in the next stage, there is no fan-out current,
and the currents flowing through both the transistors must be equal.
The input voltage is applied to the gate of the pull-down (pd)
transistor, and the output is taken out from the drain of the pd device.

1. Pull-down device off and pull-up device in linear region: This

corresponds to point ‘A’ on the curve with the input voltage Vin < Vtn
,Vout = Vdd and Ids = 0 . In this situation, there is no current flow from
the power supply and no current flows through either of the transistors.

MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.

MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
4.3.3 nMOS Enhancement-Mode Transistor as Pull up

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MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MOS Inverter Configurations- pMOS Transistor as a Pull Up in
Complementary Mode

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 a pMOS enhancement type transistor is used as a pull-up device.
 Here the gates of both the pull-up and pull-down transistors are tied
together and used as input

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MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.
MAHABOOB SUBANI SHAIK ASST PROFESSOR IN ECE,BEC, BAPATLA.