ARCHITECTURE OF 8086

Introduction :
The 8086 microprocessor is an 16-bit microprocessor designed by Intel in the late 1970s. It is the first
member of the x86 families of microprocessors, which includes many popular CPUs used in personal
computers.
The architecture of the 8086 microprocessor is based on a complex instruction set computer (CISC)
architecture, which means that it supports a wide range of instructions, many of which can perform multiple
operations in a single instruction. The 8086 microprocessor has a 20-bit address bus, which can address up to
1 MB of memory, and a 16-bit data bus, which can transfer data between the microprocessor and memory or
I/O devices.
FUNCTIONAL UNITS: The 8086 microprocessor has two main execution units: the execution unit (EU)
and the bus interface unit (BIU). The BIU is responsible for fetching instructions from memory and decoding
them, while the EU executes the instructions. The BIU also manages data transfer between the
microprocessor and memory or I/O devices.

BUS INTERFACE UNIT (BIU):

a) Memory Segment Registers& IP:
b) Instruction Queue:

EXECUTION UNIT (EU):

a) General Purpose Registers
b) ALU
c) Flag Register (PSW)

PIN DIAGRAM OF 8086 MICROPROCESSOR

Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a 5V DC supply
for its operation. The 8086 uses a 20-line address bus. It has a 16-line data bus. The 20 lines of the
address bus operate in multiplexed mode. The 16-low order address bus lines have been multiplexed
with data and 4 high-order address bus lines have been multiplexed with status signals.
AD0-AD15: Address/Data bus. These are low order address bus. They are multiplexed with data.
When AD lines are used to transmit memory address the symbol A is used instead of AD, for example
A0-A15. When data are transmitted over AD lines the symbol D is used in place of AD, for example
D0-D7, D8-D15 or D0-D15.
A16-A19: High order address bus. These are multiplexed with status signals.
S2, S1, S0: Status pins. These pins are active during T4, T1 and T2 states and is returned to passive
state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the 8288 bus controller for
generating all the memory and I/O operation) access control signals. Any change in S2, S1, S0 during
T4 indicates the beginning of a bus cycle.
S2 S1 S0 Characteristics

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt
S2 S1 S0 Characteristics

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive state

A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with corresponding
status signals.

A17/S4 A16/S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

HE’/S7: Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most significant
half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE (Active Low)
signal. It is multiplexed with status signal S7. S7 signal is available during T2, T3 and T4.
RD’: This is used for read operation. It is an output signal. It is active when low.
READY : This is the acknowledgement from the memory or slow device that they have completed the
data transfer. The signal made available by the devices is synchronized by the 8284A clock generator
to provide ready input to the microprocessor. The signal is active high(1).
INTR : Interrupt Request. This is triggered input. This is sampled during the last clock cycles of each
instruction for determining the availability of the request. If any interrupt request is found pending, the
processor enters the interrupt acknowledge cycle. This can be internally masked after resulting the
interrupt enable flag. This signal is active high(1) and has been synchronized internally.
NMI : Non maskable interrupt. This is an edge triggered input which results in a type II interrupt. A
subroutine is then vectored through an interrupt vector lookup table which is located in the system
memory. NMI is non-maskable internally by software. A transition made from low(0) to high(1)
initiates the interrupt at the end of the current instruction. This input has been synchronized internally.
INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each interrupt acknowledge
cycle.
MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will operate in.
RQ’/GT1′, RQ’/GT0′ : Request/Grant. These pins are used by local bus masters used to force the
microprocessor to release the local bus at the end of the microprocessor’s current bus cycle. Each of the
pin is bi-directional. RQ’/GT0′ have higher priority than RQ’/GT1′.
LOCK’ : Its an active low pin. It indicates that other system bus masters have not been allowed to gain
control of the system bus while LOCK’ is active low(0). The LOCK signal will be active until the
completion of the next instruction.
TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will
continue, else the processor remains in an idle state. The input is internally synchronized during each of
the clock cycle on leading edge of the clock.
CLK : Clock Input. The clock input provides the basic timing for processing operation and bus control
activity. Its an asymmetric square wave with a 33% duty cycle.
RESET : This pin requires the microprocessor to terminate its present activity immediately. The signal
must be active high(1) for at least four clock cycles.
Vcc : Power Supply( +5V D.C.)
GND : Ground
QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction queue
according to the table shown below:
QS1 QS0 Status

0 0 No operation

0 1 First byte of op code from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

M/IO’: This signal is used to distinguish between memory and I/O operations. The M Signal is Active
high whereas the IO’ Signal is Active Low. When this Pin is High, the memory operations takes place.
On the other hand, when the Pin is low, the Input/Output operations from the peripheral devices takes
place.
=DT/R : Data Transmit/Receive. This pin is required in minimum systems, that want to use an 8286 or
8287 data bus transceiver. The direction of data flow is controlled through the transceiver.
DEN: Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum system
which uses transceiver. DEN is active low(0) during each memory and input-output access and for
INTA cycles.
HOLD/HOLDA: HOLD indicates that another master has been requesting a local bus .This is an
active high(1). The microprocessor receiving the HOLD request will issue HLDA (high) as an
acknowledgement in the middle of a T4 or T1 clock cycle.
ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address into the 8282
or 8283 address latch. It is an active high(1) pulse during T1 of any bus cycle. ALE signal is never
floated, is always integer.

PHYSICAL ADDRESS COMPUTATION

Each of segments: CS,DS, ES and SS are addressed by an address stored in corresponding segment register. The
20-bit address of a byte is called its physical address. These registers are of 16-bit in size. Each register stores
the base address (starting address) of the corresponding segment. Because the segment registers cannot store 20
bits, they only store the upper 16 bits. Logical address is in the form of:
Base Address + Offset = PHYSICAL ADDRESS
Offset is the displacement of the memory location from the starting location of the segment.

FLAG REGISTER OF 8086 MICROPROCESSOR

The Flag register is a Special Purpose Register. Depending upon the value of result after any arithmetic and
logical operation the flag bits become set (1) or reset (0).

Figure – Format of flag register There are total 9 flags in 8086 and the flag register is divided into two
types: (a) Status Flags – There are 6 flag registers in 8086 microprocessor which become set(1) or reset(0)
depending upon condition after either 8-bit or 16-bit operation. These flags are conditional/status flags. 5 of
these flags are same as in case of 8085 microprocessor and their working is also same as in 8085
microprocessor. The sixth one is the overflow flag. The 6 status flags are:
1. Sign Flag (S)
2. Zero Flag (Z)
3. Auxiliary Carry Flag (AC)
4. Parity Flag (P)
5. Carry Flag (CY)
These first five flags are defined here
6. Overflow Flag (O) – This flag will be set (1) if the result of a signed operation is too large to fit in the
number of bits available to represent it, otherwise reset (0). After any operation, if D[6] generates any
carry and passes to D[7] OR if D[6] does not generates carry but D[7] generates, overflow flag becomes
set, i.e., 1. If D[6] and D[7] both generate carry or both do not generate any carry, then overflow flag
becomes reset, i.e., 0. Example: On adding bytes 100 + 50 (result is not in range -128…127), so overflow
flag will set.
MOV AL, 50 (50 is 01010000 which is positive)
MOV BL, 32 (32 is 00110010 which is positive)
ADD AL, BL (82 is 10000010 which is negative)
1. Overflow flag became set as we added 2 +ve numbers and we got a -ve number.
(b) Control Flags – The control flags enable or disable certain operations of the microprocessor. There are 3
control flags in 8086 microprocessor and these are:
1. Directional Flag (D) – This flag is specifically used in string instructions. If directional flag is set (1),
then access the string data from higher memory location towards lower memory location. If directional
flag is reset (0), then access the string data from lower memory location towards higher memory location.
2. Interrupt Flag (I) – This flag is for interrupts. If interrupt flag is set (1), the microprocessor will
recognize interrupt requests from the peripherals. If interrupt flag is reset (0), the microprocessor will not
recognize any interrupt requests and will ignore them.
3. Trap Flag (T) – This flag is used for on-chip debugging. Setting trap flag puts the microprocessor into
single step mode for debugging. In single stepping, the microprocessor executes a instruction and enters
into single step ISR. If trap flag is set (1), the CPU automatically generates an internal interrupt after each
instruction, allowing a program to be inspected as it executes instruction by instruction. If trap flag is
reset (0), no function is performed.

Memory Segmentation in 8086 Microprocessor

Segmentation is the process in which the main memory of the computer is logically divided into different
segments and each segment has its own base address. It is basically used to enhance the speed of execution of
the computer system, so that the processor is able to fetch and execute the data from the memory easily and
fast.
Need for Segmentation –
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below) called as
Segment Registers.
 Code segment register (CS): is used for addressing memory location in the code segment of the memory,
where the executable program is stored.
 Data segment register (DS): points to the data segment of the memory where the data is stored.
 Extra Segment Register (ES): also refers to a segment in the memory which is another data segment in
the memory.
 Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack segment is
that segment of memory which is used to store stack data.
The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to access one of the 1MB
memory locations. The four segment registers actually contain the upper 16 bits of the starting addresses of
the four memory segments of 64 KB each with which the 8086 is working at that instant of time. A segment
is a logical unit of memory that may be up to 64 kilobytes long. Each segment is made up of contiguous
memory locations. It is an independent, separately addressable unit. Starting address will always be changing.
It will not be fixed.
Note that the 8086 does not work the whole 1MB memory at any given time. However, it works only with
four 64KB segments within the whole 1MB memory.
Below is the one way of positioning four 64 kilobyte segments within the 1M byte memory space of an 8086.
Types Of Segmentation –
1. Overlapping Segment – A segment starts at a particular address and its maximum size can go up to
64kilobytes. But if another segment starts along with this 64kilobytes location of the first segment, then
the two are said to be Overlapping Segment.
2. Non-Overlapped Segment – A segment starts at a particular address and its maximum size can go up to
64kilobytes. But if another segment starts before this 64kilobytes location of the first segment, then the
two segments are said to be Non-Overlapped Segment.
Rules of Segmentation Segmentation process follows some rules as follows:
 The starting address of a segment should be such that it can be evenly divided by 16.
 Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.

Advantages of the Segmentation The main advantages of segmentation are as follows:

 It provides a powerful memory management mechanism.
 Data related or stack related operations can be performed in different segments.
 Code related operation can be done in separate code segments.
 It allows to processes to easily share data.
 It allows to extend the address ability of the processor, i.e. segmentation allows the use of 16 bit
registers to give an addressing capability of 1 Megabytes. Without segmentation, it would require
20 bit registers.
 It is possible to enhance the memory size of code data or stack segments beyond 64 KB by
allotting more than one segment for each area.
 INTERRUPTS IN 8086 MICROPROCESSOR

INTERRUPT: An interrupt is a condition that halts the microprocessor temporarily to work on a different task
and then returns to its previous task. An interrupt is an event or signal that requests the CPU’s attention. This
halt allows peripheral devices to access the microprocessor.
TYPES OF INTERRUPTS

Hardware Interrupts – Hardware interrupts are those interrupts that are caused by any peripheral device by
sending a signal through a specified pin to the microprocessor. There are two hardware interrupts in the 8086
microprocessor. They are:

 NMI (Non-Maskable Interrupt): It is a single pin non-maskable hardware interrupt that cannot be
disabled. It is the highest priority interrupt in the 8086 microprocessor. After its execution, this
interrupt generates a TYPE 2 interrupt. IP is loaded from word location 00008 H, and CS is
loaded from the word location 0000A H.
 INTR (Interrupt Request): It provides a single interrupt request and is activated by the I/O port.
This interrupt can be masked or delayed. It is a level-triggered interrupt. It can receive any
interrupt type, so the value of IP and CS will change on the interrupt type received.
2. Software Interrupts – These are instructions inserted within the program to generate interrupts. There
are 256 software interrupts in the 8086 microprocessor. The instructions are of the format INT type,
where the type ranges from 00 to FF. The starting address ranges from 00000 H to 003FF H. These are
2-byte instructions. IP is loaded from type * 04 H, and CS is loaded from the following address given by
(type * 04) + 02 H.

3. Predefined interrupts

 TYPE 0 corresponds to division by zero(0).

 TYPE 1 is used for single-step execution for debugging the program.
 TYPE 2 represents NMI and is used in power failure conditions.
 TYPE 3 represents a break-point interrupt.
 TYPE 4 is the overflow interrupt.
INTERRUPT SERVICE ROUTINE (ISR)
Whenever an interrupt occurs, the processor completes the current instruction and starts the implementation of
an Interrupt Service Routine (ISR) or Interrupt Handler. ISR is a program that tells the processor what to do
when the interrupt occurs. After the ISR execution, control returns to the main routine where it was interrupted.
In the 8086 microprocessor following tasks are performed when the microprocessor encounters an interrupt:
1. The value of the flag register is pushed into the stack. It means that first, the value of SP (Stack Pointer) is
decremented by two then the value of the flag register is pushed to the memory address of the stack
segment.
2. The value of starting memory address of CS (Code Segment) is pushed into the stack.
3. The value of IP (Instruction Pointer) is pushed into the stack.
4. IP is loaded from word location (Interrupt type) * 04.
5. CS is loaded from the following word location.
6. Interrupt, and Trap flags are reset to 0.
 The 256 interrupt vectors are arranged in the table in memory. When 8086 responds to an interrupt , it
goes to four memory locations to get the address of CS and IP for the start of interrupt service
procedure.In 8086 first 1K byte of memory from 00000H to 003FFH, is set aside as a table for storing
the starting address of interrupt service procedures. since 4 bytes are required to store the CS and IP
values for each interrupt service procedure, the table can hold the starting address for up to 256interrupt
procedures. The starting address of an interrupt service is called the interrupt pointer/ vector, so the table
is known as Interrupt –Pointer / vector table.Priority of 8086 interrupts

ADDRESSING MODES IN 8086 MICROPROCESSOR

The way of specifying data to be operated by an instruction is known as addressing modes. This specifies that
the given data is an immediate data or an address. It also specifies whether the given operand is register or
register pair.

Types of addressing modes:

1. Register mode – In this type of addressing mode both the operands are registers.
Example:
MOV AX, BX
XOR AX, DX
ADD AL, BL
2. Immediate mode – In this type of addressing mode the source operand is a 8 bit or 16 bit data. Destination
operand can never be immediate data.
Example:
MOV AX, 2000
MOV CL, 0A
ADD AL, 45
AND AX, 0000
Note that to initialize the value of segment register an register is required.
MOV AX, 2000
MOV CS, AX
3. Displacement or direct mode – In this type of addressing mode the effective address is directly given in
the instruction as displacement.
Example:
MOV AX, [DISP]
MOV AX, [0500]
4. Register indirect mode – In this addressing mode the effective address is in SI, DI or BX.
Example: Physical Address = Segment Address + Effective Address
MOV AX, [DI]
ADD AL, [BX]
MOV AX, [SI]
5. Based indexed mode – In this the effective address is sum of base register and index register.
Base register: BX, BP
Index register: SI, DI
The physical memory address is calculated according to the base register.
Example:
MOV AL, [BP+SI]
MOV AX, [BX+DI]
6. Indexed mode – In this type of addressing mode the effective address is sum of index register and
displacement.
Example:
MOV AX, [SI+2000]
MOV AL, [DI+3000]
7. Based mode – In this the effective address is the sum of base register and displacement.
Example:
MOV AL, [BP+ 0100]
8. Based indexed displacement mode – In this type of addressing mode the effective address is the sum of
index register, base register and displacement.
Example:
MOV AL, [SI+BP+2000]
9. String mode – This addressing mode is related to string instructions. In this the value of SI and DI are auto
incremented and decremented depending upon the value of directional flag.
Example:
MOVS B
MOVS W
10. Input/Output mode – This addressing mode is related with input output operations.
Example:
IN A, 45
OUT A, 50
11. Relative mode – In this the effective address is calculated with reference to instruction pointer.
Example:
JNZ 8 bit address
IP=IP+8 bit address

INSTRUCTION SET
1. Logical instructions in 8086 microprocessor
Logical instructions are the instructions which perform basic logical operations such as AND, OR, etc. In 8086
microprocessor, the destination operand need not be the accumulator. Following is the table showing the list of
logical instructions:
OPCODE OPERAND DESTINATION EXAMPLE

AND D, S D = D AND S AND AX, 0010

OR D, S D = D OR S OR AX, BX

NOT D D = NOT of D NOT AL

XOR D, S D = D XOR S XOR AL, BL

TEST [0250],
TEST D, S performs bit-wise AND operation and affects the flag register 06

shifts each bit in D to the right C times and 0 is stored at MSB

SHR D, C position SHR AL, 04

shifts each bit in D to the left C times and 0 is stored at LSB

SHL D, C position SHL AX, BL

ROR D, C rotates all bits in D to the right C times ROR BL, CL

OPCODE OPERAND DESTINATION EXAMPLE

ROL R, C rotates all bits in D to the left C times ROL BX, 06

RCR D, C rotates all bits in D to the right along with carry flag C times RCR BL, CL

RCL R, C rotates all bits in D to the left along with carry flag C times RCL BX, 06

Here D stands for destination, S stands for source and C stands for count. They can either be register, data or
memory address
2. Arithmetic instructions in 8086 microprocessor
Arithmetic Instructions are the instructions which perform basic arithmetic operations such as addition,
subtraction and a few more. Unlike in 8085 microprocessor, in 8086 microprocessor the destination operand
need not be the accumulator.
Following is the table showing the list of arithmetic instructions:
OPCODE OPERAND EXPLANATION EXAMPLE

ADD D, S D=D+S ADD AX, [2050]

ADC D, S D = D + S + prev. carry ADC AX, BX

SUB D, S D=D–S SUB AX, [SI]

SBB D, S D = D – S – prev. carry SBB [2050], 0050

MUL 8-bit register AX = AL * 8-bit reg. MUL BH

MUL 16-bit register DX AX = AX * 16-bit reg. MUL CX

IMUL 8 or 16 bit register performs signed multiplication IMUL CX

DIV 8-bit register AX = AX / 8-bit reg. ; AL = quotient ; AH = remainder DIV BL

DIV 16-bit register DX AX / 16-bit reg. ; AX = quotient ; DX = remainder DIV CX

IDIV 8 or 16 bit register performs signed division IDIV BL

INC D D=D+1 INC AX

DEC D D=D–1 DEC [2050]

CBW none converts signed byte to word CBW

OPCODE OPERAND EXPLANATION EXAMPLE

CWD none converts signed byte to double word CWD

NEG D D = 2’s compliment of D NEG AL

DAA none decimal adjust accumulator DAA

DAS none decimal adjust accumulator after subtraction DAS

AAA none ASCII adjust accumulator after addition AAA

AAS none ASCII adjust accumulator after subtraction AAS

AAM none ASCII adjust accumulator after multiplication AAM

AAD none ASCII adjust accumulator after division AAD

3. Data transfer instructions in 8086 microprocessor

Data transfer instructions are the instructions which transfers data in the microprocessor. They are also called
copy instructions.
Following is the table showing the list of data transfer instructions:
OPCODE OPERAND EXPLANATION EXAMPLE

MOV D, S D=S MOV AX, [SI]

PUSH D pushes D to the stack PUSH DX

POP D pops the stack to D POP AS

PUSHA none put all the registers into the stack PUSHA

POPA none gets words from the stack to all registers POPA

XCHG D, S exchanges contents of D and S XCHG [2050], AX

IN D, S copies a byte or word from S to D IN AX, DX

OUT D, S copies a byte or word from D to S OUT 05, AL

OPCODE OPERAND EXPLANATION EXAMPLE

XLAT none translates a byte in AL using a table in the memory XLAT

LAHF none loads AH with the lower byte of the flag register LAHF

SAHF none stores AH register to lower byte of the flag register SAHF

PUSHF none copies the flag register at the top of the stack PUSHF

POPF none copies a word at the top of the stack to the flag register POPF

4. STRING MANIPULATION INSTRUCTIONS IN 8086 MICROPROCESSOR

String is a series of data byte or word available in memory at consecutive locations. It is either referred as byte
string or word string. Their memory is always allocated in a sequential order. Instructions used to manipulate
strings are called string manipulation instructions.
Following is the table showing the list of string manipulation instructions:
OPCODE OPERAND EXPLANATION EXAMPLE

REP
REP instruction repeat the given instruction till CX != 0 MOVSB

REPE instruction repeat the given instruction while CX = 0 REPE

REPZ instruction repeat the given instruction while ZF = 1 REPZ

REPNE instruction repeat the given instruction while CX != 0 REPNE

REPNZ instruction repeat the given instruction while ZF = 0 REPNZ

MOVSB none moves contents of byte given by DS:SI into ES:DI MOVSB

MOVSW none moves contents of word given by DS:SI into ES:DI MOVSW

MOVD none moves contents of double word given by DS:SI into ES:DI MOVD

LODSB none moves the byte at address DS:SI into AL; SI is incr/decr by 1 LODSB

LODSW none moves the word at address DS: SI into AX; SI is incr/decr by 2 LODSW

moves the double word at address DS:SI into EAX; SI is incr/decr

LODSD none by 4 LODSD
OPCODE OPERAND EXPLANATION EXAMPLE

moves contents of AL to byte address given by ES:DI; DI is

STOSB none incr/dec by 1 STOSB

moves the contents of AX to the word address given by ES:DI; DI

STOSW none is incr/decr by 2 STOSW

moves contents of EAX to the DOUBLE WORD address given by

STOSD none ES:DI; DI is incr/decr by 4 STOSD

SCASB none compares byte at ES:DI with AL and sets flags according to result SCASB

SCASW none compares word at ES:DI with AX and sets flags SCASW

SCASD none compares double word at ES:DI with EAX and sets flags SCASD

CMPSB none compares byte at ES:DI with byte at DS:SI and sets flags CMPSB

CMPSW none compares word at ES:DI with word at DS:SI and sets flags CMPSW

compares double word at ES:DI with double word at DS:SI and sets
CMPSD none flags CMPSD

5. Process control instructions in 8086 microprocessor

Process control instructions are the instructions which control the processor’s action by setting(1) or resetting(0)
the values of flag registers.
OPCODE OPERAND EXPLANATION EXAMPLE
STC none sets carry flag to 1 STC
CLC none resets carry flag to 0 CLC
CMC none compliments the carry flag CMC
STD none sets directional flag to 1 STD
CLD none resets directional flag to 0 CLD
STI none sets the interrupt flag to 1 STI
CLI none resets the interrupt flag to 0 CL
 ASSEMBLING ,LINKING &LOADING (Assembly Language Programming)
Editor: An editor is a program which allows you to create a file containing the assembly language statements for your
programs. • The actual position of each field on a line is not important. After typing the program we have to save the file
on the disk or floppy. • This file is called source file. It contains the extension .ASM for turbo assembler.
Assembler: this program is used to translate the assembly language mnemonics for instructions to the corresponding
binary codes. • It runs in two passes. • on the first pass it generates a symbol table. • On the second pass it generates the
binary codes. • The first file is called the object file and having the extension .OBJ • The second file generated by the
assembler is called the assembler list file and is having the extension .LST
LINKER: It is a program used to join several object files into one object file. • The linker produces link file which
contains the binary codes for all combined modules. • The linker also produces a link map file which contains the address
information about the linked files. • The produced link files have the extension .EXE and .MAP
LOCATOR: It is a program used to assign the specific addressess of where the segments of object code are to be loaded
into memory. • A locator program converts the .EXE file to a .BIN file which has the physical addressess.
Debugger: If your program does not require external hardware or requires only hardware accessible directly from your
microcomputer then you can use a debugger to run and debug your program. • It allows you to load your object code
program and troubleshoot it. • A debugger also allows you to set a breakpoint at any point in your program. • The
advantage of a breakpoint is we can debug the program upto the breakpoint and it is correct then we can further move
after that point.
Emulator: Another way to run the program is using emulator. It is a mixture of hardware and software. • It is used to teat
and debug external systems.

Assembler directives

Assembler directives are the instructions used by the assembler at the time of assembling a
source program. More specifically, we can say, assembler directives are the commands or
instructions that control the operation of the assembler.
Assembler directives are the instructions provided to the assembler, not the processor as the
processor has nothing to do with these instructions. These instructions are also known
as pseudo-instructions or pseudo-opcode.
1. DB: Define Byte: The DB directive is used to reserve byte or bytes of memory locations in the available memory.
Example: VALUE DB 50H
LIST DB 0lH, 02H, 03H, 04H
• This statement directs the assembler to reserve four memory locations for a list named LIST and initialise them with the
above specified four values.
• MESSAGE DB 'GOOD MORNING'
Assembler directives
2. DW: Define Word: The DW directive serves the same purposes as the DB directive, but it now makes the assembler
reserve the number of memory words (16-bit) instead of bytes.
EX: WORDS DW 1234H
•Another option of the DW directive is explained with the DUP operator.
EX: WDATA DW 5 DUP (6666H)
• This statement reserves five words, i.e. 10-bytes of memory for a word lable WDATA and initializes all the word
locations with 6666H.
3.DQ: Define Quad word: This directive is used to direct the assembler to reserve 4 words (8 bytes) of memory for the
specified variable and may initialise it with the specified values.
4. DT: Define Ten Bytes: The DT directive directs the assembler to define the specified variable requiring la-bytes for its
storage and initialise the 10bytes with the specified values.
5. ASSUME: Assume Logical Segment Name The ASSUME directive is used to inform the assemble, the names of the
logical segments to be assumed for different segments used in the program.
6. END: END of Program The END directive marks the end of an assembly language program. END statement should
be the last statement in the file
7. SEGMENT: Logical Segment The SEGMENT directive marks the starting of a logical segment. The started segment
is also assigned a name, i.e. label, by this statement.
8. ENDS: END of Segment This directive marks the end of a logical segment. Any statement
appearing after ENDS will be neglected from the segment.
EX: DATA SEGMENT
.
.
.
DATA ENDS
ASSUME CS: CODE, DS:DATA
CODE SEGMENT.
.
.
.
CODE ENDS
END
The above structure represents a simple program containing two segments named DATA and CODE. The data related to
the program must lie between the DATA SEGMENT and DATA ENDS statements. Similarly, all the executable
instructions must lie between CODE SEGMENT and CODE ENDS statements.
9. EQU: Equate: The directive EQU is used to assign a label with a value or a symbol. The use of this directive is just to
reduce the recurrence of the numerical values or constants in a program code. The recurring value is assigned with a label,
and that label is used in place of that numerical value, throughout the program.
Example LABEL EQU 0500H
ADDITION EQU ADD

MACRO, PROCEDURE, STACK

1 . Macro :
Macro is a set of instruction and the programmer can use it anywhere in the program by using its name. It is
mainly used to achieve modular programming. So same set of instructions can be used multiple times when
ever required by the help of macro. Wherever macro’s identifier is used, it is replaced by the actual defined
instructions during compilation thereby no calling and return occurs.

Syntax of macro :
%macro macro_name number_of_parameters
<macro body>
%endmacro
2. Procedure :
Procedures are also like macro, but they are used for large set of instruction when macro is useful for small
set of instructions. It contains a set of instructions which performs a specific task. It contains three main
parts i.e Procedure name to identify the procedure, procedure body which contains set of instructions, and
RET statement which denotes return statement. Unlike macros, procedures follow call-return method
thereby achieving true modularity.
Syntax of Procedure :
procedure_name :
procedure body ….......................
RET
To call a procedure
CALL procedure_name
After execution of procedure control passes to the calling procedure using RET statement.

S.No. MACRO PROCEDURE

Procedure contains a set of instructions which can

Macro definition contains a set of instruction to be called repetitively which can perform a specific
01. support modular programming. task.

It is used for small set of instructions mostly less It is used for large set of instructions mostly more
02. than ten instructions. than ten instructions.

03. In case of macro memory requirement is high. In case of procedure memory requirement is less.

CALL and RET instruction/statements are not CALL and RET instruction/statements are required
04. required in macro. in procedure.

Assembler directive MACRO is used to define Assembler directive PROC is used to define
macro and assembler directive ENDM is used to procedure and assembler directive ENDP is used to
05. indicate the body is over. indicate the body is over.

Execution time of macro is less as it executes faster Execution time of procedures is high as it executes
06. than procedure. slower than macro.

Here machine code is created multiple times as

each time machine code is generated when macro Here machine code is created only once, it is
07. is called. generated only once when the procedure is defined.

In a macro parameter is passed as part of statement In a procedure parameters are passed in registers
08. that calls macro. and memory locations of stack.

Overhead time does not take place as there is no Overhead time takes place during calling procedure
09. calling and returning. and returning control to calling program.
8086 STACK

The stack is a block of memory that may be used for temporarily storing the contents of
the registers inside the CPU. It is a top-down data structure whose elements are accessed using
the stack pointer (SP) which gets decremented by two as we store a data word into the stack and
gets incremented by two as we retrieve a data word from the stack back to the CPU register.
 The process of storing the data in the stack is called ‘pushing into’ the stack and the
reverse process of transferring the data back from the stack to the CPU register is known as
‘popping off’ the stack. The stack is essentially Last-In-First-Out (LIFO) data segment. This

means that the data which is pushed into the stack last will be on top of stack and will be
popped off the stack first.

The stack pointer is a 16-bit register that contains the offset address of the memory
location in the stack segment. The stack segment, like any other segment, may have a memory
block of a maximum of 64 Kbytes locations, and thus may overlap with any other segments.
Stack Segment register (SS) contains the base address of the stack segment in the memory.

The Stack Segment register (SS) and Stack pointer register (SP) together address the stack-top
as explained below:

If the stack top points to a memory location 52050H, it means that the location 52050H is
already occupied with the previously pushed data. The next 16 bit push operation will
decrement the stack pointer by two, so that it will point to the new stack-top 5204EH and the
decremented contents of SP will be 204EH. This location will now be occupied by the recently
pushed data.
Thus for a selected value of SS, the maximum value of SP=FFFFH and the segment can have
maximum of 64K locations. If the SP starts with an initial value of FFFFH, it will be
decremented by two whenever a 16-bit data is pushed onto the stack. After successive push
operations, when the stack pointer contains 0000H, any attempt to further push the data to the
stack will result in stack overflow.
After a procedure is called using the CALL instruction, the IP is incremented to the next
instruction. Then the contents of IP, CS and flag register are pushed automatically to the stack.
The control is then transferred to the specified address in the CALL instruction i.e. starting
address of the procedure. Then the procedure is executed.
 Push
• Pop
• Top of stack
• Stack pointer
• LIFO
STACK INSTRUCTIONS

The two set of instructions which explicitly modify the stack are the PUSH (which places items on the stack) and the POP (which
retrieves items from the stack). In both cases, the stack pointer is adjusted accordingly to point always to the top of stack.
Thus, PUSH AX means SP=SP-2 and AX -> [SP]
POP AX means [SP] -> AX and SP=SP+2.