An 8-bit RRAM based Multiplier for Hybrid

Memory Computing
Xuan Zhou1, Xiaolei Zhu2, Bing Chen2, Yi Zhao2, Chengjie Fu2
1
College of Electrical Engineering, Zhejiang University, Hangzhou, China
2
College of Micro-electronics，Zhejiang University，Hangzhou, China

email: [email protected], [email protected]

Abstract—Hybrid-memory computing can reconcile the speed stored in the RRAM is 1V and the SET/RESET voltage is 2V
of in-memory computing and the power of near-memory. An and -2V respectively. The write and read properties of RRAM
RRAM based multiplier for hybrid-memory computing is are shown in Fig. 1. The original state of RRAM is High-
proposed to balance the efficiency and flexibility. It is Resistor-State(HRS). Since 2ns, 2V is applied to the RRAM and
implemented in standard RRAM model and 65nm CMOS the RRAM is set to Low-Resistor-State (LRS) within 0.7 ns. The
technology. The simulation results show that the proposed RRAM reset speed is even faster. The RRAM is reset immediately after
based multiplier achieves a calculation speed of 1.6us and 1.32 -2V is applied at 5ns. The simulation results shows that the
mW from 1V power supply.
current read out from the LRS RRAM is 329 uA while 0.65 uA
from the HRS RRAM. The resistance of HRS is three orders of
Keywords—in memory computing, near memory computing,
multiplier, RRAM, hybrid
magnitude larger than that of LRS, which makes it easy to read
out data stored in RRAMs correctly.
I. INTRODUCTION
As the boom of data volume, there is a growing desire to
reduce the latency of data transmission [1]. Memory
computing, including near-memory computing and in-
memory computing, is regarded as one of the most promising
solution towards latency. In-memory computing, though of
better efficiency, has more restrictions in application than
near-memory computing [1] [2]. Near-memory computing,
however, can construct circuits of more functions [2]. In order
to balance the efficiency and flexibility, hybrid-memory
computing is proposed. Hybrid-memory computing is a
combination of in-memory computing and near-memory
computing. In a hybrid-memory computing process, the data
will be processed in memory firstly and then in the circuit near
memory. Fig. 1. Voltage and current waveform of RRAM read/write operation
RRAM is a very promising novel memory device and a
lot of RRAM based multiplier has been reported in recent years III. MULTIPLIER ARCHITECTURE
[3]-[6]. An RRAM based multiplier for hybrid-memory Fig. 2 shows the algorithm of RRAM based hybrid-memory
computing is proposed to balance the efficiency and flexibility. computing multiplier. In the first step, in-memory computing,
It is implemented in standard RRAM model and 65nm CMOS the multiplicator and multiplicand are applied to the RRAM
technology. The simulation results show that the proposed array as voltage signals and the partial products are calculated
RRAM based multiplier achieves a calculation speed of 1.6us and stored in RRAM array. Then the partial products are read
out and added to get the product of multiplier by the method of
and 1.32 mW from 1V power supply. It demonstrates that
near-memory computing.
RRAM based multiplier for hybrid-memory computing has
good performance in light of speed and power, which has great
potentials in the future application on Internet of Things and
wearable bio-electronic devices.
II. MEMRISTOR BASIC PROPERTIES
In this paper, the RRAM based multiplier is constructed with
a well-performed RRAM model [3], which makes the multiplier
perform well in speed. The voltage for reading out information
(a)

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 A. Initializing step
-2V is the voltage for RESET. Apply -1V to BL [7:0] and
1V to WL [7:0] for 1ns to reset all RRAMs to HRS.
(b)
Fig. 2. RRAM based multiplier process
B. Writing step
Apply the voltage corresponding to the value of a [i]/b [j] to
The proposed RRAM-based multiplier mainly consists of WL [7:0] and BL [7:0] for 1ns.
three parts: RRAM array, flip-flop array and full adder as shown
C. Reading step
in Fig. 3. The 8×8 RRAM array is the key of multiplier. BL[7:0]
are the terminals for multiplicator inputs while WL [7:0] are for 8 reading step periods is needed to read out all the data in
multiplicand inputs. Each BL is connected with the positive RRAM array as mentioned before. During reading step, the low
terminals of a column of RRAM and each WL is connected with voltage potential (0V) is applied to WL [7:0] and the high
the negative terminals of a row of RRAM. voltage potential (1V) to each BL in order to read out each row
of partial products separately. During 8 reading step periods,
from BL [7] to BL [0], only one BL is set to 1V at a time and all
other BLs is set to 0V.
For the first reading step period, all SR flip-flops are set to
work mode. Thus, the voltage information on WLs read out
from RRAMs is stored in the rightmost column of SR flip-flops.
In fact, all flip-flops including the rightmost column of SR flip-
flops store the data from the RRAMs connected with BL [7]. In
order to maintain the data stored in the rightmost column of SR
flip-flops, these flip-flops are set to hold mode since then. For
the second reading step period, all flip-flops except those in
rightmost column are set to work mode. Then the data in
RRAMs connected to BL [6] is stored in the second column of
SR flip-flops from the right. After 8 reading step periods, data
in RRAM array is transferred to flip-flop array successfully.
Fig. 3. Schematic of RRAM multiplier structure Although reading out data only consumes less than 1ns, it takes
time for amplifiers to react and flip-flops to refresh the data.
Assume the multiplicand and multiplicator of the 8bit×8bit Therefore, each reading step lasts for 30ns.
RRAM multiplier are a [7:0] and b [7:0] respectively. The
V. SIMULATION RESULTS AND DISCUSSION
relation of a [i]/b [j] and the corresponding voltage volume
applied to WL [i]/BL [j] is shown in Table. 1. To verify the function of RRAM based multiplier, the
simulation of a multiplication is shown in Fig. 4. P [15:0] is the
TABLE I. VALUE OF a[i]/b[j] AND THE CORRESPONDING VOLTAGE product of a [7:0]×b [7:0]. Only less than 1ns is required to write
VOLUME or read out. Even so, in consideration of reliability, 1ns is set to
write data to RRAM, and 200ns for reading step is set to satisfy
a[i]=1 a[i]=0 b[j]=1 b[j]=0
the rise or fall time of amplifier. Table. 2 shows the energy and
voltage applied -1 0 1 0 power consumed by the hybrid-memory computing multiplier.
to WL/BL(V) The simulation results show that the proposed RRAM based
multiplier achieves a calculation speed of 1.6us and 1.32 mW
The state of RRAM is determined by voltage difference from 1V power supply. Compared to the counterpart of CMOS
between two terminals. Due to the 2V RRAM “SET” voltage based multiplier, the RRAM based multiplier well balances the
and -2V “RESET” voltage, the RRAM will be set to LRS only efficiency and flexibility in light of speed and power.
when both a[i] and b[j] are 1.
IV. 8×8 FLIP-FLOP ARRAY DESIGN
Flip-flop array is used to store all partial products for FA to
calculate the final product. There are 8 RRAMs in every row but
only 1 WL wire for reading out. To avoid confusion, only one
column of RRAMs can be read out at a time. The voltage on WL
stands for the data stored in RRAM when 1V is applied to BL.
All partial products are transferred to flip-flop array after 8
reading steps. Meanwhile, CMOS based FA has the final
product calculated.
With three sequential steps: writing and reading, a multiplier
can be realized based on the RRAM model mentioned above.

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 p<8> p<9> p<10> p<11>
1
REFERENCES
1
[1] Gagandeep Singh, Lorenzo Chelini, et al.: ‘A review of near-memory
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Voltage (V)

0.5 0.5 System Design (DSD).

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p<0> p<1> p<2> p<3>
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Voltage (V)

0.5 0.5

0 0
1.6 1.7 1.6 1.7 1.6 1.7 1.6 1.7

p<4> p<5> p<6> p<7>

1 1
Voltage (V)

0.5 0.5

0 0
1.6 1.7 1.6 1.7 1.6 1.7 1.6 1.7

Fig. 4. Transient simulation results of RRAM-based multiplier

(a[7:0]=10111010 b[7:0]=10010111 p[15:0]=0110110110110110)

TABLE II. POWER CONSUMPTION

energy(nJ) power(mW)
2.116 1.323
in-memory near-memory in-memory near-memory
0.152 1.964 0.095 1.228

VI. CONCLUSION
A novel RRAM based multiplier with the structure of
hybrid-memory computing is proposed and functionally
verified by simulation. It shows good performance in speed,
power and area. The proposed multiplier extends the
application for RRAM and shows great potentials in the future
application on Internet of Things and wearable bio-electronic
devices.
VII. ACKNOWLEDGEMENT
This work is supported by the Advance Research Program
of Equipment (Grant No. JZX2017-1590/Y484).

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