Sushanta K.

Mandal

Logic Gates Switching Circuit

• Logic gates are electronic circuits that operates on one or more
input signals to produce an output signal
AND Gate OR Gate NOT Gate
x
x y
Voltage Voltage y
Lamp z Lamp z
source source

x y x.y x y x+y x x’
Switches in series – logic AND Switches in parallel – logic OR
0 0 0 0 0 0 0 1
0 1 0 0 1 1 1 0
1 0 0 1 0 1
1 1 1 1 1 1

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NOR Gate NAND Gate

A
• NOR Symbol, Equivalent Circuit, Truth Y
B
Table
• This is a NAND gate. It is a
combination of an AND gate followed by
an inverter. Its truth table shows this…
A B Y
0 0 1
0 1 1
1 0 1
1 1 0

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Sushanta K. Mandal

XOR Gate (Exclusive-OR) XNOR Gate (Exclusive-NOR)

A
A
Y B Y
B

• This is an Exclusive-NOR gate

• This is a XOR gate. A B Y • The complement of the XOR gate.
• The switching algebra symbol 0 0 0 • The switching algebra symbol
for this operation is , i.e.
0 1 1 for this operation is , i.e. A B Y
1 0 1 A  B. 0 0 1
AB. 1 1 0 • A  B=AB+A’B’. 0 1 0

• A  B=A’B+AB’.
1 0 0
1 1 1
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S-R Latch with NOR Gates

• NAND, NOR gates are called universal gate. R (reset) Q(t+1) S R Q(t+1)

0 0 Q(t) Memory

• AND, OR and NOT are called basic gates.

1 0 1 Set State
0 1 0 Reset State
1 1 Undefined state
S (set)
• XOR(EX-OR), XNOR(EX-NOR) are called Q’(t+1)

derived gates. •
•
S-R latch made from cross-coupled NORs
If Q = 1, set state
• If Q = 0, reset state
• Usually S=0 and R=0 is called Memory state
• S=1 and R=1 generates undefined or indeterminate
results.

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S-R Latch with NAND Gates S-R Latches

Q(t+1) S R Q(t+1)
S
1 1 Q(t) Memory
0 1 1 Set state
1 0 0 Reset state
0 0 Undefined state
R Q’(t+1)

• S-R Latch made from cross-coupled NANDs

• Sometimes called S’-R’ latch
• Usually S=1 and R=1 is called Memory state
• S=0 and R=0 generates undefined or indeterminate
results.

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S-R Latch with control input

Graphic symbol of S-R Latch

Q(t+1)

Q’(t+1) • S-R Latch with control input is called Flip-Flop

• It is used to store one bit of information
• Occasionally, desirable to avoid latch changes
• C = 0 disables all latch state changes
• Control signal enables data change when C = 1
• Right side of circuit same as ordinary S-R latch.
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Clocks and synchronization Graphic symbol of S-R Flip-Flop

• A clock is a special device that whose output

continuously alternates between 0 and 1.
clock period Q(t+1)

• The time it takes the clock to change from 1 to 0 and

Q’(t+1)
back to 1 is called the clock period, or clock cycle time.
• The clock frequency is the inverse of the clock period.
The unit of measurement for frequency is the hertz.

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J-K Flip-Flop Flip-Flops

• A flip-flop is a state of a latch that can be switched by
momentary change in the control input.
• This momentary change is called a trigger and the transition
it causes is said to trigger the flip-flop.
• The flip-flop is triggered every time the pulse goes to a high
or logic level 1.

• S-R Latch with control input is called Flip-Flop

• Replace the two input NAND gate with the three input Response to positive level(Level Triggering)
NAND gate to get a J-K Flip Flop from a S-R FF. • The problem with the flip-flops is that as long as the input
• C = 0 disables all the data changes clock pulse remains at this level, any changes in the input
• Control signal C=1 enables data change when C = 1 data will cause a change in the output and the state of the
latch.
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• Race around condition or Racing.

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Master Slave J-K Flip-Flop

The Master-Slave Flip-Flop is basically two gated SR flip-flops
connected together in
a series configuration with the slave having an inverted clock pulse.
The outputs
from Q and Q from the "Slave" flip-flop are fed back to the inputs of
the "Master" with the outputs of the "Master" flip-flop being
connected to the two inputs of the "Slave" flip-flop. This feedback
configuration from the slave's output to the master's input gives the
characteristic toggle of the JK flip-flop .
The input signals J and K are connected to the gated "master"
SR flip-flop which "locks" the input condition while the clock
(Clk) input is "HIGH" at logic level "1". As the clock input of the
"slave" flip-flop is the inverse (complement) of the "master"
clock input, the "slave" SR flip-flop does not toggle. The outputs
from the "master" flip-flop are only "seen" by the gated "slave"
flip-flop when the clock input goes "LOW" to logic level "0".
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When the clock is "LOW", the outputs from the "master" flip- The Solution
flop are latched and any additional changes to its inputs are
ignored. The gated "slave" flip-flop now responds to the state • A clock pulse goes through two transition from 0 to 1 and the
of its inputs passed over by the "master" section. Then on the return from 1 to 0
"Low-to-High" transition of the clock pulse the inputs of the • The solution: by changing the operation of a flip-flop to
"master" flip-flop are fed through to the gated inputs of the trigger it only during a signal transition.
"slave" flip-flop and on the "High-to-Low" transition the same
inputs are reflected on the output of the "slave" making this • Two types of transition: the positive transition (from 0 t0 1)
type of flip-flop edge or pulse-triggered. and the negative transition (from 1 to 0)

Then, the circuit accepts input data when the clock

signal is "HIGH", and passes the data to the output on
the falling-edge of the clock signal. In other words, Positive-edge response
the Master-Slave JK Flip-flop is a "Synchronous"
device as it only passes data with the timing of the
clock signal.
Negative-edge response
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Flip-Flop Symbols
J-K flip flop Symbols
Input Input
Q Q

C Q C Q

Positive Edge Negative Edge

Triggered Flip Flop Triggered Flip Flop
Positive-edge Negative-edge
Triggered FF Triggered FF

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D-Flip Flop Clocked D Flip-Flop

X
D S
• Stores a value on the positive edge of C
Q • Input changes at other times have no effect on output
C

Q’
R
Y

D C Q
0 1 0
1 1 1
X 0 Q0 (Memory)

Input value D is passed to output Q when C is high

Input value D is ignored when C is low

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Clocked J-K Flip Flop Registers

• Two data inputs, J and K
• J -> set, K -> reset, if J=K=1 then toggle output • A flip-flop can store only one bit data (0 or 1)

– A single-bit register

• Register consists of a group of flip-flops and gates

Characteristic Table • An n-bit register consists of n-bit flip-flops

– store n-bit information

• Shift register is used to store and shift data.

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Shift Registers(SISO)
Types of Shift Register
• Serial in serial out (SISO)
• Serial in Parallel out (SIPO)
• Parallel in serial out (PISO)
• Shifts binary information in one or both directions.
• Parallel in Parallel out (PIPO)
• On the positive edge of the first clock pulse, the
signal on the in is latched in the first FF.

• On the next clock pulse, the data of the first FF is

stored in the second FF, and the data present at
the in is stored is the first FF, etc.
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Counters Counters
• Counter categories:
• Binary counter: follows the binary number
sequence. – Ripple counters
• An n-bit binary counter: – Synchronous counters
– Consists of n flip-flops
• Ripple counters: The flip-flop’s output transition
– Can count in binary from 0 to 2n -1 triggers other flip-flops.

• A counter is a register that goes through a • Synchronous counters: A common clock triggers
sequence of states. all flip-flops simultaneously rather than one at a
time in succession as in ripple counters.

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Binary Ripple Counter 3-bit Binary Ripple Counter

• All the J and K inputs of all the flip-flops are Q2 Q1 Q0

connected to a logic 1. 0 0 0
0 0 1
• Each flip-flop complement if the signal in its C 0
0
1
1
0
1
input goes through a negative transition. 1 0 0
1 0 1
• The flip-flop holding the LSB receives the 1
1
1
1
0
1
incoming count pulses. 0 0 0
Q0 is complemented with the count pulse. Since Q0 goes from 1 to 0, it triggers
• The count starts with binary 0 and increments by Q1 and complements it. As a result, Q1 goes from 1  0, which in turn complements
one with each count pulse input. Q2 changing it from 0  1. Q2 does not trigger Q3 because Q2 produces a positive
transition. The flip-flops change one bit at a time in succession and the signal
propagates through the counter in a ripple fashion from one stage to the next.
EC402 Digital Electronic Circuits 31 32
Spring 2011

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4-bit Binary Ripple Counter 4-bit Binary Ripple Counter

J Q1
Count C
K

J Q2
C
K

J Q3
C
K

J Q4
C
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Logic-1 K

Problems with Ripple Counter

• Asynchronous or ripple counters are arranged
in such a way that the output of one flip flop
changes the state of the next.

• In a long chain of ripple counter stages, the last

flip flop changes its state considerably later than
the first FF due to propagation delays in each
stage.

• Problems occur if this delay is longer than the

response time of other logic elements connected
to the circuit.
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