Design of

sequential circuits
© Luis Entrena, Celia López,
Mario García, Enrique San Millán

Universidad Carlos III de Madrid

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Electrónica Digital. Grado en Ingeniería en Electrónica Industrial y Automática 1

Sequential circuits
⚫ Features
• Memory: for a given set of input values, outputs may be
different depending on the state of the circuit
• The circuit state is the result of previous input values
• The circuit state is stored in flip-flops
• Outputs affected by inputs and state
• Example: counter

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Outline
⚫ Sequential circuits
• Bistables
• Asynchronous latches
• Synchronous flip-flops
• Synchronous flip-flops with asynchronous inputs
• Synchronous circuits
• Registers
• Counters
⚫ Design of sequential circuits in VHDL
• Flip-flops and registers
• Rules for the design of sequential circuits
• Counters
• Examples and exercises

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Bistables
⚫ Definition of bistable
• Circuit storing an information bit. It has two stable states, logic 0
and logic 1. The state does not change until the control inputs
allow it.
⚫ Classification
• Control logic: inputs determining the new state
• D, T, SR, JK
• Synchronism:
• Asynchronous (latch): can change the state in response to any input,
at any time
• Synchronous (flip-flop): they have a control input that controls when
the state can change
• Level-triggered
• Edge-triggered

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Asynchronous latches
⚫ SR asynchronous flip-flop On
• S=‘1’ => Set
‘0’
‘1’ S
• R=‘1’ => Reset ‘0’
Off Q
• S=R=‘0’ => Keep state ‘1’ R

⚫ Characteristics
• Memory: it keeps the state if inputs are not active
• Asynchronous: the state changes inmediately if R or S are
activated

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Asynchronous latches
⚫ State keeping circuit
‘1’ ‘0’ ‘1’ Q
Two stable states
‘0’ ‘1’ ‘0’

⚫ With control signals

R Q
S R Q /Q
0 0 Q /Q Keep state
1 0 1 0 Set
/Q 0 1 0 1 Reset
S 1 1 0 0 Invalid condition

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Level-triggered synchronous
D flip-flop
⚫ It has a control signal that allows the state to be
changed
⚫ Level-triggered synchonous D Flip-flop (D-latch)
• C=‘1’ => state changes to D value
• C=‘0’ => keep state
D Q

C /Q

0 Q
D
C D Q /Q
1
0 X Q /Q Keep state
/Q
1 0 0 1 Assign ‘0’
C
1 1 1 0 Assign ‘1’

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Edge-triggered synchronous
D flip-flop
⚫ Edge-triggered synchonous D flip-flop
D Q
LATCH

Edge D Q /Q
detector
Clk
C /Q

Edge detector tp,inv

Clk
Bad solution due to
Clk technology. Inverter
/Clk
C
delay is not
C controllable.

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Master-Slave synchronous
D flip-flop
⚫ Two latches active with opposite levels
MASTER SLAVE
D QM QS = Q
D Q D Q

C C
Clk

Master Slave Master Slave

Clk
⚫ QS changes only in
D clock rising edges
QM
⚫ QS new value is D
value just before the
QE clock edge

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Edge-triggered synchronous
D flip-flop
⚫ The one used most
⚫ Only changes in clock edges
Clk
(normally rising edges)
D
⚫ The output change takes place
just after the edge Q

⚫ The output new value is taken

from D input just before the edge

Clk

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Flip-flops with asynchronous
inputs
⚫ Synchronous flip-flops with asynchronous inputs for initialization
• Clear: asynchronous initialitation to ‘0’ preset
• Preset: asynchronous initialitation to ‘1’
• Usually low-level active
D Q

/Q
preset
clear
clear

Clk

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Flip-flop control logic
⚫ Flip-flop inputs control the way the state is changed
• Kinds of flip-flops depending on the inputs:
• D,T,JK,SR
• Enable signal:
• Allows/prevents the state to change
• If not enabled, the state is kept
• Synchronous initialization
• Set to ‘0’ or ‘1’ in a synchronous way

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Flip-flop control logic
⚫ Working tables
• Describe functionality
JK flip-flop
SR flip-flop (Jump & Kill)

D flip-flop T flip-flop (Set-Reset) J K Q’

(Data) (Toggle) S R Q’ 0 0 Q
D Q’ T Q’ 0 0 Q 0 1 0
0 0 0 Q 0 1 0 1 0 1
1 1 1 /Q 1 0 1 1 1 /Q

D flip-flop T flip-flop
⚫ Transition tables D Q Q’ T Q Q’

• Describe the new state in 0

0
0
1
0
0
0
0
0
1
0
1
terms of present state and
1 0 1 1 0 1
input values
1 1 1 1 1 0
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Flip-flop control logic
⚫ Flip-flops with enable input

D flip-flop T flip-flop
D Q E D Q’ E T Q’
T Q
E 0 X Q 0 X Q E
/Q 1 0 0 1 0 Q /Q
1 1 1 1 1 /Q

T
Q Q
D 0 E
1 D Q T Q
E
/Q /Q

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Flip-flop control logic
⚫ Flip-flop with synchronous initialization
• Set: forces ‘1’
• Reset: forces ‘0’
⚫ Example: D flip-flop with Enable, Set and Reset
• Priority: Reset, Set, Enable

D Q
E D 0
1 Q
/S E
D Q
/R
/S
/Q

/R

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6. Timing characteristics
⚫ Timing flip-flop constraints
• Clock level length → (t0min,t1min)
• Asynchronous signals length → (treset min)
• Data insertion times→ (tsetup,thold)
• Output propagation delay → (tpClk, Q)

(treset mín)
clear
(tomín,t1mín)
clk

D
(tsetup,thold)
Q

Clk

Q
(tpClk,Q)

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Synchronous circuits
⚫ In a sequential circuit with several flip-flops, it is necessary to
ensure that flip-flop states are always coherent, taking timing
constraints into account
⚫ Solution: synchronous circuit
• Every flip-flop uses exactly the same clock
• Every flip-flop is triggered by the same clock edge (usually the rising
edge)
• Flip-flops can use an asynchronous input, usually known as Reset: it
must be common to all flip-flops and it can only be used for
initialization

D Q D Q D Q

/Q /Q /Q

Clk
Reset

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 Synchronous circuits:
the clock cycle
⚫ Meeting timing constraints is notably simpler in
synchronous circuits
• Just limit the maximum clock frequency
⚫ Critical path:
• Path between two flip-flops with the largest delay
• Slowest path between two flip-flops. It determines the
maximum allowable clock frequency for the circuit.

Clk
TClk > tpClk,Q + tcritical + tsetup
TClk
fClk = 1 / TClk
tpClk,Q tcritical tsetup
Example: TClk = 1ns → fClk = 1GHz

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Outline
⚫ Sequential circuits
• Bistables
• Asynchronous latches
• Synchronous flip-flops
• Synchronous flip-flops with asynchronous inputs
• Synchronous circuits
• Registers
• Counters
⚫ Design of sequential circuits in VHDL
• Flip-flops and registers
• Rules for the design of sequential circuits
• Counters
• Examples and exercises

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Flip-flops
⚫ Synchronous circuits
• We will only use edge-triggered D flip-flops
• To model edge-triggered flip-flops we will use the ‘EVENT
attribute
⚫ VHDL attributes:
• Denote values, functions, types or ranges associated to
several language elements
⚫ ‘EVENT attribute
• Applies to a signal
• Indicates if the signal changes value at evaluation time. It
returns TRUE or FALSE

clk’EVENT AND clk = ‘1’-- Rising edge

clk’EVENT AND clk = ‘0’-- Falling edge

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D Flip-flop
-- D Flip-Flop -- D Latch
-- rising edge triggered -- level sensitive
PROCESS (clk) PROCESS (c, d)
BEGIN BEGIN
IF clk’EVENT AND clk = ‘1’ THEN IF c = ‘1’ THEN
q <= d; q <= d;
END IF; END IF;
END PROCESS; END PROCESS;

d q d q

clk c

ONLY SYNCHRONOUS
DESIGN
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Flip-flop with asynchronous reset
⚫ Asynchronous inputs (reset) must be included in the
sensitivity list of the process
⚫ Note: The control signals priority is determined by
the order of the IF ... ELSIF ... clauses
PROCESS (reset, clk)
BEGIN
IF reset = ‘1’ THEN
q <= ‘1’;
ELSIF clk’EVENT AND clk = ‘1’ THEN
q <= d;
END IF;
END PROCESS;

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Flip-flop with synchronous inputs
⚫ Synchronous inputs should not be included in the
sensitivity list

}
PROCESS (reset, clk)
BEGIN
IF reset = ‘1’ THEN Asynchronous part
(just initialization)
q <= ‘0’;
ELSIF clk’EVENT AND clk = ‘1’ THEN

}
IF enable = ‘1’ THEN
q <= d; Synchronous part
END IF;
END IF;
END PROCESS;

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Rules for the design of
synchronous sequential circuits
⚫ They must be described using processes
⚫ There must be a clock event condition:
• IF clk’EVENT AND clk = ‘1’ THEN
• IF RISING_EDGE(clk) THEN
• IF clk’EVENT AND clk = ‘0’ THEN
• IF FALLING_EDGE(clk) THEN
• No additional conditions (or ELSE) can be placed after the
clock event condition
• If a signal is assigned, it is not necessary to assign it for every
branch: for the branches where it is not assigned, the signal will
keep its value (memory)
⚫ Sensitivity list: clock + asynchronous inputs (reset)
• The synchronous data inputs should not be included in the
sensitivity list

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Rules for the design of
synchronous sequential circuits
⚫ “Template” for the design of synchronous sequential
circuits

PROCESS( <clock + reset>)

BEGIN
IF < asynchronous initialization condition> THEN
-- Asynchronous initialization
ELSIF < active clock edge> THEN
-- Synchronous behavior
END IF;
END PROCESS;

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Inference of registers and
flip-flops
⚫ Every signal that is assigned between IF clk’EVENT ... and
END IF infers a flip-flop

-- Combinational adder -- Registered adder

PROCESS (a, b) PROCESS (clk)
BEGIN BEGIN
s <= a AND b; IF clk’EVENT AND clk = ‘1’ THEN
END PROCESS; s <= a AND b;
END IF;
END PROCESS;

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Inference of registers and
flip-flops
⚫ A register may not have -- Registered Adder
reset, but a reset signal -- Incorrect initialization!
always needs an PROCESS (clk)
associated register!
BEGIN
⚫ Combinational logic must IF reset = ‘1’ THEN
not be purposely a <= ‘0’;
initialized (it is indirectly b <= ‘0’;
initialized) s <= ‘0’;
ELSIF clk’EVENT AND clk = ‘1’ THEN
s <= a AND b;
END IF;
END PROCESS;

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Examples
⚫ Design a JK falling-edge triggered flip-flop
JK Flip-flop
(Jump & Kill)
J K Q’
0 0 Q
0 1 0
1 0 1
1 1 /Q

ENTITY jk_flip_flop IS
PORT ( reset: IN STD_LOGIC;
clk: IN STD_LOGIC;
j, k: IN STD_LOGIC;
q: OUT STD_LOGIC);
END jk_flip_flop;

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Solution: JK flip-flop
ARCHITECTURE a OF jk_flip_flop IS
BEGIN
PROCESS (reset, clk) It is not necessary to cover
BEGIN all cases
IF reset = ‘1’ THEN • In the missing case
q <= ‘0’; (j = ‘0’ AND k = ‘0’), the
ELSIF clk’EVENT AND clk = ‘0’ THEN flip-flop keeps its state
IF j = ‘0’ AND k = ‘1’ THEN
q <= ‘0’;
ELSIF j = ‘1’ AND k = ‘0’ THEN
q <= ‘1’;
ELSIF j = ‘1’ AND k = ‘1’ THEN
q <= NOT q; Problem: q has been declared as output
END IF; but it is also used as input
END IF;
END PROCESS;
END a;

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Solution: JK flip-flop
ARCHITECTURE a OF jk_flip_flop IS
SIGNAL s: STD_LOGIC; Solution: intermediate
BEGIN signal
PROCESS (reset, clk)
BEGIN
IF reset = ‘1’ THEN
s <= ‘0’;
ELSIF clk’EVENT AND clk = ‘0’ THEN
IF j = ‘0’ AND k = ‘1’ THEN
s <= ‘0’;
ELSIF j = ‘1’ AND k = ‘0’ THEN
s <= ‘1’;
ELSIF j = ‘1’ AND k = ‘1’ THEN
s <= NOT s;
END IF;
END IF;
END PROCESS;
q <= s;
END a;

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Solution: JK flip-flop
ARCHITECTURE a OF jk_flip_flop IS
SIGNAL s: STD_LOGIC;
SIGNAL inputs: STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
inputs <= j & k;
PROCESS (reset, clk)
BEGIN
IF reset = ‘1’ THEN
s <= ‘0’; Alternative solution
ELSIF clk’EVENT AND clk = ‘0’ THEN using CASE
CASE inputs IS
WHEN “01” => s <= ‘0’;
WHEN “10” => s <= ‘1’;
WHEN “11” => s <= NOT s;
END CASE;
END IF;
END PROCESS;
q <= s;
END a;

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Example: edge detector
⚫ Egde detector: circuit that detects an input (e) edge. The output (f)
must be active during a single clock cycle whatever the length of the
input pulse
ENTITY edge_detector IS
PORT ( reset: IN STD_LOGIC;
clk: IN STD_LOGIC;
e: IN STD_LOGIC;
f: OUT STD_LOGIC);
END edge_detector;

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Example: edge detector
ARCHITECTURE a OF edge_detector IS
BEGIN
PROCESS (reset, e)
BEGIN
IF reset = ‘1’ THEN
f <= ‘0’;
ELSIF e’EVENT AND e = ‘1’ THEN Problem: e is not the clock
f <= ‘1’; • VIOLATION of synchronous
principle!
END IF;
END PROCESS;
END a;

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Example: edge detector
ARCHITECTURE a OF edge_detector IS
BEGIN
PROCESS (reset, clk)
BEGIN
Synchronous solution
IF reset = ‘1’ THEN • q stores the previous input
q <= ‘0’; value
ELSIF clk’EVENT AND clk = ‘1’ THEN • f is asserted when input e
q <= e; is ‘1’ and previously (q) it
was ‘0’
END IF;
END PROCESS;

f <= ‘1’ WHEN e = ‘1’ and q = ‘0’ ELSE ‘0’;

END a;

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