Scribd
Upload
13 views

ECE172 Digital Circuits and Systems Ch04 HVT 2023-CombinationalCircuits BuildingBlocks

Uploaded by

thanhfacebook123dn
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
13 views

ECE172 Digital Circuits and Systems Ch04 HVT 2023-CombinationalCircuits BuildingBlocks

Uploaded by

thanhfacebook123dn
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 40

ECE 172.

Digital Systems
Chapter 4. Combinational Circuits
& Building Blocks
Huỳnh Việt Thắng
Electronic & Telecommunication Engineering
DaNang University of Science and Technology
[email protected]

Feb. 2023
References
• [Chapter 6] Stephen Brown and Zvonko Vranesic,
“Fundamentals of Digital Logic with Verilog
Design”, 3rd Edition
Overview
• Combinational Circuits are systems whose outputs
are only logic function according to the inputs

• Logic gates NOT, AND, OR, NOR, NAND, XOR,


XNOR are basic logic elements, and are also
known as simple combinational systems.

• NOR and NAND gates are fully combinational


systems.

3
Characteristics of Combinational Systems
• Consider a combinational system with n inputs
and m outputs

• The basic characteristic of a combinational system


is that the output signal at each time instant
depends only on the value of the input signals at
that time and does not depend on the value of the
output signals at previous times.
4
Design steps for Combinational Systems

1. Forming the Truth Table(*)


2. Derive the logic functions
3. Derive logic circuit diagram
4. Describe logic functions with Hardware Description
Language (Verilog/VHDL) (if necessary)
5. Simulate the circuit(**) (if necessary)
6. Hardware Implementation & in-circuit Verification

(*) Considered as the most important step


(**) Proteus is recommended

5
Contents
• Multiplexer (MUX)
• De-Multiplexer (DEMUX)
• Encoder
• Decoder
• Code conversion: BCD to 7-segment decoder
MUX & DEMUX
in Communication System

Channel

7
Multiplexer (MUX) – Mạch ghép kênh
• Multiplexer (channel selector) is a circuit that has
the function of selecting 1 out of N input channels
to bring to a single output (called a common
transmission line)

• Converts input parallel data to output serial data


(chuyển dữ liệu song song thành dữ liệu nối tiếp)

8
Multiplexers: 2-to-1 MUX
s
s f
w0 0 w0
f 0
w1 1 1 w1

(a) Graphical symbol (b) Truth table

w0 w0

s f s

w1 w1 f

(c) Sum-of-products circuit (d) Circuit with transmission gates

Figure 6.1. A 2-to-1 multiplexer.


Transmission Gate
- A transmission gate: switch that connects x to f
- A switch is turned on by setting VS = 5V & V!S = 0V.
s
+ Vx= 0V: NMOS is
turned on, Vf = 0 (drain is
x f s f pulled down to Gnd –
0 Z source)
s
1 x + Vx= 5V: PMOS is
turned on, Vf = 5V (drain
(a) Circuit (b) Truth table
is pulled up to VDD –
source)
s = 0
e
x f=Z s
x f
s = 1 x f
x f=x s

(c) Equivalent circuit (d) Graphical symbol (e) Implementation


4-to-1 MUX

Using 2-to-1 MUXs to build a


4-to-1 MUXs
Verilog implementation
1. Write the Verilog code to implement the 2-to-1 MUX?
(Let’s name this module “mux21”)
2. Write the Verilog code to implement one 4-to-1 MUX
(“mux41”) using the pre-designed module
“mux21”
3. Write the Verilog code to implement one 16-to-1
MUX (“mux161”) using the pre-designed module
“mux41”
Example 6.2: Crossbar Switch

• The logic blocks (in the FPGA) have


two inputs, and there are four tracks
in each routing channel.
• Each of the programmable switches
that connects a logic block input or
output to an interconnection wire is
shown as an X.

1. Explain the operation and write the


truth table for the circuit
2. Write Verilog code to implement
the circuit using the pre-designed
“MUX21” from previous example
Implementation of Lookup Table (LUT)

• See also: Shannon’s expansion (section 6.1.2)


Synthesis of logic function using MUX
Synthesis of the following function using only one 4-
to-1 MUX and necessary logic gates:
f (A, B, C) = (1, 3, 5, 6) = 𝐴ҧ𝐵𝐶 ҧ
ത + 𝐴𝐵𝐶 ത + 𝐴𝐵𝐶.ҧ
+ 𝐴𝐵𝐶

Read Sec. “6.1.1 Synthesis of logic function using Multiplexers”


Encoders
• Binary Encoders:
– A binary encoder encodes information from 2n inputs into an n-bit
code, as indicated in Figure 6.22. Exactly one of the input signals
should have a value of 1, and the outputs present the binary
number that identifies which input is equal to 1.
– Encoders are used to reduce the number of bits needed to represent
given information. A practical use of encoders is for
transmitting/storing information in a digital system (fewer
wires/bits).
–
Encoders (cont.)
• Priority Encoders:
– In a priority encoder each input has a priority level associated with
it. The encoder outputs indicate the active input that has the highest
priority. When an input with a high priority is asserted, the
other inputs with lower priority are ignored.
– Practical Priority encoder TTL ICs: 74147, 74148
Encoders (cont.)
• Priority Encoders:
– Define a set of intermediate signals:
74148
A 8-to-3 priority encoder
Application: 16-to-4 Priority Encoder (active low)
Application: 16-to-4 Priority Encoder (active high)
Propagation delay & power dissipation
Decoders
• Decoder circuits are used to decode encoded information.
• A binary decoder, depicted in Figure 6.15, is a logic circuit with n inputs and
2n outputs. Only one output is asserted at a time, and each output
corresponds to one valuation of the inputs.
• The decoder also has an enable input, En, that is used to disable the outputs;
if En = 0, then none of the decoder outputs is asserted. If En = 1, the
valuation of wn−1 · · · w1w0 determines which of the outputs is asserted.

• An n-bit binary code in which exactly one of the bits is set to 1 at a time is
referred to as one-hot encoded, meaning that the single bit that is set to 1 is
deemed to be “hot.” The outputs of a binary decoder are one-hot encoded.
2-to-4 Decoder
3-to-8 Decoder
• 3-to-8 Decoder using 2-to-4 Decoders
4-to-16 Decoder
Using Decoder & Tri-state Buffers to
implement a MUX
74138, 74139 Decoder/Demultiplexer
Decoding memory blocks
• Example 6.11
Decoding memory blocks
BCD-to-7-Segment Decoder
(Giải mã LED 7 đoạn)
• Seven Segments Display LED

32
BCD-to-7-Segment Decoder (cont.)
• Common Anode 7 Segments (Anode chung = cực + chung)
• Common Cathode 7 Segments (Cathode chung = cực - chung)

• For each type of 7-segment LED, there is a separate


decoder IC
33
Common Anode 7-seg LED decoder
(Practical Ics: 7447/74247)
• The anodes of the LED segments are tied to Vdd
– to control LED segment ON: control pin = 0
– to control LED segment OFF: control pin = 1

• display “0”: a=b=c=d=e=f=0; g=1.


• display “5”: a=c=d=f=g=0; b=e=1.

34
Common Anode 7-seg LED decoder (cont.)
• Truth Table

35
7-Segment Decoder Practical ICs

• 7447: Decoder IC for Common Anode 7-segment LED


• 4511: Decoder IC for Common Cathode 7-segment LED
37
38
Exercises
Exercise 6.1
w1 w2 w3 f
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1

You might also like