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EC361 Digital System Design

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Krishnapriyasudhakaran Krishna
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11 views

EC361 Digital System Design

Uploaded by

Krishnapriyasudhakaran Krishna
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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COURSE YEAR OF

CODE COURSE NAME L-T-P-C INTRODUCTION


EC361 Digital System Design 3-0-0-3 2016
Prerequisite: EC207 Logic Circuit Design
Course objectives:
1. To study synthesis and design of CSSN
2. To study synthesis and design of ASC
3. To study hazards and design hazard free circuits
4. To study PLA folding
1. To study architecture of one CPLDs and FPGA family
Syllabus:
Clocked synchronous networks, asynchronous sequential circuits, Hazards, Faults, PLA,
CPLDs and FPGA
Expected outcome:
The student will be able:
1. To analyze and design clocked synchronous sequential circuits
2. To analyze and design asynchronous sequential circuits
3. To apply their knowledge in diagnosing faults in digital circuits, PLA
4. To interpret architecture of CPLDs and FPGA
Text Books:
1. Donald G Givone, Digital Principles & Design, Tata McGraw Hill, 2003
2. John F Wakerly, Digital Design, Pearson Education, Delhi 2002
3. John M Yarbrough, Digital Logic Applications and Design, Thomson Learning
References:
1. Miron Abramovici, Melvin A. Breuer and Arthur D. Friedman, Digital Systems Testing
and Testable Design, John Wiley & Sons Inc.
2. Morris Mano, M.D.Ciletti, Digital Design, 5th Edition, PHI.
3. N. N. Biswas, Logic Design Theory, PHI
4. Richard E. Haskell, Darrin M. Hanna , Introduction to Digital Design Using Digilent
FPGA Boards, LBE Books- LLC
5. Samuel C. Lee, Digital Circuits and Logic Design, PHI
6. Z. Kohavi, Switching and Finite Automata Theory, 2nd ed., 2001, TMH
Course Plan
Module Course content End
Sem.
Hours
Exam
Marks
Analysis of clocked Synchronous Sequential Networks(CSSN) 2
Modelling of CSSN – State assignment and reduction 1
Design of CSSN 2 15
I
Iterative circuits 1
ASM Chart and its realization 2
Analysis of Asynchronous Sequential Circuits (ASC) 2
Flow table reduction- Races in ASC 1
II State assignment problem and the transition table- Design of 15
2
AS
Design of Vending Machine controller. 2
FIRST INTERNAL EXAM
Hazards – static and dynamic hazards – essential 1
Design of Hazard free circuits – Data synchronizers 1
III Mixed operating mode asynchronous circuits 1 15
Practical issues- clock skew and jitter 1
Synchronous and asynchronous inputs – switch bouncing 2
Fault table method – path sensitization method – Boolean
2
difference method
IV Kohavi algorithm 2 15
Automatic test pattern generation – Built in Self Test(BIST) 3
SECOND INTERNAL EXAM
PLA Minimization - PLA folding 2
Foldable compatibility Matrix- Practical PLA 2
V 20
Fault model in PLA 1
Test generation and Testable PLA Design. 3
CPLDs and FPGAs - Xilinx XC 9500 CPLD family, functional
3
block diagram– input output block architecture - switch matrix
VI 20
FPGAs – Xilinx XC 4000 FPGA family – configurable logic
3
block - input output block, Programmable interconnect
END SEMESTER EXAM

Question Paper Pattern ( End semester exam)

Max. Marks: 100 Time : 3 hours

The question paper shall consist of three parts. Part A covers modules I and II, Part B covers
modules III and IV, and Part C covers modules V and VI. Each part has three questions
uniformly covering the two modules and each question can have maximum four subdivisions.
In each part, any two questions are to be answered. Mark patterns are as per the syllabus with
50 % for theory, derivation, proof and 50% for logical/numerical problems.

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