IC Compiler II Update Training

Data Model

Version O-2018.06-SP2, O-2018.06-SP4, and P-2019.03

March, 2019
CONFIDENTIAL INFORMATION
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information of Synopsys. You are not permitted to disseminate or use any of
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without prior written authorization.

IMPORTANT NOTICE
In the event information in this presentation reflects Synopsys’ future plans, such plans
are as of the date of this presentation and are subject to change. Synopsys is not
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functionality discussed in this presentation. Additionally, Synopsys’ services and products
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or a mutually agreed upon written contract with Synopsys.

© 2019 Synopsys, Inc. 2

 Data Model Enhancements
(O-2018.06-SP2, O-2018.06-SP4, and P-2019.03)

Database Management Design and Tech Data Tcl Interfaces

• Analog Pin Related Improvement (O-2018.06-SP2) • Shaping Constraints (O-2018.06-SP2)
• Virtual Interface Blocks (VIB) for 3DIC (O-2018.06-SP2) • report_unbound Support for Missing Layers/Purpose
• Via Matrix Support (O-2018.06-SP4) (O-2018.06-SP2)
• Voltage Area Rule Hierarchy Options (O-2018.06-SP4) • Netlist Checking Enhancements (O-2018.06-SP4)
• Rule Based Name Matching (O-2018.06-SP4)
• Application Option Tcl Command Enhancements
Data Import and Export (O-2018.06-SP4)
• Instance-Specific Mask Shapes during Stream Out • Placement Attractions Support (P-2019.03)
(O-2018.06-SP2) • Supernet Enhancements (P-2019.03)
• Writing Routing Constraints (O-2018.06-SP4) • Usage Support for n-D Buses (P-2019.03)
• write_def Support for Physical Hierarchy Traversal • Message/Logfile Unification (P-2019.03)
(O-2018.06-SP4) • Label-Based Linking (P-2019.03)
• PMJ Via Ladder Support in Read/Write DEF (P-2019.03) • Identifying Computing Environment Issues (P-2019.03)
• Read/Write Verilog Support for n-D Buses (P-2019.03)

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Database Management
• Analog Pin Related Improvement in NDM (O-2018.06-SP2)
• Virtual Interface Blocks (VIB) for 3DIC (O-2018.06-SP2)
• Via Matrix Support (O-2018.06-SP4)
• Voltage Area Rule Hierarchy Options (O-2018.06-SP4)

© 2019 Synopsys, Inc. 4

Analog Pin Related Improvement (O-2018.06-SP2)

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Analog Pin Related Improvement
Overview

• In previous releases, if a signal net was connected to a lib_pin with the Liberty is_analog
attribute set on it, its type remained signal only

• Starting in O-2018.06-SP2, the IC Compiler II tool marks the net type of the net, which
connects to the analog library pin (lib_pin with the is_analog Liberty attribute set on it), as
analog_signal or analog_ground or analog_power
– If the lib_pin has the is_analog Liberty attribute set and the port type of lib pin is signal, the net type
of the connected net is set to analog_signal
– If the lib_pin has the is_analog Liberty attribute set and the port type of lib pin is power/ground, the
net type of the connected net is set to analog_power or analog_ground

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Analog Pin Related Improvement
New Attribute

• To control the net_type automatic inference behavior, use the new attribute
net_type_policy, the default for this attribute is auto
– When net type is set explicitly by creating the net using the -power, -ground, -tie_high, or
-tie_low options or by using the set_attribute command on an existing net, net_type_policy
will become override
– For nets created without the -power, -ground, -tie_high, or -tie_low options, net_type_policy
will be auto
– If the net_type_policy is auto and net is connected to an analog pin, then the net_type will become
as analog_*
– When the net_type_policy is override , then net_type is not changed, even if it is connected to
analog pin

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Analog Pin Related Improvement
Usage
For example:

icc2_shell> get_attribute [get_lib_pins */vddif] is_analog • The net_type attribute is reset back to the
true
icc2_shell> get_attribute [get_nets pad[0]] net_type
original value when all analog pins are
signal disconnected from the net
icc2_shell> get_attribute [get_nets pad[0]] net_type_policy
auto
icc2_shell> connect_net pad[0] [get_pins C/vddif] • For existing saved library, iteration would be
icc2_shell> get_attribute [get_nets pad[0]] net_type
analog_signal done to check the lib pin’s attribute during
icc2_shell> disconnect_net pad[0] [get_pins C/vddif] link process and then the net_type of
icc2_shell> get_attribute [get_nets pad[0]] net_type connected net will be changed to
signal analog_signal/analog_ground/analog_
icc2_shell> create_net -ground A
icc2_shell> get_attribute [get_nets A] net_type_policy power
override
icc2_shell> get_attribute [get_nets A] net_type
groud
icc2_shell> connect_net A [get_pins C/vddif]
icc2_shell> get_attribute [get_nets A] net_type
groud

© 2019 Synopsys, Inc. 8

Virtual Interface Blocks (VIB) for 3DIC (O-2018.06-SP2)

© 2019 Synopsys, Inc. 9

Virtual Interface Blocks (VIB) for 3DIC
Overview

• The IC Compiler II tool supports two styles of the virtual interface block
(VIB) consisting of the ports, nets, shapes, and vias at the interface
between two stacked dies
– In-netlist model: VIBs are instantiated in the top-level netlist and are written
into the netlist
– Top-level model: VIBs are instantiated in the top-level netlist, but are not
written into the netlist

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Virtual Interface Blocks (VIB) for 3DIC
User Interface

• Two new commands introduced to create/remove the virtual interface

block:
– create_3d_virtual_blocks
– remove_3d_virtual_blocks

• Two new attributes introduced on block object:

– bond_style
– virtual_blocks

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Virtual Interface Blocks (VIB) for 3DIC
Usage

• The commands create_3d_virtual_blocks and remove_3d_virtual_blocks

create/remove virtual blocks for each die-to-die and die-to-interposer interface.

• You specify how many layers are of interest in the analysis. This determines the routing and
cut layer shapes that are copied into the VIB.

• Only ports, which are connected together in the top level, are copied to the VIB
– For example, if die1/portA and die2/portB are connected to each other in the top, they are copied
to the VIB. Their names will be die1.portA and die2.portB in the VIB.

• If the ports are PG and have the same name, only a single port is created on the VIB
– For example, if die1/VDD and die2/VDD are power ports and connected to each other in the top, one
power port named VDD is created on the VIB.

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Virtual Interface Blocks (VIB) for 3DIC
Stream Out

• As the VIB created for the DIEs by command create_3d_virtual_blocks, is

an internal design in database. Starting from O-2018.06-SP2, write_gds and
write_oasis are improved to output the VIB content

• There are two ways for write_gds/write_oasis to output the GDSII, OASIS
file for a VIB
– Specifying the virtual block by option –design of write_gds/write_oasis
– Specifying the virtual block by current_block, and running write_gds/write_oasis
directly

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Via Matrix Support (O-2018.06-SP4)

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Via Matrix Support
Overview and Benefit

• In IC Compiler II version N-2017.09, the via_matrix object was introduced and supported
– Starting in version O-2018.06-SP4, the via matrix feature is generally available in the tool and new
enhancements include support for mask patterns and via matrix editing.

• Using via matrixes significantly reduces the disk size and memory usage of blocks that
contains a large number of PG vias.

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Definition of Via Matrix
via_def, base_via, and via_matrix

• The via_def is the via definition from which to create the via matrix.
– There can be only one via definition for a via matrix.

• The basic element in the via matrix is called base_via, which is created from a specific via_def
– The base_via can be a simple via, multi-cut via, or custom via

• The via matrix is a matrix of the base_via

A base via in via matrix Via matrix with 5 base vias, each base via has 2 cuts

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Definition of Via Matrix
Creation of base_via

• A base_via of the via matrix is created from via_def according to these rules
– If the via_def is a simple via, and the row and column for the base_via is set to 1x1, then a simple
single cut base_via is created

– If the via_def is a simple via and the rows and columns for the base via are greater than 1x1, then a
simple multi-cut base_via is created
– The rows and columns should not be less than what the via_def defines.
– Every cut is included by default or specified by a cut pattern.

– If the via_def is a custom via type, then a custom base_via is created.

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Via Matrix
Examples
• A via matrix is a matrix of one of the following base vias
– Simple via
create_via_matrix -cut_mask_constraint {{0 0 mask_one}} \
-cut_mask_pattern uniform -lower_mask_pattern arbitrary \
-net {VSS} -orientation R0 -origin {30 30} -pitch {1 1.2} \
-shape_use lib_cell_pin_connect -size {3 5} \
-upper_mask_constraint {{0 0 mask_one}} \
-upper_mask_pattern uniform -via_def {VIA23}
– Simple multi-cut via
create_via_matrix -base_size {1 2} \
-cut_mask_constraint {{0 0 mask_one}} \
-cut_mask_pattern uniform -lower_mask_pattern arbitrary \
-net {VSS} -orientation R0 -origin {30 30} -pitch {1 1.2} \
-shape_use lib_cell_pin_connect -size {3 5} \
-upper_mask_constraint {{0 0 mask_one}} \
-upper_mask_pattern uniform -via_def {VIA23}
– Custom via
create_via_matrix -cut_mask_constraint {{0 0 mask_one}} \
-cut_mask_pattern uniform -lower_mask_pattern arbitrary \
-net {VSS} -orientation R0 -origin {30 30} -pitch {1 1.2} \
-shape_use lib_cell_pin_connect -size {3 5} \
-upper_mask_constraint {{0 0 mask_one}} \
-upper_mask_pattern uniform -via_def {VIA23C}

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Mask Pattern of via_matrix
uniform (default)
• The mask pattern of via_matrix applies to the via_matrix, not the pattern inside the base via
icc2_shell> get_attribute [get_via_defs -library [current_lib] VIA23] mask_pattern
uniform
icc2_shell> get_attribute [get_layer VIA2] number_of_masks
2
icc2_shell> create_via_matrix -net {VSS} -via_def {VIA23} -base_size {1 2} \
-cut_mask_pattern uniform \
-lower_mask_pattern uniform \
-upper_mask_pattern uniform \
-cut_mask_constraint {{0 0 mask_one }} \
-origin {50 60} -pitch {1 1.2} -shape_use lib_cell_pin_connect -size {2 4}

icc2_shell> get_attribute [get_via_defs -library [current_lib] VIA34] mask_pattern

alternating
icc2_shell> get_attribute [get_layer VIA3] number_of_masks
2
icc2_shell> create_via_matrix -net {VSS} -via_def {VIA34} -base_size {1 2} \
-cut_mask_pattern uniform \
-lower_mask_pattern uniform \
-upper_mask_pattern uniform \
-cut_mask_constraint {{0 0 mask_one}}\
-origin {60 60} -pitch {1 1.2} -shape_use lib_cell_pin_connect -size {2 4}

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Mask Pattern of via_matrix
arbitrary
• The mask pattern of via_matrix applies to the via_matrix, not the pattern inside the base via
icc2_shell> get_attribute [get_via_defs -library [current_lib] VIA23] mask_pattern
uniform
icc2_shell> get_attribute [get_layer VIA2] number_of_masks
2
icc2_shell> create_via_matrix -net {VSS} -via_def {VIA23} -base_size {1 2} \
-cut_mask_pattern arbitrary \
-lower_mask_pattern uniform \
-upper_mask_pattern uniform \
-cut_mask_constraint {{0 0 mask_two } {0 1 mask_one} {0 2 mask_one} {0 3
mask_one} {1 0 mask_one} {1 1 mask_one} {1 3 mask_one}} \
-origin {50 60} -pitch {1 1.2} -shape_use lib_cell_pin_connect -size {2 4}

icc2_shell> get_attribute [get_via_defs -library [current_lib] VIA34] mask_pattern

alternating
icc2_shell> get_attribute [get_layer VIA3] number_of_masks
2
icc2_shell> create_via_matrix -net {VSS} -via_def {VIA34} -base_size {1 2} \
-cut_mask_pattern arbitrary \
-lower_mask_pattern uniform \
-upper_mask_pattern uniform \
-cut_mask_constraint {{0 0 mask_two } {0 1 mask_one} {0 2 mask_one} {0 3
mask_one} {1 0 mask_one} {1 1 mask_one} {1 3 mask_one}} \
-origin {60 60} -pitch {1 1.2} -shape_use lib_cell_pin_connect -size {2 4}

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Mask Pattern of via_matrix
alternate_columns, alternate_rows
• The mask pattern of via_matrix applies to the via_matrix, not the pattern inside the base via
icc2_shell> get_attribute [get_via_defs -library [current_lib] VIA23] mask_pattern
uniform
icc2_shell> get_attribute [get_layer VIA2] number_of_masks
2
icc2_shell> create_via_matrix -net {VSS} -via_def {VIA23} -base_size {1 2} \
-cut_mask_pattern alternate_columns \
-lower_mask_pattern uniform \
-upper_mask_pattern uniform \
-cut_mask_constraint {{0 0 mask_one}} \
-origin {50 60} -pitch {1 1.2} -shape_use lib_cell_pin_connect -size {2 4}

icc2_shell> get_attribute [get_via_defs -library [current_lib] VIA34] mask_pattern

alternating
icc2_shell> get_attribute [get_layer VIA3] number_of_masks
2
icc2_shell> create_via_matrix -net {VSS} -via_def {VIA34} -base_size {1 2} \
-cut_mask_pattern alternate_rows \
-lower_mask_pattern uniform \
-upper_mask_pattern uniform \
-cut_mask_constraint {{0 0 mask_one}} \
-origin {60 60} -pitch {1 1.2} -shape_use lib_cell_pin_connect -size {2 4}

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Via Matrix Support
User Interface

• The following commands are added to create, remove, update, report and edit via matrixes
convert_vias_to_via_matrix # Converts normal vias to via matrix
convert_via_matrixes_to_vias # Converts via matrixes to normal vias
create_via_matrix # Creates a via matrix
get_via_matrixes # Creates a collection of via matrixes
remove_via_matrixes # Removes via matrixes
report_via_matrixes # Reports via matrix information
edit_via_matrix # Edits a via matrix

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Via Matrix Support
Usage: Create Via Matrix

• To utilize the via matrix in the design, you can

– Create the PG via in the via matrix format while performing PG routing with create_pg_vias and
create_pg_stapling_vias

– Import the “DO xxx STEP” structure in the DEF file into the block as a via matrix

– Convert the normal via into via_matrix manually if the PG data is prepared in the 3rd party tools
convert_vias_to_via_matrix [get_vias -filter {via_def_name==VIA0RECT_PG && net.name==VSS}]
convert_vias_to_via_matrix [get_vias -filter {via_def_name==VIA0RECT_PG && net.name==VDD}]

– Manually create via matrix with create_via_matrix command

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Creating Via Matrixes
While Performing PG Routing

• To create a PG via in via matrix format while performing PG routing, you can use the new -
create_via_matrix option of the create_pg_vias and create_pg_stapling_vias
commands

• This is the recommended approach to utilize via matrixes in IC Compiler II flow.

• Note that the create_pg_vias -create_via_matrix command must be used with the
-pitch and –start options

• See the man page and PG routing usage guide for details.

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Via Matrix Support
Usage: Data In/Out in DEF

• The write_def command writes out via matrixes to the DEF SPECIALNETS section
– If the via matrix is a fully-populated matrix and all the base vias have the same mask pattern, the via
matrix is written as an arrayed instance defined with one statement:
" (x y) [MASK viaMaskNum] viaName [orient] DO numx BY numY STEP stepX stepY "

– Otherwise, write_def writes the via matrix behind the first valid base via in the form of a pragma.
Other base vias only have the ID of the via matrix in the following format:
#SNPS_VIA_MATRIX id [numX numY xPitch yPitch xOrigin yOrigin orient baseOrient
BotMaskPattern CutMaskPattern TopMaskPattern viaPattern]

• The read_def command reads the DEF “DO … STEP” structure as a via matrix in the design
library.
– To do this, set the file.def.support_via_matrix application option to true before running the
read_def command

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Creating Via Matrixes
Example of convert_vias_to_via_matrix

• If the PG via was created in a third-party tool and imported into the block as a normal via, you
can also convert the via into a via matrix by using the convert_vias_to_via_matrix
command

• You can also convert via matrixes into normal vias by using
convert_via_matrixes_to_vias
– For example, when the mask pattern of the individual via needs to be changed
– Or the individual via should be removed as a hole.

convert_vias_to_via_matrix convert_via_matrixes_to_vias

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Creating Via Matrixes
Example Using create_via_matrix

• You can create via matrixes manually by using the create_via_matrix command

create_via_matrix -base_size {1 2} \
-cut_mask_constraint {{0 0 mask_one}} \
-cut_mask_pattern uniform \
-lower_mask_pattern arbitrary -net {VSS} \
-orientation R0 -origin {30 30} \
-pitch {1 1.2} -shape_use lib_cell_pin_connect \
-size {3 5} -upper_mask_constraint {{0 0 mask_one}} \
-upper_mask_pattern uniform -via_def {VIA23}

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Editing Via Matrixes
Example Using edit_via_matrix

• You can remove the base_vias • You can add base_vias into a
from a via matrix by specifying via matrix by specifying a
a region region
icc2_shell> set pb1 icc2_shell> edit_via_matrix -add
[get_placement_blockage] {{61.6950 59.0400} {64.7800
{pb_0} 61.0550}} VIA_MATRIX_1

icc2_shell> edit_via_matrix – 1
delete [get_attribute $pb1
bounding_box] *
1

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Via Matrix Support
Usage: Data In/Out in GDSII and OASIS

• When writing an OASIS or GDSII file, you must specify the -via_matrix_property option with the
write_gds or write_oasis command so that the via matrix information is written into the stream file as
a property. Later, when you read the stream file back into the tool, the tool restores the via matrix.
– If you do not plan to read the via matrix back into the design, you do not need to use this option
– This option does not change any geometry in the stream file

• To restore the via matrix information from the stream file, use the -via_matrix_property option with
the read_gds or read_oasis command. This creates the via in via matrix format in the design library
– Note: the via matrix data is created as fill data since they are stored as array data in the stream files.
– Note: the property value must be the same in the write_gds and read_gds commands.

• The via_matrix_prop_attribute integer syntax is added for the layer mapping file. This syntax
provides the same function as the -via_maxtrix_property integer option of the read_gds,
read_oasis, write_gds, and write_oasis commands

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Via Matrix Support
Usage: Support in IC Compiler II

• The via matrix is fully supported by all IC Compiler II applications

– The support in most cases is on by default

– For the legalizer, via matrix support is only available with the new placer design rule checker
(NPLDRC). Therefore, you must enable the following application option：

set_app_options -name place.legalize.enable_advanced_prerouted_net_check -value true

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Via Matrix Support
Usage: Support in StarRC / IC Validator

• IC Validator has supported via matrixes starting with version N-2017.06

• StarRC has supported via matrixes starting with version N-2017.06

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Voltage Area Rule Hierarchy Options (O-2018.06-SP4)

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Voltage Area Rule Hierarchy Options
Overview

• In the N-2017.09-SP6 release, the -allow_logical_feedthrough option was added to the

create_voltage_area_rule command, allowing you to specify whether logical-feedthrough
buffers could be inserted in the voltage area.

• Starting in version O-2018.06-SP4, you can also specify the hierarchies within the voltage
area in which logical-feedthrough buffers are allowed or not allowed.

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Voltage Area Rule Hierarchy Options
User Interface

• You can use the following new options of the create_voltage_area_rule command to
specify the hierarchies that can be used for logical-feedthrough buffer insertion:
 -include_logical_feedthrough_hierarchy cell_list
 -exclude_logical_feedthrough_hierarchy cell_list

• You can use the following new attributes on voltage_area_rule objects:

 included_logical_feedthrough_hierarchy
 excluded_logical_feedthrough_hierarchy
 is_top_logical_feedthrough_excluded
 is_top_logical_feedthrough_included

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Voltage Area Rule Hierarchy Options
Usage

• The two options can be specified only if the -allow_logical_feedthrough option is

specified as true, and they cannot be used together.

• When one of the two options is specified, only one voltage area can be specified by the
-voltage_areas option.

• If neither option is specified but the -allow_logical_feedthrough option is specified as

true, the tool can insert logical-feedthrough buffers in any hierarchy in the voltage area.

• The cell_list option value can only contain cells that are root cells of the power domains in
the specified voltage area.

• The cell_list option supports the “.” character to indicate that logical-feedthrough buffers
can be inserted into the top logical hierarchy.

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