Republic of the Philippines

NUEVA VIZCAYA STATE UNIVERSITY

Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023

College of Engineering
Bambang Campus

DEGREE Bachelor of Science in COURSE NO. ECE9

PROGRAM Electronics Engineering
SPECIALIZATION Instrumentation & COURSE TITLE Logic Circuits and Switching Theory
Control
YEAR LEVEL 3rd Year TIME FRAME 24 hrs WK NO. 10-13 IM 03
NO.

I. UNIT TITLE/CHAPTER TITLE

Combinational Logic Circuits

II. LESSON TITLE

1. Adders, Subtractors
2. Decoders, Encoders
3. Code Converter
4. Magnitude Comparator
5. Multiplexer, Demultiplexer

III. LESSON OVERVIEW

This lesson involves application of Boolean algebra, its minimization, and its logic gate implementation
into the design of combinational logic circuits.

IV. DESIRED LEARNING OUTCOMES

At the end of this lesson, the student should be able to:

1. Identify the functions of the different Combinational logic circuits

2. Analyze problems with the different logic circuits
3. Evaluate the different logic circuits according to their use
4. Implement different logic circuits
5. Design a functioning logic circuit

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reproduced for educational purposes only and not for commercial distribution.

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
V. LESSON CONTENT

3-1 INTRODUCTION
Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists
of logic gates whose outputs at any time are determined from only the present combination of inputs. A
combinational circuit performs an operation that can be specified logically by a set of Boolean functions.
In contrast, sequential circuits employ storage elements in addition to logic gates. Their outputs are a
function of the inputs and the state of the storage elements. Because the state of the storage elements
is a function of previous inputs, the outputs of a sequential circuit depend not only on present values of
inputs, but also on past inputs, and the circuit behavior must be specified by a time sequence of inputs
and internal states.

3-2 COMBINATIONAL CIRCUITS

A combinational circuit consists of input variables, logic gates, and output variables. Combinational
logic gates react to the values of the signals at their inputs and produce the value of the output signal,
transforming binary information from the given input data to a required output data. A block diagram of
a combinational circuit is shown below.

The n input binary variables come from an external source; the m output variables are produced by the
internal combinational logic circuit and go to an external destination. Each input and output variable
exists physically as an analog signal whose values are interpreted to be a binary signal that represents
logic 1 and logic 0. (NOTE: Logic simulators show only 0’s and 1’s, not the actual analog signals.) In
many applications, the source and destination are storage registers. If the registers are included with
the combinational gates, then the total circuit must be considered to be a sequential circuit.

For n input variables, there are 2n possible input combinations. For each possible input combination,
there is one possible output value. Thus, a combinational circuit can be specified with a truth table that
lists the output values for each combination of input variables. A combinational circuit also can be
described by m Boolean functions, one for each output variable. Each output function is expressed in
terms of the n input variables.

In IM-01, we learned about binary numbers and binary codes that represent discrete quantities of
information. The binary variables are represented physically by electric voltages or some other type of
signal. The signals can be manipulated in digital logic gates to perform required functions. In Chapter
2, we introduced Boolean algebra as a way to express logic functions algebraically. In Chapter 3, we
learned how to simplify Boolean functions to achieve economical (simpler) gate implementations. The
purpose of the current chapter is to use the knowledge acquired in previous chapters to formulate
systematic analysis and design procedures for combinational circuits. The solution of some typical
examples will provide a useful catalog of elementary functions that are important for the understanding
of digital systems. We’ll address two tasks: (1) Analyze the behavior of a given logic circuit, and (2)
synthesize a circuit that will have a given behavior.

There are several combinational circuits that are employed extensively in the design of digital systems.
These circuits are available in integrated circuits and are classified as standard components. They
perform specific digital functions commonly needed in the design of digital systems. In this chapter, we
introduce the most important standard combinational circuits, such as adders, subtractors,
comparators, decoders, encoders, and multiplexers. These components are available in integrated
circuits as medium-scale integration (MSI) circuits. They are also used as standard cells in complex
very large-scale integrated (VLSI) circuits such as application-specific integrated circuits (ASICs). The
standard cell functions are interconnected within the VLSI circuit in the same way that they are used in
multiple-IC MSI design.

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
3-3 ANALYSIS PROCEDURE
The analysis of a combinational circuit requires that we determine the function that the circuit
implements. This task starts with a given logic diagram and culminates with a set of Boolean functions,
a truth table, or, possibly, an explanation of the circuit operation. If the logic diagram to be analyzed is
accompanied by a function name or an explanation of what it is assumed to accomplish, then the
analysis problem reduces to a verification of the stated function. The analysis can be performed
manually by finding the Boolean functions or truth table or by using a computer simulation program.

The first step in the analysis is to make sure that the given circuit is combinational and not sequential.
The diagram of a combinational circuit has logic gates with no feedback paths or memory elements. A
feedback path is a connection from the output of one gate to the input of a second gate that forms part
of the input to the first gate. Feedback paths in a digital circuit define a sequential circuit and must be
analyzed according to certain procedures not covered in this chapter.

Once the logic diagram is verified to be that of a combinational circuit, one can proceed to obtain the
output Boolean functions or the truth table. If the function of the circuit is under investigation, then it is
necessary to interpret the operation of the circuit from the derived Boolean functions or truth table. The
success of such an investigation is enhanced if one has previous experience and familiarity with a wide
variety of digital circuits.

To obtain the output Boolean functions from a logic diagram, we proceed as follows:
1. Label all gate outputs that are a function of input variables with arbitrary symbols—but with
meaningful names. Determine the Boolean functions for each gate output.
2. Label the gates that are a function of input variables and previously labeled gates with other
arbitrary symbols. Find the Boolean functions for these gates.
3. Repeat the process outlined in step 2 until the outputs of the circuit are obtained.
4. By repeated substitution of previously defined functions, obtain the output Boolean functions in
terms of input variables.

The analysis of the combinational circuit of the figure below illustrates the proposed procedure. We
note that the circuit has three binary inputs—A, B, and C—and two binary outputs—F1 and F2.

The outputs of various gates are labeled with intermediate symbols. The outputs of gates that are a
function only of input variables are T1 and T2. Output F2 can easily be derived from the input variables.
The Boolean functions for these three outputs are
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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
F 2=AB+ AC + BCT 1=A + B+CT 2= ABC

Next, we consider outputs of gates that are a function of already defined symbols:
T 3=F 2 T 1 F 1=T 3 +T 2
'

To obtain F 1 as a function of A , B, and C , we form a series of substitutions as follows:

F 1=T 3 +T 2=F 2 T 1+ ABC =( AB+ AC + BC ) ( A + B+C )+ ABC ¿ ( A' + B' )( A ' + C' ) ( B ' +C ' ) ( A +B+ C ) + ABC
' '

¿ ( A' + B' C ' )( A B' + A C' + B C' + B' C ) + ABC¿ A' B C ' + A ' B' C+ A B' C' + ABC

If we want to pursue the investigation and determine the information transformation task achieved by
this circuit, we can draw the circuit from the derived Boolean expressions and try to recognize a familiar
operation. The Boolean functions for F 1 and F 2 implement a circuit discussed in Section 4-5. Merely
finding a Boolean representation of a circuit doesn’t provide insight into its behavior, but in this
example, we will observe that the Boolean equations and truth table for F 1 and F 2 match those
describing the functionality of what we call a full adder.

The derivation of the truth table for a circuit is a straightforward process once the output Boolean
functions are known. To obtain the truth table directly from the logic diagram without going through the
derivations of the Boolean functions, we proceed as follows:
1. Determine the number of input variables in the circuit. For n inputs, form the 2^n possible input
combinations and list the binary numbers from 0 to 2^n-1 in a table.
2. Label the outputs of selected gates with arbitrary symbols.
3. Obtain the truth table for the outputs of those gates which are a function of the input variables
only.
4. Proceed to obtain the truth table for the outputs of those gates which are a function of previously
defined values until the columns for all outputs are determined.

This process is illustrated with the circuit of the figure above. In the table below, we form the eight
possible combinations for the three input variables.

Truth Table for the Logic Diagram shown above.

'
A B C F2 F2 T1 T2 T3 F1
0 0 0 0 1 0 0 0 0
0 0 1 0 1 1 0 1 1
0 1 0 0 1 1 0 1 1
0 1 1 1 0 1 0 0 0
1 0 0 0 1 1 0 1 1
1 0 1 1 0 1 0 0 0
1 1 0 1 0 1 0 0 0
1 1 1 1 0 1 1 0 1

The truth table for F 2 is determined directly from the values of A , B, and C , with F 2 equal to 1 for any
'
combination that has two or three inputs equal to 1. The truth table for F 2 is the complement of that of
F 2. The truth tables for T 1 and T 2 are the OR and AND functions of the input variables, respectively.
' '
The values for T 3 are derived from T 1 and F 2: T 3 is equal to 1 when both T 1 and F 2 are equal to 1, and
T 3 is equal to 0 otherwise. Finally, F 1 is equal to 1 for those combinations in which either T 2 or T 3 or
both are equal to 1. Inspection of the truth table combinations for A , B, C , F 1, and F 2 shows that it is
identical to the truth table of the full adder given in Section 4.5 for x , y , z , S, and C , respectively.

Another way of analyzing a combinational circuit is by means of logic simulation. This is not practical,
however, because the number of input patterns that might be needed to generate meaningful outputs
could be very large. But simulation has a very practical application in verifying that the functionality of a
circuit actually matches its specification.
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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023

3-4 DESIGN PROCEDURE

The design of combinational circuits starts from the specification of the design objective and culminates
in a logic circuit diagram or a set of Boolean functions from which the logic diagram can be obtained.
The procedure involves the following steps:
1. From the specifications of the circuit, determine the required number of inputs and outputs and
assign a symbol to each.
2. Derive the truth table that defines the required relationship between inputs and outputs.
3. Obtain the simplified Boolean functions for each output as a function of the input variables.
4. Draw the logic diagram and verify the correctness of the design (manually or by simulation).

A truth table for a combinational circuit consists of input columns and output columns. The input
columns are obtained from the 2n binary numbers for the n input variables. The binary values for the
outputs are determined from the stated specifications. The output functions specified in the truth table
give the exact definition of the combinational circuit. It is important that the verbal specifications be
interpreted correctly in the truth table, as they are often incomplete, and any wrong interpretation may
result in an incorrect truth table.

The output binary functions listed in the truth table are simplified by any available method, such as
algebraic manipulation, the map method, or a computer-based simplification program. Frequently,
there is a variety of simplified expressions from which to choose. In a particular application, certain
criterial will serve as a guide in the process of choosing an implementation. A practical design must
consider such constraints as the number of gates, number of inputs to a gate, propagation time of the
signal through the gates, number of interconnections, limitations of the driving capability of each gate
(i.e., the number of gates to which the output of the circuit may be connected), and various other criteria
that must be taken into consideration when designing integrated circuits. Since the importance of each
constraint is dictated by the particular application, it is difficult to make a general statement about what
constitutes an acceptable implementation. In most cases, the simplification begins by satisfying an
elementary objective, such as producing the simplified Boolean functions in a standard form. Then the
simplification proceeds with further steps to meet other performance criteria.

3-5 COMBINATIONAL LOGIC

Half Adder
 a combinational circuit that can perform the addition of two binary numbers with one bit each
0 0 1 1 x
+0 +1 +0 +1  y
00 01 01 10

- The addition of two binary numbers is shown above. The augend and the addend are both
one bit each while the sum is composed of two bits. It follows the basic arithmetic for
addition of binary numbers.
- The two bits of the output are the sum (LSB) and the carry (MSB).
- For augend 0 and addend 0, the sum is 0 and the carry is 0.
- For augend 0 and addend 1, the sum is 1 and the carry is 0.
- For augend 1 and addend 0, the sum is 1 and the carry is 0.
- For augend 1 and addend 1, the sum is 0 and the carry is 1.

Half Adder
x y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

- The addition of two one-bit binary numbers with two-bit binary output is summarized in a
truth table as shown above.
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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
- As shown in the truth table, there are two inputs ( x , y ) and there are two outputs (C for
carry, S for sum). This is the truth table for a Half Adder combinational circuit.
- Extracting the Boolean functions for S and C gives us

'
S= x y+ xy ' C=xy

- The logic-gate implementation of the two Boolean functions is as shown below.

- Or

Full Adder
 a combinational circuit that can perform the addition of three binary numbers with one bit each
0 0 0 0 1 1 1 1 x
+0 +0 +1 +1 +0 +0 +1 +1  y
+0 +1 +0 +1 +0 +1 +0 +1 z
00 01 01 10 01 10 10 11

- The addition of three binary numbers is shown above. The augend and the two addends
are one bit each while the sum is composed of two bits. It follows the basic arithmetic for
addition of binary numbers.
- The two bits of the output are the sum (LSB) and the carry (MSB).
- For augend 0 and addends 0 and 0, the sum is 0 and the carry is 0.
- For augend 0 and addends 0 and 1, the sum is 1 and the carry is 0.
- For augend 0 and addends 1 and 0, the sum is 1 and the carry is 0.
- For augend 0 and addends 1 and 1, the sum is 0 and the carry is 1.
- For augend 1 and addends 0 and 0, the sum is 1 and the carry is 0.
- For augend 1 and addends 0 and 1, the sum is 0 and the carry is 1.
- For augend 1 and addends 1 and 0, the sum is 0 and the carry is 1.
- For augend 1 and addends 1 and 1, the sum is 1 and the carry is 1.

Full Adder
x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

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reproduced for educational purposes only and not for commercial distribution.

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
- The addition of three one-bit binary numbers with two-bit binary output is summarized in a
truth table as shown above.
- As shown in the truth table, there are three inputs ( x , y , z ) and there are two outputs (C for
carry, S for sum). This is the truth table for a Full Adder combinational circuit.
- Extracting the Boolean functions for S and C gives us

' ' ' ' ' '

S= x y z + x y z + x y z + xyz
S= x' ( y ' z + y z' ) + x ( y ' z' + yz )
'
S= x ( y ⊕ z ) + x ( y ⊙ z )

C=xy + yz + xz

- The logic-gate implementation of the two Boolean functions is as shown below.

Half Subtractor
 a combinational circuit that can perform the subtraction of two binary numbers with one bit each
0 0 1 1 x
-0 -1 -0 -1  y
0 1 1 0
B=0 B=1 B=0 B=0

- The subtraction of two binary numbers is shown above. The minuend and the subtrahend
are both one bit each while the difference is composed of one bit but with a borrow-bit (B)
included. It follows the basic arithmetic for subtraction of binary numbers.
- For minuend 0 and subtrahend 0, the difference is 0 and the borrow is 0.
- For minuend 0 and subtrahend 1, the difference is 1 and the borrow is 1.
- For minuend 1 and subtrahend 0, the difference is 1 and the borrow is 0.
- For minuend 1 and subtrahend 1, the difference is 0 and the borrow is 0.

Half Subtractor
x y B D

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

- The subtraction of two one-bit binary numbers is summarized in a truth table as shown
above.
- As shown in the truth table, there are two inputs ( x , y ) and there are two outputs ( B for
borrow, D for difference). This is the truth table for a Half Subtractor combinational circuit.
- Extracting the Boolean functions for D and B gives us

D=x ⊕ y B=x y
'

- The logic-gate implementation of the two Boolean functions is as shown below.

Full Subtractor
 a combinational circuit that can perform the subtraction of three binary numbers with one bit
each
0 0 0 0 1 1 1 1 x
-0 -0 -1 -1 -0 -0 -1 -1  y
-0 -1 -0 -1 -0 -1 -0 -1 z
0 1 1 0 1 0 0 1
B=0 B=1 B=1 B=1 B=0 B=0 B=0 B=1

- The subtraction of three binary numbers is shown above. The minuend and the two
subtrahends are one bit each while the difference is composed of one bit but with a borrow-
bit (B) included.
- For minuend 0 and subtrahends 0 and 0, the difference is 0 and the borrow is 0.
- For minuend 0 and subtrahends 0 and 1, the difference is 1 and the borrow is 0.
- For minuend 0 and subtrahends 1 and 0, the difference is 1 and the borrow is 0.
- For minuend 0 and subtrahends 1 and 1, the difference is 0 and the borrow is 1.
- For minuend 1 and subtrahends 0 and 0, the difference is 1 and the borrow is 0.
- For minuend 1 and subtrahends 0 and 1, the difference is 0 and the borrow is 1.
- For minuend 1 and subtrahends 1 and 0, the difference is 0 and the borrow is 1.
- For minuend 1 and subtrahends 1 and 1, the difference is 1 and the borrow is 1.

Full Subtractor
x y z B D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

- The subtraction of three one-bit binary numbers is summarized in a truth table as shown
above.
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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
- As shown in the truth table, there are three inputs ( x , y , z) and there are two outputs ( B for
borrow, D for difference). This is the truth table for a Full Subtractor combinational circuit.
- Extracting the Boolean functions for D and B gives us

' ' ' ' ' '

D=x y z + x y z + x y z + xyz
D=z ' ( x ' y + x ' y ) + z ( x ' y ' + xy )
'
D=z ( x ⊕ y ) + z ( x ⊙ y )

' '
B=x z + x y + yz

- The logic-gate implementation of the two Boolean functions is as shown below.

Code Converter
 Code converters are digital circuits that are used to convert the input information into a desired
code. Let’s take a 3-bit Binary to Excess-3 Code Converter as an example.
- This code converter takes a 3-bit binary input and converts its decimal equivalent into its
excess-3 (plus 3 decimal units) output with four bits each. The output is composed of four
bits because the excess-3 of the highest decimal equivalent of the 3-bit input requires four
bits for its binary equivalent. That is, input 7 (the decimal equivalent of input 111) has an
excess-3 output of 7+3=10. And the binary equivalent of decimal 10 is 1010, which is
composed of four bits.

3-bit Binary Excess-3 Code

x y z a b c d
0 0 0 0 0 1 1 3
0 0 1 0 1 0 0 4
0 1 0 0 1 0 1 5
0 1 1 0 1 1 0 6
1 0 0 0 1 1 1 7
1 0 1 1 0 0 0 8
1 1 0 1 0 0 1 9
1 1 1 1 0 1 0  10

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
- Binary input 000 has decimal equivalent 0. Excess-3 of 0 is 0+3=3 and the four-bit binary
code for 3 is 0011.
- Binary input 001 has decimal equivalent 1. Excess-3 of 1 is 1+3=4 and the four-bit binary
code for 4 is 0100.
- Binary input 010 has decimal equivalent 2. Excess-3 of 2 is 2+3=5 and the four-bit binary
code for 5 is 0101.
- Binary input 011 has decimal equivalent 3. Excess-3 of 3 is 3+3=6 and the four-bit binary
code for 6 is 0110.
- Binary input 100 has decimal equivalent 4. Excess-3 of 4 is 4 +3=7 and the four-bit binary
code for 7 is 0111.
- Binary input 101 has decimal equivalent 5. Excess-3 of 5 is 5+3=8 and the four-bit binary
code for 8 is 1000.
- Binary input 110 has decimal equivalent 6. Excess-3 of 6 is 6+3=9 and the four-bit binary
code for 9 is 1001.
- Binary input 111 has decimal equivalent 7. Excess-3 of 7 is 7+3=10 and the four-bit binary
code for 10 is 1010.
- Extracting the Boolean equation for the four outputs a , b , c , d gives us

a=xy + xz ' ' ' '

b=x y + x z + x y z c= y z + yz
' '
d= z '
' ' '
a=x ( y + z ) b=x ( y + z ) + x y z c= y ⊙ z
- The logic-gate implementation of the four Boolean functions is as shown below.

Magnitude Comparator
 a combinational circuit that can compare two numbers
 ¿ ,< ,=, ≤ ,≥ , ≠
 Ex. Design a combinational circuit that can compare two binary numbers with four bits each.
(¿ ,< ,=¿)
- Let the first number be A with the most significant bit (MSB) A3 and the least significant bit
(LSB) A0 as A3 A 2 A 1 A 0.
- Let the second number be B with MSB B3 and LSB B0 as B3 B2 B 1 B0.
1st number ¿ A=A 3 A 2 A 1 A0
2nd number ¿ B=B3 B2 B1 B0
For A=B :
- Test each of the bit positions of the given numbers if they are equal.
- is A0 =B 0?
A0 B0 A0 =B 0
0 0 1
0 1 0
1 0 0
1 1 1
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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023

- Since 0 is equal to 0, then A0 =B 0 is 1 (true).

- Since 0 is not equal to 1, then A0 =B 0 is 0 (false).
- Since 1 is not equal to 0, then A0 =B 0 is 0.
- Since 1 is equal to 1, then A0 =B 0 is 1.
- Let the expression A0 =B 0 be x 0. Extracting the Boolean function for x 0 gives us

' '
x 0= A 0 B0 + A 0 B0= A 0 ⊙ B0

- is A1=B1 ?
A1 B1 A1=B1
0 0 1
0 1 0
1 0 0
1 1 1

- Let the expression A1=B1 be x 1. Extracting the Boolean function for x 1 gives us

' '
x 1= A 1 B 1+ A 1 B 1= A 1 ⊙ B 1

- is A2=B2 ?
A2 B2 A2=B2
0 0 1
0 1 0
1 0 0
1 1 1

- Let the expression A2=B2 be x 2. Extracting the Boolean function for x 2 gives us

' '
x 2= A 2 B 2+ A 2 B 2= A 2 ⊙ B 2

- is A3 =B3 ?
A3 B3 A3 =B3
0 0 1
0 1 0
1 0 0
1 1 1

- Let the expression A3 =B3 be x 3. Extracting the Boolean function for x 3 gives us

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 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
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' '
x 3= A3 B3+ A 3 B3 =A 3 ⊙ B3

- ANDing the four conditions, x 0 , x 1 , x 2 , x 3 , will give an output high if each bit of one
number is equal to the corresponding bit of the other number.
( A=B )=x 3 ⋅ x 2 ⋅ x1 ⋅ x 0=( A '3 B'3 + A3 B 3 )( A'2 B '2+ A 2 B2 )( A '1 B'1+ A 1 B1 )( A '0 B'0 + A 0 B0 ) =( A0 ⊙ B 0 ) ( A 1 ⊙ B

For A> B :
- Test first the MSB of each number to see if they are equal.
- If they are equal, the expression for x 3 above is applied ( x 3= A3 ⊙ B3).
- If not, test if A ’s MSB is greater than that of B’s.
A3 B3 A3 > B3
0 0 0
0 1 0
1 0 1
1 1 0
( A3 > B3 ) =A 3 B'3
- This expression will satisfy the condition A> B . That is,
'
A3 B 3
- If the MSB of each number are equal, test their 2nd MSB if they are equal.
- If they are equal, the expression for x 2 above is applied ( x 2= A2 ⊙ B 2).
- If not, test if A ’s 2nd MSB is greater than that of B’s.
A2 B2 A2 > B2
0 0 0
0 1 0
1 0 1
1 1 0
( A 2> B2 ) =A 2 B'2
- ANDing this expression with x 3 will satisfy the condition A> B . That is,
' '
x 3 A 2 B 2= ( A 3 ⊙ B3 ) A 2 B 2
- If the 2nd MSB of each number are still equal, test their 3rd MSB if they are equal.
- If they are equal, the expression for x 1 above is applied ( x 1= A1 ⊙ B 1).
- If not, test if A ’s 3rd MSB is greater than that of B’s.
A1 B1 A1 > B1
0 0 0
0 1 0
1 0 1
1 1 0
( A1 > B1 )= A 1 B'1
- ANDing this expression with x 3 and x 2 will satisfy the condition A> B . That is,
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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
' '
x 3 x 2 A 1 B 1= ( A 3 ⊙ B3 ) ( A 2 ⊙ B 2 ) A 1 B 1
- If the three MSB of each number are all equal, test their least significant bit (LSB) if they
are equal.
- If they are equal, the expression for x 0 above is applied and A=B ( x 0= A 0 ⊙ B0).
- If not, test if A ’s LSB is greater than that of B’s.
A0 B0 A0 > B0
0 0 0
0 1 0
1 0 1
1 1 0
( A 0> B 0 )= A0 B0 '
- ANDing this expression with x 3, x 2 and x 1 will satisfy the condition A> B . That is,
' '
x 3 x 2 x1 A 0 B 0=( A 3 ⊙ B3 )(A 2 ⊙ B2 )( A1 ⊙ B 1) A 0 B0
- Since any of the four expressions above satisfies the condition A> B , ORing them will
complete the comparison that A> B .
( A> B ) =A 3 B'3 + ( A 3 ⊙ B3 ) A 2 B'2 + ( A 3 ⊙ B3 ) ( A2 ⊙ B 2) A1 B'1+ ( A 3 ⊙ B3 ) ( A 2 ⊙ B2 ) ( A 1 ⊙ B1 ) A 0 B '0

For A< B :
- Just like for A> B , test from MSB to LSB and see if each bit of one number is equal to
that of the other number.
- If the binary digits of the same bit position of the two binary numbers (i.e., A3 and B3)
are equal, proceed to the lesser significant bit, and so on and so forth.
- If these binary digits are not equal, test if one digit is less than the other.
A3 B3 A3 < B3
0 0 0
0 1 1
1 0 0
1 1 0
( A3 < B3 ) =A '3 B3
A2 B2 A2 < B2
0 0 0
0 1 1
1 0 0
1 1 0
( A 2< B2 ) =A '2 B2
A1 B1 A1 < B1
0 0 0
0 1 1
1 0 0
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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
1 1 0
( A1 < B1 )= A '1 B1
A0 B0 A0 < B0
0 0 0
0 1 1
1 0 0
1 1 0
( A 0< B 0 )= A'0 B0
- If A3 < B3, its expression will satisfy the condition A< B . That is,
'
A3 B 3
- If A3 =B3 and A2 < B2, ANDing each of their expressions will satisfy the condition
A< B . That is,
' '
x 3 A 2 B 2= ( A 3 ⊙ B3 ) A 2 B 2
- If A3 =B3 , A2=B2 and A1 < B1, ANDing each of their expressions will satisfy the
condition A< B . That is,
' '
x 3 x 2 A 1 B 1= ( A 3 ⊙ B3 ) ( A 2 ⊙ B 2 ) A 1 B 1
- If A3 =B3 , A2=B2 , A1=B1 and A0 < B0 , ANDing each of their expressions will satisfy
the condition A< B . That is,
' '
x 3 x 2 x1 A 0 B 0=( A3 ⊙ B3 ) ( A 2 ⊙ B2 ) ( A1 ⊙ B 1 ) A 0 B0
- Since any of the four expressions above satisfies the condition A< B , ORing them will
complete the comparison that A< B .
( A< B ) =A '3 B3 + ( A 3 ⊙ B3 ) A '2 B2 + ( A 3 ⊙ B3 ) ( A2 ⊙ B 2) A'1 B1+ ( A 3 ⊙ B3 ) ( A 2 ⊙ B2 ) ( A 1 ⊙ B1 ) A '0 B 0

The combination of the implementation of the Magnitude Comparator that tests if ( A=B ), ( A> B )
or ( A< B ) is show below.

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
Decoder
 a combinational circuit with n inputs and 2n maximum number of output lines

The Basic Binary Decoder

Suppose you need to determine when a binary 1001 occurs on the inputs of a digital circuit. An
AND gate can be used as the basic decoding element because it produces a HIGH output only
when all its inputs are HIGH. Therefore, you must make sure that all of the inputs to the AND
gate are HIGH when the binary number 1001 occurs; this can be done by inverting the two
middle bits.

 Ex. 3-to-8 Line Decoder  a decoder with 8 outputs, every (and only) one of which is active in a
single set of input combinations

Design Problem: Design an active-high 3-to-8 Line Decoder

- An active-high logic circuit is a circuit composing of LEDs. “Active-high” means that the LED is
active (or “on”) when the logic is high (or “1”) and inactive (or “off”) when the logic is low (or “0”).
On the other hand, an active-low logic circuit is a circuit wherein the output LED is active (on)
when the logic is low (0) and inactive (off) when the logic is high (1).
- In a 3-to-8 Line Decoder, every LED (output) represents the decimal equivalent of a
corresponding binary input combination.

3-to-8 Line Decoder

x y z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

- This is the truth table of a 3-to-8 Line Decoder.

- Output D 0 is high while all other outputs are low since the decimal equivalent of input 000 is
0
- Output D 1 is high while all other outputs are low since the decimal equivalent of input 001 is
1
- Output D 2 is high while all other outputs are low since the decimal equivalent of input 010 is
2
- Output D 3 is high while all other outputs are low since the decimal equivalent of input 011 is
3
- Output D 4 is high while all other outputs are low since the decimal equivalent of input 100 is
4
- Output D 5 is high while all other outputs are low since the decimal equivalent of input 101 is
5
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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
- Output D 6 is high while all other outputs are low since the decimal equivalent of input 110 is
6
- Output D 7 is high while all other outputs are low since the decimal equivalent of input 111 is
7
- The Boolean equation for each output and the logic-gate implementation for the 3-to-8 Line
Decoder are as follows:
' ' ' ' ' ' '
D0=x y z D1=x y zD2=x y z
' ' ' ' '
D3=x yzD4 =x y z D5=x y z D6=xy z
D7=xyz

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
 Ex. 7-segment LED Display Decoder  a decoder that aims to display the decimal form of a
BCD input

Design Problem: Design a common-cathode 7-Segment LED Display Decoder.

- A common-cathode circuit is a circuit of LEDs wherein the cathodes are connected together to a
common connection to ground, meaning it is initially logic 0 and a LED activates with logic 1.
On the other hand, a common-anode circuit is a circuit of LEDs with its anodes connected
together to a common connection to signal, meaning it is initially logic 1 and a LED activates
with logic 0.
- The circuit diagram of a common-cathode 7-segment LED display is as shown

and the LEDs light up to display decimal forms of a binary-coded decimal (BCD) input as

- For decimal number 0, LEDs a , b , c , d ,e , f are on while LED g is off.

- For decimal number 1, LEDs b , c are on while LEDs a , d , e , f , g are off.
- For decimal number 2, LEDs a , b , d , e , g are on while LEDs c , f are off.
- For decimal number 3, LEDs a , b , c , d , g are on while LEDs e , f are off.
- For decimal number 4, LEDs b , c , f , g are on while LEDs a , d , e are off.
- For decimal number 5, LEDs a , c , d , f , g are on while LEDs b , e are off.
- For decimal number 6, LEDs a , c , d ,e , f , g are on while LED b is off.
- For decimal number 7, LEDs a , b , c are on while LEDs d , e , f , g are off.
- For decimal number 8, LEDs a , b , c , d ,e , f , g are all on.
- Finally, for decimal number 9, LEDs a , b , c , d , f , g are on while LED e is off.
- The behavior of the LEDs are summarized in a truth table as shown below.
Common-Cathode 7-Segment LED Display Decoder
Decimal
w x y z a b c d e f g
equivalent
0 0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 1 0 1 1 0 0 0 0
0 0 1 0 2 1 1 0 1 1 0 1
0 0 1 1 3 1 1 1 1 0 0 1
0 1 0 0 4 0 1 1 0 0 1 1
0 1 0 1 5 1 0 1 1 0 1 1
0 1 1 0 6 1 0 1 1 1 1 1
0 1 1 1 7 1 1 1 0 0 0 0
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 1 1 0 1 1
1 0 1 0 10 X X X X X X X
1 0 1 1 11 X X X X X X X
1 1 0 0 12 X X X X X X X
1 1 0 1 13 X X X X X X X
1 1 1 0 14 X X X X X X X
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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
1 1 1 1 15 X X X X X X X
(NOTE: The output for BCD 10 to 15 are marked as don’t-care conditions because one 7-
segment LED display can only display a one-digit decimal number.)

- Extracting the Boolean equation for each output gives us

' ' ' ' '

a=w + y + xz+ x ' z ' d=w+ x y+ y z + x z + x y z ' ' '
g=w+ x y + x z + x y

' ' '

'
b=x + y z + yz
' ' e= y z + x z

' ' ' '

'
c= y + z + x f =w + y z + x y + x z

(NOTE: Positions m 10 to m 15 of each k-map are all X (don’t-care condition) but will still yield the
same expressions for the outputs.)

- The logic-gate implementation of the 7-segment LCD Display is as shown below.

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
Encoder
 a combinational logic circuit with 2n inputs and n outputs
 Ex. 8x3 Encoder  an encoder with outputs representing the binary equivalent of the input
number

8x3 Encoder
A0 A1 A2 A3 A4 A5 A6 A7 x y z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

- In an 8x3 encoder, every input is an LED that represents a decimal number (the subscripts
of the A ’s) and the outputs are LEDs representing the binary equivalent of the input.
- When A0 , which represents decimal 0, is high, LED xyz are all “off” to represent binary
000.
- When A1 (decimal 1) is high, only LED z is “on” to represent binary 001.
- When A2 (decimal 2) is high, only LED y is “on” to represent binary 010.
- When A3 (decimal 3) is high, LED yz are “on” to represent binary 011.
- When A 4 (decimal 4) is high, only LED x is “on” to represent binary 100.
- When A5 (decimal 5) is high, LED xz are “on” to represent binary 101.
- When A6 (decimal 6) is high, LED xy are “on” to represent binary 110.
- When A7 (decimal 7) is high, LED xyz are all “on” to represent binary 111.

Multiplexer
 a combinational circuit with multiple inputs and only one output

Block Diagram of a Multiplexer

- The block diagram of a 2n ×1 mux (2n by 1 multiplexer) is shown above. 2n ×1 means that
there are 2n number of inputs and 1 output. Also, there are n number of “select” terminals,
as shown.
- n can be determined by n=m−1 wherein m is the number of input variables in a given
Boolean equation

Design Problem: Given the Boolean function F=xy + x ' yz , implement F using a multiplexer.

- From the given Boolean function, there are three input variables xyz . Thus,
m=3n=3−1=22n=2 2=4
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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
and the block diagram of the mux for F is

4 ×1
mux

2 select terminals

- The select terminals are always assigned from the lowest significant bit (in this case, y and z ).
- The most significant bit ( x ) is analyzed in an implementation table. But first, we need to write
the truth table of F .
Truth Table of F
x y z F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

- From the truth table, assign m 0 and m 4 under I 0 on the implementation table; m 1 & m 5 under I 1;
m2 & m6 under I 2; and, m3 & m7 under I 3.
Implementation Table
I0 I1 I2 I3
x
'
m0 m1 m2 m3
x m4 m5 m6 m7
oIf the same values are under I j, that value becomes the fixed value for input I j.
oIf different values are under I i (i.e., 1 and 0), the variable that gave 1 will be assigned to
I i.
- The implementation table for x is as shown below.
Implementation Table
I0 I1 I2 I3
x
' 0 0 0 1
x 0 0 1 1
0 0 x 1
o Since outputs m 0 & m 4 for F are both 0, the fixed value for I 0 is 0. This means that pin
I 0 must always be logic 0.
o Outputs m 1 & m 5 are also both 0, which means that pin I 1 must always be logic 0.
o Output m 2 is 0 while output m 6 is 1. Since m 6, which is logic 1, is under literal x and not
x , pin I 2 must be connected to input x .
'

o Output m 3 & m 7 are both 1, which means that pin I 3 must always be logic 1.
- A multiplexer uses a two-level gate implementation with an OR gate for the highest level
(directly to the output).
- On the lower level are 2n AND gates and fan-in of the highest level OR gate.

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023

- As can be seen at the implementation above, whatever the state of x is, when y & z are both
high, the output is high (also as specified by the truth table).
- When y is high and z is low, a low-state x will give an output low, while a high-state x will give
an output high (also as specified by the truth table).

3-6 DESIGN PROBLEMS

Recall that the procedure in the design of combinational circuits involves the following steps:

1. From the specifications of the circuit, determine the required number of inputs and outputs and
assign a symbol to each.
2. Derive the truth table that defines the required relationship between inputs and outputs.
3. Obtain the simplified Boolean functions for each output as a function of the input variables.
4. Draw the logic diagram and verify the correctness of the design (manually or by simulation).

These steps must be considered as we analyze some design problems.

Example 3.1 Design a combinational circuit with three inputs xyz and three outputs ABC . When the
decimal equivalent of the binary input is 3 or more, the binary output is one less than the
input. When the decimal equivalent of the binary input is less than 3, the binary output is
two greater than the input.

Solution:
Following the procedure stated above for the design of combinational circuits:
Step 1:
 There are three inputs xyz and three outputs ABC .
Step 2:
Inputs Outputs
x y z A B C
0 0 0 0 0+2=2 0 1 0
0 0 1 1 1+2=3 0 1 1
0 1 0 2 2+2=4 1 0 0
0 1 1 3 3−1=2 0 1 0
1 0 0 4 4−1=3 0 1 1
1 0 1 5 5−1=4 1 0 0
1 1 0 6 6−1=5 1 0 1
1 1 1 7 7−1=6 1 1 0
- The first three columns of the truth table show the eight possible combinations of the
input variables xyz .
- The fourth column shows the decimal equivalent of the input combinations.
- The fifth column shows what was specified in the design problem that when the decimal
input is less than 3, the decimal output is two greater than the input; while when the
decimal input is 3 or more, the decimal output is one less than the input.
- The last three columns show the binary equivalent of the fifth column… these last three
columns are the required outputs of the design problem.

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
Step 3:
- From the last three columns of the truth table in step 2, the expressions for the output
variables can be extracted as follows:

'
A= y z + xz

' ' '

B= y z + yz + x z

' ' '

C=x z + x y z

Step 4:
- The logic diagram for the design problem is as shown below.

Example 3.2 Design a logic circuit with input signal A , control input B, and outputs X and Y to
operate as follows:
1. When B=1, output X will follow input A , and output Y will be 0 .
2. When B=0 , output X will be 0 , and output Y will follow input A .

Solution:
Step 1:
 There are two inputs AB and two outputs XY .
Step 2:
- Let us fill the truth table one step at a time according to the specifications in the problem.

A B X Y
0 0
0 1
1 0
1 1

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
- As stated in the problem, when B=1, output X will follow input A

A B X Y
0 0
0 1 0
1 0
1 1 1

and output Y will be 0.

A B X Y
0 0
0 1 0 0
1 0
1 1 1 0

- Again, as stated in the problem, when B=0 , output X will be 0

A B X Y
0 0 0
0 1 0 0
1 0 0
1 1 1 0

and output ¿ Y will follow input A .

A B X Y
0 0 0 0
0 1 0 0
1 0 0 1
1 1 1 0

-
Step 3:
 Since X is high only when both A and B is high, the Boolean expression for X is
X =AB
 Since Y is high only when A is high and B is low, the Boolean expression for Y is
'
Y=A B
Step 4:
- The logic diagram for the design problem is as shown below.

Example 3.3 A manufacturing plant needs to have a horn sound to signal quitting time. The horn
should be activated when either of the following conditions is met:
1. It’s after 5 o’clock and all machines are shut down.
2. It’s Friday, the production run for the day is complete, and all machines are shut
down.

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
Design a logic circuit that will control the horn. (Hint: Use four logic input variables to
represent the various conditions; for example, input A will be HIGH only when the time
of day is 5 o’clock or later.)

Solution:
Step 1:
Let the horn sound be the output, say F . Also, let
A=¿ time of day ¿ {10 ,, 5before
pmonwards
5 pm
¿{
1, Friday
B=¿ day of week
0 , not Friday
¿{
1, complete
C=¿ production run
0 , not yet complete
¿{
1 , shut down
D=¿ machines
0, still on
 There are four inputs and only one output.

Step 2:
- Let us fill the table one step at a time according to the specifications of the problem.

A B C D F
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

- “The horn should be activated when it’s after 5 o’clock and all machines are shut down.”
This means that F (the horn) is 1 (active) when A (time) is 1 (5pm onwards) and D (the
machines) is 1 (shut down).

A B C D F
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1 1
1 0 1 0

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 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
1 0 1 1 1
1 1 0 0
1 1 0 1 1
1 1 1 0
1 1 1 1 1

- “The horn should be activated when it’s Friday, the production run for the day is
complete, and all machines are shut down.” This means that F (the horn) is 1 (active)
when B (the day of the week) is 1 (Friday), C (production run for the day) is 1
(complete), and D (the machines) is 1 (shut down).

A B C D F
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1 1
1 0 0 0
1 0 0 1 1
1 0 1 0
1 0 1 1 1
1 1 0 0
1 1 0 1 1
1 1 1 0
1 1 1 1 1

- When none of the given conditions are met, F (the horn) is 0 (not active).

A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

Step 3:
- The Boolean equation for F can be extracted as

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reproduced for educational purposes only and not for commercial distribution.

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 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023

F= AD+ BCD

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reproduced for educational purposes only and not for commercial distribution.

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JKTAlamo
 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
Step 4:
- The logic circuit for F is implemented as

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reproduced for educational purposes only and not for commercial distribution.

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 Republic of the Philippines
NUEVA VIZCAYA STATE UNIVERSITY
Bambang, Nueva Vizcaya
INSTRUCTIONAL MODULE
IM No.: IM03-ECE9-1S-2022-2023
VI. REFERENCES

Mano, M. (2016). Digital Design with an Introduction to the Verilog HDL (5th ed.). pp. 17-42
Singapore: Pearson Education South Asia. Retrieved from https://nitsri.ac.in/Department/Computer
%20Science%20&%20Engineering/digital_design-__morris_mano-fifth_edition.pdf
Petriu, E.M. Digital Logic Circuits.
Shannon, C.E. A Symbolic Analysis of Relay and Switching Circuits.

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reproduced for educational purposes only and not for commercial distribution.

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