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Ece137b Notes Set 6b

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3 views

Ece137b Notes Set 6b

Uploaded by

Sagnik Bachhar
Copyright
© © All Rights Reserved
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ECE137B notes; copyright 2018

Switching circuits:
basics and switching speed

Mark Rodwell,
University of California, Santa Barbara
Amplifiers vs. switching circuits

Some transistor circuit might have


Vin vs. Vout characteristics like this:

The characteristics have a nearly linear


amplification region:

Plus limiting or clipping regions


set by cutoff (minimum current)
or "saturation" (minimum voltage)
Trivial example: CS stage with resistive load

Here, the lower limit on Vout is set by saturation,


and the upper limit by cutoff
Amplifiers vs. switching circuits
Biased in the linear region,
and with a sufficiently small input,
the circuit is an *amplifier*

But, if the input is large, then the output


switches between the clipping values.
This is a *switching circuit*
Switching circuits vs. logic gates
Logic gates are a particular *type* of switching circuit

A general switching cicuit might have a


different range for Vout and Vin .
...and might not perform *logic*
Switching circuits vs. logic gates
Logic gates are a particular *type* of switching circuit

A logic gate will have the same


range for Vout and Vin .
...and usually has multiple inputs to
perform Boolean operations

CMOS NAND gate:


Switching circuits vs. logic gates

Our focus here is on switching circuits, and on calculating


DC Vin  Vout transfer characteristics
switching risetimes and falltimes

You should have , by now, studied basic logic gates


in other classes
Noise margins
" Noise" margins: tolerance for
component variation, EMI

Input low level can vary over a


considerable range, yet
always produce nearly the same
output "high" level

Input high level can vary over a


considerable range, yet
always produce nearly the same output "low" level

Defining margins precisely is difficult for general switching circuits.


....easier for logic
Another switching circuit: CMOS

1 V

I D , NFET  I D , PFET and VDS , PFET  VDD  VDS , NFET


From these relationships, we obtain the loadline constructions above
Both the positive and negative clipping limits, hence switched
output voltage levels, are set by transistor saturation.
Another switch: emitter-coupled pair

One example of this: the digital 50 coaxial cable interface


between the PRBS pulse generator and the LED/laser driver in
lab project choice #2.
Another switch: emitter-coupled pair
Zo Zo

There are also logic families using bipolar


differential pairs, current mode logic, left, and emitter
coupled logic, right
emitter-coupled pair transfer characteristics

The stated levels on the diagram are easily found.


But, how do we find Vin?
emitter-coupled pair transfer characteristics
slope  I o RL / 4VT

DC bias Vin at zero Volts, then apply a small signal: what is the gain ?
g m  g m1  g m 2  I o / 2VT , Av  Vout / Vin  g m RL / 2  I o RL / 4VT
emitter-coupled pair transfer characteristics
slope  I o RL / 4VT

height  I o RL

so, the slope of the switching region is I o RL / 4VT ,


while the output voltage swing is I o RL ,
so the input voltage range must be the ratio of these:
Vin  ( I o RL ) / ( I o RL / 4VT )  4VT  4kT / q
emitter-coupled pair: comments

You can repeat this calculation for a differential input  different Vin

We have assume that Q1 , Q2 don't saturate over the logic swing.


if they do, then this will change the Vin  Vout characteristics
Limiting mechanisms: current-steering

We can design differential current-steering circuits such that


both Vout ,high and Vout ,low are set by cutoff.
Limiting mechanisms: CS or CE

In these common-source-like and common-emitter-like circuits


either or both Vout ,high and Vout ,low are set by saturation.
Limiting mechanisms: CS or CE

When BJT's saturate,


they usually store large amounts of minority carrier change.

Switching speed is then very slow.

With a few exceptions,


saturation is avoided in bipolar switching circuits
Computing risetimes: charge control method

Charge control method: hand estimate switching circuit delay, risetime


-Compute total charge on all capacitors at high Qhigh and low levels Qlow
-Compute voltage on node at high level Vhigh and low level Vlow
-Compute change in charge Q  Qhigh  Qlow and voltage V  Vhigh  Vlow
-If node is charged by constant current I , then charging is linear
Trise / fall  Q / I and Tdelay  Trise / fall / 2
-If node is charged through resistance R, then charging is exponential
Equivalent capacitance C  Q / V , time constant   RC
Trise / fall  2.2 and Tdelay   ln(2)
Charging through a current source

The input voltage falls suddenly, turning the FET off.


Let's ignore, just for now,
the PFET knee voltage; treat as current source.
Now, constant current charges capacitance.
Charging is linear
Trise / fall  Q / I 0 and Tdelay  Trise / fall / 2
Charging through a resistance

The input voltage falls suddenly, turning the FET off.


Node is charged through resistance R; charging is exponential
Equivalent capacitance C  Q / V , time constant   RC
Trise / fall  2.2 and Tdelay   ln(2)
Example: Waveform at Q1 drain

Vin switches at t  0.
We will estimate VD1 (t ).
Example: Waveform at Q1 drain

Note:
1) VD1 (t ) initially swings negative: Vin (t ) couples to VD1 (t ) though
a capacitive voltage divider between Cgd 1 and (Cgd 2 , Cgd 3 , Cgs 3 )
2)VD1 (t ) then charges towards +1V.
Between VD1 = 0V and 0.8V, Q2 is a constant-current source
Between VD 2 = 0.8V and 1V, Q2 acts as a resistance (saturation)
Example: Waveform at Q1 drain

Switching time between A and C: 1st part: charging to 0.8V


change in charge in:
Cgd 1: @ A: Q  1V  Cgd 1 , @ C: Q  0.8V  Cgd 1 , Q  1.8V  C gd 1
Cgd 2 : @ A: Q  0.8V  Cgd 2 , @ C: Q  0V  Cgd 2 , Q  0.8V  C gd 2
Cgd 3 : @ A: Q  1V  Cgd 3 , @C Q  0.8V  Cgd 3 , Q  1.8V  C gd 3
Cgs 3 : @ A: Q  0V  Cgs 3 , @ C: Q  0.8V  Cgs 3 , Q  0.8V  C gd 3
Time for drain of Q1 to charge to 0.8V:
T1 = 1.8V  Cgd 1  0.8V  Cgd 2  1.8V  C gd 3  0.8V  C gd 3  1mA
Example: Waveform at Q1 drain

Switching time between C and D: 2nd part: charging from 0.8V towards 1V
Cgd 1: @ C: Q  0.8  Cgd 1 , @ D: Q  1V  C gd 1 , Q  0.2V  C gd 1
Cgd 2 : @ C: Q  0V  Cgd 2 , @ D: Q  0.2V  Cgd 2 , Q  0.2V  C gd 2
Cgd 3 : @ C: Q  0.8V  Cgd 3 , @ D: Q  1V  C gd 3 , Q  0.2V  C gd 3
Cgs 3 : @ C: Q  0.8V  Cgs 3 , @ D: Q  1V  C gs 3 , Q  0.2V  C gd 3
Effective capacitance :
Ceff =  0.2V  Cgd 1  0.2V  Cgd 2  0.2V  Cgd 3  0.2V  Cgd 3  0.2V=...
Time constant   RDS , sat Ceff  RDS , sat  Cgd 1  Cgd 2  Cgd 3  Cgd 3 
Exponential charging: VD1 (t )  0.8V+(1V  0.8V)(1  exp((t  T1 ) /  ))
Example: bipolar differential switch

Let us calculate the risetime at the base of Q3


Example: bipolar differential switch

Let us calculate the risetime at the base of Q3


Times are relative to the time at which
the collector current of Q2 switches to zero.
Example: bipolar differential switch

Switching time between A and B:


change in charge in:
Ccb 2 : @ A: Q  Vlow  Ccb 2 , @ B: Q  Vhigh  Ccb 2 , Q  (Vhigh  Vlow )  Ccb 2
Ccb 3 : @ A: Q  (Vlow  VCC )  Ccb 3 , @ B: Q  (Vhigh  VCC )  Ccb 3 , Q  (Vhigh  Vlow )  Ccb 3
C je 2 : @ A: Q  (Vlow  V0   )  C je 2 , @ B: Q  (Vhigh  Vhigh   )  C je 2 , Q  (V0  Vlow )  C je 2
Cdiff 2 : @ A: Q  0 mA  f 2 , @ B: Q  I 0  f 2 , Q  I 0  f 2
Effective capacitance:
Ceff =Q / (Vhigh  Vlow )
  (Vhigh  Vlow )  Ccb 2  (Vhigh  Vlow )  Ccb 3  (V0  Vlow )  C je 2  I 0  f 2  (Vhigh  Vlow )
Example: bipolar differential switch

Effective capacitance:
V0  Vlow I 
Ceff  Ccb 2  Ccb 3  C je 2  0 f 2 but Vhigh  Vlow  I 0 RL
Vhigh  Vlow Vhigh  Vlow
Charging time constant:
V0  Vlow
 charge  RLCeff  RLCcb 2  RLCcb 3  RLC je 2  f 2
Vhigh  Vlow
Voltage waveform:
Vb 3 (t )  Vlow  (Vhigh  Vlow )(1  exp(t /  charge ))
Limitations of charge control

1) the method is very approximate

2) We do not predict the detailed shape of the switching waveform


More detailed analysis can find secondary switching transients at
one or move points within the overall waveform. In some cases,
spikes are produced. This is more advanced material

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