Linear displacement is movement in one direction along a single axis.

A position or linear
displacement sensor is a device whose output signal represents the distance an object has
traveled from a reference point. A displacement measurement also indicates the direction of
motion (See Figure 1).

Figure 1. Linear Displacement Measurement

A linear displacement typically has units of millimeters (mm) or inches (in.) and a negative or
positive direction associated with it.

Linear Variable Differential Transformers

(LVDTs)..
Linear variable differential transformers (LVDT) are used to measure displacement. LVDTs
operate on the principle of a transformer. As shown in Figure 2, an LVDT consists of a coil
assembly and a core. The coil assembly is typically mounted to a stationary form, while the
core is secured to the object whose position is being measured. The coil assembly consists
of three coils of wire wound on the hollow form. A core of permeable material can slide
freely through the center of the form. The inner coil is the primary, which is excited by an AC
source as shown. Magnetic flux produced by the primary is coupled to the two secondary
coils, inducing an AC voltage in each coil.

The main advantage of the LVDT transducer over other types of displacement transducer is
the high degree of robustness. Because there is no physical contact across the sensing
element, there is no wear in the sensing element.

Because the device relies on the coupling of magnetic flux, an LVDT can have infinite
resolution. Therefore the smallest fraction of movement can be detected by suitable signal
conditioning hardware, and the resolution of the transducer is solely determined by the
resolution of the data acquisition system.
Working Principle of LVDT
The working of LVDT is based on the principle of Faraday’s law of
electromagnetic induction that states that “the net induced emf in the circuit is
directly proportional to the rate of change of magnetic flux across the circuit,
and the magnetic flux of the coil wounded with wires can be changed by
moving a bar magnet through the coil.”As the primary winding of the LVDT is
connected to the AC power supply, the alternating magnetic field is produced
in the primary winding, which results in the induced emf the secondary
windings. Let us assume that the induced voltages in the secondary windings
S1 and S2 be E1 and E2 respectively. Now, according to Faraday’s Law, the
rate of change of magnetic flux, i.e., dØ/dt is directly proportional to the
magnitude of induced emf’s, i.e., E1 and E2. Hence, the induced emf in the
secondary windings will be more if the value of ‘dt’ will be low (dØ/dt ∝ E1
and E2), and the low value of ‘dt’ implies that the soft iron core present inside
the LVDT is moving faster. Thus, emf of large magnitude will induce in the
secondary windings S1 and S2 if the movement of the core is faster inside the
LVDT.

As we have discussed in the construction above that both the secondary

winding S1 and S2 are connected in series with each other but in opposite
phases, due to this phase opposition connection, the total output voltage (Eo)
in the circuit will be given by,
What Is Boolean algebra?
Boolean algebra is a division of mathematics that deals with operations on
logical values and incorporates binary variables. Boolean algebra traces its
origins to an 1854 book by mathematician George Boole.1

The distinguishing factor of Boolean algebra is that it deals only with the
study of binary variables. Most commonly Boolean variables are presented
with the possible values of 1 ("true") or 0 ("false"). Variables can also have
more complex interpretations, such as in set theory. Boolean algebra is also
known as binary algebra.

KEY TAKEAWAYS

 Boolean algebra is a branch of mathematics that deals with operations

on logical values with binary variables.
 The Boolean variables are represented as binary numbers to represent
truths: 1 = true and 0 = false.
 Elementary algebra deals with numerical operations whereas Boolean
algebra deals with logical operations.
 The primary modern use of Boolean algebra is in computer
programming languages.
 In finance, Boolean algebra is used in binomial options pricing models,
which helps determine when an option should be exercised.
Logic gates and combinational logic
Digital systems are said to be constructed by using logic gates. These gates are the
AND, OR, NOT, NAND, NOR, EXOR and EXNOR gates. The basic operations are
described below with the aid of truth tables.

AND gate

The AND gate is an electronic circuit that gives a high output (1) only if all its
inputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in
mind that this dot is sometimes omitted i.e. AB
OR gate

The OR gate is an electronic circuit that gives a high output (1) if one or
more of its inputs are high. A plus (+) is used to show the OR operation.

NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the
input at its output. It is also known as an inverter. If the input variable is A,
the inverted output is known as NOT A. This is also shown as A', or A with a
bar over the top, as shown at the outputs. The diagrams below show two ways
that the NAND logic gate can be configured to produce a NOT gate. It can also
be done using NOR logic gates in the same way.

NAND gate

This is a NOT-AND gate which is equal to an AND gate followed by a NOT

gate. The outputs of all NAND gates are high if any of the inputs are low. The
 symbol is an AND gate with a small circle on the output. The small circle
represents inversion.

NOR gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT

gate. The outputs of all NOR gates are low if any of the inputs are high.
The symbol is an OR gate with a small circle on the output. The small circle
represents inversion.

EXOR gate

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but
not both, of its two inputs are high. An encircled plus sign ( ) is used to show
the EOR operation.

EXNOR gate
The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a
low output if either, but not both, of its two inputs are high. The symbol is an EXOR
gate with a small circle on the output. The small circle represents inversion.

The NAND and NOR gates are called universal functions since with either one the
AND and OR functions and NOT can be generated.

Note:

A function in sum of products form can be implemented using NAND gates by

replacing all AND and OR gates by NAND gates.

A function in product of sums form can be implemented using NOR gates by

replacing all AND and OR gates by NOR gates.

Table 1: Logic gate symbols

The combinational logic circuits have no feedback, and any changes to the
signals being applied to their inputs will immediately have an effect at the
output. In other words, in a Combinational Logic Circuit, the output is
dependant at all times on the combination of its inputs. Thus a combinational
circuit is memoryless.
So if one of its inputs condition changes state, from 0-1 or 1-0, so too will the
resulting output as by default combinational logic circuits have “no memory”,
“timing” or “feedback loops” within their design.

Half Adders[edit | edit source]

When adding two separate bits together there are four possible combinations. Each of these is
shown in the left with its solution.

It can easily be seen that the bit in the right-hand column (the "ones" column) is a 1 only when the
addends are different. XORing the addends together can therefore give us the right-hand bit. This bit
is called the sum and is the modulo-2 sum of the addends (i.e. the solution if you loop round to zero
again once you pass one).
The left-hand bit reads 1 only when both addends are 1, so an AND gate can be used to generate
this bit, called the carried bit. As a summary:

The diagram to the left shows the complete half adder with the addends being represented by A
and B, the sum represented by S and the carried bit represented by C.
The truth table is as follows (the number in the brackets are the weights of the bits - each
addend is one, as is the sum - the carried bit is two)

A (1) B (1) S (1) C (2)

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Full Adders[edit | edit source]
The downfall of half adders is that while they can generate a carry out output, they cannot deal with
a carry in signal. This means that they can only ever be stand-alone units, and cated to add multiple
bit numbers.
A full adder solves this problem by adding three numbers together - the two addends as in the half
adder, and a carry in input.
A full adder can be constructed from two half adders by connecting A and B to the input of one half
adder, connecting the sum from that to an input to the second adder, connecting the carry in, Cin, to
the other input and ORing the two half adder carry outputs to give the final carry output, Cout.

The diagram below shows a full adder at the gate level.

A version of this diagram showing the two half adder modules outlined is available here. The output
of the full adder is the two-bit arithmetic sum of three one-bit numbers.
The logic expressions for this full adder are:

By applications of boolean algebra, the second statement simplifies to

 Giving the inputs in a three digit number where the first is the state of A, the second the
state of B and the third the state of Cin, below is a description of the function of this full adder:

 All combinations resultings in one (100, 010, 001) produce a high at the sum output, as
the presence of only one high at the second XOR gate (the first gate gives a low when A
and B are low and a high when either A or B is high) gives a high output at the sum
output. The fact that only one input is ever high prevents either AND gate from going
high and give a high Cout.

 All combinations resulting in two (011, 101, 110) produce a high carry out and a low sum:

o 011 sends the first XOR gate high as A and B are different. Combined with the high
at Cin, this sends the top AND gate high and therefore the carry output high as well.
The presence of two highs at the second XOR gate hold the sum low.

o 101 works in exactly the same way as 011, as A and B are interchangeable.

o 110: The high A and B force the first XOR low; this low, combined with the low from
Cin gives a low at the sum. The highs at A and B send the lower AND gate high and
therefore Cout is high.

 When the inputs are 111, the first XOR gate is low due to the two high inputs, and the
second XOR gate goes high, as it has one low input (from the first XOR gate) and one
high input (from the Cin input). This gives a high sum output. The fact that both A and B
are high triggers the lower AND gate, and the Cout output goes high as well.
The truth table for a full adder is given below with the weights of the inputs and outputs:
If A and B are both high then the AND gate connected to them gives a high output, but the
XOR gate gives a low, forcing the other AND gate low. If the "sum" output of the first half
adder is high, then one of A or B must be low, meaning that the AND gate connected to
them is force low. This means that two inputs to the OR gate combining the half adder carry
outs can never both be high, this gate can be replaced with an XOR gate (OR and XOR
differ only when both inputs are high). This means that only two kinds of gates are needed,
and a full adder can be realised with only two ICs.
These can be run in stages, with the carry out of one stage driving the carry in of the next.
This is discussed in the next section.
Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection
lines and single output line. One of these data inputs will be connected to the output
based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and
ones. So, each combination will select only one data input. Multiplexer is also called
as Mux.
4x1 Multiplexer
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one
output Y. The block diagram of 4x1 Multiplexer is shown in the following figure.

One of these 4 inputs will be connected to the output based on the combination of
inputs present at these two selection lines. Truth table of 4x1 Multiplexer is shown
below.

Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

From Truth table, we can directly write the Boolean function for output, Y as
Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3
We can implement this Boolean function using Inverters, AND gates & OR gate.
The circuit diagram of 4x1 multiplexer is shown in the following figure.

We can easily understand the operation of the above circuit. Similarly, you can
implement 8x1 Multiplexer and 16x1 multiplexer by following the same procedure.

Implementation of Higher-order Multiplexers.

Now, let us implement the following two higher-order Multiplexers using lower-order
Multiplexers.

 8x1 Multiplexer
 16x1 Multiplexer
8x1 Multiplexer
In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1
Multiplexer. We know that 4x1 Multiplexer has 4 data inputs, 2 selection lines and one
output. Whereas, 8x1 Multiplexer has 8 data inputs, 3 selection lines and one output.
So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs.
Since, each 4x1 Multiplexer produces one output, we require a 2x1 Multiplexer in
second stage by considering the outputs of first stage as inputs and to produce the final
output.
Let the 8x1 Multiplexer has eight data inputs I7 to I0, three selection lines s2, s1 & s0 and
one output Y. The Truth table of 8x1 Multiplexer is shown below.

Selection Inputs Output

S2 S1 S0 Y

0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7

We can implement 8x1 Multiplexer using lower order Multiplexers easily by considering
the above Truth table. The block diagram of 8x1 Multiplexer is shown in the following
figure.

The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data inputs
of upper 4x1 Multiplexer are I7 to I4 and the data inputs of lower 4x1 Multiplexer are I3 to
I0. Therefore, each 4x1 Multiplexer produces an output based on the values of selection
lines, s1 & s0.
The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer that
is present in second stage. The other selection line, s2 is applied to 2x1 Multiplexer.
 If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I3 to
I0 based on the values of selection lines s1 & s0.
 If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I7 to
I4 based on the values of selection lines s1 & s0.
Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer
performs as one 8x1 Multiplexer.

A (1) B (1) Cin (1) S (1) Cout (2)

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0
 0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

If A and B are both high then the AND gate connected to them gives a high output, but the
XOR gate gives a low, forcing the other AND gate low. If the "sum" output of the first half
adder is high, then one of A or B must be low, meaning that the AND gate connected to
them is force low. This means that two inputs to the OR gate combining the half adder carry
outs can never both be high, this gate can be replaced with an XOR gate (OR and XOR
differ only when both inputs are high). This means that only two kinds of gates are needed,
and a full adder can be realised with only two ICs.
These can be run in stages, with the carry out of one stage driving the carry in of the next.
This is discussed in the next section.