3644 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 70, NO.

9, SEPTEMBER 2023

Design of Energy-Efficient RFET-Based Exact and

Approximate 4:2 Compressors and Multipliers
Nima Kavand , Armin Darjani , Shubham Rai , Member, IEEE, and Akash Kumar , Senior Member, IEEE

Abstract—The ever-increasing demand for low-power and area- ever-increasing CMOS scaling problems and slowing down
efficient circuits for use in battery-powered devices and the CMOS of Dennard scaling have made it challenging to create more
scaling problems have attracted the attention of VLSI design- compact and low-power circuits with each new technology
ers to beyond-CMOS technologies like Reconfigurable Field-Effect generation. For this reason, several compressors have been
Transistors (RFETs). Improving the efficiency of multipliers is proposed based on beyond-CMOS technologies [3], [4].
critical as the core component of many applications such as image Among emerging technologies, Reconfigurable Field-Effect
processing and Machine Learning (ML). This brief proposes a
Transistor (RFET) follows a top-down manufacturing pro-
compact and energy-efficient RFET-based architecture for the
4:2 compressor and Dadda multiplier, leveraging transistor-level cess similar to CMOS [5], [6], and its unique features, like
reconfigurability and multi-input support of the RFET. Moreover, ambipolarity and multi-input support, open new doors to
we propose a novel approximate 4:2 compressor based on efficient designing compact low-power circuits [7]. Several previous
RFET logic cells to cater to the needs of error-resilient applica- works showed the benefits of RFET in creating basic logic
tions. Extensive circuit-level simulations with 14nm germanium gates [6], [8], [9], [10].
nanowire (GeNW) RFET technology show that the proposed In this brief, we propose an area- and energy-efficient 4:2
RFET-based exact multiplier improves the power consumption compressor and Dadda multiplier exploiting RFET features.
and power-delay product (PDP) by 65% and 45%, respectively, Moreover, as error-resilient applications like image processing
compared to the conventional CMOS-based counterpart in 14nm or ML allow designers to use approximate compressors and
FinFET technology. Besides, we show that utilizing the proposed multipliers to reduce energy consumption and area [1], [4],
approximate compressor, the area and PDP of the multiplier [11], [12], [13], [14], [15], [16], [17], [18], we also propose
reduce by 46% and 42%. The effectiveness of the approximate a novel approximate 4:2 compressor designed based on effi-
multiplier is evaluated in the image multiplication, and the average
PSNR and SSIM values are 31.39 and 0.87, respectively.
cient RFET logic cells. Although most research in the RFET
domain has been focused on Silicon nanowire (SiNW) transis-
Index Terms—RFET, GeNW, compressor, multiplier, approxi- tors, recently introduced GeNW transistors [19], [20], [21] can
mate computing. offer much better performance. As the power and performance
I. I NTRODUCTION trade-off is essential in a multiplier, in this brief, we use GeNW
N RECENT years, the wide usage of various micropro- RFET [21] to analyze 4:2 compressors and Dadda multiplier.
I cessors in battery-powered portable devices pushed VLSI
designers to employ different methods to gain more compact
The contributions of this brief are as follows:
• RFET-based exact 4:2 compressor: We propose an RFET-

and energy-efficient circuits. Among digital arithmetic blocks, based architecture for a compact and low-power exact
multipliers play an important role in many applications, such 4:2 compressor. We demonstrate that only 1-to-1 replace-
as image processing, and machine learning (ML). Multiplier ment of CMOS transistors with RFETs doesn’t lead to an
circuits are large and power-hungry and contribute consid- optimal circuit. Thus, we propose a design that exploits
erably to overall system performance. A multiplier usually reconfigurability and multi-input support of RFETs.
• RFET-based approximate 4:2 compressor: We introduce
comprises three phases: 1) Partial Product Generation (PPG),
2) Partial Product Reduction (PPR), 3) Final Addition. a novel 4:2 approximate compressor utilizing efficient
As the second stage has the largest portion of the area, RFET-based logic cells like minority and multiplexer for
propagation delay, and power consumption, efficient design of error-resilient applications.
• Exact and approximate Dadda multiplier: We imple-
this phase is crucial. Dadda method is one of the fastest and
most well-known methods for PPR, and 4:2 compressors are ment exact and approximate 8 × 8 multipliers employing
commonly used for implementing it [1]. our proposed compressors. We propose a structure for
Several works have proposed CMOS-based efficient 4:2 intra- and inter-compressor connections within the exact
compressors in terms of delay, power, and area [2]. However, multiplier to minimize the number of cascaded transmis-
sion gates (TG) in the critical path of the multiplier.
Manuscript received 30 March 2023; accepted 6 May 2023. Date of publi- • HW and accuracy analysis: We performed SPICE simula-
cation 15 May 2023; date of current version 29 August 2023. This work was tions using the 14nm GeNW RFET Verilog-A model [21]
supported in part by the Deutsche Forschungsgemeinschaft (DFG, German to evaluate our proposed compressors and multipliers in
Research Foundation) through SecuReFET under Project 439891087, and in terms of area and energy efficiency. Besides, we analyze
part by the German Federal Ministry for Education and Research (BMBF)
under the Framework of VE-CirroStrato. This brief was recommended by the accuracy of the approximate multiplier and investigate
Associate Editor A. Calimera. (Corresponding author: Akash Kumar.) the quality of this multiplier in an image multiplication
The authors are with the Department of Computer Science, Technische application.
Universität Dresden, 01062 Dresden, Germany (e-mail: nima.kavand@
tu-dresden.de; [email protected]; [email protected]; II. BACKGROUND
[email protected]).
Color versions of one or more figures in this article are available at RFET Structure and Functionality: RFETs are a group of
https://doi.org/10.1109/TCSII.2023.3275983. ambipolar transistors that can be electrostatically programmed
Digital Object Identifier 10.1109/TCSII.2023.3275983 at run-time to act either as nmos or pmos transistors. The
1549-7747 
c 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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 KAVAND et al.: DESIGN OF ENERGY-EFFICIENT RFET-BASED EXACT AND APPROXIMATE 4:2 COMPRESSORS AND MULTIPLIERS 3645

Fig. 1. a) RFET reconfigurability b) RFET with two, three, and multi gates.

Fig. 3. Connections in the proposed exact 4:2 Compressor.

Fig. 2. RFET-based full adder a) Unbalanced version [27] b) Balanced

version.

behavior of RFET is controlled by two kinds of indepen-

dent gate terminals, which are called program gates (PGs) and
control gates (CGs). The PGs determine the dominant charge
carrier, i.e., electron or hole, by modulating the drain and-or
source Schottky barriers. The CGs control the amount of car- Fig. 4. Proposed approximate 4:2 compressor a) Structure b) Truth table.
rier flow through the channel, just like the traditional CMOS
gate. Fig. 1.a shows the reconfigurability of RFET based on
different logic values of PG. Most RFETs demonstrate sym- delay [9]. In the full adder, which is shown in Fig. 2.a, input
metrical I-V characteristics in both program types that are A has the worst propagation delay compared to input B and
utilized for transistor-level reconfigurability [22]. C because it is connected to the 16 PGs. In order to prevent
Depending on the number and placement of the PGs and a high-delay critical path in the compressor (and hence the
CGs, different RFET designs have been proposed. Example final multiplier design), the difference between the delay of
schematics of RFETs with two [23], three [24], and multi the inputs should be reduced. Thus, we propose a balanced
gates [25] are illustrated in Fig. 1.b. Our designs in this brief version of the RFET-based full adder, shown in Fig. 2.b, for
are based on the three-gate RFET. Having more than one implementing our exact compressor. In the balanced version,
independent gate enables us to merge two or more transis- by changing the order of input connections the delay of input
tors in series into one transistor with a negligible increase in A is decreased and becomes close to the delay of input B.
the channel resistance [8], which leads to more compact logic Six combinations are possible for connecting Cin , X4 , and
cells. Based on the logic cell design, inputs can be applied to the output of the first full adder to the input pins of the second
CGs and PGs, knowing that in most RFETs, PG has higher full adder (A, B, and C) in the compressor. We chose the struc-
threshold voltage and slower switching [9]. ture illustrated in Fig. 3, because in this design, signals pass
through only one TG inside the compressor for five “input-
output” pairs (X1 , Cout ), (X3 , Cout ), (X4 , Carry), (Cin , Carry),
III. P ROPOSED A RCHITECTURE and (X4 , Sum). Additionally, this design makes it possible to
A. RFET-Based Compressors connect the compressors on the two levels of the PPR phase
1) Exact 4:2 Compressor: A 4:2 compressor traditionally in the multiplier in a way that results in the least number of
consists of two connected full adders. In CMOS-based design, cascaded TGs. This is further explained in Section III-B. Note
full adders are considered as large arithmetic components that pins A, B, and C in Fig. 3 indicate the full adder pins
with significant power consumption. For example, the mirror with the same name in Fig. 2.b.
adder [26], which is one of the most efficient and well-known 2) Approximate 4:2 Compressor: To design a more
CMOS-based full adders, requires 28 transistors, while RFET- compact and energy-efficient compressor for error-resilient
based full adder presented in [27] and shown in Fig. 2.a is applications, we investigate RFET benefits in designing
made up of only 14 transistors. Even considering a 1.5× [28] approximate compressors. Our approximate compressor is
area footprint for a three-gate RFET compared to a CMOS designed based on minority (Min) and multiplexer-inverter
transistor to place the extra gate signals, the area of the RFET- (MUX-INV) cells, which have efficient RFET-based imple-
based full adder would still be lower than the CMOS-based mentations. The structures of these logic cells are presented
full adder. This area reduction comes from the transistor-level in [8]. The proposed approximate 4:2 compressor is shown
reconfigurability of RFET, which enables us to design many in Fig. 4.a. This compressor is only made up of 15 transistors
logic cells like XOR and majority gates more efficiently. compared to the RFET-based exact compressor, which requires
To implement an efficient RFET-based exact compressor, it 28 transistors. In this design, similar to [1], [4], [11], [12], [13]
is crucial to consider both the design of the full adders and input Cin and output Cout are ignored as the first simplification
the connections inside the compressor. In designing the full step. The logic function of our approximate compressor can
adder, the differences between inputs connected to PG and be defined as:
CG pins should be considered, as PGs usually have a higher Sum = (X1 X2 + X1 X3 + X2 X3 )X4 + X3 X4 (1)

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 3646 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 70, NO. 9, SEPTEMBER 2023

is in the critical path. To resolve this problem without adding

extra buffers, we use input pin B instead of C for the carry
propagation. In this case, as the critical path passes through B
input pins, we create the RCA using the unbalanced full adder
shown in Fig. 2.a. In the unbalanced version, input B has a
lower propagation delay compared to the balanced version.
After applying these optimizations in the PPR and final
addition phases, a signal faces at most four cascaded TGs,
three in the PPR and one in the final addition. Hence the need
for adding buffers is eliminated. In the following, we summa-
rize our steps in designing the RFET-based exact multiplier:
a) In PPG: We use RFET-based AND operators for generating
PPs. b) In PPR: We select the 4:2 compressor shown in Fig. 4
for this phase and connect them based on our priority rule.
c) In final addition: We employ unbalanced full adders to
create the RCA and consider input B for propagating Carry
signals.
2) Approximate Dadda Multiplier: For designing the
Fig. 5. Architecture of the proposed 8 × 8 Dadda multiplier.
approximate multiplier, we replace all the exact 4:2 com-
pressors in the PPR phase with the approximate compressor
proposed in Section III-A2. Here, despite the exact multiplier,
Carry = X3 X4 + X4 (2)
we do not have the problem of cascaded TGs in the PPR phase
The truth table of the proposed approximate 4:2 compressor because the MUX-INV used in the approximate compressor is
and error distance (ED) corresponding to each output are given implemented by complementary logic, which is driven directly
in Fig. 4.b. The error rate is 37.5% and the maximum value of by VDD and GND. PPG and final addition phases are similar
ED is ±1. As the number of “+1”s and “-1”s are equal in the to the exact multiplier.
EDs, they usually can neutralize each other in the approximate
multiplier structure. IV. E XPERIMENTAL R ESULTS
This section presents the simulation result of the proposed
B. RFET-Based Multipliers compressors and multipliers. We have done circuit-level
1) Exact Dadda Multiplier: In this section, a design for SPICE simulations of the circuits using Cadence Spectre to
an exact 8 × 8 RFET-based Dadda multiplier is presented. analyze the power and performance metrics of the hardware.
In our design, we aim to minimize the number of cascaded To have a fair comparison, 14nm LSTP FinFET [29], [30]
TGs to avoid a high-resistive critical path and degraded signals and 14nm GeNW RFET model [21] are used for simulating
without adding any extra buffers. According to [27], in RFET- CMOS-based and RFET-based circuits, respectively. We have
based designs, buffers should be employed every five stages of chosen the GeNW model among other RFET models to gain
TGs to restore signal driveability. Thus, we want to keep the better performance and power trade-off. We consider supply
number of cascaded TGs under five. For this aim, we select the voltage 0.8 V and frequency 2 GHz.
proper design for the required components and connect them
properly in the PPR and final addition phases of the multiplier.
The main component of the PPR phase is the 4:2 compres- A. Compressors
sor. As mentioned, utilizing the proposed compressor structure To evaluate the efficiency of our exact compressor, we com-
shown in Fig. 3, each signal passes through one or zero TG pared it with the conventional CMOS implementation of the
inside the compressor. Besides, utilizing this design, we can exact compressor, which contains two mirror adders [26]. A
minimize the cascaded TGs in the two levels of the PPR phase mirror adder’s symmetrical pull-up and pull-down networks
by defining a priority rule for connecting the incoming signals result in equal rise and fall transition times and low power
from level one to the input pins of compressors in level two consumption. To emphasize the role of our design, we also
of the PPR phase. If we consider the PRI(X) as the priority of compared the proposed exact compressor with a naive RFET-
X, the priority orders of the incoming signals and input pins based compressor whose structure is just the same as the
are defined as: conventional CMOS implementation with 1-to-1 replacements
PRI(Carry) > PRI(Sum) > PRI(PP) (3) of CMOS transistors with RFETs. To show the benefits of
our RFET-based approximate compressor, we compare it with
PRI(X2 ) = PRI(X4 ) > PRI(X3 ) > PRI(X1 ) (4) the RFET-based exact compressor. Besides, we provide a
These relations mean the incoming signal with higher prior- comparison between the proposed RFET-based approximate
ity should be connected to the first available input pin with the compressor and a compressor with the same architecture
highest priority. This guarantees that a signal passes through a implemented using CMOS.
maximum of three compressors (two compressors in level one The simulation results of the exact and approximate com-
and one compressor in level two), hence three cascaded TGs pressors are given in Table I. We analyzed the circuits in terms
in the PPR phase. The architecture of the proposed multiplier of delay, power, power-delay product (PDP), energy-delay
with the proper connections is depicted in Fig. 5. product (EDP), and area. Delay represents the propagation
The final addition phase is carried out by a Ripple Carry delay of the critical path of the compressors, and power is
Adder (RCA). In [27], authors used input pin C to propagate the average dynamic power consumption during transitions.
the Carry signal between full adders in an RCA. However, it In addition, the PDP and EDP provide a more reasonable
results in cascaded TGs in the way of the carry signal, which evaluation of the energy consumption of the circuits. As each

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 KAVAND et al.: DESIGN OF ENERGY-EFFICIENT RFET-BASED EXACT AND APPROXIMATE 4:2 COMPRESSORS AND MULTIPLIERS 3647

TABLE I
HW A NALYSIS OF 4:2 C OMPRESSORS

TABLE II
HW A NALYSIS OF 8 × 8 DADDA M ULTIPLIERS

TABLE III
three-gate RFET is approximately 1.5× [28] larger than a sin- T HE ACCURACY OF THE A PPROXIMATE 8 × 8 M ULTIPLIERS
gle CMOS device due to its extra gate signals, we estimate
the circuit area based on the unit size transistor (UST) [28].
The proposed RFET-based exact compressor consumes 72%
less power than the CMOS counterpart with a negligible raise
in delay. Hence PDP and EDP are improved in our design by
72% and 71%. Besides, the area is reduced by 25% thanks to
the reconfigurability and multi-input support of RFET.
To show the strength of our design, we also evaluated the
naive RFET-based compressor. According to Table I, although
in the naive implementation, the power consumption has
decreased, the delay and area have increased significantly com-
TABLE IV
pared to the CMOS-based design. Hence, for achieving an T HE PSNR AND SSIM OF THE A PPROXIMATE M ULTIPLIERS
efficient RFET-based circuit, 1-to-1 replacement of CMOS
transistors with RFETs is not sufficient, and choosing a proper
design that can exploit RFET features is crucial.
According to Table I, the proposed RFET-based approxi-
mate compressor improves the delay, power, PDP, EDP, and
area by 38%, 8%, 42%, 64%, and 46% compared to the RFET-
based exact compressor. Since our approximate compressor
is designed based on the efficient RFET cells like the Min
and MUX-INV, the area and energy efficiency of its RFET
implementation is better than its CMOS implementation.
2) Accuracy Analysis of Approximate Multipliers: To
B. Multipliers report the accuracy of approximate designs, we used Error
1) HW Analysis: We simulated exact and approximate 8×8 Rate (ER), Mean Error Distance (MED), and Normalized
Dadda multipliers using the exact and approximate com- Error Distance (NED), which are commonly used accuracy
pressors introduced in Section IV-A. All the compressors metrics [31]. To evaluate the accuracy of our approximate
in the approximate multipliers are approximate. The simu- compressor in multiplication, we compared multipliers imple-
lation results of multipliers are given in Table II. Although mented using our compressor and other compressors in the
the CMOS-based multiplier has 38% lower delay than the literature. For a fair comparison, all the compressors in
RFET-based multiplier, in our design, PDP and EDP have been the multipliers are replaced with approximate compressors,
reduced by 45% and 11%, respectively, due to a significant and we do not consider any truncation. We applied all the
reduction in power consumption by 65%. As CMOS-based possible input combinations (65536 inputs) to the approxi-
AND gates have higher performance than RFET-based AND mate multipliers and calculated the accuracy metrics using
gates, this increase in delay is partly due to the AND gates MATLAB. The results of the accuracy analysis are given in
in the PPG phase. Comparing the results of our design with Table III. According to this table, the accuracy of the proposed
naive RFET-based design, we can see again that the 1-to-1 multiplier is in the range of other approximate multipliers
replacement of CMOS transistors with RFETs does not lead in the literature. However, if we implement all these designs
to an optimal design. using RFETs, our compressor has the lowest hardware com-
In comparison to the RFET-based exact multiplier, the plexity. It shows that RFET properties should be considered
RFET-based approximate multiplier reduces delay, power, to design an efficient RFET-based approximate circuit. Note
PDP, EDP, and area by 48%, 2%, 49%, 74%, and 21%, respec- that the designs with better accuracy incur much more area
tively. Moreover, the RFET-based approximate multiplier has overhead to the circuits.
better area and energy efficiency than the CMOS-based 3) Approximate Multiplier in the Image Multiplication:
approximate multiplier with the same structure. To evaluate the efficiency of the approximate multipliers

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 3648 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 70, NO. 9, SEPTEMBER 2023

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