ELECTRONICS I FOURAH BAY COLLEGE, USL 2023

FET Biasing
The general relationships that can be applied to the dc analysis of all FET amplifiers are:

For JFETS and depletion-type MOSFETs, Shockley’s equation is applied to relate the input
and output quantities:

For enhancement-type MOSFETs, the following equation is applicable:

A graphical analysis would require a plot of Shockley’s equation as shown below. Recall that
choosing VGS = VP/2 will result in a drain current of IDSS/4 when plotting the equation. For
the analysis, three points defined by IDSS, VP, and the intersection will be sufficient for
plotting the curve.

FIXED-BIAS CONFIGURATION

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The configuration of the above circuit includes the ac levels Vi and Vo and the coupling
capacitors (C1 and C2). We have established that, the coupling capacitors are “open circuits”
for the dc analysis and low impedances (essentially short circuits) for the ac analysis. The
resistor RG is present to ensure that Vi appears at the input to the FET amplifier for the ac
analysis. For the dc analysis,

The zero-volt drop across RG permits replacing RG by a short-circuit equivalent, as shown in

the circuit below.

Applying Kirchhoff’s voltage law will result

Since VGG is a fixed dc supply, the voltage VGS is fixed in magnitude, resulting in the

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“fixed-bias configuration.”
The resulting level of drain current ID is now controlled by Shockley’s equation:

The drain-to-source voltage of the output can be determined by applying Kirchhoff’s voltage
law:

For the voltage with respect to ground

Determine. VGSQ, IDQ, VDS, VD, VG, and VS for the network shown below

Solution:

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SELF-BIAS CONFIGURATION
The self-bias configuration eliminates the need for two dc supplies. The controlling gate-to-
source voltage is now determined by the voltage across a resistor RS introduced in the
network shown below.

The current through RS is the source current IS, but IS = ID and IG = 0A

Note: VGS is a function of the output current ID and not fixed in magnitude as it was for the
fixed-bias configuration.

The level of VDS can be determined by applying Kirchhoff’s voltage law to the output circuit

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Eg. Determine VGSQ, IDQ, VDS, VS, VG, VD for the network shown below

Solution
The gate-to-source voltage is determined by

Using Shockley diode equation

At the quiescent point

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VOLTAGE-DIVIDER BIASING
The voltage-divider bias arrangement applied to BJT transistor amplifiers is also applied to
FET amplifiers as shown in the network below. The basic construction is exactly the same,
but the dc analysis of each is quite different. IG = 0 A for FET amplifiers, but the magnitude
of IB for common-emitter BJT amplifiers can affect the dc levels of current and voltage in
both the input and output circuits. Recall that IB provided the link between input and output
circuits for the BJT voltage-divider configuration while VGS will do the same for the FET
configuration.

The network below is redrawn for the dc analysis with the source separated to permit
separation of the input and output regions of the network

If IG = 0 A, then IR1 = IR2 and using voltage divider rule as follows:

Applying Kirchoff’s voltage law

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If we select ID to be 0 mA

For the other point, at any point on the vertical axis VGS = 0 V and solve for the resulting
value of ID

Once the quiescent values of IDQ and VGSQ are determined, the remaining network analysis
can be performed in the usual manner. That is,

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Eg. Determine IDQ and VGSQ, VD, VS, VDS, VDG for the network shown below

Solution
For the transfer characteristics, if ID = IDSS/4 = 2 mA, then VGS = VP/2 = 2 V. The resulting
curve represent Shockley’s equation.

The network equation is defined by

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The resulting bias line with quiescent values appears on the graph

DEPLETION-TYPE MOSFETs
The similarities in appearance between the transfer curves of JFETs and depletion type
MOSFETs permit a similar analysis of each in the dc domain. The primary difference
between the two is the fact that depletion-type MOSFETs permit operating points with
positive values of VGS and levels of ID that exceeds IDSS. In fact, for all the configurations
discussed thus far, the analysis is the same if the JFET is replaced by a depletion-type
MOSFET.

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The only undefined part of the analysis is how to plot Shockley’s equation for positive values
of VGS. How far into the region of positive values of VGS and values of ID greater than IDSS
does the transfer curve have to extend.

Eg. For the n-channel depletion-type MOSFET of the figure below determine:
(a) IDQ and VGSQ
(b) VDS

Solution

(a) For the transfer characteristics, a plot point is defined by ID = IDSS/4 =

1.5 mA and VGS = VP/2 = 1.5 V. Considering the level of VP and the fact that Shockley’s
equation defines a curve that rises more rapidly as VGS becomes more positive, a plot point
will be defined at VGS = 1 V. Substituting into Shockley’s equation yields

The resulting transfer curve appears as shown on the graph below. Proceeding as described
for JFETs, using the voltage divider rule:

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The plot points and resulting bias line appear on the graph

ENHANCEMENT-TYPE MOSFETs
The transfer characteristics of the enhancement-type MOSFET are quite different from those
encountered for the JFET and depletion-type MOSFETs, resulting in a graphical solution
quite different from the preceding sections. First and foremost, recall that for the n-channel
enhancement-type MOSFET, the drain current is zero for levels of gate-to-source voltage less
than the threshold level VGS(Th) as shown in Fig. 6.35. For levels of VGS greater than VGS(Th),
the drain current is defined by

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Since specification sheets typically provide the threshold voltage and a level of drain current
(ID(on)) and its corresponding level of VGS(on), two points are defined immediately as shown
above. To complete the curve, the constant k of the equation above must be determined from
the specification sheet data by substituting into equation and solving for k as follows:

Once k is defined, other levels of ID can be determined for chosen values of VGS.

Feedback Biasing
A popular biasing arrangement for enhancement-type MOSFETs is the feedback biasing
shown below. The resistor RG brings a suitably large voltage to the gate to drive the
MOSFET “on.”

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Since IG = 0 mA and VRG = 0 V, the dc equivalent network appears as shown below.

A direct connection now exists between drain and gate, resulting in

For the output circuit,

The equation above is that of a straight line, the same procedure described earlier can be
employed to determine the two points that will define the plot on the graph. Substituting
ID = 0 mA into

Substituting VGS = 0 V into the equation above, we have

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The plots defined by the equation above appear in with the resulting operating point.

Eg. Determine IDQ and VDSQ for the enhancement-type MOSFET of the figure below.

Solution

Plotting the transfer curve by solving for k

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For a value slightly greater than VGS(Th)) assume VGS = 10 V

For the network bias line

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At the operating point, the resulting Q-point of operation are:

Voltage-Divider Biasing

The fact that IG = 0 mA results in the following VGG given as

Applying KCL around the indicated loop shown in the network above

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Since the characteristics are a plot of ID versus VGS and the equations above relates the same
two variables, the two curves can be plotted on the same graph and a solution determined at
their intersection. Once IDQ and VGSQ are known, all the remaining quantities of the network
such as VDS, VD, and VS can be determined.

Eg. Determine IDQ, VGSQ, and VDS for the network shown below.

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From the plot, the point of operation is:

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