2018 TCASI I. Galton Understanding Phase Error and Jitter Definitions Implications Simulations and Measurement
2018 TCASI I. Galton Understanding Phase Error and Jitter Definitions Implications Simulations and Measurement
Abstract— Precision oscillators are ubiquitous in modern elec- multiplication by a sinusoidal oscillator signal whereas most
tronic systems, and their accuracy often limits the performance practical mixer circuits perform multiplication by squared-up
of such systems. Hence, a deep understanding of how oscillator oscillator signals. Fundamental questions typically are left
performance is quantified, simulated, and measured, and how unanswered such as: How does the squaring-up process change
it affects the system performance is essential for designers. the oscillator error? How does multiplying by a squared-up
Unfortunately, the necessary information is spread thinly across
the published literature and textbooks with widely varying
oscillator signal instead of a sinusoidal signal change a mixer’s
notations and some critical disconnects. This paper addresses this behavior and response to oscillator error?
problem by presenting a comprehensive one-stop explanation of Another obstacle to learning the material is that there are
how oscillator error is quantified, simulated, and measured in three distinct oscillator error metrics in common use: phase
practice, and the effects of oscillator error in typical oscillator error, jitter, and frequency stability. Each metric offers advan-
applications. tages in certain applications, so it is important to understand
Index Terms— Oscillator phase error, phase noise, jitter, how they relate to each other, yet with the exception of [1],
frequency stability, Allan variance, frequency synthesizer, crystal, the authors are not aware of prior publications that provide
phase-locked loop (PLL). this information directly.
The goal of this tutorial is to comprehensively and sys-
tematically present this information. There are many publica-
I. I NTRODUCTION tions that describe and model the circuit-level mechanisms of
for v(t) ensures that V B I AS − v(t) is only between Vo f f provided the limit exists, where f has units of Hz, and
and Von very near the zero-crossing times of v(t). One FT{φT (t)} is the Fourier transform of φ(t) restricted to the
consequence is that e(t) can be neglected much like in the case interval 0 ≤ t ≤ T . Specifically,
of the mixer described above. Another consequence is that ∞
each transistor’s nonlinear transition between its on and off F T {φT (t)} = φT (t)e− j 2π f t dt (12)
states has little effect on the sampling circuit’s performance. −∞
Hence, the frozen voltage stored on the capacitor when v(t)
is close to V0 well-approximates x(τn ). where
4) Other Clocking Applications: Oscillators are also used to
φ(t), if 0 ≤ t ≤ T,
clock a wide range of other analog, mixed-signal, and digital φT (t) = (13)
0, otherwise.
circuits including DACs, frequency dividers, phase-frequency
detectors (PFDs), time-to-digital converters (TDCs), digital- As is well known and can be verified from the definition
to-time converters (DTCs), timers, and synchronous digital above, Sφφ ( f ) for any value of f can be interpreted as 1/ f
logic. In most cases, the components within these circuits times the time average power of φ(t) in the frequency band
that are clocked by the oscillator signals are edge-triggered between f and f + f in the limit as f → 0. Hence, each
latches or flip-flops. value of Sφφ ( f ) represents a power density per Hz. In this
The clock input of each such edge-triggered latch or flip- case, φ(t) has units of radians, so Sφφ ( f ) has units of radians2
flop is driven by a clock signal of the form V B I AS + v(t), per Hz.
where, once again, V B I AS is a constant bias voltage and Replacing |FT{φT (t)}|2 in (11) by the product of the right
v(t) is a squared-up oscillator signal. By design, the edge- side of (12) and the complex conjugate of the right side of (12)
triggered circuit only changes its state when v(t) is in a and rearranging the result yields
narrow range of values about its midpoint, and V0 is large
enough that that −V0 + e(t) and V0 + e(t) are outside this ∞
range for all t. Therefore, by exactly the same reasoning Sφφ ( f ) = Rφφ (τ )e− j 2πτ f dτ , (14)
−∞
described above for mixers and sampling circuits, such circuits
are insensitive to e(t). where Rφφ (τ ) is given by
T
E. Phase Error Versus Phase Noise 1
Rφφ (τ ) = lim φ(t)φ(t + τ )dt (15)
T →∞ T
An oscillator signal’s phase error, φ(t), usually contains 0
both a random component and a deterministic component. The and is called the time average autocorrelation of φ(t).
random component is caused by device noise, such as thermal Equation (14) implies that Sφφ ( f ) is the Fourier transform of
and flicker noise, introduced by the transistors and other com- the time average autocorrelation. Applying the inverse Fourier
ponents that make up the oscillator circuit. The deterministic transform to (14) gives
component is the result of deterministic disturbances that are
∞
inadvertently generated within or parasitically coupled into the
oscillator circuitry. For example, the deterministic component Rφφ (τ ) = Sφφ ( f ) e j 2πτ f d f . (16)
−∞
of φ(t) in a PLL-based oscillator inevitably contains spurious
tones, also known as spurs, that are not harmonics of the It follows from (15) that the time average power of φ(t) is
oscillator frequency. Rφφ (0), so (16) implies that the time average power of φ(t)
In this paper, φ(t) is called phase error and the random is the integral of Sφ ( f ) over all frequencies.
component of φ(t) is called phase noise. This choice was The Fourier transform of any real-valued function is conju-
made to avoid confusion because the word noise is considered gate symmetric, and |c| = |c∗ | for any complex number c,
by many people to denote purely random phenomena. It is also so (11) implies that Sφφ ( f ) = Sφφ (− f ). Consequently,
consistent with much of the published literature, e.g., most the one-sided time average power spectrum of φ(t), defined as
papers that report the measured performance of PLL-based
oscillators refer to phase noise and spurious tones as distinct Sφ ( f ) = 2Sφφ ( f ) for f ≥ 0, (17)
types of phase error. Unfortunately, the literature is not con-
sistent in this respect. For instance, in the IEEE standard is often used. The factor of 2 ensures that the time average
φ(t) is called phase fluctuations and, somewhat confusingly, power of φ(t) is the integral of Sφ ( f ) over all positive
the term phase noise is reserved exclusively for a function frequencies.‡
L( f ) (pronounced “script-ell of f ”) equal to half the one-sided As described above,
time average power spectrum of φ(t) [10].
1
L( f ) = Sφ ( f ) (18)
2
F. Time Average Power Spectra
Laboratory measurements and circuit simulations of power by definition. This definition is important because L( f ) is
spectra inevitably estimate time average power spectra as what laboratory phase noise measurement instruments esti-
opposed to statistical power spectra [17]. The two-sided time mate. For reasons explained in Section III-A, when L( f ) is
average power spectrum of a real-valued continuous-time expressed in decibels (dB), i.e., 10log10(L( f )), its units are
signal, in this case φ(t), is defined as defined to be dBc/Hz.
1 ‡ For the remainder of the paper, all time average power spectra are referred
Sφφ ( f ) = lim |F T {φT (t)}|2 for − ∞ < f < ∞ (11)
T →∞ T to as just power spectra for brevity.
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v(t) ∼
= A sin (ω0 t) + A cos (ω0 t) φ(t). (22)
B. Continuous-Time Versus Discrete-Time Paradox
The first and second terms on the right side of (22) are the
It is argued in Section II that only the samples of a squared-
ideal oscillator signal and an additive noise term caused by
up oscillator signal’s phase error at the oscillator signal’s
oscillator phase error, respectively.
zero-crossing times, i.e., φ(tn ), affect the oscillator output
The power spectrum of v(t) and its properties are given
waveform in the absence of e(t) error. Yet it is argued in
by (11)-(17) except with φ replaced by v. Given that the ideal
Section III-A that in many cases of interest the power spectrum
oscillator signal term in (22) has zero bandwidth, the one-sided
of the fundamental term of such an oscillator signal is a
power spectrum of v(t) for f = ω0 /(2π) only depends on
function of the power spectrum of the continuous-time phase
the noise term. It follows from well-known Fourier transform
error waveform, φ(t). This apparent contradiction can be
properties and the power spectrum definition that the one-sided
resolved as follows.
power spectrum of v(t) can be written as
As described in Section II-C, a squared-up oscillator signal
A2 ω0 ω0 can be used in place of a sinusoidal oscillator signal provided
Sv ( f ) ∼
= Sφ f − for f = . (23) the power spectra of the terms in the squared-up signal
4 2π 2π
centered at integer multiples of f 0 = ω0 /(2π) do not overlap
This can be rearranged and combined with (18) to give the power spectrum of the fundamental term centered at f 0 .
ω0 This requires that Sφφ ( f ) be bandlimited to a bandwidth that
Sv 2π + f
L( f ) ∼
= for f > 0. (24) is lower than f 0 /2. In such cases the definition of Sφφ ( f )
A2 /2 given by (11)-(13) implies that FT{φT (t)} is also bandlimited
The right side of (24) used to be the definition of L( f ) [22]. with this bandwidth in the limit as T → ∞. It follows from
When this was the case, (18) followed from this definition as the sampling theorem that FT{φT (t)} in (11) can be replaced
an approximation. The old definition had the advantage that it
was a proxy for Sφ ( f )/2 that could easily be measured directly § Older literature often shows phase noise as L( f ) to underscore this fact.
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Both the broadband phase and the broadband additive error are
sampled at the zero crossings of the oscillator signal. The lim-
iting amplifier’s wide bandwidth typically causes aliasing of
many bands of broadband noise into the | f | < f0 /2 frequency
band.
The conversion of additive error to phase error also affects
the clock buffers which follow the limiting amplifier. The
purpose of a clock buffer is to maintain the squared-up
edges of the clock signal over long transmission distances,
and therefore is susceptible to the same error-sampling effect
discussed for limiting amplifiers. While each clock buffer may
only contribute a small amount of phase error, in ICs such as
network routers or FPGAs where GHz clocks are distributed
several centimeters, their cumulative error usually dominates
the oscillator’s intrinsic phase error [23], [24].
Fig. 7. Sampling behavior of the limiting amplifier on the oscillators phase The simulation methodology described in Section VI-A
and additive error. ensures that the sampling and conversion effects described
above are properly captured, so that any amplitude error on
by T0 times the discrete-time Fourier transform of φ(nT0 ) for the resulting squared-up clock signal can usually be ignored,
| f | < f 0 /2. Hence, in such cases as explained in Section II-B. The phase error power spectrum
of this squared-up clock signal can then be “input-referred”
Sφφ ( f )
⎧ as shown in Fig. 7 to generate the equivalent band-limited
∞ 2
⎪
⎨ T2 f0 Sφφ ( f ) which contains all the sampled noise.
− j 2π f nT0
lim 0 φT (nT0 ) e , if | f | < ,
= T →∞ T 2 Throughout the remainder of the paper, Sφφ ( f ) is used
⎪
⎩ n=−∞
in equations that relate the phase error power spectrum to
0, otherwise. samples of the phase error or, equivalently, to jitter, as a proxy
(25) for either the actual phase error power spectrum or Sφφ ( f ).
Provided the bandwidth of Sφφ ( f ) is sufficiently low, (10) In cases where the actual phase error is bandlimited to
implies that φ(τn ) ∼ | f | < f 0 /2, the reader should view Sφφ ( f ) as denoting
= φ(nT0 ) to a high degree of accuracy.
In such cases, it follows from (25) that Sφφ ( f ) can be the power spectrum of the actual phase error. Otherwise,
expressed as a function of φ(t) sampled at the oscillator the reader should view Sφφ ( f ) as denoting Sφφ ( f ). In this
signal’s positive-going zero-crossing times. A nearly identical way, the quantity denoted by Sφφ ( f ) in such equations is
argument shows that it can also be expressed as a function of bandlimited to | f | < f 0 /2 by definition.
φ(t) sampled at the oscillator signal’s negative-going zero- D. Why Sφφ ( f ) Increases With Oscillator Frequency
crossing times. Thus, provided |φ(t)| << 1, it follows As can be seen from (1) and (6), oscillator frequency,
from (17), (23), and (25) that Sv ( f ) can be expressed as a ω0 , and phase error, φ(t), are separate variables in both
function of φ(tn ) instead of φ(t). the sinusoidal and squared-up oscillator signal models. This
C. Sampled Phase Error separation obscures an implicit dependency of phase error
on oscillator frequency that arises because phase error rep-
The assumption that Sφφ ( f ) = 0 for | f | ≥ f 0 /2, which resents the oscillator’s timing error as a fraction of its period
led to (25), is usually acceptable in wireless transceivers, but its period is inversely proportional to its frequency. For
because the various signal paths in wireless transceivers example, (10) implies that changing an oscillator’s frequency
typically have bandwidths much less than f 0 /2 by design. by X dB without changing the mean squared value of its
In contrast, the assumption is rarely valid in clocked systems absolute jitter would increase its phase error power by 2X dB.
which generally lack equivalent band-limiting circuits. In such Indeed, it has been shown for many different types of
cases, (25) does not hold because sampling the phase error at oscillators that the effect of circuit noise on absolute jitter
a rate of f 0 causes aliasing. is relatively independent of the frequency to which a given
A common approach to avoid this problem is to replace oscillator is tuned [25]–[28]. In such cases, changing the
the actual phase error power spectrum, Sφφ ( f ), with a con- oscillator’s frequency does not significantly change the mean
ceptual modified phase error power spectrum, Sφφ ( f ), equal squared value of its absolute jitter.
to the right side of (25). Even though Sφφ ( f ) = Sφφ ( f ) This effect can cause confusion when comparing the phase
when Sφφ ( f ) is not bandlimited to | f | < f 0 /2, Sφφ ( f ) is noise performance of oscillators tuned to different frequencies.
bandlimited to | f | < f 0 /2 and already contains all content that The confusion can be avoided by normalizing the phase noise
would have aliased into the frequency band | f | < f 0 /2 had of the oscillators to a common frequency prior to comparing
Sφφ ( f ) been sampled at a rate of f0 . Accordingly, Sφφ ( f ) can their phase noise spectra. The phase noise of an oscillator
be used in place of Sφφ ( f ) in all of this paper’s results that normalized to a frequency ωn is (ωn /ω0 )2 Sφφ ( f ) where ω0 is
relate the phase error power spectrum to f0 -rate samples of the nominal frequency and Sφφ ( f ) is the phase noise spectrum
the phase error or, by extension, to absolute jitter. of the oscillator. In general, the phase noise of two oscillators
Fig. 7 shows how this approach can be extended to handle normalized to the same frequency will be approximately equal
broadband additive error that gets converted to phase error if they have equivalent jitter performance. For example, two
when a sinusoidal oscillator signal is amplified and clipped by oscillators, one with frequency ω0 and phase error power
a limiting amplifier to generate a squared-up oscillator signal. spectrum Sφφ ( f ) and one with frequency 2ω0 and phase error
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jitter can be approximated as y[n] ∼ = x(nT 0 ) + x (nT0 ) · τn , necessary to capture phase error quantities of interest. For
where x (t) is the first derivative of x(t). example, to measure the phase error of a 1 GHz oscillator
Even with these assumptions and approximation, the jitter- down to 1 kHz would require running a transient simulation
induced error, x (nT0 ) · τn , is hard to analyze without for one million oscillator periods just to capture a single period
simulation. Textbooks typically consider a worst-case scenario of a 1-kHz phase error component.
in which x(t) is a maximum-frequency, maximum-amplitude For the past few decades, simulation methods have been
sinusoid, x(t) = Amax sin(ωx t) [33]. In this case, the sampled available that greatly accelerate the analysis of relatively
voltage error is approximately Amax ωx τn cos(ωx nT0 ). Thus, simple circuits that generate and process periodic signals, such
prior to quantization, this jitter-induced error already sets an as oscillators and clock buffers. While such methods are much
upper bound on the maximum achievable SNR given by faster than direct transient simulation, they have limitations,
as described below, which make them generally inapplica-
1 2
2 A max 1 ble to the simulation of larger systems such as PLL-based
S N Rmax = 10 log10 1 2 = 10 log10 .
2 A max ωx σabs
2 2 ω2x σabs
2 oscillators.
(37) For larger systems, it is more common to use the data gener-
ated in block transistor-level simulations to develop behavioral
Restricting x(t) to be a single sinusoid makes the analysis models, which are then used to simulate the complete system
tractable, but it has been shown empirically that the SNRs in an event-driven simulator. As explained below, event-driven
of ADCs with broadband input signals achieve much higher simulators are ideally suited for simulating large systems that
performance than the single-tone result would suggest [34]. process discrete events, such as an oscillator’s zero crossings.
Yet (37) remains useful as pessimistic performance bound.
Moreover, σabs , the clock quality metric on which SNRmax A. Transistor-Level Simulation
depends, is often used instead of Sφ ( f ) to stipulate the To perform a phase noise or random jitter simulation,
required ADC clock quality in applications. When an ADC’s the simulator must first compute the circuit’s periodic steady
input signal, x(t), is broadband, the error caused by jitter, state, which is comprised of the periodic waveforms at the
i.e., x(nT0 + τn ) – x(nT0 ), tends to be spread across the various circuit nodes after all transient settling effects have
Nyquist band in a way that does not depend strongly on died out. For example, when an oscillator with a high-
the shape of Sφ ( f ), so σabs is a more convenient metric. Q resonator is started, it usually takes many cycles for
Notable exceptions are software-defined and reconfigurable the oscillation envelope to stabilize. In contrast, a clock
radios in which ADCs capture broad spectrum signals, but buffer driven by an external clock signal may only need
the constituent desired signals and interferers each occupy a few cycles to stabilize [38]. There are two main tech-
relatively narrow bandwidths [35]. In such cases, Sφ ( f ) is niques used to compute this solution: shooting and harmonic
required to characterize the full radio performance [36]. balance [39]–[41].
The shooting method is a time-domain approach wherein
F. Jitter Histograms the circuit is iteratively simulated over a time interval equal
to the expected period. After each iteration, the differences
Equation (33) provides a means with which to calculate
between the circuit’s initial and final states are measured, and
σabs from J ( f ), but it is possible to approximate σabs without
the initial state for the next iteration is modified. This process
knowing J ( f ) by plotting a histogram of the τn sequence.
continues until the circuit’s final state is equal to its initial
The histogram provides an estimate of the probability distribu-
state, indicating the periodic solution is achieved [39]. The
tion of τn from which σabs can be calculated directly. This is
majority of the computation time is spent on transient simu-
useful in applications like ADC clocking wherein J ( f ) is not
lations, so this method is especially effective for circuits with
particularly useful. Furthermore, with reasonable assumptions
short periodicities, e.g., multi-GHz RF oscillators. Moreover,
on the sources of the random and deterministic absolute jitter
as the waveforms are computed in the time-domain, sharp
contributions to the total absolute jitter, it is possible to
transitions resulting in broadband frequency-domain content,
estimate the relative magnitudes of their contributions [37].
such as occur in ring oscillators and CMOS clock buffers, are
For many clocked systems, jitter histograms are also a useful
not problematic [42].
visualization of clock signal phase error. For example, in a
In contrast, harmonic balance is considered a frequency-
serial communication receiver there is a circuit which samples
domain method. The circuit is first divided into two partitions,
incoming data at time intervals controlled by a sampling clock.
one containing all the linear elements, and another containing
As described in Section VII-C, it is usually possible to observe
the nonlinear elements. The simulator iteratively solves for
the waveforms of the data and sampling clock in the time
the voltages at, and current through, the nodes at the interface
domain. Knowing the histogram of the sampling clock jitter
between these two partitions. Given an initial guess at the
shows the distribution of when the data is sampled in time,
node voltages, the currents into the linear partition are solved
which is usually informative because realistic absolute jitter
in the frequency domain, which are computed using simple
histograms are non-Gaussian. In contrast, simply calculating
matrix multiplications. This is much faster than a transient
σabs by integrating J ( f ) would give no information on the
simulation which requires iteratively solving differential equa-
distribution of τn .
tions. The currents into the nonlinear partition are solved by
first applying the Inverse-Fast-Fourier Transform (IFFT) to the
VI. P HASE E RROR S IMULATION node voltages, computing the currents in the time domain,
In principle, an oscillator’s phase error could be esti- then returning them to the frequency domain via the FFT.
mated via transistor-level transient simulations. However, this By Kirchoff’s current law, the current into the linear partition
is rarely practical, even with present-day high-performance must equal the current leaving the nonlinear partition, so the
computers. The difficulty arises from the large timescales simulator iterates until this condition is satisfied.
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The computation of the nonlinear currents is cumbersome, is performed on the clock signal at the output of the limiting
but the huge speed advantage gained in the frequency-domain amplifier.
computation of the linear currents gives the harmonic bal- In spite of the advancements in simulator technology, there
ance method an overall advantage for circuits which are are still situations where simulating the combined oscillator
weakly nonlinear, only have a few nonlinear elements, or have and limiting amplifier can cause the simulator to have conver-
extremely long periodicities. For weakly nonlinear circuits, gence issues. For example, this often occurs when simulating
the overhead of the FFT and IFFT operations is modest a high-Q crystal oscillator driving a CMOS limiting amplifier.
because the circuit solution can be represented by only a For the reasons discussed above, the oscillator and its limiting
few harmonics in the frequency domain, and by having few amplifier are optimally simulated using the harmonic balance
nonlinear elements, the quantity of time-domain computations and shooting methods, respectively, so their combination is
is reduced. For circuits with long periodicities, to achieve challenging for either simulator. In this situation, what is
a given accuracy the harmonic balance method is usually often done is to perform separate simulations on each block,
more efficient than the shooting method because it does not while loading the oscillator with an approximation of the
suffer from accumulated numerical noise which plagues long CMOS buffer load, and driving the CMOS buffer with an
transient simulations. Ideal candidates for harmonic balance approximation of the oscillator’s sinusoidal output. The two
analysis are low-noise, extremely high-Q systems such as results are then added in power to represent the total phase
crystal oscillators [42]. noise at the CMOS buffer’s output.
Regardless of how the circuit’s periodic steady state solution When simulating clock buffer chains, their layout strongly
is calculated, the second step in a phase noise or random jitter influences the clock signal waveforms, which in turn influ-
simulation is to use this solution to compute how the different ences their jitter performance. It is therefore important to
circuit noise sources contribute to voltage noise on the periodic electromagnetically model the interconnect between the clock
signal at a chosen node. This method takes advantage of the buffers, including both the signal and ground return path,
periodicity of the signals within the circuit so that the effect of to account for potential transmission-line effects that are not
very low frequency circuit noise can be analyzed using only accurately captured in RC parasitic extractors [51]. The results
a single period of the circuit’s behavior [43], [44]. from electromagnetic simulators are invariably high-order
The distinctions made in the above discussion regarding the frequency-domain models in the form of s- or y-parameters.
types of circuits best suited to either the shooting or harmonic Such models are most efficiently simulated in their native form
balance methods were more critical when these methods using the harmonic balance method. Alternatively, their domi-
were first developed. However, the rapid improvement in nant effects can usually be captured in lumped element models
simulation and computer technology over the intervening to be used with transient-based simulators, and some simula-
decades has blurred this separation. While there do still exist tors can automatically perform this conversion [46], [47].
specialized problems which are better served by one or the Clock buffer chains are also highly sensitive to their power
other method, there are now general-purpose industry-standard supplies and power distribution networks. This includes the
simulation tools based on both methods, as well as hybrid interconnect between the clock buffers’ voltage regulators,
methods [45], [46]. the voltage regulators themselves, and even the package
Moreover, while early incarnations of these simulators models. Clock buffer supply current waveforms usually have
only estimated the raw signal power spectrum, present-day broadband content at frequencies well beyond a voltage
simulators are able to estimate both phase and amplitude regulator’s bandwidth. At these high frequencies, there are
error power spectra, and decompose the spectra into upper- often parasitic resonances. Therefore, accurate clock buffer
and lower-sideband contributions [47]. Furthermore, provided simulations require not only the circuits and their drivers and
the necessary information, they can accurately compute the loads, but electromagnetic models of their complete on-chip
modified phase error power spectrum resulting from sampling environment, and their supply circuitry as well [52]–[54].
and/or noise folding, as discussed in Section III.C [48].
Simulation technology has reached a level of maturity where
the simulator tool is typically no longer the design bottleneck. B. Behavioral Simulation
Rather, assuming the device models are accurate, most analysis There are two major obstacles to using the simulation
errors are the result of improper or incomplete simulation methods described above for more complicated systems such
methodology. For example, a complete clock distribution sys- as PLL-based oscillators. The first obstacle is that a peri-
tem comprised of an oscillator, limiting amplifier, and clock odic steady-state solution must exist and be computed [42].
buffers is usually still too large to be simulated efficiently This precludes the simulation of fractional-N type PLL-based
in one circuit. Rather, it is partitioned into sections which are oscillators, as well as systems which use digitally-generated
simulated independently. Unfortunately, oscillators and buffers pseudorandom dither, because such circuits tend to have
tend to be extremely sensitive to the circuits they drive, and extremely long periods (e.g., several days) [48]. The second
buffers additionally tend to be sensitive to the circuits that obstacle is that even in cases where the period is relatively
drive them [49], [50]. Therefore, realistic driving and loading small, the complexity of a complete PLL-based oscillator
conditions must be included when simulating each partition. imposes impractical processing and memory requirements, and
In particular, the oscillator and its limiting amplifier is a even when these resources are available, computing the peri-
critical combination, as the interface between them is espe- odic steady-state solution can still take days. This simulation
cially susceptible to broadband additive noise to phase noise methodology would provide little utility during the design
conversion. When simulating the jitter of an oscillator and phase, where many iterations usually are required.
its limiting amplifier, the clock buffer following the limiting A more practical method for simulating PLL-based oscil-
amplifier should be included. This only serves as a realistic lators is to use behavioral event-driven simulations [55]–[57].
load, for reasons described above, as the simulation analysis These simulations offer a huge speed advantage over transient
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transistor-level simulations, because behavioral event-driven signal in the frequency band ( f − RBW/2, f + RBW/2).
simulations only capture the relevant functionality of circuits This is proportional to an estimate of the power spectrum of
rather than all of the voltages and currents of every node with the oscillator signal, Sv ( f ), as described in Section II-F. The
very small time steps. For example, a transistor-level oscillator accuracy of this estimate improves as the RBW decreases.
simulation iteratively solves differential equations to compute If the assumptions that ε(t) ∼ = 0 and |φ(t)| << 1 made
many points per period of the oscillator waveform. Yet, as has in Section III-A are valid, then (23) can be used to estimate
been argued throughout this paper, many circuits driven by an Sφ ( f ) from Sv ( f ). As oscillator phase error power spectra
oscillator signal are insensitive to the oscillator signal at times tend to rise at low frequencies, this approximation becomes
other than its zero crossings. Therefore, PLL-based oscillators invalid at very low offsets from the carrier [61]. Extremely
are almost always behaviorally-modeled by generating the low frequency oscillator phase error is indistinguishable from
sequence of their rising or falling zero-crossing times, τn . This frequency drift, which can also corrupt spur measurements,
sequence can be processed using (10) and (25) to generate the as explained shortly.
conceptual band-limited phase error power spectrum, Sφφ ( f ). Most spectrum analyzers have modes specifically for phase
Even though the shape of the oscillator signal waveform is lost noise measurement which perform the carrier power normal-
in a behavioral simulation, many non-idealities such as noise ization and apply any instrument-specific correction factors
and nonlinearity can still be accurately modeled [55]–[59]. automatically. Examples of correction factors include account-
The main drawback of behavioral event-driven simulations ing for the exact transfer function of the equivalent bandpass
is that their results are only as accurate as their behav- filter, and accounting for non-idealities in the power detector
ioral models of the circuit’s sub-blocks. Care is therefore that follows the equivalent bandpass filter [62], [63].
required to continually cross-verify the behavioral models If amplitude error is not negligible, then replacing A with
against transistor-level simulations of the corresponding circuit [ A+ε(t)] in (20) results in an extra additive term ε(t) sin(ω0 t)
sub-blocks. in (22). Furthermore, any additive error on the oscillator signal
Mixed-signal simulators, or co-simulators, bridge the gap will also appear in its power spectrum. Therefore, the oscillator
between the speed of behavioral event-driven simulators and signal power spectrum contains both amplitude error as well
the functional accuracy of transistor-level simulators [60]. as additive error, and these errors are indistinguishable from
A co-simulator can efficiently simulate a system comprised phase error in Sv ( f ). This results in a pessimistic estimate of
of transistor circuits, behaviorally-modeled circuits, and fully- Sφ ( f ) from Sv ( f ).
digital circuits. The behavioral models are written in a mixed- The full form of the right side of (22) including ampli-
signal language such as Verilog-AMS, while the digital circuits tude modulation is the carrier signal plus ε(t)sin(ω0 t) +
can be described in Verilog. The co-simulator partitions the Acos(ω0 t)φ(t), where ε(t) and Aφ(t) can be viewed as com-
system into its different types, and runs simulators optimized plex modulation of the carrier. Therefore, when the oscillator
for each type in lock-step. Data between the simulated parti- signal has both phase and amplitude error, the sidebands of
tions is continually communicated, so that the whole system its power spectrum are no longer symmetric, in contrast to the
is simulated in unison. case of pure phase error described in Section III-A. Parasitic
The power of a co-simulation is that a design can start coupling in both the circuit as well as the measurement setup
with all behavioral models, and then transistor-level circuit can result in amplitude modulation of the oscillator signal,
blocks can be used in place of the corresponding behavioral leading to such asymmetries. This effect is often noticeable in
models as they are designed. As different combinations of the spurious tones of PLL-based oscillators.
transistor-level circuits and behavioral models can be run, As explained in Section III-A, the power of a spur in the
this implicitly improves the behavioral model verification. oscillator phase error power spectrum at frequency f m is equal
Unfortunately, because the analog portions of the system are to the power of the spur in the oscillator signal power spectrum
simulated with a transistor-level simulator, co-simulations still at frequency f0 + f m , divided by the power of the carrier. Thus,
take orders of magnitude more simulation time than fully the phase error spur power in dBc can be read from a dB-scale
behavioral simulations. oscillator signal power spectrum as the difference between the
values of the power spectrum at f0 + f m and f 0 .
VII. P HASE E RROR M EASUREMENT However, there is a caveat to this spur measurement tech-
nique. As described above, the value of the spectrum analyzer
A. Spectrum Analyzers measurement at frequency f 0 + f m is the power at the output
A spectrum analyzer performs the equivalent of passing its of the conceptual RBW-bandwidth bandpass filter centered
input signal through a bandpass filter whose center frequency at frequency f 0 + f m . Therefore, the measured power is
is swept across a user-defined range of frequencies, called approximately the sum of the spur power plus the oscillator
the span.†† This frequency-swept bandpass filter is called the signal noise power density integrated over the band ( f 0 + f m −
equivalent bandpass filter. The power of the equivalent band- RBW/2, f 0 + f m + RBW/2). As the power of the spur of
pass filter’s output signal is measured, and this power is plotted interest decreases, the RBW must be decreased so that the
on the spectrum analyzer display’s vertical axis on a dB scale measured power at that frequency is dominated by the spur
against the equivalent bandpass filter’s center frequency on power, not the integrated noise power.
the horizontal axis. The bandwidth of the equivalent bandpass The left plot in Fig. 10 shows a PLL-based oscillator’s signal
filter is called the resolution bandwidth (RBW), and the time measured power spectrum over a 100 kHz span centered at the
it takes for the equivalent bandpass filter’s center frequency to 2.4 GHz carrier frequency, measured by a Rohde & Schwarz
traverse the span is called the sweep time. FSW13 spectrum analyzer. Symmetric spurs are visible at
If the spectrum analyzer input is driven by an oscillator
signal, then the displayed power on the spectrum analyzer †† This is a behavioral description, not an explanation of how spectrum
at a frequency f is equal to the power of the oscillator analyzers are implemented (a good explanation of which can be found in [17]).
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Fig. 10. Measured power spectra of a PLL-based oscillator signal (left) and its phase noise (right).
approximately 7.4, 14.7, and 29.5 kHz offsets from the carrier, lock the spectrum analyzer’s local oscillator to the PLL-based
with the largest shown by the delta marker as −73 dBc. The oscillator’s reference oscillator [62]. In this case, the spectrum
phase noise of this PLL-based oscillator in the 10 kHz to analyzer’s local oscillator has the same frequency drift as
100 kHz region is known to be −108 dBc/Hz. However, the PLL-based oscillator, which avoids the spur-measurement
because this measurement was taken with a 10 Hz RBW problem described above.
and without averaging, any spur below about −80 dBc would
become indistinguishable from the noise, so to resolve a lower-
power spur would require a narrower RBW. B. Phase Noise Analyzers
Unfortunately, narrow RBWs can complicate spur measure- The lowest-noise phase noise measurements are made with
ments and lead to erroneously optimistic results, because the phase noise analyzers, which are also called signal source ana-
time it takes for the spectrum analyzer to measure the power lyzers depending on the manufacturer. Phase noise analyzers
at the output of the equivalent bandpass filter increases as the are essentially extremely sensitive receivers, and are capable
RBW decreases. Oscillator frequency drift may cause the spur of differentiating between the amplitude and phase noise com-
frequency to drift in the measurement. Often, this has the effect ponents of an oscillator signal over a limited bandwidth [64].
of spreading the spur power across a range of frequencies that Two different measurement techniques are commonly used,
can extend beyond the bandwidth of the spectrum analyzer’s homodyne phase discrimination and heterodyne frequency
conceptual bandpass filter, thereby underestimating the spur discrimination [65]. The phase discrimination method is typ-
power. Moreover, because frequency drift varies randomly ically called narrowband-optimized mode, as it is optimized
over time, its effect on a spur may differ from its effect on for measuring the close-in phase noise of oscillators with very
the carrier, as they are measured at different points during the little frequency drift, such as crystal oscillators and PLL-based
sweep time. These effects can cause spur power measurement oscillators locked to crystal oscillators. The frequency discrim-
to be optimistic, often by several dB. inator method is often called wideband-optimized mode, and
The above discussion also explains why it is necessary to is better-suited to measure the phase noise of oscillators with
disable spectrum analyzer averaging when measuring spurs. relatively high low-frequency phase noise or frequency drift,
Spectrum analyzer averaging causes the instrument to average such as free-running voltage-controlled oscillators. Both of
the results of multiple sequentially captured measurements. these measurement methods are further improved by corre-
This mode is useful for increasing the precision of noise lation techniques, which essentially average out the uncorre-
measurements. Unfortunately, oscillator frequency drift causes lated noise between multiple identical measurement channels
the spur to appear at different frequencies across different inside the instrument [66]. The total added noise from these
measurement sweeps. When these results are averaged, the instruments can be less than 10 femtoseconds of integrated
resulting spur power is reduced as it is averaged with noise, jitter.
and just as explained above, the averaging may affect the spur The right side of Fig. 10 shows the phase noise plot of
power and carrier power differently, due to any randomness in the same PLL-based oscillator discussed in the previous sub-
the frequency drift. section, as measured by a Keysight E5052B signal source
Most spectrum analyzers implement the conceptual band- analyzer. For the reasons given in the previous section,
pass filtering operation described above by either downcon- the averaging techniques used by this instrument to improve
verting the input signal to a fixed intermediate frequency the noise measurement precision adversely affects its ability to
and passing the result through a fixed-frequency bandpass resolve spurs. For example, the spurs at 7.4, 14.7, and 29.5 kHz
filter, or digitizing the input signal and performing fast Fourier in the left-side power spectrum are also visible in the phase
transform (FFT) based spectrum estimation [17]. Either way, noise plot, but their powers are not directly readable as they
the accuracy of the center frequency of the conceptual band- are spread over a range of frequencies.
pass filter depends on the accuracy of the spectrum analyzer’s
local oscillator frequency, which, in turn, depends on the accu-
racy of the spectrum analyzer’s reference oscillator frequency. C. Time-Domain Methods
Most spectrum analyzers offer the option of using an exter- For serial communication applications, phase error is usu-
nal reference oscillator signal. When measuring PLL-based ally measured in the time domain with high-speed digitizing
oscillator phase error spurs, this feature makes it possible to oscilloscopes, as they can make measurements that would
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C. Interpretation and Comparison With Phase Noise needed to analyze the Rubidium oscillators in GPS satellites
Mobile devices such as cellular phones and GPS receivers that exhibit complex frequency drift behavior [91].
contain circuits called realtime clocks (RTC). An RTC contains The approach to selecting a type of variance is similar to
an internal oscillator tuned to a known nominal frequency. the choice of window type for power spectrum estimation. The
By counting the oscillator’s cycles, a sense of time is kept. different types emphasize (or obscure) different aspects of the
The frequency stability of the mobile device RTC oscillator is signal, and depending on the features of interest one may be
typically poor, so the RTC is periodically recalibrated using more appropriate than another. The references [90], [97], [98]
the base station time as described below. provide more details on many commonly-used types of
Every τ seconds, the base station transmits its time to the variance.
mobile device. The mobile device updates its internal time to
IX. C ONCLUSION
the received time, but also computes the error between the
RTC’s measurement of the τ -second interval and the actual Oscillators and the clock signals they generate are ubiqui-
interval as defined by the base station. The mobile device then tous in modern electronic systems. Due to their wide range of
uses this measured error to correct the RTC’s prediction of the applications, different disciplines have each developed their
subsequent τ -second interval. own metrics and methods by which to characterize oscillator
In this manner, the mobile device’s time error from the non-idealities, each uniquely suited to their particular appli-
base station time is reset to 0 every τ seconds, but its time cation. Wireless systems are predominantly concerned with
error grows as time elapses from the most recent reset up the oscillator’s phase error power spectrum. Digital clocked
to the next reset. In this scenario, the standard deviation circuits, and wireline communication systems are more fre-
of the mobile device’s time error immediately before each quently analyzed using time-domain jitter calculations. Metrol-
recalibration is closely approximated by τ σ y (τ ). While this ogy and physics applications frequently employ the Allan
idealized example ignores practical challenges faced by such variance. Although these metrics, and the instruments used
systems, e.g., temperature fluctuations between recalibrations, to measure them, appear very different, as explained in this
it illustrates how the Allen variance is a useful tool to tutorial they are all just different perspectives on oscillator
characterize the precision of time measurements based on the phase error.
performance of the underlying oscillator used to measure the
time interval. ACKNOWLEDGEMENTS
Using a σ -τ plot in the above example, if the chosen τ falls The authors wish to thank Walid Ali-Ahmad, Enrique
in the −1 sloped region, then τ σ y (τ ) is a constant with respect Alvarez-Fontecilla, Ajay Balankutty, Brian Buell, Matthew
to τ . If τ falls in the flat region, then τ σ y (τ ) grows linearly Felmlee, Raghavendra Haresamudram, Sassan Tabatabaei,
with τ , and if τ falls in the rising region, then τ σ y (τ ) grows Yiwu Tang and the anonymous reviewers for their many
at a much higher rate. From the σ -τ plot, it is also easy to excellent comments and suggestions which helped us improve
calculate the maximum allowable time between recalibrations this paper.
given a maximum time error standard deviation requirement.
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