= — Assignment -4 Explain the architecture of 8086 micxoprocesser - Main Featwts : lot is am enhanced version of 8085 ‘mitxoproressct, designed. by the Intd in 1076~ >t ip 16-bit micxoprocesse’t - operation Modes Of 8086 Miciso p20 cessor + Max Mode : Tb iS mnulliprecessoe System & one prxocesso' - b- Min Mode: Tb is single process “system Featuxes of 8086 : 29086 iS a Ho PIN IC ~ rts operating volts is 5 vols + TES operating forequency is SMHE- |. Total memory addxessing capacity address bud rneang nore than “img (external) + lb-bit date. bub ond 20 bit me Fe ee ae ees “th ble. bobo te le ed. _/ ARITHMETIC | LoGuc | oniT | Serre | — geenANae 2 | ee ELAR aes AYBIV- Bus Imtofoce Unit 2: EU- Execution Unit CS—> Code Segment Register $$ —> Stacle Segment Regis tex DS—> Dat» Seqenent Register ES —> Extwo sequent, Registor EP—> rrstruckion Pointer offset Register ¢ GP—> gtock Pointex SI —> Sowle ‘Index BP —> Bose pointe. or — Destination Tndex physical address = segment address #10 + offset BIU amd EV Gm werk simulloneoubly +0 incarease the Syste speed gus Tnterfoce Unit (97ul* Lotrstsuction queue Segment regesterd addness—S- Lypus lagic ciscuit * Responsible foc furfyentcg alk Pu ydated operations: Functions of IU: + Te Sends address oF memory ex to- wre fetdh instzuction from memory - preads | 2vites doto from mnemery [E10 Posts + Tt cue ond provides asddwess BAovecion + pe supports ingtucbon qb facility Tnsbuction @ueue: | speed. up Ge program execution +The GIO fetches 6 inoteuckions byte fron te menmey ord. store tn the | rstsuction qpene_—_ [to fetch the) met basbsuchion shen Guoent in stsuLKign Ensbsuction ig in execution L>the qHeuc oporto! on the — principle of FIFO: L>In case of jump and. coll ingbsuchions, the instyuction queue newly foomed by Bpecified by sump/call loading, insbsuchions frrorn nes addxerAe, Geqrnent Registers : She physiad address of $086 ig gd-bit wide fo access 12° o> 1m byte mmenery Yecabion - = + vagisd caress, 16 bt ims. sqmenb [JOUK-ES wide - kiBCK sean | SOCK seqmont [sou k- mene ee $5 ima Memay & divided Seqrent__[youn-05 watt capened of HKD. ee | wegment [uk ¢S voade Segment: 3 med fee cadressing the exeasable psogtare ingesuchong segment: Té & used to chore the dota used by ot Dota $ preogicarn « 3.Stock Segmaend + Tb femdley) mersry 40 etore dota amd addresses dusting execution - WExteo. Segment > Tz & on oddittonal dota. Segment used by the sting, - Innsteuctim Pointer * hold the. _ addressed ab the Th is a Ie bib register to hoax &nstuchion, to be execucked - lxecution Unit LEY): —reonbuol Cixcuibry yprithmebic Logic ‘Corcubt: > Flea, Register |vtremexal purpose Registerd : lee ord. Fndex RegisterusVv Functions of EU: instructions Tt teh the BIV from where to fetch oe deta + pe decodes amd executes rhe Conbrol Curcuiby directs amd Controls the instructions » intorng|| Operations: the decoder ‘transbted the Instauctions ino a Serie oF ackons +o be Performed . Aritrmetic Legic Umid: | Tt porferms ol onithmetic and kage opacationd - Axithmebic tho ref Legical AND, OR, NOT Flog Register * . Th tg a orbit weisber 4) Ht Oo. 4 87 6 5 Ys 2 id ju jv U | U jOF oe [ze [re [sr Jer] v Jar [u |er|u or Conditional Flogo C6 Flags) cory Fag (LF) P20 Flag (zr) — pusiliony Flag (AF) > sign Flag (6) Parity, Flag CPF) — overfp Flag (°F) 2 Gnbot Flap 3. Flagh] > Dap Flag (TFD — Inteorupt Flag (ZF) —> duction Flog (OF) + Conditonal flag> represents the Storted ob the laxithmeb'c wesults - © Conbrol Pog Control the operations of 6U- Pointerd and Index Registers + LSeqmort Hegistord 516 bit wide paphysical address of $08 Lo gb po-bit phyatcal add index register ore andoctated with Segment wegister (50, 6 —> 20 bit wide eas one @D more pointer OL GBPST, oF]Jiegtack pointer : Tb Conbaind the bb’ offset from the Stab | (5?) of the Stock — Seamenb - physical Adm@ess= 55 SP 20 bib addxess b.gane pointer: Ib is based on dota addressing node: (P+ 55] (eb Is. gouxce Tndex : To hold the offset of dato wed m te dota (st) Segment LSE ond 05} ly Destination Tmdex + Sbsirg instsuctions use EG omd OT 40 pit additess Loz & €5) (oD) Calculote +0 207 rener.al Purpose Registerd : Lothene one 8 Senerol purpose 2égi5 AL, BH, BL, CH tem : AH, cL, DH, DL —> & bib AX Register (accumulator) +To Stet opexandd fox ALU operations - BX Register ( Bade.) 1 store the Starting within the 05° | cx Register Counter) Th is wed tn loop tngtauction ; obe padieess ah the memory Ox Register (Dota) + To held Tio post addressed:2 Explain the pln diagrar of 8085 qicsopxocensor oma 7 igyows the oxchitecture Re 45 3 SRST OSES esr 5-5} } SM fu <> Moff | <> Adib a pore — (80%) means whenev' stopped rear on od Lorn $085 mivtoprocendee ipo addnessingy ard doko. meet gt aS, RST ES, tetbeocupt ocknodledgement mivsop) eons that oc we give 0” tole 3+} HOLD 8 a-}mvon ¢ s9-tcur (ont) > ° ast aerer we i 354 READY | a+ v0fih—> HP Mic Ro PROCESSOR qnteso processor - jo ends the device cormected 10 ‘sin (sedab Br Dato) these 2 pms OL Cownatenicotion INTR, ENTA ‘hee ore RST 5:5, rocosee il ep is said 4o be active low it storbed - ce give “Ute OFF puoessth - 19 pind axe AD\-ADZ both teamsfoc Pind.| Lsng-Aig totol 16 bits oddreess ond AD-Dz total 8 bits data txansfer Lined’ Ls 26!" pin Vag yneans ground coal od only oddxeés Lined « >21-28 pins thee cre ty xedponsidle fer the Stabub So, axe Steduus ‘partly pind - > we 6 a adive high Signal ALE 5 latch emanle which of address and data linen and > WR thd pin is ottive loo signas wesite operation - [> RO wis pin & aleo active lod signal to Bead: operatin. L>Rgavy Pin is wespmsible {et otter Completion of 2aCh tab it prrovideh 0 rendy signal +o, perfeim the next tak. I> RESET IN this pin is, active low pin - tte > cur (out) tnis gin iS wesponsible fee yeoek of deviced Connected PHOLessett - Ls HoLd pin is Besponsible fer how poe “ame the devices oxe worded - >HLOA pin gives Geknowledgenent 40, the processer - L>Vor mend supply, volkage - Ltn 8085 pm dagwom contain everything Ke ALL, registry Timing, & Contyol Umit ett:| Avchitecture of =Ro8S: ane (t REGUTE TWSTRUCTIONS LT bs | me : DecremenT ConTROL TIMMRING Sina Lott hab a 16 bit progrern coum ter (PC) Lyt hab a 16 bit Stack wwunbpointex ($2) >Six @-bié gendkal purpose wegistee auung in paiss + BG 06HE [spate bud &© a goup of 8 ines Oo-OF- Accumulate: Lore te an S-bit register used 4o perform evdthretic sbgical, yo ord load | Stoxe operablons Lop is connected to the intoenal data bud ‘and ALU puctrmesic Logic Unit caLu): the 8085 A hos Oo Simple & > ny the name Suggests, ike porferms antthmetic cond logical opexcctions Ke cddition , subbsaction , AN, oR, eke on 8 bib data- Lyte weds in (-osdination with the occumubater, bem pany weggist, 5 Flags and onithmebic amd logic clacuits- rempoxxany Register * gedit xégister, ishich held the — bemposory data. ob quithmetic on loglcd. opercctiond + bit ALD -|Flag Register : 03 0 8 % Bal 5 | Oy Ac Cory Coy)? Tf the sepuls stored tn am otcumulolite generates ja corey in tbs ral off thon ib % seb cthowise it’ % Regeb the cory flag alto Served ob @ , bo«Kou Hoa, fore 1/0 cy o) p 93 [gubtsachior t ' . 1 &: F5 sy tt toyors 45.0110 001 01 __ \oortr!oto —_— Parity (p): TP te no of 11'S even in laccuruiates theo ww Sek “othardise ibis webek fee tHe odd - the olp stored fm the Ausciliony Cory (ac): TF ony cay goed “Pom 340 Dy ie ofp thon it is Seb otherwise ib & sere : zeros (Di cthe © cedure Steed ia am cette, S Zao 1M lyin flip flop &s Seb othousise cere i. : flag is sé signs (5): HF OF ch the emule ts | Hen sign othexaaice ened : ee thab the numbec on the D7 bo 1 the number ws negative, Hf He nuanbor on, the, Dr & 01 the tumber ‘S positive - ' | General purpase Register > | ayhere axe 6 general purpose xegister in go8S niCso~ PEASE ie B/C10,E,H, L: Goch xegistee Can hold’ g-bit daka: thebe Lregistors cam uve in pois fo hold Wb- bit doko ond thee taxing Combinalion & Like B-¢, D-E omd wok: Stok Pornterr : Ib is alto oO hich ts alisays trasonenteb] decremented by > during Push and Pop operations - W-ble wegistoe thot wens LiKe o stack,Progam Counbor ! . It & a Ib-bit Kegistt Ud Jo store the memory addvens ogi location of the, next brobuchion 40 be execided rnieto- | dhe prograrn Whenewi an Ingteuction | bo thot the pJeog4arn Counter poinls ys (of the “nese ingtauchon thet | | Processor tncserments amd. being execubed fo dhe rnerony odd geing 10 be executed Addxess Bus | >The address bub is 0 group of 16 lines goreraly identhel ob Ag Ais othe addness | bus 1S unidivectonal Hey disecton fiom MPU 10 peripheral devices othe 085 MeL caith tts 16 address Lines & Copeble 4 eddnessing 9! = 65536 (64K) byt money locabons Data Bus: | —sthe dota bub is a group dixectional te, date flow mm pits foo Sh one These lined one bi- ple MPO 4 gxipholrol deviced - Jy the 8 ,datolines enables the. MPU to ramipulate 8 BIE dain Jranging fom 00 to FF (08> 256 nurnbers) the largest purber lthat con oppeax on qe dala bab rien (25510) [Tnstsuction Register find Decoder ! I->zt is on g-bit register |_seshen on inctsuction iS fetche we gtd in’ te Insbsuction segisber Hy Brstsuction decoder decodes the tfetmabin present in the tecuction seqister - Hiring And Conteh Umit > Lye provides trsig ord Gorbtal Signale Jo the micaepeest fo pertston eparationd + 4 from memory ord them i Lo the foloving O%& the Hendy ae eee pee eel Stgnols, ahichContsol extemal and — tntoenal Useutts - Control Signals: READY, DB, wR, ALE + Stotub Signabd: $0, $1, 10/4 13-omA Signold HOLD, HLOA U-RESET Sigrald + RESET IN) RESET OUT