International Journal of Power Electronics and Drive Systems (IJPEDS)

Vol. 12, No. 2, Jun 2021, pp. 902~912

ISSN: 2088-8694, DOI: 10.11591/ijpeds.v12.i2.pp902-912  902

Design and implementation of a single-phase five-level inverter

using a DC Source with voltage balancer on capacitor

Leonardus Heru Pratomo, Slamet Riyadi

Department of Electrical Engineering, Soegijapranata Catholic University, Indonesia

Article Info ABSTRACT

Article history: The global use of renewable energy resources has led to the design and
development of high performance, efficient, controllable, and cheap
Received Oct 27, 2020 multilevel inverters, which act as a solution to the numerous power
Revised Jan 15, 2021 deficiencies. However, in terms of control, these multilevel inverters are
Accepted Mar 1, 2021 often associated with DC sources and complexity. Therefore, this research
designed a single-phase five-level inverter using a DC source, with a novel
sinusoidal pulse-width-modulated (SPWM) control scheme. The system
Keywords: consists of a flying capacitor DC-DC converter and H-bridge inverter
(FCDCDC-HBI). A single absolute reference signal and the phase-shifted
DC-DC converter triangular carrier were used to generate SPWM to enhance the capacitor
Five-level inverter voltage balance. The designed inverter is capable of producing five levels of
Flying capacitor output voltage levels, namely Vi, Vi/2, 0, −Vi/2, and −Vi from a DC supply,
H-bridge inverter thereby reducing the overall cost and complexity of the SPWM system. This
Single-phase research also produced a detailed operation principle of the proposed system,
which was verified through simulation and implemented using a prototype.
Finally, hardware implementation results are presented to check the
performance of the inverter.
This is an open access article under the CC BY-SA license.

Corresponding Author:
Leonardus Heru Pratomo
Department of Electrical Engineering
Soegijapranata Catholic University
Jl. Pawiyatan Luhur IV/1 Bendan Dhuwur Semarang 50234, Indonesia
Email: [email protected]

1. INTRODUCTION
Over the years, various studies have been carried out to determine the possibility of a reduction total
harmonic distortion in power inverter that used in industrial application. The single-phase multilevel inverters
have rise in popularity for low-voltage on/off grid grid-tied inverters [1]-[3]. These inverters are expected to
operate with high efficiency, low output voltage/current total harmonic distortion, simple control, and better
performance during steady and transient operations. The multilevel inverter has several benefits over the two-
level type with better power quality, reduced stress on the load, and others. Nevertheless, the neutral diode
clamped of the multilevel inverter [4], [5] faces the inability to produce large numbers of active power
switches, DC sources, and inadequate power balancing input. Although the flying capacitor of the multilevel
inverter [6]-[8] has a significant DC power source, it is faced with voltage balancing problems and complex
control algorithms. One of the many solutions to overcome this problem is to use a shifted carrier signal and
combinational logic gate [9]-[11]. This study is also based on designing a single-phase cascaded H-bridge
converter for grid-connected PV applications [12], [13], with the cascaded topology in need of isolated DC
supplies and several power switches. Therefore, this research analyzes a single-phase symmetrical multilevel
inverter topology composed of two parts, namely the level (high-frequency switching) and polarity

Journal homepage: http://ijpeds.iaescore.com

Int J Pow Elec & Dri Syst ISSN: 2088-8694  903

generators (low- frequency of 50Hz) [14]. Some asymmetrical topologies of the multilevel inverters used to
obtain several output steps without increasing the switch count are shown in [15]-[18], with the DC voltage
sources asymmetrically represented in geometric progression.
This research developed and implemented a five-level inverter topology that uses five active
switches and one passive switch [19], [20]. Previous studies utilized four active switches [21] and needed two
DC sources. However, one of the drawbacks of this type of inverter is the number of power switching
devices, and isolated DC power sources, increasing the cost and circuit complexity. Therefore, a hybrid
multilevel inverter implemented using an H-bridge inverter, and three-level cells were developed [22]. This
device needs eight active power switches to create a five-level inverter topology, which was developed from
the three-level H-bridge using a single DC source [23]. Furthermore, the developed inverter needs seven
active power switches to generate a five-level output voltage. A single active power switch carried out the
balancing capacitor with a more complicated control configuration. A five-level inverter is achieved by
connecting the H-bridge with a two DC power source, using a multilevel inverter coupled in series [24]. A
five-level inverter topology was also designed, which used a single DC source with eighty-six active switches
[25]. This inverter used the space vector polygon formed to control the five-level inverter. Therefore, the risk
of unbalanced capacitor voltage exists when the inverter is not properly modulated. Furthermore, previous
studies developed a multilevel inverter which uses a DC source without split capacitors. This is likely to be
the most wanted topology, however, this inverter has not been properly, and the dc component on the
inductor current is dangerous for full use of magnetic core [26], [27]. The five-level inverter consisting of
five active power switches and two capacitors was developed by [28], however it needed more control for
balancing the capacitor. The five-level inverter (seven active switches) used phase-shifted carrier to control
and balance the bulk capacitor, it uses six active power switches without any sensors for operated that
inverter [29]. Furthermore, the PV-grid application used a multilevel inverter associated with a DC source is
suitable for this application [1], [3], [30].
This research proposed a single-phase five-level inverter using a DC source with a simple voltage
balancer on a capacitor to make a better level. It also depends on the three levels generator of a Flying
Capacitor DC-DC Converter (two diodes, two active power switches, and one capacitor) and H-bridge
Inverter (FCDCDC-HBI) into a new single-phase five-level inverter using a single DC source and a novel
sinusoidal pulse width modulation (SPWM) strategy. An operation mode is analyzed to obtain a SPWM
pattern that is able to balance the capacitor voltage using a phase-shifted carrier signal of 1800, which
automatically enables the equilibrium voltage on the flying capacitor. The FCDCDC used to determine the
size of the capacitor is carried out by storing quality valued energy in the capacitor and inductor. This
condition occurs when charging and discharging the charge in the capacitor, therefore, it eliminates the need
for sensors and a complex control algorithm system to balance the voltage on the capacitor. The proposed
five-level inverter and its controller's performance was validated using Power Simulator software and
prototyping the laboratory experiments.

2. RESEARCH METHOD
This research was carried out using a hybrid multilevel topology, divided into two parts. The Flying
Capacitor DC-DC Converter is the fist part, with high-frequency switches used to generate three levels.
Meanwhile, the H-Bridge Inverter is the second part, which operates at a low-frequency of 50Hz, as shown in
Figure 1.

Low switching part

Polarity generation
High switching part
Level generation
S3 S4
S1 S2

L Vo
Vi
Vi / 2 R
S6 S5
D1 D2

Flying Capacitor DC-DC Converter H - Brige Inverter

Figure 1. Proposed FCDCDC-HBI topology

Design and implementation of a single-phase five-level inverter … (Leonardus Heru Pratomo)
904  ISSN: 2088-8694

The FCDCDC-HBI inverter always has two operating conditions, namely positive and negative
values, which comprise a five-level inverter working principle. Figure 2 is a positive operating condition,
mode of operation 1 consists of all power switches (S1 and S2) on the FCDCDC and HBI topology with S3
and S5 switched “on,” as shown in Figure 2 (a). Mode of operation 2 comprises of a power switch (S1 or S2)
on the FCDCDC and HBI topology with S3 and S5 switched “on,” as shown in Figure 2 (b) and Figure 2 (c).
The capacitor charges and discharges directly, as shown in Figure 2 (b) and Figure 2 (c), respectively. This
operation mode balances the voltage on the capacitor. Mode of operation 3 comprises of no power switches
(S1 and S2) on the FCDCDC and HBI with S3 and S5 switched “on,” as shown in Figure 2 (d).

S3 S4 S3 S4
S1 S2 S1 S2

L Vo L Vo
Vi Vi
Vi / 2 R Vi / 2 R
S6 S5 S6 S5
D1 D2 D1 D2

(a) (b)

S3 S4 S3 S4
S1 S2 S1 S2

L Vo L Vo
Vi Vi
Vi / 2 R Vi / 2 R
S6 S5 S6 S5
D1 D2 D1 D2

(c) (d)

Figure 2. Mode of operation on positive value, (a) 1, (b) 2a, (c) 2b, (c), (d) 3

toff
toff
S1 S1
ton t on
Vd Ts t Vd Ts t
Vi Vi
t2 t1
Vi /2 Vi /2
t1 t t
t2
0 0
iL iL

Tout Ts t Tout Ts t
(a) (b)
Figure 3. Switching operation, (a) on interval 0  m  1 / 2 , (b) on interval 1 / 2  m  1

Figure 3 (a) shows the operation mode analysis on 3 and 2 using an interval 0  m  1 / 2 in which
the two-leg H-bridge inverter Vd fluctuates the voltage Vi/2 and 0 and causes the inductor current to rise. The
equations derived under these conditions are as (1).

vd = vL + Vo
Vi di
= L L + Vo
2 dt
diL V
L = i − Vo
dt 2

Int J Pow Elec & Dri Syst, Vol. 12, No. 2, June 2021 : 902 – 912
Int J Pow Elec & Dri Syst ISSN: 2088-8694  905

V  V 
LiL =  i − Vo  t =  i − Vo  t1 (1)
 2   2 

When the voltages on the two-leg H-bridge, the inverters have zero values, thereby leading to a decrease in
inductor current. The equations that can be derived under these conditions are as (2).

vL = Vo − vd
di
L L = Vo − 0
dt
LiL = Vot = Vot2 (2)

Substituting (1) into (2) formulates (3).

V t V 2t
Vo = i 1 = i on = m Vi (3)
2 Tout 2 Ts

Figure 3 (b) shows the analysis of operation mode on 1 and 2 using an interval 1 / 2  m  1 , thereby causing
the two-leg H-bridge inverter Vd to fluctuate the Vi and Vi/2 voltages. This increases the inductor current and
the equations derived are as (4).

vd = vL + Vo
di
Vi = L L + Vo
dt
diL
L = Vi − Vo
dt
LiL = (Vi − Vo ) t = (Vi − Vo )t1
(4)

The voltages on two-leg H-bridge inverters are Vi/2 and leads to a decrease in the inductor current. The
derived under these conditions are as (5).

diL V
L = Vo − i
dt 2
 V   V 
LiL = Vo − i t = Vo − i t2 (5)
 2   2 

Substituting (4) into (5) formulates (6).

V 2t
Vo = i on = m Vi (6)
2 Ts

Operation mode 2 need to be applied to keep the voltage capacitor constant, as shown in Figure 2 (b)
and Figure 2 (c). The decrease in voltage across the DC capacitor indicates the power given to the load, as
shown in Figure 2 (c). The increase in capacitor voltage at DC indicates power absorption from the power
source (E), as shown in Figure 2 (b). Therefore, to ensure the increase and decrease in power, the capacitor
voltage needs to be kept constant, as shown in Figure 4.

Design and implementation of a single-phase five-level inverter … (Leonardus Heru Pratomo)

906  ISSN: 2088-8694

t1 t3
VCapacitor
W2
W1
t2

Figure 4. The charging and discharging voltage across capacitor

The capacitor transmitted power to load at an interval of 𝑡1 − 𝑡2 , thereby decreasing the capacitor
voltage. The amount of energy is expressed (7).
t2
W1 = P (t ) dt
 (7)
t1

This interval produces a voltage across the capacitor known as 𝑉𝑐𝑎𝑝1 . The capacitor absorbed power
from the source (E) at an interval of 𝑡2 − 𝑡3 , thereby increasing the capacitor voltage. The amount of energy
is expressed by (8).
t3
W2 = P(t )dt
 (8)
t2

This interval would produce a voltage across the capacitor known as Vca p 2 . The balancing power used
the mode of operation 2, therefore the capacitor's energy is derived as (9).
W = W1 = W2 (9)

The capacitor voltage is obtained using the (10).

Vca p1  Vca p 2 ,
Vca p 3  Vca p 2 ,
Vca p1 = Vca p 3 . (10)

The delivery energy process causes voltage fluctuations in the capacitor as (11).

V = Vcap 2 − Vcap1 (11)

The capacitor was capable of storing energy with an increase and decrease in voltage as obtained using (12).

W = C ( V )
1 2

2
C (Vcap 2 − Vcap1 )
1
W=
2
(12)
2

A capacitor voltage in a balanced condition is needed for a FCDCDC-HBI inverter, with the
equilibrium energy determined by the charging and discharging of the power active switches based on the
mode of operation 2. This has the ability to store energy in the capacitor that equals those in the inductor. The
value of the capacitor can be determined as (13).

WC = WL
,
LI2
C= (13)
V 2

Int J Pow Elec & Dri Syst, Vol. 12, No. 2, June 2021 : 902 – 912
Int J Pow Elec & Dri Syst ISSN: 2088-8694  907

The (3) and (6) show the relationship between the output and input voltage of the conventional and
multilevel inverter (FCDCDC-HBI). The five-level waveform is based on the FCDCDC-HBI and the
proposed scheme of the SPWM control, as shown in Figure 5 and Figure 6.

V_tri 1 V_tri 2 V_Sin

Vm

0
SPWM_1 (S1) t
1
0
SPWM_2 (S2) t
1
0
1
Zero Crossing Detector_ + (S3, S5)
0
t
1
Zero Crossing Detector_ - (S4, S6)
0
Vi t
Vi / 2 Vi / 2

0 0 t
- Vi / 2 - Vi / 2

- Vi

Figure 5. The waveform of the five-level based on FCDCDC-HBI

Comparator
Abs
Driver S1
Signal
Genarator
Driver S2
Triangle Signal
Generator -1

Zero Crossing Detector

Driver S3
ZCD_+
Driver S5
Driver S4
ZCD_-
Driver S6

Figure 6. The proposed scheme of a SPWM control

3. RESULTS AND DISCUSSION

The proposed FCDCDC-HBI was verified using the Power Simulator Software and implemented on a
prototype scale. Table 1 shows the parameters used as well as the proposed control scheme implemented
using an Arduino Mega 2560 microcontroller. Furthermore, MOSFET IRFP 460 and MUR 1560 were used
as the active and passive power switches of the FCDCDC-HBI. Meanwhile, B1212S-1Ws and TLP 350s
were used as an isolated DC-DC converter and active power switch drivers. The prototype for experimental
works is shown in Figure 7.

Table 1. Parameters for the validation works

Parameters Value
Input Voltage 100 Volt DC
Resistive Load 25 Ohm
Capacitor 470 uF/450V
Inductor Filter 2.5 mH
Operated frequency 5 KHz

Figure 7. The prototype for experimental works

Design and implementation of a single-phase five-level inverter … (Leonardus Heru Pratomo)

908  ISSN: 2088-8694

The initial stage of verification is carried out by computational simulation. Figure 8 (a) shows the
simulation result of an absolute SPWM gating signal used to power switch S1 and S2. An absolute SPWM
gating signal shifts 1800 between SPWM on S1 and S2. Figure 8 (b) shows a pulse shaper polarity inverted
(zero-crossing detector) at 50Hz, which is used to switch S3-S5 (positive cycle) and S4-S6 (negative cycle).
Furthermore, the power switch S1 and S2 used a high frequency of 5KHz, while those on S3-S5 and S4-S6
were low. These conditions (SPWM and zero-crossing detector waveform) are similar to the diagram shown
in Figure 4.

(a) (b)

Figure 8. Simulated waveforms, (a) SPWM signal: S1 and S2, (b) zero-crossing detector signal: S5 - S8 and
S6 – S7

After ensuring that the S1 - S6 switching pattern is properly running, the next step is to verify the
proposed scheme of a SPWM control, which is implemented through the Arduino Mega 2560
microcontroller. Figure 9 (a) shows the implementation result of an absolute SPWM used to power switch S1
and S2 with a high switching frequency of 5KHz. Figure 9 (b) shows the polarity inverter with zero-crossing
detectors of 50Hz used to switch S3-S5 and S4-S6. Therefore, SPWM (Figure 8 (a) and Figure 9 (a)) and
zero-crossing detectors (Figure 8 (b) and Figure 9 (b)) resemble each other.

(a) (b)

Figure 9. Implemented waveforms, (a) SPWM signal: S1 (yellow) and S2 (blue), (b) zero-crossing detector
signal on S5 - S8 (yellow) and S6 – S7 (blue)

The proposed FCDCDC-HBI topology shown in Figure 1 is used to simulate a SPWM control
scheme, as indicated in Figure 5. Furthermore, Figure 10 (a) shows the simulation result of the five-level
inverter voltage output waveform (switching operation on the interval 0  m  1 ). The magnitude voltage
levels were at +100V, +50V, 0V, −50V, and −100V. Meanwhile, the magnitude of the five-level inverter was
related to the switching operation in (3) and (6), thereby minimizing the voltage harmonics by enlarging the
filter inductor or switching frequency as shown in Figure 10 (b). Figure 11 shows the simulation result of the

Int J Pow Elec & Dri Syst, Vol. 12, No. 2, June 2021 : 902 – 912
Int J Pow Elec & Dri Syst ISSN: 2088-8694  909

three-level inverter voltage output waveform (switching operation on the interval 0  m  1 / 2 ). The
magnitude voltage levels were at +50V, 0V, and −50V, respectively, which were also used to obtain the
induced filter's fundamental value. The magnitude of the three-level inverter was related to the switching
operation in (3).

(a) (b)

Figure 10. Simulated waveform, (a) inverter output voltage on the interval 0  m  1 , (b) the fundamental
voltage and current output of the inverter

Figure 11. Simulated waveforms: inverter output voltage on the interval 0  m  1 / 2

Figure 3 shows the analyses of the switching frequency operation on interval 0  m  1/ 2 and
1 / 2  m  1 . It indicates that in one switching period there are two patterns, namely S1 and S2. This method
makes double switching frequency (5KHz become 10KHZ), with the output voltage waveforms in
Figure 10 (b) and Figure 11 extracted using a Fast Fourier Transform (FFT) as shown in Figure 12. The
frequency spectrum becomes 10KHZ at a switching frequency of 5KHZ. The advantage associated with this
method is in terms of the size of the inductor filter used.

(a) (b)

Figure 12. The frequency spectrum, (a) voltage output waveform on the interval 0  m  1 , (b) voltage output
waveform on the interval 0  m  1 / 2
Design and implementation of a single-phase five-level inverter … (Leonardus Heru Pratomo)
910  ISSN: 2088-8694

The final stage of this verification is to conduct prototype tests of the proposed single-phase five-
level inverter. In these tests, the switching operation on the interval 0  m  1 is performed to get five levels.
Figure 13 (a) shows that the FCDCDC-HBI inverter is capable of producing five levels of output voltage
levels, namely 100V, 50V, 0V, −50V, and −100V in a waveform. It also shows that the inverter output
voltage of Figures 10 (a) and Figure 13 (a) resemble each other. The five-level inverter voltage output
waveform has a good balancer using a phase-shifted carrier signal 1800 as recommended in the proposed
scheme of a SPWM control (Figure 5). Finally, Figure 13 (b) shows the implementation result of five-level
inverter voltage and current output waveform after filtering using a 2.5mH inductor.

(a) (b)

Figure 13. Implemented waveform, (a) inverter output voltage on the interval 0  m  1 , (b) output current
(blue) and voltage (yellow)

The performance of the FCDCDC-HBI inverter using simulation and implementation resemble each
other, as shown in Figure 13. Furthermore, it is important to balance the voltage of a flying capacitor DC-DC
converter in controlling the multilevel inverter due to its ability to control switches S1 and S2 easily using a
phase-shifted triangular carrier (1800) without any combinational logic gate. The zero-crossing detector of the
H-bridge inverter has the ability to control switches S3-S5 (positive cycle) and S4-S6 (negative cycle) at
50Hz.

4. CONCLUSION
The multilevel inverter topology presented in this research depends on the three levels DC-DC
converter (FCDCDC) and polarity generators (HBI). The research showed that a proposed five-level inverter
based on FCDCDC-HBI topology has more advantages in terms of equilibrium voltage on the capacitor,
simple control, and cost-effectiveness. Furthermore, the new system is ideal for sustainable power based on a
single-stage delivery technique. An absolute SPWM for the FCDCDC requires no voltage balancer in the
capacitor and combinational logic gate. The proposed topology effectively operates as a five-level inverter
with a novel modulation strategy.

ACKNOWLEDGEMENTS
The authors gratefully acknowledge the Ministry of Research and Technology of the Republic of
Indonesia under the scheme PDUPT 2021, Number: 010/L6/AK/SP2H.1/PENELITIAN/2019.

REFERENCES
[1] Nasrudin A. Rahim, Krismadinata Chaniago and Jeyraj Selvaraj, “Single-phase seven-level grid-connected inverter
for photovoltaic system,” IEEE Trans. Ind. Electron, vol. 58, no. 6, pp. 2435-2443, June 2011.
[2] L. Heru Pratomo, F. Danang Wijaya and Eka Firmansyah, “Impedance matching method in two-stage converters
for single phase PV-grid system,” International Journal of Electrical and Computer Engineering (IJECE), vol. 5,
no. 4, pp. 626-635, Aug 2015, DOI: 10.11591/ijece.v5i4.pp626-635.
[3] Jia-Min Shen, Hurng-Liahng Jou, Jinn-Chang Wu and Kuen-Der Wu, “Five-level inverter for renewable power
generation system,” IEEE Transactions on Energy Conversion, vol. 28, no. 2, pp. 257-266, Jun 2013,
DOI: 10.1109/TEC.2013.2252352.

Int J Pow Elec & Dri Syst, Vol. 12, No. 2, June 2021 : 902 – 912
Int J Pow Elec & Dri Syst ISSN: 2088-8694  911

[4] M. M. Renge and H. M. Suryawanshi, “Five-level diode clamped inverter to eliminate common mode voltage and
reduce dv/dt in medium voltage rating induction motor drives,” IEEE Trans. Power Electron, vol. 23, no.4,
pp. 1598-1160, Jul 2008, DOI: 10.1109/TPEL.2008.925423.
[5] Engin Ozdemir, Sule Ozdemir and Leon M. Tolbert “Fundamental frequency modulated six-level diode-clamped
multilevel inverter for three-phase stand-alone photovoltaic system,” IEEE Trans. Ind. Electron, vol 56, no. 11,
pp. 4407-4415, Nov 2009, DOI: 10.1109/TIE.2008.928096.
[6] Robert Stala, Stanislaw Pirog, Marcin Baszynski, Andrzej Mondzik, Adam Penczek, Jaroslaw Czekonski, et al.,
“Results of investigation of multicell converters with balancing circuit—Part I,” IEEE Trans. Ind. Electron, vol.
56, no. 7, pp. 2610-2619, Jul 2009, DOI: 10.1109/TIE.2009.2021681.
[7] Robert Stala, Stanislaw Pirog, Marcin Baszynski, Andrzej Mondzik, Adam Penczek, Jaroslaw Czekonski, et al.,
“Results of investigation of multicell converters with balancing circuit—Part II,” IEEE Trans. Ind. Electron, vol.
56, no. 7, pp. 2620-2628, Jul 2009, DOI: 10.1109/TIE.2009.2022562.
[8] Vahid Dargahi, Arash Khoshkbar Sadigh, Mostafa Abarzadeh, Mohammad Reza Alizadeh Pahlavani and Abbas
Shoulaie, “Flying capacitors reduction in an improved double flying capacitor multicell converter controlled by a
modified modulation method,” IEEE Trans. On Power Electronic, vol. 27, no. 9, pp. 3875-3887, Sept 2012,
DOI: 10.1109/TPEL.2012.2188647.
[9] Anshuman Shukla, Arindam Ghosh and Avinash Joshi, “Natural balancing of flying capacitor voltages in multicell
inverter under PD carrier-based PWM,” IEEE Transactions on Power Electronics, vol. 26, no.6, pp. 1682-1693,
Jun 2010, DOI: 10.1109/TPEL.2010.2089807.
[10] Amin Ashraf Gandomi, Kazem Varesi and Seyed Hossein Hosseini, “Control strategy applied on double flying
capacitor multi-cell inverter for increasing number of generated voltage levels,” IET Power Electronics, vol. 8,
no. 6, pp. 887-897, June 2015, DOI: 10.1049/iet-pel.2014.0475.
[11] P. Lezana and R. Aceitón, “Hybrid multicell converter: topology and modulation,” IEEE Transactions on
Industrial Electronics, vol. 58, no. 9, pp. 3938-3945, Sept 2011, DOI: 10.1109/TIE.2010.2102316.
[12] Elena Villanueva, Pablo Correa, JosÉ Rodriguez and Mario Pacas, “Control of a single phase cascaded H-bridge
multilevel inverter for grid-connected photovoltaic systems,” IEEE Trans. Ind. Electron, vol. 56, no. 11,
pp. 4399-4406, Nov 2009, DOI: 10.1109/FTIE.2009.2029579.
[13] Carlo Cecati, Fabrizio Ciancetta and Pierluigi Siano, “A multilevel inverter for photovoltaic systems with fuzzy
logic control,” IEEE Trans. Ind. Electron, vol. 57, no. 12, pp. 4115-4125, Dec 2010, DOI:
10.1109/TIE.2010.2044119.
[14] E. Najafi, et al., “Design and implementation of a new multilevel inverter topology,” IEEE Trans. Ind. Electron,
vol. 59, no. 11, pp. 4148-4154, Nov 2012.
[15] E. Babaei and M. S. Moeinian, “Asymmetric cascaded multilevel inverter with charge balance control of a low
resolution symmetric subsystem,” in Energy Conversion Management, vol. 51, no. 11, pp. 2272-2278, 2010.
[16] Ebrahim Babaei, Mohammad Farhadi Kangarlu and Mohammad Ali Hosseinzadeh, “Asymmetrical multilevel
converter topology with reduced number of components,” IET Power Electronics, vol. 6, no. 6, pp. 1188-1196,
Nov 2013, DOI: 10.1049/iet-pel.2012.0497.
[17] C. Dhanamjayulu and S. Meikandasivam, “Implementation and comparison of symmetric and asymmetric
multilevel inverters for dynamic loads,” IEEE Access, vol. 6, pp, 738-746, Dec 2017, DOI:
10.1109/ACCESS.2017.2775203.
[18] S. Y. Darmian and S. M Barakati, “A new asymmetric multilevel inverter with reduced number of components,”
IEEE Journal of Emerging and Selected Topics in Power Electronics, Vol. 8, no. 4, pp. 4333-4342, 2019,
DOI: 10.1109/JESTPE.2019.2945757.
[19] L. H. Pratomo, “One leg control strategy in single-phase five-level inverter,” The 2019 International Symposium on
Electrical and Electronics Engineering, 2019.
[20] Suroso, Daru Tri Nugroho, Abdullah Nur Azis and Toshihiko Noguchi, “Simplified five-level voltage source
inverter with level-phase shifted,” Indonesian Journal of Electrical Engineering and Computer Science (IJEECS),
vol. 13, no. pp. 461-468, Feb 2019, DOI: 10.11591/ijeecs.v13.i2.pp461-468.
[21] L. H. Pratomo, “A new topology of a single-phase five-level inverter, “ Indonesian Journal of Electrical
Engineering and Informatics (IJEEI), vol. 8, no. 3, pp. 447-456, Sept 2020, DOI: 10.11591/ijeei.v8i3.1766.
[22] Domingo Ruiz-Caballero, René Sanhueza, Héctor Vergara, Miguel Lopez, Marcelo Lobo Heldwein and
Samir Ahmad Mussa, “Cascaded symmetrical hybrid multilevel DC-AC converter”, in Proc. of ECCE,
pp. 4012-4019, 2010, DOI: 10.1109/ECCE.2010.5617805.
[23] Suroso, Abdullah Nur Aziz and Toshihiko Noguchi, “Five-level PWM inverter with a single DC power source for
DC-AC power conversion,” International Journal of Power Electronics and Drive System (IJPEDS), vol. 8, no. 3,
pp. 1230-1237, Sept 2017, DOI: 10.11591/ijpeds.v8.i3.pp1212-1219.
[24] R. S. Alishah, and S. H. Hosseini, “A new multilevel inverter structure for high-power applications using
multicarrier PWM switching strategy”, International Journal of Power Electronics and Drive System (IJPEDS),
vol. 6, no. 2,
pp. 318-325, June 2015, DOI: 10.11591/ijpeds.v6.i2.pp318-325.
[25] P. Roshankumar, P. P. Rajeevan, K. Mathew, K. Gopakumar, Jose I. Leon and Leopoldo G. Franquelo, “A five-
level inverter topology with single-DC supply by cascading a flying capacitor inverter and an H-bridge,” IEEE
Trans on Power Electronics, vol. 27, no. 8, pp. 3505-3512, Agust 2012, DOI: 10.1109/TPEL.2012.2185714.
[26] J. Salmon, J. Ewanchuk and A. Knight, “PWM inverters using splitwound coupled inductors,” 2008 IEEE Industry
Applications Society Annual Meeting, 2008, DOI: 10.1109/08IAS.2008.299.

Design and implementation of a single-phase five-level inverter … (Leonardus Heru Pratomo)

912  ISSN: 2088-8694

[27] C. Chapelsky, J. Salmon and A. M. Knight, “Design of the magnetic components for high-performance multilevel
half-bridge inverter legs,” IEEE Trans. Magn., vol. 45, no. 10, pp. 4785-4788, Oct 2009,
DOI: 10.1109/TMAG.2009.2023229.
[28] Jinn-Chang Wu, Mao-Jhang He and Hurng-Liahng Jou, “New five-level inverter-based grid-connected power
conversion interface,” IET Power Electron, vol. 6, no. 7, pp. 1239-1247, Aug 2013, DOI: 10.1049/iet-
pel.2012.0616.
[29] Leonardus Heru Pratomo, F. Danang Wijaya and Eka Firmansyah, “A simple strategy of controlling a balanced
voltage capacitor in single phase five-level inverter,” International Journal of Power Electronics and Drive
Systems (IJPEDS), vol. 6, no. 1, pp. 160-167, March 2015, DOI: 10.11591/ijpeds.v6.i1.pp160-167.
[30] Jinn-Chang Wu, Mao-Jhang He and Hurng-Liahng Jou, “New five-level inverter-based grid-connected power
conversion interface,” IET Power Electron, vol. 6, no. 7, pp. 1239-1247, 2013, DOI: 10.1049/iet-pel.2012.0616.

BIOGRAPHIES OF AUTHORS

Leonardus Heru Pratomo was born in Ambarawa-Indonesia, in 1976. He received the B.

Eng degree from Catholic University, Semarang-Indonesia in 1994 and M. Eng degree from
Bandung Institute of Technology, Bandung-Indonesia in 2004. In 2016, he received the Ph.
D degree in Electrical Engineering from Gadjah Mada University, Jogjakarta-Indonesia.
Currently, he is a Lecturer and Researcher at the Electrical Engineering Department at
Soegijapranata Catholic University, Semarang, Indonesia since 2000. Now. His research
interest is focused on electric drives, multilevel inverter topology, grid-tie inverter and active
power filtering. Some of his researches were supported by, The Ministry of Research and
Technology-Indonesia, The Directorate Generale of Higher Education - Ministry of National
Education-Indonesia, etc

Slamet Riyadi was born in Semarang-Indonesia, in 1967. He received B.S. degree from
Diponegoro University, Semarang in 1991 and M. Eng degree from Bandung Institute of
Technology, Bandung-Indonesia in 1997. In 2006, he received Ph. D degree in Electrical
Engineering from Bandung Institute of Technology with Partial Research done in
ENSEEIHT-INPT Toulouse, France. Currently, he is a Profesor in the Departement of
Electrical Engineering, Soegijapranata Catholic University, Semarang-Indonesia as a
lecturer and researcher. His current research is focused on power factor correction
techniques, active power filtering, PV-Grid Systems and electric motor drives. Some of his
researches were supported by, ASEM duo-France, The Ministry of Research and
Technology-Indonesia, The Directorate Generale of Higher Education-Ministry of National
Education-Indonesia, etc. He is also an IEEE member.

Int J Pow Elec & Dri Syst, Vol. 12, No. 2, June 2021 : 902 – 912