IEEE TRANSACTIONS ON COMPUTERS, VOL. c-21, NO.

11, NOVEMBER 1972 1183

[16] W. Mayeda and C. V. Ramamoorthy, "Distinguishability cri- digital circuits," IEEE Trans. Comput., vol. C-17, pp. 352-366,
teria in oriented graphs and their application to computer diag- Apr. 1968.
nosis-I," IEEE Trans. Circuit Theory, vol. CT-16, pp. 448-454, [20] Y. Koga, C. Chin, and K. Naemura, "A method of test genera-
Nov. 1969. tion for fault location in combinational logic," in 1970 Fall Joint
[17] S. R. Petrick, "A direct determination of the irredundant forms Comput. Conf., AFIPS Conf. Proc., vol. 37. Montvale, N. J.:
of a Boolean function from the set of prime implicants," U. S. AFIPS Press, 1970, pp. 69-78.
Air Force Cambridge Res. Cen., Bedford, Mass., Tech. Rep. [21] C. V. Ramamoorthy and L. C. Chang, "System segmentation
56-110, Apr. 1956. for the parallel diagnosis of computeis," IEEE Trans. Comput.,
[18] H. Y. Chang, "A distinguishability criterion for selecting effi- vol. C-20, pp. 261-270, Mar. 1971.
cient diagnostic tests," in 1968 Spring Joint Comput. Conf., [22] J. D. Russell and C. R. Kime, "Structural factors in the fault
AFIPS Conf. Proc., vol. 32. Washington, D. C.: Thompson, diagnosis of combinational networks," IEEE Trans. Comput.
1968, pp. 529-534. (Special Issue on Fault-Tolerant Computing), vol. C-20, pp.
[19] W. H. Kaultz, "Fault testing and diagnosis in combinational 1276-1285, Nov. 1971.

Easily Testable Realizations ror Logic Functions

SUDHAKAR M. REDDY

Abstract-Desirable properties of "easily testable networks" are puts. In the dynamic redundancy approach, the digital
given. A realization for arbitrary logic function, using AND and system is tested frequently to detect and locate faults
EXCLUSIVE-OR gates, based on Reed-Muller canonic expansion is
given that has many of these desirable properties. If only permanent so that the faults can be rectified by replacing or re-
stuck-at-O (s-a-O) or stuck-at-i (s-a-i) faults occur in a single AND pairing the faulty units. It is then apparent that ele-
gate or only a single EXCLUSIVE-OR gate is faulty, the following re- gant solutions to the design of logic circuits that have
sults are derived on fault detecting test sets for the proposed net- simple testing properties will help in the application of
works: 1) only (n/4) tests, independent of the function being real- dynamic redundancy.
ized, are required if the primary inputs are fault-free; 2) only 2n. The problems of designing logic circuits are normally
additional inputs (which depend on the function realized) are re-
quired if the primary inputs can be faulty, where n, is the number of solved under the following specifications: 1) devices to
variables appearing in even number of product terms in the Reed- be used in the network (e.g., AND, OR gates); 2) con-
Muller canonical expansion of the function; and 3) the additional 2ne straints on network structure or topology (e.g., two-
inputs are not required if the network is provided with an observable level tree networks); 3) class of logic functions to be
point at the output of an extra AND gate. realized; and 4) design criteria (e.g., minimum number
It is further shown that the networks to generate the test sets and
to interpret the results of testing are simple and easy to design. of gate inputs).
Classically the solutions to design problems lhave
Index Terms-Easily testable networks, fault detection, Reed- been obtained withl the criteria to minimize the hard-
Muller canonic expressions, single faults, stuck-at-faults. ware complexity. The testing problem is considered
INTRODUCTION
only after the design of the network has been com-
pleted. We propose to include testing aspects into the
I.

ITH THE ever increasing use of digital com- design specifications. In specifying the devices and
puters in all aspects of social, economic, and in- structure the main considerations in the classical ap-
dustrial problems of the society, it is increas- proach have been technology and mathematical tract-
ingly evident that the computers must perform more ability of the solutions. In the approach being proposed
and more reliably. The reliability of a digital system (that is to incorporate testing aspects), we will have to
can be improved by the introduction of redundancy. additionally consider the "testability" of the devices
Redundancy can be introduced in two different ways; and/or the network structure or topology, since the
namely: 1) static redundancy; and 2) dynamic re- test sets for a network depend on the network topology
dundancy. In the static redundancy approach, net- and the devices used. Because of this in the design of
works are built to be fault tolerant such that even in what we call "easily testable networks," we will give
the presence of faults, the networks give correct out- the design criterion first and then attempt to identify
the devices and topology to satisfy the chosen design
Manuscript received December 3, 1971; revised June 5, 1972. criterion.
This work was supported in part by NSF Grant GK-10025 and in
part by the Office of Naval Research under Grant N0001468A-0500.
Optimal solutions with a given set of specifications
Parts of this paper were presented at the International Symposium will naturally be pursued in a design algorithm. As in
on Fault-Tolerant Computing, Newton, Mass., June 19-21, 1972.
The author is with the Department of Electrical Engineering,
the case of the classical approach, optimal solutions
University of Iowa, Iowa City, Iowa 52240. might be extremely difficult to obtain uinless the speci-

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 1184 IEEE TRANSACTIONS ON COMPUTERS, NOVEMBER 1972

fications are suitably restricted. For example, with total Next we give a qualitative formulation of the ap-
gate input count as the design criterion, optimal solu- proach to incorporate testing into design algorithms. We
tions (that are not exhaustive or semiexhaustive) are will list some desirable properties of what will be called
available only in very few cases. The classical example easily testable networks that would be realized by such
is when we restrict the network structure to be a two- design algorithms.
level AND-OR or OR-AND tree. When testing aspects are
to be included some of the obvious design criteria, for Desirable Properties of Easily Testable Networks
example, number of test inputs to detect faults, might 1) Small test sets.
not lead to good design algorithms short of exnaustive 2) No redundancy. The reason for not allowing re-
searches. For example, to design a two-level AND-OR dundancy is that in the presence of faults in redundant
network, for an arbitrary logic function that will re- leads, the test sets sometimes become invalid [4].1
quire the least number of tests to detect s-a-O or s-a-i 3) The test set can be found without much extra
faults seems to be impossible short of an exhaustive work either during the design phase or after the net-
search over all irredundant two-level realizations of the work is designed. As an example it might be possible to
function. From this simple example it appears that design a network for a switching function which has a
defining goals in quantitative terms might not always predetermined test set. We will give such an algorithm
lead to useful results. We might do better by defining in the next section.
the goals in qualitative terms and then attempting to 4) The structure of the test set is such that it is easy
restate them in quantitative terms whenever feasible. to generate it and/or easy to interpret the results. For
In what follows we will give a qualitative definition of example, one such case can be where the test set is the
what we call easily testable networks. As indicated output of a feedback shift register and a small com-
above, since we are placing the design criteria ahead of binational network is sufficient to interpret the results.
other considerations, we will have to go through a In the next section we show that the network to inter-
phase of experimentation and identification of devices pret the results need only realize a linear switching
and structures that appear to be good candidates for function.
designing easily testable networks. Through our pre- 5) The faults are locatable to the desired degree.
liminary results, given in the next section, we propose In Section II we will give a design technique for
to show that tree networks and two-dimensional cellular arbitrary logic function that uses AND and EOR gates re-
arrays using EXCLUSIVE-OR (EOR) and AND gates are sulting in networks that have the following properties.
promising candidates. We will next give definitions of We assume that only single s-a-O or s-a-1 faults can
terms and notations that will be used in the rest of the occur on input and output leads of AND gates and when
paper and then qualitatively discuss what should be the EOR gates are faulty (only one of them can be
considered in design procedures that will yield easily faulty), any of the 15 other two-variable functions are
testable networks. allowed as the output function of the EOR gate.
Gate Networks: Networks constructed from AND, OR, 1) If the primary input leads are fault-free, then
NOR, NAND, and NOT gates. there exists a realization for an arbitrary n-variable
Test Set: A set of input vectors that are applied to logic function that requires a fault detection test set
test a digital circuit. with only n+4 tests and this test set is independent of
Faults: In this paper while giving our initial results the function being realized.
and problem formulations, we will assume that the type 2) If the primary input leads could be faulty, then
of faults that can occur are permanent s-a-O and s-a-1 only n+4+2ne tests are required for detecting faults,
faults. It is generally accepted that these are the faults where ne is the number of primary inputs appearing in
that are most probable in gate networks. (We will see an even number of product terms in the Reed-Muller
later on that no restriction on the type of faults in the expansion for the function being realized.
EOR gates need be placed for the validity of the results 3) If the primary input leads could be faulty, then
presented in this paper.) by adding an extra observable output and an extra
Fault Detecting Set: A test set that determines whether AND gate, (n+4) tests of 1) will be sufficient and these
the. circuit is working correctly or not under the as- tests will again be independent of the function being
sumption that faults among a given class might have realized.
occurred.
Fault Locating Set: A test set that determines where II. AN EASILY TESTABLE NETWORK
the faults are in the circuit under the assumption that Any arbitrary logic function f(xi, x2, , xe,) has a -

faults among a given class might have occurred. unique Reed-Muller expansion [1], [2] as given in
Redundancy: A set of leads in a circuit is said to be (1):
redundant if logical constants (O or 1) can be assumed
on these leads without changing the value of the output
I If redundancy is present, theii it should be such that test sets
function. (This is just one type of redundancy possible designed for testable faLlIts remain valid in the presence of faults in
but again the most probable type in gate networks.) the redundant portion of the network.

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 REDDY: REALIZATIONS FOR LOGIC FUNCTIONS 1185

X-xi112 X. X- Xx 1 2
' i J1J2 i m

C,+ZX1Xi * DC2n-1X1t2, . * 2 n(1)

e . .

where ii is either xi or the complement of xi and cj is a

binary constant (1 or 0). Notice that only fixed polarity
variables appear; that is, a given variable appears only x0, = c0
in complemented or the uncomplemented form but not
in both forms. For the sake of simplicity let us assume
that all the variables appear uncomplemented. As
given in (1), f(xl, x2, * *, xn) can be realized by the AND gate
network shown in Fig. 1. Each AND gate forms a product
term in (1) for which the corresponding cj is 1.
-A_ j-L Exclusive OR gate
It is helpful to consider an example to preview the
arguments that will be used in proving Theorems 1 and , x,,) as given in (1).
Fig. 1. Network realizing f(xi, X2, *
2 of this section. Recall that we are assuming that only
a single s-a-O or s-a-i fault occurs in the inputs or out-
puts of AND gates or only a single EOR gate is faulty. xi
The output of the faulty EOR gate is allowed to be any
x3
one of the 15 two-variable logic functions other than
EOR.
Example:
f1(x1, X2, X3, X4) = 1 ) X1X2 E X1X4 ( X1X2X3 E X2X3X4
E XlX2X3X4.
The network realizingfi(x1, X2, X3, X4) is given in Fig. 2. f(x.X2,X3x4)
Initially let us assume that the primary input terminals
are fault-free, i.e., the input buses are fault-free but Fig. 2. Network realizingfi(xi, X2, X3, X4).
faults can occur on the inputs to the individual gates.
It has been shown that to detect a single faulty gate in
a cascade of EOR gates, it is sufficient to apply a set of then the output of this gate changes from 0 to 1 and
tests which will apply all possible input combinations the output of the network also changes (either from
to each cell [3]. Such a.test set exists for this network 0 to 1 or from 1 to 0 depending on the output of the
as follows: fault-free network).
Xo X1 X2 X3 X4
Now let us assume that the primary inputs can be
faulty. If a primary input is actually faulty, then the
1 0 0 0 O0 rest of the network is fault-free. To detect the occur-
rence of a primary-input fault, we need to sensitize an
1,I0
01 1 01 01 1 odd number of paths from this input through the AND
gates to the output of the network. The requirement
that an odd number of paths are to be sensitized is due
Furthermore we see that a s-a-0 fault at any AND to the fact that EOR gates are also modulo 2 adders,
gate input or output is detected by appJying either one which implies that an even number of changes at the
of the test inputs [01111, 11111]. A s-a-1 fault at the input to the EOR cascade cancel out and do not imply
output of any AND gate is detected by applying either a change in the output of the cascade.
one of the test inputs [00000, 10000]. A s-a-1 fault at Clearly then the (n+4) tests given above also detect
any one of the inputs to the AND gates is detected by faults at those primary inputs which appear in an odd
one of the four test inputs in the set T2: number of product terms. For example, X3 and X4 ap-
pear in an odd number of product terms. A s-a-0 fault at
'd O 1 1 I' any one of these primary inputs is detected by either
d 1 0 1 1 one of the test inputs 0 1111 or 11111. A s-a- I fault at X3
d I1 0 1 is detected by either one of the test inputs 01101 or
11101 and a s-a-1 fault at X4 is detected by either one of
d I 1 1 0 the test inputs 01110 or 11110. To detect faults at the
where d can be taken as 0 or 1. The validity of this primary inputs that appear in an even number of
claim can be seen by observing that the ith input vector product terms, we give a technique to find the test set.
in T2 places a zero on all AND gate inputs to which xi A single path from an external input xi to the output
is connected, 1 <i<4, and all the other inputs are 1. of the network can be sensitized by the followling input
If the input connected to xi on jth AND gate is s-a-1, vectors (recall that we need to sensitize an odd number

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 1186 IEEE TRANSACTIONS ON COMPUTERS, NOVEMBER 1972

of paths). Let P = xix. Xk be a product term in the We see that the (n +4) test inputs given in Theorem 1
expansion of fi containing minimum number of literals. test s-a-O and s-a-1 faults at the input variables ap-
For example x1x2 is such a product term containing xi pearing in an odd number of product terms. Therefore,
(notice that x1x4 is another such product term). Let we can state the following theorem when primary in-
Vil ( Vi) be the input vector with xi = 1 (xi = O), x; = . .
puts can be faulty.
=XR= 1 (i.e., all the other variables in P are fixed at 1) Theorem 2: For an arbitrary logic function over n
and xi=0 if xi does not appear in P (value of xo again variables there exists a realization for which it is suf-
can be 1 or 0). For example, P=x1x2: we get V1' = dllOO ficient to apply at most (n+4) +2ne test inputs to de-
and V10=dOiOO. If Vil is applied as input, then the tect single faults given in Theorem 1, where ne is the
only AND gate giving an output of 1 (under a fault-free number of variables appearing in an even number of
condition) that has xi as input is the one corresponding product terms.
to P. So if xi lead is s-a-O, the output of this AND gate Proof: From Theorem 1 we need only (n+4) test
changes to zero when Vil is applied as input and will be inputs to detect all faults except those at the primary
detected. Similarlv a s-a-i fault at xi will be detected by inputs that appear in an even number of product terms.
the application of Vi°. For our example we get Faults at these primary inputs need at most 2ne input
vectors given by Vil and V0°, 1 < i < n, defined earlier.
Vil = dii00 V10 = dO1O0
Therefore, in all, we need at most (n+4) +2nfe test
V2' = dllO0 V2°= diOOO. inputs to detect single faults. Q.E.D.
Therefore by applying the inputs in the set T3, stuck-at- There are several points worth noting in the results
faults at the primary inputs can be detected: implied by Theorems 1 and 2. The test set given in
Theorem 1 is independent of the function f(x1, X2, Xn).
T3 = [diiOO, dOi00, dlOOO]. Therefore, if it can be assumed that the network pri-
By applying all the inputs in T' = TiUT2UT3, we mary inputs are fault-free, then a test set independent
can detect a single stuck-at-fault in the network of Fig. of the function is possible. It is certainly reasonable to
2. We can now state and prove the following two assume that primary input buses are fault-free when
theorems. testing a network after fabrication. If the network is
Theorem 1: For an arbitrary logic function over n part of a bigger circuit where its inputs are being ob-
variables there exists a realization for which it is suf- tained as the outputs of other combinational networks,
ficient to apply at most (n+4) test inputs to detect it might not be a good assumption.
single s-a-0 or s-a-i faults in the inputs or output of an Next we have seen that it can be assumed that the
AND gate or a single faulty EOR gate, under the assump- output of a faulty EOR gate can be assumed to be any
one of the 15 two-variable functions (other than EOR).
tion that the primary input terminals are fault-free.
Proof: T he proof is constructive. Assume that the Therefore, the restriction that the faults be of the
given logic function, say J(xi, x2, s-a-O or s-a-1 type is really with respect to the AND
, x,,), is realized
gates. Even then, as can be readily seen, any number of
by a network as given in Fig. 1. Then a fault detecting s-a-O and/or s-a-i faults can appear in a single AND gate
test set T will detect all single s-a-0 or s-a-i faults:
and still the fault detecting test set given above will be
T = T, ' T2 valid. Furthermore, the s-a-0 and s-a-1 faults are the
where most common type of faults in AND gates; therefore, the
fault detecting test sets given in this section detect all
XO Xl X2 . .
*.Xn single faults that are most probable in a network of the
type given in Fig. 1.
Next we will give a technique to add an extra AND
o 1 1 ...* 1 gate and an extra observable output such that the
T 4 input vectors
I 0 0 ...0 (n+4) test inputs in T=TUJT2 given in Theorem 1
11 I 1 ... 1, are sufficient to detect all single faults. We have seen
that we need test inputs other than the ones in T to
and test for faults in input variables which appear in an
d 1 1
0 *...I even number of product terms. For the functionfi given
earlier, xi and x2 appear in an even number of product
T2-g =
I K 1 ll
n input vectors. terms. In Fig. 3 we have the realization for fi given in
Fig. 2 with an extra AND gate (the dotted portion of the
d 1 1 .. I OJ network will be explained later). Assuming that the
output g of the AND gate is also observed, we see that
As explained above by applying test inputs in T, the test inputs in T are sufficient to detect faults in
faults in the EOR cascade are detected and by applying xl and x2 as well as in this extra AND gate also, since a
test inputs in T2 faults in the inputs of the AND gates single patlh is sensitized from xi or x2 to the output g.
are detected. Q.E.D. We will detect a fault even if the network realizing fi

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 REDDY: REALIZATIONS FOR LOGIC FUNCTIONS 1187

Fig. 3. Modified realization forfi.

is fault-free, including the primary inputs if there were Fig. 4. Network to generate the test inputs.
faults in the AND gate added now. If we desire to use the
portion of the network realizing f1 in such1 a situation, (here we allow any number of observable outputs). It
we need to make sure that the faults detected at g are can be shown that the minimum number of tests in a
not in the primary inputs. This can be done by adding fault detecting set for any network realizing the n-
another AND gate with output gl =g. Then observing variable AND function is n+1, which implies that
the otutputs g and g1, we can determine that the faults NM>n+l. Therefore, we see that the test set T is
are not at the primary inputs; if in g or gl but not in asymptotically optimum with respect to the number
both, we detect a wrong output value for one of the of required tests.
test inputs in T. In general then, for an arbitrary func- We have established that realizations for logic func-
tion f, by adding one or two extra AND gates to the tions given above have properties PI, P2, and P3 (it is
realization of Fig. 1, with inputs from all those variables not hard to see that the proposed networks are irre-
that appear in an even number of product terms in the dundant if the EOR gates are realized by irredundant
Reed-Muller expansion forf, we detect all single stuck- gate networks) of the easily testable networks. If our
at-faults by applying only (n+4) tests and these tests design aim was to build logic networks for which it was
are independent of the function f. We state this result easy to determine whether the given network has any
formally in Theorem 3. of the faults assumed possible (fault detection), then
Theorem 3: For any arbitrary logic function we can claim that the realizations being proposed also
f(xi, X2, , xn) there exists a realization that requires have property P5. We next show that the proposed
at most (n+4) test inputs to detect single faults given networks have property P4.
in Theorem 1 and this test set is independent of the The network given in Fig. 4 will generate the (n+4)
function. tests where the counter counts modulo (n+4) the
The number of test inputs given above might not be master reset (which resets all the flip-flops in the shift
minimal for the realization of Fig. 1. For example, if register) is 1 only if the contents of the counter (written
there are any variables that appear only at the inputs [COUNTER]) is less than or equal to 1, the master set
to the EOR gates, then some of the inputs in T2 need not (which sets all the flip-flops in the shift register) is 1
be applied. For example, if xj is one such input, then the only if [COUNTER] = 2, the shift riglht signal is 1 o ily
input (dll . . . 101 . . . 1) in T2 need not be applied. if [COUNTER] =3, the rotate right signal is 1 only if
If the function realized is the n-variable AND function, [COUNTER] >4, and xo is 1 only if [COUNTER] =0 or 2.
then only the input (I1 . . 1) in T1 need be applied. Furthermore, the network required to interpret the re-
A measure of how close to the minimal test set is the sults of the application of test inputs will be shown to
test set given in this section can be obtained by the be simple also. A general network organization for test-
following arguments. Each n-variable function can be ing a logic circuit is given in Fig. 5. The checker is fault-
associated with a unique number j between 0 and 221 -1 free and gives the correct output of the function being
called the characteristic number. We will refer to a realized by the network under test for each test input.
function by its characteristic number. Let Ni be the If the output of the EOR gate (which also is fault-free)
minimum number of tests in a fault detecting set for is 1 for any test input, then the network being tested is
networks realizing the function j and NM be the maxi- faulty. Let F and C be the logic fuinctions realized by
mum [Ni: O<j<22 n_1]. The test set T given above is the network under test (when it is fault-free) and the
independent of the n-variable function being realized checker, respectively. Clearly C depends on F and we
and hence a measure of how close to the minimal test is have seen that the test set is independent of F. We
T can be obtained by comparing a lower bound on might want the network generating the test set to be
NM with the cardinality of T. A simple lower bound independent of F and towards this end we derive two
on Nm can be obtained by finding the minimum number more outputs B1 and B2 from the test generating net-
of tests required to test any realization of an n-variable work, where B1=O if [COUNTER]<3 and 1 otherwise,
AND function by using AND, OR, NAND, and NOR gates and B2 = 0 if [COUNTER ] < 1.

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 1188 IEEE TRANSACTIONS ON COMPUTERS, NOVEMBER 1972

TEST INPUTS It is easy to check that the logic functions given in

the table have the property that their value coiincides
with the value of F whenever a test input is applied-.
Q.E.D.
III. CONCLUSIONS
One of the major drawbacks of the proposed net-
works is the number of logic levels. Several methods to
reduce the number of levels have been developed and
are reported in [5]. We have also derived test sets, in-
dependent of the function being realized, when m>1
gates are allowed to be faulty. These results will be
presented in a later paper. Test sets to locate faults
Fig. 5. Organization to test a logic network. have also been derived and were presented in [6].
In this paper we have given a set of desirable prop-
Definition: A logic function is said to be linear if and erties of easily testable networks and have proposed a
only if its Reed-Mu-ller (RM) canonical expansion does network organization for arbitrary logic functions that
not contain any product term with more than one vari- has these properties.
able.
Let xi,, x'2, XiL be the input variables such that
,
ACKNOWLEDGMENT
the value of F with xo=O, xij=O, and all other inputs
equal tol,1 <j<L,areO.LetP =xoEDxiED3xi,E * Oxi, The author wishes to thank Prof. F. P. Preperata of
and the number of terms other than the constant term the University of Illinois, Urbana, for initially pointing
in the RM canonical expansion of F be N. out that the checker function need only be a linear
Theorem 4: The logic function realized by the checker function.
of Fig. 5 need only be a linear function of the variables REFERENCES
IBI, B2, xO, Xj, X2, . . .
Xn }.
[1] D. E. Muller, "Application of Boolean algebra to switching circuit
Proof: We need to look at four different types of F design and to error detection," IRE Trans. Electron. Comput.,
characterized by the values of N and L. The four types vol. EC-3, pp. 6-12, Sept. 1954.
of F and the logic function to be realized by the checker [2] A. Mukhopadhyay and G. Schmitz, "Minimization of EXCLUSIVE
OR and LOGICAL EQUIV'ALENCE switching circuits," IEEE Trans.
are given in the following table. Comput., vol. C-19, pp. 132-140, Feb. 1970.
[3] W. H. Kautz, "Testing faults in combinational cellular logic
arrays," in Proc. 8th Annu. Symp. Switching and Automata Theory,
Logic Function Realized Oct. 1971, pp. 161-174.
N L by the Checker [4] A. D. Friedman, "Fault detection in redundant circuits," IEEE
Trans. Electron. Comput. (Short Notes), vol. EC-16, pp. 99-100,
odd number odd number P Feb. 1967.
even number odd number B2DP [5] S. M. Reddy, "Easily testable realizations for logic functions,"
odd number even number B2eP Dep. Math., Univ. Iowa, Iowa City, Themis Rep. 54, May 1972.
even number even number B1®3P [6] "Fault locatable two dimensional cellular logic arrays," in
Proc. 6th Annu. Princeton Conf. Inform. Sci. Sys., Mar. 1972.

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