Sir M.

Visvesvaraya Institute of Technology

Affiliated to VTU,Belagavi | Approved by AICTE, New Delhi / Government of Karnataka
Krishnadevaraya Nagar, Hunasamaranahalli, International Airport Road, Bangalore – 562157.

Analog and Digital Electronics

Laboratory Manual
21ECL35

III Semester
 Analog and Digital Electronics Lab [ 21ECL35]

FUNDAMENTAL CONCEPTS
BASIC DEFINITIONS:
Active element:
An active element is one which is capable of generating energy of its own.
Eg: Transistors, FET etc.
Passive element:
A passive element is one which is incapable of generating energy of its own. But it is capable of
storing and dissipating energy.
Eg: Resistor, Capacitor, Inductor etc.
Waveform:
The path traced by a quantity, such as the voltage plotted as a function of some variable such as
time, position, degrees, radiations, temperature, and so on.
Instantaneous value:
The magnitude of a waveform at any instant of time, denoted by lowercase letters (e1, e2)
Peak value:
The amplitude of a waveform of the extent of its voltage or current excursion from the zero
reference.
Peak to peak value = 2 * peak value
Ep-p = 2Em
Periodic waveform:
A waveform that continually repeats itself after the same time interval. The Fig. shows a periodic
waveform.
Period (T):
The time of a periodic waveform.

RESISTOR
A resistor is a passive circuit element which consumes energy.

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SYMBOL

RESISTOR COLOR CODE

Color coding is used for identifying the value of the given resistor. There are two different methods
of color coding in use, namely
1. Four colored band
2. Five colored band
Four colored band

Color band Color Multiplier Color Tolerance

Black 0 Silver 10-2 Red ±2%
Brown 1 Gold 10-1 Gold ±5%
Red 2 Black 100 =1 Silver ±10%
Orange 3 Brown 101 = 10 No color ±20%
Yellow 4 Red 102
Green 5 Orange 103
Blue 6 Yellow 104
Violet 7 Green 105
Grey 8 Blue 106
White 9

Example
Brown ; Black ; Red ; Gold
1 0 102 ±5%
Value is 1000 ±5% Ω

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FIVE COLORED BAND

Color band Color Multiplier Color Tolerance

Black 0 Silver 10-2 Brown ±1%
Brown 1 Gold 10-1 Red ±2%
Red 2 Black 100 =1 Gold ±5%
Orange 3 Brown 101 = 10 Silver ±10%
Yellow 4 Red 102 No color ±20%
Green 5 Orange 103
Blue 6 Yellow 104
Violet 7 Green 105
Grey 8 Blue 106
White 9 Example
Red ; Yellow ;
Black ; Black ; Red
2 4 0 100 ±5%
Value is 240 ±2% Ω

CAPACITOR
A capacitor is a circuit element which is capable of storing energy in the form of voltage during
some period and returns during other time.

SYMBOL

TYPES OF CAPACITOR

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CAPACITOR CONVERSION TABLE

CODE / Marking µF nF pF
microfarads nanofarads picofarads
1RO 0.000001 0.001 1
100 0.00001 0.01 10
101 0.0001 0.1 100
102 0.001 1 1,000
103 0.01 10 10,000
104 0.1 100 100,000
105 1 1,000 1,000,000
106 10 10,000 10,000,000
107 100 100000 100,000,000

CAPACITOR TOLERANCE TABLE

C +/- 0.25pF
D +/- 0.5pF
F 1%
G 2%
J 5%
K 10%
M 20%
Z +80 -20%
Examples:
103K = 0.01µF i.e., 10nF with 10% Tolerance
104K = 0.1µF i.e., 100nF with 10% Tolerance

DIODE
In electronics, a diode is a two-terminal electronic component with asymmetric transfer
characteristic, with low (ideally zero) resistance to current flow in one direction, and high (ideally
infinite) resistance in the other.

SYMBOL

anode cathode

TESTING OF DIODE

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1. Connect a multimeter ( in resistance mode) across the diode

2. Observe the resistance of the diode in that position. If it shows lower resistance value, diode is in
forward bias. Then the terminal connected to the positive terminal of the multimeter is anode (p-
junction) and another terminal is cathode (n-junction).
3. Now reverse the multimeter position and observe the resistance value. If it shows high resistance
then the given diode is good.

BIPOLAR JUNCTION TRANSISTOR (BJT)

A bipolar junction transistor (BJT) is a three-terminal electronic device constructed of doped
semiconductor material and may be used in amplifying or switching applications. Bipolar transistors are
so named because their operation involves both electrons and holes.

SYMBOL

E- Emitter

B-Base

C-Collector

PIN DIAGRAM

Bottom view of SL100 & BC107

TESTING OF BJT
1. For a npn transistor connect the multimeter positive terminal to base terminal of the transistor
and negative terminal to the emitter terminal of the transistor.
2. Follow the procedure given for diode. If it is successful then the given transistor base emitter
junction is good.

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3. Now shift the negative terminal of the multimeter to the collector terminal of the transistor
by maintaining the positive terminal same.
4. Follow the same procedure given for the diode. If it is successful then the given transistors
base collector junction is good.
5. Observe the collector to emitter resistance of the given transistor. It should be a high
resistance in both directions.
6. Above said procedure can be executed for pnp transistor. Here multimeter positions should
be interchanged. Remaining procedure remains the same.

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Experiment 1
Design and set up the BJT common emitter voltage amplifier with and without feedback
and determine the gain- bandwidth product, input and output impedances.

AIM :
To design and set up the BJT common emitter voltage amplifier with and without feedback
and determine the gain- bandwidth product, input and output impedances.

COMPONENTS REQUIRED:
Sl. No. Components Details Specification Quantity
1. Transistor SL100 1 No
2. Resistors 470Ω, 4.7 KΩ, 2.2KΩ , 22KΩ 1 No each

3. Capacitors 0.47 µF 2 Nos

47 µF 1 No
4. Regulated power Supply 0-30 V Variable

5. Signal Generator, CRO

THEORY:
Common emitter (CE) amplifier is widely used in audio frequency applications in radio and
television receivers. It provides current, voltage and power gains. For the proper functioning of
an amplifier the transistor must be biased in the active region. A small increase in base current
results in relatively large increase in collector current and a small decrease in base current is
followed by large decrease in collector current.
The circuit shown a NPN transistor is connected as a common emitter ac amplifier in which the
voltage divider bias is employed. The name voltage divider comes from the voltage divider
network formed by the resistors R1 and R2. The voltage divider bias provides good stabilizationso
that the operating point can be made independent of the variations in hFE. This is achievedby
properly selecting the resistor values R1 and R2.
The input resistance of the amplifier Ri = R1 || R2 || (1+hFE) re with bypass capacitor CE is
connected and Ri = R1 || R2 || (1+hFE) (re + RE) with CE is removed, where re is internal emitter
resistance of the transistor. The resistance re is given by the expression
re = V T / I E
where VT = the equivalent thermal voltage at room temperature.

The output resistance of the amplifier R0 ≈ RC where RC is the collector resistance.

The purpose of the bypass capacitor CE is to bypass signal current to the ground. The ac signal
(feedback voltage ) developed across the emitter resistor RE is bypassed through the capacitorCE
.Thus the gain of the amplifier increases , since this bypassing reduces the negative feedbackacross
RE . This implies that when the bypass capacitor CE is connected, gain increases and bandwidth
decreases and when it is disconnected, gain falls and bandwidth increases.

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The purpose of the coupling capacitors CC1 and CC2 is to couple the ac signal to the input and
output of the amplifier respectively. They block the DC signal and also determine the lowest
frequency which is to be amplified.

CIRCUIT DIAGRAM:

PIN DIAGRAM

Bottom view of SL100 & BC107 & BC547

TESTING OF BJT
• For an NPN transistor connect the multimeter positive terminal to base terminal
ofthe transistor and negative terminal to the emitter terminal of the transistor.
• Follow the procedure given for diode. If it is successful then the given
transistorbase emitter junction is good.
• Now shift the negative terminal of the multimeter to the collector terminal of the
transistor by maintaining the positive terminal same.

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• Follow the same procedure given for the diode. If it is successful then the
giventransistors base collector junction is good.
• Observe the collector to emitter resistance of the given transistor. It should
be ahigh resistance in both directions.
• Above said procedure can be executed for pnp transistor. Here
multimeter positions should be interchanged. Remaining procedure
remains the same.

DESIGN:
Given VCC = 10V, IC = 2mA, β = 50

RE: VRE = VCC / 10 = 10 / 10 = 1V for biasing IE ≈ IC = 2mA

From the fig. We see that,
IERE = VRE
RE = 1/(2x10-3) = 500Ω
Therefore RE ≈ 470 Ω

RC: VCE = VCC / 2 =5V for Q point to be in active region.

Applying KVL to output loop
VCC –ICRC - VCE - VRE = 010 – 2x10-3RC – 5-1 = 0
Therefore RC = 2.2kΩ
R1 & R2:

From biasing circuitVB =VBE+ VRE

= 0.7+ 1 = 1.7V
Assume 10 IB f l o w s through R1 and 9 IB flows through R2.

W.K.T. IC = βIB

2 x 10-3 = 50 IB
Therefore IB = 40μA

from the fig. we see that,

R1 =( VCC – VB ) / 10 IB = (10 – 1.7) / (10 x 40 x 10-6 ) = 21kΩ

Therefore R1 ≈ 2 2 kΩ

R2 = VB / 9IB = 1.7 / (9 x 40 x 10-6 ) = 4.72kΩ

Therefore R2 ≈ 4.7kΩ

CE, CC, CB :

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Let CB = CC = 0.1μF
XCE = RE/10
Therefore f = 10 / (2πCE RE)

Let f = 100Hz and W.K.T RE=470Ω

Therefore CE = 10 / 2πf.RE =
34μFTherefore CE ≈ 47μF.

PROCEDURE:
1. Check and verify the DC bias conditions without connecting capacitors and AC
inputsignal.
2. Connect the capacitors in the circuit. Apply 20 mV peak to peak sinusoidal signal
fromthe function generator to the circuit input. Observe the input and output
waveforms on the CRO screen simultaneously.
3. Keep the input voltage constant at 20mV, vary the frequency of the input signal from
0- 1MHz or highest frequency available in the generator. Measure the output peak to
peak voltage corresponding to different frequencies and enter it in a tabular column.
4. Plot the frequency response characteristics on a semilog graph sheet with gain in
dB onY-axis and f on X-axis. Mark fL and fH corresponding to 3 dB point.
5. Calculate the bandwidth of the amplifier using the expression BW= fH - fL.
6. Determine the mid band gain from the graph plotted.
7. Calculate the gain bandwidth product.
8. Remove the emitter bypass capacitor CE from the circuit and repeat the steps
3-6.Observe that bandwidth increases and gain decreases in the absence of
C E.

OBSERVATIONS:
CE amplifier without feedback (with CE) Vi= mVpp
Frequency Output Voltage Gain = Vo / Vi Gain (dB) = 20Log(Vo/Vi)
(Hz) Vo(P-P)

100
. . . .
. . . .
. . . .

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CE amplifier with feedback (without CE) Vi= mVpp

Frequency Output Voltage Gain = Vo / Vi Gain (dB) = 20Log(Vo/Vi)

(Hz) Vo(P-P)

50
. . . .
. . . .
. . . .

GRAPH:

Frequency response of CE amplifier without feedback (with CE)

Frequency response of CE amplifier with feedback (without CE)

TO MEASURE INPUT IMPEDANCE (Zin):

1. DRB is connected in series with the input as shown in figure and set DRB to 0Ω.
2. Input is applied say (20-30mV p-p) keeping the frequency in mid-band region (say
f=25kHz.)
3. Measure amplitude of Vo (p-p). Let Vo = Va say.

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4. Resistance on DRB is increased till Vo = Va/2.The corresponding DRB value

gives theinput impedance Zin of the amplifier.

TO MEASURE OUTPUT IMPEDANCE Zo:

1. DRB is connected in parallel with output and let the resistance of DRB be at its max.
2. Input is applied say (20-30mV p-p) keeping the frequency in mid-band region (say
f=25kHz.)
3. Measure amplitude of Vo (p-p). Let Vo = Va say.
4. Resistance on DRB is decreased till Vo = Va/2.The corresponding DRB value
gives theoutput impedance Zo of the amplifier.

RESULT:
▪ The CE amplifier with and without feedback was designed and rigged up.
▪ Bandwidth was calculated from the frequency response curve.
▪ Thus the RC Coupled Amplifier was designed and studied.
Parameters With feedback Without feedback

Input Impedance

Output Impedance

Gain (Mid-band)

Bandwidth

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Experiment 2
Design and set-up BJT/FET
i) Colpitts Oscillator
ii) Crystal Oscillator and
iii) RC Phase shift oscillator

AIM:
i) To design and set-up BJT/FET Colpitts Oscillator and determine the
frequency ofoscillation

COMPONENTS REQUIRED:
Sl.No. Components Details Specification Qty
1. Transistor SL100 1
0.47µF, 2
2. Capacitors 47 µF , 1
1000pF 2
3. Resistors 470Ω, 4.7 KΩ, 2.2KΩ , 22KΩ 1 each
1 KΩ Potentiometer

4. Inductors 1 mH 1
DC Power Supply(0-30V), CRO(20MHZ) with Probe,
Multimeter

THEORY:
Oscillators are devices, which generate oscillations. The frequency of oscillations depends on
the feedback network. Feedback maybe of two types namely positive and negative. In
positive feedback, the feedback signal is applied in phase with the input signal thus
increasing it. In negative feedback; the feedback signal is applied out of phase with the input,
thus reducing it. The feedback used in oscillator is positive feedback. The oscillatorswork on
the principle of Barkhausen criteria. This states that for sustained oscillations. Loop gain
Avβ must be equal to 1.The phase shift around the loop must be 0 deg of 360deg.Here AV is
the gain of the amplifier and β is the attenuation of the feedback network. Consider the
feedback network shown in the fig (1) below. Assume an amplifier with inputsignal Vin. The
output signal VO will be 180 deg out of phase with Vin. So to get an in phaseoutput, the
feedback network provides 180 deg phase shift. Therefore the output from thefeedback
network can be made in phase and equal in amplitude to Vin and Vin can be removed .Even
then the oscillations continue. Practical oscillations do not need any inputsignal to start
oscillations. They are self-starting due to thermally produced noise in resistors and other
components. Only one frequency of noise satisfies, Barkhausen criteria and the circuit
oscillates with that frequency. The magnitude of the output keeps on increasing each time it

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goes around the loop. The amplification of fo is limited by circuitsshow nonlinearities.

Therefore to start oscillations Avβ>1 and to sustain it, the loop gain Avβ=1.

Vin Vo

Vf

Fig 1

The feedback network used here consists of L and C. Consider the circuit shown
below fig 2. This circuit consists of L and C in parallel. The capacitor stores energy in its
electric field whenever there is voltage across it and the inductor stores energy in its
magnetic field whenever there is current through it. Initially let us assume that the
capacitor has charged to V volts. When S is closed c= 0. When S is closed at t = t0,
capacitor starts charging through the inductor. Thus a voltage gets built up across the
inductor due to the change in current through it. If the capacitor was charged with the
polarity as shown in the fig 2 the current starts flowing from the positive plate of the
capacitor to the negative plate of the capacitor. As shown the voltage across the capacitor
reduces during the discharge time v reduces and I increases. At time t1 v will be0and I will
be maximum as c is fully discharged, the capacitor charges like sinusoidal oscillations.
Thus the circuit oscillates with the frequency fo = 1/ 2π√LC

Fig 2:
The resonant frequency fo for Colpitts oscillator is

fo = 1/ 2π√𝐿𝐶𝑒𝑞
where Ceq = C1.C2/(C1 + C2)

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CIRCUITDIAGRAM:

COLPITTS OSCILLATOR:

DESIGN:
Given VCC = 10V, IC = 2mA, β = 50

RE: VRE = VCC / 10 = 10 / 10 = 1V for biasing IE ≈ IC= 2 mA

From the fig. We see
that,IERE = VRE
RE = 1/(2x10-3) = 500Ω
Therefore RE ≈ 470 Ω
RC: VCE = VCC / 2 =5V for Q point to be in active region.
Applying KVL to output loop
VCC –ICRC - VCE - VRE = 0
10 – 2x10-3RC – 5-1 = 0
Therefore RC = 2.2kΩ

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R1 & R2:
From biasing circuit VB = VBE+ VRE
= 0.7+1 = 1.7V
Assume 10 IB flows through R1 and 9 IB flows through R2.
W.K.T. IC = βIB

2 x 10-3 = 50 IB
Therefore IB = 40 μA From the fig. we see that,

R1 = (VCC – VB )/ 10 IB = (10 – 1.7) / (10 x 40 x 10-6 ) = 21kΩ

Therefore R1 ≈ 2 2 kΩ
R2 = VB / 9IB = 1.7 / (9 x 40 x 10-6 ) = 4.72kΩ
Therefore R2 ≈ 4.7kΩ

CE, CC, CB : Let CB=CC = 0.1μF

XCE = RE/10
Therefore f = 10 / (2πCE RE)
Let f = 100Hz and W.K.T RE = 470Ω

Therefore CE = 10 / 2πf.RE = 34μF Use CE ≈ 47μF.

DESIGN OF TANK CIRCUIT:

Assume = fo = 100 KHz

COLPITTS OSCILLATOR
fo = 1/ (2π√𝐿𝐶𝑒𝑞)----------------- where Ceq = (C1C2)/(C1 + C2)
Assume C1 = C2 = 1000 pF
Ceq =
⸫ fo = 1/ 2π√𝐿 ∗ 0.05 ∗ 10−6
 L = 5 mH (Use decade inductance box)

PROCEDURE:
1. Rig up the circuit as shown in the circuit diagram.
2. Before connecting the feedback network, check the circuit for
biasingconditions i.e. check VCE, and VRE.
3. After connecting the feedback network. Check the output.
4. Check for the sinusoidal waveform at output. Note down the frequency
of the output waveform and check for any deviation from the designed

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value ofthe frequency.

5. To get a sinusoidal waveform adjust 1KΩ potentiometer.
6. DCB/DIB can be varied to vary the frequency of the output waveform.

RESULT:
Amplitude and frequency of sine wave from Colpitts Oscillator =------------V, ----------------kHz

2(ii) CRYSTAL OSCILLATOR

AIM :
To design and setup the crystal oscillator and determine the frequency of oscillation.
COMPONENTS REQUIRED:

1. Transistor SL100 1 No
0.1 f 2 No
2. Capacitors
47 f 1 No
3. Resistors 22K, 2.2k, 4.7k,
470 Each 1
1 K Pot No
4. Crystal 2 MHz or 1.8 MHz 1 No
DC Supply, CRO with Probe

THEORY:
One of the most important features of any oscillator is its frequency stability, or in otherwords its
ability to provide a constant frequency output under varying load conditions. Some of the factors
that affect the frequency stability of an oscillator generally include: variations intemperature,
variations in the load as well as changes to its DC power supply voltage. Frequency stability of
the output signal can be improved by the proper selection of the components used for the resonant
feedback circuit including the amplifier but there is a limit to the stability that can be obtained
from normal LC and RC tank circuits.
To obtain a very high level of oscillator stability a Quartz Crystal is generally used as the
frequency determining device to produce another types of oscillator circuit known generally
asa Quartz Crystal Oscillator.
When a voltage source is applied to a small thin piece of quartz crystal, it begins to change
shape producing a characteristic known as the Piezo-electric effect. This Piezo-electric
Effectis the property of a crystal by which an electrical charge produces a mechanical force
by changing the shape of the crystal and vice versa, a mechanical force applied to the
crystal produces an electrical charge.
Then, piezo-electric devices can be classed as transducers as they convert energy of one

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kind into energy of another (electrical to mechanical or mechanical to electrical). This piezo-
electriceffect produces mechanical vibrations or oscillations which are used to replace the
LC tank circuit.
There are many different types of crystal substances which can be used as oscillators with
themost important of these for electronic circuits being the quartz minerals because of their
greatermechanical strength. Some of the other commonly used piezoelectric crystals are
Rochelle salt& Tourmaline.
The crystals characteristic or resonant frequency is inversely proportional to its physical
thickness between the two metallised surfaces. A mechanically vibrating crystal can be
represented by an equivalent electrical circuit consisting of low resistance R, a large
inductance L and small capacitance C as shown below.

The equivalent electrical circuit for the quartz crystal shows a series RLC circuit, which
represents the mechanical vibrations of the crystal, in parallel with a capacitance, Cp which
represents the electrical connections to the crystal. Quartz crystal oscillators tend to operate
towards their “series resonance”.
The equivalent impedance of the crystal has a series resonance where Cs resonates with
inductance, Ls at the crystals operating frequency. This frequency is called the crystals series
frequency, ƒs. As well as this series frequency, there is a second frequency point established
as a result of the parallel resonance created when Ls and Cs resonates with the parallel
capacitor Cp as shown.

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CIRCUIT DIAGRAM:

DESIGN:
Given VCC = 10V, IC = 2mA, β = 50
RE: VRE = VCC / 10 = 10 / 10 = 1V for biasing IE ≈ IC =2
mAFrom the fig. We see that,
IERE = VRE
RE = 1/ (2x10-3) = 500Ω
Therefore RE ≈ 470 Ω

RC: VCE = VCC / 2 =5V for Q point to be in active region.

Applying KVL to output loop
VCC –ICRC - VCE - VRE = 0
10 – 2 x 10-3 RC – 5-1 = 0
Therefore RC = 2.2kΩ
R1 & R2:
From biasing
circuitVB =
VBE+ VRE
= 0.7+1 = 1.7V
Assume 10 IB f l o w s through R1 and 9 IB flows through R2.

W.K.T. IC = βIB 2 x 10-3 = 50 IB

Therefore IB = 40 μA
from the fig. we see that,

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R1 = (VCC – VB )/ 10 IB = (10 – 1.7 )/ (10 x 40 x 10-6 ) = 21kΩ

Therefore R1 ≈ 2 2 kΩ

R2 = VB / 9IB = 1.7 / (9 x 40 x 10-6 ) = 4.72kΩ

Therefore R2 ≈ 4.7kΩ

CE, CC, CB: Let CB =CC = 0.1μF

XCE = RE/10
Therefore f = 10 / (2πCE
RE) Let f = 100Hz and W.K.T RE
= 470Ω

Therefore CE = 10 / 2πf.RE =
34μFTherefore CE ≈ 47μF.

DESIGN OF RESONANT TANK CIRCUIT:

CRYSTAL OSCILLATOR:
Use a 2 MHZ crystal to obtain 2MHZ frequency.
[optional ]Use two capacitors each with a nominal valueof 0.1μF in series with the crystal to
block dc.

PROCEDURE:
1. Rig up the circuit as shown in the circuit diagram.
2. Before connecting the feedback network, check the circuit for
biasingconditions i.e. check VCE, and VRE.
3. After connecting the feedback network. Check the output.
4. Check for the sinusoidal waveform at output. Note down the frequency
of the output waveform and check for any deviation from the designed
value ofthe frequency.
5. To get a sinusoidal waveform adjust 1KΩ potentiometer.

EXPECTED GRAPH :

Frequency f0 = 1/T

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RESULT:
Amplitude and frequency of Oscillation =------------V, ---------------- Hz

2(iii) RC Phase shift Oscillator

AIM:

Design a circuit, which generates repetitive waveform (Sinusoidal signal) of frequency 7 KHz.

COMPONENTS/APPARATUS REQUIRED:

Sl. Apparatus/Components Range/Specification Quantity

No.
1. Transistor SL100 1 No
2. Capacitors 0.0022 f 3 NoS.

0.1 f 2 Nos.

47µf 1 No
3. Resistors 22K, 4.7K, 1.2K, 330 Each 1 No
1 K Pot
470 3 Nos.
DC Supply, CRO with Probe
THEORY:

RC Phase shift oscillator consists of a single transistor amplifier and a RCphase shift network. The
Phase shift network consists of three RC sections. Here a fraction of the output of the amplifier is
passed through a phase shift network before feeding back to the input. The phase shift in each section
is 600 so that the total phase shift is 1800.Another 1800 phase shift is provided by the transistor amplifier
and therefore the total phase shift of the oscillator is 360 0 .The frequency of oscillations is given by

fo = 1 / [26(RC)]

Let us consider a RC circuit..

Let I be the current flowing through both R and C. Then using I as the reference vector,Vo is in phase
with I while Vc ,the voltage across the capacitor is 900 behind as shown in the figure.

Vi is the sum of Vo and Vc.Hence Vc is  degrees ahead of Vi and represents a phase shift of  degrees

Vo = IR, Vc =IXc

Tan  =Vc/Vo =Ixc/IR = Xc/R = 1/(2fCR)

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Therefore f = 1/(2fCR Tan )

If there are 3 sections each must give approximately 600

i.e.  = 600 Tan  =3 =1.73

f= 1/(2CR3)

The above phase discussion ignored the additional current I that flows through C for other sections,
so that Vc is actually larger than the value indicated, which means f is smaller.
More accurately f = 1/26(RC)

CIRCUIT DIAGRAM:

DESIGN:

Given VCC = 10V, IC = 2mA, β = 50

RE: VRE = VCC / 10 = 10 / 10 = 1V for biasing IE ≈ IC = 2 mA

From the fig. We see that,

IERE = VRE

RE = 1/(2x10-3) = 500Ω

Therefore RE ≈ 470 Ω

RC: VCE = VCC / 2 =5V for Q point to be in active region.

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Applying KVL to output loop VCC –ICRC - VCE - VRE = 0

10 – 2x10-3RC – 5-1 = 0

Therefore RC = 2.2kΩ

R1 & R2:

From biasing circuit VB = VBE+ VRE

= 0.7+1 = 1.7V

Assume 10 IB flows through R1 and 9 IB flows through R2.

W.K.T. IC = βIB

2 x 10-3 = 50 IB

Therefore IB = 40 μA From the fig. we see that,

R1 = VCC – VB / 10 IB = 10 – 1.7 / (10 x 40 x 10-6 ) = 21kΩ

Therefore R1 ≈ 2 2 kΩ

R2 = VB / 9IB = 1.7 / (9 x 40 x 10-6 ) = 4.72kΩ

Therefore R2 ≈ 4.7kΩ

CE, CC, CB : Let CB = CC = 0.1μF XCE =

RE/10

Therefore f = 10 / (2πCE RE) Let f = 100Hz

and W.K.T RE = 470Ω
Therefore CE = 10 / 2πf.RE = 34μF Therefore CE ≈ 47μF.
DESIGN OF TANK CIRCUIT:
We know that f=1/(2 RC6)
Given fO = 10 KHz
Assume C = 0.002 F
R = 1/(2 x 0.002 x 10-6 x 10 x 10+3 x 6)  2.2k 

PROCEDURE:
1. Make the connections as shown in the circuit diagram.
2. Check the circuit for biasing.
3. Adjust the 1k potentiometer to get sinusoidal waveform at the output.
4. To measure the phase shift
Method 1:
Connect the channel 1 of the CRO to point D and channel 2 to point A.

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We will get two sine waves with a phase difference

Measure the difference by converting the time into angle.
Method 2:
a] Connect channel 1 to point D and channel 2 to point A.
Press the XY knob and measure the phase shift.
 =Sin-1 (a/b) (approx.=600)

b] Connect channel 2 to point B the graph is as shown

b
a

 = Sin-1(a/b) Phase angle =1800-  (approx. = 1200)

C] Connect channel 2 to point C
The transfer function will be almost a straight line and  =00 and therefore phase angle =1800 - 00 =
1800

WAVEFORM:

0 t

RESULT: Thus the circuit for a sinusoidal waveform generator was designed and tested.
Designed Frequency :
Practical Frequency observed : _

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EXPERIMENT 3 :
ADDER, INTEGRATOR DIFFERENTIATOR AND COMPARATOR
AIM:
To Design Adder, Integrator and Differentiator using op-amp

APPARATUS REQUIRED:
S. No Apparatus required Quan
tity
1 Function generator 1
2 Regulated power supply ±12V 1
3 uA 741 opamp 1
4 Resistors-150Ω, 15kΩ, 1.5kΩ,
150kΩ,10kΩ
5 Capacitor – 0.1µF, 0.01µF
6 Bread board 1
7 CRO 1

THEORY:
Adder:
Op-amp may be used to perform summing operation of several input signals in inverting and
non-inverting mode. The input signals to be summed up are given to inverting terminal or non-
inverting terminal through the input resistance to perform inverting and non-inverting summing
operations respectively.
Integrator:
An op-amp integrating circuit produces an output voltage which is proportional to the area
(amplitude multiplied by time) contained under the waveform. To avoid the saturation of the
output voltage and to provide gain control, a resistor with high value of resistance can be
addedin parallel with the feedback capacitor Cf. The closed-loop gain of the integrator will
be
-(Rf/R1), just like a normal inverting amplifier. Consequently, at low frequencies of the input
signal the circuit behaves normally like an integrator. At high frequencies, the capacitor acts
asa short circuit and by-passes the resistor Rf. The capacitor’s reactance in turn reduces the
gainof the amplifier.

Differentiator:
An op-amp differentiator or a differentiating amplifier is a circuit configuration which
producesoutput voltage amplitude that is proportional to the rate of change of the applied
input voltage.A practical differentiator circuit which uses a resistor Ri in series with the input
capacitor anda capacitor Cf in parallel with the feedback resistor. The output voltage of the
practical op-ampdifferentiating amplifier circuit is given as,

Vout = -Rf.Ci {d(Vin)/dt}

i.e. the output voltage is Rf.Ci times the differentiation of the input voltage.

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The addition of resistor Ri and capacitor Cf stabilizes the circuit at higher frequencies, and
alsoreduces the effect of noise on the circuit.

COMPARATOR:

The comparator is an electronic decision-making circuit that makes use of an operational

amplifiers very high gain in its open-loop state, that is, there is no feedback resistor.

Voltage comparators uses positive feedback or no feedback at all (open-loop mode) to switch
its output between two saturated states. Then due to this high open loop gain, the output from
the comparator swings either fully to its positive supply, +Vcc or fully to its negative supply,
-Vcc on the application of varying input signal which passes some preset threshold value.
Inverting Adder:
Design:
Vo = - (Rf/Ri)[V1+V2]
Choose Rf = R1 = R2 = 10kΩ for unity gain.

TABULAR COLUMN:
Si.No V1 V2 Vo = -(V1+V2)

PROCEDURE :
1. Apply DC signal (say V1 = 2V, V2 = 1V) and check for the output.
2. Apply AC signal (say V1 = 2V, V2 = 2V) at a frequency of 1KHz and check
for theoutput
3. Apply V1 = 2V(AC signal) and V2 = 1V (DC signal) and check for the output

Practical Inverting
Differentiator:Design:
WKT T = 2πRFCi. Take T =1ms and Ci =
0.1µF.Then RF = 1.59kΩ. Use RF = 1.5kΩ.

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Ri= RF/10 = 159Ω. Use Ri = 150Ω

Select RiCi = RFCF Take CF = 0.01 µF

CIRCUIT DIAGRAM:

EXPECTED WAVEFORMS:

Tabular Column:
Type of Input Amplitude Input Output Output
Input Vi(p-p) in volts frequency in Amplitude frequency in
Signal Hz Vo(p-p) in volts Hz

Sine
Square
Triangle

Practical inverting
Integrator:Design:
Let f=1KHz, Ri=15KΩ
Then Rf = 10Ri = 150kΩ ,

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WKT 𝑓 = 1
2𝜋𝑅𝑖𝐶𝑓

‫؞‬Cf = 0.01µF
Circuit Diagram:

Tabular Colum:
Type of Input Amplitude Input Output Output
Input Vi(p-p) in volts frequency in Amplitude frequency in
Signal Hz Vo(p-p) in volts Hz
Sine
Square

Expected Waveforms:

COMPARATOR CIRCUIT DIGRAM :

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Vref = 3 V and Vin = 10Vp-p 1 Khz Sine wave

Waveforms :

Vin= 10Vpp Sinusoidal Voltage

Vout= Square Wave Output Votage of Comparator

Vref=3V DC

Procedure:
1. Rig up the circuit as shown in the circuit diagram after testing the op-amp.
2. Apply an sinusoidal input Vi of 1Vpp of f=1kHz. Observe the input and output
signalon the CRO.
3. Apply different types of signal like square and triangular. Observe the output
signalVo and draw a graph.

Result:
Thus Adder, Integrator ,Differentiator and Comparator circuits were designed using op-
amp and verified for their functionalities.

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EXPERIMENT 4:
4- BIT R-2R DAC
AIM:

To design 4 bit R – 2R Op-Amp Digital to Analog Converter

(i) using 4 bit binary input fromtoggle switches and
(ii) by generating digital inputs using mod-16 counter.
COMPONENTS REQUIRED :
Resistors (1 KΩ and 2.2 KΩ) , Digital multimeter , bread board, OP-Amp 741, connecting wires.

THEORY :
A ladder is a series/parallel resistor network a R-2R ladder requires only two resistor value R
and 2R. Nowadays digital systems are used in many applications because of their
increasingly efficient, reliable and economical operation. Since digital systems such as
microcomputers use a binary system of ones and zeros, the data to be put into the
microcomputer have to be converted from analog form to digital form. The circuit that
performs this conversion and reverse conversion are called A/D and D/A converters
respectively. D/A converter in its simplest form use an op-amp and resistors either inthe
binary weighted form or R-2R form. The fig. below shows D/A converter with resistors
connectedin R-2R form. It is so called as the resistors used here are R and 2R. The binary
inputs are simulatedby switches b0 to b3 and the output is proportional to the binary inputs.
Binary inputs are either in high (+5V) or low (0V) state. The analysis can be carried out with
the help of Thevenin’s theorem. The output voltage corresponding to all possible
combinations of binary inputs can be calculated as below.
V0 = - RF [ (b3/2R) + (b2/4R) + (b1/8R) + (b0/16R) ]
Where each inputs b3, b2, b1 and b0 may be high (+5V) or low (0V).
The great advantage of D/A converter of R-2R type is that it requires only two sets of
precision resistance values. In weighted resistor type more resistors are required and the
circuit is complex. Asthe number of binary inputs is increased beyond 4 even D/A converter
circuits get complex and theiraccuracy degenerates. Therefore in critical applications IC D/A
converter is used. Some of the parameters must be known with reference to converters. They
are resolution, linearity error, settling time etc.
Resolution = 0.5V / 28 = 5 / 256 = 0.01

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CIRCUIT DIAGRAM :-

Fig1: Circuit diagram of R-2R DAC

DESIGN:
When Digital i/ps D3 D2 D1 D0 =1001
If VR= 5 V , For a 4 – bit DAC Resolution = V = VR / 24 = 0.2083 V
i.e V= 0.2083 V is the smallest change in the Op – Amp Voltage from R- 2R ladder
network.Out put Vo = ( 23 D3 + 22 D2 +21 D1 + 20 D0) V
Where V = [VR / 24 ] [ 2R/3R] = [ VR/ 24]
So Vo = ( 23 D3 + 22 D2 +21 D1 + 20 D0) . (VR/ 24)
For i/p (1001) , Vo (max) = (9 x 5)/ 24 = 1.875 V
To Generate Stair Case Waveform :

Choose clock frequency = 10 KHz

Step Width = 1 /f = 1/ 10 KHz = 0.1 msec
Minimum Step Size = 0.208 V
Ex: Given step size is 0.208 V
Maximum Step output Vo max = Step Size * No. of Steps
= 0.208 * 9 steps = 1.872 V
Gain of Op –Amp A = (Given Step / Minimum Step ) = 0.208 /0.208 = 1
We can use Voltage follower using Op –Amp.
PROCEDURE :
1. Connect the DAC circuit using R-2R network and Op-Amp Voltage Follower.
2. Construct a Decade Counter using IC 7490/7493
3. Apply Clock Pulses manually at clock input (pin 14 in IC-7490) and record the sequence
ofcounting.
4. Apply a (Say 10KHz clock) and observe their staircase output waveform on CRO

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5. Sketch the input and output waveform on a graph sheet

TABULAR COLUMN :

Decimal D3 D2 D1 D0 Vout(Theoretical) Vout (Practical)

Equivalent Volts Volts

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

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CIRCUIT TO GENERATE STAIRCASE WAVEFORM :

Procedure to generate staircase waveform:-

1. Connect DAC circuit using R-2R ladder network and Op-amp voltage follower.
2. Construct a modulo-16 counters using a suitable digital IC like 7493.counter
outputsQ0,Q1,Q2,Q3 are connected as digital inputs to DAC circuit.

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3. Apply the clock pulses of frequency (1Kz to 10KHz square wave] at pin-14
andobserve the staircase O/P waveform on the CRO,
4. Measure the parameters like time period, step size and calculate the resolution.
5. Sketch the waveform on the graph.

RESULT:
Thus 4 bit R – 2R Op-Amp Digital to Analog Converter (i) using 4 bit binary input
from toggle switches and (ii) by generating digital inputs using mod-16 counter was
designedand outputs were verified.

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EXPERIMENT 5 :
MONOSTABLE and ASTABLE MULTIVIBRATOR
(i) TABLE MULTIVIBRATOR AIM:
To design and verify the operation of monostable multivibrator using 555 Timer.

COMPONENTS REQUIRED:

Sl.No. Equipment/Component name Quantity

1. 555 IC 1
2. Capacitors - 0.01µF 3
3. Resistor 4.7kΩ, 1
100KΩ 1
4. Diode BY127 1
5. Power supply 1
6. Bread board 1
7. Function Generator 1
8. Cathode ray oscilloscope 1

THEORY:
A Monostable Multivibrator, often called a one-shot Multivibrator, is a pulse generating circuitin
which the duration of the pulse is determined by the RC network connected externally to the555
timer. Monostable multivibrator has one stable state and a quasi stable state, the output ofit is
normally low. On the application of external negative trigger pulse at pin 2, the circuit is triggered
and the flip flop in the timer is set which in turn releases the short circuit across C and pushes the
output high. At the same time the voltage across C rises exponentially with thetime constant RAC
and remains in this state for a period RAC even if it is triggered again duringthis interval. When the
voltage across the capacitor reaches 2/3 Vcc, the threshold comparatorresets the flip flop in the
timer which discharges C and the output is driven low, the circuit willremain in this state until the
application of the next trigger pulse. The time during which the output remains high is given by,
Tp = 1.1RAC sec.
Design I:
Given: Pulse width TPW = 0.5msec, Frequency = 1 KHz, output signal TON = 1msec

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Stage 1 Differentiator:
RT CT << TPW
Assume: τ = RT CT = 0.047 msecLet, CT = 0.01µF Then, RT = 4.7 KΩ

Stage II: (For output signal)

Let, TON = 1msec Wkt, TON = 1.1RAC

Assume C = 0.01µF, substituting in the above eqn we get R = 100 KΩ

PROCEDURE:
1. up the circuit as per the circuit diagram.
2. on the DC power supply.
3. the input pulse (square wave) of 1KHz, 5VPP at point Tp1.
4. erve the waveform at test point Tp2, on the falling edge of the input and measure
thewidth of the pulse.
5. lculate the amplitude of the pulse at Tp2 on the rising edge of the input . The diode will
forward bias and clamp the voltage at Tp2 to a maximum of (1/3) x 5V = 1.67volts.
6. erve the waveform at test point Tp3. The external capacitor starts charging on
thefalling edge of the trigger and continues charging for 1msec. At that time the
voltage across the capacitor will be equal to 2/3 Vcc.
7. erve the waveform at test point Tp4. Calculate the pulse width of the output.
CIRCUIT DIAGRAM

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EXPECTED WAVEFORM

TABULAR COLUMN
Ton (Theoretical) Ton (practical) Vc Vc
msec msec (Theoretical) (practical)
Volts Volts
1msec 2/3Vcc = 3.3V

RESULT:
Thus monostable multivibrator was designed and verified.

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5 (ii) ASTABLE MULTIVIBRATOR

AIM: To design and verify the operation of astable multivibrator using 555 Timer for given
frequency and duty cycle.

APPARATUS REQUIRED:
Sl No. Components Quantity
1 555 IC 1
2 Resistor - 3.3KΩ 1
3 Resistors- 6.8KΩ 1
4 Capacitor - 0.01µF 1
5 Capacitor - 0.1µF 1
6 Diode BY127 2
7 Bread board 1
8 Probes 3
9 CRO 1
10 Power supply 5V 1
11 Connecting wires

THEORY:
A 555 timer is a monolithic timing circuit that can produce accurate and highly stable
time delays or oscillations, some of the applications of 555 are square wave generator, astable
and monostable multivibrator. Astable multivibrator is a free running oscillator which has two
quasi stable state, in one state the output voltage remains low for a time interval of Toffandthen
switches over to other state in which the output remains high for an interval of Ton.The time
interval Ton and Toff are determined by the an external resistor and capacitor. It does not require
an external trigger, when the power is switched on the timing capacitor begins to chargetowards
2/3 Vcc through RA & RB, when the capacitor voltage has reached this value, the uppercomparator
of the timer triggers the flip flop in it and the capacitor begins to discharge throughRB,when the
capacitor voltage reaches 1/3 Vcc the lower comparator is triggered and another cycle begins,
the charging and discharging cycle repeats between 2/3 Vcc and 1/3Vcc for the charging and
discharging periods Ton andToff respectively. Since the capacitor charges throughRAand RB and
discharges through RB only, the charge and discharge are not equal and hence the output is not
a symmetrical square wave and the multivibrator is called an asymmetric astable multivibrator

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(duty cycle = 75%). The symmetrical square wave (duty cycle=50% and Ton= Toff = 0.5msec)
can be obtained if a diode is connected across resistor RB, as illustratedin figure The capacitor C
charges through RA and diode D to approximately + 2/3VCC and discharges through resistor RB
(other side of RB is connected to the discharge terminal, pin 7) and until the capacitor voltage
drops to 1/3 VCC. Then the cycle is repeated.

DESIGN:
Asymmetrical Astable Multivibrator
At any time instant
Vc(t) = Vf – (Vf – Vi)e-T/RC
Where Vc(t)= charging voltage of Capacitor
Vf = final voltage, Vi = initial voltage
Substituting, T = Ton, Vc(t) =(2/3) Vcc
Vf = Vcc, Vi = (1/3)Vcc
We get Ton = 0.693 (RA+RB)C

At T = Toff Vc(t) = Vcc / 3

Vf = 0 Vi = Vcc ( 2/3)
Toff = 0.693RBC

 T = Ton + Toff = 0.693 (RA+ 2RB)C

Given data
f = 1 kHz, Duty cycle = 0.75 (75%)
Duty Cycle D = Ton / T => Ton = 0.75msec
⸫Toff = T – Ton = 0.25
msec0.25 x 10-3 = 0.693
RB C
Choose C = 0.1µf
RB = 0.25 x 10-3 = 3.6 KΩ (Use
3.3KΩ)0.693 x 0.1 x 10-6
Ton = 0.693 (RA + RB)C

=> RA = (Ton / 0.693 C) - RB

⸫ RA = 7.2kΩ (use 6.8KΩ)

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CIRCUIT DIAGRAM:

DESIGN:
Symmetrical Astable Multivibrator
VUT = upper threshold voltage = 2/3
VCC VLT = Lower threshold voltage =
1/3 VCCTON = 0.693 RAC
TOFF = 0.693 RB C

T = TON+ TOFF = 0.693 ( RA + RB ) C

Output frequency f = 1 / T = 1.44 / (RA+RB) C

Duty cycle D = 𝑇𝑂𝑁 = 𝑅𝐴

𝑇 𝑅𝐴+𝑅𝐵

Given f = 1 KHz, Duty cycle D= 0.5 (50%)

Let T = TON + TOFF= 1 msec
D = 0.5  TON = 0.5 msec and TOFF =
0.5msecTOFF = 0.693 RB C

Choose C = 0.1µf
TOFF
 RB = = 7.2KΩ (Choose R = 6.8KΩ)
0.693𝐶

RA = RB = 7.2KΩ (Choose R = 6.8KΩ)

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CIRCUIT DIAGRAM:

PROCEDURE:
1. Rig up the circuit as per the circuit diagram.

2. Switch on the DC power supply.

3. Observe the wave form on CRO at pin 3 and measure the outputamplitude &time period
4. Observe the wave form on CRO at pin 6 and measure VUT and VLT
5. Verify that VCharging=2/3Vcc and Vdischarging=1/3 Vcc
6. Calculate the duty cycle D, output frequency and verify with design values.

OBSERVATIONS:

Asymmetrical Astable Multivibrator

Ton Ton Toff Toff Vcharging Vcharging Vdischarging Vdischarging

(Theoritical) (practical) (Theo) (Prac) (Theo) (Prac) (Theo) (Prac)
ms ms ms Ms Volts Volts Volts Volts

0.75ms 0.25ms 3.33 1.66

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Symmetrical Astable Multivibrator

Ton Ton Toff Toff Vcharging Vcharging Vdischarging Vdischarging
(Theoritical) (practical) (Theo) (Prac) (Theo) (Prac) (Theo) (Prac)Volt
ms ms ms Ms Volts Volts Volts s

0.5ms 0.5ms 3.33 V 1.66 V

EXPECTED WAVEFORMS

RESULT: Thus astable multivibrator was designed and verified.

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EXPERIMENT 6

SILICON CONTROLLED RECTIFIER (THYRISTOR) V-I

CHARACTERISTICS

AIM: 1. To plot the V-I characteristics of SCR

2. To Find Latching and Holding current of the given SCR

APPARATUS:
Component Name Range Quantity
Silicon Controlled Rectifier TY612 1
Regulated D C Power 0‐30 V 2
Supply
Voltmeter 0‐100V 1
Digital Multimeter - 1
Ammeters 0‐250mA 2
Resistor 2.2K 1
Resistor 500 1

THEORY:

Thyristor Characteristics: ‐ A thyristor is a four-layer semiconductor device of PNPN structure

with three PN junctions. It has three terminal anode, cathode and gate. When the anode voltage
is made positive with respect to cathode, the junctions J1 and J3 are forward biased. The junctions
J2 is reversed biased and, only a small leakage current flows from anode to cathode. The thyristor
is then said to be in the OFF mode. If an Anode to Cathode voltage is increased to a sufficiently
large value, the reversed biased junction J2 will break. This is known as avalanche breakdown
and the corresponding voltage is called forward breakdown voltage VBO. Since junctions J1 and
J3 are already forward biased, there will be free movement of carriers across all three junctions,
resulting in a large forward anode current. The device will then be in a conducting state or on
state. The voltage drop would be due to the ohmic drop in the four layers and it is small, typically,
1V. In the on state, the anode current is limited by an external impedance or resistance.
Latching current is the minimum anode current required to maintain the thyristor in the on state
immediately after the thyristor has been turned on and the gate signal has been removed. Once
the thyristor is turned on, it behaves like a conducting diode and there is no control over the
device. The device will continue to conduct because there is no depletion layer on the junction
J2 due to the free movements of the carriers. However, if the forward anode current is reduced
below a level known as the holding current, a depletion layer will develop around the junction
J2, due to reduced number of carriers and the thyristor will be in the blocking state. Holding
current is the minimum anode current required to maintain the thyristor in the on state.
Holding current is less than latching current. A thyristor can be turned on by increasing the
forward voltage VAK beyond VBO, but such a turn on could be destructive. In practice, the

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forward voltage is maintained below VBO and the thyristor is turned on by applying a positive
voltage between its gate and cathode. Once a thyristor is turned on by a gating signal and its
anode current is greater than holding current, the device continues to conduct due to positive
feedback, even if the gating signal is removed.
CIRCUIT DIAGRAM

IK  /I

1K /1W

PROCEDURE
1. Connections are made as shown in the circuit diagram.
2. The value of gate current Ig, is set to convenient value by adjusting Vgg.
3. By varying the anode- cathode supply voltage Vaa gradually in step-by step, note down the
corresponding values of Vak & Ia. Note down VAK & Ia at the instant of firing of SCR and
after firing (by reducing the voltmeter ranges and increasing the ammeter ranges) then increase
the supply voltage Vaa.
4. Note down corresponding values of Vak & Ia.
5. The point at which SCR fires, gives the value of break over voltage VBO.
6. A graph of Vak verses Ia is to be plotted.
7. The on-state resistance can be calculated from the graph by using a formula.
8. The gate supply voltage Vgg is to be switched off Observe the ammeter reading by reducing
the anode-cathode supply voltage Vaa. The point at which the ammeter reading suddenly goes
to zero gives the value of Holding Current Ih. Steps No.2, 3, 4, 5, 6, 7, 8 are repeated for another
value of the gate current Ig.
Alternate Method
1. Connections are made as shown in the circuit diagram

2. Adjust the value of Ig to zero or some minimum value

3. By varying the voltage Vak from 0 to 10 volts with a step of 2 volts, note down corresponding
values of Ia

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4. Now apply the gate voltage gradually, until SCR fires, then note down the values of Ig and also
the values of Ia and Vak
5. Increase Vaa to some value and note down Ia and Vak

6. Reduce gate voltage to zero, observe ammeter reading by reducing Vaa which gives the values
of Ih (holding current) at the point at which, current suddenly drops to zero
7. Repeat the steps 2, 3, 4, 5 & 6 for different values of break over voltage Plot a graph of Vak v/s
Ia

To find Latching current (IL):

1. Keep proper Vak to trigger SCR by gate current. Then trigger SCR by applying gate current.
2. Gradually decrease VAK in steps and at each step switch-off the gate supply (i.e., VGK source)
and observe that, whether device remains in the ON state or not.
3. Repeat step 2 (by trial-and-error method) till the SCR jumps to blocking state, and then note
down the minimum value of Ia which keeps device in the on state as Latching current.

To Find Holding current (Ih):

Keep proper Vak to trigger SCR by gate current. Then trigger SCR by applying gate current.
Switch-Off VGK source permanently. Now gradually decrease VAK and note down the
minimum value of Ia below which, the device suddenly falls from ON-state to OFF- state as
Holding current.

TABULAR COLUMN
Ig = mA
V2 (V) VAK IA (mA)
(Volts)

The on-state resistance can be calculated from the graph by using formula,

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RON - STATE = ∆ VAK/ ∆ 𝐼𝐴

MODEL GRAPH – V I CHARACTERISTICS OF SCR

Result : The Static Characteristics of the given SCR has been measured.

Ig = ................. mA.
VBO = ................. V
IH = ................ mA
IL =.................. mA

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Experiment No 7:

PRECISION HALF AND FULL WAVE RECTIFIER

AIM: To design and verify characteristics of
a. Precision Half Wave Rectifier and

b. Precision Full Wave Rectifier, using OP-Amp.

THEORY:
The major limitation of ordinary diodes is that it cannot rectify voltage below
0.6v, the cut in voltageof the diode. The precision rectifier, which is also known
as a super diode, is a configuration obtained with an operational amplifier in
order to have a circuit behaving like an ideal di n be useful for high-precision
signal processing.

PRECISION HALF WAVE RECTIFIER:

A Half-wave rectifier is an electronic circuit. The rectifier circuit takes

alternating current (AC) from the wall outlet and converts it into a positive
direct current (DC) output. The particular electronic device that accomplishes
this task is a semiconductor called diode. diode like all semiconductors is a
material which has a resistance in between that of a conductor or wire and an
insulator like that of a plastic.

PRECISION FULL WAVE RECTIFIER:

A Full Wave Rectifier is a circuit, which converts an ac voltage into a pulsating

dc voltage using both half cycles of the applied ac voltage. It uses two diodes of
which one conducts during one half cycle while the other conducts during other
half cycle of the applied ac voltage
During the positive half cycle of the input voltage, diode D1 becomes forward
biased and D2 becomes reverse biased. Hence D1 conducts and D2 remains
OFF. The load current flows through D1 and the voltagedrop across R half cycle
of the input voltage, diode D1 becomes reverse biased and D2 becomes forward
biased. Hence D1 remains OFF and D2 conducts, The load current flows
through D2 and the voltage drop across R half cycle of the input voltage.

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CIRCUIT DIAGRAMS:

a. PRECISION HALF WAVE RECTIFIER USING OPAMP:

b. PRECISION FULLWAVE RECTIFIER USING OPAMP:

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PROCEDURE:

1. Connect all the circuit elements as shown in Figure.

2. Set the input to 0.5 v p-p and frequency of 1 kHz and apply to the input.

3. Observe the output voltages by on the CRO

4. Note down the waveforms.

5. Observe transfer characteristics for both the rectifiers and plot the same.

WAVEFORMS:

a) PRECISION HALF WAVE RECTIFIER

b) PRECISION FULLWAVE RECTIFIER

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RESULT: Half wave and Full Wave precision rectifier are designed using an op-

amp was designed and the output is verified .

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DIGITAL ELECTRONICS PART :

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Experiment No: 8
Realize
i. Half Adder & Full Adder using i) basic gates. ii) NAND gates
ii. Half subtractor& Full subtractor using i) basic gates ii) NAND gates.
iii. 4-Variable Function using IC74151 [ 8:1 MUX]

Aim: To realize half /full adder using logic gates and NAND Gates

Theory:
(a) ADDER:
An Adder is a circuit which performs addition of binary numbers. Producing
sum and carry. An half adder is a digital circuit which performs addition of
two binary numbers which are one bit each and produces a sum and a
carry (one bit each). A full adder isa digital circuit which performs addition
of three binary numbers (one bit each), to produce a sum and a carry (one
bit each). Full adders are basic block of any adder circuit as they add two
numbers along with the carry from the previous addition.

1. Half Adder
Block Diagram: Truth Table

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Logic Diagram: i) Using Logic Gates

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Logic Diagram: i) Using NAND Gates

2. Full Adder Block Diagram:

(a) Full Adder Using

Logic GatesTruth
Table (Full Adder)

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Logic Diagram: : i) Using Logic Gates

Cin

Logic Diagram: : i) Using NAND Gates

Procedure:

1. Place the IC in the socket of the trainer kit.

2. Make the connections as shown in the circuit diagram.
3. Verify the truth table for half adder and full adder circuits using
basic and Universal gates.

SUBTRACTORS

Theory:
Subtractors are digital circuits which perform subtraction of binary
numbers to produce a difference and a borrow if any. A half subtractor
subtracts two one bit numbers to give their difference and a borrow if any.
A full subtractor subtracts two one bit numbers along with a borrow (from
previous stage) to generate a difference and a borrow.

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1. Half SubtractorBlock Diagram:

Logic Diagram: : i) Using Logic Gates Truth Table

A B Sum Carry
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Logic Diagram: : i) Using NAND Gates

2. Full Subtractor Block

Diagram

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(a) Full Subtractor Using Logic Gates Truth Table

A B Bin Diff Borrow

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Logic Diagram: : i) Using NAND Gates

Iii ) To realise 4-variable function F(A,B,C,D) = ∑m (2,4,5,7,10,14)using

IC74151(8:1MUX).

Theory:
The given function is in terms of minterms and is to be implemented using
a 8:1 MUX. An 8:1MUX has three select lines, whereas the given function
is a 4 variable function. Hence a logicis needed to give combination of D as
inputs while only A,B,and C as select line inputs. The method for the same
is described below.

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Pin Diagram:

Logic Diagram:

Result:
i) Adders and subtractors are verified using logic gates and Universal
gates.
ii) A 4 variable Function was realized using IC74151

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Experiment : 9

Realize
[ I ] Binary to Gray Code Conversion and Vice - Versa [ IC74139 ].
[ ii ] BCD to Excess-3 Code Conversion and Vice - Versa.

Aim :
To design and realize Binary to Gray Coe conversion using IC74139 .

COMPONENTS REQUIRED:
IC’s 74139, 7400, 7404, 7420 Patch Cords & IC Trainer Kit.

THEORY:
A decoder is a combinational circuit that connects the binary information from ‘n’
input lines to a maximum of 2n unique output lines. Decoder is also called a min-
term generator/maxterm generator.
A demultiplexer is a combinational logic circuit that receives the information on a
single input and transmits the same information over one of 2n possible output
lines. The bit combinations of the select lines control the selection of specific
output line to be connected to the input at given instant.
Demultiplexers are also called as data distributors, since they transmit the same
data which is received at the input to different
destinations. Thus, a demultiplexer is a 1-to-N
device where as the multiplexer is an N-to-1 device.

The figure shows the block diagram of a

demultiplexer or simply a DEMUX. It consists of 1
input line, n output lines and m select lines. In this,
m selection lines are required to produce 2m
possible output lines (consider 2m = n). For
example, a 1-to-4 demultiplexer requires 2 select
lines to control the 4 output lines.

The IC 74LS139 is a high speed Dual 2-of-4 Decoder/1:4 Demultiplexer. The

device has two independent decoders, each accepting two inputs and providing
active LOW Outputs. Each decoder has an active LOW Enable input which can
be used as a data input for a 4-output demultiplexer. Each half of the LS139 can
be used as a function generator providing all four minterms of two variables.

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Pin details – IC 74139

I) BINARY TO GRAY CODE CONVERSION & VICE VERSA (74139)

THEORY:

Gray code – also known as Cyclic Code, Reflected Binary Code (RBC) – is defined as
an ordering of the binary number system such that each incremental value can only
differ by one bit. In gray code, while traversing from one step to another step only one
bit in the code group changes. That is to say that two adjacent code numbers differ
from each other by only one bit.

Gray code is the most popular of the unit distance codes, but it is not suitable for
arithmetic operations. Gray code has some applications in analog to digital
converters, as well as being used for error correction in digital communication. The
logical circuit which converts the binary code to equivalent gray code is known as
binary to gray code converter.

Binary to gray code conversion process. There are several steps to do these types
of conversions. Steps given below elaborate on the idea on this type of conversion.

(1) The M.S.B. of the gray code will be exactly equal to the first bit of the given
binary number.

(2) Now the second bit of the code will be exclusive-or of the first and second bit of
the given binary number, i.e if both the bits are same the result will be 0 and if they
are different the result will be 1.
(3) The third bit of gray code will be equal to the exclusive -or of the second and
third bit of the given binary number. Thus the Binary to gray code conversion goes
on. One example given below can make your idea clear on this type of conversion.
Binary to Gray:

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Truth table Circuit Diagram

Binary Input Gray code output
B2 B1 B0 G2 G1 G0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0

G2 = B2
G1 = B1 ⊕ B2
G0 = B0 ⊕ B1

Gray to Binary :
Truth table Logic -diagram

Gray code Input Binary output

G2 G1 G0 B2 B1 B0

0 0 0 0 0 0

0 0 1 0 0 1

0 1 1 0 1 0

0 1 0 0 1 1

1 1 0 1 0 0

1 1 1 1 0 1

1 0 1 1 1 0

1 0 0 1 1 1

B2 = G2 , B1 = G1⊕ B2 , B0 = G0⊕ B1

Result : Thus Binary to gray code conversion and Vice versa was realized and
verified.

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II) BCD to Excess -3 Code Conversion and Vice Versa using IC74139.
Aim:
To realize BCD TO EXCESS-3 CODE CONVERSION AND VICE VERSA USING IC
7483.
Theory:
Code converter is a combinational circuit that translates the input code word into a
new corresponding word. The excess-3 code digit is obtained by adding three to the
corresponding BCD digit. To Construct a BCD-to-excess-3-code converter with a 4-
bit adder feed BCD code to the 4- bit adder as the first operand and then feed constant
3 as the second operand. The output is the corresponding excess-3 code.
To make it work as a excess-3 to BCD converter, we feed excess-3 code as the first
operand and then feed 2's complement of 3 as the second operand. The output is the
BCD code.
Truth Table :

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Logic Diagram:

EXCESS-3 CODE to BCD conversion :

Truth Table:

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Logic Diagram :

PROCEDURE:
1. Check all the components for their working.
2. Make connections as per the logic diagram.
3. Apply BCD code as first operand (A) and binary 3 as second operand (B) and
Cin = 0 for BCD – Excess 3 code conversion.
4. Apply Excess-3 code as first operand (A) and binary 3 as second operand (B)
and
Cin = 1 for Excess 3 – BCD code conversion.
5. Verify the truth table and observe the outputs.

RESULT :
Thus BCD to Excess 3 and Vice Versa code conversion was realized and verified.

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Experiment -10 :
Realize using NAND Gates :
i) Master-Slave JK Flip Flop.
ii) D Flip Flop.
iii) T Flip Flop.

Aim :
Realize the following flip-flops using NAND gates -Master-Slave JK,D and T Flip-
flop.
Components Required :
IC’s 7400, 7410 Patch Cords & IC Trainer Kit.
THEORY:
A flip-flop is a circuit that has two stable states and can be used to store state
information. A flip-flop is a bi-stable multivibrator. The circuit can be made to change
state by signals applied to one or more control inputs and will have one or two
outputs. It is the basic storage element in sequential logic.

Flip-flops and latches are a fundamental building block of digital electronics systems
used in computers, communications, and many other types of systems. With the help
of Boolean logic we can create memory with them. Flip flops can also be considered
as the most basic idea of a Random Access Memory [RAM].

The most commonly used application of flip flops is in the implementation of a

feedback circuit. As memory relies on the feedback concept, flip flops can be used to
design it.
For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q output will
toggle as long as CLK is high, which makes the output of the flip-flop unstable or
uncertain. This problem is called race around condition in J-K flip-flop. This problem
(Race Around Condition) can be avoided by ensuring that the clock input is at logic
“1” only for a very short time. This introduced the concept of Master Slave JK flip flop.

The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected

together in a series configuration. Out of these, one acts as the “master” and the other
as a “slave”. The output from the master flip flop is connected to the two inputs of the
slave flip flop whose output is fed back to inputs of the master flip flop.
Working of a Master Slave J K flip flop:

1. When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect
the state of the system. The slave flip-flop is isolated until the CP goes to 0. When the

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CP goes back to 0, information is passed from the master flip- flop to the slave and
output is obtained.

2. Firstly, the master flip flop is positive level triggered and the slave flip flop is
negative level triggered, so the master responds before the slave.

3. If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave
and the clock forces the slave to

reset, thus the slave copies the master.

4. If J=1 and K=0, the high Q output of the master goes to the J input of the slave
and the Negative transition of the clock sets the slave, copying the master.

5. If J=1 and K=1, it toggles on the positive transition of the clock and thus the
slave toggles on the negative transition of the clock.

6. If J=0 and K=0, the flip flop is disabled and Q remains unchanged.

D Flip-flop: The D flip-flop has only a single data input D. That data input is
connected to the J input of a JK flip-flop, while the inverse of D is connected to the K
input. The output will be the same as the input.
T Flip-flop: The T flip-flop is known as Toggle flip-flop. It’s a modification of JK flip-
flop obtained by connecting both the J & K inputs together. When T=0, i.e J=K=0,
there is no change in the output. When T=1, i.e J=K=1 then the output toggles.

Master-Slave JK Flip flop - Logic diagram :

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Truth Table :

Master-Slave D Flip flop - Logic diagram :

𝐏̅𝐑𝐄
̅̅ CLK D Qn+1 ̅ n+1
𝐐 Comment
CLR
0 0 Not Allowed

0 1 X X 1 0 Set

1 0 X X 0 1 Reset
1 1 1 0 0 1 Same as ‘D’

1 1 1 1 1 0 Same as ‘D’

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Ii ) D Flip-Flop :

Logic Diagram :

Iii ) T Flip Flop :

Logic Diagram :

PROCEDURE:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as per the logic diagram.
4. Verify the Truth Table and observe the outputs
RESULT: Thus the Flip Flops are realized and functionality is verified.

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Experiment - 11:
Realize the following shift registers using IC7474/7495
(i) SISO (ii) SIPO (iii)) PISO(iv) )PIPO (v) Ring (vi) Johnson counter

Aim:
To realise SIPO, SISO, PISO, PIPO operations Ring and Johnson counters using
IC7495/7474
Theory:
Registers are simply a group of flip flops that can be used to store a binary number.
A shift register is nothing but a register which can accept binary number and shift it.
The data can be entered in the shift register either in serial or in parallel. The output
can be taken either in serial or in parallel. Since there are two ways to shift data in
to a register and two ways to shift data out of the register four types of registers can
be constructed. A register capable of shifting its binary information either to the left
or to the right is called a shift register. The logical configuration of a shift register
consists of a chain of flip flops connected in cascade with the output of one flip flop
connected to the input of the next flip flop. All the flip flops receive a common clock
pulse which causes the shift from one stage to the next.

The Q output of a D flip flop is connected to the D input of the flip flop to the left.
Each clock pulse shifts the contents of the register one-bit position to the right. The
serial input determines, what goes into the right most flip flop during the shift.

Shift registers are used extensively in logic circuits to control digital displays.

A classic example is numbers being typed into a calculator. As the numbers are
entered, the digits shift to the left one position. This shifting is controlled by a shift
register.
Types of shift registers:
1. Serial In Serial Out [SISO]:
In this type of register, the output of one flip-flop is connected to the input of the next
flip-flop. Output of the register is obtained from the last flip-flop. Depending on the
direction of the input given shifting takes place in this. Bit by bit loading is done with
every clock pulse and shifting takes place with every clock pulse.
2. Serial In Parallel Out [SIPO]:
This is similar to SISO except that the output is taken from each flip-flop. Thereby
the shifted value is shown at once.

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3. Parallel In Parallel Out [PIPO]:

Upon giving clock pulse, data is loaded in parallel in all flip-flops. Output is taken
from each of the flip-flop.

4. Parallel In Serial Out [PISO]:

Here the data is loaded parallelly and the output is obtained from the last flip-flop.
Ring Counter:
A ring counter is a circular shift register which is initiated such that only one of its
flip-flops has the state one while others are in their zero states. A ring counter is a
Shift Register with the output of the last one connected to the input of the first, that
is, in a ring. Typically, a pattern consisting of a single bit is circulated so the state
repeats every ‘n’ clock cycles if ‘n’ flip-flops are used. It can be used as a cycle counter
of n states.

Johnson Counter:
A Johnson counter (or switch tail ring counter, twisted-ring counter, walking-ring
counter) is a modified ring counter, where the output from the last stage is inverted
and fed back as input to the first stage. The register cycles through a sequence of bit-
patterns, whose length is equal to twice the length of the shift register, continuing
indefinitely.

They can be implemented easily using D- or JK-type flip-flops.

IC 7495 – Pin details :

DS –> Serial i/p data to be right shifted.

P0, P1, P2, P3 –> Parallel i/p data
Q0, Q1, Q2, Q3 –> Parallel O/P of shift register
S/M = O –> ̅C̅P̅1̅ / Clk1 enabled
S/M = 1 –> ̅C̅P̅2̅ / Clk2 enabled
CP1 / Clk1 -> For right shift of data
̅ CP2 / Clk2 -> Parallel load of data

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Function table of IC 7495 :

Circuit diagram:

1. SISO: Truth Table :

Clock Serial i/p QA QB QC QD

1 do=0 0 X X X
2 d1=1 1 0 X X
3 d2=1 1 1 0 X
4 d3=1 1 1 1 0=do
5 X X 1 1 1=d1
6 X X X 1 1=d2
7 X X X X 1=d3

2. SIPO : Truth Table :

Clock Serial i/p QA QB QC QD

1 0 0 X X X

3. PISO : 2 1 1 0 X X
3 1 1 1 0 X
4 1 1 1 1 0
Truth Table :

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3.PISO
Logic Diagram Truth Table :

Mode Clock Parallel i/p Serial o/p

A B C D QA QB QC QD
1 1 1 0 1 1 1 0 1 1
0 2 X X X X X 1 0 1
0 3 X X X X X X 1 0
0 4 X X X X X X X 1

4. PIPO :

Clock Parallel i/p Parallel o/p

A B C D QA QB QC QD
1 1 0 1 1 1 0 1 1

5. RING Counter :

Mode Clock QA QB QC QD
1 1 1 0 0 0
0 2 0 1 0 0
0 3 0 0 1 0
0 4 0 0 0 1
0 5 1 0 0 0
0 6 repeat

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6. JOHNSON Counter :

Mode Cloc QA QB QC QD
k
1 1 1 0 0 0
0 2 1 1 0 0
0 3 1 1 1 0
0 4 1 1 1 1
0 5 0 1 1 1
0 6 0 0 1 1
0 7 0 0 0 1
0 8 0 0 0 0
0 9 1 0 0 0
0 10 repeat

PROCEDURE:

1. Serial In Serial Out (SISO)

1. Connections are made as per the circuit diagram.

2. Load the shift register with 4 bits of data one by one serially.
3. At the end of 4th clock pulse, the first data ‘d0’ appears at ‘QD’.
4. Apply another clock pulse, the second data ‘d1’ appears at ‘QD’.
5. Apply another clock pulse, the third data ‘d2’ appears at ‘QD’.
6. Application of next clock pulse will enable the 4 thdata ‘d3 ’ to appear at ‘QD’.
Thus the data applied serially at the input ‘DS ‘comes out serially at ‘QD’.

2. Serial In Parallel Out (SIPO)

1. Connections are made as per the circuit diagram.

2. Connect ‘M’ to logic 0 and apply the data at the serial i/p ‘DS ‘from LSB.
3. Apply one clock pulse at clk1, observe the data right shifted and available at
‘QA’.
4. Apply the next data at ‘DS ‘, and once again apply the clock pulse .Observe
the data on ‘QA’ shifted to ‘QB’ and the new data applied available on ‘QA’.
5. Repeat the above steps till all the 4 bits of data are entered one by one into
the shift register.

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3. Parallel In Serial Out (PISO)

1. Connections are made as per the circuit diagram.

2. Apply the desired 4 bit data at A, B, C and D.
3. Keeping the mode control M=1 apply one clock pulse at clk2. The data applied
at A, B, C and D will appear at QA, QB, QC and QD respectively.
4. Now make mode control M=0. Apply clock pulses one by one and observe the
data coming out serially at ‘QD’.

4. Parallel In Parallel Out (PIPO)

1. Connections are made as per the circuit diagram.

2. Apply the desired 4-bit data at A, B, C and D.
3. Apply one clock pulse at clk2 with Mode control M=1.
4. The four-bit data at A, B, C and D appears at QA, QB, QC and QD
respectively.

5. Ring Counter

1. Connections are made as per the circuit diagram.

2. Apply the data 1000 at parallel i/p’s A, B, C and D respectively.
3. Keeping the mode M = 1, apply one clock pulse, verify the data loaded at the
o/p at QA, QB, QC and QD respectively.
4. Now the mode M is made 0 and clock pulses are applied one by one and the
truth table is verified.

6. Johnson Counter

1. Connections are made as per the circuit diagram.

2. Keeping the mode M = 1, apply the data 0000 at parallel i/p’s A, B, C and D
respectively.
3. Apply one clock pulse, verify the data loaded at the o/p at QA, QB, QC and
QD respectively.
4. Now the mode M is made 0 and clock pulses are applied one by one and the
truth table is verified.

RESULT:

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EXPERIMENT NO 12 :
i. Design Mod – N Synchronous Up & Down counter using 7476 JK Flip-Flop
.
ii. Mod-N counter using IC 7490 / 7476
iii. Synchronous counter using IC 74192

AIM :
Design and realize,
(i) Mod-N Synchronous Up counter & Down counter using 7476 JK Flip-flop.
(ii) Mod-N counter using IC 7490 / 7476
(iii) Synchronous counter using IC 74192

COMPONENTS REQUIRED:
IC’s 7476, 7400, 7490,74192,7408,7410,7432, Patch Cords & IC Trainer Kit.
THEORY:
Counter is a sequential circuit that counts the no. of clock pulses entering at its
clock i/p. Count represents the no. of clock pulses arrived. A specific sequence of
states appears as counter o/p. It’s basically a set of flip-flops whose state changes
in response to pulses applied at the i/p of the counter.
Counters are of two types:
• Asynchronous or ripple counters.
• Synchronous counters.
Counters in which all the flip-flops are clocked simultaneously are called
synchronous counters.
In Asynchronous counters, flip-flops are not triggered simultaneously. Clock pulse
is applied to first flip-flop and each successive flip-flop is clocked by output of
previous flip-flop.
Counters are also classified as:
• Up counter – counting in the upward direction like 0, 1, 2, 3….. N.
• Down counter - counting in the downward direction like N, N-1, N-2 ……. 3,
2, 1, 0.
The no. of states through which the counter passes before returning to the starting
state is called Modulus of the counter. Each of the count of the counter indicates
the state of the counter.

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An n-bit counter consists of n - flip-flops with 2n states and divides the input
frequency by 2n. Hence called divide-by- 2n counter.
IC 7476 works as a Dual JK Flip-flop chip. It consists of individual J-K, clock, preset,
and clear inputs. The J-K input is loaded into the master while the clock is high and
transferred to the slave on the high to low transition. For normal JK flip operation,
asynchronous inputs - preset and clear are held high.

IC 7476(Dual JK Flip-flop) – Pin details :

Mod-5 Synchronous Up counter:

State transition table:
Present state Next state Excitation inputs
Q3 Q2 Q1 Q3 Q2 Q1 J3 K3 J2 K2 J1 K
1
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 0 0 0 X 1 0 X 0 X
Circuit Diagram :

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Mod-8 Synchronous Down counter:

Excitation table :
Present state Next state Excitation inputs
Q3 Q2 Q1 Q3 Q2 Q1 J3 K3 J2 K2 J1 K
1

1 1 1 1 1 0 X 0 X 0 X 1
1 1 0 1 0 1 X 0 X 1 1 X
1 0 1 1 0 0 X 0 0 X X 1
1 0 0 0 1 1 X 1 1 X 1 X
0 1 1 0 1 0 0 X X 0 X 1
0 1 0 0 0 1 0 X X 1 1 X
0 0 1 0 0 0 0 X 0 X X 1
0 0 0 1 1 1 1 X 1 X 1 X

Functional Diagram :

IC 7490(Decade counter) – Pin details:

MR1 & MR2 – Master Reset inputs.
MS1 & MS2 – Master Set inputs.
Q0, Q1, Q2, Q3 - Flip flop outputs (Q0 –
LSB; Q3 – MSB)
̅CP0 – Clock input for FF0
𝐂P1 – Clock input for FF1

DEPT OF ECE , SIR MVIT 76

 Analog and Digital Electronics Lab [ 21ECL35 ] |

Reset Count Truth Table :

Clock MR1 MR2 MS1 MS2 QD QC QB QA

X H H L X L L L L RESET
X H H X L L L L L RESET
X X X H H H L L H SET TO 9
X L X L COUNT
L X L X COUNT
L X X L COUNT
X L L X COUNT

Decade Counter :
IC-7490 is a TTL MSI decade /BCD counter. It contains four master slave flip flops
and additional gating to provide a divide-by-two counter and a three stage binary
counter which provides a divide by 5 counter. Its operation is as below:
1. The output of MOD-2 is externally connected to the input B which is the clock
input of the internal MOD-5 counter.
2. Hence QA toggles on every falling edge of clock input whereas the output QD,
QC, QB of the MOD-5 counter will increment from 000 to 100 on low going change of
QA output.
3. Due to cascading of MOD-2 and MOD-5 counter, the overall configuration
becomes a MOD-10 i.e. decade counter.
4. The reset inputs R1, R2 and preset inputs S1, S2 are connected to ground so
as to make them inactive.
Functional diagram : Count Table :

QD QC QB QA
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
0 0 0 0

DEPT OF ECE , SIR MVIT 77

 Analog and Digital Electronics Lab [ 21ECL35 ] |

Mod-7/ Divide-by-7 counter using IC 7490:

Functional diagram : Count Table :

QD QC QB QA
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 0 0 0

Mod-5/ Divide-by-5 counter using IC 7490:

Functional diagram : Count Table :

QD QC QB QA
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0

IC 74192(Presettable BCD/Decade Up-down counter) – Pin details:

CPU - Count Up Clock Pulse Input

CPD - Count Down Clock Pulse Input
MR - Asynchronous Master Reset (Clear)
Input
PL - Asynchronous Parallel Load (Active
LOW) Input
Pn - Parallel Data Inputs
Qn - Flip-Flop Outputs
TCD - Terminal Count Down Output (Active
LOW)
TCU - Terminal Count Up Output (Active LOW)

DEPT OF ECE , SIR MVIT 78

 Analog and Digital Electronics Lab [ 21ECL35 ] |

The 74LS192 is Asynchronously Presettable UP/DOWN BCD Decade (8421) Counter.

Separate Count Up and Count Down Clocks are used and in either counting mode
the circuits operate synchronously. Separate Terminal Count Up and Terminal Count
Down outputs are provided which are used as the clocks for subsequent stages
without extra logic, thus simplifying multistage counter designs. Individual preset
inputs allow the circuits to be used as programmable counters. Both the Parallel Load
(PL) and the Master Reset (MR) inputs asynchronously override the clocks.

The Terminal Count Up (TCU) and Terminal Count Down (TCD) outputs are normally
HIGH. When a circuit has reached the maximum count state (9 for the LS192), the
next HIGH-to-LOW transition of the Count Up Clock will cause TCU to go LOW. TCU
will stay LOW until CPU goes HIGH again, thus effectively repeating the Count Up
Clock, but delayed by two gate delays. Similarly, the TCD output will go LOW when
the circuit is in the zero state and the Count Down Clock goes LOW. Since the TC
outputs repeat the clock waveforms, they can be used as the clock input signals to
the next higher order circuit in a multistage counter.

Each circuit has an asynchronous parallel load capability permitting the counter to
be preset. When the Parallel Load (PL) and the Master Reset (MR) inputs are LOW;
information present on the Parallel Data inputs (P0, P3) is loaded into the counter
and appears on the outputs regardless of the conditions of the clock inputs. A HIGH
signal on the Master Reset input will disable the preset gates, override both Clock
inputs, and latch each Q output in the LOW state. If one of the Clock inputs is LOW
during and after a reset or load operation, the next LOW-to-HIGH transition of that
Clock will be interpreted as a legitimate signal and will be counted.

Up-counter (0-9):

QD QC QB QA
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
0 0 0 0

DEPT OF ECE , SIR MVIT 79

 Analog and Digital Electronics Lab [ 21ECL35 ] |

Down-counter (9-0) :

QD QC QB QA
1 0 0 1
1 0 0 0
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1
0 0 0 0
1 0 0 1

Presettable Up counter with Preset value = 5, N = 4 (To count from 5 to 8):

QD QC QB QA
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
0 1 0 1

DEPT OF ECE , SIR MVIT 80

 Analog and Digital Electronics Lab [ 21ECL35 ] |

Presettable Down counter with Preset value = 8, N = 6 (To count from 8 to 3):

QD QC QB QA
1 0 0 0
0 1 1 1
0 1 1 0
0 1 0 1
0 1 0 0
0 0 1 1
1 0 0 0

PROCEDURE:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as per the logic diagram.
4. Verify the Count table and observe the outputs.

RESULT:

DEPT OF ECE , SIR MVIT 81

 Analog and Digital Electronics Lab [ 21ECL35 ] |

EXPERIMENT NO :13
Pseudo random sequence generator using IC7495 :
AIM:
Design Pseudo Random sequence generator using 7495
COMPONENTS REQUIRED:
IC’s 7495, 7486, 7410, Patch Cords & IC Trainer Kit.
THEORY:
A circuit which generates a prescribed sequence of bits in synchronism with the
clock is called as a sequence generator.
To generate a sequence of length ‘S’ it is necessary to use at least ‘N’ number of Flip-
Flops which satisfies the condition S ≤ 2N -1.
DESIGN 1:
Given Sequence = 100010011010111
The given sequence length S = 15, therefore N = 4.

Map
Value Clock QA QB QC QD o/p Y

15 1 1 1 1 1 0
7 2 0 1 1 1 0
3 3 0 0 1 1 0
1 4 0 0 0 1 1
8 5 1 0 0 0 0
4 6 0 1 0 0 0
2 7 0 0 1 0 1
9 8 1 0 0 1 1
12 9 1 1 0 0 0
6 10 0 1 1 0 1
11 11 1 0 1 1 0
5 12 0 1 0 1 1
10 13 1 0 1 0 1
13 14 1 1
14 15 1 1 1 0 1

Y = Qc ⊕ QD

DEPT OF ECE , SIR MVIT 82

 Analog and Digital Electronics Lab [ 21ECL35 ] |

DESIGN 2:
Given Sequence = 1101011

The given sequence length S = 7. The no. of flip-flops required for the given sequence is 3.
But using three flip-flops distinct states are not generated and so the no. of flip-flops is
increased to 4.
Map
Value Clock QA QB QC QD o/p Y

14 1 1 1 1 0 1

15 2 1 1 1 1 0

7 3 0 1 1 1 1

11 4 1 0 1 1 0

5 5 0 1 0 1 1

10 6 1 0 1 0 1

13 7 1 1 0 1 1

DEPT OF ECE , SIR MVIT 83

 Analog and Digital Electronics Lab [ 21ECL35 ] |

PROCEDURE :

1. Check all the components for their working.

2. Insert the appropriate IC into the IC base.
3. Make connections as per the logic diagram.
4. By keeping Mode control = 1, load the inputs A, B, C, D as in truth table 1st
row and give a clock pulse.
5. For count mode make Mode control = 0 and then provide the clock pulse.
6. Verify the truth table and observe the outputs at QA, QB , QC , QD or Y.

RESULT:

DEPT OF ECE , SIR MVIT 84