International Journal of Power Electronics and Drive Systems (IJPEDS)

Vol. 13, No. 1, March 2022, pp. 289~297

ISSN: 2088-8694, DOI: 10.11591/ijpeds.v13.i1.pp289-297  289

A proposed asymmetrical configuration of cascaded multilevel

inverter topology for high level generation

Lipika Nanda, Chitralekha Jena, Arjyadhara Pradhan, Babita Panda

Department of Electrical Engineering, School of Electrical Engineering, Kalinga Institute of Industrial Technology, Odisha, India

Article Info ABSTRACT

Article history: Multilevel inverters are having high demand in high power applications. It
works in medium voltage range. In this converter, for specific time intervals
Received Jul 2, 2021 fewer switches will be conducting so switching loss is also reduced. This
Revised Jan 17, 2022 paper represents overall total harmonic distortion (THD) for different levels
Accepted Jan 25, 2022 and different carrier frequencies. Switching loss, conduction loss of inverter
has been discussed and hence inverter efficiency can be calculated. Phase
displacement pulse width modulation method has been proposed in order to
Keywords: generate pulses. The proposed topology is well presented by its practical
implementation with two current direct sources. All the simulations are
Asymmetric MLI being carried out using MATLAB/Simulink platform to validate the
Bidirectional switch hardware results.
Switching loss
Symmetric MLI
Total harmonic distortion This is an open access article under the CC BY-SA license.
Voltage stress

Corresponding Author:
Lipika Nanda
Department of Electrical Engineering, School of Electrical Engineering
Kalinga Institute of Industrial Technology
Odisha 751024, India
Email: [email protected]

1. INTRODUCTION
Multilevel inverters are highly in demand in high power and medium voltage applications [1]. There
are mainly three different types of multilevel inverters are being focused for industrial applications. Various
topologies had been developed since 1970. It can be interfaced to renewable sources i.e., solar photo voltaic,
wind and fuel gas [2]−[4]. Considering the number of components, high reliability cascaded multi level
inverter (MLI) is being chosen. As the number of level increases, the number of H-bridges also increases [5],
[6]. This makes the system more complicated. By increasing the number of levels in the inverter, the output
voltages have more steps generating a staircase waveform, which has a reduced harmonic distortion.
Depending upon the voltages sources cascaded MLI are classified into two, i.e. symmetrical and
asymmetrical Cascaded MLI [7]. Direct voltages are having different values in asymmetrical Cascaded
multilevel inverter [8]. So, the Inverter achieves higher number of voltage levels compared with symmetrical
configuration for same number of level generation [9], [10]. Several newly developed MLI topologies,
popularly known as “reduced device count (RDC),” have been reported in recent years [11]−[15]. In this
paper a novel topology has been proposed and its asymmetrical configuration has been emphasized to
produce more number of levels. As the number of levels increased the output waveforms become more
sinusoidal in nature. Hence total harmonic distortion (THD) reduces. Phase-shifted and level-shifted are the
two modulation schemes using carrier based pulse width modulation (PWM). Using the same frequency
modulation index in the different modulation techniques, the equivalent switching frequency in the level
shifted technique is significantly lower than in the phased shifted method [16]−[21]. This turns into a better

Journal homepage: http://ijpeds.iaescore.com

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harmonic performance. Hence level shifted PWM techniques are being used. The main features of the
proposed topology is it has reduced number of dc sources and semiconductor switches also.

2. RESEARCH METHODOLOGY
2.1. Existing topology
The existing topology as shown in Figure 1 has two voltage sourcesV1 and V2. It has two capacitors
C1 and C2connected to one voltage source side i.e., V1and seven switches. If the values of V1 and V2 are equal
it is treated asymmetrical configuration. It can produce up to 11 levels with certain voltage combination.
Hence to generate higher levels a new modified topology has been proposed in Figure 2.

S3

S1 S5
C1

D1 D2

V1 S7 LOAD V2

D3 D4
C1 S2 S6

S4

Figure 1. Existing topology

2.2. Proposed topology

The existing topology has been modified and represented in Figure 2 in order to generate higher
levels. As the proposed topology also generates same levels of output voltage and current waveforms in
symmetrical configuration of existing topology, its asymmetrical configuration has been highlighted and
presented in this section. It has two voltage sources i.e.V 1 and V2 and four capacitors i.e.C 1-C4 connected
as shown in Figure 2. It has six unit directional i.e., S1, S2, S3, S4, S7, and S8 and two bidirectional
switches i.e., S5 and S8 in the circuit.

S7

S1 S3
C1 C2

D1 D2 D5 D7

V1 S5 LOAD S6 V2

D3 D4 D6 D8
C1 S4 S2 C2

S8

Figure 2. Modified topology

3. MODES OF OPERATION
In this section different modes of operation of the proposed converter for thirteen level
generation have been represented from mode 1 to mode 13 order to generate first level i.e., Vdc, S5, S2 and
S8 are conducting. Similarly, to generate second level, in mode 2 operation, S6, S4, and S8 are turned on
keeping capacitor C2 charged. In mode 3 operation, C2 discharged by charging capacitor C1.In order to
generate all the six positive levels, the lower switch i.e., S8 is being turned on and to generate all the six
negative levels, switch S7 has been turned on in the Figure 2. Similarly, S1, S7, S3, or S2, S4, and S8 are
turned ON, short circuiting the load, to generate zero level respectively.

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4. SWICHING STATES
This section represents various switching states of the proposed topology. It shows V 1=V/2,
V2=V where Vdc=V/4 which is known as unsymmetrical binary configuration, to generate 13 level sand V1=V,
V2=3 V where Vdc=V/2, which is called as unsymmetrical trinary configuration, to generate 17 levels
respectively. Figure 3 depicts to generate first level i.e., Vdc in thirteen level generations Switches S5, S2, S8
are conducting. To generate second level i.e., 2Vdc in thirteen level generations switches S6, S4, S8 are
conducting. Similarly, six positive levels are generated and six negative levels are generated along with zero
level as represented in different modes of operation in Figure 3 (see Appendix). Table 1 explains the different
switching strategies of the proposed converter. It also depicts about the switches and diodes are conducting
for particular level generation.

Table 1. Different switching strategies

1 3 Levels 17 Levels
Output Conducting switches Conducting Diodes Output Conducting switches Conducting Diodes
Vdc S5, S2, S8 D1, D4 Vdc S5, S2, S8 D1, D4
2Vdc S6, S4, S8 D5, D6 2Vdc S1, S2, S8 NIL
3Vdc S5, S6, S8 D1, D4, D5, D8 3Vdc S8, S4, S6 D5, D8
4Vdc S8, S4, S3 NIL 4Vdc S8, S5, S6 D1, D2, D3, D4
5Vdc S8, S5, S3 D1, D4 5Vdc S1, S6, S8 D5, D8
6Vdc S8, S1, S3 NIL 6Vdc S8, S4, S3 NIL
0 S1, S3, S7 NIL 7Vdc S8, S5, S3 D1, D4
-Vdc S5, S3, S7 D2, D3 8Vdc S8, S1, S3 NIL
-2Vdc S7, S1, S6 D7, D6 0 S1, S2, S3 NIL
-3Vdc S5, S6, S7 D7, D6, D2, D3 - Vdc S7, S3, S5 D2, D3
-4Vdc S2, S1, S7 NIL -2Vdc S7, S3, S4 NIL
-5Vdc S2, S5, S7 D2, D3 -3Vdc S6, S1, S7 D7, D6
-6Vdc S2, S4, S7 NIL -4Vdc S6, S5, S7 D2, D3, D7, D6
х х х -5Vdc S7, S6, S4 D7, D6
х х х -6Vdc S2, S1, S7 NIL
х х х -7Vdc S2, S7, S5 D2, D3
Х х х -8Vdc S2, S4, S7 NIL

5. SIMULATION RESULT ANALYSIS

Various types of the pulse width modulation (PWM) techniques are existing out of which level
shifted PWM technique is being considered because of its many advantages over other conventional
techniques. Figure 4 depicts the simulation diagram of the proposed converter at carrier frequency 10 KHz
and modulation index at 1. S5 and S6 are two bidirectional switches and S1, S2, S3, S4, S7, S8 are unidirectional
switches in Figure 2. Figure 4 represents load voltage and load current wave form at carrier frequency = 10
KHz. Simulation has been carried out for R=10 Ω, L=25 mH at modulation index 1.
Figure 4 (a) indicates output load voltage for 13 level. Average output voltage is 43.85 V at
THD=5.44%. The fundamental cycle has been represented in voltage waveform which is from 0 to 0.02 sec.
Voltage THD also within IEEE standard. Six positive levels, six negative levels of unequal voltage distribution
represented in Figure 4 (a) which shows the asymmetric nature of the proposed multilevel inverter. Figure 4 (b)
indicates output load current for 13 level. Average output load current is 3.45 A at THD = 0.28%. Current THD
is also within IEEE standard.
Fundamental cycle has been represented in voltage waveform which is from 0 to 0.02 sec. Figure 4 (c)
indicates average output voltage is 38.85 V with THD=3.9%. Figure 4 (d) indicates average output current is
3.5A with THD=1.7%. Voltage THD also within IEEE standard. Eight positive levels, eight negative levels of
unequal voltage distribution along with zero level represented in Figure 4 (c) which shows the asymmetric
nature of the proposed multilevel inverter. Figure 4 (d) indicates output load current for 17 level. Average
output load current is 3.5 A at THD=1.7%. Current THD is also within IEEE standard. Figures 4 (a) and 4 (b)
also depict with increase in level generation of the same converter THD is reduced.
Table 2 depicts various losses occurred across the semiconductor switches i.e., at 10 KHz carrier
frequency. Table 2 also describes that conduction loss across the switches is same where, as switching loss
depends on the usability of the switch. Switches S7 and S8 are mostly used when the converter is working to
generate positive levels and negative levels respectively. Hence switching losses are more in S 7 and S8
compared to other switches.
Table 3 depicts about the inverter loss. According to the various researchers [22]−[25] an inverter has
major two types of losses i.e., switching loss which occurs when a switch is conducted (turn on) and also when
it is in off state (turn off), conduction loss when the switch is in conduction state. It has been calculated from
its input power and output power with its voltage THDs and current THDs. Table 3 depicts with increase in
A proposed asymmetrical configuration of cascaded multilevel inverter topology for … (Lipika Nanda)
292  ISSN: 2088-8694

carrier frequency voltage THD enhanced and current THD decreased. At 10 KHz carrier frequency voltage
THD and current THD are found to be minimum. Hence it is the optimum condition of the converter which can
be considered for hardware realization.

(a) (b)

(c) (d)

Figure 4. Simulation results of voltage across load and current for (a) asymmetrical output voltage signals,
(b) asymmetrical output current signal, (c) asymmetrical output voltage signal, and (d) asymmetrical output
current (17 level)

Table 2. Loss calculation at 10 KHz carrier frequency

S1 S2 S3 S4 S5 S6 S7 S8 Total
Switching loss (in W) 0.035 0.0016 0.0012 0.0023 0.05 0.0489 0.06 0.06 0.259
Conduction Loss (in W) 0.0051 0.0052 0.005 0.0052 0.0055 0.0051 0.005 0.045 0.081
Total Loss (in W) 0.0401 0.0068 0.0062 0.0075 0.0555 0.054 0.065 0.105 0.0249

Table 3. Inverter loss and THD across the RL-load

Carrier Frequencies (in KHz) Input power (in W) Output power (in W) Inverter (in W) VTHD ITHD
1 62.26 56.7 8.56 6.36 1.91
3 65.9 57.20 8.7 6.72 1.45
5 66.83 57.6 9.23 6.89 1.05
7 68.11 58.6 9.51 6.98 0.74
10 69.49 59.22 10.27 5.44 0.28

Table 4 depicts voltage THD is reduced and current THD is increased with increase in modulation
index. Hence it is always advised to operate the converter at high carrier frequency and at modulation
index 1. At 10 KHz carrier frequency voltage THD and current THD are found to be minimum at modulation
index 1. Figure 5 represents current THD at various carrier frequencies of the inverter. Current THD has been
reduced as the carrier frequency increases. It indicates that current becomes more sinusoidal at higher carrier

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frequencies. With high modulation index voltage THD reduces which has been observed in Figure 6. Hence
it was advised to operate the inverter at modulation index 1 in order to make the inverter output more
distortion free. Also, in Table 4 it was mentioned clearly.

Table 4. Modulation index verses THD of proposed topology (13 level)

Modulation Index VTHD ITHD
0.6 12.2 0.12
0.7 11.8 0.18
0.8 10.42 0.22
0.9 7.72 0.25
1 5.44 0.28

Figure 5. Current THD vs carrier frequency Figure 6. Voltage THD vs modulation index at 10 KHz

6. HARDWARE REALIZATION
To verify the effectiveness of the proposed topology, experimental results have been presented in
this section. In Figure 7 the entire converter has been considered as a system/Plant to which two sources are
attached. The output of the inverter is PWM controlled and it is controlling the system operation. The block
diagram of hardware which has been designed in research lab-III of Kalinga Institute of Industrial
Technology deemed to be university (KIIT). Circuit is designed using EAGLE software. They are fed to gate
driver circuits. Gate driver circuits have input supply from 230/15 V, 1A step down transformer. Pulses
generated from driver circuits have been fed to each MOSFET IRF540 N gate terminals. Output of the power
circuit is given to the load RL type RO2. Power supply of MOSFET gate driver circuit 3. Gate drive circuit 4.
Main power circuit 5. Output connector from DSPACE. Figure 8 explains the hardware diagram of the
proposed converter where input power supplies are through MOSFET gate driver circuits. MOSFET IRF540
Ns are taken as switches. Six MOSFETS work with six gate driver circuits. DSPACE has been connected to
output waveforms in order to describe the turn off and on state of the inverter.

Figure 7. Overall scheme of the system Figure 8. Overall hardware design of the proposed topology

Figures 9 (a) and 9 (b) depict the two input signals of the inverter. V1 is 10 V and V2 is 5 V. It
shows the asymmetrical configuration of the proposed inverter. Figure 9(c) represents the output signals. It
shows output voltage as 14 V and current as 0.125 A respectively with R=120 Ω, L=50 mH at carrier
frequency 1 KHz and input capacitors of 470 µF each.

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(a) (b)

(c)

Figure 9. Hardware results for (a) input voltage V1=10 V, (b) input voltage V2=5V, and (c) peak voltage and
current across RL-load

7. CONCLUSION
In this research article, the detailed analysis of the proposed asymmetrical cascaded multi level
inverter has been carried out successfully at different modulation index and carrier frequencies. The output
waveforms are more sinusoidal and hence better power quality can be obtained at higher carrier frequencies.
The proposed topology has been fabricated and verified with its simulation result also. Input voltage of 15 V
and output voltage is 14 V which is quite high compared to other existe topologies as cited in the references.
Also THDs if the proposed topology are nominal.

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APPENDIX

Figure 3. Modes of operation

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Figure 3. Modes of operation (continue)

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BIOGRAPHIES OF AUTHORS

Lipika Nanda is working as an assistant professor since 2007 in KIIT

University.Her broad working area is design of power converters, multi-level inverter and its
applications. She is a life member of various professional societies like SESI, ISTE, ISLE,
ISCA, and IEEE. She has 3 Australian patents, 2 book chapters. She has published around 20
papers in international journals and conferences. She can be contacted at email:
[email protected].

Chitralekha Jena had joined in KIIT University as an assistant professor since

2012.She had completed her PhD from Jadavpur University in the year of 2017. Her research
area includes optimization of different power system problems, load frequency control,
renewable energy, and power management of micro grid. She has more than 20 publications in
reputed journals and conferences. She can be contacted at email:
[email protected].

Arjyadhara Pradhan is working as an assistant professor since 2009 in KIIT

University. Her area of interest is Power Electronics, Electrical Drives, and Renewable Energy
Systems. She has 8 Australian patents and 2 Indian patents. She has published around 20
papers in international journals and conferences. She can be contacted at email:
[email protected].

Babita Panda has fifteen years of experience in education. She is working as an

assistant professor in KIIT University. Her area of interest is Power Electronics, Electrical
Drives, Renewable Energy Systems and Control System. She has more than 25 publications in
reputed journals and conferences. She can be contacted at email: [email protected].

A proposed asymmetrical configuration of cascaded multilevel inverter topology for … (Lipika Nanda)