International Journal of Power Electronics and Drive Systems (IJPEDS)

Vol. 12, No. 1, Mar 2021, pp. 121~129

ISSN: 2088-8694, DOI: 10.11591/ijpeds.v12.i1.pp121-129  121

A fast and robust reference current generation algorithm for

three-phase shunt active power filter

Zakaria Chedjara1, Ahmed Massoum2, Patrice Wira3, Ahmed Safa4, Abdelmadjid Gouichiche5
1,2LaboratoireICEPS, Université Djilali Liabes Sidi Bel Abbes, Algérie
3Laboratoire IRIMAS Université de Haute alsace, 4 rue des frères lumière, Mulhouse cedex, France
4,5Laboratoire LGEP, Université Ibn khaldoun, Tiaret, Algérie

Article Info ABSTRACT

Article history: The identification of the reference currents constitutes an important part of
the control of the active power filter. This part requires an accurate
Received Jun 01, 2020 estimation of the frequency, phase, and proper extraction of the load current
Revised Jan 6, 2021 harmonics. This makes the modeling more difficult and requests a rigorous
Accepted 3 Feb, 2021 selection of techniques to be used. For the sake of simplicity, the direct
method is motivated by the need for the simplicity and flexibility than the
existing techniques such as the instantaneous power theory and diphase
Keywords: currents method. However, this method requires a robust phase-locked loop
to extract the unity voltages and a robust controller to estimate the magnitude
Artificial neural network of the source current. To this end, this paper proposes the hybrid phase-
Shunt active power filter locked loop (HPLL) as a good option mainly because 1) it achieves zero
Synchronization phase error under frequency drifts, 2) Fast dynamic response, 3) totally block
the DC offset, 4) From the control point of view, it is a type 1 control system
which results in high stability margin. To the best of authors’ knowledge, the
HPLL has not been used in active power filter yet. Furthermore, a neural PI
regulator is used to estimate the magnitude of the source current. Simulation
results show the efficiency of the proposed technique and illustrate all its
interesting features. For the sake of comparison, the proposed method is
compared to other advanced techniques.
This is an open access article under the CC BY-SA license.

Corresponding Author:
Zakaria Chedjara
Laboratoire ICEPS
Université Djilali Liabes sidi Bel Abbes, Algérie
Email: [email protected]

1. INTRODUCTION
The increasing penetration of distributed generation (DG) sources into the power grid and the
proliferation of domestic non-linear loads have posed serious power quality problems and made the
mitigation task more difficult than before [1]-[8].
Shunt active power filters (SAPF) in low-voltage electrical networks remains one of the most
studied and developed compensation methods. However, the shunt active power filter remains a complex
strategy that needs a thorough and careful study to perform well. Each part in the SAPF control algorithm
performs a very precise task and depends heavily on the performance of the other parts. This dependence
makes the modeling more difficult and requests a rigorous selection of techniques to be used as shown I
Figure 1.
The identification of the current references constitutes an important part of the control of active
power filter. This part requires an accurate estimation of the frequency, phase, and proper extraction of the
load current harmonics. To this end, many identifications have been reported in the literature [9]-[22]; they

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122  ISSN: 2088-8694

can have categorized into the time domain and frequency domain approaches. The frequency domain such as
the discrete Fourier transform (DFT) and recursive DFT [20], the nonlinear least square [21]. However, these
techniques require a computational demanding, and its estimation accuracy is affected by the choice of
sampling frequency and window length, the time-domain techniques such as the instantaneous power theory
(IPT) [4], the diphase current method (DQ) and the direct [2], [22].
All these techniques, regardless of their structure differences, operate satisfactorily under an ideal
condition, in which the grid voltage is free of any noise. However, this situation almost never occurs in
practice due to more and more frequent power quality problems (presence of harmonics, interharmonics, DC
offset and asymmetrical voltage drops).
The most widely used technique is the phase-locked loop (PLL), the conventional types suffer from
three critical limitations: 1) only an approximation but not a true amplitude and phase angle of the positive
sequence component are detected; 2) the detected positive sequence voltages are distorted and unbalanced; 3)
the dynamic response of the system is significantly affected [23].
To deal with this problem, some efforts for designing more efficient PLLs methods have been made
recently. A review of recent advances is given in [23]. These efforts improve the filtering capability and
disturbance rejection ability of PLLs by including different filters, the moving average filter (MAF), the
Delayed Signal Cancelation operator (DSC), Second-Order Generalized Integrator (DSOGI) and others.
These techniques suffer from one or more on the following shortcomings: 1) slow dynamic response, 2)
inefficiency under large frequency drifts and highly distorted source voltage, 3) are less attractive to deal
with the DC-offset problem, 4) require a deep stability analysis.
Furthermore, the IPT and DQ require a low-pass or high-pass filter to extract the fundamental or the
harmonic components. However, these kinds of filters must be designed carefully in order to avoid erroneous
compensation reference signals during the SAPF operation. For the sake of simplicity, the direct method
requires fewer calculations (does not necessitate pre-processing, such as high-pass and low-pass filtering, in
order to separate the fundamental and the harmonic components) than IPT, DQ and ensures better accuracy
and robustness.
To address these issues, this paper proposes the hybrid synchronous/ stationary filtering technique
(HPLL) with the direct method [24] as good option mainly because, 1) it achieves zero phase error under
frequency drifts, 2) Fast dynamic response, 3) totally block the DC offset, 4) From the control point of view,
it is a type 1 control system which results in high stability margin. To the best of authors’ knowledge, the
HPLL has not been used in active power filter yet. Besides, a neural regulator to enhance the dynamic of the
DC bus voltage.

Figure 1. Shunt active power filter control

Int J Pow Elec & Dri Syst, Vol. 12, No. 1, March 2021 : 121 – 129
Int J Pow Elec & Dri Syst ISSN: 2088-8694  123

2. REFERENCE CURRENT GENERATION USING THE DIRECT METHOD

In this work, the direct method has been adopted as shown in Figure 2 [2]. There are three blocks for
this control strategy. The first block estimates the maximum currents of the source using a proportional
integrator (PI) with a neural approach. These currents take care of the active power required by the active
filter and the losses generated in the inverter. Instantaneous reference source currents are evaluated by
multiplying the estimated maximum currents by the unit voltage vectors. The second block determines the
reference currents of the filter which are obtained by subtracting from the reference source currents, the
instantaneous load currents and compared to the currents of the filter. The third block gives the errors which
are used through a PWM (pulse width modulation) to generate control signals for the active filter.

Figure 2. Identification structure of reference currents with the direct method

2.1. Problem formulation

With the direct method, the identification of the reference currents depends on the phase estimation
algorithm. A phase-locked loop is the most widely used technique to recover a balanced system.Figure 2
illustrates the conventional SRF-PLL (the synchronous reference frame). Since conventional SRF-PLL is the
basic structure for implementing almost all advanced PLLs, a brief description of its operating principle and
properties is first presented [23].

Figure 3. SRF-PLL with LPF

In conventional SRF-PLL, Clarke and Park's transformations are applied to voltage signals to
transfer them to the synchronous reference frame (dq). The resulting dq axis signals contain the phase and
amplitude error information. The signal containing the phase error, here Vq, passes through the LF, which is
an integral proportional regulator (PI). The cooperation of this regulator and the VCO guarantees a zero
average phase tracking error at nominal and non-nominal frequencies in steady state. Note that the unit vector
generated by the VCO [i.e., sin and cos] is used by the PD (park transformation) to generate the phase and
amplitude error information. Also note that the PI controller output and the d-axis signals are estimates of the
frequency and magnitude of the grid voltage, respectively. The d-axis signal is transmitted to a low-pass filter
in order to reject/attenuate the possible disturbances and accurately estimate the magnitude of the grid
voltage. According to the ref, the transfer function of SRF-PLL with additional LPF is (1):

A fast and robust reference current generation algorithm for three-phase shunt active … (Zakaria Chedjara)
124  ISSN: 2088-8694

Vˆ+ k
=
V ( s − jc ) + k
(1)

Figure 4 shows the frequency response of (5) for ω=314 rad/s and three values of k. In these plots, it
can be noted that the negative frequency is interpreted as a response to the negative sequence vector signal.
The frequency response is asymmetric around the zero and it provides a unit gain with zero-phase shifts at
the fundamental frequency of positive sequence, while offering some level of attenuation to the same
negative sequence frequency. The dynamic response depends on the parameter k.

Figure 4. Bode diagram of the. SRF-PLL with LPF

As mentioned before this technique suffers from the following shortcomings:

1) Only an approximation of the detected amplitude and phase of the positive sequence components.
2) Under greatly unbalanced and distorted conditions: The detected fundamental component is unbalanced
and distorted.
3) The dynamic response is significantly reduced. These shortcomings are the main motivation behind
developing the advanced techniques.

2.2. DC bus voltage

PI regulators generally achieve a good compromise between performance and cost, that is why these
kinds of regulators are used in 80% of industrial regulation systems [25]-[30]. Despite this, the determination
of the parameters (P, I) is not obvious and fundamentally not optimal. To deal with these challenges, we
propose the use of a neural network learning capability to determine these parameters. Figure 5 shows the
principle of this technique where an ADALINE with two weights is used: 𝜔0 as the proportional parameter
and 𝜔1 as an integral parameter. These weights relate the errors e(k) and e(k-1) at time k and k-1 to the
output in the linear combination. The error is defined between the reference signal delivered to the regulator
and the measured output of the system to be controlled.

Figure 5. The neural PI regulator

Int J Pow Elec & Dri Syst, Vol. 12, No. 1, March 2021 : 121 – 129
Int J Pow Elec & Dri Syst ISSN: 2088-8694  125

3. THE H-PLL TECHNIQUE

A schematic diagram of this technique is shown in Figure 6. From the control point of view, this
technique is a type1 since it characterized by having only one integrator in its control loop and this allows a
fast-dynamic response and high stability margin. The key parts of this structure are the MAF in dq space and
DSC in αβ space and this is the reason why it referred to the hybrid PLL.

Figure 6. The H-PLL structure

3.1. MAF
A MAF is good alternative to make the SRF immune to the unbalance, harmonic, and DC offset.
The MAF described as (2):

1 − e−Tw s
GMAF ( s) =
Tw s (2)

Where Tw is the length of the MAF window, the MAF passes the DC Component and completely
blocks the frequency components of multiple integers from (1/Tw) in hertz. This is the reason why the MAF
is sometimes called (quasi-ideal LPF). This selection of Tw is a tradeoff between excellent filtering
capability and fast dynamic response. For example, Tw=T removes all harmonics and DC offset but
unfortunately, this selection results in slow dynamic response. Besides, to achieve fast dynamic response
selecting Tw=T/2. In this case, however, the MAF cannot reject the DC offset [24].

3.2. DSC
To solve this problem, we use the operator (DSC) in the PLL input [24]. DSC is a finite impulse
response filter which can be defined in the Laplace domain as

2 T
j − s
1+ e n
e n
 DSCn (s) =
2 (3)

Where n is the delay factor, and it should be determined based on which components are to be
removed. According to ref, selecting n=2 to remove the DC component.

4. SIMULATION RESULTS
The proposed algorithm is simulated using Matlab/Simulink. Three scenarios are investigated: ideal
source conditions, unbalanced and distorted, DC offset in order to analyze the performance and the
effectiveness of the proposed algorithm. Since the MCCF-PLL is mathematically equivalent and perform
similarly under different operating conditions to some advanced Type 2 PLLs such as decoupled double SRF
(DDSRF), (DSOGI), multiple reference frame PLL (MRF-PLL) and the frequency adaptive discrete filter
(FADF) with two stages [30], it has been used as a reference in evaluating the proposed technique.

4.1. Ideal source voltage

This scenario will serve as a reference for two other scenarios. Figure 7 shows the behavior of the
active power filter under ideal source voltage condition. Under this condition, the active power filter lowered
the THD from 28% to 1.71% with the proposed scheme and 1.89% with the MCCF-PLL. Besides, it can be
A fast and robust reference current generation algorithm for three-phase shunt active … (Zakaria Chedjara)
126  ISSN: 2088-8694

seen that, the proposed scheme is fast compared with MCCF-PLL, to be more exact the H-PLL have a
settling time about 1 cycle while, the MCCF-PLL have 2 cycles. In addition, the neural regulator enhances
the DC bus voltage dynamic.

(a)

(b)

(c)

(d)

(e)

Figure 7. Simulation results under highly unbalanced source voltage: (a) load current and its frequency
spectrum, (b) source current and its frequency spectrum with the MCCF-PLL, (c) source current and its
frequency spectrum with the H-PLL, (d) DC bus voltage with the neural regulator, (e) DC bus voltage with
the classical PI regulator

4.2. DC offset condition

In this scenario, a DC component of phase (a) and phase (c) +50v, -50v is added to the grid voltages.
Figure 8 shows the behavior of the active power filter under DC offset condition. Under this condition, the

Int J Pow Elec & Dri Syst, Vol. 12, No. 1, March 2021 : 121 – 129
Int J Pow Elec & Dri Syst ISSN: 2088-8694  127

active power filter had good performances only with the proposed scheme with a source current THD of
1.89%. It can be noted that the proposed algorithm is largely better than the MCCF-PLL.

(a)

(b)

(c)

(d)

Figure 8. Simulation results under DC offset: (a) source current and its frequency spectrum with the MCCF-
PLL, (b) source current and its frequency spectrum with the H-PLL with neural regulator, (c) DC bus voltage
with MCCF-PLL, (d) DC bus voltage with H-PLL and neural regulator

4.3. Distorted source voltage condition

In this scenario, the source voltages are unbalanced and distorted with the THD of 10.31%. Figure 9
shows the behavior of the active power filter under unbalanced and distorted conditions. Under this
condition, the two schemes converge to similar results.

4.4. Performance comparaison

This subsection provides a comparative study of the proposed H-PLL and the neural regulator to
extract the magnitude source of the current with the MCCF-PLL; the methods are compared according to the
following standpoints: Unbalance robustness, frequency adaptability, distortions, DC offset, the dynamic of
source current and DC bus voltage.
According to Table 1 and Table 2, the proposed H-PLL technique with a neural regulator is
recommended as a good alternative mainly because it effectively rejected the unbalance, DC offset, and the
harmonic component and offers a satisfactory compromise between the dynamic response, filtering
capability.

Table 1. THD under circumstances Table 2. Comparison of transient responses

THD% H-PLL MCCF-PLL Settling time H-PLL MCCF-PLL
Ideal condition 1.71% 1.89% Frequency step change <2 cycles [24] 2.5 cycles [28]
Unbalance and distorted 3.48% 2.88% Source current 1 cycle 2 cycles
DC-offset 1.71% 19.41% DC bus voltage 2 cycles 3 cycles

A fast and robust reference current generation algorithm for three-phase shunt active … (Zakaria Chedjara)
128  ISSN: 2088-8694

(a)

(b)

(c)

Figure 9. Simulation results under distorted conditions: (a) source voltage and its frequency spectrum, (b)
source current and its frequency spectrum with the H-PLL, (c) source current and its frequency spectrum
with MCCF-PLL

5. CONCLUSION-
In this paper the H-PLL synchronization technique to enhance the performance of APF under
adverse grid conditions with the direct method is presented. The main advantage of the proposed method is
the fact of being able to work under adverse grid conditions with the fast-dynamic response and with high
stability margin. The neural PI regulator is used to enhance the dynamic of the DC bus. Simulation results
have been obtained and show that the proposed H-PLL with a neural regulator is a very suitable for shunt
active power filter.

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A fast and robust reference current generation algorithm for three-phase shunt active … (Zakaria Chedjara)