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Artinoor AdVD - Course Handout 2020

Analog Vlsi design

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39 views2 pages

Artinoor AdVD - Course Handout 2020

Analog Vlsi design

Uploaded by

Abhishek abhishek
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Course Plan for MOS Circuit Design

(CDAC Noida)

Course Code No.: MEVS-605 Semester-First


Subject: Advanced VLSI Design.
Course-coordinator: Ms. Kiran Walia
Course Instructor: Dr. Arti Noor.
Lab Instructor: Ms Isha Gupta
Duration of Semester: Dec.-Apr 2020

Unit 1
Introduction [T1, T2]: Basic principle of MOS transistor, Introduction to large signal MOS models (long
channel) for digital design.
MOS Circuit Layout & Simulation and manufacturing: scaling, MOS SPICE model and simulation,
CMOS layout: design rules, Transistor layout, Inverter layout, NMOS and CMOS basic manufacturing
steps.

Unit 2
The MOS Inverter [T1]: Inverter principle, the basic CMOS inverter, transfer characteristics, logic
threshold, Noise margins, switching characteristics, Propagation Delay, Power Consumption.
Combinational MOS Logic Design [T1]: Static MOS design, Ratioed logic, Pass Transistor logic, complex
logic circuits.

Unit 3
Sequential MOS Logic Design [T1]
Static latches, Flip flops & Registers, Dynamic Latches & Registers, CMOS Schmitt trigger, Astable
Circuits. Memory Design: ROM & RAM cells design.
Dynamic MOS design [T1]: Dynamic logic families and performances. Clock Distribution [T1] [T2]
Input and Output Interface circuits.

Unit 4
Subsystem design [T2, R1]
Design styles, design concepts: Hierarchy, Regularity, Modularity, Locality. CMOS Sub system design:
Adders, Multipliers.

Text Books

[T1] S. Kang & Y. Leblebici “CMOS Digital IC Circuit Analysis & Design”- McGraw Hill, 2003.
[T2] J. Rabaey, “Digital Integrated Circuits Design”, Pearson Education, Second Edition, 2003.

Reference Books

[R1] Neil Weste and David Harris :“ CMOS VLSI design” Pearson Education 2009.

LAB TOOLS
Mentor Graphics IC Station.

Internal Marking Scheme


Assignments and Attendance in Class: 10 Marks
Test-1 15 marks
Internal Total marks 25 Marks
Detailed Weekly Schedule

Dates Topics
Week 1 Overview of VLSI design, currents trends and problems, Basic properties of
semiconductors.
Week 2 MOS system under external biasing condition, Calculation of surface
potential, depletion width and electric field. Structure and operation of MOS
transistor, threshold voltage expression, I-V curve of MOSFET, Scaling
Week 3 Small geometry effects on MOST, MOSFET capacitances, MOS Fabrication
Week 4 Inverter analysis, Inverter switching characteristic, noise margins.
Week 5 Inverter Delay-time definition, estimation of interconnect parasitic,
calculation of power dissipations.
Week 6 MOS combinational logic circuit design, CMOS logic circuits, Complex
logic circuits, transmission gates.
Week 7 Test-1,
Week 8 Behavior of bistable elements, SR latch, Clocked latch, flip flop circuits.
Week 9 Basic principles of pass transistors, voltage bootstrapping, synchronous
dynamic circuits.
Week 10 DRAM , SRAM, Nonvolatile memory design, flash memory.
Week 11 Interconnection and on-chip clock generation, distribution of clock and
related problems.
Week 12 Concepts: Hierarchy, Regularity, Modularity, Locality. CMOS Sub system
design: Adders.
Week 13 CMOS Sub system design: Adders.
Week 14 Multiplier

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