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Rram Us20170025605a1

The gate of the access transistor of a 1 transistor 1 resistor (22) Filed: Sep. 26, 2015 (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence Related U.S. Application Data ofa Voltage applied across the 1T1R cell (e.g., via the bit line), (63) Continuation of application No. 147483.359, filed on the RAM memory element with from a high CS1S Sep. 11, 2014, now Pat. No. 9,153,321, which is a tance to a lower resistance. As

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17 views

Rram Us20170025605a1

The gate of the access transistor of a 1 transistor 1 resistor (22) Filed: Sep. 26, 2015 (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence Related U.S. Application Data ofa Voltage applied across the 1T1R cell (e.g., via the bit line), (63) Continuation of application No. 147483.359, filed on the RAM memory element with from a high CS1S Sep. 11, 2014, now Pat. No. 9,153,321, which is a tance to a lower resistance. As

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ken901007
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TATE A ‘US 2017002560581 cu») United States 2) Patent Application Publication co) Pub. No.: US 2017/0025605 Al Park et al. (43) Pub. Daté Jan, 26, 2017 oy Publication Classification (1) Inc. OIL Aso (2006.01) MOU 27724 (200501), (2) US.CL. CPC sn HOI 45/1246 (2013.01), HOLL 45/085 (2013.01): Oz. 48/1233 (2013.01): HOLL 45/1266 2013.01); HOIL 45/146 (2013.01) HOLL 45616 (201301), HOIL 272463 Gor301) (71) Applicants:Seoul National University R&:DB FOUNDATION, Seou! (KR); Gachon Industry-Academie ‘oundation, Seongnam-si 7) ABSTRACT A resistive random access memory device is provided with ‘tunneling insulator layer between a resistance change layer oul (KR) ‘and a bottom electrode. Thus, it is possible: to raise the ‘election (ono!) ratio by the current of a direct tuaneling indeed by low voltage in the unselected eel and the eurent ‘of'an F-N tunneling induced by high voltage in the selected cell, to efficiently suppress the leakage current in the read (72) Inventors: Byung-Gook Park, Seoul (KR) (21) Appl. Now 18/182,640 (22) Filed: Jun, 15, 2016 ‘operation, to make a Tow current operation less WA level by ‘controling the thickness ofthe tunneling insulator layer, and G0) Foreign Application Priority Data tobe simultaneously fabricated together with circuit devices by forming the bottom electrodes (word lines) with a semi- Jul, 20,2015 (KR) 10-2015-0102690 conductor material Patent Application Publication Jan. 26,2017 Sheet 1 of 7 US 2017/0025605 A1 FIG. 1 Top electrode [M] Switching layer [I] Bottom electrode [M] FIG.2 Initial | | Forflng Vv ot i Conducting filament Patent Application Publication Jan. 26,2017 Sheet 2 of 7 US 2017/0025605 A1 FIG. 3(A) ‘RES! 3 HRS 38} ft wtf Compliance LRS Voltage FIG. 3(B) a | Compliance Voltage Patent Application Publication Jan. 26,2017 Sheet 3 of 7 US 2017/0025605 Al FIG4 Word Lines FIG. 5 RRAM+Selector 1/2aex0 VRE v Patent Application Publication Jan. 26,2017 Sheet 4 of 7 US 2017/0025605 A1 FIG.6 FIG.7 Patent Application Publication Jan. 26,2017 Sheet Sof 7. US 2017/0025605 AL FIG.8& 30 20 —10 FIG. 9(A) FIG. 9(B) 30 — 20 forf=a 40 < Mt * SiN, Te 10 Patent Application Publication Jan. 26,2017 Sheet 6 of 7 US 2017/0025605 Al FIG. 10(A) FIG. 10(B) Low voltage High voltage 32 TE 40 TE }~__ 40 SiN lz 30 [sin E |.__-39 Ran No SiOz T 7~—20 [Si0Q, FN [20 [BE p10 BE 10 FIG.11 Current [A] ‘Sif 7.500) sip (Sam)i0, 2 5rm) Patent Application Publication Jan. 26,2017 Sheet 7 of 7 US 2017/0025605 Al FIG, 12(A) Current [A] FIG. 12(B) L_ 0.003} Si,N, (Snm) 20x10 r= iN,onm) of | 6 ----= 0x F = 0.002 +o 1.5x10% a L a oe r -\10x108 & L 5 E 3S i L Lj 0.0 05 Voltage [V] US 2017/0025605 AI DEVICE EMBEDDING TUNNEL, INSULATING LAYER AND MEMORY ARRAY USING THE SAME AND FABRICATION METHOD THEREOF CROSS-REFERENCE TO RELATED APPLICATION 10001] This application claims priority to Korean Patent Application No. 10-2015-0102600 filed on Jul 20, 2015, under 35 U.S.C. 119, the entire contents of which are hereby ‘inconporated by referene. BACKGROUND [0002] 1. Field ofthe Invention [0003] The present invention relates toa resistive swite- ing memory, i.e, a resistive random access memory (RRAM) devi, and more particularly 10 a resistive random socess memory device embedding a tunnel insulating layer and a memory array using the same and fabrication method thereof, 10004} 2. Description of the Related Art 10005] Today, NAND flash memory technology leads the markets of mass storage devices by scaling down contins- ‘ously. However, since the size of device is scaled down, below 20m, some reliability problems ae recently coming ‘out, Thus, various next generation non-volatile memories have boon suggested and studied actively for replacing the NAND flash memory technology: 10006) Among them, RRAM having a simple structure is ‘advantageous for scaling dowa and basically has a material ‘composition of MIM (mota-insulator-metal) as shown in FIG. I. The switching operation of RRAM is divided into 3 steps. As shown in FIG. 2, it is consisted of a forming process that forms conductive filaments in an initial tate t0 be a low resistance state, a reset operation that euts off the ‘conductive filaments 10 inerease the resistance and a set ‘operation that reproduce the conductive filaments 10 ‘decrease the resistance. The forming process is an initial ‘operation ofthe set operation aod noods higher voltage tha the others. 10007] In the conventional structure of RAM, because the interface between s metal and an insulator i plane, whea voltages. are applied to both ends, the electric field is Uniformly distibuted So, in the MIM structure, because the ‘conductive filaments produced during the forming and set ‘operations are formed at random places, itis dificult t0 precisely control and shows a high eset current. Especially, ‘unipolar RRAM that operates as shown in FIG. 3A) is, disadvantageous in commercialization due 10 uneven Switching parameter distabution sand high reset curren. ‘Thus, recently, a bipolar RRAM that operates as shown in FIG. 3(B) is more interested, [0008] "In memory atray using RRAM, there isan array ‘method, as shown in FIG. 4, chat top and bottom electrodes are vertically erssed to each other to use as word and bit Tines, respectively: For reading data, a V/2 method is used. Namely as shown in FIG. 4, when a cell 300 i solectod t0 be read, V and 0 voltages are applied toa bitline 200 as 2 top electrode and a word line 100 as a bottom electrode, respectively: And 1/2 V is applied to the other Tines for applying only 1/2 V between the top and bottom electrodes ‘of cells 410, 420, 480 and 440 commonly connected to each, Jan. 26, 2017 ofthe ines 100 od 200 of the cel 300 selected 1 be read. However wou the cel 300 selected tobe read is FIRS (high resistance state), bevase nt only cute (a a slid Tine shown in FIG. 4 of the solved cell, but also leakage currents (a broken lines shawn in FIG, 4) of the adjacent cells 430 and 440 are sense oper, the leakage currents ‘ofthe adjacent cols 430 and 40 ae to ho eauses of an er fn a reading operation and restriction im an aay size {0009} ‘To overcome the leskage curent problems ofthe ajceat cells as shown ia FIG. i operated as he V2 rethod afer changing the electrical propery of a memory device by connceting each bipolar RRAM cel wih bipolar Selector” Accordingly, becatse an additonal proces is ecded to form the additional bipolr seletors, the com. plexity of the fabricating process inereased and the thickness ofthe etic device is thickly increased So, there js a disadvantage in forming s high imegaton [0010] To overcome the above disadvaataye, Korean Pate ent No, 10-1257368 discloses an attempt to simultancous!y form a resistance change layer and a threshold switching layer for subsiting # switching device. According the above patent, the bottom eletrode is fomaed of platinum (@, the tp eloctode ie formed of transition metal sch as tungsten (W). a phase-change loyer between the electrodes Js armed of transition mital oxide sich as niobium oxide (8.0, vatadum oxide (V,0,,.) Ti, Fe, Nite. Whe oxygen fons within the phase-change layer are moved to the top eeviade by applying a voltage to bath electrodes, fom the botiom elsciods, the phase-change layer is materially chagd into state with oxygen vaeaneies to grow and form the threshold saitching layer baving 4 conductive propery Induced by eat energy in ese oF applying a higher valtoge than the predetermined voltage and inthe top electrode the resistance change layer is Tormed by oxidaon reaction Thu it hs technical features simallancously forming 0 Jayers having cifeent characterises each oer by a single Iorming process {0011} However, because the Patent No. 101257365 also

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