UNIT-4

Stacks and Subroutines

Stacks:

A stack is a LIFO data structure which is employed in the RAM area where Programmers uses the stack

to store temporary data and addresses and the microprocessors use the stack to execute subroutines.

The 8085 has a 16-bit register known as the Stack Pointer. The function of the stack pointer is to hold

the starting address of the stack. This address can be decided by the programmer.

The stack operates on the Last In, First Out (LIFO) principle. The location of the most recent data on the

stack is known as the TOP of the stack. The stack pointer always points to the top of the stack.

Contents can be stored in the stack using the

PUSH instruction and can restore the contents by using the instruction POP
.
MNEMONIC DESCRIPTION

LXI SP, 16-bit Load the stack pointer register with a 16-bit address.

PUSH Rp Copies the contents of the specified register pair on the stack

POP Rp Copies the contents of the top two memory locations of the stack into the specified register pa

PUSH and POP Operation in 8085

PUSH Rp

This is a 1-byte instruction. This instruction copies the contents of the specified register pair on the

stack as described below:

• The stack pointer is decremented and the contents of the higher-order register are copied to
the location shown by the stack pointer register.
• The stack pointer is again decremented and the contents of the low-order register are copied
to that location.
POP Rp

This is a 1-byte instruction. This instruction copies the contents of the top two memory locations of the

stack into the specified register pair.

 • First, the contents of the memory location indicated by the stack pointer register are copied
into the low-order register and then the stack pointer register is incremented by 1.
• The contents of the next memory location are copied into the high-order register and the
stack pointer register is again incremented by 1.

Example

LXI SP,
LXI H,
PUSH H
Delay Counter
POP H
• The instruction
LXI SP, will initialize the stack pointer with the address of 2099H.
• LXI H, will initialize or load HL register pair with data so H = 42
and L = F2
.

• After the execution of PUSH H instruction the stack pointer is decreased by one to
and the contents of the H register are copied to memory location
.
• The stack pointer is again decreased by one to and the contents of the L register are
copied to memory location
.

Contents
of Stack and Registers After PUSH Operation
• After the execution of POP H instruction, the contents of the top of the stack location shown
by the stack pointer are copied in the L register and the stack pointer is increased by one
to
.
 • The contents of the top of the stack are copied in the H register and the stack pointer is
increased by one.
• The contents of the memory locations and
are not destroyed until some other data bytes are stored in these locations.

Contents of Stack and Registers After POP Operation

Subroutines:

A subroutine is a set of instructions that will be used repeatedly in different locations of the program.
Instead of repeating the same instructions several times, they can be combined into a subroutine that is
called from various locations. A subroutine in Assembly language can exist anywhere in the code.
However, It is a common practice to separate subroutines from the main program.

Subroutine Call and Program Transfer

The 8085 microprocessor has two instructions to implement subroutines. The CALL instruction is used
to redirect program execution to a subroutine. The RET instruction is used to return the execution to the
calling routine. They are described in the following table.

MNEMONIC DESCRIPTION

3-byte instruction.
CALL 16-bit address
Jumps unconditionally to the memory location specified.

1-byte instruction.
RET
Unconditionally returns from the subroutine.

When the CALL instruction has been executed the contents of the program counter is saved to the top
of the stack. This return address is retrieved from the stack when the RET instruction is executed.
 Basic Interfacing Concepts

Input Output Interfacing 8085 Microprocessor:

Any application of a microprocessor-based system requires the transfer of data between external
circuitry to the microprocessor and microprocessor to the external circuitry. User can give information
to the microprocessor using keyboard and user can see the result or output information from the
microprocessor with the help of display device. The transfer of data between keyboard and
microprocessor, and microprocessor and display device is called Input Output Interfacing 8085
Microprocessor or I/O data transfer. This data transfer is done with the help of I/O ports.

Input Port :

It is used to read data from the input device such as keyboard. The simplest form of input port is a
buffer. The input device is connected to the microprocessor through buffer as shown in the Fig. 4.28.
This buffer is a tri-state buffer and its output is available only when enable signal is active.

When microprocessor wants to read data from the input device (keyboard), the control signals from the
microprocessor activates the buffer by asserting enable input of the buffer. Once the buffer is enabled,
data from the input device is available on the data bus. Microprocessor reads this data by initiating
read command.

Output Port :

It is used to send data to the output device such as display from the microprocessor. The simplest form
of output port is a latch. The output device is connected to the microprocessor through latch as shown
in the Fig. 4.29.
When microprocessor wants to send data to the output device, it puts the data on the data bus and
activates the clock signal of the latch, latching the data from the data bus at the output of latch. It is
then available at the output of latch for the output device.

A simple block diagram of I/O interface The basic input output device is a set of three-state buffers.
The basic output device is consisting of data latches. The term IN presents for moving data from the
I/O device into the microprocessor, and the term OUT presents for moving data out of the
microprocessor to the I/O device. The three-state buffers are used to construct an 8-bit input port. The
external TTL logic data are connected to the input of the buffers. The output of the buffers connected
to the data bus. While the microprocessor executes an IN instruction then the I/O port address is
decoded for generating the logic 0 on SEL. Logic 0 placed on the output control inputs (1G and 2G) of
the 74ALS244 buffer causes the data input connections (A) to be connected to the data output (Y)
connections. If a logic-I is place on the output control inputs of the 74ALS244 buffer, the device enters
the three-sate high impedance mode that effectively disconnect the switches from the data bus. The
basic input circuit is essential for appearing any time that input data are interfaced to the
microprocessor

I/O Peripherals Interface :

• The objective of Interfacing I/O peripherals:

-is to obtain information or results from process.
-to store, process or display
• The instructions IN and OUT perform this operation.
• The following examples shows the process of instruction

2050 D3 OUT 01H

2051 01
I/O Peripherals Interface

• Figure 2 shows one of the way to decode address lines to obtain output address 01 H

. • The line address A 7 -A 0 is connected to eight NAND gates function as decoder.

• The line A 0 is connected directly, A 7 -A 1 are connected through inverter gates.

• The G 2 gate is combined with gate G 1 and IO/W control signal to generate select signal I/O
whenever both signals are active low.

Multiple output address, I/O interface (Partial decoder):

• Figure 2 have shown the technique to decode I/O output address in absolute decoding technique.

• There is another technique which is cost saving - partial decoding.

• This technique gives the flexibility to user as to use more than one addresses to one output or input
device.
Multiple output address, I/O interface Figure 3: Partial Decoding

Multiple output address, I/O interface

• The address lines A 1 and A 0 are unused.

• Depending on the logic input given at address lines A 1 and A 0;

– the output addresses: 00 h, 01 h, 02 h or 03 h, which refer to the same output device.

• The multiple address is normally used in a small system;

– OK if those addresses are not being used by any other system, input or output devices.

Input Interface

• The assembly instruction for that circuit in fig. 4 is IN FFH.

• Note: FFH = 1111 binary • The line address is decoded using NAND gates.

• When address A 7 -A 0 is active high (FFH), the output of NAND gate will have an active low signal
and then combined with control signals IOR at G 2.
• Suppose the μp run the IN FFH instruction, data at DIP switches will be placed at data bus and copied
to accumulator.

Input Interface Figure 4: IN FFH

I/O interface using decoder

• Circuit in figure 5 decode input and output device at once using 3 -to-8 decoder and four input NAND
gates.

• The address lines A 2, A 1 and A 0 are used as inputs to decoder, and the remaining line address A 7
ke A 3 is used to enable the decoder chip.

• The decoder has eight outputs;

therefore, we can use the decoder to address eight kinds of input and output devices.
I/O interface using decoder Figure 5
Seven segment display output interface. Figure 6

Seven segment display output interface

• Fig 6 shows two different type of 7 -segment display; common cathode and common anode.

• 7 -segment display consists of a few LEDs and are arranged physically as shown in figure 7 a.

• It has seven segment from A to G that normally connected to data bus D 0 to D 6 respectively.

• If decimal point is used, D 7 will be connected to DP; and left unconnected if it is unused.
Seven segment display output interface. Figure 7

Seven segment display output interface.

• Fig. 7 shows the example to interface seven segment display and address decoder with an address of
FDH.

• The common anode display is used therefore 0 logic is needed to activate the segment. • Suppose to
display number 4 at seven segment display, therefore the segment F, G, B and C have to be activated

. • Follows are the instructions to execute it: –

MVI A, 66 H

OUT FDH

Data lines: D7 D6 D5 D4 D3 D2 D1 D0

Segments: NC G F E D C B A

Bits: X 1 1 0 0 1 1 0 = 66 H
Absolute Vs Partial Decoding:
 Interrupts in 8085

Interrupts are the signals generated by the external devices to request the microprocessor to perform a
task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
Interrupt Service Routine (ISR)
A small program or a routine that when executed, services the corresponding interrupting source is
called an ISR.

Interrupt are classified into following groups based on their parameter −

• Vector interrupt − In this type of interrupt, the interrupt address is known to the
processor. For example: RST7.5, RST6.5, RST5.5, TRAP.

INTERRUPT VECTOR ADDRESS

TRAP (RST 4.5)

24 H

RST 5.5 2C H

RST 6.5 34 H

RST 7.5 3C H

• Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the
processor so, the interrupt address needs to be sent externally by the device to perform
interrupts. For example: INTR.
• Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing some
instructions into the program. For example: RST7.5, RST6.5, RST5.5.
• Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by
writing some instructions into the program. For example: TRAP.
• Software interrupt − In this type of interrupt, the programmer has to add the instructions
into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e.
RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
• Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e.
TRAP, RST7.5, RST6.5, RST5.5, INTA.
TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts. By default, it is enabled
until it gets acknowledged. In case of failure, it executes as ISR and sends the data to backup memory.
This interrupt transfers the control to the location 0024H.
RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts. When this interrupt is
executed, the processor saves the content of the PC register into the stack and branches to 003CH
address.
RST 6.5
It is a maskable interrupt, having the third highest priority among all interrupts. When this interrupt is
executed, the processor saves the content of the PC register into the stack and branches to 0034H
address.
RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor saves the content of the PC
register into the stack and branches to 002CH address.
INTR
It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by resetting
the microprocessor.
When INTR signal goes high, the following events can occur −
• The microprocessor checks the status of INTR signal during the execution of each
instruction.
• When the INTR signal is high, then the microprocessor completes its current instruction
and sends active low interrupt acknowledge signal.
• When instructions are received, then the microprocessor saves the address of the next
instruction on stack and executes the received instruction.
Note − INTA is not an interrupt, it is used by the microprocessor for sending acknowledgement. TRAP
has the highest priority, then RST7.5 and so on.
Priority of Interrupts –

When microprocessor receives multiple interrupt requests simultaneously, it will execute the
interrupt service request (ISR) according to the priority of the interrupts.
SIM and RIM instructions in 8085

Set Interrupt Mask (SIM) :

In 8085 Instruction set, SIM stands for “Set Interrupt Mask”. It is 1-Byte instruction and it is a
multi-purpose instruction.

The main uses of SIM instruction are –

• Masking/unmasking of RST7.5, RST6.5, and RST5.5

• Reset to 0 RST7.5 flip-flop.

• Perform serial output of data.

Read Interrupt Mask (RIM):
In 8085 Instruction set, RIM stands for “Read Interrupt Mask”. It is a 1-Byte multi-purpose instruction.

It is used for the following purposes –

• To check whether RST7.5, RST6.5, and RST5.5 are masked or not.

• To check whether interrupts are enabled or not.

• To check whether RST7.5, RST6.5, or RST5.5 interrupts are pending or not.

• To perform serial input of data.

 Programmable Interrupt Controller (8259)

8259 microprocessor is defined as Programmable Interrupt Controller (PIC) microprocessor. There

are 5 hardware interrupts and 2 hardware interrupts in 8085 and 8086 respectively. But by connecting
8259 with CPU, we can increase the interrupt handling capability. 8259 combines the multi interrupt
input sources into a single interrupt output. Interfacing of single PIC provides 8 interrupts inputs from
IR0-IR7.
For example, Interfacing of 8085 and 8259 increases the interrupt handling capability of 8085
microprocessor from 5 to 8 interrupt levels.
Features of 8259 PIC microprocessor –
1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered interrupt level.
3. We can masked individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by cascading further
8259 PIC.
5. Clock cycle is not required.

Pin Diagram of 8259 –

We can see through above diagram that there are total 28 pins in 8259 PIC microprocessor where
Vcc :5V Power supply and Gnd: ground. Other pins use are explained below.

Block Diagram of 8259 PIC microprocessor –

The Block Diagram consists of 8 blocks which are – Data Bus Buffer, Read/Write Logic, Cascade
Buffer Comparator, Control Logic, Priority Resolver and 3 registers- ISR, IRR, IMR.
1. Data bus buffer –
This Block is used as a mediator between 8259 and 8085/8086 microprocessor by acting
as a buffer. It takes the control word from the 8085 (let say) microprocessor and transfer it
to the control logic of 8259 microprocessor. Also, after selection of Interrupt by 8259
microprocessors, it transfers the opcode of the selected Interrupt and address of the
Interrupt service sub routine to the other connected microprocessor. The data bus buffer
consists of 8 bits represented as D0-D7 in the block diagram. Thus, shows that a
maximum of 8 bits data can be transferred at a time.
2. Read/Write logic –
This block works only when the value of pin CS is low (as this pin is active low). This block
is responsible for the flow of data depending upon the inputs of RD and WR. These two
pins are active low pins used for read and write operations.
3. Control logic –
It is the center of the microprocessor and controls the functioning of every block. It has pin
INTR which is connected with other microprocessor for taking interrupt request and pin
INT for giving the output. If 8259 is enabled, and the other microprocessor Interrupt flag is
high then this causes the value of the output INT pin high and in this way 8259 responds to
the request made by another microprocessor.
4. Interrupt request register (IRR) –
It stores all the interrupt level which are requesting for Interrupt services.
5. In-service register (ISR) –
It stores the interrupt level which are currently being executed.
6. Interrupt mask register (IMR) –
It stores the interrupt level which have to be masked by storing the masking bits of the
interrupt level.
7. Priority resolver –
It examines all the three registers and set the priority of interrupts and according to the
priority of the interrupts, interrupt with highest priority is set in ISR register. Also, it reset the
interrupt level which is already been serviced in IRR.
 8. Cascade buffer –
To increase the Interrupt handling capability, we can further cascade more number of pins
by using cascade buffer. So, during increment of interrupt capability, CSA lines are used to
control multiple interrupt structure.
SP/EN (Slave program/Enable buffer) pin is when set to high, works in master mode else in slave
mode. In Non-Buffered mode, SP/EN pin is used to specify whether 8259 work as master or slave and
in Buffered mode, SP/EN pin is used as an output to enable data bus.
DMA -DMA controller (8257)
DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest rate. It
allows the device to transfer the data directly to/from memory without any interference of the CPU.
Using a DMA controller, the device requests the CPU to hold its data, address and control bus, so the
device is free to transfer data directly to/from the memory. The DMA data transfer is initiated only after
receiving HLDA signal from the CPU.

How DMA Operations are Performed?

Following is the sequence of operations performed by a DMA −

• Initially, when any device has to send data between the device and the memory, the
device has to send DMA request (DRQ) to DMA controller.
• The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert
the HLDA.
• Then the microprocessor tri-states all the data bus, address bus, and control bus. The
CPU leaves the control over bus and acknowledges the HOLD request through HLDA
signal.
• Now the CPU is in HOLD state and the DMA controller has to manage the operations over
buses between the CPU, memory, and I/O devices.

Features of 8257

Here is a list of some of the prominent features of 8257 −

• It has four channels which can be used over four I/O devices.
• Each channel has 16-bit address and 14-bit counter.
• Each channel can transfer data up to 64kb.
• Each channel can be programmed independently.
• Each channel can perform read transfer, write transfer and verify transfer operations.
• It generates MARK signal to the peripheral device that 128 bytes have been transferred.
• It requires a single-phase clock.
• Its frequency ranges from 250Hz to 3MHz.
• It operates in 2 modes, i.e., Master mode and Slave mode.

8257 Pin Description

The following image shows the pin diagram of a 8257 DMA controller −
DRQ0−DRQ3
These are the four individual channel DMA request inputs, which are used by the peripheral devices for
using DMA services. When the fixed priority mode is selected, then DRQ0 has the highest priority and
DRQ3 has the lowest priority among them.
DACKo − DACK3
These are the active-low DMA acknowledge lines, which updates the requesting peripheral about the
status of their request by the CPU. These lines can also act as strobe lines for the requesting devices.
Do − D7
These are bidirectional, data lines which are used to interface the system bus with the internal data bus
of DMA controller. In the Slave mode, it carries command words to 8257 and status word from 8257. In
the master mode, these lines are used to send higher byte of the generated address to the latch. This
address is further latched using ADSTB signal.
IOR
It is an active-low bidirectional tri-state input line, which is used by the CPU to read internal registers of
8257 in the Slave mode. In the master mode, it is used to read data from the peripheral devices during a
memory write cycle.
IOW
It is an active low bi-direction tri-state line, which is used to load the contents of the data bus to the 8-bit
mode register or upper/lower byte of a 16-bit DMA address register or terminal count register. In the
master mode, it is used to load the data to the peripheral devices during DMA memory read cycle.
CLK
It is a clock frequency signal which is required for the internal operation of 8257.
RESET
This signal is used to RESET the DMA controller by disabling all the DMA channels.
Ao - A3
These are the four least significant address lines. In the slave mode, they act as an input, which selects
one of the registers to be read or written. In the master mode, they are the four least significant memory
address output lines generated by 8257.
CS
It is an active-low chip select line. In the Slave mode, it enables the read/write operations to/from 8257.
In the master mode, it disables the read/write operations to/from 8257.
A4 - A7
These are the higher nibble of the lower byte address generated by DMA in the master mode.
READY
It is an active-high asynchronous input signal, which makes DMA ready by inserting wait states.
HRQ
This signal is used to receive the hold request signal from the output device. In the slave mode, it is
connected with a DRQ input line 8257. In Master mode, it is connected with HOLD input of the CPU.
HLDA
It is the hold acknowledgement signal which indicates the DMA controller that the bus has been
granted to the requesting peripheral by the CPU when it is set to 1.
MEMR
It is the low memory read signal, which is used to read the data from the addressed memory locations
during DMA read cycles.
MEMW
It is the active-low three state signal which is used to write the data to the addressed memory location
during DMA write operation.
ADST
This signal is used to convert the higher byte of the memory address generated by the DMA controller
into the latches.
AEN
This signal is used to disable the address bus/data bus.
TC
It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present peripheral devices.
MARK
The mark will be activated after each 128 cycles or integral multiples of it from the beginning. It
indicates the current DMA cycle is the 128th cycle since the previous MARK output to the selected
peripheral device.
Vcc
It is the power signal which is required for the operation of the circuit.
INTERNAL ARCHITECTURE OF 8257:

The functional Block Diagram of DMA controller(8257) is shown in Figure 3.8.2 and thedescription are
as follows: It consists of five functional blocks:

a) Data bus buffer

b) Control logic

c) Read/write logic

d) Priority Resolver

e) DMA channels

Figure 3.8.2 Functional Block Diagram of 8257

Data Bus Buffer:

8- bit Tristate, bidirectional buffer interfaces the internal bus of 8257 withthe
external system bus under the control of various control signals.

Read/Write Logic:

In the slave mode, the read/write logic accepts the I/O Read or I/O Write signals,
decodes the Ao-A3 lines and either writes the contents of the data bus to theaddressed internal
register or reads the selected register depending upon whether IOW or IOR signal is
activated.In master mode, the read/write logic generates the IOR and IOW signals to control
the dataflow to or from the selected peripheral.

Control Logic:

The control logic controls the sequences of operations and generates the required control
signals like AEN, ADSTB, MEMR, MEMW, TC and MARK along with the address lines A4-A7, in
master mode.

Priority Resolver:

The priority resolver resolves the priority of the four DMA channels depending upon
whether normal priority or rotating priority is programmed.

Register Organization of 8257:

The 8257 performs DMA operation over four independent DMA channels with thefollowing
Registers.

1. DMA Address Register

Each DMA channel has one DMA address register. The function of this register isto store the
address of the starting memory location, which will be accessed by the DMA channel. The
device that wants to transfer data over a DMA channel, will access the block of the memory
with the starting addressstored in the DMA Address

Register.
 2. Terminal Count Registers

Each of the four DMA channels of 8257 has one terminal count register (TC).This 16-bit
registers used for ascertaining that the data transfer through a DMA channel ceases or stops
after the required number of DMA cycles.
After each DMA cycle, the terminal count register content will be decremented by
one and finally it becomes zero after the required number of DMA cycles are over. The
bits 14 and 15 of this register indicate the type of theDMA operation (transfer).

3. Mode Set Register

The mode set register is used for programming the 8257 as per the requirements of the
system. The function of the mode set register is to enable the DMA channels individually and
also to set the various modes of operation as shown in Figure 3.8.3.

Figure 3.8.3 Mode Set Register

The bits Do-D3 enable one of the four DMA channels of 8257.If the TC STOP bit is set, the
selected channel is disabled after the terminal count condition is reached, and it further prevents
any DMA cycle on the channel. If the TC STOP bit is programmed to be

zero, the channel is not disabled, even after the count reaches zero and further request areallowed
on the same channel. The auto load bit, if set, enables channel 2 for the repeat block chaining
operations, without immediate software intervention between the two successive blocks. The
extended write bit, if set to ‘1’, extends the duration of MEMW and IOW signals by activating them
earlier, which is useful in interfacing the peripheralswith different access times.
4. Status register

The lower order 4-bits of this register contain the terminal count status for the fourindividual
channels. If any of these bits is set, it indicates that the specific channel hasreached the terminal
count condition. The update flag is not affected by the read operation. This flag can only be
cleared by resetting 8257. The update flag is set everytime, the channel 2 registers are loaded
with contents of the channel 3 registers. It is cleared by the completion of the first DMA cycle of
the new block. This register canonly read.

DMA TRANSFER & OPERATIONS

The 8257 is able to accomplish three types of operations such

as

1. DMA operation
2. Write Operation
3. Read Operation

Operational sequence of 8257 is as follows

o The 8257 request any one of the 8257 DRQ inputs to transfer single byte.
o In response to the request, the 8257 sends HRQ signal to CPU at its HLDinput
and waits for acknowledgement at the HLDA input.

o If the DMA controller receives the HLDA signal it indicates that the bus isavailable for
the transfer.

o The DMA controller generate the read and write commands to transfer the

byte from/to the I/O Device.

o The DACK line of the used channel is pulled down by the DMA controllerto I/O device
that requested for DMA transfers.

o The HRQ line is lowered by the DMA controller to indicate the CPU that it may regain
 the control of the bus.

o The DRQ must be high until acknowledged.

o In each s4 state ,the DRQ lines are sampled and highest priority request is recognized
during next transfer. The HRQ line is maintained active till all the DRQ line go low.