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DLD Notes Summary Digital Logic Design

DLD

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10 views17 pages

DLD Notes Summary Digital Logic Design

DLD

Uploaded by

hungl5846
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DLD notes - Summary Digital Logic Design

Digital Logic Design (Trường Đại học Quốc tế, Đại học Quốc gia Thành phố Hồ Chí
Minh)

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Lec7 : Sequential logic circuit


Sequential logic circuit:
- Synchronous sequential circuits
- Asynchronous sequential circuits
• Latch Active High and Latch Active Low

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• Clocked S-C Flip-Flop

• Clocked J-K Flip-Flop and Asynchronous J-K Flip Flop

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• D Latch and Clocked D Flip-Flop

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• T-Flip Flop

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Lec8 : Counters
The design processes of asynchronous counters:
MOD-4

MOD-8

MOD-16

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MOD-10

MOD-12

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Nếu đề yc vẽ truth table thì vẽ bảng này, ko thì vẽ bảng này ở nháp (để suy ra mạch chỗ
NAND):
CLK QA QB QC QD CLR
0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 1
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 1
6 0 1 1 0 1
7 0 1 1 1 1
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 1
11 1 0 1 1 1
12 1 1 0 0 0
0 0 0 0 0

QA QB CLR
0 0 1
0 1 1
1 0 1
1 1 0
➔ CLR = (QA . QB)’

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Asynchronous Down Counter

15-10

7-2

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IC Asynchronous Counters

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Synchronous Down and Up/Down Counter

Step 3

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Lec9 : IC Counter and Register


❑ Analysis and description for the operation of IC counters such as presettable and
74193 counters (MOD-16).
Lec10 : IC Counter and Register(cont)
• Basic Shift Register Functions

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SISO:

PISO (4 bits) :

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SIPO: series in parallel out

PIPO: parallel in parallel out

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• Bidirectional Shift Registers


̅̅̅̅̅̅̅control = 1 thì shift right
𝑅𝐼𝐺𝐻𝑇/𝐿𝐸𝐹𝑇
= 0 thì shift left

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• Shift Register Counters: Ring Counter & Johnson’s Counter


▪ Ring Counter: Circuit diagram and Design

15

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▪ Johnson’s Counter: Circuit diagram and Design

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