O1, For the circuit shown in Fig, the Boolean jon for the output Y in terms of inputs P, (Transeo-12) expres Q, Rand Sis P=D-L_, soe OP 1b: ee se C (a) P+O+R+5 © (P+5)(R+3) (b) PHQER+S (@ (P+Q) (RES) 02. The gate whose output is high when all the » inputs are low and low for other combinations of we oo ¢ inputsis (EPDCL-14) ©) 0 (@)ORgate (b) AND gate 1 © © ()NAND gate (@ NOR gate ua 03. Identify the 1-bit comparator circuit (APSPDCL-14) ® => 9 =D- => fa @> 04. Annetwork has the given truth table. fis given by (APSPDCL-14) © (x1, X2) 1 xi [X -|-[Jo) Bale hal 1 0 1 (a) x) +%2 +% () ¥, +¥, +x,x; (© tX% (@) x,X,+%x, [| AX Séine Tndia’s Best Online Coaching Pi Enjoy a smooth online er system & Coding Conversion nown below is equivalent of Na CAPSPDCL (05. The circuit sh 06, In 2's complement representation, the number | 11100101 represents the decimal number (HMWS-15, (b)-31 (a) +37 (a) -27 (0) #27 07. Binary subtraction of a decimal 15 from 43 wil utilize which two's complement? (HMWS-18) (a) 011100 (b) 110000 (©) 110001 (@ 101011 08. The reduced form of the Boolean expressions [B+C(ABTAC)]is crsGeneo¥9 (@) AB (b) AB (AB (@ AB+ BC 09. The minimum number of 2-input NAND # required to implement the Boolean futon” i ABYC, assuming that A,B and C are wi (rsGenet storm for GATE, ESE, PSUs, SSCJE, SSC, Banks, ae) ‘learning experience iy "ESTEE avis languages at your commen ad (& scanned with OKEN Scanner(b) three (© five ) six (a) 000 (iit ©1901 (10 ‘The Boolean expression Y(A,B,¢) = od uci A+ BC i to be realized using 2.; wb : input gates of only ong type, What is the minimum momber of gates required for the realization? ) 16, Aces F According to Boolean algebra and switching functions, Match the following: (TSTranseo-18) ee, @l ()2 Expression 3 @) 4 ormore A) (K+ HR). (x +H) + y) 11, What is the Gray code word for the binary © Conley) number 101011? (TSTransco-15) 0x2) + Gy)+ oe (@) 101011 () 110101 () R42) +2+2y we (oui (@) 111110 Simplification/Result mi 12, Which of the following gates can be used to (™y realize all possible combination logic functions? wo (TSSPDCL-15) fa ) (O)x+y+z+w ) (@)xty+z Gi) NOR gate (@)A-L;B-N;C-M;D-O (ii) Exclusive OR gate ()A-L:B-N;C_0;D-M (iv) NAND gate ()A-N;B-M;C-0;D-P (WAND gate (#) A-N; B-L;C-M;D-P (@) (iii), (iv) and (v) () (i), (iii) and (iv) (©) ii) and (iv) (d) (i) and (v) KEY and Detailed Solutions 13. Hexa decimal equivalent value of decimal || 1.) | 02@ | 03.@) | 04.() | 05.@ ee (1sTransco-18) 06. (a) | 07.(@) | 08.) | 09.) | 10.) (782.28 (b) 2F5.40 i o 12. (©) 13. (b) 14. (a) | 15. (6) (©) 3E4.60 (4208 — \4. The function {(A,B,C) = AB+A.C in SoP | Ol. Ans: (b) form using minterms is___ (APEPDCL-19)_| Sol: oe (@) f= mp +m, +me +m rowed (b) £= mg + m, + mz +s = (©) f=my+m;+my + Yn. oW Ras, aa ee In two level logic 7 gray code equivalent of binary 101 is *NAND - NAND’ Logic = AND - OR’ Logic (APSPDCL-19) x ave Doubt eating Sessions | Free Online Test Series ASKanexpert Bl agar Live Doub ering 3 (& scanned with OKEN Scanner02. Ans: (a) Sot ATR] Omput ofofr | [TJo}o Ope This is for NOR gate 03. Ans: (a) Sol: X-OR gate is unequal comparator. 04. Ans: (¢) Sol: 1 f=%,+ ‘This equation satisfies option (c) Note: option (c) => X, +,x, (+x, X% +2) (&,+x;) X +x, =1] 0S. Ans: (4) Sok: 1 | 2 | flr, x2) 0 joi of fo 1 fo lo 1 [1 [o f= KX, =X +X, 06, Ans: (a) Sol: Given number is -> 11100101 (2's complement number). To get the decimal equivalent, again do 2's complement to given number, BX siiine on 2's complement of given . -@n “il (00011011)2 = (27)10 ‘As MSB is *1" in given no result =p, Shortcut: P1201 x2940%240x2 +1249, 01 Up HAHDHOAVOD +091, 2-27 07. Ans: (a) Sol: Short Cut: 43-15 = 28 «binary equivalent of (28)10= (011100), 08. Ans: (©) Sol: Given expression is [p+c{aB+Ac)] fp+o(a5)Ac] =A[B+C(A+B)(A+C)] = ap+O(4 +A B +A T+ BC] = A[B+C[AG+B+O)+BC]] = A[B+C(A+BC]] =AB 09. Ans: (c) Sol: Z=(AC) B (& scanned with OKEN Scanner| P Q im ing Seasons | Fre aloe Fest Series [ASK an expert See she ish on 126 ih nd Monts ‘ioral oe | Avaliable 1M a (& scanned with OKEN ScannerChapter of the clock signal applied 1° the p shown in Fig: is jlable at 01. The frequency rising edge triggered D fip-fo 10 Kitz, The frequency of the signal AV Qis (Transeo-32) JUL loz (@) 10 kHz (b) 2.5 kHz (©) 20 kHz (@ 5 kHz 02, A 3-stage ripple counter has Flipflop with propagation delay of 25 nsec and pulse width of strobe input 10 nsec, Then the maximum operating frequency at which counter operates reliably is (APGenco-12) (a)16.67 MHz, (b) 17.6 MHz (©) 12.67 MHz (@ 11.76 MHz 03. The initial state of MOD 16 counter is 0110, After 37 clock pulses, the state of the counter ane (aMws-12) (a) 1011 (b) 0110 (©0101 @ 0001 04, The number of unused states in a 4-bit Johnson counter is aaws.i5 (@) 12 (4 8 @2 05. Which of the following is not a characterise of of a flip-flop? caMWs.i5 DX i. ‘ [sie est Onin oa |_ 4 online (@) Ithas one input terminal (p) Ithas two outputs (@) It has two outputs which are ‘complemen each other It is a bistable device @ 96, A4 bit modulo-16 ripple counter uses 1K 1, flop Ifthe progression delay ofeach fp 50 ns, the maximum clock frequency that cen (TSGeneo-19) (b) 10 MHz (d) 4 MHz, used is equal to: (a) 20 MHz (@) 5 MHz 07, A 10-bit ADC with a full scale output voltage ot 10.24 V is designed to have +LSB/2 accuracy the ADC is calibrated at 25°C and the operaig temperature ranges from 0°C to 50°C. Then hi maximum net temperature coefficient of ADC should not exceed. (TSGeneo-!§) (a) 200nveC (b) + 400nV7°C (©) + 600nv?C (a) + 800HVC 08. The output f of the 4-to-1 MUX shown in fig: (rsTranseo! ie Lae > sax oir s TT ty Fig Oy xy Ory (@aytt (& scanned with OKEN ScannerI B, 1 switch til ting counter is made by using sale D-FF. The resulting circuit is (APtranseo-17) (THF (b) D-FF ()SRFF @JK-FF ‘he clock frequency of an 8-bit successive approximation type A to D converter is 2MHz, ‘The conversion time for an analog signal sample to be converted to digital equivalent value is (TSTransco-18) @2ns (©) Ins © 4ys (@) 16s, The present outputs of the flip-flops of a 3 bit synchronous down converter are 110. After 7 clock pulses the outputs change to (TSTransco-18) @10 (111 © 101 (@ 100 AT -flipflop function obtained from a JK- flipflop. If the flipflop belongs to a TTL family, the connection needed at the input must be (TSNPDCL-18) @ (b) J-K=0 (©J=1 and K=0 (d) J-0 and K=1 Number of 2-to -4 needed to implement a 4-to-6 decoder are (TSNPDCL-18) @s5 (b)4 ©16 @6 The present output Q, of an edge triggered JK flip~ flop is logic 0. If J =1, then Qnes will be (APtransco-19) (@) logic 0 (b) Race around (© Indeterminate (@ logic 1 [COOTER The minimum number of 2 to | multiplexers Tequired to realize an 8 to 1 Multiplexer is (APtransco-19) (a4 (3 7 (10 16. Full adder is constructed by using___- (APEPDCL-19) (a) one OR gate and one half adder (b) two half adders and one OR gate (©) two half adders and two OR gates (@ one half adders and two OR gates 17. In a 4-bit Johnson counter sequence, the total number of states are (APSPDCL-19) @1 (b)3 ©4 (@8 18. A Four flip-flop ripple counter is being operated at a clock frequency of 32 kHz. The frequency (kHz) of the waveform at the output of the MSB flip-flop is (MWS-20) (@2 (b)1 (4 @s 19. If an inverter is placed between the inputs of an S-R flip -flop, the resulting flip-flop is (HMWS-20) (@) Master Slave flip-flop (b) T flip-flop (©) D flip-flop (@) JK flip-flop KEY and Detailed Solutions qi TH) RO [Be [HO 1S 6.© | 07.@ | 86) | 0.@ | 10 7. | 122@ | 3-@ | 14@ [| 15-© 76) | 170 [8 @ | © Regular Live Doubt clearing “plfordable Fee | Available 3M [3M [6M [22M [18M and “Affordable Fee | Available 8 EO Sessions | Free Online Test Series | ASKan expert "24 Months Subscription Packages (& scanned with OKEN Scanner(ACE as 01. Ans: (a) Sol: D-FF characteristic equation is Q (t+1) =D But, from figure, D = Qi) Hence Q(t +1) =O(f) = ic., FF is in Toggle mode Hence output Freq = Sesitrequeney — LOKHE sate 2 02. Ans: (@) Sol: Given data: a= 25 nsec, tute = 10 nsec ony = Btps + tante (3 25 + 10) nsce eee = 11.76 Mite x CLK | Output 0 ‘O10 ry om_| 2 100 3 1001 i5 O01 16 o1i0 For every 16 clock cycles, the output is repeated 2 16*2=32 For 32™ clock cycle, output = 110 For 33" clock cycle, output = 0111 For 37" clock cycle, output = 191 Sol: 05. Sol: 06. Sol: 07. Sol: PX Sine ‘Ans: (©) ' No. of unused states in 44 — bit Johnson = Total no. of states — 10. of used states * 2x 4= 16-8=8 Ans: (a) A flip-flop is a bistable device, which ig jy two outputs which are complement of other. Ans: (c) For 4-bit modulus 16 ripple counter has 4 flip-flops whose propagation delay is 4r, Total propagation delay T=4 50.n sec= 200 n sec -- Maximum clock frequency — ©” sOOnsec ~ Ans: (a) 1/ Vv, Accuracy = + LSB/2 = 4—| Ves : LS] IP 10. — 23[ 92 ]-2sa0°v maximum net temperature = 25x10" 25°C coefficient at25°C =+200nv/°C (& scanned with OKEN Scannerttactas T-FF in Ans: (©) sat The conversion time of n-bit successive Approximate type A/D = Ty 1 For 8-bit conversion = 8 x: 2MHz =4us Ans: (b) Initial output of down counter = 110 IF clock - 101 2 clock — 100 3" clock - O11 4 clock-010 S* clock - 001 6 clock - 000 clock ~ 111 FF 12. Ans: (a) Sol: Conversion of J.K flip flop to T flip flop is Possible when J = K but generally used to 2004 T Decoder £ Hence we requires 5, 24 decoders to design 4 6 decoder 14. Ans: (@) Sol: Given Present output Q=0,J=1 I-K flip flop JK Q Qu 10.0.1 Tete Ol IK 10 Qui=1 JK 11 Out put will Toggle from truth output Quer is logic 1 15, Ans: (©) Sol: Minimum number of 2 to 1 multiplexer required to realize 8 to 1 multiplexer is, toggle the outputs. Hence JK =1. a0 2 Aan 2 cqane re Boab eating Sons | Fro nl Tet eles Aan eer 7 “ea ee | Hraahe i [so F2 HON and 4 Months Serinon Pacags (& scanned with OKEN Scanner‘Ans: (a) Sol: frequency at MSB 4241-7 16. Ans: () cm 19. Ans: (c) S sum Sol: a—J : F.F C-out BN Harare )> a I=Q@tl)>1=D 17. Ans: (4) i +. For D — Flip Sol: No. of Johnson counter states = 2n Qatl)=p =2x4 =8 states (& scanned with OKEN Scanner| canter) AD and DA Converters . o es ‘The number of comparators needed to build a 6- pitsimultaneous A/D converter (EPDCL-10) @8 7 6 @) 64 ‘The no. of comparators needed to build a 6-bit counter type A/D converter (EPDCL-10) @s (b) 32 6 @1 Which of the following is the fastest A/D converter (EPDCL-10) (@) counter type A/D (0) successive approximation (©) dual slope (@ integrating type What is the maximum output voltage of 8-bit DIA converter with 10V supply (EPDCL-10) (2) 9.961V (6) 9.691 V (tov @sv The number of comparisons carried out in a 3- bit. flash-type A/D converter is (Transco-AE-12) (@) 16 @)7 4 @3 The percent resolution of an 8-bit D/A converter - (APGenco-12) (@) 0.392 (b) 1/256 (©) Wass (d) (a) and (b) both oats Berta joyasmooth online WL —ainb Coaching Platform for GATE ESE, PSUs, SSCE SSG, ine eaigexpertnce fn various langwnes your eomvénlepee 07. 08. 10. 12, Identify the logic gate family which consumes maximum power and which has minimum propagation delay. (HMWS-12) (a) Mos (b) TTL (ECL (@ cMos Which of the following is a D/A converter? (EPDCL-14) (@) Flash converter (b) Weighted resistor (©) Successive approximation (@) Dual slope The ADC having highest conversion speed is (APSPDCL-14) (a) Dual-slope ADC (b) Successive approximation ADC (©) Flash ADC (d) Servo ADC ‘The memory which needs refreshing (APSPDCL-14) (a) ROM (>) EPROM (©) SRAM (@ DRAM The number of comparators required in a 3-bit comparator type ADC is. (HMWS-15) @8 ()3 @7 @2 Ina flash A/D converter, the priority encoder is used to (HMWS-15) (a) Select the last input (b) Select the highest value input (6) Select the lowest value input (@ Select the first input ape & PSC Exams (& scanned with OKEN Scanner14, 1s. 16. 17. 18, [Prete] A 4-bit R/2R ladder digital-to-analog converter uses (uMWS-15) (8) Four resistor values (b) Three resistor values (©) Five resistor values (@) Two resistor values The main advantage of the successive- approximation A/D converter over the counter ~ Tamp A/D converter is its (aMws-15) (@) Shorter conversion time (©) Less complex circuitry (©) Longer conversion time (@ More complex circuitry The practical use of binary-weighted digital-to- analog converters is limited to. (HMWS-15) (a) Op-amp comparators (b) 4-bit D/A converters (©) 8-it D/A converters (@) RR ladder D/A converters A digit voltmeter has 4% digit display. The 1 V range can read upto (TSTransco-15) (a) 1000 (b) 1. (©) 1.999 (d) 1999 For the T flip-flop Qua is given by ee (APSPDCL-14) @ TQ, +TQ, ) TQ, +Q, ©T @ TQ, The number of comparators required in a 4 bit comparator type ADC is (APTransco-17) (a) 16 (b) 15 (17 @nr 20. au. 2. 23. 24, resistor value corresponding to LSB ig og and the resislor value corresponding yy M will be (APrraneiy (a) 0.4 kQ (b) 3k ()28k2 (#)25ka ‘The number of comparators requted to dj 4-bit flash ADC is CTssppcr iy (a)2 (b)4 7 @Is An 8 bit D/A converter has a full scale voltage of 20V. What is the output vole when the input is 11011011 (TSNPDCLig (@) 160mv (b) 78mv (@20v @iWv ‘The minimum number of comparators used in; aa N-bit Successive approximation ADC is___ (APEPDCL -19) @l @)N-1 N+ (@2N A 6-bit DAC produces Vo = 0.25 V fora inp ode of 000001. Vo for the input code 1111018 — (APEPDCL-19) | @sv (b)25V (©)30.50,V @ 15.25V Small timing errors in ADC additional os ate called ag (apsppcl9) (8) Flicker (b) Aliasing (©) Jitter @ Shot noise (& scanned with OKEN ScannereB pace is conversion time of a 12 bit counter type ADC with 1 MHz clock frequency to convert a fille scale input is (APSPDCL-19) (0) 4.095 s (b) 4.095 ms (6) 4.095 ps (@) 2.048 ms KEY and Detailed Solutions 02.4) | 03.(b) ] 04. (a) | 05. (by 7. | 8.0) | 9. 10a 2.0) | 3.@ | 14@ | 15.0) 17-@)_ | 18.) | 19.@ | 20.@ 2.@) | 22@ | 23.@) | 24) | 25.0) i, Ans: (a) Sal: The number of comparators needed to build a 6- bit simultaneous A/D converter = 2-1 ©. Ans: (4) Sol: The no. of comparators needed to build a 6-bit counter type A/D converter=1. B Ans: (b) Sol: Speed: Flash type > Successive approximation > counter type > dual slope/integrating type A/D. 4. Ans: (a) Sol: Given data: n = 8, Vip= 10V Vewoasy = Resolution * (Decimal equivalent of ‘max binary number) For an 8 bit D/A converter max count value = 2 = 256 10 255 =9.961 V 6 05, Sol: So 2? — 1 = 7 comparators required. 06. Ans: (a) Sol: %Resolution = 0392 Ans: (6) Sol: 1). The order of propagation delay of logic families is ECL TTL > CMOS (high) (low) 08. Ans: (b) Sol: ‘A/D Converter D/A Converter Flash Type Successive | R—2R ladder approximation Ramp Type Tnverter R-2R ladder Counter Type Weighted resistor Dual slope Integrating on Be Screener form for GATE, ESE, PSUs, SSC-JE, SSC, Banks, Groups & PSC Exams (& scanned with OKEN Scanner09, Sol: 10. Sol: 1. Sol: 15. Sol: [Prin eI Ans: ion > Speed: Flash type > Successive approximation counter type > dual stopefintegeating type A/D- Ans: (a) * SRAM requires 6-transistors for storing one bit DRAM requires one capacitor and one electronic switch (BIT/FET) to store one bit. DRAM requires memory refreshing logic circuit to refresh all the capacitor voltages, whereas SRAM does not require memory refresh logic circuit since itis designed with transistors. Ans: (¢) The number of comparators required in a n-bit comparator type ADC is 2°-1. +. for 3-bit=2°-1 => 7 ‘Ans: (b) The priority encoder is used to select the highest value input. Ans: (d) ‘Weighted resistor D/A converters requires wide variety of resistors, but R/2R ladder type D/A converter requires two resistor values. Ans: (a) The main advantage of the successive — approximation A/D converter over the counter ~ ramp A/D converter is that it has shorter conversion time. Ans: (b) The practical use of binary-weighted digital-to- analog converters is limited to 4-bit D/A converters Regular Live Doubt lear ‘Affordable Fee | Avalla 1M] sol: For T flip-flop canoe TAD] 0 [a [QO T [QW | eH) ojo fo oft fa T[o | T{1 [0 Ot+)=TeOW =TO+TOW 18, Ans: (b) Sol: n=4 given ‘No. of comparator = 2" —1 19. Ans: (d) Sol: Rise = Rus x 2°! Given Rusa = 40 kO and n=5 Rao = WE 2540 16 20. Ans: (@) Sol: The number of comparators required to mbit flash AD For 4-bit = 24 21. Ans: (@) Sol: (11011011), | Sat 142) = (2 eat gncat gx? +h?” = [128+64+16+8+241] ig Sstons a | Free Gnline Test Series [ASK an ex? 1M 12M 16M and 24 Months Subscription? | (& scanned with OKEN Scanner| aa EE ene ree ee eee pace | -29 23, Ans: (a) cafall scale value = (HN) =2*=1 Sol: Given Vq = 0.25 for input code 000001 i.e., resolution Vo = 0.25 =285 219 9) For input code 4 11101 Vo= ? Vo* 955 = (3241648 +4404 1) x 0.25 = 17 volts =9 15.25 pans (@) 25. Ans: (b) i ts Sol: Conversion time of counter type ADC pe | | = QI) Xt Comparato Successive Ve Approximation |*—CLK jolt iP Register Vn | y* (MSB) pete fey Conversion time = (27-1) * 1ps = 4095 Ips = 4,095 ms orator CAT OE, PU a ene nvr nears eyourcnreince | (& scanned with OKEN Scanner